1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2020 Advanced Micro Devices, Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * Contact Information : 28 * Rajesh Kumar <rajesh1.kumar@amd.com> 29 * Shreyank Amartya <Shreyank.Amartya@amd.com> 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/kernel.h> 38 #include <sys/malloc.h> 39 #include <sys/module.h> 40 #include <sys/mutex.h> 41 #include <sys/rman.h> 42 #include <sys/socket.h> 43 #include <sys/sysctl.h> 44 #include <sys/systm.h> 45 46 #include <net/if.h> 47 #include <net/if_media.h> 48 49 #include <dev/mii/mii.h> 50 #include <dev/mii/miivar.h> 51 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcivar.h> 54 55 #include "xgbe.h" 56 #include "xgbe-common.h" 57 58 #include "miibus_if.h" 59 #include "ifdi_if.h" 60 #include "opt_inet.h" 61 #include "opt_inet6.h" 62 63 MALLOC_DEFINE(M_AXGBE, "axgbe", "axgbe data"); 64 65 extern struct if_txrx axgbe_txrx; 66 static int axgbe_sph_enable; 67 68 /* Function prototypes */ 69 static void *axgbe_register(device_t); 70 static int axgbe_if_attach_pre(if_ctx_t); 71 static int axgbe_if_attach_post(if_ctx_t); 72 static int axgbe_if_detach(if_ctx_t); 73 static void axgbe_if_stop(if_ctx_t); 74 static void axgbe_if_init(if_ctx_t); 75 76 /* Queue related routines */ 77 static int axgbe_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int); 78 static int axgbe_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int); 79 static int axgbe_alloc_channels(if_ctx_t); 80 static void axgbe_if_queues_free(if_ctx_t); 81 static int axgbe_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 82 static int axgbe_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 83 84 /* Interrupt related routines */ 85 static void axgbe_if_disable_intr(if_ctx_t); 86 static void axgbe_if_enable_intr(if_ctx_t); 87 static int axgbe_if_msix_intr_assign(if_ctx_t, int); 88 static void xgbe_free_intr(struct xgbe_prv_data *, struct resource *, void *, int); 89 90 /* Init and Iflib routines */ 91 static void axgbe_pci_init(struct xgbe_prv_data *); 92 static void axgbe_pci_stop(if_ctx_t); 93 static void xgbe_disable_rx_tx_int(struct xgbe_prv_data *, struct xgbe_channel *); 94 static void xgbe_disable_rx_tx_ints(struct xgbe_prv_data *); 95 static int axgbe_if_mtu_set(if_ctx_t, uint32_t); 96 static void axgbe_if_update_admin_status(if_ctx_t); 97 static void axgbe_if_media_status(if_ctx_t, struct ifmediareq *); 98 static int axgbe_if_media_change(if_ctx_t); 99 static int axgbe_if_promisc_set(if_ctx_t, int); 100 static uint64_t axgbe_if_get_counter(if_ctx_t, ift_counter); 101 static void axgbe_if_vlan_register(if_ctx_t, uint16_t); 102 static void axgbe_if_vlan_unregister(if_ctx_t, uint16_t); 103 #if __FreeBSD_version >= 1300000 104 static bool axgbe_if_needs_restart(if_ctx_t, enum iflib_restart_event); 105 #endif 106 static void axgbe_set_counts(if_ctx_t); 107 static void axgbe_init_iflib_softc_ctx(struct axgbe_if_softc *); 108 109 /* MII interface registered functions */ 110 static int axgbe_miibus_readreg(device_t, int, int); 111 static int axgbe_miibus_writereg(device_t, int, int, int); 112 static void axgbe_miibus_statchg(device_t); 113 114 /* ISR routines */ 115 static int axgbe_dev_isr(void *); 116 static void axgbe_ecc_isr(void *); 117 static void axgbe_i2c_isr(void *); 118 static void axgbe_an_isr(void *); 119 static int axgbe_msix_que(void *); 120 121 /* Timer routines */ 122 static void xgbe_service(void *, int); 123 static void xgbe_service_timer(void *); 124 static void xgbe_init_timers(struct xgbe_prv_data *); 125 static void xgbe_stop_timers(struct xgbe_prv_data *); 126 127 /* Dump routines */ 128 static void xgbe_dump_prop_registers(struct xgbe_prv_data *); 129 130 /* 131 * Allocate only for MAC (BAR0) and PCS (BAR1) registers, and just point the 132 * MSI-X table bar (BAR5) to iflib. iflib will do the allocation for MSI-X 133 * table. 134 */ 135 static struct resource_spec axgbe_pci_mac_spec[] = { 136 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, /* MAC regs */ 137 { SYS_RES_MEMORY, PCIR_BAR(1), RF_ACTIVE }, /* PCS regs */ 138 { -1, 0 } 139 }; 140 141 static pci_vendor_info_t axgbe_vendor_info_array[] = 142 { 143 PVID(0x1022, 0x1458, "AMD 10 Gigabit Ethernet Driver"), 144 PVID(0x1022, 0x1459, "AMD 10 Gigabit Ethernet Driver"), 145 PVID_END 146 }; 147 148 static struct xgbe_version_data xgbe_v2a = { 149 .init_function_ptrs_phy_impl = xgbe_init_function_ptrs_phy_v2, 150 .xpcs_access = XGBE_XPCS_ACCESS_V2, 151 .mmc_64bit = 1, 152 .tx_max_fifo_size = 229376, 153 .rx_max_fifo_size = 229376, 154 .tx_tstamp_workaround = 1, 155 .ecc_support = 1, 156 .i2c_support = 1, 157 .irq_reissue_support = 1, 158 .tx_desc_prefetch = 5, 159 .rx_desc_prefetch = 5, 160 .an_cdr_workaround = 1, 161 }; 162 163 static struct xgbe_version_data xgbe_v2b = { 164 .init_function_ptrs_phy_impl = xgbe_init_function_ptrs_phy_v2, 165 .xpcs_access = XGBE_XPCS_ACCESS_V2, 166 .mmc_64bit = 1, 167 .tx_max_fifo_size = 65536, 168 .rx_max_fifo_size = 65536, 169 .tx_tstamp_workaround = 1, 170 .ecc_support = 1, 171 .i2c_support = 1, 172 .irq_reissue_support = 1, 173 .tx_desc_prefetch = 5, 174 .rx_desc_prefetch = 5, 175 .an_cdr_workaround = 1, 176 }; 177 178 /* Device Interface */ 179 static device_method_t ax_methods[] = { 180 DEVMETHOD(device_register, axgbe_register), 181 DEVMETHOD(device_probe, iflib_device_probe), 182 DEVMETHOD(device_attach, iflib_device_attach), 183 DEVMETHOD(device_detach, iflib_device_detach), 184 185 /* MII interface */ 186 DEVMETHOD(miibus_readreg, axgbe_miibus_readreg), 187 DEVMETHOD(miibus_writereg, axgbe_miibus_writereg), 188 DEVMETHOD(miibus_statchg, axgbe_miibus_statchg), 189 190 DEVMETHOD_END 191 }; 192 193 static driver_t ax_driver = { 194 "ax", ax_methods, sizeof(struct axgbe_if_softc), 195 }; 196 197 devclass_t ax_devclass; 198 DRIVER_MODULE(axp, pci, ax_driver, ax_devclass, 0, 0); 199 DRIVER_MODULE(miibus, ax, miibus_driver, miibus_devclass, 0, 0); 200 IFLIB_PNP_INFO(pci, ax_driver, axgbe_vendor_info_array); 201 202 MODULE_DEPEND(ax, pci, 1, 1, 1); 203 MODULE_DEPEND(ax, ether, 1, 1, 1); 204 MODULE_DEPEND(ax, iflib, 1, 1, 1); 205 MODULE_DEPEND(ax, miibus, 1, 1, 1); 206 207 /* Iflib Interface */ 208 static device_method_t axgbe_if_methods[] = { 209 DEVMETHOD(ifdi_attach_pre, axgbe_if_attach_pre), 210 DEVMETHOD(ifdi_attach_post, axgbe_if_attach_post), 211 DEVMETHOD(ifdi_detach, axgbe_if_detach), 212 DEVMETHOD(ifdi_init, axgbe_if_init), 213 DEVMETHOD(ifdi_stop, axgbe_if_stop), 214 DEVMETHOD(ifdi_msix_intr_assign, axgbe_if_msix_intr_assign), 215 DEVMETHOD(ifdi_intr_enable, axgbe_if_enable_intr), 216 DEVMETHOD(ifdi_intr_disable, axgbe_if_disable_intr), 217 DEVMETHOD(ifdi_tx_queue_intr_enable, axgbe_if_tx_queue_intr_enable), 218 DEVMETHOD(ifdi_rx_queue_intr_enable, axgbe_if_rx_queue_intr_enable), 219 DEVMETHOD(ifdi_tx_queues_alloc, axgbe_if_tx_queues_alloc), 220 DEVMETHOD(ifdi_rx_queues_alloc, axgbe_if_rx_queues_alloc), 221 DEVMETHOD(ifdi_queues_free, axgbe_if_queues_free), 222 DEVMETHOD(ifdi_update_admin_status, axgbe_if_update_admin_status), 223 DEVMETHOD(ifdi_mtu_set, axgbe_if_mtu_set), 224 DEVMETHOD(ifdi_media_status, axgbe_if_media_status), 225 DEVMETHOD(ifdi_media_change, axgbe_if_media_change), 226 DEVMETHOD(ifdi_promisc_set, axgbe_if_promisc_set), 227 DEVMETHOD(ifdi_get_counter, axgbe_if_get_counter), 228 DEVMETHOD(ifdi_vlan_register, axgbe_if_vlan_register), 229 DEVMETHOD(ifdi_vlan_unregister, axgbe_if_vlan_unregister), 230 #if __FreeBSD_version >= 1300000 231 DEVMETHOD(ifdi_needs_restart, axgbe_if_needs_restart), 232 #endif 233 DEVMETHOD_END 234 }; 235 236 static driver_t axgbe_if_driver = { 237 "axgbe_if", axgbe_if_methods, sizeof(struct axgbe_if_softc) 238 }; 239 240 /* Iflib Shared Context */ 241 static struct if_shared_ctx axgbe_sctx_init = { 242 .isc_magic = IFLIB_MAGIC, 243 .isc_driver = &axgbe_if_driver, 244 .isc_q_align = PAGE_SIZE, 245 .isc_tx_maxsize = XGBE_TSO_MAX_SIZE + sizeof(struct ether_vlan_header), 246 .isc_tx_maxsegsize = PAGE_SIZE, 247 .isc_tso_maxsize = XGBE_TSO_MAX_SIZE + sizeof(struct ether_vlan_header), 248 .isc_tso_maxsegsize = PAGE_SIZE, 249 .isc_rx_maxsize = MJUM9BYTES, 250 .isc_rx_maxsegsize = MJUM9BYTES, 251 .isc_rx_nsegments = 1, 252 .isc_admin_intrcnt = 4, 253 254 .isc_vendor_info = axgbe_vendor_info_array, 255 .isc_driver_version = XGBE_DRV_VERSION, 256 257 .isc_ntxd_min = {XGBE_TX_DESC_CNT_MIN}, 258 .isc_ntxd_default = {XGBE_TX_DESC_CNT_DEFAULT}, 259 .isc_ntxd_max = {XGBE_TX_DESC_CNT_MAX}, 260 261 .isc_ntxqs = 1, 262 .isc_flags = IFLIB_TSO_INIT_IP | IFLIB_NEED_SCRATCH | 263 IFLIB_NEED_ZERO_CSUM | IFLIB_NEED_ETHER_PAD, 264 }; 265 266 static void * 267 axgbe_register(device_t dev) 268 { 269 int axgbe_nfl; 270 int axgbe_nrxqs; 271 int error, i; 272 char *value = NULL; 273 274 value = kern_getenv("dev.ax.sph_enable"); 275 if (value) { 276 axgbe_sph_enable = strtol(value, NULL, 10); 277 freeenv(value); 278 } else { 279 /* 280 * No tunable found, generate one with default values 281 * Note: only a reboot will reveal the new kenv 282 */ 283 error = kern_setenv("dev.ax.sph_enable", "1"); 284 if (error) { 285 printf("Error setting tunable, using default driver values\n"); 286 } 287 axgbe_sph_enable = 1; 288 } 289 290 if (!axgbe_sph_enable) { 291 axgbe_nfl = 1; 292 axgbe_nrxqs = 1; 293 } else { 294 axgbe_nfl = 2; 295 axgbe_nrxqs = 2; 296 } 297 298 axgbe_sctx_init.isc_nfl = axgbe_nfl; 299 axgbe_sctx_init.isc_nrxqs = axgbe_nrxqs; 300 301 for (i = 0 ; i < axgbe_nrxqs ; i++) { 302 axgbe_sctx_init.isc_nrxd_min[i] = XGBE_RX_DESC_CNT_MIN; 303 axgbe_sctx_init.isc_nrxd_default[i] = XGBE_RX_DESC_CNT_DEFAULT; 304 axgbe_sctx_init.isc_nrxd_max[i] = XGBE_RX_DESC_CNT_MAX; 305 } 306 307 return (&axgbe_sctx_init); 308 } 309 310 /* MII Interface Functions */ 311 static int 312 axgbe_miibus_readreg(device_t dev, int phy, int reg) 313 { 314 struct axgbe_if_softc *sc = iflib_get_softc(device_get_softc(dev)); 315 struct xgbe_prv_data *pdata = &sc->pdata; 316 int val; 317 318 axgbe_printf(3, "%s: phy %d reg %d\n", __func__, phy, reg); 319 320 val = xgbe_phy_mii_read(pdata, phy, reg); 321 322 axgbe_printf(2, "%s: val 0x%x\n", __func__, val); 323 return (val & 0xFFFF); 324 } 325 326 static int 327 axgbe_miibus_writereg(device_t dev, int phy, int reg, int val) 328 { 329 struct axgbe_if_softc *sc = iflib_get_softc(device_get_softc(dev)); 330 struct xgbe_prv_data *pdata = &sc->pdata; 331 332 axgbe_printf(3, "%s: phy %d reg %d val 0x%x\n", __func__, phy, reg, val); 333 334 xgbe_phy_mii_write(pdata, phy, reg, val); 335 336 return(0); 337 } 338 339 static void 340 axgbe_miibus_statchg(device_t dev) 341 { 342 struct axgbe_if_softc *sc = iflib_get_softc(device_get_softc(dev)); 343 struct xgbe_prv_data *pdata = &sc->pdata; 344 struct mii_data *mii = device_get_softc(pdata->axgbe_miibus); 345 struct ifnet *ifp = pdata->netdev; 346 int bmsr; 347 348 axgbe_printf(2, "%s: Link %d/%d\n", __func__, pdata->phy.link, 349 pdata->phy_link); 350 351 if (mii == NULL || ifp == NULL || 352 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 353 return; 354 355 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 356 (IFM_ACTIVE | IFM_AVALID)) { 357 358 switch (IFM_SUBTYPE(mii->mii_media_active)) { 359 case IFM_10_T: 360 case IFM_100_TX: 361 pdata->phy.link = 1; 362 break; 363 case IFM_1000_T: 364 case IFM_1000_SX: 365 case IFM_2500_SX: 366 pdata->phy.link = 1; 367 break; 368 default: 369 pdata->phy.link = 0; 370 break; 371 } 372 } else 373 pdata->phy_link = 0; 374 375 bmsr = axgbe_miibus_readreg(pdata->dev, pdata->mdio_addr, MII_BMSR); 376 if (bmsr & BMSR_ANEG) { 377 378 axgbe_printf(2, "%s: Autoneg Done\n", __func__); 379 380 /* Raise AN Interrupt */ 381 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 382 XGBE_AN_CL73_INT_MASK); 383 } 384 } 385 386 static int 387 axgbe_if_attach_pre(if_ctx_t ctx) 388 { 389 struct axgbe_if_softc *sc; 390 struct xgbe_prv_data *pdata; 391 struct resource *mac_res[2]; 392 if_softc_ctx_t scctx; 393 if_shared_ctx_t sctx; 394 device_t dev; 395 unsigned int ma_lo, ma_hi; 396 unsigned int reg; 397 398 sc = iflib_get_softc(ctx); 399 sc->pdata.dev = dev = iflib_get_dev(ctx); 400 sc->sctx = sctx = iflib_get_sctx(ctx); 401 sc->scctx = scctx = iflib_get_softc_ctx(ctx); 402 sc->media = iflib_get_media(ctx); 403 sc->ctx = ctx; 404 sc->link_status = LINK_STATE_DOWN; 405 pdata = &sc->pdata; 406 pdata->netdev = iflib_get_ifp(ctx); 407 408 spin_lock_init(&pdata->xpcs_lock); 409 410 /* Initialize locks */ 411 mtx_init(&pdata->rss_mutex, "xgbe rss mutex lock", NULL, MTX_DEF); 412 mtx_init(&pdata->mdio_mutex, "xgbe MDIO mutex lock", NULL, MTX_SPIN); 413 414 /* Allocate VLAN bitmap */ 415 pdata->active_vlans = bit_alloc(VLAN_NVID, M_AXGBE, M_WAITOK|M_ZERO); 416 pdata->num_active_vlans = 0; 417 418 /* Get the version data */ 419 DBGPR("%s: Device ID: 0x%x\n", __func__, pci_get_device(dev)); 420 if (pci_get_device(dev) == 0x1458) 421 sc->pdata.vdata = &xgbe_v2a; 422 else if (pci_get_device(dev) == 0x1459) 423 sc->pdata.vdata = &xgbe_v2b; 424 425 /* PCI setup */ 426 if (bus_alloc_resources(dev, axgbe_pci_mac_spec, mac_res)) 427 return (ENXIO); 428 429 sc->pdata.xgmac_res = mac_res[0]; 430 sc->pdata.xpcs_res = mac_res[1]; 431 432 /* Set the PCS indirect addressing definition registers*/ 433 pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF; 434 pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT; 435 436 /* Configure the PCS indirect addressing support */ 437 reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg); 438 pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET); 439 pdata->xpcs_window <<= 6; 440 pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE); 441 pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7); 442 pdata->xpcs_window_mask = pdata->xpcs_window_size - 1; 443 DBGPR("xpcs window def : %#010x\n", 444 pdata->xpcs_window_def_reg); 445 DBGPR("xpcs window sel : %#010x\n", 446 pdata->xpcs_window_sel_reg); 447 DBGPR("xpcs window : %#010x\n", 448 pdata->xpcs_window); 449 DBGPR("xpcs window size : %#010x\n", 450 pdata->xpcs_window_size); 451 DBGPR("xpcs window mask : %#010x\n", 452 pdata->xpcs_window_mask); 453 454 /* Enable all interrupts in the hardware */ 455 XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff); 456 457 /* Retrieve the MAC address */ 458 ma_lo = XP_IOREAD(pdata, XP_MAC_ADDR_LO); 459 ma_hi = XP_IOREAD(pdata, XP_MAC_ADDR_HI); 460 pdata->mac_addr[0] = ma_lo & 0xff; 461 pdata->mac_addr[1] = (ma_lo >> 8) & 0xff; 462 pdata->mac_addr[2] = (ma_lo >>16) & 0xff; 463 pdata->mac_addr[3] = (ma_lo >> 24) & 0xff; 464 pdata->mac_addr[4] = ma_hi & 0xff; 465 pdata->mac_addr[5] = (ma_hi >> 8) & 0xff; 466 if (!XP_GET_BITS(ma_hi, XP_MAC_ADDR_HI, VALID)) { 467 axgbe_error("Invalid mac address\n"); 468 return (EINVAL); 469 } 470 iflib_set_mac(ctx, pdata->mac_addr); 471 472 /* Clock settings */ 473 pdata->sysclk_rate = XGBE_V2_DMA_CLOCK_FREQ; 474 pdata->ptpclk_rate = XGBE_V2_PTP_CLOCK_FREQ; 475 476 /* Set the DMA coherency values */ 477 pdata->coherent = 1; 478 pdata->arcr = XGBE_DMA_PCI_ARCR; 479 pdata->awcr = XGBE_DMA_PCI_AWCR; 480 pdata->awarcr = XGBE_DMA_PCI_AWARCR; 481 482 /* Read the port property registers */ 483 pdata->pp0 = XP_IOREAD(pdata, XP_PROP_0); 484 pdata->pp1 = XP_IOREAD(pdata, XP_PROP_1); 485 pdata->pp2 = XP_IOREAD(pdata, XP_PROP_2); 486 pdata->pp3 = XP_IOREAD(pdata, XP_PROP_3); 487 pdata->pp4 = XP_IOREAD(pdata, XP_PROP_4); 488 DBGPR("port property 0 = %#010x\n", pdata->pp0); 489 DBGPR("port property 1 = %#010x\n", pdata->pp1); 490 DBGPR("port property 2 = %#010x\n", pdata->pp2); 491 DBGPR("port property 3 = %#010x\n", pdata->pp3); 492 DBGPR("port property 4 = %#010x\n", pdata->pp4); 493 494 /* Set the maximum channels and queues */ 495 pdata->tx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1, 496 MAX_TX_DMA); 497 pdata->rx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1, 498 MAX_RX_DMA); 499 pdata->tx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1, 500 MAX_TX_QUEUES); 501 pdata->rx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1, 502 MAX_RX_QUEUES); 503 DBGPR("max tx/rx channel count = %u/%u\n", 504 pdata->tx_max_channel_count, pdata->rx_max_channel_count); 505 DBGPR("max tx/rx hw queue count = %u/%u\n", 506 pdata->tx_max_q_count, pdata->rx_max_q_count); 507 508 axgbe_set_counts(ctx); 509 510 /* Set the maximum fifo amounts */ 511 pdata->tx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2, 512 TX_FIFO_SIZE); 513 pdata->tx_max_fifo_size *= 16384; 514 pdata->tx_max_fifo_size = min(pdata->tx_max_fifo_size, 515 pdata->vdata->tx_max_fifo_size); 516 pdata->rx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2, 517 RX_FIFO_SIZE); 518 pdata->rx_max_fifo_size *= 16384; 519 pdata->rx_max_fifo_size = min(pdata->rx_max_fifo_size, 520 pdata->vdata->rx_max_fifo_size); 521 DBGPR("max tx/rx max fifo size = %u/%u\n", 522 pdata->tx_max_fifo_size, pdata->rx_max_fifo_size); 523 524 /* Initialize IFLIB if_softc_ctx_t */ 525 axgbe_init_iflib_softc_ctx(sc); 526 527 /* Alloc channels */ 528 if (axgbe_alloc_channels(ctx)) { 529 axgbe_error("Unable to allocate channel memory\n"); 530 return (ENOMEM); 531 } 532 533 TASK_INIT(&pdata->service_work, 0, xgbe_service, pdata); 534 535 /* create the workqueue */ 536 pdata->dev_workqueue = taskqueue_create("axgbe", M_WAITOK, 537 taskqueue_thread_enqueue, &pdata->dev_workqueue); 538 taskqueue_start_threads(&pdata->dev_workqueue, 1, PI_NET, 539 "axgbe dev taskq"); 540 541 /* Init timers */ 542 xgbe_init_timers(pdata); 543 544 return (0); 545 } /* axgbe_if_attach_pre */ 546 547 static void 548 xgbe_init_all_fptrs(struct xgbe_prv_data *pdata) 549 { 550 xgbe_init_function_ptrs_dev(&pdata->hw_if); 551 xgbe_init_function_ptrs_phy(&pdata->phy_if); 552 xgbe_init_function_ptrs_i2c(&pdata->i2c_if); 553 xgbe_init_function_ptrs_desc(&pdata->desc_if); 554 555 pdata->vdata->init_function_ptrs_phy_impl(&pdata->phy_if); 556 } 557 558 static void 559 axgbe_set_counts(if_ctx_t ctx) 560 { 561 struct axgbe_if_softc *sc = iflib_get_softc(ctx);; 562 struct xgbe_prv_data *pdata = &sc->pdata; 563 cpuset_t lcpus; 564 int cpu_count, err; 565 size_t len; 566 567 /* Set all function pointers */ 568 xgbe_init_all_fptrs(pdata); 569 570 /* Populate the hardware features */ 571 xgbe_get_all_hw_features(pdata); 572 573 if (!pdata->tx_max_channel_count) 574 pdata->tx_max_channel_count = pdata->hw_feat.tx_ch_cnt; 575 if (!pdata->rx_max_channel_count) 576 pdata->rx_max_channel_count = pdata->hw_feat.rx_ch_cnt; 577 578 if (!pdata->tx_max_q_count) 579 pdata->tx_max_q_count = pdata->hw_feat.tx_q_cnt; 580 if (!pdata->rx_max_q_count) 581 pdata->rx_max_q_count = pdata->hw_feat.rx_q_cnt; 582 583 /* 584 * Calculate the number of Tx and Rx rings to be created 585 * -Tx (DMA) Channels map 1-to-1 to Tx Queues so set 586 * the number of Tx queues to the number of Tx channels 587 * enabled 588 * -Rx (DMA) Channels do not map 1-to-1 so use the actual 589 * number of Rx queues or maximum allowed 590 */ 591 592 /* Get cpu count from sysctl */ 593 len = sizeof(cpu_count); 594 err = kernel_sysctlbyname(curthread, "hw.ncpu", &cpu_count, &len, NULL, 595 0, NULL, 0); 596 if (err) { 597 axgbe_error("Unable to fetch number of cpus\n"); 598 cpu_count = 1; 599 } 600 601 if (bus_get_cpus(pdata->dev, INTR_CPUS, sizeof(lcpus), &lcpus) != 0) { 602 axgbe_error("Unable to fetch CPU list\n"); 603 /* TODO - handle CPU_COPY(&all_cpus, &lcpus); */ 604 } 605 606 DBGPR("ncpu %d intrcpu %d\n", cpu_count, CPU_COUNT(&lcpus)); 607 608 pdata->tx_ring_count = min(CPU_COUNT(&lcpus), pdata->hw_feat.tx_ch_cnt); 609 pdata->tx_ring_count = min(pdata->tx_ring_count, 610 pdata->tx_max_channel_count); 611 pdata->tx_ring_count = min(pdata->tx_ring_count, pdata->tx_max_q_count); 612 613 pdata->tx_q_count = pdata->tx_ring_count; 614 615 pdata->rx_ring_count = min(CPU_COUNT(&lcpus), pdata->hw_feat.rx_ch_cnt); 616 pdata->rx_ring_count = min(pdata->rx_ring_count, 617 pdata->rx_max_channel_count); 618 619 pdata->rx_q_count = min(pdata->hw_feat.rx_q_cnt, pdata->rx_max_q_count); 620 621 DBGPR("TX/RX max channel count = %u/%u\n", 622 pdata->tx_max_channel_count, pdata->rx_max_channel_count); 623 DBGPR("TX/RX max queue count = %u/%u\n", 624 pdata->tx_max_q_count, pdata->rx_max_q_count); 625 DBGPR("TX/RX DMA ring count = %u/%u\n", 626 pdata->tx_ring_count, pdata->rx_ring_count); 627 DBGPR("TX/RX hardware queue count = %u/%u\n", 628 pdata->tx_q_count, pdata->rx_q_count); 629 } /* axgbe_set_counts */ 630 631 static void 632 axgbe_init_iflib_softc_ctx(struct axgbe_if_softc *sc) 633 { 634 struct xgbe_prv_data *pdata = &sc->pdata; 635 if_softc_ctx_t scctx = sc->scctx; 636 if_shared_ctx_t sctx = sc->sctx; 637 int i; 638 639 scctx->isc_nrxqsets = pdata->rx_q_count; 640 scctx->isc_ntxqsets = pdata->tx_q_count; 641 scctx->isc_msix_bar = pci_msix_table_bar(pdata->dev); 642 scctx->isc_tx_nsegments = 32; 643 644 for (i = 0; i < sctx->isc_ntxqs; i++) { 645 scctx->isc_txqsizes[i] = 646 roundup2(scctx->isc_ntxd[i] * sizeof(struct xgbe_ring_desc), 647 128); 648 scctx->isc_txd_size[i] = sizeof(struct xgbe_ring_desc); 649 } 650 651 for (i = 0; i < sctx->isc_nrxqs; i++) { 652 scctx->isc_rxqsizes[i] = 653 roundup2(scctx->isc_nrxd[i] * sizeof(struct xgbe_ring_desc), 654 128); 655 scctx->isc_rxd_size[i] = sizeof(struct xgbe_ring_desc); 656 } 657 658 scctx->isc_tx_tso_segments_max = 32; 659 scctx->isc_tx_tso_size_max = XGBE_TSO_MAX_SIZE; 660 scctx->isc_tx_tso_segsize_max = PAGE_SIZE; 661 662 /* 663 * Set capabilities 664 * 1) IFLIB automatically adds IFCAP_HWSTATS, so need to set explicitly 665 * 2) isc_tx_csum_flags is mandatory if IFCAP_TXCSUM (included in 666 * IFCAP_HWCSUM) is set 667 */ 668 scctx->isc_tx_csum_flags = (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP | 669 CSUM_TCP_IPV6 | CSUM_UDP_IPV6 | CSUM_SCTP_IPV6 | 670 CSUM_TSO); 671 scctx->isc_capenable = (IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6 | 672 IFCAP_JUMBO_MTU | 673 IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWFILTER | 674 IFCAP_VLAN_HWCSUM | 675 IFCAP_TSO | IFCAP_VLAN_HWTSO); 676 scctx->isc_capabilities = scctx->isc_capenable; 677 678 /* 679 * Set rss_table_size alone when adding RSS support. rss_table_mask 680 * will be set by IFLIB based on rss_table_size 681 */ 682 scctx->isc_rss_table_size = XGBE_RSS_MAX_TABLE_SIZE; 683 684 scctx->isc_ntxqsets_max = XGBE_MAX_QUEUES; 685 scctx->isc_nrxqsets_max = XGBE_MAX_QUEUES; 686 687 scctx->isc_txrx = &axgbe_txrx; 688 } 689 690 static int 691 axgbe_alloc_channels(if_ctx_t ctx) 692 { 693 struct axgbe_if_softc *sc = iflib_get_softc(ctx); 694 struct xgbe_prv_data *pdata = &sc->pdata; 695 struct xgbe_channel *channel; 696 int i, j, count; 697 698 DBGPR("%s: txqs %d rxqs %d\n", __func__, pdata->tx_ring_count, 699 pdata->rx_ring_count); 700 701 /* Iflibe sets based on isc_ntxqsets/nrxqsets */ 702 count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count); 703 704 /* Allocate channel memory */ 705 for (i = 0; i < count ; i++) { 706 channel = (struct xgbe_channel*)malloc(sizeof(struct xgbe_channel), 707 M_AXGBE, M_NOWAIT | M_ZERO); 708 709 if (channel == NULL) { 710 for (j = 0; j < i; j++) { 711 free(pdata->channel[j], M_AXGBE); 712 pdata->channel[j] = NULL; 713 } 714 return (ENOMEM); 715 } 716 717 pdata->channel[i] = channel; 718 } 719 720 pdata->total_channel_count = count; 721 DBGPR("Channel count set to: %u\n", pdata->total_channel_count); 722 723 for (i = 0; i < count; i++) { 724 725 channel = pdata->channel[i]; 726 snprintf(channel->name, sizeof(channel->name), "channel-%d",i); 727 728 channel->pdata = pdata; 729 channel->queue_index = i; 730 channel->dma_tag = rman_get_bustag(pdata->xgmac_res); 731 bus_space_subregion(channel->dma_tag, 732 rman_get_bushandle(pdata->xgmac_res), 733 DMA_CH_BASE + (DMA_CH_INC * i), DMA_CH_INC, 734 &channel->dma_handle); 735 channel->tx_ring = NULL; 736 channel->rx_ring = NULL; 737 } 738 739 return (0); 740 } /* axgbe_alloc_channels */ 741 742 static void 743 xgbe_service(void *ctx, int pending) 744 { 745 struct xgbe_prv_data *pdata = ctx; 746 struct axgbe_if_softc *sc = (struct axgbe_if_softc *)pdata; 747 bool prev_state = false; 748 749 /* Get previous link status */ 750 prev_state = pdata->phy.link; 751 752 pdata->phy_if.phy_status(pdata); 753 754 if (prev_state != pdata->phy.link) { 755 pdata->phy_link = pdata->phy.link; 756 axgbe_if_update_admin_status(sc->ctx); 757 } 758 759 callout_reset(&pdata->service_timer, 1*hz, xgbe_service_timer, pdata); 760 } 761 762 static void 763 xgbe_service_timer(void *data) 764 { 765 struct xgbe_prv_data *pdata = data; 766 767 taskqueue_enqueue(pdata->dev_workqueue, &pdata->service_work); 768 } 769 770 static void 771 xgbe_init_timers(struct xgbe_prv_data *pdata) 772 { 773 callout_init(&pdata->service_timer, 1); 774 } 775 776 static void 777 xgbe_start_timers(struct xgbe_prv_data *pdata) 778 { 779 callout_reset(&pdata->service_timer, 1*hz, xgbe_service_timer, pdata); 780 } 781 782 static void 783 xgbe_stop_timers(struct xgbe_prv_data *pdata) 784 { 785 callout_drain(&pdata->service_timer); 786 callout_stop(&pdata->service_timer); 787 } 788 789 static void 790 xgbe_dump_phy_registers(struct xgbe_prv_data *pdata) 791 { 792 axgbe_printf(1, "\n************* PHY Reg dump *********************\n"); 793 794 axgbe_printf(1, "PCS Control Reg (%#06x) = %#06x\n", MDIO_CTRL1, 795 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1)); 796 axgbe_printf(1, "PCS Status Reg (%#06x) = %#06x\n", MDIO_STAT1, 797 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1)); 798 axgbe_printf(1, "Phy Id (PHYS ID 1 %#06x)= %#06x\n", MDIO_DEVID1, 799 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID1)); 800 axgbe_printf(1, "Phy Id (PHYS ID 2 %#06x)= %#06x\n", MDIO_DEVID2, 801 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID2)); 802 axgbe_printf(1, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS1, 803 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS1)); 804 axgbe_printf(1, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS2, 805 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS2)); 806 axgbe_printf(1, "Auto-Neg Control Reg (%#06x) = %#06x\n", MDIO_CTRL1, 807 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1)); 808 axgbe_printf(1, "Auto-Neg Status Reg (%#06x) = %#06x\n", MDIO_STAT1, 809 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_STAT1)); 810 axgbe_printf(1, "Auto-Neg Ad Reg 1 (%#06x) = %#06x\n", 811 MDIO_AN_ADVERTISE, 812 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE)); 813 axgbe_printf(1, "Auto-Neg Ad Reg 2 (%#06x) = %#06x\n", 814 MDIO_AN_ADVERTISE + 1, 815 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1)); 816 axgbe_printf(1, "Auto-Neg Ad Reg 3 (%#06x) = %#06x\n", 817 MDIO_AN_ADVERTISE + 2, 818 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2)); 819 axgbe_printf(1, "Auto-Neg Completion Reg (%#06x) = %#06x\n", 820 MDIO_AN_COMP_STAT, 821 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_COMP_STAT)); 822 823 axgbe_printf(1, "\n************************************************\n"); 824 } 825 826 static void 827 xgbe_dump_prop_registers(struct xgbe_prv_data *pdata) 828 { 829 int i; 830 831 axgbe_printf(1, "\n************* PROP Reg dump ********************\n"); 832 833 for (i = 0 ; i < 38 ; i++) { 834 axgbe_printf(1, "PROP Offset 0x%08x = %08x\n", 835 (XP_PROP_0 + (i * 4)), XP_IOREAD(pdata, 836 (XP_PROP_0 + (i * 4)))); 837 } 838 } 839 840 static void 841 xgbe_dump_dma_registers(struct xgbe_prv_data *pdata, int ch) 842 { 843 struct xgbe_channel *channel; 844 int i; 845 846 axgbe_printf(1, "\n************* DMA Reg dump *********************\n"); 847 848 axgbe_printf(1, "DMA MR Reg (%08x) = %08x\n", DMA_MR, 849 XGMAC_IOREAD(pdata, DMA_MR)); 850 axgbe_printf(1, "DMA SBMR Reg (%08x) = %08x\n", DMA_SBMR, 851 XGMAC_IOREAD(pdata, DMA_SBMR)); 852 axgbe_printf(1, "DMA ISR Reg (%08x) = %08x\n", DMA_ISR, 853 XGMAC_IOREAD(pdata, DMA_ISR)); 854 axgbe_printf(1, "DMA AXIARCR Reg (%08x) = %08x\n", DMA_AXIARCR, 855 XGMAC_IOREAD(pdata, DMA_AXIARCR)); 856 axgbe_printf(1, "DMA AXIAWCR Reg (%08x) = %08x\n", DMA_AXIAWCR, 857 XGMAC_IOREAD(pdata, DMA_AXIAWCR)); 858 axgbe_printf(1, "DMA AXIAWARCR Reg (%08x) = %08x\n", DMA_AXIAWARCR, 859 XGMAC_IOREAD(pdata, DMA_AXIAWARCR)); 860 axgbe_printf(1, "DMA DSR0 Reg (%08x) = %08x\n", DMA_DSR0, 861 XGMAC_IOREAD(pdata, DMA_DSR0)); 862 axgbe_printf(1, "DMA DSR1 Reg (%08x) = %08x\n", DMA_DSR1, 863 XGMAC_IOREAD(pdata, DMA_DSR1)); 864 axgbe_printf(1, "DMA DSR2 Reg (%08x) = %08x\n", DMA_DSR2, 865 XGMAC_IOREAD(pdata, DMA_DSR2)); 866 axgbe_printf(1, "DMA DSR3 Reg (%08x) = %08x\n", DMA_DSR3, 867 XGMAC_IOREAD(pdata, DMA_DSR3)); 868 axgbe_printf(1, "DMA DSR4 Reg (%08x) = %08x\n", DMA_DSR4, 869 XGMAC_IOREAD(pdata, DMA_DSR4)); 870 axgbe_printf(1, "DMA TXEDMACR Reg (%08x) = %08x\n", DMA_TXEDMACR, 871 XGMAC_IOREAD(pdata, DMA_TXEDMACR)); 872 axgbe_printf(1, "DMA RXEDMACR Reg (%08x) = %08x\n", DMA_RXEDMACR, 873 XGMAC_IOREAD(pdata, DMA_RXEDMACR)); 874 875 for (i = 0 ; i < 8 ; i++ ) { 876 877 if (ch >= 0) { 878 if (i != ch) 879 continue; 880 } 881 882 channel = pdata->channel[i]; 883 884 axgbe_printf(1, "\n************* DMA CH %d dump ****************\n", i); 885 886 axgbe_printf(1, "DMA_CH_CR Reg (%08x) = %08x\n", 887 DMA_CH_CR, XGMAC_DMA_IOREAD(channel, DMA_CH_CR)); 888 axgbe_printf(1, "DMA_CH_TCR Reg (%08x) = %08x\n", 889 DMA_CH_TCR, XGMAC_DMA_IOREAD(channel, DMA_CH_TCR)); 890 axgbe_printf(1, "DMA_CH_RCR Reg (%08x) = %08x\n", 891 DMA_CH_RCR, XGMAC_DMA_IOREAD(channel, DMA_CH_RCR)); 892 axgbe_printf(1, "DMA_CH_TDLR_HI Reg (%08x) = %08x\n", 893 DMA_CH_TDLR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_TDLR_HI)); 894 axgbe_printf(1, "DMA_CH_TDLR_LO Reg (%08x) = %08x\n", 895 DMA_CH_TDLR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDLR_LO)); 896 axgbe_printf(1, "DMA_CH_RDLR_HI Reg (%08x) = %08x\n", 897 DMA_CH_RDLR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_RDLR_HI)); 898 axgbe_printf(1, "DMA_CH_RDLR_LO Reg (%08x) = %08x\n", 899 DMA_CH_RDLR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDLR_LO)); 900 axgbe_printf(1, "DMA_CH_TDTR_LO Reg (%08x) = %08x\n", 901 DMA_CH_TDTR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDTR_LO)); 902 axgbe_printf(1, "DMA_CH_RDTR_LO Reg (%08x) = %08x\n", 903 DMA_CH_RDTR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDTR_LO)); 904 axgbe_printf(1, "DMA_CH_TDRLR Reg (%08x) = %08x\n", 905 DMA_CH_TDRLR, XGMAC_DMA_IOREAD(channel, DMA_CH_TDRLR)); 906 axgbe_printf(1, "DMA_CH_RDRLR Reg (%08x) = %08x\n", 907 DMA_CH_RDRLR, XGMAC_DMA_IOREAD(channel, DMA_CH_RDRLR)); 908 axgbe_printf(1, "DMA_CH_IER Reg (%08x) = %08x\n", 909 DMA_CH_IER, XGMAC_DMA_IOREAD(channel, DMA_CH_IER)); 910 axgbe_printf(1, "DMA_CH_RIWT Reg (%08x) = %08x\n", 911 DMA_CH_RIWT, XGMAC_DMA_IOREAD(channel, DMA_CH_RIWT)); 912 axgbe_printf(1, "DMA_CH_CATDR_LO Reg (%08x) = %08x\n", 913 DMA_CH_CATDR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CATDR_LO)); 914 axgbe_printf(1, "DMA_CH_CARDR_LO Reg (%08x) = %08x\n", 915 DMA_CH_CARDR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CARDR_LO)); 916 axgbe_printf(1, "DMA_CH_CATBR_HI Reg (%08x) = %08x\n", 917 DMA_CH_CATBR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_CATBR_HI)); 918 axgbe_printf(1, "DMA_CH_CATBR_LO Reg (%08x) = %08x\n", 919 DMA_CH_CATBR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CATBR_LO)); 920 axgbe_printf(1, "DMA_CH_CARBR_HI Reg (%08x) = %08x\n", 921 DMA_CH_CARBR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_CARBR_HI)); 922 axgbe_printf(1, "DMA_CH_CARBR_LO Reg (%08x) = %08x\n", 923 DMA_CH_CARBR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CARBR_LO)); 924 axgbe_printf(1, "DMA_CH_SR Reg (%08x) = %08x\n", 925 DMA_CH_SR, XGMAC_DMA_IOREAD(channel, DMA_CH_SR)); 926 axgbe_printf(1, "DMA_CH_DSR Reg (%08x) = %08x\n", 927 DMA_CH_DSR, XGMAC_DMA_IOREAD(channel, DMA_CH_DSR)); 928 axgbe_printf(1, "DMA_CH_DCFL Reg (%08x) = %08x\n", 929 DMA_CH_DCFL, XGMAC_DMA_IOREAD(channel, DMA_CH_DCFL)); 930 axgbe_printf(1, "DMA_CH_MFC Reg (%08x) = %08x\n", 931 DMA_CH_MFC, XGMAC_DMA_IOREAD(channel, DMA_CH_MFC)); 932 axgbe_printf(1, "DMA_CH_TDTRO Reg (%08x) = %08x\n", 933 DMA_CH_TDTRO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDTRO)); 934 axgbe_printf(1, "DMA_CH_RDTRO Reg (%08x) = %08x\n", 935 DMA_CH_RDTRO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDTRO)); 936 axgbe_printf(1, "DMA_CH_TDWRO Reg (%08x) = %08x\n", 937 DMA_CH_TDWRO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDWRO)); 938 axgbe_printf(1, "DMA_CH_RDWRO Reg (%08x) = %08x\n", 939 DMA_CH_RDWRO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDWRO)); 940 } 941 } 942 943 static void 944 xgbe_dump_mtl_registers(struct xgbe_prv_data *pdata) 945 { 946 int i; 947 948 axgbe_printf(1, "\n************* MTL Reg dump *********************\n"); 949 950 axgbe_printf(1, "MTL OMR Reg (%08x) = %08x\n", MTL_OMR, 951 XGMAC_IOREAD(pdata, MTL_OMR)); 952 axgbe_printf(1, "MTL FDCR Reg (%08x) = %08x\n", MTL_FDCR, 953 XGMAC_IOREAD(pdata, MTL_FDCR)); 954 axgbe_printf(1, "MTL FDSR Reg (%08x) = %08x\n", MTL_FDSR, 955 XGMAC_IOREAD(pdata, MTL_FDSR)); 956 axgbe_printf(1, "MTL FDDR Reg (%08x) = %08x\n", MTL_FDDR, 957 XGMAC_IOREAD(pdata, MTL_FDDR)); 958 axgbe_printf(1, "MTL ISR Reg (%08x) = %08x\n", MTL_ISR, 959 XGMAC_IOREAD(pdata, MTL_ISR)); 960 axgbe_printf(1, "MTL RQDCM0R Reg (%08x) = %08x\n", MTL_RQDCM0R, 961 XGMAC_IOREAD(pdata, MTL_RQDCM0R)); 962 axgbe_printf(1, "MTL RQDCM1R Reg (%08x) = %08x\n", MTL_RQDCM1R, 963 XGMAC_IOREAD(pdata, MTL_RQDCM1R)); 964 axgbe_printf(1, "MTL RQDCM2R Reg (%08x) = %08x\n", MTL_RQDCM2R, 965 XGMAC_IOREAD(pdata, MTL_RQDCM2R)); 966 axgbe_printf(1, "MTL TCPM0R Reg (%08x) = %08x\n", MTL_TCPM0R, 967 XGMAC_IOREAD(pdata, MTL_TCPM0R)); 968 axgbe_printf(1, "MTL TCPM1R Reg (%08x) = %08x\n", MTL_TCPM1R, 969 XGMAC_IOREAD(pdata, MTL_TCPM1R)); 970 971 for (i = 0 ; i < 8 ; i++ ) { 972 973 axgbe_printf(1, "\n************* MTL CH %d dump ****************\n", i); 974 975 axgbe_printf(1, "MTL_Q_TQOMR Reg (%08x) = %08x\n", 976 MTL_Q_TQOMR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TQOMR)); 977 axgbe_printf(1, "MTL_Q_TQUR Reg (%08x) = %08x\n", 978 MTL_Q_TQUR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TQUR)); 979 axgbe_printf(1, "MTL_Q_TQDR Reg (%08x) = %08x\n", 980 MTL_Q_TQDR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TQDR)); 981 axgbe_printf(1, "MTL_Q_TC0ETSCR Reg (%08x) = %08x\n", 982 MTL_Q_TC0ETSCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TC0ETSCR)); 983 axgbe_printf(1, "MTL_Q_TC0ETSSR Reg (%08x) = %08x\n", 984 MTL_Q_TC0ETSSR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TC0ETSSR)); 985 axgbe_printf(1, "MTL_Q_TC0QWR Reg (%08x) = %08x\n", 986 MTL_Q_TC0QWR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TC0QWR)); 987 988 axgbe_printf(1, "MTL_Q_RQOMR Reg (%08x) = %08x\n", 989 MTL_Q_RQOMR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQOMR)); 990 axgbe_printf(1, "MTL_Q_RQMPOCR Reg (%08x) = %08x\n", 991 MTL_Q_RQMPOCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQMPOCR)); 992 axgbe_printf(1, "MTL_Q_RQDR Reg (%08x) = %08x\n", 993 MTL_Q_RQDR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQDR)); 994 axgbe_printf(1, "MTL_Q_RQCR Reg (%08x) = %08x\n", 995 MTL_Q_RQCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQCR)); 996 axgbe_printf(1, "MTL_Q_RQFCR Reg (%08x) = %08x\n", 997 MTL_Q_RQFCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQFCR)); 998 axgbe_printf(1, "MTL_Q_IER Reg (%08x) = %08x\n", 999 MTL_Q_IER, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_IER)); 1000 axgbe_printf(1, "MTL_Q_ISR Reg (%08x) = %08x\n", 1001 MTL_Q_ISR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR)); 1002 } 1003 } 1004 1005 static void 1006 xgbe_dump_mac_registers(struct xgbe_prv_data *pdata) 1007 { 1008 axgbe_printf(1, "\n************* MAC Reg dump **********************\n"); 1009 1010 axgbe_printf(1, "MAC TCR Reg (%08x) = %08x\n", MAC_TCR, 1011 XGMAC_IOREAD(pdata, MAC_TCR)); 1012 axgbe_printf(1, "MAC RCR Reg (%08x) = %08x\n", MAC_RCR, 1013 XGMAC_IOREAD(pdata, MAC_RCR)); 1014 axgbe_printf(1, "MAC PFR Reg (%08x) = %08x\n", MAC_PFR, 1015 XGMAC_IOREAD(pdata, MAC_PFR)); 1016 axgbe_printf(1, "MAC WTR Reg (%08x) = %08x\n", MAC_WTR, 1017 XGMAC_IOREAD(pdata, MAC_WTR)); 1018 axgbe_printf(1, "MAC HTR0 Reg (%08x) = %08x\n", MAC_HTR0, 1019 XGMAC_IOREAD(pdata, MAC_HTR0)); 1020 axgbe_printf(1, "MAC HTR1 Reg (%08x) = %08x\n", MAC_HTR1, 1021 XGMAC_IOREAD(pdata, MAC_HTR1)); 1022 axgbe_printf(1, "MAC HTR2 Reg (%08x) = %08x\n", MAC_HTR2, 1023 XGMAC_IOREAD(pdata, MAC_HTR2)); 1024 axgbe_printf(1, "MAC HTR3 Reg (%08x) = %08x\n", MAC_HTR3, 1025 XGMAC_IOREAD(pdata, MAC_HTR3)); 1026 axgbe_printf(1, "MAC HTR4 Reg (%08x) = %08x\n", MAC_HTR4, 1027 XGMAC_IOREAD(pdata, MAC_HTR4)); 1028 axgbe_printf(1, "MAC HTR5 Reg (%08x) = %08x\n", MAC_HTR5, 1029 XGMAC_IOREAD(pdata, MAC_HTR5)); 1030 axgbe_printf(1, "MAC HTR6 Reg (%08x) = %08x\n", MAC_HTR6, 1031 XGMAC_IOREAD(pdata, MAC_HTR6)); 1032 axgbe_printf(1, "MAC HTR7 Reg (%08x) = %08x\n", MAC_HTR7, 1033 XGMAC_IOREAD(pdata, MAC_HTR7)); 1034 axgbe_printf(1, "MAC VLANTR Reg (%08x) = %08x\n", MAC_VLANTR, 1035 XGMAC_IOREAD(pdata, MAC_VLANTR)); 1036 axgbe_printf(1, "MAC VLANHTR Reg (%08x) = %08x\n", MAC_VLANHTR, 1037 XGMAC_IOREAD(pdata, MAC_VLANHTR)); 1038 axgbe_printf(1, "MAC VLANIR Reg (%08x) = %08x\n", MAC_VLANIR, 1039 XGMAC_IOREAD(pdata, MAC_VLANIR)); 1040 axgbe_printf(1, "MAC IVLANIR Reg (%08x) = %08x\n", MAC_IVLANIR, 1041 XGMAC_IOREAD(pdata, MAC_IVLANIR)); 1042 axgbe_printf(1, "MAC RETMR Reg (%08x) = %08x\n", MAC_RETMR, 1043 XGMAC_IOREAD(pdata, MAC_RETMR)); 1044 axgbe_printf(1, "MAC Q0TFCR Reg (%08x) = %08x\n", MAC_Q0TFCR, 1045 XGMAC_IOREAD(pdata, MAC_Q0TFCR)); 1046 axgbe_printf(1, "MAC Q1TFCR Reg (%08x) = %08x\n", MAC_Q1TFCR, 1047 XGMAC_IOREAD(pdata, MAC_Q1TFCR)); 1048 axgbe_printf(1, "MAC Q2TFCR Reg (%08x) = %08x\n", MAC_Q2TFCR, 1049 XGMAC_IOREAD(pdata, MAC_Q2TFCR)); 1050 axgbe_printf(1, "MAC Q3TFCR Reg (%08x) = %08x\n", MAC_Q3TFCR, 1051 XGMAC_IOREAD(pdata, MAC_Q3TFCR)); 1052 axgbe_printf(1, "MAC Q4TFCR Reg (%08x) = %08x\n", MAC_Q4TFCR, 1053 XGMAC_IOREAD(pdata, MAC_Q4TFCR)); 1054 axgbe_printf(1, "MAC Q5TFCR Reg (%08x) = %08x\n", MAC_Q5TFCR, 1055 XGMAC_IOREAD(pdata, MAC_Q5TFCR)); 1056 axgbe_printf(1, "MAC Q6TFCR Reg (%08x) = %08x\n", MAC_Q6TFCR, 1057 XGMAC_IOREAD(pdata, MAC_Q6TFCR)); 1058 axgbe_printf(1, "MAC Q7TFCR Reg (%08x) = %08x\n", MAC_Q7TFCR, 1059 XGMAC_IOREAD(pdata, MAC_Q7TFCR)); 1060 axgbe_printf(1, "MAC RFCR Reg (%08x) = %08x\n", MAC_RFCR, 1061 XGMAC_IOREAD(pdata, MAC_RFCR)); 1062 axgbe_printf(1, "MAC RQC0R Reg (%08x) = %08x\n", MAC_RQC0R, 1063 XGMAC_IOREAD(pdata, MAC_RQC0R)); 1064 axgbe_printf(1, "MAC RQC1R Reg (%08x) = %08x\n", MAC_RQC1R, 1065 XGMAC_IOREAD(pdata, MAC_RQC1R)); 1066 axgbe_printf(1, "MAC RQC2R Reg (%08x) = %08x\n", MAC_RQC2R, 1067 XGMAC_IOREAD(pdata, MAC_RQC2R)); 1068 axgbe_printf(1, "MAC RQC3R Reg (%08x) = %08x\n", MAC_RQC3R, 1069 XGMAC_IOREAD(pdata, MAC_RQC3R)); 1070 axgbe_printf(1, "MAC ISR Reg (%08x) = %08x\n", MAC_ISR, 1071 XGMAC_IOREAD(pdata, MAC_ISR)); 1072 axgbe_printf(1, "MAC IER Reg (%08x) = %08x\n", MAC_IER, 1073 XGMAC_IOREAD(pdata, MAC_IER)); 1074 axgbe_printf(1, "MAC RTSR Reg (%08x) = %08x\n", MAC_RTSR, 1075 XGMAC_IOREAD(pdata, MAC_RTSR)); 1076 axgbe_printf(1, "MAC PMTCSR Reg (%08x) = %08x\n", MAC_PMTCSR, 1077 XGMAC_IOREAD(pdata, MAC_PMTCSR)); 1078 axgbe_printf(1, "MAC RWKPFR Reg (%08x) = %08x\n", MAC_RWKPFR, 1079 XGMAC_IOREAD(pdata, MAC_RWKPFR)); 1080 axgbe_printf(1, "MAC LPICSR Reg (%08x) = %08x\n", MAC_LPICSR, 1081 XGMAC_IOREAD(pdata, MAC_LPICSR)); 1082 axgbe_printf(1, "MAC LPITCR Reg (%08x) = %08x\n", MAC_LPITCR, 1083 XGMAC_IOREAD(pdata, MAC_LPITCR)); 1084 axgbe_printf(1, "MAC TIR Reg (%08x) = %08x\n", MAC_TIR, 1085 XGMAC_IOREAD(pdata, MAC_TIR)); 1086 axgbe_printf(1, "MAC VR Reg (%08x) = %08x\n", MAC_VR, 1087 XGMAC_IOREAD(pdata, MAC_VR)); 1088 axgbe_printf(1, "MAC DR Reg (%08x) = %08x\n", MAC_DR, 1089 XGMAC_IOREAD(pdata, MAC_DR)); 1090 axgbe_printf(1, "MAC HWF0R Reg (%08x) = %08x\n", MAC_HWF0R, 1091 XGMAC_IOREAD(pdata, MAC_HWF0R)); 1092 axgbe_printf(1, "MAC HWF1R Reg (%08x) = %08x\n", MAC_HWF1R, 1093 XGMAC_IOREAD(pdata, MAC_HWF1R)); 1094 axgbe_printf(1, "MAC HWF2R Reg (%08x) = %08x\n", MAC_HWF2R, 1095 XGMAC_IOREAD(pdata, MAC_HWF2R)); 1096 axgbe_printf(1, "MAC MDIOSCAR Reg (%08x) = %08x\n", MAC_MDIOSCAR, 1097 XGMAC_IOREAD(pdata, MAC_MDIOSCAR)); 1098 axgbe_printf(1, "MAC MDIOSCCDR Reg (%08x) = %08x\n", MAC_MDIOSCCDR, 1099 XGMAC_IOREAD(pdata, MAC_MDIOSCCDR)); 1100 axgbe_printf(1, "MAC MDIOISR Reg (%08x) = %08x\n", MAC_MDIOISR, 1101 XGMAC_IOREAD(pdata, MAC_MDIOISR)); 1102 axgbe_printf(1, "MAC MDIOIER Reg (%08x) = %08x\n", MAC_MDIOIER, 1103 XGMAC_IOREAD(pdata, MAC_MDIOIER)); 1104 axgbe_printf(1, "MAC MDIOCL22R Reg (%08x) = %08x\n", MAC_MDIOCL22R, 1105 XGMAC_IOREAD(pdata, MAC_MDIOCL22R)); 1106 axgbe_printf(1, "MAC GPIOCR Reg (%08x) = %08x\n", MAC_GPIOCR, 1107 XGMAC_IOREAD(pdata, MAC_GPIOCR)); 1108 axgbe_printf(1, "MAC GPIOSR Reg (%08x) = %08x\n", MAC_GPIOSR, 1109 XGMAC_IOREAD(pdata, MAC_GPIOSR)); 1110 axgbe_printf(1, "MAC MACA0HR Reg (%08x) = %08x\n", MAC_MACA0HR, 1111 XGMAC_IOREAD(pdata, MAC_MACA0HR)); 1112 axgbe_printf(1, "MAC MACA0LR Reg (%08x) = %08x\n", MAC_TCR, 1113 XGMAC_IOREAD(pdata, MAC_MACA0LR)); 1114 axgbe_printf(1, "MAC MACA1HR Reg (%08x) = %08x\n", MAC_MACA1HR, 1115 XGMAC_IOREAD(pdata, MAC_MACA1HR)); 1116 axgbe_printf(1, "MAC MACA1LR Reg (%08x) = %08x\n", MAC_MACA1LR, 1117 XGMAC_IOREAD(pdata, MAC_MACA1LR)); 1118 axgbe_printf(1, "MAC RSSCR Reg (%08x) = %08x\n", MAC_RSSCR, 1119 XGMAC_IOREAD(pdata, MAC_RSSCR)); 1120 axgbe_printf(1, "MAC RSSDR Reg (%08x) = %08x\n", MAC_RSSDR, 1121 XGMAC_IOREAD(pdata, MAC_RSSDR)); 1122 axgbe_printf(1, "MAC RSSAR Reg (%08x) = %08x\n", MAC_RSSAR, 1123 XGMAC_IOREAD(pdata, MAC_RSSAR)); 1124 axgbe_printf(1, "MAC TSCR Reg (%08x) = %08x\n", MAC_TSCR, 1125 XGMAC_IOREAD(pdata, MAC_TSCR)); 1126 axgbe_printf(1, "MAC SSIR Reg (%08x) = %08x\n", MAC_SSIR, 1127 XGMAC_IOREAD(pdata, MAC_SSIR)); 1128 axgbe_printf(1, "MAC STSR Reg (%08x) = %08x\n", MAC_STSR, 1129 XGMAC_IOREAD(pdata, MAC_STSR)); 1130 axgbe_printf(1, "MAC STNR Reg (%08x) = %08x\n", MAC_STNR, 1131 XGMAC_IOREAD(pdata, MAC_STNR)); 1132 axgbe_printf(1, "MAC STSUR Reg (%08x) = %08x\n", MAC_STSUR, 1133 XGMAC_IOREAD(pdata, MAC_STSUR)); 1134 axgbe_printf(1, "MAC STNUR Reg (%08x) = %08x\n", MAC_STNUR, 1135 XGMAC_IOREAD(pdata, MAC_STNUR)); 1136 axgbe_printf(1, "MAC TSAR Reg (%08x) = %08x\n", MAC_TSAR, 1137 XGMAC_IOREAD(pdata, MAC_TSAR)); 1138 axgbe_printf(1, "MAC TSSR Reg (%08x) = %08x\n", MAC_TSSR, 1139 XGMAC_IOREAD(pdata, MAC_TSSR)); 1140 axgbe_printf(1, "MAC TXSNR Reg (%08x) = %08x\n", MAC_TXSNR, 1141 XGMAC_IOREAD(pdata, MAC_TXSNR)); 1142 axgbe_printf(1, "MAC TXSSR Reg (%08x) = %08x\n", MAC_TXSSR, 1143 XGMAC_IOREAD(pdata, MAC_TXSSR)); 1144 } 1145 1146 static void 1147 xgbe_dump_rmon_counters(struct xgbe_prv_data *pdata) 1148 { 1149 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; 1150 1151 axgbe_printf(1, "\n************* RMON counters dump ***************\n"); 1152 1153 pdata->hw_if.read_mmc_stats(pdata); 1154 1155 axgbe_printf(1, "rmon txoctetcount_gb (%08x) = %08lx\n", 1156 MMC_TXOCTETCOUNT_GB_LO, stats->txoctetcount_gb); 1157 axgbe_printf(1, "rmon txframecount_gb (%08x) = %08lx\n", 1158 MMC_TXFRAMECOUNT_GB_LO, stats->txframecount_gb); 1159 axgbe_printf(1, "rmon txbroadcastframes_g (%08x) = %08lx\n", 1160 MMC_TXBROADCASTFRAMES_G_LO, stats->txbroadcastframes_g); 1161 axgbe_printf(1, "rmon txmulticastframes_g (%08x) = %08lx\n", 1162 MMC_TXMULTICASTFRAMES_G_LO, stats->txmulticastframes_g); 1163 axgbe_printf(1, "rmon tx64octets_gb (%08x) = %08lx\n", 1164 MMC_TX64OCTETS_GB_LO, stats->tx64octets_gb); 1165 axgbe_printf(1, "rmon tx65to127octets_gb (%08x) = %08lx\n", 1166 MMC_TX65TO127OCTETS_GB_LO, stats->tx65to127octets_gb); 1167 axgbe_printf(1, "rmon tx128to255octets_gb (%08x) = %08lx\n", 1168 MMC_TX128TO255OCTETS_GB_LO, stats->tx128to255octets_gb); 1169 axgbe_printf(1, "rmon tx256to511octets_gb (%08x) = %08lx\n", 1170 MMC_TX256TO511OCTETS_GB_LO, stats->tx256to511octets_gb); 1171 axgbe_printf(1, "rmon tx512to1023octets_gb (%08x) = %08lx\n", 1172 MMC_TX512TO1023OCTETS_GB_LO, stats->tx512to1023octets_gb); 1173 axgbe_printf(1, "rmon tx1024tomaxoctets_gb (%08x) = %08lx\n", 1174 MMC_TX1024TOMAXOCTETS_GB_LO, stats->tx1024tomaxoctets_gb); 1175 axgbe_printf(1, "rmon txunicastframes_gb (%08x) = %08lx\n", 1176 MMC_TXUNICASTFRAMES_GB_LO, stats->txunicastframes_gb); 1177 axgbe_printf(1, "rmon txmulticastframes_gb (%08x) = %08lx\n", 1178 MMC_TXMULTICASTFRAMES_GB_LO, stats->txmulticastframes_gb); 1179 axgbe_printf(1, "rmon txbroadcastframes_gb (%08x) = %08lx\n", 1180 MMC_TXBROADCASTFRAMES_GB_LO, stats->txbroadcastframes_gb); 1181 axgbe_printf(1, "rmon txunderflowerror (%08x) = %08lx\n", 1182 MMC_TXUNDERFLOWERROR_LO, stats->txunderflowerror); 1183 axgbe_printf(1, "rmon txoctetcount_g (%08x) = %08lx\n", 1184 MMC_TXOCTETCOUNT_G_LO, stats->txoctetcount_g); 1185 axgbe_printf(1, "rmon txframecount_g (%08x) = %08lx\n", 1186 MMC_TXFRAMECOUNT_G_LO, stats->txframecount_g); 1187 axgbe_printf(1, "rmon txpauseframes (%08x) = %08lx\n", 1188 MMC_TXPAUSEFRAMES_LO, stats->txpauseframes); 1189 axgbe_printf(1, "rmon txvlanframes_g (%08x) = %08lx\n", 1190 MMC_TXVLANFRAMES_G_LO, stats->txvlanframes_g); 1191 axgbe_printf(1, "rmon rxframecount_gb (%08x) = %08lx\n", 1192 MMC_RXFRAMECOUNT_GB_LO, stats->rxframecount_gb); 1193 axgbe_printf(1, "rmon rxoctetcount_gb (%08x) = %08lx\n", 1194 MMC_RXOCTETCOUNT_GB_LO, stats->rxoctetcount_gb); 1195 axgbe_printf(1, "rmon rxoctetcount_g (%08x) = %08lx\n", 1196 MMC_RXOCTETCOUNT_G_LO, stats->rxoctetcount_g); 1197 axgbe_printf(1, "rmon rxbroadcastframes_g (%08x) = %08lx\n", 1198 MMC_RXBROADCASTFRAMES_G_LO, stats->rxbroadcastframes_g); 1199 axgbe_printf(1, "rmon rxmulticastframes_g (%08x) = %08lx\n", 1200 MMC_RXMULTICASTFRAMES_G_LO, stats->rxmulticastframes_g); 1201 axgbe_printf(1, "rmon rxcrcerror (%08x) = %08lx\n", 1202 MMC_RXCRCERROR_LO, stats->rxcrcerror); 1203 axgbe_printf(1, "rmon rxrunterror (%08x) = %08lx\n", 1204 MMC_RXRUNTERROR, stats->rxrunterror); 1205 axgbe_printf(1, "rmon rxjabbererror (%08x) = %08lx\n", 1206 MMC_RXJABBERERROR, stats->rxjabbererror); 1207 axgbe_printf(1, "rmon rxundersize_g (%08x) = %08lx\n", 1208 MMC_RXUNDERSIZE_G, stats->rxundersize_g); 1209 axgbe_printf(1, "rmon rxoversize_g (%08x) = %08lx\n", 1210 MMC_RXOVERSIZE_G, stats->rxoversize_g); 1211 axgbe_printf(1, "rmon rx64octets_gb (%08x) = %08lx\n", 1212 MMC_RX64OCTETS_GB_LO, stats->rx64octets_gb); 1213 axgbe_printf(1, "rmon rx65to127octets_gb (%08x) = %08lx\n", 1214 MMC_RX65TO127OCTETS_GB_LO, stats->rx65to127octets_gb); 1215 axgbe_printf(1, "rmon rx128to255octets_gb (%08x) = %08lx\n", 1216 MMC_RX128TO255OCTETS_GB_LO, stats->rx128to255octets_gb); 1217 axgbe_printf(1, "rmon rx256to511octets_gb (%08x) = %08lx\n", 1218 MMC_RX256TO511OCTETS_GB_LO, stats->rx256to511octets_gb); 1219 axgbe_printf(1, "rmon rx512to1023octets_gb (%08x) = %08lx\n", 1220 MMC_RX512TO1023OCTETS_GB_LO, stats->rx512to1023octets_gb); 1221 axgbe_printf(1, "rmon rx1024tomaxoctets_gb (%08x) = %08lx\n", 1222 MMC_RX1024TOMAXOCTETS_GB_LO, stats->rx1024tomaxoctets_gb); 1223 axgbe_printf(1, "rmon rxunicastframes_g (%08x) = %08lx\n", 1224 MMC_RXUNICASTFRAMES_G_LO, stats->rxunicastframes_g); 1225 axgbe_printf(1, "rmon rxlengtherror (%08x) = %08lx\n", 1226 MMC_RXLENGTHERROR_LO, stats->rxlengtherror); 1227 axgbe_printf(1, "rmon rxoutofrangetype (%08x) = %08lx\n", 1228 MMC_RXOUTOFRANGETYPE_LO, stats->rxoutofrangetype); 1229 axgbe_printf(1, "rmon rxpauseframes (%08x) = %08lx\n", 1230 MMC_RXPAUSEFRAMES_LO, stats->rxpauseframes); 1231 axgbe_printf(1, "rmon rxfifooverflow (%08x) = %08lx\n", 1232 MMC_RXFIFOOVERFLOW_LO, stats->rxfifooverflow); 1233 axgbe_printf(1, "rmon rxvlanframes_gb (%08x) = %08lx\n", 1234 MMC_RXVLANFRAMES_GB_LO, stats->rxvlanframes_gb); 1235 axgbe_printf(1, "rmon rxwatchdogerror (%08x) = %08lx\n", 1236 MMC_RXWATCHDOGERROR, stats->rxwatchdogerror); 1237 } 1238 1239 void 1240 xgbe_dump_i2c_registers(struct xgbe_prv_data *pdata) 1241 { 1242 axgbe_printf(1, "*************** I2C Registers **************\n"); 1243 axgbe_printf(1, " IC_CON : %010x\n", 1244 XI2C_IOREAD(pdata, 0x00)); 1245 axgbe_printf(1, " IC_TAR : %010x\n", 1246 XI2C_IOREAD(pdata, 0x04)); 1247 axgbe_printf(1, " IC_HS_MADDR : %010x\n", 1248 XI2C_IOREAD(pdata, 0x0c)); 1249 axgbe_printf(1, " IC_INTR_STAT : %010x\n", 1250 XI2C_IOREAD(pdata, 0x2c)); 1251 axgbe_printf(1, " IC_INTR_MASK : %010x\n", 1252 XI2C_IOREAD(pdata, 0x30)); 1253 axgbe_printf(1, " IC_RAW_INTR_STAT : %010x\n", 1254 XI2C_IOREAD(pdata, 0x34)); 1255 axgbe_printf(1, " IC_RX_TL : %010x\n", 1256 XI2C_IOREAD(pdata, 0x38)); 1257 axgbe_printf(1, " IC_TX_TL : %010x\n", 1258 XI2C_IOREAD(pdata, 0x3c)); 1259 axgbe_printf(1, " IC_ENABLE : %010x\n", 1260 XI2C_IOREAD(pdata, 0x6c)); 1261 axgbe_printf(1, " IC_STATUS : %010x\n", 1262 XI2C_IOREAD(pdata, 0x70)); 1263 axgbe_printf(1, " IC_TXFLR : %010x\n", 1264 XI2C_IOREAD(pdata, 0x74)); 1265 axgbe_printf(1, " IC_RXFLR : %010x\n", 1266 XI2C_IOREAD(pdata, 0x78)); 1267 axgbe_printf(1, " IC_ENABLE_STATUS : %010x\n", 1268 XI2C_IOREAD(pdata, 0x9c)); 1269 axgbe_printf(1, " IC_COMP_PARAM1 : %010x\n", 1270 XI2C_IOREAD(pdata, 0xf4)); 1271 } 1272 1273 static void 1274 xgbe_dump_active_vlans(struct xgbe_prv_data *pdata) 1275 { 1276 int i; 1277 1278 for(i=0 ; i<BITS_TO_LONGS(VLAN_NVID); i++) { 1279 if (i && (i%8 == 0)) 1280 axgbe_printf(1, "\n"); 1281 axgbe_printf(1, "vlans[%d]: 0x%08lx ", i, pdata->active_vlans[i]); 1282 } 1283 axgbe_printf(1, "\n"); 1284 } 1285 1286 static void 1287 xgbe_default_config(struct xgbe_prv_data *pdata) 1288 { 1289 pdata->blen = DMA_SBMR_BLEN_64; 1290 pdata->pbl = DMA_PBL_128; 1291 pdata->aal = 1; 1292 pdata->rd_osr_limit = 8; 1293 pdata->wr_osr_limit = 8; 1294 pdata->tx_sf_mode = MTL_TSF_ENABLE; 1295 pdata->tx_threshold = MTL_TX_THRESHOLD_64; 1296 pdata->tx_osp_mode = DMA_OSP_ENABLE; 1297 pdata->rx_sf_mode = MTL_RSF_DISABLE; 1298 pdata->rx_threshold = MTL_RX_THRESHOLD_64; 1299 pdata->pause_autoneg = 1; 1300 pdata->tx_pause = 1; 1301 pdata->rx_pause = 1; 1302 pdata->phy_speed = SPEED_UNKNOWN; 1303 pdata->power_down = 0; 1304 pdata->enable_rss = 1; 1305 } 1306 1307 static void 1308 axgbe_setup_sysctl(struct xgbe_prv_data *pdata) 1309 { 1310 struct sysctl_ctx_list *clist; 1311 struct sysctl_oid *parent; 1312 struct sysctl_oid_list *top; 1313 1314 clist = device_get_sysctl_ctx(pdata->dev); 1315 parent = device_get_sysctl_tree(pdata->dev); 1316 top = SYSCTL_CHILDREN(parent); 1317 } 1318 1319 static int 1320 axgbe_if_attach_post(if_ctx_t ctx) 1321 { 1322 struct axgbe_if_softc *sc = iflib_get_softc(ctx); 1323 struct xgbe_prv_data *pdata = &sc->pdata; 1324 struct ifnet *ifp = pdata->netdev; 1325 struct xgbe_phy_if *phy_if = &pdata->phy_if; 1326 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1327 if_softc_ctx_t scctx = sc->scctx; 1328 int i, ret; 1329 1330 /* set split header support based on tunable */ 1331 pdata->sph_enable = axgbe_sph_enable; 1332 1333 /* Initialize ECC timestamps */ 1334 pdata->tx_sec_period = ticks; 1335 pdata->tx_ded_period = ticks; 1336 pdata->rx_sec_period = ticks; 1337 pdata->rx_ded_period = ticks; 1338 pdata->desc_sec_period = ticks; 1339 pdata->desc_ded_period = ticks; 1340 1341 /* Reset the hardware */ 1342 ret = hw_if->exit(&sc->pdata); 1343 if (ret) 1344 axgbe_error("%s: exit error %d\n", __func__, ret); 1345 1346 /* Configure the defaults */ 1347 xgbe_default_config(pdata); 1348 1349 /* Set default max values if not provided */ 1350 if (!pdata->tx_max_fifo_size) 1351 pdata->tx_max_fifo_size = pdata->hw_feat.tx_fifo_size; 1352 if (!pdata->rx_max_fifo_size) 1353 pdata->rx_max_fifo_size = pdata->hw_feat.rx_fifo_size; 1354 1355 DBGPR("%s: tx fifo 0x%x rx fifo 0x%x\n", __func__, 1356 pdata->tx_max_fifo_size, pdata->rx_max_fifo_size); 1357 1358 /* Set and validate the number of descriptors for a ring */ 1359 MPASS(powerof2(XGBE_TX_DESC_CNT)); 1360 pdata->tx_desc_count = XGBE_TX_DESC_CNT; 1361 MPASS(powerof2(XGBE_RX_DESC_CNT)); 1362 pdata->rx_desc_count = XGBE_RX_DESC_CNT; 1363 1364 /* Adjust the number of queues based on interrupts assigned */ 1365 if (pdata->channel_irq_count) { 1366 pdata->tx_ring_count = min_t(unsigned int, pdata->tx_ring_count, 1367 pdata->channel_irq_count); 1368 pdata->rx_ring_count = min_t(unsigned int, pdata->rx_ring_count, 1369 pdata->channel_irq_count); 1370 1371 DBGPR("adjusted TX %u/%u RX %u/%u\n", 1372 pdata->tx_ring_count, pdata->tx_q_count, 1373 pdata->rx_ring_count, pdata->rx_q_count); 1374 } 1375 1376 /* Set channel count based on interrupts assigned */ 1377 pdata->channel_count = max_t(unsigned int, scctx->isc_ntxqsets, 1378 scctx->isc_nrxqsets); 1379 DBGPR("Channel count set to: %u\n", pdata->channel_count); 1380 1381 /* Get RSS key */ 1382 #ifdef RSS 1383 rss_getkey((uint8_t *)pdata->rss_key); 1384 #else 1385 arc4rand(&pdata->rss_key, ARRAY_SIZE(pdata->rss_key), 0); 1386 #endif 1387 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1); 1388 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1); 1389 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1); 1390 1391 /* Initialize the PHY device */ 1392 pdata->sysctl_an_cdr_workaround = pdata->vdata->an_cdr_workaround; 1393 phy_if->phy_init(pdata); 1394 1395 /* Set the coalescing */ 1396 xgbe_init_rx_coalesce(&sc->pdata); 1397 xgbe_init_tx_coalesce(&sc->pdata); 1398 1399 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_KR, 0, NULL); 1400 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_T, 0, NULL); 1401 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_SFI, 0, NULL); 1402 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_KX, 0, NULL); 1403 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_CX, 0, NULL); 1404 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_LX, 0, NULL); 1405 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL); 1406 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 1407 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_SGMII, 0, NULL); 1408 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); 1409 ifmedia_add(sc->media, IFM_ETHER | IFM_100_SGMII, 0, NULL); 1410 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 1411 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO); 1412 1413 /* Initialize the phy */ 1414 pdata->phy_link = -1; 1415 pdata->phy_speed = SPEED_UNKNOWN; 1416 ret = phy_if->phy_reset(pdata); 1417 if (ret) 1418 return (ret); 1419 1420 /* Calculate the Rx buffer size before allocating rings */ 1421 ret = xgbe_calc_rx_buf_size(pdata->netdev, if_getmtu(pdata->netdev)); 1422 pdata->rx_buf_size = ret; 1423 DBGPR("%s: rx_buf_size %d\n", __func__, ret); 1424 1425 /* Setup RSS lookup table */ 1426 for (i = 0; i < XGBE_RSS_MAX_TABLE_SIZE; i++) 1427 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, 1428 i % pdata->rx_ring_count); 1429 1430 /* 1431 * Mark the device down until it is initialized, which happens 1432 * when the device is accessed first (for configuring the iface, 1433 * eg: setting IP) 1434 */ 1435 set_bit(XGBE_DOWN, &pdata->dev_state); 1436 1437 DBGPR("mtu %d\n", ifp->if_mtu); 1438 scctx->isc_max_frame_size = ifp->if_mtu + 18; 1439 scctx->isc_min_frame_size = XGMAC_MIN_PACKET; 1440 1441 axgbe_setup_sysctl(pdata); 1442 1443 axgbe_sysctl_init(pdata); 1444 1445 axgbe_pci_init(pdata); 1446 1447 return (0); 1448 } /* axgbe_if_attach_post */ 1449 1450 static void 1451 xgbe_free_intr(struct xgbe_prv_data *pdata, struct resource *res, void *tag, 1452 int rid) 1453 { 1454 if (tag) 1455 bus_teardown_intr(pdata->dev, res, tag); 1456 1457 if (res) 1458 bus_release_resource(pdata->dev, SYS_RES_IRQ, rid, res); 1459 } 1460 1461 static void 1462 axgbe_interrupts_free(if_ctx_t ctx) 1463 { 1464 struct axgbe_if_softc *sc = iflib_get_softc(ctx); 1465 struct xgbe_prv_data *pdata = &sc->pdata; 1466 if_softc_ctx_t scctx = sc->scctx; 1467 struct xgbe_channel *channel; 1468 struct if_irq irq; 1469 int i; 1470 1471 axgbe_printf(2, "%s: mode %d\n", __func__, scctx->isc_intr); 1472 1473 /* Free dev_irq */ 1474 iflib_irq_free(ctx, &pdata->dev_irq); 1475 1476 /* Free ecc_irq */ 1477 xgbe_free_intr(pdata, pdata->ecc_irq_res, pdata->ecc_irq_tag, 1478 pdata->ecc_rid); 1479 1480 /* Free i2c_irq */ 1481 xgbe_free_intr(pdata, pdata->i2c_irq_res, pdata->i2c_irq_tag, 1482 pdata->i2c_rid); 1483 1484 /* Free an_irq */ 1485 xgbe_free_intr(pdata, pdata->an_irq_res, pdata->an_irq_tag, 1486 pdata->an_rid); 1487 1488 for (i = 0; i < scctx->isc_nrxqsets; i++) { 1489 1490 channel = pdata->channel[i]; 1491 axgbe_printf(2, "%s: rid %d\n", __func__, channel->dma_irq_rid); 1492 irq.ii_res = channel->dma_irq_res; 1493 irq.ii_tag = channel->dma_irq_tag; 1494 iflib_irq_free(ctx, &irq); 1495 } 1496 } 1497 1498 static int 1499 axgbe_if_detach(if_ctx_t ctx) 1500 { 1501 struct axgbe_if_softc *sc = iflib_get_softc(ctx); 1502 struct xgbe_prv_data *pdata = &sc->pdata; 1503 struct xgbe_phy_if *phy_if = &pdata->phy_if; 1504 struct resource *mac_res[2]; 1505 1506 mac_res[0] = pdata->xgmac_res; 1507 mac_res[1] = pdata->xpcs_res; 1508 1509 phy_if->phy_exit(pdata); 1510 1511 /* Free Interrupts */ 1512 axgbe_interrupts_free(ctx); 1513 1514 /* Free workqueues */ 1515 taskqueue_free(pdata->dev_workqueue); 1516 1517 /* Release bus resources */ 1518 bus_release_resources(iflib_get_dev(ctx), axgbe_pci_mac_spec, mac_res); 1519 1520 /* Free VLAN bitmap */ 1521 free(pdata->active_vlans, M_AXGBE); 1522 1523 axgbe_sysctl_exit(pdata); 1524 1525 return (0); 1526 } /* axgbe_if_detach */ 1527 1528 static void 1529 axgbe_pci_init(struct xgbe_prv_data *pdata) 1530 { 1531 struct xgbe_phy_if *phy_if = &pdata->phy_if; 1532 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1533 int ret = 0; 1534 1535 if (!__predict_false((test_bit(XGBE_DOWN, &pdata->dev_state)))) { 1536 axgbe_printf(1, "%s: Starting when XGBE_UP\n", __func__); 1537 return; 1538 } 1539 1540 hw_if->init(pdata); 1541 1542 ret = phy_if->phy_start(pdata); 1543 if (ret) { 1544 axgbe_error("%s: phy start %d\n", __func__, ret); 1545 ret = hw_if->exit(pdata); 1546 if (ret) 1547 axgbe_error("%s: exit error %d\n", __func__, ret); 1548 return; 1549 } 1550 1551 hw_if->enable_tx(pdata); 1552 hw_if->enable_rx(pdata); 1553 1554 xgbe_start_timers(pdata); 1555 1556 clear_bit(XGBE_DOWN, &pdata->dev_state); 1557 1558 xgbe_dump_phy_registers(pdata); 1559 xgbe_dump_prop_registers(pdata); 1560 xgbe_dump_dma_registers(pdata, -1); 1561 xgbe_dump_mtl_registers(pdata); 1562 xgbe_dump_mac_registers(pdata); 1563 xgbe_dump_rmon_counters(pdata); 1564 } 1565 1566 static void 1567 axgbe_if_init(if_ctx_t ctx) 1568 { 1569 struct axgbe_if_softc *sc = iflib_get_softc(ctx); 1570 struct xgbe_prv_data *pdata = &sc->pdata; 1571 1572 axgbe_pci_init(pdata); 1573 } 1574 1575 static void 1576 axgbe_pci_stop(if_ctx_t ctx) 1577 { 1578 struct axgbe_if_softc *sc = iflib_get_softc(ctx); 1579 struct xgbe_prv_data *pdata = &sc->pdata; 1580 struct xgbe_phy_if *phy_if = &pdata->phy_if; 1581 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1582 int ret; 1583 1584 if (__predict_false(test_bit(XGBE_DOWN, &pdata->dev_state))) { 1585 axgbe_printf(1, "%s: Stopping when XGBE_DOWN\n", __func__); 1586 return; 1587 } 1588 1589 xgbe_stop_timers(pdata); 1590 taskqueue_drain_all(pdata->dev_workqueue); 1591 1592 hw_if->disable_tx(pdata); 1593 hw_if->disable_rx(pdata); 1594 1595 phy_if->phy_stop(pdata); 1596 1597 ret = hw_if->exit(pdata); 1598 if (ret) 1599 axgbe_error("%s: exit error %d\n", __func__, ret); 1600 1601 set_bit(XGBE_DOWN, &pdata->dev_state); 1602 } 1603 1604 static void 1605 axgbe_if_stop(if_ctx_t ctx) 1606 { 1607 axgbe_pci_stop(ctx); 1608 } 1609 1610 static void 1611 axgbe_if_disable_intr(if_ctx_t ctx) 1612 { 1613 /* TODO - implement */ 1614 } 1615 1616 static void 1617 axgbe_if_enable_intr(if_ctx_t ctx) 1618 { 1619 /* TODO - implement */ 1620 } 1621 1622 static int 1623 axgbe_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *va, uint64_t *pa, int ntxqs, 1624 int ntxqsets) 1625 { 1626 struct axgbe_if_softc *sc = iflib_get_softc(ctx); 1627 struct xgbe_prv_data *pdata = &sc->pdata; 1628 if_softc_ctx_t scctx = sc->scctx; 1629 struct xgbe_channel *channel; 1630 struct xgbe_ring *tx_ring; 1631 int i, j, k; 1632 1633 MPASS(scctx->isc_ntxqsets > 0); 1634 MPASS(scctx->isc_ntxqsets == ntxqsets); 1635 MPASS(ntxqs == 1); 1636 1637 axgbe_printf(1, "%s: txqsets %d/%d txqs %d\n", __func__, 1638 scctx->isc_ntxqsets, ntxqsets, ntxqs); 1639 1640 for (i = 0 ; i < ntxqsets; i++) { 1641 1642 channel = pdata->channel[i]; 1643 1644 tx_ring = (struct xgbe_ring*)malloc(ntxqs * 1645 sizeof(struct xgbe_ring), M_AXGBE, M_NOWAIT | M_ZERO); 1646 1647 if (tx_ring == NULL) { 1648 axgbe_error("Unable to allocate TX ring memory\n"); 1649 goto tx_ring_fail; 1650 } 1651 1652 channel->tx_ring = tx_ring; 1653 1654 for (j = 0; j < ntxqs; j++, tx_ring++) { 1655 tx_ring->rdata = 1656 (struct xgbe_ring_data*)malloc(scctx->isc_ntxd[j] * 1657 sizeof(struct xgbe_ring_data), M_AXGBE, M_NOWAIT); 1658 1659 /* Get the virtual & physical address of hw queues */ 1660 tx_ring->rdesc = (struct xgbe_ring_desc *)va[i*ntxqs + j]; 1661 tx_ring->rdesc_paddr = pa[i*ntxqs + j]; 1662 tx_ring->rdesc_count = scctx->isc_ntxd[j]; 1663 spin_lock_init(&tx_ring->lock); 1664 } 1665 } 1666 1667 axgbe_printf(1, "allocated for %d tx queues\n", scctx->isc_ntxqsets); 1668 1669 return (0); 1670 1671 tx_ring_fail: 1672 1673 for (j = 0; j < i ; j++) { 1674 1675 channel = pdata->channel[j]; 1676 1677 tx_ring = channel->tx_ring; 1678 for (k = 0; k < ntxqs ; k++, tx_ring++) { 1679 if (tx_ring && tx_ring->rdata) 1680 free(tx_ring->rdata, M_AXGBE); 1681 } 1682 free(channel->tx_ring, M_AXGBE); 1683 1684 channel->tx_ring = NULL; 1685 } 1686 1687 return (ENOMEM); 1688 1689 } /* axgbe_if_tx_queues_alloc */ 1690 1691 static int 1692 axgbe_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *va, uint64_t *pa, int nrxqs, 1693 int nrxqsets) 1694 { 1695 struct axgbe_if_softc *sc = iflib_get_softc(ctx); 1696 struct xgbe_prv_data *pdata = &sc->pdata; 1697 if_softc_ctx_t scctx = sc->scctx; 1698 struct xgbe_channel *channel; 1699 struct xgbe_ring *rx_ring; 1700 int i, j, k; 1701 1702 MPASS(scctx->isc_nrxqsets > 0); 1703 MPASS(scctx->isc_nrxqsets == nrxqsets); 1704 if (!pdata->sph_enable) { 1705 MPASS(nrxqs == 1); 1706 } else { 1707 MPASS(nrxqs == 2); 1708 } 1709 1710 axgbe_printf(1, "%s: rxqsets %d/%d rxqs %d\n", __func__, 1711 scctx->isc_nrxqsets, nrxqsets, nrxqs); 1712 1713 for (i = 0 ; i < nrxqsets; i++) { 1714 1715 channel = pdata->channel[i]; 1716 1717 rx_ring = (struct xgbe_ring*)malloc(nrxqs * 1718 sizeof(struct xgbe_ring), M_AXGBE, M_NOWAIT | M_ZERO); 1719 1720 if (rx_ring == NULL) { 1721 axgbe_error("Unable to allocate RX ring memory\n"); 1722 goto rx_ring_fail; 1723 } 1724 1725 channel->rx_ring = rx_ring; 1726 1727 for (j = 0; j < nrxqs; j++, rx_ring++) { 1728 rx_ring->rdata = 1729 (struct xgbe_ring_data*)malloc(scctx->isc_nrxd[j] * 1730 sizeof(struct xgbe_ring_data), M_AXGBE, M_NOWAIT); 1731 1732 /* Get the virtual and physical address of the hw queues */ 1733 rx_ring->rdesc = (struct xgbe_ring_desc *)va[i*nrxqs + j]; 1734 rx_ring->rdesc_paddr = pa[i*nrxqs + j]; 1735 rx_ring->rdesc_count = scctx->isc_nrxd[j]; 1736 spin_lock_init(&rx_ring->lock); 1737 } 1738 } 1739 1740 axgbe_printf(2, "allocated for %d rx queues\n", scctx->isc_nrxqsets); 1741 1742 return (0); 1743 1744 rx_ring_fail: 1745 1746 for (j = 0 ; j < i ; j++) { 1747 1748 channel = pdata->channel[j]; 1749 1750 rx_ring = channel->rx_ring; 1751 for (k = 0; k < nrxqs ; k++, rx_ring++) { 1752 if (rx_ring && rx_ring->rdata) 1753 free(rx_ring->rdata, M_AXGBE); 1754 } 1755 free(channel->rx_ring, M_AXGBE); 1756 1757 channel->rx_ring = NULL; 1758 } 1759 1760 return (ENOMEM); 1761 1762 } /* axgbe_if_rx_queues_alloc */ 1763 1764 static void 1765 axgbe_if_queues_free(if_ctx_t ctx) 1766 { 1767 struct axgbe_if_softc *sc = iflib_get_softc(ctx); 1768 struct xgbe_prv_data *pdata = &sc->pdata; 1769 if_softc_ctx_t scctx = sc->scctx; 1770 if_shared_ctx_t sctx = sc->sctx; 1771 struct xgbe_channel *channel; 1772 struct xgbe_ring *tx_ring; 1773 struct xgbe_ring *rx_ring; 1774 int i, j; 1775 1776 for (i = 0 ; i < scctx->isc_ntxqsets; i++) { 1777 1778 channel = pdata->channel[i]; 1779 1780 tx_ring = channel->tx_ring; 1781 for (j = 0; j < sctx->isc_ntxqs ; j++, tx_ring++) { 1782 if (tx_ring && tx_ring->rdata) 1783 free(tx_ring->rdata, M_AXGBE); 1784 } 1785 free(channel->tx_ring, M_AXGBE); 1786 channel->tx_ring = NULL; 1787 } 1788 1789 for (i = 0 ; i < scctx->isc_nrxqsets; i++) { 1790 1791 channel = pdata->channel[i]; 1792 1793 rx_ring = channel->rx_ring; 1794 for (j = 0; j < sctx->isc_nrxqs ; j++, rx_ring++) { 1795 if (rx_ring && rx_ring->rdata) 1796 free(rx_ring->rdata, M_AXGBE); 1797 } 1798 free(channel->rx_ring, M_AXGBE); 1799 channel->rx_ring = NULL; 1800 } 1801 1802 /* Free Channels */ 1803 for (i = 0; i < pdata->total_channel_count ; i++) { 1804 free(pdata->channel[i], M_AXGBE); 1805 pdata->channel[i] = NULL; 1806 } 1807 1808 pdata->total_channel_count = 0; 1809 pdata->channel_count = 0; 1810 } /* axgbe_if_queues_free */ 1811 1812 static void 1813 axgbe_if_vlan_register(if_ctx_t ctx, uint16_t vtag) 1814 { 1815 struct axgbe_if_softc *sc = iflib_get_softc(ctx); 1816 struct xgbe_prv_data *pdata = &sc->pdata; 1817 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1818 1819 if (!bit_test(pdata->active_vlans, vtag)) { 1820 axgbe_printf(0, "Registering VLAN %d\n", vtag); 1821 1822 bit_set(pdata->active_vlans, vtag); 1823 hw_if->update_vlan_hash_table(pdata); 1824 pdata->num_active_vlans++; 1825 1826 axgbe_printf(1, "Total active vlans: %d\n", 1827 pdata->num_active_vlans); 1828 } else 1829 axgbe_printf(0, "VLAN %d already registered\n", vtag); 1830 1831 xgbe_dump_active_vlans(pdata); 1832 } 1833 1834 static void 1835 axgbe_if_vlan_unregister(if_ctx_t ctx, uint16_t vtag) 1836 { 1837 struct axgbe_if_softc *sc = iflib_get_softc(ctx); 1838 struct xgbe_prv_data *pdata = &sc->pdata; 1839 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1840 1841 if (pdata->num_active_vlans == 0) { 1842 axgbe_printf(1, "No active VLANs to unregister\n"); 1843 return; 1844 } 1845 1846 if (bit_test(pdata->active_vlans, vtag)){ 1847 axgbe_printf(0, "Un-Registering VLAN %d\n", vtag); 1848 1849 bit_clear(pdata->active_vlans, vtag); 1850 hw_if->update_vlan_hash_table(pdata); 1851 pdata->num_active_vlans--; 1852 1853 axgbe_printf(1, "Total active vlans: %d\n", 1854 pdata->num_active_vlans); 1855 } else 1856 axgbe_printf(0, "VLAN %d already unregistered\n", vtag); 1857 1858 xgbe_dump_active_vlans(pdata); 1859 } 1860 1861 #if __FreeBSD_version >= 1300000 1862 static bool 1863 axgbe_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 1864 { 1865 switch (event) { 1866 case IFLIB_RESTART_VLAN_CONFIG: 1867 default: 1868 return (true); 1869 } 1870 } 1871 #endif 1872 1873 static int 1874 axgbe_if_msix_intr_assign(if_ctx_t ctx, int msix) 1875 { 1876 struct axgbe_if_softc *sc = iflib_get_softc(ctx); 1877 struct xgbe_prv_data *pdata = &sc->pdata; 1878 if_softc_ctx_t scctx = sc->scctx; 1879 struct xgbe_channel *channel; 1880 struct if_irq irq; 1881 int i, error, rid = 0, flags; 1882 char buf[16]; 1883 1884 MPASS(scctx->isc_intr != IFLIB_INTR_LEGACY); 1885 1886 pdata->isr_as_tasklet = 1; 1887 1888 if (scctx->isc_intr == IFLIB_INTR_MSI) { 1889 pdata->irq_count = 1; 1890 pdata->channel_irq_count = 1; 1891 return (0); 1892 } 1893 1894 axgbe_printf(1, "%s: msix %d txqsets %d rxqsets %d\n", __func__, msix, 1895 scctx->isc_ntxqsets, scctx->isc_nrxqsets); 1896 1897 flags = RF_ACTIVE; 1898 1899 /* DEV INTR SETUP */ 1900 rid++; 1901 error = iflib_irq_alloc_generic(ctx, &pdata->dev_irq, rid, 1902 IFLIB_INTR_ADMIN, axgbe_dev_isr, sc, 0, "dev_irq"); 1903 if (error) { 1904 axgbe_error("Failed to register device interrupt rid %d name %s\n", 1905 rid, "dev_irq"); 1906 return (error); 1907 } 1908 1909 /* ECC INTR SETUP */ 1910 rid++; 1911 pdata->ecc_rid = rid; 1912 pdata->ecc_irq_res = bus_alloc_resource_any(pdata->dev, SYS_RES_IRQ, 1913 &rid, flags); 1914 if (!pdata->ecc_irq_res) { 1915 axgbe_error("failed to allocate IRQ for rid %d, name %s.\n", 1916 rid, "ecc_irq"); 1917 return (ENOMEM); 1918 } 1919 1920 error = bus_setup_intr(pdata->dev, pdata->ecc_irq_res, INTR_MPSAFE | 1921 INTR_TYPE_NET, NULL, axgbe_ecc_isr, sc, &pdata->ecc_irq_tag); 1922 if (error) { 1923 axgbe_error("failed to setup interrupt for rid %d, name %s: %d\n", 1924 rid, "ecc_irq", error); 1925 return (error); 1926 } 1927 1928 /* I2C INTR SETUP */ 1929 rid++; 1930 pdata->i2c_rid = rid; 1931 pdata->i2c_irq_res = bus_alloc_resource_any(pdata->dev, SYS_RES_IRQ, 1932 &rid, flags); 1933 if (!pdata->i2c_irq_res) { 1934 axgbe_error("failed to allocate IRQ for rid %d, name %s.\n", 1935 rid, "i2c_irq"); 1936 return (ENOMEM); 1937 } 1938 1939 error = bus_setup_intr(pdata->dev, pdata->i2c_irq_res, INTR_MPSAFE | 1940 INTR_TYPE_NET, NULL, axgbe_i2c_isr, sc, &pdata->i2c_irq_tag); 1941 if (error) { 1942 axgbe_error("failed to setup interrupt for rid %d, name %s: %d\n", 1943 rid, "i2c_irq", error); 1944 return (error); 1945 } 1946 1947 /* AN INTR SETUP */ 1948 rid++; 1949 pdata->an_rid = rid; 1950 pdata->an_irq_res = bus_alloc_resource_any(pdata->dev, SYS_RES_IRQ, 1951 &rid, flags); 1952 if (!pdata->an_irq_res) { 1953 axgbe_error("failed to allocate IRQ for rid %d, name %s.\n", 1954 rid, "an_irq"); 1955 return (ENOMEM); 1956 } 1957 1958 error = bus_setup_intr(pdata->dev, pdata->an_irq_res, INTR_MPSAFE | 1959 INTR_TYPE_NET, NULL, axgbe_an_isr, sc, &pdata->an_irq_tag); 1960 if (error) { 1961 axgbe_error("failed to setup interrupt for rid %d, name %s: %d\n", 1962 rid, "an_irq", error); 1963 return (error); 1964 } 1965 1966 pdata->per_channel_irq = 1; 1967 pdata->channel_irq_mode = XGBE_IRQ_MODE_LEVEL; 1968 rid++; 1969 for (i = 0; i < scctx->isc_nrxqsets; i++, rid++) { 1970 1971 channel = pdata->channel[i]; 1972 1973 snprintf(buf, sizeof(buf), "rxq%d", i); 1974 error = iflib_irq_alloc_generic(ctx, &irq, rid, IFLIB_INTR_RXTX, 1975 axgbe_msix_que, channel, channel->queue_index, buf); 1976 1977 if (error) { 1978 axgbe_error("Failed to allocated que int %d err: %d\n", 1979 i, error); 1980 return (error); 1981 } 1982 1983 channel->dma_irq_rid = rid; 1984 channel->dma_irq_res = irq.ii_res; 1985 channel->dma_irq_tag = irq.ii_tag; 1986 axgbe_printf(1, "%s: channel count %d idx %d irq %d\n", 1987 __func__, scctx->isc_nrxqsets, i, rid); 1988 } 1989 pdata->irq_count = msix; 1990 pdata->channel_irq_count = scctx->isc_nrxqsets; 1991 1992 for (i = 0; i < scctx->isc_ntxqsets; i++) { 1993 1994 channel = pdata->channel[i]; 1995 1996 snprintf(buf, sizeof(buf), "txq%d", i); 1997 irq.ii_res = channel->dma_irq_res; 1998 iflib_softirq_alloc_generic(ctx, &irq, IFLIB_INTR_TX, channel, 1999 channel->queue_index, buf); 2000 } 2001 2002 return (0); 2003 } /* axgbe_if_msix_intr_assign */ 2004 2005 static int 2006 xgbe_enable_rx_tx_int(struct xgbe_prv_data *pdata, struct xgbe_channel *channel) 2007 { 2008 struct xgbe_hw_if *hw_if = &pdata->hw_if; 2009 enum xgbe_int int_id; 2010 2011 if (channel->tx_ring && channel->rx_ring) 2012 int_id = XGMAC_INT_DMA_CH_SR_TI_RI; 2013 else if (channel->tx_ring) 2014 int_id = XGMAC_INT_DMA_CH_SR_TI; 2015 else if (channel->rx_ring) 2016 int_id = XGMAC_INT_DMA_CH_SR_RI; 2017 else 2018 return (-1); 2019 2020 axgbe_printf(1, "%s channel: %d rx_tx interrupt enabled %d\n", 2021 __func__, channel->queue_index, int_id); 2022 return (hw_if->enable_int(channel, int_id)); 2023 } 2024 2025 static void 2026 xgbe_disable_rx_tx_int(struct xgbe_prv_data *pdata, struct xgbe_channel *channel) 2027 { 2028 struct xgbe_hw_if *hw_if = &pdata->hw_if; 2029 enum xgbe_int int_id; 2030 2031 if (channel->tx_ring && channel->rx_ring) 2032 int_id = XGMAC_INT_DMA_CH_SR_TI_RI; 2033 else if (channel->tx_ring) 2034 int_id = XGMAC_INT_DMA_CH_SR_TI; 2035 else if (channel->rx_ring) 2036 int_id = XGMAC_INT_DMA_CH_SR_RI; 2037 else 2038 return; 2039 2040 axgbe_printf(1, "%s channel: %d rx_tx interrupt disabled %d\n", 2041 __func__, channel->queue_index, int_id); 2042 hw_if->disable_int(channel, int_id); 2043 } 2044 2045 static void 2046 xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata) 2047 { 2048 unsigned int i; 2049 2050 for (i = 0; i < pdata->channel_count; i++) 2051 xgbe_disable_rx_tx_int(pdata, pdata->channel[i]); 2052 } 2053 2054 static int 2055 axgbe_msix_que(void *arg) 2056 { 2057 struct xgbe_channel *channel = (struct xgbe_channel *)arg; 2058 struct xgbe_prv_data *pdata = channel->pdata; 2059 unsigned int dma_ch_isr, dma_status; 2060 2061 axgbe_printf(1, "%s: Channel: %d SR 0x%04x DSR 0x%04x IER:0x%04x D_ISR:0x%04x M_ISR:0x%04x\n", 2062 __func__, channel->queue_index, 2063 XGMAC_DMA_IOREAD(channel, DMA_CH_SR), 2064 XGMAC_DMA_IOREAD(channel, DMA_CH_DSR), 2065 XGMAC_DMA_IOREAD(channel, DMA_CH_IER), 2066 XGMAC_IOREAD(pdata, DMA_ISR), 2067 XGMAC_IOREAD(pdata, MAC_ISR)); 2068 2069 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR); 2070 2071 /* Disable Tx and Rx channel interrupts */ 2072 xgbe_disable_rx_tx_int(pdata, channel); 2073 2074 /* Clear the interrupts */ 2075 dma_status = 0; 2076 XGMAC_SET_BITS(dma_status, DMA_CH_SR, TI, 1); 2077 XGMAC_SET_BITS(dma_status, DMA_CH_SR, RI, 1); 2078 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_status); 2079 2080 return (FILTER_SCHEDULE_THREAD); 2081 } 2082 2083 static int 2084 axgbe_dev_isr(void *arg) 2085 { 2086 struct axgbe_if_softc *sc = (struct axgbe_if_softc *)arg; 2087 struct xgbe_prv_data *pdata = &sc->pdata; 2088 struct xgbe_channel *channel; 2089 struct xgbe_hw_if *hw_if = &pdata->hw_if; 2090 unsigned int i, dma_isr, dma_ch_isr; 2091 unsigned int mac_isr, mac_mdioisr; 2092 int ret = FILTER_HANDLED; 2093 2094 dma_isr = XGMAC_IOREAD(pdata, DMA_ISR); 2095 axgbe_printf(2, "%s DMA ISR: 0x%x\n", __func__, dma_isr); 2096 2097 if (!dma_isr) 2098 return (FILTER_HANDLED); 2099 2100 for (i = 0; i < pdata->channel_count; i++) { 2101 2102 if (!(dma_isr & (1 << i))) 2103 continue; 2104 2105 channel = pdata->channel[i]; 2106 2107 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR); 2108 axgbe_printf(2, "%s: channel %d SR 0x%x DSR 0x%x\n", __func__, 2109 channel->queue_index, dma_ch_isr, XGMAC_DMA_IOREAD(channel, 2110 DMA_CH_DSR)); 2111 2112 /* 2113 * The TI or RI interrupt bits may still be set even if using 2114 * per channel DMA interrupts. Check to be sure those are not 2115 * enabled before using the private data napi structure. 2116 */ 2117 if (!pdata->per_channel_irq && 2118 (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) || 2119 XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI))) { 2120 2121 /* Disable Tx and Rx interrupts */ 2122 xgbe_disable_rx_tx_ints(pdata); 2123 } else { 2124 2125 /* 2126 * Don't clear Rx/Tx status if doing per channel DMA 2127 * interrupts, these will be cleared by the ISR for 2128 * per channel DMA interrupts 2129 */ 2130 XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, TI, 0); 2131 XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, RI, 0); 2132 } 2133 2134 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RBU)) 2135 pdata->ext_stats.rx_buffer_unavailable++; 2136 2137 /* Restart the device on a Fatal Bus Error */ 2138 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE)) 2139 axgbe_error("%s: Fatal bus error reported 0x%x\n", 2140 __func__, dma_ch_isr); 2141 2142 /* Clear all interrupt signals */ 2143 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr); 2144 2145 ret = FILTER_SCHEDULE_THREAD; 2146 } 2147 2148 if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) { 2149 2150 mac_isr = XGMAC_IOREAD(pdata, MAC_ISR); 2151 axgbe_printf(2, "%s MAC ISR: 0x%x\n", __func__, mac_isr); 2152 2153 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS)) 2154 hw_if->tx_mmc_int(pdata); 2155 2156 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS)) 2157 hw_if->rx_mmc_int(pdata); 2158 2159 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, SMI)) { 2160 mac_mdioisr = XGMAC_IOREAD(pdata, MAC_MDIOISR); 2161 2162 if (XGMAC_GET_BITS(mac_mdioisr, MAC_MDIOISR, 2163 SNGLCOMPINT)) 2164 wakeup_one(pdata); 2165 } 2166 2167 } 2168 2169 return (ret); 2170 } /* axgbe_dev_isr */ 2171 2172 static void 2173 axgbe_i2c_isr(void *arg) 2174 { 2175 struct axgbe_if_softc *sc = (struct axgbe_if_softc *)arg; 2176 2177 sc->pdata.i2c_if.i2c_isr(&sc->pdata); 2178 } 2179 2180 static void 2181 axgbe_ecc_isr(void *arg) 2182 { 2183 /* TODO - implement */ 2184 } 2185 2186 static void 2187 axgbe_an_isr(void *arg) 2188 { 2189 struct axgbe_if_softc *sc = (struct axgbe_if_softc *)arg; 2190 2191 sc->pdata.phy_if.an_isr(&sc->pdata); 2192 } 2193 2194 static int 2195 axgbe_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t qid) 2196 { 2197 struct axgbe_if_softc *sc = iflib_get_softc(ctx); 2198 struct xgbe_prv_data *pdata = &sc->pdata; 2199 int ret; 2200 2201 if (qid < pdata->tx_q_count) { 2202 ret = xgbe_enable_rx_tx_int(pdata, pdata->channel[qid]); 2203 if (ret) { 2204 axgbe_error("Enable TX INT failed\n"); 2205 return (ret); 2206 } 2207 } else 2208 axgbe_error("Queue ID exceed channel count\n"); 2209 2210 return (0); 2211 } 2212 2213 static int 2214 axgbe_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t qid) 2215 { 2216 struct axgbe_if_softc *sc = iflib_get_softc(ctx); 2217 struct xgbe_prv_data *pdata = &sc->pdata; 2218 int ret; 2219 2220 if (qid < pdata->rx_q_count) { 2221 ret = xgbe_enable_rx_tx_int(pdata, pdata->channel[qid]); 2222 if (ret) { 2223 axgbe_error("Enable RX INT failed\n"); 2224 return (ret); 2225 } 2226 } else 2227 axgbe_error("Queue ID exceed channel count\n"); 2228 2229 return (0); 2230 } 2231 2232 static void 2233 axgbe_if_update_admin_status(if_ctx_t ctx) 2234 { 2235 struct axgbe_if_softc *sc = iflib_get_softc(ctx); 2236 struct xgbe_prv_data *pdata = &sc->pdata; 2237 2238 axgbe_printf(1, "%s: phy_link %d status %d speed %d\n", __func__, 2239 pdata->phy_link, sc->link_status, pdata->phy.speed); 2240 2241 if (pdata->phy_link < 0) 2242 return; 2243 2244 if (pdata->phy_link) { 2245 if (sc->link_status == LINK_STATE_DOWN) { 2246 sc->link_status = LINK_STATE_UP; 2247 if (pdata->phy.speed & SPEED_10000) 2248 iflib_link_state_change(ctx, LINK_STATE_UP, 2249 IF_Gbps(10)); 2250 else if (pdata->phy.speed & SPEED_2500) 2251 iflib_link_state_change(ctx, LINK_STATE_UP, 2252 IF_Gbps(2.5)); 2253 else if (pdata->phy.speed & SPEED_1000) 2254 iflib_link_state_change(ctx, LINK_STATE_UP, 2255 IF_Gbps(1)); 2256 else if (pdata->phy.speed & SPEED_100) 2257 iflib_link_state_change(ctx, LINK_STATE_UP, 2258 IF_Mbps(100)); 2259 else if (pdata->phy.speed & SPEED_10) 2260 iflib_link_state_change(ctx, LINK_STATE_UP, 2261 IF_Mbps(10)); 2262 } 2263 } else { 2264 if (sc->link_status == LINK_STATE_UP) { 2265 sc->link_status = LINK_STATE_DOWN; 2266 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 2267 } 2268 } 2269 } 2270 2271 static int 2272 axgbe_if_media_change(if_ctx_t ctx) 2273 { 2274 struct axgbe_if_softc *sc = iflib_get_softc(ctx); 2275 struct ifmedia *ifm = iflib_get_media(ctx); 2276 2277 sx_xlock(&sc->pdata.an_mutex); 2278 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2279 return (EINVAL); 2280 2281 switch (IFM_SUBTYPE(ifm->ifm_media)) { 2282 case IFM_10G_KR: 2283 sc->pdata.phy.speed = SPEED_10000; 2284 sc->pdata.phy.autoneg = AUTONEG_DISABLE; 2285 break; 2286 case IFM_2500_KX: 2287 sc->pdata.phy.speed = SPEED_2500; 2288 sc->pdata.phy.autoneg = AUTONEG_DISABLE; 2289 break; 2290 case IFM_1000_KX: 2291 sc->pdata.phy.speed = SPEED_1000; 2292 sc->pdata.phy.autoneg = AUTONEG_DISABLE; 2293 break; 2294 case IFM_100_TX: 2295 sc->pdata.phy.speed = SPEED_100; 2296 sc->pdata.phy.autoneg = AUTONEG_DISABLE; 2297 break; 2298 case IFM_AUTO: 2299 sc->pdata.phy.autoneg = AUTONEG_ENABLE; 2300 break; 2301 } 2302 sx_xunlock(&sc->pdata.an_mutex); 2303 2304 return (-sc->pdata.phy_if.phy_config_aneg(&sc->pdata)); 2305 } 2306 2307 static int 2308 axgbe_if_promisc_set(if_ctx_t ctx, int flags) 2309 { 2310 struct axgbe_if_softc *sc = iflib_get_softc(ctx); 2311 struct xgbe_prv_data *pdata = &sc->pdata; 2312 struct ifnet *ifp = pdata->netdev; 2313 2314 axgbe_printf(1, "%s: MAC_PFR 0x%x drv_flags 0x%x if_flags 0x%x\n", 2315 __func__, XGMAC_IOREAD(pdata, MAC_PFR), ifp->if_drv_flags, ifp->if_flags); 2316 2317 if (ifp->if_flags & IFF_PPROMISC) { 2318 2319 axgbe_printf(1, "User requested to enter promisc mode\n"); 2320 2321 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == 1) { 2322 axgbe_printf(1, "Already in promisc mode\n"); 2323 return (0); 2324 } 2325 2326 axgbe_printf(1, "Entering promisc mode\n"); 2327 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 1); 2328 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0); 2329 } else { 2330 2331 axgbe_printf(1, "User requested to leave promisc mode\n"); 2332 2333 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == 0) { 2334 axgbe_printf(1, "Already not in promisc mode\n"); 2335 return (0); 2336 } 2337 2338 axgbe_printf(1, "Leaving promisc mode\n"); 2339 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 0); 2340 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1); 2341 } 2342 2343 return (0); 2344 } 2345 2346 static uint64_t 2347 axgbe_if_get_counter(if_ctx_t ctx, ift_counter cnt) 2348 { 2349 struct axgbe_if_softc *sc = iflib_get_softc(ctx); 2350 struct ifnet *ifp = iflib_get_ifp(ctx); 2351 struct xgbe_prv_data *pdata = &sc->pdata; 2352 struct xgbe_mmc_stats *pstats = &pdata->mmc_stats; 2353 2354 pdata->hw_if.read_mmc_stats(pdata); 2355 2356 switch(cnt) { 2357 case IFCOUNTER_IPACKETS: 2358 return (pstats->rxframecount_gb); 2359 case IFCOUNTER_IERRORS: 2360 return (pstats->rxframecount_gb - pstats->rxbroadcastframes_g - 2361 pstats->rxmulticastframes_g - pstats->rxunicastframes_g); 2362 case IFCOUNTER_OPACKETS: 2363 return (pstats->txframecount_gb); 2364 case IFCOUNTER_OERRORS: 2365 return (pstats->txframecount_gb - pstats->txframecount_g); 2366 case IFCOUNTER_IBYTES: 2367 return (pstats->rxoctetcount_gb); 2368 case IFCOUNTER_OBYTES: 2369 return (pstats->txoctetcount_gb); 2370 default: 2371 return (if_get_counter_default(ifp, cnt)); 2372 } 2373 } 2374 2375 static int 2376 axgbe_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 2377 { 2378 struct axgbe_if_softc *sc = iflib_get_softc(ctx); 2379 struct xgbe_prv_data *pdata = &sc->pdata; 2380 int ret; 2381 2382 if (mtu > XGMAC_JUMBO_PACKET_MTU) 2383 return (EINVAL); 2384 2385 ret = xgbe_calc_rx_buf_size(pdata->netdev, mtu); 2386 pdata->rx_buf_size = ret; 2387 axgbe_printf(1, "%s: rx_buf_size %d\n", __func__, ret); 2388 2389 sc->scctx->isc_max_frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 2390 return (0); 2391 } 2392 2393 static void 2394 axgbe_if_media_status(if_ctx_t ctx, struct ifmediareq * ifmr) 2395 { 2396 struct axgbe_if_softc *sc = iflib_get_softc(ctx); 2397 struct xgbe_prv_data *pdata = &sc->pdata; 2398 2399 ifmr->ifm_status = IFM_AVALID; 2400 if (!sc->pdata.phy.link) 2401 return; 2402 2403 ifmr->ifm_active = IFM_ETHER; 2404 ifmr->ifm_status |= IFM_ACTIVE; 2405 2406 axgbe_printf(1, "Speed 0x%x Mode %d\n", sc->pdata.phy.speed, 2407 pdata->phy_if.phy_impl.cur_mode(pdata)); 2408 pdata->phy_if.phy_impl.get_type(pdata, ifmr); 2409 2410 ifmr->ifm_active |= IFM_FDX; 2411 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 2412 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 2413 } 2414