144b781cfSAndrew Turner /*
244b781cfSAndrew Turner * AMD 10Gb Ethernet driver
344b781cfSAndrew Turner *
47113afc8SEmmanuel Vadot * Copyright (c) 2014-2016,2020 Advanced Micro Devices, Inc.
57113afc8SEmmanuel Vadot *
644b781cfSAndrew Turner * This file is available to you under your choice of the following two
744b781cfSAndrew Turner * licenses:
844b781cfSAndrew Turner *
944b781cfSAndrew Turner * License 1: GPLv2
1044b781cfSAndrew Turner *
1144b781cfSAndrew Turner * This file is free software; you may copy, redistribute and/or modify
1244b781cfSAndrew Turner * it under the terms of the GNU General Public License as published by
1344b781cfSAndrew Turner * the Free Software Foundation, either version 2 of the License, or (at
1444b781cfSAndrew Turner * your option) any later version.
1544b781cfSAndrew Turner *
1644b781cfSAndrew Turner * This file is distributed in the hope that it will be useful, but
1744b781cfSAndrew Turner * WITHOUT ANY WARRANTY; without even the implied warranty of
1844b781cfSAndrew Turner * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
1944b781cfSAndrew Turner * General Public License for more details.
2044b781cfSAndrew Turner *
2144b781cfSAndrew Turner * You should have received a copy of the GNU General Public License
2244b781cfSAndrew Turner * along with this program. If not, see <http://www.gnu.org/licenses/>.
2344b781cfSAndrew Turner *
2444b781cfSAndrew Turner * This file incorporates work covered by the following copyright and
2544b781cfSAndrew Turner * permission notice:
2644b781cfSAndrew Turner * The Synopsys DWC ETHER XGMAC Software Driver and documentation
2744b781cfSAndrew Turner * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
2844b781cfSAndrew Turner * Inc. unless otherwise expressly agreed to in writing between Synopsys
2944b781cfSAndrew Turner * and you.
3044b781cfSAndrew Turner *
3144b781cfSAndrew Turner * The Software IS NOT an item of Licensed Software or Licensed Product
3244b781cfSAndrew Turner * under any End User Software License Agreement or Agreement for Licensed
3344b781cfSAndrew Turner * Product with Synopsys or any supplement thereto. Permission is hereby
3444b781cfSAndrew Turner * granted, free of charge, to any person obtaining a copy of this software
3544b781cfSAndrew Turner * annotated with this license and the Software, to deal in the Software
3644b781cfSAndrew Turner * without restriction, including without limitation the rights to use,
3744b781cfSAndrew Turner * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
3844b781cfSAndrew Turner * of the Software, and to permit persons to whom the Software is furnished
3944b781cfSAndrew Turner * to do so, subject to the following conditions:
4044b781cfSAndrew Turner *
4144b781cfSAndrew Turner * The above copyright notice and this permission notice shall be included
4244b781cfSAndrew Turner * in all copies or substantial portions of the Software.
4344b781cfSAndrew Turner *
4444b781cfSAndrew Turner * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
4544b781cfSAndrew Turner * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
4644b781cfSAndrew Turner * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
4744b781cfSAndrew Turner * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
4844b781cfSAndrew Turner * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
4944b781cfSAndrew Turner * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
5044b781cfSAndrew Turner * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
5144b781cfSAndrew Turner * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
5244b781cfSAndrew Turner * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
5344b781cfSAndrew Turner * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
5444b781cfSAndrew Turner * THE POSSIBILITY OF SUCH DAMAGE.
5544b781cfSAndrew Turner *
5644b781cfSAndrew Turner *
5744b781cfSAndrew Turner * License 2: Modified BSD
5844b781cfSAndrew Turner *
5944b781cfSAndrew Turner * Redistribution and use in source and binary forms, with or without
6044b781cfSAndrew Turner * modification, are permitted provided that the following conditions are met:
6144b781cfSAndrew Turner * * Redistributions of source code must retain the above copyright
6244b781cfSAndrew Turner * notice, this list of conditions and the following disclaimer.
6344b781cfSAndrew Turner * * Redistributions in binary form must reproduce the above copyright
6444b781cfSAndrew Turner * notice, this list of conditions and the following disclaimer in the
6544b781cfSAndrew Turner * documentation and/or other materials provided with the distribution.
6644b781cfSAndrew Turner * * Neither the name of Advanced Micro Devices, Inc. nor the
6744b781cfSAndrew Turner * names of its contributors may be used to endorse or promote products
6844b781cfSAndrew Turner * derived from this software without specific prior written permission.
6944b781cfSAndrew Turner *
7044b781cfSAndrew Turner * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
7144b781cfSAndrew Turner * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
7244b781cfSAndrew Turner * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
7344b781cfSAndrew Turner * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
7444b781cfSAndrew Turner * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
7544b781cfSAndrew Turner * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
7644b781cfSAndrew Turner * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
7744b781cfSAndrew Turner * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7844b781cfSAndrew Turner * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7944b781cfSAndrew Turner * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8044b781cfSAndrew Turner *
8144b781cfSAndrew Turner * This file incorporates work covered by the following copyright and
8244b781cfSAndrew Turner * permission notice:
8344b781cfSAndrew Turner * The Synopsys DWC ETHER XGMAC Software Driver and documentation
8444b781cfSAndrew Turner * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
8544b781cfSAndrew Turner * Inc. unless otherwise expressly agreed to in writing between Synopsys
8644b781cfSAndrew Turner * and you.
8744b781cfSAndrew Turner *
8844b781cfSAndrew Turner * The Software IS NOT an item of Licensed Software or Licensed Product
8944b781cfSAndrew Turner * under any End User Software License Agreement or Agreement for Licensed
9044b781cfSAndrew Turner * Product with Synopsys or any supplement thereto. Permission is hereby
9144b781cfSAndrew Turner * granted, free of charge, to any person obtaining a copy of this software
9244b781cfSAndrew Turner * annotated with this license and the Software, to deal in the Software
9344b781cfSAndrew Turner * without restriction, including without limitation the rights to use,
9444b781cfSAndrew Turner * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
9544b781cfSAndrew Turner * of the Software, and to permit persons to whom the Software is furnished
9644b781cfSAndrew Turner * to do so, subject to the following conditions:
9744b781cfSAndrew Turner *
9844b781cfSAndrew Turner * The above copyright notice and this permission notice shall be included
9944b781cfSAndrew Turner * in all copies or substantial portions of the Software.
10044b781cfSAndrew Turner *
10144b781cfSAndrew Turner * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
10244b781cfSAndrew Turner * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
10344b781cfSAndrew Turner * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
10444b781cfSAndrew Turner * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
10544b781cfSAndrew Turner * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
10644b781cfSAndrew Turner * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
10744b781cfSAndrew Turner * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
10844b781cfSAndrew Turner * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
10944b781cfSAndrew Turner * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
11044b781cfSAndrew Turner * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
11144b781cfSAndrew Turner * THE POSSIBILITY OF SUCH DAMAGE.
11244b781cfSAndrew Turner */
11344b781cfSAndrew Turner
1149c6d6488SAndrew Turner #include <sys/cdefs.h>
11544b781cfSAndrew Turner #include "xgbe.h"
11644b781cfSAndrew Turner #include "xgbe-common.h"
11744b781cfSAndrew Turner
1189c6d6488SAndrew Turner #include <net/if_dl.h>
1199c6d6488SAndrew Turner
xgbe_get_max_frame(struct xgbe_prv_data * pdata)1207113afc8SEmmanuel Vadot static inline unsigned int xgbe_get_max_frame(struct xgbe_prv_data *pdata)
1217113afc8SEmmanuel Vadot {
1227113afc8SEmmanuel Vadot return (if_getmtu(pdata->netdev) + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1237113afc8SEmmanuel Vadot }
1247113afc8SEmmanuel Vadot
1257113afc8SEmmanuel Vadot static unsigned int
xgbe_usec_to_riwt(struct xgbe_prv_data * pdata,unsigned int usec)1267113afc8SEmmanuel Vadot xgbe_usec_to_riwt(struct xgbe_prv_data *pdata, unsigned int usec)
12744b781cfSAndrew Turner {
12844b781cfSAndrew Turner unsigned long rate;
12944b781cfSAndrew Turner unsigned int ret;
13044b781cfSAndrew Turner
13144b781cfSAndrew Turner rate = pdata->sysclk_rate;
13244b781cfSAndrew Turner
13344b781cfSAndrew Turner /*
13444b781cfSAndrew Turner * Convert the input usec value to the watchdog timer value. Each
13544b781cfSAndrew Turner * watchdog timer value is equivalent to 256 clock cycles.
13644b781cfSAndrew Turner * Calculate the required value as:
13744b781cfSAndrew Turner * ( usec * ( system_clock_mhz / 10^6 ) / 256
13844b781cfSAndrew Turner */
13944b781cfSAndrew Turner ret = (usec * (rate / 1000000)) / 256;
14044b781cfSAndrew Turner
1417113afc8SEmmanuel Vadot return (ret);
14244b781cfSAndrew Turner }
14344b781cfSAndrew Turner
1447113afc8SEmmanuel Vadot static unsigned int
xgbe_riwt_to_usec(struct xgbe_prv_data * pdata,unsigned int riwt)1457113afc8SEmmanuel Vadot xgbe_riwt_to_usec(struct xgbe_prv_data *pdata, unsigned int riwt)
14644b781cfSAndrew Turner {
14744b781cfSAndrew Turner unsigned long rate;
14844b781cfSAndrew Turner unsigned int ret;
14944b781cfSAndrew Turner
15044b781cfSAndrew Turner rate = pdata->sysclk_rate;
15144b781cfSAndrew Turner
15244b781cfSAndrew Turner /*
15344b781cfSAndrew Turner * Convert the input watchdog timer value to the usec value. Each
15444b781cfSAndrew Turner * watchdog timer value is equivalent to 256 clock cycles.
15544b781cfSAndrew Turner * Calculate the required value as:
15644b781cfSAndrew Turner * ( riwt * 256 ) / ( system_clock_mhz / 10^6 )
15744b781cfSAndrew Turner */
15844b781cfSAndrew Turner ret = (riwt * 256) / (rate / 1000000);
15944b781cfSAndrew Turner
1607113afc8SEmmanuel Vadot return (ret);
16144b781cfSAndrew Turner }
16244b781cfSAndrew Turner
1637113afc8SEmmanuel Vadot static int
xgbe_config_pbl_val(struct xgbe_prv_data * pdata)1647113afc8SEmmanuel Vadot xgbe_config_pbl_val(struct xgbe_prv_data *pdata)
16544b781cfSAndrew Turner {
1667113afc8SEmmanuel Vadot unsigned int pblx8, pbl;
16744b781cfSAndrew Turner unsigned int i;
16844b781cfSAndrew Turner
1697113afc8SEmmanuel Vadot pblx8 = DMA_PBL_X8_DISABLE;
1707113afc8SEmmanuel Vadot pbl = pdata->pbl;
17144b781cfSAndrew Turner
1727113afc8SEmmanuel Vadot if (pdata->pbl > 32) {
1737113afc8SEmmanuel Vadot pblx8 = DMA_PBL_X8_ENABLE;
1747113afc8SEmmanuel Vadot pbl >>= 3;
17544b781cfSAndrew Turner }
17644b781cfSAndrew Turner
1777113afc8SEmmanuel Vadot for (i = 0; i < pdata->channel_count; i++) {
1787113afc8SEmmanuel Vadot XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, PBLX8,
1797113afc8SEmmanuel Vadot pblx8);
1807113afc8SEmmanuel Vadot
1817113afc8SEmmanuel Vadot if (pdata->channel[i]->tx_ring)
1827113afc8SEmmanuel Vadot XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR,
1837113afc8SEmmanuel Vadot PBL, pbl);
1847113afc8SEmmanuel Vadot
1857113afc8SEmmanuel Vadot if (pdata->channel[i]->rx_ring)
1867113afc8SEmmanuel Vadot XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR,
1877113afc8SEmmanuel Vadot PBL, pbl);
18844b781cfSAndrew Turner }
18944b781cfSAndrew Turner
1907113afc8SEmmanuel Vadot return (0);
1917113afc8SEmmanuel Vadot }
1927113afc8SEmmanuel Vadot
1937113afc8SEmmanuel Vadot static int
xgbe_config_osp_mode(struct xgbe_prv_data * pdata)1947113afc8SEmmanuel Vadot xgbe_config_osp_mode(struct xgbe_prv_data *pdata)
19544b781cfSAndrew Turner {
19644b781cfSAndrew Turner unsigned int i;
19744b781cfSAndrew Turner
1987113afc8SEmmanuel Vadot for (i = 0; i < pdata->channel_count; i++) {
1997113afc8SEmmanuel Vadot if (!pdata->channel[i]->tx_ring)
20044b781cfSAndrew Turner break;
20144b781cfSAndrew Turner
2027113afc8SEmmanuel Vadot XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, OSP,
20344b781cfSAndrew Turner pdata->tx_osp_mode);
20444b781cfSAndrew Turner }
20544b781cfSAndrew Turner
2067113afc8SEmmanuel Vadot return (0);
20744b781cfSAndrew Turner }
20844b781cfSAndrew Turner
2097113afc8SEmmanuel Vadot static int
xgbe_config_rsf_mode(struct xgbe_prv_data * pdata,unsigned int val)2107113afc8SEmmanuel Vadot xgbe_config_rsf_mode(struct xgbe_prv_data *pdata, unsigned int val)
21144b781cfSAndrew Turner {
21244b781cfSAndrew Turner unsigned int i;
21344b781cfSAndrew Turner
21444b781cfSAndrew Turner for (i = 0; i < pdata->rx_q_count; i++)
21544b781cfSAndrew Turner XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RSF, val);
21644b781cfSAndrew Turner
2177113afc8SEmmanuel Vadot return (0);
21844b781cfSAndrew Turner }
21944b781cfSAndrew Turner
2207113afc8SEmmanuel Vadot static int
xgbe_config_tsf_mode(struct xgbe_prv_data * pdata,unsigned int val)2217113afc8SEmmanuel Vadot xgbe_config_tsf_mode(struct xgbe_prv_data *pdata, unsigned int val)
22244b781cfSAndrew Turner {
22344b781cfSAndrew Turner unsigned int i;
22444b781cfSAndrew Turner
22544b781cfSAndrew Turner for (i = 0; i < pdata->tx_q_count; i++)
22644b781cfSAndrew Turner XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TSF, val);
22744b781cfSAndrew Turner
2287113afc8SEmmanuel Vadot return (0);
22944b781cfSAndrew Turner }
23044b781cfSAndrew Turner
2317113afc8SEmmanuel Vadot static int
xgbe_config_rx_threshold(struct xgbe_prv_data * pdata,unsigned int val)2327113afc8SEmmanuel Vadot xgbe_config_rx_threshold(struct xgbe_prv_data *pdata, unsigned int val)
23344b781cfSAndrew Turner {
23444b781cfSAndrew Turner unsigned int i;
23544b781cfSAndrew Turner
23644b781cfSAndrew Turner for (i = 0; i < pdata->rx_q_count; i++)
23744b781cfSAndrew Turner XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RTC, val);
23844b781cfSAndrew Turner
2397113afc8SEmmanuel Vadot return (0);
24044b781cfSAndrew Turner }
24144b781cfSAndrew Turner
2427113afc8SEmmanuel Vadot static int
xgbe_config_tx_threshold(struct xgbe_prv_data * pdata,unsigned int val)2437113afc8SEmmanuel Vadot xgbe_config_tx_threshold(struct xgbe_prv_data *pdata, unsigned int val)
24444b781cfSAndrew Turner {
24544b781cfSAndrew Turner unsigned int i;
24644b781cfSAndrew Turner
24744b781cfSAndrew Turner for (i = 0; i < pdata->tx_q_count; i++)
24844b781cfSAndrew Turner XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TTC, val);
24944b781cfSAndrew Turner
2507113afc8SEmmanuel Vadot return (0);
25144b781cfSAndrew Turner }
25244b781cfSAndrew Turner
2537113afc8SEmmanuel Vadot static int
xgbe_config_rx_coalesce(struct xgbe_prv_data * pdata)2547113afc8SEmmanuel Vadot xgbe_config_rx_coalesce(struct xgbe_prv_data *pdata)
25544b781cfSAndrew Turner {
25644b781cfSAndrew Turner unsigned int i;
25744b781cfSAndrew Turner
2587113afc8SEmmanuel Vadot for (i = 0; i < pdata->channel_count; i++) {
2597113afc8SEmmanuel Vadot if (!pdata->channel[i]->rx_ring)
26044b781cfSAndrew Turner break;
26144b781cfSAndrew Turner
2627113afc8SEmmanuel Vadot XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RIWT, RWT,
26344b781cfSAndrew Turner pdata->rx_riwt);
26444b781cfSAndrew Turner }
26544b781cfSAndrew Turner
2667113afc8SEmmanuel Vadot return (0);
26744b781cfSAndrew Turner }
26844b781cfSAndrew Turner
2697113afc8SEmmanuel Vadot static int
xgbe_config_tx_coalesce(struct xgbe_prv_data * pdata)2707113afc8SEmmanuel Vadot xgbe_config_tx_coalesce(struct xgbe_prv_data *pdata)
27144b781cfSAndrew Turner {
2727113afc8SEmmanuel Vadot return (0);
27344b781cfSAndrew Turner }
27444b781cfSAndrew Turner
2757113afc8SEmmanuel Vadot static void
xgbe_config_rx_buffer_size(struct xgbe_prv_data * pdata)2767113afc8SEmmanuel Vadot xgbe_config_rx_buffer_size(struct xgbe_prv_data *pdata)
27744b781cfSAndrew Turner {
27844b781cfSAndrew Turner unsigned int i;
27944b781cfSAndrew Turner
2807113afc8SEmmanuel Vadot for (i = 0; i < pdata->channel_count; i++) {
2817113afc8SEmmanuel Vadot if (!pdata->channel[i]->rx_ring)
28244b781cfSAndrew Turner break;
28344b781cfSAndrew Turner
2847113afc8SEmmanuel Vadot XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, RBSZ,
28544b781cfSAndrew Turner pdata->rx_buf_size);
28644b781cfSAndrew Turner }
28744b781cfSAndrew Turner }
28844b781cfSAndrew Turner
2897113afc8SEmmanuel Vadot static void
xgbe_config_tso_mode(struct xgbe_prv_data * pdata)2907113afc8SEmmanuel Vadot xgbe_config_tso_mode(struct xgbe_prv_data *pdata)
29144b781cfSAndrew Turner {
29244b781cfSAndrew Turner unsigned int i;
29344b781cfSAndrew Turner
2942968dde3SVincenzo Maffione int tso_enabled = (if_getcapenable(pdata->netdev) & IFCAP_TSO);
2952968dde3SVincenzo Maffione
2967113afc8SEmmanuel Vadot for (i = 0; i < pdata->channel_count; i++) {
2977113afc8SEmmanuel Vadot if (!pdata->channel[i]->tx_ring)
29844b781cfSAndrew Turner break;
29944b781cfSAndrew Turner
3002968dde3SVincenzo Maffione axgbe_printf(1, "TSO in channel %d %s\n", i, tso_enabled ? "enabled" : "disabled");
3012968dde3SVincenzo Maffione XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, TSE, tso_enabled ? 1 : 0);
30244b781cfSAndrew Turner }
30344b781cfSAndrew Turner }
30444b781cfSAndrew Turner
3057113afc8SEmmanuel Vadot static void
xgbe_config_sph_mode(struct xgbe_prv_data * pdata)3067113afc8SEmmanuel Vadot xgbe_config_sph_mode(struct xgbe_prv_data *pdata)
30744b781cfSAndrew Turner {
30844b781cfSAndrew Turner unsigned int i;
3092968dde3SVincenzo Maffione int sph_enable_flag = XGMAC_IOREAD_BITS(pdata, MAC_HWF1R, SPHEN);
3102968dde3SVincenzo Maffione
3112968dde3SVincenzo Maffione axgbe_printf(1, "sph_enable %d sph feature enabled?: %d\n",
3122968dde3SVincenzo Maffione pdata->sph_enable, sph_enable_flag);
3132968dde3SVincenzo Maffione
3142968dde3SVincenzo Maffione if (pdata->sph_enable && sph_enable_flag)
3152968dde3SVincenzo Maffione axgbe_printf(0, "SPH Enabled\n");
31644b781cfSAndrew Turner
3177113afc8SEmmanuel Vadot for (i = 0; i < pdata->channel_count; i++) {
3187113afc8SEmmanuel Vadot if (!pdata->channel[i]->rx_ring)
31944b781cfSAndrew Turner break;
3202968dde3SVincenzo Maffione if (pdata->sph_enable && sph_enable_flag) {
3212968dde3SVincenzo Maffione /* Enable split header feature */
3227113afc8SEmmanuel Vadot XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, SPH, 1);
3232968dde3SVincenzo Maffione } else {
3242968dde3SVincenzo Maffione /* Disable split header feature */
3252968dde3SVincenzo Maffione XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, SPH, 0);
32644b781cfSAndrew Turner }
32744b781cfSAndrew Turner
3282968dde3SVincenzo Maffione /* per-channel confirmation of SPH being disabled/enabled */
3292968dde3SVincenzo Maffione int val = XGMAC_DMA_IOREAD_BITS(pdata->channel[i], DMA_CH_CR, SPH);
3302968dde3SVincenzo Maffione axgbe_printf(0, "%s: SPH %s in channel %d\n", __func__,
3312968dde3SVincenzo Maffione (val ? "enabled" : "disabled"), i);
3322968dde3SVincenzo Maffione }
3332968dde3SVincenzo Maffione
3342968dde3SVincenzo Maffione if (pdata->sph_enable && sph_enable_flag)
33544b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_RCR, HDSMS, XGBE_SPH_HDSMS_SIZE);
33644b781cfSAndrew Turner }
33744b781cfSAndrew Turner
3387113afc8SEmmanuel Vadot static int
xgbe_write_rss_reg(struct xgbe_prv_data * pdata,unsigned int type,unsigned int index,unsigned int val)3397113afc8SEmmanuel Vadot xgbe_write_rss_reg(struct xgbe_prv_data *pdata, unsigned int type,
3407113afc8SEmmanuel Vadot unsigned int index, unsigned int val)
3417113afc8SEmmanuel Vadot {
3427113afc8SEmmanuel Vadot unsigned int wait;
3437113afc8SEmmanuel Vadot int ret = 0;
3447113afc8SEmmanuel Vadot
3457113afc8SEmmanuel Vadot mtx_lock(&pdata->rss_mutex);
3467113afc8SEmmanuel Vadot
3477113afc8SEmmanuel Vadot if (XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) {
3487113afc8SEmmanuel Vadot ret = -EBUSY;
3497113afc8SEmmanuel Vadot goto unlock;
3507113afc8SEmmanuel Vadot }
3517113afc8SEmmanuel Vadot
3527113afc8SEmmanuel Vadot XGMAC_IOWRITE(pdata, MAC_RSSDR, val);
3537113afc8SEmmanuel Vadot
3547113afc8SEmmanuel Vadot XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, RSSIA, index);
3557113afc8SEmmanuel Vadot XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, ADDRT, type);
3567113afc8SEmmanuel Vadot XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, CT, 0);
3577113afc8SEmmanuel Vadot XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, OB, 1);
3587113afc8SEmmanuel Vadot
3597113afc8SEmmanuel Vadot wait = 1000;
3607113afc8SEmmanuel Vadot while (wait--) {
3617113afc8SEmmanuel Vadot if (!XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB))
3627113afc8SEmmanuel Vadot goto unlock;
3637113afc8SEmmanuel Vadot
3647113afc8SEmmanuel Vadot DELAY(1000);
3657113afc8SEmmanuel Vadot }
3667113afc8SEmmanuel Vadot
3677113afc8SEmmanuel Vadot ret = -EBUSY;
3687113afc8SEmmanuel Vadot
3697113afc8SEmmanuel Vadot unlock:
3707113afc8SEmmanuel Vadot mtx_unlock(&pdata->rss_mutex);
3717113afc8SEmmanuel Vadot
3727113afc8SEmmanuel Vadot return (ret);
3737113afc8SEmmanuel Vadot }
3747113afc8SEmmanuel Vadot
3757113afc8SEmmanuel Vadot static int
xgbe_write_rss_hash_key(struct xgbe_prv_data * pdata)3767113afc8SEmmanuel Vadot xgbe_write_rss_hash_key(struct xgbe_prv_data *pdata)
3777113afc8SEmmanuel Vadot {
3787113afc8SEmmanuel Vadot unsigned int key_regs = sizeof(pdata->rss_key) / sizeof(uint32_t);
3797113afc8SEmmanuel Vadot unsigned int *key = (unsigned int *)&pdata->rss_key;
3807113afc8SEmmanuel Vadot int ret;
3817113afc8SEmmanuel Vadot
3827113afc8SEmmanuel Vadot while (key_regs--) {
3837113afc8SEmmanuel Vadot ret = xgbe_write_rss_reg(pdata, XGBE_RSS_HASH_KEY_TYPE,
3847113afc8SEmmanuel Vadot key_regs, *key++);
3857113afc8SEmmanuel Vadot if (ret)
3867113afc8SEmmanuel Vadot return (ret);
3877113afc8SEmmanuel Vadot }
3887113afc8SEmmanuel Vadot
3897113afc8SEmmanuel Vadot return (0);
3907113afc8SEmmanuel Vadot }
3917113afc8SEmmanuel Vadot
3927113afc8SEmmanuel Vadot static int
xgbe_write_rss_lookup_table(struct xgbe_prv_data * pdata)3937113afc8SEmmanuel Vadot xgbe_write_rss_lookup_table(struct xgbe_prv_data *pdata)
3947113afc8SEmmanuel Vadot {
3957113afc8SEmmanuel Vadot unsigned int i;
3967113afc8SEmmanuel Vadot int ret;
3977113afc8SEmmanuel Vadot
3987113afc8SEmmanuel Vadot for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) {
3997113afc8SEmmanuel Vadot ret = xgbe_write_rss_reg(pdata, XGBE_RSS_LOOKUP_TABLE_TYPE, i,
4007113afc8SEmmanuel Vadot pdata->rss_table[i]);
4017113afc8SEmmanuel Vadot if (ret)
4027113afc8SEmmanuel Vadot return (ret);
4037113afc8SEmmanuel Vadot }
4047113afc8SEmmanuel Vadot
4057113afc8SEmmanuel Vadot return (0);
4067113afc8SEmmanuel Vadot }
4077113afc8SEmmanuel Vadot
4087113afc8SEmmanuel Vadot static int
xgbe_set_rss_hash_key(struct xgbe_prv_data * pdata,const uint8_t * key)4097113afc8SEmmanuel Vadot xgbe_set_rss_hash_key(struct xgbe_prv_data *pdata, const uint8_t *key)
4107113afc8SEmmanuel Vadot {
4117113afc8SEmmanuel Vadot memcpy(pdata->rss_key, key, sizeof(pdata->rss_key));
4127113afc8SEmmanuel Vadot
4137113afc8SEmmanuel Vadot return (xgbe_write_rss_hash_key(pdata));
4147113afc8SEmmanuel Vadot }
4157113afc8SEmmanuel Vadot
4167113afc8SEmmanuel Vadot static int
xgbe_set_rss_lookup_table(struct xgbe_prv_data * pdata,const uint32_t * table)4177113afc8SEmmanuel Vadot xgbe_set_rss_lookup_table(struct xgbe_prv_data *pdata, const uint32_t *table)
4187113afc8SEmmanuel Vadot {
4197113afc8SEmmanuel Vadot unsigned int i;
4207113afc8SEmmanuel Vadot
4217113afc8SEmmanuel Vadot for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++)
4227113afc8SEmmanuel Vadot XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, table[i]);
4237113afc8SEmmanuel Vadot
4247113afc8SEmmanuel Vadot return (xgbe_write_rss_lookup_table(pdata));
4257113afc8SEmmanuel Vadot }
4267113afc8SEmmanuel Vadot
4277113afc8SEmmanuel Vadot static int
xgbe_enable_rss(struct xgbe_prv_data * pdata)4287113afc8SEmmanuel Vadot xgbe_enable_rss(struct xgbe_prv_data *pdata)
4297113afc8SEmmanuel Vadot {
4307113afc8SEmmanuel Vadot int ret;
4317113afc8SEmmanuel Vadot
4327113afc8SEmmanuel Vadot if (!pdata->hw_feat.rss)
4337113afc8SEmmanuel Vadot return (-EOPNOTSUPP);
4347113afc8SEmmanuel Vadot
4357113afc8SEmmanuel Vadot /* Program the hash key */
4367113afc8SEmmanuel Vadot ret = xgbe_write_rss_hash_key(pdata);
4377113afc8SEmmanuel Vadot if (ret)
4387113afc8SEmmanuel Vadot return (ret);
4397113afc8SEmmanuel Vadot
4407113afc8SEmmanuel Vadot /* Program the lookup table */
4417113afc8SEmmanuel Vadot ret = xgbe_write_rss_lookup_table(pdata);
4427113afc8SEmmanuel Vadot if (ret)
4437113afc8SEmmanuel Vadot return (ret);
4447113afc8SEmmanuel Vadot
4457113afc8SEmmanuel Vadot /* Set the RSS options */
4467113afc8SEmmanuel Vadot XGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options);
4477113afc8SEmmanuel Vadot
4487113afc8SEmmanuel Vadot /* Enable RSS */
4497113afc8SEmmanuel Vadot XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 1);
4507113afc8SEmmanuel Vadot
4517113afc8SEmmanuel Vadot axgbe_printf(0, "RSS Enabled\n");
4527113afc8SEmmanuel Vadot
4537113afc8SEmmanuel Vadot return (0);
4547113afc8SEmmanuel Vadot }
4557113afc8SEmmanuel Vadot
4567113afc8SEmmanuel Vadot static int
xgbe_disable_rss(struct xgbe_prv_data * pdata)4577113afc8SEmmanuel Vadot xgbe_disable_rss(struct xgbe_prv_data *pdata)
45844b781cfSAndrew Turner {
45944b781cfSAndrew Turner if (!pdata->hw_feat.rss)
4607113afc8SEmmanuel Vadot return (-EOPNOTSUPP);
46144b781cfSAndrew Turner
46244b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 0);
46344b781cfSAndrew Turner
4647113afc8SEmmanuel Vadot axgbe_printf(0, "RSS Disabled\n");
4657113afc8SEmmanuel Vadot
4667113afc8SEmmanuel Vadot return (0);
46744b781cfSAndrew Turner }
46844b781cfSAndrew Turner
4697113afc8SEmmanuel Vadot static void
xgbe_config_rss(struct xgbe_prv_data * pdata)4707113afc8SEmmanuel Vadot xgbe_config_rss(struct xgbe_prv_data *pdata)
47144b781cfSAndrew Turner {
4727113afc8SEmmanuel Vadot int ret;
47344b781cfSAndrew Turner
47444b781cfSAndrew Turner if (!pdata->hw_feat.rss)
47544b781cfSAndrew Turner return;
47644b781cfSAndrew Turner
4777113afc8SEmmanuel Vadot /* Check if the interface has RSS capability */
4787113afc8SEmmanuel Vadot if (pdata->enable_rss)
4797113afc8SEmmanuel Vadot ret = xgbe_enable_rss(pdata);
4807113afc8SEmmanuel Vadot else
4817113afc8SEmmanuel Vadot ret = xgbe_disable_rss(pdata);
4827113afc8SEmmanuel Vadot
4837113afc8SEmmanuel Vadot if (ret)
4847113afc8SEmmanuel Vadot axgbe_error("error configuring RSS, RSS disabled\n");
48544b781cfSAndrew Turner }
48644b781cfSAndrew Turner
4877113afc8SEmmanuel Vadot static int
xgbe_disable_tx_flow_control(struct xgbe_prv_data * pdata)4887113afc8SEmmanuel Vadot xgbe_disable_tx_flow_control(struct xgbe_prv_data *pdata)
48944b781cfSAndrew Turner {
49044b781cfSAndrew Turner unsigned int max_q_count, q_count;
49144b781cfSAndrew Turner unsigned int reg, reg_val;
49244b781cfSAndrew Turner unsigned int i;
49344b781cfSAndrew Turner
49444b781cfSAndrew Turner /* Clear MTL flow control */
49544b781cfSAndrew Turner for (i = 0; i < pdata->rx_q_count; i++)
49644b781cfSAndrew Turner XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 0);
49744b781cfSAndrew Turner
49844b781cfSAndrew Turner /* Clear MAC flow control */
49944b781cfSAndrew Turner max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES;
50044b781cfSAndrew Turner q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count);
50144b781cfSAndrew Turner reg = MAC_Q0TFCR;
50244b781cfSAndrew Turner for (i = 0; i < q_count; i++) {
50344b781cfSAndrew Turner reg_val = XGMAC_IOREAD(pdata, reg);
50444b781cfSAndrew Turner XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 0);
50544b781cfSAndrew Turner XGMAC_IOWRITE(pdata, reg, reg_val);
50644b781cfSAndrew Turner
50744b781cfSAndrew Turner reg += MAC_QTFCR_INC;
50844b781cfSAndrew Turner }
50944b781cfSAndrew Turner
5107113afc8SEmmanuel Vadot return (0);
51144b781cfSAndrew Turner }
51244b781cfSAndrew Turner
5137113afc8SEmmanuel Vadot static int
xgbe_enable_tx_flow_control(struct xgbe_prv_data * pdata)5147113afc8SEmmanuel Vadot xgbe_enable_tx_flow_control(struct xgbe_prv_data *pdata)
51544b781cfSAndrew Turner {
51644b781cfSAndrew Turner unsigned int max_q_count, q_count;
51744b781cfSAndrew Turner unsigned int reg, reg_val;
51844b781cfSAndrew Turner unsigned int i;
51944b781cfSAndrew Turner
52044b781cfSAndrew Turner /* Set MTL flow control */
52144b781cfSAndrew Turner for (i = 0; i < pdata->rx_q_count; i++) {
5227113afc8SEmmanuel Vadot unsigned int ehfc = 0;
5237113afc8SEmmanuel Vadot
5247113afc8SEmmanuel Vadot if (pdata->rx_rfd[i]) {
5257113afc8SEmmanuel Vadot /* Flow control thresholds are established */
5267113afc8SEmmanuel Vadot /* TODO - enable pfc/ets support */
5277113afc8SEmmanuel Vadot ehfc = 1;
5287113afc8SEmmanuel Vadot }
5297113afc8SEmmanuel Vadot
5307113afc8SEmmanuel Vadot XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, ehfc);
5317113afc8SEmmanuel Vadot
5327113afc8SEmmanuel Vadot axgbe_printf(1, "flow control %s for RXq%u\n",
5337113afc8SEmmanuel Vadot ehfc ? "enabled" : "disabled", i);
53444b781cfSAndrew Turner }
53544b781cfSAndrew Turner
53644b781cfSAndrew Turner /* Set MAC flow control */
53744b781cfSAndrew Turner max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES;
53844b781cfSAndrew Turner q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count);
53944b781cfSAndrew Turner reg = MAC_Q0TFCR;
54044b781cfSAndrew Turner for (i = 0; i < q_count; i++) {
54144b781cfSAndrew Turner reg_val = XGMAC_IOREAD(pdata, reg);
54244b781cfSAndrew Turner
54344b781cfSAndrew Turner /* Enable transmit flow control */
54444b781cfSAndrew Turner XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 1);
5457113afc8SEmmanuel Vadot
54644b781cfSAndrew Turner /* Set pause time */
54744b781cfSAndrew Turner XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, 0xffff);
54844b781cfSAndrew Turner
54944b781cfSAndrew Turner XGMAC_IOWRITE(pdata, reg, reg_val);
55044b781cfSAndrew Turner
55144b781cfSAndrew Turner reg += MAC_QTFCR_INC;
55244b781cfSAndrew Turner }
55344b781cfSAndrew Turner
5547113afc8SEmmanuel Vadot return (0);
55544b781cfSAndrew Turner }
55644b781cfSAndrew Turner
5577113afc8SEmmanuel Vadot static int
xgbe_disable_rx_flow_control(struct xgbe_prv_data * pdata)5587113afc8SEmmanuel Vadot xgbe_disable_rx_flow_control(struct xgbe_prv_data *pdata)
55944b781cfSAndrew Turner {
56044b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 0);
56144b781cfSAndrew Turner
5627113afc8SEmmanuel Vadot return (0);
56344b781cfSAndrew Turner }
56444b781cfSAndrew Turner
5657113afc8SEmmanuel Vadot static int
xgbe_enable_rx_flow_control(struct xgbe_prv_data * pdata)5667113afc8SEmmanuel Vadot xgbe_enable_rx_flow_control(struct xgbe_prv_data *pdata)
56744b781cfSAndrew Turner {
56844b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 1);
56944b781cfSAndrew Turner
5707113afc8SEmmanuel Vadot return (0);
57144b781cfSAndrew Turner }
57244b781cfSAndrew Turner
5737113afc8SEmmanuel Vadot static int
xgbe_config_tx_flow_control(struct xgbe_prv_data * pdata)5747113afc8SEmmanuel Vadot xgbe_config_tx_flow_control(struct xgbe_prv_data *pdata)
57544b781cfSAndrew Turner {
5769c6d6488SAndrew Turner if (pdata->tx_pause)
57744b781cfSAndrew Turner xgbe_enable_tx_flow_control(pdata);
57844b781cfSAndrew Turner else
57944b781cfSAndrew Turner xgbe_disable_tx_flow_control(pdata);
58044b781cfSAndrew Turner
5817113afc8SEmmanuel Vadot return (0);
58244b781cfSAndrew Turner }
58344b781cfSAndrew Turner
5847113afc8SEmmanuel Vadot static int
xgbe_config_rx_flow_control(struct xgbe_prv_data * pdata)5857113afc8SEmmanuel Vadot xgbe_config_rx_flow_control(struct xgbe_prv_data *pdata)
58644b781cfSAndrew Turner {
5879c6d6488SAndrew Turner if (pdata->rx_pause)
58844b781cfSAndrew Turner xgbe_enable_rx_flow_control(pdata);
58944b781cfSAndrew Turner else
59044b781cfSAndrew Turner xgbe_disable_rx_flow_control(pdata);
59144b781cfSAndrew Turner
5927113afc8SEmmanuel Vadot return (0);
59344b781cfSAndrew Turner }
59444b781cfSAndrew Turner
5957113afc8SEmmanuel Vadot static void
xgbe_config_flow_control(struct xgbe_prv_data * pdata)5967113afc8SEmmanuel Vadot xgbe_config_flow_control(struct xgbe_prv_data *pdata)
59744b781cfSAndrew Turner {
59844b781cfSAndrew Turner xgbe_config_tx_flow_control(pdata);
59944b781cfSAndrew Turner xgbe_config_rx_flow_control(pdata);
60044b781cfSAndrew Turner
6019c6d6488SAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0);
60244b781cfSAndrew Turner }
60344b781cfSAndrew Turner
6047113afc8SEmmanuel Vadot static void
xgbe_enable_dma_interrupts(struct xgbe_prv_data * pdata)6057113afc8SEmmanuel Vadot xgbe_enable_dma_interrupts(struct xgbe_prv_data *pdata)
60644b781cfSAndrew Turner {
60744b781cfSAndrew Turner struct xgbe_channel *channel;
6087113afc8SEmmanuel Vadot unsigned int i, ver;
60944b781cfSAndrew Turner
6107113afc8SEmmanuel Vadot /* Set the interrupt mode if supported */
6117113afc8SEmmanuel Vadot if (pdata->channel_irq_mode)
6127113afc8SEmmanuel Vadot XGMAC_IOWRITE_BITS(pdata, DMA_MR, INTM,
6137113afc8SEmmanuel Vadot pdata->channel_irq_mode);
6147113afc8SEmmanuel Vadot
6157113afc8SEmmanuel Vadot ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER);
6167113afc8SEmmanuel Vadot
6177113afc8SEmmanuel Vadot for (i = 0; i < pdata->channel_count; i++) {
6187113afc8SEmmanuel Vadot channel = pdata->channel[i];
6197113afc8SEmmanuel Vadot
62044b781cfSAndrew Turner /* Clear all the interrupts which are set */
6217113afc8SEmmanuel Vadot XGMAC_DMA_IOWRITE(channel, DMA_CH_SR,
6227113afc8SEmmanuel Vadot XGMAC_DMA_IOREAD(channel, DMA_CH_SR));
62344b781cfSAndrew Turner
62444b781cfSAndrew Turner /* Clear all interrupt enable bits */
6257113afc8SEmmanuel Vadot channel->curr_ier = 0;
62644b781cfSAndrew Turner
62744b781cfSAndrew Turner /* Enable following interrupts
62844b781cfSAndrew Turner * NIE - Normal Interrupt Summary Enable
62944b781cfSAndrew Turner * AIE - Abnormal Interrupt Summary Enable
63044b781cfSAndrew Turner * FBEE - Fatal Bus Error Enable
63144b781cfSAndrew Turner */
6327113afc8SEmmanuel Vadot if (ver < 0x21) {
6337113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, NIE20, 1);
6347113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, AIE20, 1);
6357113afc8SEmmanuel Vadot } else {
6367113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, NIE, 1);
6377113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, AIE, 1);
6387113afc8SEmmanuel Vadot }
6397113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 1);
64044b781cfSAndrew Turner
64144b781cfSAndrew Turner if (channel->tx_ring) {
64244b781cfSAndrew Turner /* Enable the following Tx interrupts
64344b781cfSAndrew Turner * TIE - Transmit Interrupt Enable (unless using
6447113afc8SEmmanuel Vadot * per channel interrupts in edge triggered
6457113afc8SEmmanuel Vadot * mode)
64644b781cfSAndrew Turner */
6477113afc8SEmmanuel Vadot if (!pdata->per_channel_irq || pdata->channel_irq_mode)
6487113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier,
6497113afc8SEmmanuel Vadot DMA_CH_IER, TIE, 1);
65044b781cfSAndrew Turner }
65144b781cfSAndrew Turner if (channel->rx_ring) {
65244b781cfSAndrew Turner /* Enable following Rx interrupts
65344b781cfSAndrew Turner * RBUE - Receive Buffer Unavailable Enable
65444b781cfSAndrew Turner * RIE - Receive Interrupt Enable (unless using
6557113afc8SEmmanuel Vadot * per channel interrupts in edge triggered
6567113afc8SEmmanuel Vadot * mode)
65744b781cfSAndrew Turner */
6587113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 1);
6597113afc8SEmmanuel Vadot if (!pdata->per_channel_irq || pdata->channel_irq_mode)
6607113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier,
6617113afc8SEmmanuel Vadot DMA_CH_IER, RIE, 1);
66244b781cfSAndrew Turner }
66344b781cfSAndrew Turner
6647113afc8SEmmanuel Vadot XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, channel->curr_ier);
66544b781cfSAndrew Turner }
66644b781cfSAndrew Turner }
66744b781cfSAndrew Turner
6687113afc8SEmmanuel Vadot static void
xgbe_enable_mtl_interrupts(struct xgbe_prv_data * pdata)6697113afc8SEmmanuel Vadot xgbe_enable_mtl_interrupts(struct xgbe_prv_data *pdata)
67044b781cfSAndrew Turner {
67144b781cfSAndrew Turner unsigned int mtl_q_isr;
67244b781cfSAndrew Turner unsigned int q_count, i;
67344b781cfSAndrew Turner
67444b781cfSAndrew Turner q_count = max(pdata->hw_feat.tx_q_cnt, pdata->hw_feat.rx_q_cnt);
67544b781cfSAndrew Turner for (i = 0; i < q_count; i++) {
67644b781cfSAndrew Turner /* Clear all the interrupts which are set */
67744b781cfSAndrew Turner mtl_q_isr = XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR);
67844b781cfSAndrew Turner XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_ISR, mtl_q_isr);
67944b781cfSAndrew Turner
68044b781cfSAndrew Turner /* No MTL interrupts to be enabled */
68144b781cfSAndrew Turner XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_IER, 0);
68244b781cfSAndrew Turner }
68344b781cfSAndrew Turner }
68444b781cfSAndrew Turner
6857113afc8SEmmanuel Vadot static void
xgbe_enable_mac_interrupts(struct xgbe_prv_data * pdata)6867113afc8SEmmanuel Vadot xgbe_enable_mac_interrupts(struct xgbe_prv_data *pdata)
68744b781cfSAndrew Turner {
68844b781cfSAndrew Turner unsigned int mac_ier = 0;
68944b781cfSAndrew Turner
69044b781cfSAndrew Turner /* Enable Timestamp interrupt */
69144b781cfSAndrew Turner XGMAC_SET_BITS(mac_ier, MAC_IER, TSIE, 1);
69244b781cfSAndrew Turner
69344b781cfSAndrew Turner XGMAC_IOWRITE(pdata, MAC_IER, mac_ier);
69444b781cfSAndrew Turner
69544b781cfSAndrew Turner /* Enable all counter interrupts */
69644b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MMC_RIER, ALL_INTERRUPTS, 0xffffffff);
69744b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MMC_TIER, ALL_INTERRUPTS, 0xffffffff);
6987113afc8SEmmanuel Vadot
6997113afc8SEmmanuel Vadot /* Enable MDIO single command completion interrupt */
7007113afc8SEmmanuel Vadot XGMAC_IOWRITE_BITS(pdata, MAC_MDIOIER, SNGLCOMPIE, 1);
70144b781cfSAndrew Turner }
70244b781cfSAndrew Turner
7037113afc8SEmmanuel Vadot static int
xgbe_set_speed(struct xgbe_prv_data * pdata,int speed)7047113afc8SEmmanuel Vadot xgbe_set_speed(struct xgbe_prv_data *pdata, int speed)
70544b781cfSAndrew Turner {
7067113afc8SEmmanuel Vadot unsigned int ss;
70744b781cfSAndrew Turner
7087113afc8SEmmanuel Vadot switch (speed) {
7097113afc8SEmmanuel Vadot case SPEED_1000:
7107113afc8SEmmanuel Vadot ss = 0x03;
7117113afc8SEmmanuel Vadot break;
7127113afc8SEmmanuel Vadot case SPEED_2500:
7137113afc8SEmmanuel Vadot ss = 0x02;
7147113afc8SEmmanuel Vadot break;
7157113afc8SEmmanuel Vadot case SPEED_10000:
7167113afc8SEmmanuel Vadot ss = 0x00;
7177113afc8SEmmanuel Vadot break;
7187113afc8SEmmanuel Vadot default:
7197113afc8SEmmanuel Vadot return (-EINVAL);
72044b781cfSAndrew Turner }
72144b781cfSAndrew Turner
7227113afc8SEmmanuel Vadot if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) != ss)
7237113afc8SEmmanuel Vadot XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, ss);
72444b781cfSAndrew Turner
7257113afc8SEmmanuel Vadot return (0);
72644b781cfSAndrew Turner }
72744b781cfSAndrew Turner
7287113afc8SEmmanuel Vadot static int
xgbe_enable_rx_vlan_stripping(struct xgbe_prv_data * pdata)7297113afc8SEmmanuel Vadot xgbe_enable_rx_vlan_stripping(struct xgbe_prv_data *pdata)
73044b781cfSAndrew Turner {
73144b781cfSAndrew Turner /* Put the VLAN tag in the Rx descriptor */
73244b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLRXS, 1);
73344b781cfSAndrew Turner
73444b781cfSAndrew Turner /* Don't check the VLAN type */
73544b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, DOVLTC, 1);
73644b781cfSAndrew Turner
73744b781cfSAndrew Turner /* Check only C-TAG (0x8100) packets */
73844b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERSVLM, 0);
73944b781cfSAndrew Turner
74044b781cfSAndrew Turner /* Don't consider an S-TAG (0x88A8) packet as a VLAN packet */
74144b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ESVL, 0);
74244b781cfSAndrew Turner
74344b781cfSAndrew Turner /* Enable VLAN tag stripping */
74444b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0x3);
74544b781cfSAndrew Turner
7467113afc8SEmmanuel Vadot axgbe_printf(0, "VLAN Stripping Enabled\n");
7477113afc8SEmmanuel Vadot
7487113afc8SEmmanuel Vadot return (0);
74944b781cfSAndrew Turner }
75044b781cfSAndrew Turner
7517113afc8SEmmanuel Vadot static int
xgbe_disable_rx_vlan_stripping(struct xgbe_prv_data * pdata)7527113afc8SEmmanuel Vadot xgbe_disable_rx_vlan_stripping(struct xgbe_prv_data *pdata)
75344b781cfSAndrew Turner {
75444b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0);
75544b781cfSAndrew Turner
7567113afc8SEmmanuel Vadot axgbe_printf(0, "VLAN Stripping Disabled\n");
7577113afc8SEmmanuel Vadot
7587113afc8SEmmanuel Vadot return (0);
75944b781cfSAndrew Turner }
76044b781cfSAndrew Turner
7617113afc8SEmmanuel Vadot static int
xgbe_enable_rx_vlan_filtering(struct xgbe_prv_data * pdata)7627113afc8SEmmanuel Vadot xgbe_enable_rx_vlan_filtering(struct xgbe_prv_data *pdata)
76344b781cfSAndrew Turner {
76444b781cfSAndrew Turner /* Enable VLAN filtering */
76544b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1);
76644b781cfSAndrew Turner
76744b781cfSAndrew Turner /* Enable VLAN Hash Table filtering */
76844b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTHM, 1);
76944b781cfSAndrew Turner
77044b781cfSAndrew Turner /* Disable VLAN tag inverse matching */
77144b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTIM, 0);
77244b781cfSAndrew Turner
77344b781cfSAndrew Turner /* Only filter on the lower 12-bits of the VLAN tag */
77444b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ETV, 1);
77544b781cfSAndrew Turner
77644b781cfSAndrew Turner /* In order for the VLAN Hash Table filtering to be effective,
77744b781cfSAndrew Turner * the VLAN tag identifier in the VLAN Tag Register must not
77844b781cfSAndrew Turner * be zero. Set the VLAN tag identifier to "1" to enable the
77944b781cfSAndrew Turner * VLAN Hash Table filtering. This implies that a VLAN tag of
78044b781cfSAndrew Turner * 1 will always pass filtering.
78144b781cfSAndrew Turner */
78244b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VL, 1);
78344b781cfSAndrew Turner
7847113afc8SEmmanuel Vadot axgbe_printf(0, "VLAN filtering Enabled\n");
7857113afc8SEmmanuel Vadot
7867113afc8SEmmanuel Vadot return (0);
78744b781cfSAndrew Turner }
78844b781cfSAndrew Turner
7897113afc8SEmmanuel Vadot static int
xgbe_disable_rx_vlan_filtering(struct xgbe_prv_data * pdata)7907113afc8SEmmanuel Vadot xgbe_disable_rx_vlan_filtering(struct xgbe_prv_data *pdata)
79144b781cfSAndrew Turner {
79244b781cfSAndrew Turner /* Disable VLAN filtering */
79344b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0);
79444b781cfSAndrew Turner
7957113afc8SEmmanuel Vadot axgbe_printf(0, "VLAN filtering Disabled\n");
7967113afc8SEmmanuel Vadot
7977113afc8SEmmanuel Vadot return (0);
79844b781cfSAndrew Turner }
79944b781cfSAndrew Turner
8007113afc8SEmmanuel Vadot static uint32_t
xgbe_vid_crc32_le(__le16 vid_le)8017113afc8SEmmanuel Vadot xgbe_vid_crc32_le(__le16 vid_le)
80244b781cfSAndrew Turner {
8037113afc8SEmmanuel Vadot uint32_t crc = ~0;
8047113afc8SEmmanuel Vadot uint32_t temp = 0;
8057113afc8SEmmanuel Vadot unsigned char *data = (unsigned char *)&vid_le;
8067113afc8SEmmanuel Vadot unsigned char data_byte = 0;
8077113afc8SEmmanuel Vadot int i, bits;
8087113afc8SEmmanuel Vadot
8097113afc8SEmmanuel Vadot bits = get_bitmask_order(VLAN_VID_MASK);
8107113afc8SEmmanuel Vadot for (i = 0; i < bits; i++) {
8117113afc8SEmmanuel Vadot if ((i % 8) == 0)
8127113afc8SEmmanuel Vadot data_byte = data[i / 8];
8137113afc8SEmmanuel Vadot
8147113afc8SEmmanuel Vadot temp = ((crc & 1) ^ data_byte) & 1;
8157113afc8SEmmanuel Vadot crc >>= 1;
8167113afc8SEmmanuel Vadot data_byte >>= 1;
8177113afc8SEmmanuel Vadot
8187113afc8SEmmanuel Vadot if (temp)
8197113afc8SEmmanuel Vadot crc ^= CRC32_POLY_LE;
8207113afc8SEmmanuel Vadot }
8217113afc8SEmmanuel Vadot
8227113afc8SEmmanuel Vadot return (crc);
8237113afc8SEmmanuel Vadot }
8247113afc8SEmmanuel Vadot
8257113afc8SEmmanuel Vadot static int
xgbe_update_vlan_hash_table(struct xgbe_prv_data * pdata)8267113afc8SEmmanuel Vadot xgbe_update_vlan_hash_table(struct xgbe_prv_data *pdata)
8277113afc8SEmmanuel Vadot {
8287113afc8SEmmanuel Vadot uint32_t crc;
8297113afc8SEmmanuel Vadot uint16_t vid;
8307113afc8SEmmanuel Vadot uint16_t vlan_hash_table = 0;
8317113afc8SEmmanuel Vadot __le16 vid_le = 0;
8327113afc8SEmmanuel Vadot
8337113afc8SEmmanuel Vadot axgbe_printf(1, "%s: Before updating VLANHTR 0x%x\n", __func__,
8347113afc8SEmmanuel Vadot XGMAC_IOREAD(pdata, MAC_VLANHTR));
8357113afc8SEmmanuel Vadot
8367113afc8SEmmanuel Vadot /* Generate the VLAN Hash Table value */
8377113afc8SEmmanuel Vadot for_each_set_bit(vid, pdata->active_vlans, VLAN_NVID) {
8387113afc8SEmmanuel Vadot
8397113afc8SEmmanuel Vadot /* Get the CRC32 value of the VLAN ID */
8407113afc8SEmmanuel Vadot vid_le = cpu_to_le16(vid);
8417113afc8SEmmanuel Vadot crc = bitrev32(~xgbe_vid_crc32_le(vid_le)) >> 28;
8427113afc8SEmmanuel Vadot
8437113afc8SEmmanuel Vadot vlan_hash_table |= (1 << crc);
8447113afc8SEmmanuel Vadot axgbe_printf(1, "%s: vid 0x%x vid_le 0x%x crc 0x%x "
8457113afc8SEmmanuel Vadot "vlan_hash_table 0x%x\n", __func__, vid, vid_le, crc,
8467113afc8SEmmanuel Vadot vlan_hash_table);
8477113afc8SEmmanuel Vadot }
84844b781cfSAndrew Turner
84944b781cfSAndrew Turner /* Set the VLAN Hash Table filtering register */
85044b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_VLANHTR, VLHT, vlan_hash_table);
85144b781cfSAndrew Turner
8527113afc8SEmmanuel Vadot axgbe_printf(1, "%s: After updating VLANHTR 0x%x\n", __func__,
8537113afc8SEmmanuel Vadot XGMAC_IOREAD(pdata, MAC_VLANHTR));
8547113afc8SEmmanuel Vadot
8557113afc8SEmmanuel Vadot return (0);
85644b781cfSAndrew Turner }
85744b781cfSAndrew Turner
8587113afc8SEmmanuel Vadot static int
xgbe_set_promiscuous_mode(struct xgbe_prv_data * pdata,unsigned int enable)8597113afc8SEmmanuel Vadot xgbe_set_promiscuous_mode(struct xgbe_prv_data *pdata, unsigned int enable)
86044b781cfSAndrew Turner {
86144b781cfSAndrew Turner unsigned int val = enable ? 1 : 0;
86244b781cfSAndrew Turner
86344b781cfSAndrew Turner if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == val)
8647113afc8SEmmanuel Vadot return (0);
8657113afc8SEmmanuel Vadot
8667113afc8SEmmanuel Vadot axgbe_printf(1, "%s promiscous mode\n", enable? "entering" : "leaving");
86744b781cfSAndrew Turner
86844b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, val);
86944b781cfSAndrew Turner
87044b781cfSAndrew Turner /* Hardware will still perform VLAN filtering in promiscuous mode */
8717113afc8SEmmanuel Vadot if (enable) {
8727113afc8SEmmanuel Vadot axgbe_printf(1, "Disabling rx vlan filtering\n");
87344b781cfSAndrew Turner xgbe_disable_rx_vlan_filtering(pdata);
8747113afc8SEmmanuel Vadot } else {
8757113afc8SEmmanuel Vadot if ((if_getcapenable(pdata->netdev) & IFCAP_VLAN_HWFILTER)) {
8767113afc8SEmmanuel Vadot axgbe_printf(1, "Enabling rx vlan filtering\n");
8777113afc8SEmmanuel Vadot xgbe_enable_rx_vlan_filtering(pdata);
8787113afc8SEmmanuel Vadot }
87944b781cfSAndrew Turner }
88044b781cfSAndrew Turner
8817113afc8SEmmanuel Vadot return (0);
8827113afc8SEmmanuel Vadot }
8837113afc8SEmmanuel Vadot
8847113afc8SEmmanuel Vadot static int
xgbe_set_all_multicast_mode(struct xgbe_prv_data * pdata,unsigned int enable)8857113afc8SEmmanuel Vadot xgbe_set_all_multicast_mode(struct xgbe_prv_data *pdata, unsigned int enable)
88644b781cfSAndrew Turner {
88744b781cfSAndrew Turner unsigned int val = enable ? 1 : 0;
88844b781cfSAndrew Turner
88944b781cfSAndrew Turner if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PM) == val)
8907113afc8SEmmanuel Vadot return (0);
89144b781cfSAndrew Turner
8927113afc8SEmmanuel Vadot axgbe_printf(1,"%s allmulti mode\n", enable ? "entering" : "leaving");
89344b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, val);
89444b781cfSAndrew Turner
8957113afc8SEmmanuel Vadot return (0);
89644b781cfSAndrew Turner }
89744b781cfSAndrew Turner
8987113afc8SEmmanuel Vadot static void
xgbe_set_mac_reg(struct xgbe_prv_data * pdata,char * addr,unsigned int * mac_reg)8997113afc8SEmmanuel Vadot xgbe_set_mac_reg(struct xgbe_prv_data *pdata, char *addr, unsigned int *mac_reg)
90044b781cfSAndrew Turner {
90144b781cfSAndrew Turner unsigned int mac_addr_hi, mac_addr_lo;
9027113afc8SEmmanuel Vadot uint8_t *mac_addr;
90344b781cfSAndrew Turner
90444b781cfSAndrew Turner mac_addr_lo = 0;
90544b781cfSAndrew Turner mac_addr_hi = 0;
90644b781cfSAndrew Turner
9079c6d6488SAndrew Turner if (addr) {
9087113afc8SEmmanuel Vadot mac_addr = (uint8_t *)&mac_addr_lo;
9099c6d6488SAndrew Turner mac_addr[0] = addr[0];
9109c6d6488SAndrew Turner mac_addr[1] = addr[1];
9119c6d6488SAndrew Turner mac_addr[2] = addr[2];
9129c6d6488SAndrew Turner mac_addr[3] = addr[3];
9137113afc8SEmmanuel Vadot mac_addr = (uint8_t *)&mac_addr_hi;
9149c6d6488SAndrew Turner mac_addr[0] = addr[4];
9159c6d6488SAndrew Turner mac_addr[1] = addr[5];
91644b781cfSAndrew Turner
9177113afc8SEmmanuel Vadot axgbe_printf(1, "adding mac address %pM at %#x\n", addr, *mac_reg);
9187113afc8SEmmanuel Vadot
91944b781cfSAndrew Turner XGMAC_SET_BITS(mac_addr_hi, MAC_MACA1HR, AE, 1);
92044b781cfSAndrew Turner }
92144b781cfSAndrew Turner
92244b781cfSAndrew Turner XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_hi);
92344b781cfSAndrew Turner *mac_reg += MAC_MACA_INC;
92444b781cfSAndrew Turner XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_lo);
92544b781cfSAndrew Turner *mac_reg += MAC_MACA_INC;
92644b781cfSAndrew Turner }
92744b781cfSAndrew Turner
9287113afc8SEmmanuel Vadot static void
xgbe_set_mac_addn_addrs(struct xgbe_prv_data * pdata)9297113afc8SEmmanuel Vadot xgbe_set_mac_addn_addrs(struct xgbe_prv_data *pdata)
93044b781cfSAndrew Turner {
93144b781cfSAndrew Turner unsigned int mac_reg;
93244b781cfSAndrew Turner unsigned int addn_macs;
93344b781cfSAndrew Turner
93444b781cfSAndrew Turner mac_reg = MAC_MACA1HR;
93544b781cfSAndrew Turner addn_macs = pdata->hw_feat.addn_mac;
93644b781cfSAndrew Turner
9379c6d6488SAndrew Turner xgbe_set_mac_reg(pdata, pdata->mac_addr, &mac_reg);
93844b781cfSAndrew Turner addn_macs--;
93944b781cfSAndrew Turner
94044b781cfSAndrew Turner /* Clear remaining additional MAC address entries */
94144b781cfSAndrew Turner while (addn_macs--)
94244b781cfSAndrew Turner xgbe_set_mac_reg(pdata, NULL, &mac_reg);
94344b781cfSAndrew Turner }
94444b781cfSAndrew Turner
9457113afc8SEmmanuel Vadot static int
xgbe_add_mac_addresses(struct xgbe_prv_data * pdata)9467113afc8SEmmanuel Vadot xgbe_add_mac_addresses(struct xgbe_prv_data *pdata)
94744b781cfSAndrew Turner {
9487113afc8SEmmanuel Vadot /* TODO - add support to set mac hash table */
94944b781cfSAndrew Turner xgbe_set_mac_addn_addrs(pdata);
95044b781cfSAndrew Turner
9517113afc8SEmmanuel Vadot return (0);
95244b781cfSAndrew Turner }
95344b781cfSAndrew Turner
9547113afc8SEmmanuel Vadot static int
xgbe_set_mac_address(struct xgbe_prv_data * pdata,uint8_t * addr)9557113afc8SEmmanuel Vadot xgbe_set_mac_address(struct xgbe_prv_data *pdata, uint8_t *addr)
95644b781cfSAndrew Turner {
95744b781cfSAndrew Turner unsigned int mac_addr_hi, mac_addr_lo;
95844b781cfSAndrew Turner
95944b781cfSAndrew Turner mac_addr_hi = (addr[5] << 8) | (addr[4] << 0);
96044b781cfSAndrew Turner mac_addr_lo = (addr[3] << 24) | (addr[2] << 16) |
96144b781cfSAndrew Turner (addr[1] << 8) | (addr[0] << 0);
96244b781cfSAndrew Turner
96344b781cfSAndrew Turner XGMAC_IOWRITE(pdata, MAC_MACA0HR, mac_addr_hi);
96444b781cfSAndrew Turner XGMAC_IOWRITE(pdata, MAC_MACA0LR, mac_addr_lo);
96544b781cfSAndrew Turner
9667113afc8SEmmanuel Vadot return (0);
96744b781cfSAndrew Turner }
96844b781cfSAndrew Turner
9697113afc8SEmmanuel Vadot static int
xgbe_config_rx_mode(struct xgbe_prv_data * pdata)9707113afc8SEmmanuel Vadot xgbe_config_rx_mode(struct xgbe_prv_data *pdata)
97144b781cfSAndrew Turner {
97244b781cfSAndrew Turner unsigned int pr_mode, am_mode;
97344b781cfSAndrew Turner
97468b47dcbSJustin Hibbits pr_mode = ((if_getflags(pdata->netdev) & IFF_PPROMISC) != 0);
97568b47dcbSJustin Hibbits am_mode = ((if_getflags(pdata->netdev) & IFF_ALLMULTI) != 0);
97644b781cfSAndrew Turner
97744b781cfSAndrew Turner xgbe_set_promiscuous_mode(pdata, pr_mode);
97844b781cfSAndrew Turner xgbe_set_all_multicast_mode(pdata, am_mode);
97944b781cfSAndrew Turner
98044b781cfSAndrew Turner xgbe_add_mac_addresses(pdata);
98144b781cfSAndrew Turner
9827113afc8SEmmanuel Vadot return (0);
98344b781cfSAndrew Turner }
98444b781cfSAndrew Turner
9857113afc8SEmmanuel Vadot static int
xgbe_clr_gpio(struct xgbe_prv_data * pdata,unsigned int gpio)9867113afc8SEmmanuel Vadot xgbe_clr_gpio(struct xgbe_prv_data *pdata, unsigned int gpio)
9877113afc8SEmmanuel Vadot {
9887113afc8SEmmanuel Vadot unsigned int reg;
9897113afc8SEmmanuel Vadot
9907113afc8SEmmanuel Vadot if (gpio > 15)
9917113afc8SEmmanuel Vadot return (-EINVAL);
9927113afc8SEmmanuel Vadot
9937113afc8SEmmanuel Vadot reg = XGMAC_IOREAD(pdata, MAC_GPIOSR);
9947113afc8SEmmanuel Vadot
9957113afc8SEmmanuel Vadot reg &= ~(1 << (gpio + 16));
9967113afc8SEmmanuel Vadot XGMAC_IOWRITE(pdata, MAC_GPIOSR, reg);
9977113afc8SEmmanuel Vadot
9987113afc8SEmmanuel Vadot return (0);
9997113afc8SEmmanuel Vadot }
10007113afc8SEmmanuel Vadot
10017113afc8SEmmanuel Vadot static int
xgbe_set_gpio(struct xgbe_prv_data * pdata,unsigned int gpio)10027113afc8SEmmanuel Vadot xgbe_set_gpio(struct xgbe_prv_data *pdata, unsigned int gpio)
10037113afc8SEmmanuel Vadot {
10047113afc8SEmmanuel Vadot unsigned int reg;
10057113afc8SEmmanuel Vadot
10067113afc8SEmmanuel Vadot if (gpio > 15)
10077113afc8SEmmanuel Vadot return (-EINVAL);
10087113afc8SEmmanuel Vadot
10097113afc8SEmmanuel Vadot reg = XGMAC_IOREAD(pdata, MAC_GPIOSR);
10107113afc8SEmmanuel Vadot
10117113afc8SEmmanuel Vadot reg |= (1 << (gpio + 16));
10127113afc8SEmmanuel Vadot XGMAC_IOWRITE(pdata, MAC_GPIOSR, reg);
10137113afc8SEmmanuel Vadot
10147113afc8SEmmanuel Vadot return (0);
10157113afc8SEmmanuel Vadot }
10167113afc8SEmmanuel Vadot
10177113afc8SEmmanuel Vadot static int
xgbe_read_mmd_regs_v2(struct xgbe_prv_data * pdata,int prtad,int mmd_reg)10187113afc8SEmmanuel Vadot xgbe_read_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad, int mmd_reg)
10197113afc8SEmmanuel Vadot {
10207113afc8SEmmanuel Vadot unsigned long flags;
10217113afc8SEmmanuel Vadot unsigned int mmd_address, index, offset;
10227113afc8SEmmanuel Vadot int mmd_data;
10237113afc8SEmmanuel Vadot
10247113afc8SEmmanuel Vadot if (mmd_reg & MII_ADDR_C45)
10257113afc8SEmmanuel Vadot mmd_address = mmd_reg & ~MII_ADDR_C45;
10267113afc8SEmmanuel Vadot else
10277113afc8SEmmanuel Vadot mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
10287113afc8SEmmanuel Vadot
10297113afc8SEmmanuel Vadot /* The PCS registers are accessed using mmio. The underlying
10307113afc8SEmmanuel Vadot * management interface uses indirect addressing to access the MMD
10317113afc8SEmmanuel Vadot * register sets. This requires accessing of the PCS register in two
10327113afc8SEmmanuel Vadot * phases, an address phase and a data phase.
10337113afc8SEmmanuel Vadot *
10347113afc8SEmmanuel Vadot * The mmio interface is based on 16-bit offsets and values. All
10357113afc8SEmmanuel Vadot * register offsets must therefore be adjusted by left shifting the
10367113afc8SEmmanuel Vadot * offset 1 bit and reading 16 bits of data.
10377113afc8SEmmanuel Vadot */
10387113afc8SEmmanuel Vadot mmd_address <<= 1;
10397113afc8SEmmanuel Vadot index = mmd_address & ~pdata->xpcs_window_mask;
10407113afc8SEmmanuel Vadot offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask);
10417113afc8SEmmanuel Vadot
10427113afc8SEmmanuel Vadot spin_lock_irqsave(&pdata->xpcs_lock, flags);
10437113afc8SEmmanuel Vadot XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index);
10447113afc8SEmmanuel Vadot mmd_data = XPCS16_IOREAD(pdata, offset);
10457113afc8SEmmanuel Vadot spin_unlock_irqrestore(&pdata->xpcs_lock, flags);
10467113afc8SEmmanuel Vadot
10477113afc8SEmmanuel Vadot return (mmd_data);
10487113afc8SEmmanuel Vadot }
10497113afc8SEmmanuel Vadot
10507113afc8SEmmanuel Vadot static void
xgbe_write_mmd_regs_v2(struct xgbe_prv_data * pdata,int prtad,int mmd_reg,int mmd_data)10517113afc8SEmmanuel Vadot xgbe_write_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad, int mmd_reg,
10527113afc8SEmmanuel Vadot int mmd_data)
10537113afc8SEmmanuel Vadot {
10547113afc8SEmmanuel Vadot unsigned long flags;
10557113afc8SEmmanuel Vadot unsigned int mmd_address, index, offset;
10567113afc8SEmmanuel Vadot
10577113afc8SEmmanuel Vadot if (mmd_reg & MII_ADDR_C45)
10587113afc8SEmmanuel Vadot mmd_address = mmd_reg & ~MII_ADDR_C45;
10597113afc8SEmmanuel Vadot else
10607113afc8SEmmanuel Vadot mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
10617113afc8SEmmanuel Vadot
10627113afc8SEmmanuel Vadot /* The PCS registers are accessed using mmio. The underlying
10637113afc8SEmmanuel Vadot * management interface uses indirect addressing to access the MMD
10647113afc8SEmmanuel Vadot * register sets. This requires accessing of the PCS register in two
10657113afc8SEmmanuel Vadot * phases, an address phase and a data phase.
10667113afc8SEmmanuel Vadot *
10677113afc8SEmmanuel Vadot * The mmio interface is based on 16-bit offsets and values. All
10687113afc8SEmmanuel Vadot * register offsets must therefore be adjusted by left shifting the
10697113afc8SEmmanuel Vadot * offset 1 bit and writing 16 bits of data.
10707113afc8SEmmanuel Vadot */
10717113afc8SEmmanuel Vadot mmd_address <<= 1;
10727113afc8SEmmanuel Vadot index = mmd_address & ~pdata->xpcs_window_mask;
10737113afc8SEmmanuel Vadot offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask);
10747113afc8SEmmanuel Vadot
10757113afc8SEmmanuel Vadot spin_lock_irqsave(&pdata->xpcs_lock, flags);
10767113afc8SEmmanuel Vadot XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index);
10777113afc8SEmmanuel Vadot XPCS16_IOWRITE(pdata, offset, mmd_data);
10787113afc8SEmmanuel Vadot spin_unlock_irqrestore(&pdata->xpcs_lock, flags);
10797113afc8SEmmanuel Vadot }
10807113afc8SEmmanuel Vadot
10817113afc8SEmmanuel Vadot static int
xgbe_read_mmd_regs_v1(struct xgbe_prv_data * pdata,int prtad,int mmd_reg)10827113afc8SEmmanuel Vadot xgbe_read_mmd_regs_v1(struct xgbe_prv_data *pdata, int prtad, int mmd_reg)
108344b781cfSAndrew Turner {
108444b781cfSAndrew Turner unsigned long flags;
108544b781cfSAndrew Turner unsigned int mmd_address;
108644b781cfSAndrew Turner int mmd_data;
108744b781cfSAndrew Turner
108844b781cfSAndrew Turner if (mmd_reg & MII_ADDR_C45)
108944b781cfSAndrew Turner mmd_address = mmd_reg & ~MII_ADDR_C45;
109044b781cfSAndrew Turner else
109144b781cfSAndrew Turner mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
109244b781cfSAndrew Turner
109344b781cfSAndrew Turner /* The PCS registers are accessed using mmio. The underlying APB3
109444b781cfSAndrew Turner * management interface uses indirect addressing to access the MMD
109544b781cfSAndrew Turner * register sets. This requires accessing of the PCS register in two
109644b781cfSAndrew Turner * phases, an address phase and a data phase.
109744b781cfSAndrew Turner *
109844b781cfSAndrew Turner * The mmio interface is based on 32-bit offsets and values. All
109944b781cfSAndrew Turner * register offsets must therefore be adjusted by left shifting the
110044b781cfSAndrew Turner * offset 2 bits and reading 32 bits of data.
110144b781cfSAndrew Turner */
110244b781cfSAndrew Turner spin_lock_irqsave(&pdata->xpcs_lock, flags);
11037113afc8SEmmanuel Vadot XPCS32_IOWRITE(pdata, PCS_V1_WINDOW_SELECT, mmd_address >> 8);
11047113afc8SEmmanuel Vadot mmd_data = XPCS32_IOREAD(pdata, (mmd_address & 0xff) << 2);
110544b781cfSAndrew Turner spin_unlock_irqrestore(&pdata->xpcs_lock, flags);
110644b781cfSAndrew Turner
11077113afc8SEmmanuel Vadot return (mmd_data);
110844b781cfSAndrew Turner }
110944b781cfSAndrew Turner
11107113afc8SEmmanuel Vadot static void
xgbe_write_mmd_regs_v1(struct xgbe_prv_data * pdata,int prtad,int mmd_reg,int mmd_data)11117113afc8SEmmanuel Vadot xgbe_write_mmd_regs_v1(struct xgbe_prv_data *pdata, int prtad, int mmd_reg,
11127113afc8SEmmanuel Vadot int mmd_data)
111344b781cfSAndrew Turner {
111444b781cfSAndrew Turner unsigned int mmd_address;
111544b781cfSAndrew Turner unsigned long flags;
111644b781cfSAndrew Turner
111744b781cfSAndrew Turner if (mmd_reg & MII_ADDR_C45)
111844b781cfSAndrew Turner mmd_address = mmd_reg & ~MII_ADDR_C45;
111944b781cfSAndrew Turner else
112044b781cfSAndrew Turner mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
112144b781cfSAndrew Turner
112244b781cfSAndrew Turner /* The PCS registers are accessed using mmio. The underlying APB3
112344b781cfSAndrew Turner * management interface uses indirect addressing to access the MMD
112444b781cfSAndrew Turner * register sets. This requires accessing of the PCS register in two
112544b781cfSAndrew Turner * phases, an address phase and a data phase.
112644b781cfSAndrew Turner *
112744b781cfSAndrew Turner * The mmio interface is based on 32-bit offsets and values. All
112844b781cfSAndrew Turner * register offsets must therefore be adjusted by left shifting the
11297113afc8SEmmanuel Vadot * offset 2 bits and writing 32 bits of data.
113044b781cfSAndrew Turner */
113144b781cfSAndrew Turner spin_lock_irqsave(&pdata->xpcs_lock, flags);
11327113afc8SEmmanuel Vadot XPCS32_IOWRITE(pdata, PCS_V1_WINDOW_SELECT, mmd_address >> 8);
11337113afc8SEmmanuel Vadot XPCS32_IOWRITE(pdata, (mmd_address & 0xff) << 2, mmd_data);
113444b781cfSAndrew Turner spin_unlock_irqrestore(&pdata->xpcs_lock, flags);
113544b781cfSAndrew Turner }
113644b781cfSAndrew Turner
11377113afc8SEmmanuel Vadot static int
xgbe_read_mmd_regs(struct xgbe_prv_data * pdata,int prtad,int mmd_reg)11387113afc8SEmmanuel Vadot xgbe_read_mmd_regs(struct xgbe_prv_data *pdata, int prtad, int mmd_reg)
113944b781cfSAndrew Turner {
11407113afc8SEmmanuel Vadot switch (pdata->vdata->xpcs_access) {
11417113afc8SEmmanuel Vadot case XGBE_XPCS_ACCESS_V1:
11427113afc8SEmmanuel Vadot return (xgbe_read_mmd_regs_v1(pdata, prtad, mmd_reg));
11437113afc8SEmmanuel Vadot
11447113afc8SEmmanuel Vadot case XGBE_XPCS_ACCESS_V2:
11457113afc8SEmmanuel Vadot default:
11467113afc8SEmmanuel Vadot return (xgbe_read_mmd_regs_v2(pdata, prtad, mmd_reg));
11477113afc8SEmmanuel Vadot }
114844b781cfSAndrew Turner }
114944b781cfSAndrew Turner
11507113afc8SEmmanuel Vadot static void
xgbe_write_mmd_regs(struct xgbe_prv_data * pdata,int prtad,int mmd_reg,int mmd_data)11517113afc8SEmmanuel Vadot xgbe_write_mmd_regs(struct xgbe_prv_data *pdata, int prtad, int mmd_reg,
11527113afc8SEmmanuel Vadot int mmd_data)
11537113afc8SEmmanuel Vadot {
11547113afc8SEmmanuel Vadot switch (pdata->vdata->xpcs_access) {
11557113afc8SEmmanuel Vadot case XGBE_XPCS_ACCESS_V1:
11567113afc8SEmmanuel Vadot return (xgbe_write_mmd_regs_v1(pdata, prtad, mmd_reg, mmd_data));
11577113afc8SEmmanuel Vadot
11587113afc8SEmmanuel Vadot case XGBE_XPCS_ACCESS_V2:
11597113afc8SEmmanuel Vadot default:
11607113afc8SEmmanuel Vadot return (xgbe_write_mmd_regs_v2(pdata, prtad, mmd_reg, mmd_data));
11617113afc8SEmmanuel Vadot }
11627113afc8SEmmanuel Vadot }
11637113afc8SEmmanuel Vadot
11647113afc8SEmmanuel Vadot static unsigned int
xgbe_create_mdio_sca(int port,int reg)11657113afc8SEmmanuel Vadot xgbe_create_mdio_sca(int port, int reg)
11667113afc8SEmmanuel Vadot {
11677113afc8SEmmanuel Vadot unsigned int mdio_sca, da;
11687113afc8SEmmanuel Vadot
11697113afc8SEmmanuel Vadot da = (reg & MII_ADDR_C45) ? reg >> 16 : 0;
11707113afc8SEmmanuel Vadot
11717113afc8SEmmanuel Vadot mdio_sca = 0;
11727113afc8SEmmanuel Vadot XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, RA, reg);
11737113afc8SEmmanuel Vadot XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, PA, port);
11747113afc8SEmmanuel Vadot XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, DA, da);
11757113afc8SEmmanuel Vadot
11767113afc8SEmmanuel Vadot return (mdio_sca);
11777113afc8SEmmanuel Vadot }
11787113afc8SEmmanuel Vadot
11797113afc8SEmmanuel Vadot static int
xgbe_write_ext_mii_regs(struct xgbe_prv_data * pdata,int addr,int reg,uint16_t val)11807113afc8SEmmanuel Vadot xgbe_write_ext_mii_regs(struct xgbe_prv_data *pdata, int addr, int reg,
11817113afc8SEmmanuel Vadot uint16_t val)
11827113afc8SEmmanuel Vadot {
11837113afc8SEmmanuel Vadot unsigned int mdio_sca, mdio_sccd;
11847113afc8SEmmanuel Vadot
11857113afc8SEmmanuel Vadot mtx_lock_spin(&pdata->mdio_mutex);
11867113afc8SEmmanuel Vadot
11877113afc8SEmmanuel Vadot mdio_sca = xgbe_create_mdio_sca(addr, reg);
11887113afc8SEmmanuel Vadot XGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca);
11897113afc8SEmmanuel Vadot
11907113afc8SEmmanuel Vadot mdio_sccd = 0;
11917113afc8SEmmanuel Vadot XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, DATA, val);
11927113afc8SEmmanuel Vadot XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, CMD, 1);
11937113afc8SEmmanuel Vadot XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, BUSY, 1);
11947113afc8SEmmanuel Vadot XGMAC_IOWRITE(pdata, MAC_MDIOSCCDR, mdio_sccd);
11957113afc8SEmmanuel Vadot
11967113afc8SEmmanuel Vadot if (msleep_spin(pdata, &pdata->mdio_mutex, "mdio_xfer", hz / 8) ==
11977113afc8SEmmanuel Vadot EWOULDBLOCK) {
11987113afc8SEmmanuel Vadot axgbe_error("%s: MDIO write error\n", __func__);
11997113afc8SEmmanuel Vadot mtx_unlock_spin(&pdata->mdio_mutex);
12007113afc8SEmmanuel Vadot return (-ETIMEDOUT);
12017113afc8SEmmanuel Vadot }
12027113afc8SEmmanuel Vadot
12037113afc8SEmmanuel Vadot mtx_unlock_spin(&pdata->mdio_mutex);
12047113afc8SEmmanuel Vadot return (0);
12057113afc8SEmmanuel Vadot }
12067113afc8SEmmanuel Vadot
12077113afc8SEmmanuel Vadot static int
xgbe_read_ext_mii_regs(struct xgbe_prv_data * pdata,int addr,int reg)12087113afc8SEmmanuel Vadot xgbe_read_ext_mii_regs(struct xgbe_prv_data *pdata, int addr, int reg)
12097113afc8SEmmanuel Vadot {
12107113afc8SEmmanuel Vadot unsigned int mdio_sca, mdio_sccd;
12117113afc8SEmmanuel Vadot
12127113afc8SEmmanuel Vadot mtx_lock_spin(&pdata->mdio_mutex);
12137113afc8SEmmanuel Vadot
12147113afc8SEmmanuel Vadot mdio_sca = xgbe_create_mdio_sca(addr, reg);
12157113afc8SEmmanuel Vadot XGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca);
12167113afc8SEmmanuel Vadot
12177113afc8SEmmanuel Vadot mdio_sccd = 0;
12187113afc8SEmmanuel Vadot XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, CMD, 3);
12197113afc8SEmmanuel Vadot XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, BUSY, 1);
12207113afc8SEmmanuel Vadot XGMAC_IOWRITE(pdata, MAC_MDIOSCCDR, mdio_sccd);
12217113afc8SEmmanuel Vadot
12227113afc8SEmmanuel Vadot if (msleep_spin(pdata, &pdata->mdio_mutex, "mdio_xfer", hz / 8) ==
12237113afc8SEmmanuel Vadot EWOULDBLOCK) {
12247113afc8SEmmanuel Vadot axgbe_error("%s: MDIO read error\n", __func__);
12257113afc8SEmmanuel Vadot mtx_unlock_spin(&pdata->mdio_mutex);
12267113afc8SEmmanuel Vadot return (-ETIMEDOUT);
12277113afc8SEmmanuel Vadot }
12287113afc8SEmmanuel Vadot
12297113afc8SEmmanuel Vadot mtx_unlock_spin(&pdata->mdio_mutex);
12307113afc8SEmmanuel Vadot
12317113afc8SEmmanuel Vadot return (XGMAC_IOREAD_BITS(pdata, MAC_MDIOSCCDR, DATA));
12327113afc8SEmmanuel Vadot }
12337113afc8SEmmanuel Vadot
12347113afc8SEmmanuel Vadot static int
xgbe_set_ext_mii_mode(struct xgbe_prv_data * pdata,unsigned int port,enum xgbe_mdio_mode mode)12357113afc8SEmmanuel Vadot xgbe_set_ext_mii_mode(struct xgbe_prv_data *pdata, unsigned int port,
12367113afc8SEmmanuel Vadot enum xgbe_mdio_mode mode)
12377113afc8SEmmanuel Vadot {
12387113afc8SEmmanuel Vadot unsigned int reg_val = XGMAC_IOREAD(pdata, MAC_MDIOCL22R);
12397113afc8SEmmanuel Vadot
12407113afc8SEmmanuel Vadot switch (mode) {
12417113afc8SEmmanuel Vadot case XGBE_MDIO_MODE_CL22:
12427113afc8SEmmanuel Vadot if (port > XGMAC_MAX_C22_PORT)
12437113afc8SEmmanuel Vadot return (-EINVAL);
12447113afc8SEmmanuel Vadot reg_val |= (1 << port);
12457113afc8SEmmanuel Vadot break;
12467113afc8SEmmanuel Vadot case XGBE_MDIO_MODE_CL45:
12477113afc8SEmmanuel Vadot break;
12487113afc8SEmmanuel Vadot default:
12497113afc8SEmmanuel Vadot return (-EINVAL);
12507113afc8SEmmanuel Vadot }
12517113afc8SEmmanuel Vadot
12527113afc8SEmmanuel Vadot XGMAC_IOWRITE(pdata, MAC_MDIOCL22R, reg_val);
12537113afc8SEmmanuel Vadot
12547113afc8SEmmanuel Vadot return (0);
12557113afc8SEmmanuel Vadot }
12567113afc8SEmmanuel Vadot
12577113afc8SEmmanuel Vadot static int
xgbe_tx_complete(struct xgbe_ring_desc * rdesc)12587113afc8SEmmanuel Vadot xgbe_tx_complete(struct xgbe_ring_desc *rdesc)
12597113afc8SEmmanuel Vadot {
12607113afc8SEmmanuel Vadot return (!XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN));
12617113afc8SEmmanuel Vadot }
12627113afc8SEmmanuel Vadot
12637113afc8SEmmanuel Vadot static int
xgbe_disable_rx_csum(struct xgbe_prv_data * pdata)12647113afc8SEmmanuel Vadot xgbe_disable_rx_csum(struct xgbe_prv_data *pdata)
126544b781cfSAndrew Turner {
126644b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 0);
126744b781cfSAndrew Turner
12687113afc8SEmmanuel Vadot axgbe_printf(0, "Receive checksum offload Disabled\n");
12697113afc8SEmmanuel Vadot return (0);
127044b781cfSAndrew Turner }
127144b781cfSAndrew Turner
12727113afc8SEmmanuel Vadot static int
xgbe_enable_rx_csum(struct xgbe_prv_data * pdata)12737113afc8SEmmanuel Vadot xgbe_enable_rx_csum(struct xgbe_prv_data *pdata)
127444b781cfSAndrew Turner {
127544b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 1);
127644b781cfSAndrew Turner
12777113afc8SEmmanuel Vadot axgbe_printf(0, "Receive checksum offload Enabled\n");
12787113afc8SEmmanuel Vadot return (0);
127944b781cfSAndrew Turner }
128044b781cfSAndrew Turner
12817113afc8SEmmanuel Vadot static void
xgbe_tx_desc_reset(struct xgbe_ring_data * rdata)12827113afc8SEmmanuel Vadot xgbe_tx_desc_reset(struct xgbe_ring_data *rdata)
128344b781cfSAndrew Turner {
128444b781cfSAndrew Turner struct xgbe_ring_desc *rdesc = rdata->rdesc;
128544b781cfSAndrew Turner
128644b781cfSAndrew Turner /* Reset the Tx descriptor
128744b781cfSAndrew Turner * Set buffer 1 (lo) address to zero
128844b781cfSAndrew Turner * Set buffer 1 (hi) address to zero
128944b781cfSAndrew Turner * Reset all other control bits (IC, TTSE, B2L & B1L)
129044b781cfSAndrew Turner * Reset all other control bits (OWN, CTXT, FD, LD, CPC, CIC, etc)
129144b781cfSAndrew Turner */
129244b781cfSAndrew Turner rdesc->desc0 = 0;
129344b781cfSAndrew Turner rdesc->desc1 = 0;
129444b781cfSAndrew Turner rdesc->desc2 = 0;
129544b781cfSAndrew Turner rdesc->desc3 = 0;
129644b781cfSAndrew Turner
12977113afc8SEmmanuel Vadot wmb();
129844b781cfSAndrew Turner }
129944b781cfSAndrew Turner
13007113afc8SEmmanuel Vadot static void
xgbe_tx_desc_init(struct xgbe_channel * channel)13017113afc8SEmmanuel Vadot xgbe_tx_desc_init(struct xgbe_channel *channel)
130244b781cfSAndrew Turner {
130344b781cfSAndrew Turner struct xgbe_ring *ring = channel->tx_ring;
130444b781cfSAndrew Turner struct xgbe_ring_data *rdata;
130544b781cfSAndrew Turner int i;
130644b781cfSAndrew Turner int start_index = ring->cur;
130744b781cfSAndrew Turner
130844b781cfSAndrew Turner /* Initialze all descriptors */
130944b781cfSAndrew Turner for (i = 0; i < ring->rdesc_count; i++) {
131044b781cfSAndrew Turner rdata = XGBE_GET_DESC_DATA(ring, i);
131144b781cfSAndrew Turner
131244b781cfSAndrew Turner /* Initialize Tx descriptor */
131344b781cfSAndrew Turner xgbe_tx_desc_reset(rdata);
131444b781cfSAndrew Turner }
131544b781cfSAndrew Turner
131644b781cfSAndrew Turner /* Update the total number of Tx descriptors */
131744b781cfSAndrew Turner XGMAC_DMA_IOWRITE(channel, DMA_CH_TDRLR, ring->rdesc_count - 1);
131844b781cfSAndrew Turner
131944b781cfSAndrew Turner /* Update the starting address of descriptor ring */
132044b781cfSAndrew Turner rdata = XGBE_GET_DESC_DATA(ring, start_index);
132144b781cfSAndrew Turner XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_HI,
13229c6d6488SAndrew Turner upper_32_bits(rdata->rdata_paddr));
132344b781cfSAndrew Turner XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_LO,
13249c6d6488SAndrew Turner lower_32_bits(rdata->rdata_paddr));
132544b781cfSAndrew Turner }
132644b781cfSAndrew Turner
13277113afc8SEmmanuel Vadot static void
xgbe_rx_desc_init(struct xgbe_channel * channel)13287113afc8SEmmanuel Vadot xgbe_rx_desc_init(struct xgbe_channel *channel)
132944b781cfSAndrew Turner {
133044b781cfSAndrew Turner struct xgbe_ring *ring = channel->rx_ring;
133144b781cfSAndrew Turner struct xgbe_ring_data *rdata;
133244b781cfSAndrew Turner unsigned int start_index = ring->cur;
133344b781cfSAndrew Turner
13347113afc8SEmmanuel Vadot /*
13357113afc8SEmmanuel Vadot * Just set desc_count and the starting address of the desc list
13367113afc8SEmmanuel Vadot * here. Rest will be done as part of the txrx path.
13377113afc8SEmmanuel Vadot */
13389c6d6488SAndrew Turner
133944b781cfSAndrew Turner /* Update the total number of Rx descriptors */
134044b781cfSAndrew Turner XGMAC_DMA_IOWRITE(channel, DMA_CH_RDRLR, ring->rdesc_count - 1);
134144b781cfSAndrew Turner
134244b781cfSAndrew Turner /* Update the starting address of descriptor ring */
134344b781cfSAndrew Turner rdata = XGBE_GET_DESC_DATA(ring, start_index);
134444b781cfSAndrew Turner XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_HI,
13459c6d6488SAndrew Turner upper_32_bits(rdata->rdata_paddr));
134644b781cfSAndrew Turner XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_LO,
13479c6d6488SAndrew Turner lower_32_bits(rdata->rdata_paddr));
134844b781cfSAndrew Turner }
134944b781cfSAndrew Turner
13507113afc8SEmmanuel Vadot static int
xgbe_dev_read(struct xgbe_channel * channel)13517113afc8SEmmanuel Vadot xgbe_dev_read(struct xgbe_channel *channel)
135244b781cfSAndrew Turner {
135344b781cfSAndrew Turner struct xgbe_prv_data *pdata = channel->pdata;
135444b781cfSAndrew Turner struct xgbe_ring *ring = channel->rx_ring;
135544b781cfSAndrew Turner struct xgbe_ring_data *rdata;
135644b781cfSAndrew Turner struct xgbe_ring_desc *rdesc;
135744b781cfSAndrew Turner struct xgbe_packet_data *packet = &ring->packet_data;
135894e3e7d2SAdrian Chadd unsigned int err, etlt, l34t = 0;
135944b781cfSAndrew Turner
13607113afc8SEmmanuel Vadot axgbe_printf(1, "-->xgbe_dev_read: cur = %d\n", ring->cur);
136144b781cfSAndrew Turner
136244b781cfSAndrew Turner rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
136344b781cfSAndrew Turner rdesc = rdata->rdesc;
136444b781cfSAndrew Turner
136544b781cfSAndrew Turner /* Check for data availability */
136644b781cfSAndrew Turner if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN))
13677113afc8SEmmanuel Vadot return (1);
136844b781cfSAndrew Turner
13697113afc8SEmmanuel Vadot rmb();
13707113afc8SEmmanuel Vadot
13717113afc8SEmmanuel Vadot if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CTXT)) {
13727113afc8SEmmanuel Vadot /* TODO - Timestamp Context Descriptor */
13737113afc8SEmmanuel Vadot XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
13747113afc8SEmmanuel Vadot CONTEXT, 1);
13757113afc8SEmmanuel Vadot XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
13767113afc8SEmmanuel Vadot CONTEXT_NEXT, 0);
13777113afc8SEmmanuel Vadot return (0);
13787113afc8SEmmanuel Vadot }
137944b781cfSAndrew Turner
138044b781cfSAndrew Turner /* Normal Descriptor, be sure Context Descriptor bit is off */
138144b781cfSAndrew Turner XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, CONTEXT, 0);
138244b781cfSAndrew Turner
138344b781cfSAndrew Turner /* Indicate if a Context Descriptor is next */
138444b781cfSAndrew Turner if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CDA))
138544b781cfSAndrew Turner XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
138644b781cfSAndrew Turner CONTEXT_NEXT, 1);
138744b781cfSAndrew Turner
138844b781cfSAndrew Turner /* Get the header length */
138944b781cfSAndrew Turner if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, FD)) {
13907113afc8SEmmanuel Vadot XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
13917113afc8SEmmanuel Vadot FIRST, 1);
139244b781cfSAndrew Turner rdata->rx.hdr_len = XGMAC_GET_BITS_LE(rdesc->desc2,
139344b781cfSAndrew Turner RX_NORMAL_DESC2, HL);
13947113afc8SEmmanuel Vadot if (rdata->rx.hdr_len)
13957113afc8SEmmanuel Vadot pdata->ext_stats.rx_split_header_packets++;
13967113afc8SEmmanuel Vadot } else
13977113afc8SEmmanuel Vadot XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
13987113afc8SEmmanuel Vadot FIRST, 0);
13997113afc8SEmmanuel Vadot
14007113afc8SEmmanuel Vadot /* Get the RSS hash */
14017113afc8SEmmanuel Vadot if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, RSV)) {
14027113afc8SEmmanuel Vadot XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
14037113afc8SEmmanuel Vadot RSS_HASH, 1);
14047113afc8SEmmanuel Vadot
14057113afc8SEmmanuel Vadot packet->rss_hash = le32_to_cpu(rdesc->desc1);
14067113afc8SEmmanuel Vadot
14077113afc8SEmmanuel Vadot l34t = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, L34T);
14087113afc8SEmmanuel Vadot switch (l34t) {
14097113afc8SEmmanuel Vadot case RX_DESC3_L34T_IPV4_TCP:
14107113afc8SEmmanuel Vadot packet->rss_hash_type = M_HASHTYPE_RSS_TCP_IPV4;
14117113afc8SEmmanuel Vadot break;
14127113afc8SEmmanuel Vadot case RX_DESC3_L34T_IPV4_UDP:
14137113afc8SEmmanuel Vadot packet->rss_hash_type = M_HASHTYPE_RSS_UDP_IPV4;
14147113afc8SEmmanuel Vadot break;
14157113afc8SEmmanuel Vadot case RX_DESC3_L34T_IPV6_TCP:
14167113afc8SEmmanuel Vadot packet->rss_hash_type = M_HASHTYPE_RSS_TCP_IPV6;
14177113afc8SEmmanuel Vadot break;
14187113afc8SEmmanuel Vadot case RX_DESC3_L34T_IPV6_UDP:
14197113afc8SEmmanuel Vadot packet->rss_hash_type = M_HASHTYPE_RSS_UDP_IPV6;
14207113afc8SEmmanuel Vadot break;
14217113afc8SEmmanuel Vadot default:
14227113afc8SEmmanuel Vadot packet->rss_hash_type = M_HASHTYPE_OPAQUE;
14237113afc8SEmmanuel Vadot break;
14247113afc8SEmmanuel Vadot }
142544b781cfSAndrew Turner }
142644b781cfSAndrew Turner
142744b781cfSAndrew Turner /* Not all the data has been transferred for this packet */
14287113afc8SEmmanuel Vadot if (!XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, LD)) {
14297113afc8SEmmanuel Vadot /* This is not the last of the data for this packet */
143044b781cfSAndrew Turner XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
14317113afc8SEmmanuel Vadot LAST, 0);
14327113afc8SEmmanuel Vadot return (0);
143344b781cfSAndrew Turner }
143444b781cfSAndrew Turner
143544b781cfSAndrew Turner /* This is the last of the data for this packet */
143644b781cfSAndrew Turner XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
14377113afc8SEmmanuel Vadot LAST, 1);
14387113afc8SEmmanuel Vadot
14397113afc8SEmmanuel Vadot /* Get the packet length */
14407113afc8SEmmanuel Vadot rdata->rx.len = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, PL);
14417113afc8SEmmanuel Vadot
14427113afc8SEmmanuel Vadot /* Set checksum done indicator as appropriate */
14437113afc8SEmmanuel Vadot /* TODO - add tunneling support */
14447113afc8SEmmanuel Vadot XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
14457113afc8SEmmanuel Vadot CSUM_DONE, 1);
144644b781cfSAndrew Turner
144744b781cfSAndrew Turner /* Check for errors (only valid in last descriptor) */
144844b781cfSAndrew Turner err = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ES);
144944b781cfSAndrew Turner etlt = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ETLT);
14507113afc8SEmmanuel Vadot axgbe_printf(1, "%s: err=%u, etlt=%#x\n", __func__, err, etlt);
145144b781cfSAndrew Turner
14527113afc8SEmmanuel Vadot if (!err || !etlt) {
14537113afc8SEmmanuel Vadot /* No error if err is 0 or etlt is 0 */
14542b8df536SStephan de Wit if (etlt == 0x09 &&
14552b8df536SStephan de Wit (if_getcapenable(pdata->netdev) & IFCAP_VLAN_HWTAGGING)) {
14567113afc8SEmmanuel Vadot XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
14577113afc8SEmmanuel Vadot VLAN_CTAG, 1);
14587113afc8SEmmanuel Vadot packet->vlan_ctag = XGMAC_GET_BITS_LE(rdesc->desc0,
14597113afc8SEmmanuel Vadot RX_NORMAL_DESC0, OVT);
14607113afc8SEmmanuel Vadot axgbe_printf(1, "vlan-ctag=%#06x\n", packet->vlan_ctag);
14617113afc8SEmmanuel Vadot }
14627113afc8SEmmanuel Vadot } else {
14637113afc8SEmmanuel Vadot unsigned int tnp = XGMAC_GET_BITS(packet->attributes,
14647113afc8SEmmanuel Vadot RX_PACKET_ATTRIBUTES, TNP);
14657113afc8SEmmanuel Vadot
14667113afc8SEmmanuel Vadot if ((etlt == 0x05) || (etlt == 0x06)) {
14677113afc8SEmmanuel Vadot axgbe_printf(1, "%s: err1 l34t %d err 0x%x etlt 0x%x\n",
14687113afc8SEmmanuel Vadot __func__, l34t, err, etlt);
146944b781cfSAndrew Turner XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
147044b781cfSAndrew Turner CSUM_DONE, 0);
14717113afc8SEmmanuel Vadot XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
14727113afc8SEmmanuel Vadot TNPCSUM_DONE, 0);
14737113afc8SEmmanuel Vadot pdata->ext_stats.rx_csum_errors++;
14747113afc8SEmmanuel Vadot } else if (tnp && ((etlt == 0x09) || (etlt == 0x0a))) {
14757113afc8SEmmanuel Vadot axgbe_printf(1, "%s: err2 l34t %d err 0x%x etlt 0x%x\n",
14767113afc8SEmmanuel Vadot __func__, l34t, err, etlt);
14777113afc8SEmmanuel Vadot XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
14787113afc8SEmmanuel Vadot CSUM_DONE, 0);
14797113afc8SEmmanuel Vadot XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
14807113afc8SEmmanuel Vadot TNPCSUM_DONE, 0);
14817113afc8SEmmanuel Vadot pdata->ext_stats.rx_vxlan_csum_errors++;
14827113afc8SEmmanuel Vadot } else {
14837113afc8SEmmanuel Vadot axgbe_printf(1, "%s: tnp %d l34t %d err 0x%x etlt 0x%x\n",
14847113afc8SEmmanuel Vadot __func__, tnp, l34t, err, etlt);
14857113afc8SEmmanuel Vadot axgbe_printf(1, "%s: Channel: %d SR 0x%x DSR 0x%x \n",
14867113afc8SEmmanuel Vadot __func__, channel->queue_index,
14877113afc8SEmmanuel Vadot XGMAC_DMA_IOREAD(channel, DMA_CH_SR),
14887113afc8SEmmanuel Vadot XGMAC_DMA_IOREAD(channel, DMA_CH_DSR));
14897113afc8SEmmanuel Vadot axgbe_printf(1, "%s: ring cur %d dirty %d\n",
14907113afc8SEmmanuel Vadot __func__, ring->cur, ring->dirty);
14917113afc8SEmmanuel Vadot axgbe_printf(1, "%s: Desc 0x%08x-0x%08x-0x%08x-0x%08x\n",
14927113afc8SEmmanuel Vadot __func__, rdesc->desc0, rdesc->desc1, rdesc->desc2,
14937113afc8SEmmanuel Vadot rdesc->desc3);
149444b781cfSAndrew Turner XGMAC_SET_BITS(packet->errors, RX_PACKET_ERRORS,
149544b781cfSAndrew Turner FRAME, 1);
149644b781cfSAndrew Turner }
149744b781cfSAndrew Turner }
149844b781cfSAndrew Turner
14997113afc8SEmmanuel Vadot axgbe_printf(1, "<--xgbe_dev_read: %s - descriptor=%u (cur=%d)\n",
15007113afc8SEmmanuel Vadot channel->name, ring->cur & (ring->rdesc_count - 1), ring->cur);
15017113afc8SEmmanuel Vadot
15027113afc8SEmmanuel Vadot return (0);
15037113afc8SEmmanuel Vadot }
15047113afc8SEmmanuel Vadot
15057113afc8SEmmanuel Vadot static int
xgbe_is_context_desc(struct xgbe_ring_desc * rdesc)15067113afc8SEmmanuel Vadot xgbe_is_context_desc(struct xgbe_ring_desc *rdesc)
150744b781cfSAndrew Turner {
150844b781cfSAndrew Turner /* Rx and Tx share CTXT bit, so check TDES3.CTXT bit */
15097113afc8SEmmanuel Vadot return (XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT));
151044b781cfSAndrew Turner }
151144b781cfSAndrew Turner
15127113afc8SEmmanuel Vadot static int
xgbe_is_last_desc(struct xgbe_ring_desc * rdesc)15137113afc8SEmmanuel Vadot xgbe_is_last_desc(struct xgbe_ring_desc *rdesc)
151444b781cfSAndrew Turner {
151544b781cfSAndrew Turner /* Rx and Tx share LD bit, so check TDES3.LD bit */
15167113afc8SEmmanuel Vadot return (XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD));
151744b781cfSAndrew Turner }
151844b781cfSAndrew Turner
15197113afc8SEmmanuel Vadot static int
xgbe_enable_int(struct xgbe_channel * channel,enum xgbe_int int_id)15207113afc8SEmmanuel Vadot xgbe_enable_int(struct xgbe_channel *channel, enum xgbe_int int_id)
152144b781cfSAndrew Turner {
15227113afc8SEmmanuel Vadot struct xgbe_prv_data *pdata = channel->pdata;
152344b781cfSAndrew Turner
15247113afc8SEmmanuel Vadot axgbe_printf(1, "enable_int: DMA_CH_IER read - 0x%x\n",
15257113afc8SEmmanuel Vadot channel->curr_ier);
152644b781cfSAndrew Turner
152744b781cfSAndrew Turner switch (int_id) {
152844b781cfSAndrew Turner case XGMAC_INT_DMA_CH_SR_TI:
15297113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 1);
153044b781cfSAndrew Turner break;
153144b781cfSAndrew Turner case XGMAC_INT_DMA_CH_SR_TPS:
15327113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TXSE, 1);
153344b781cfSAndrew Turner break;
153444b781cfSAndrew Turner case XGMAC_INT_DMA_CH_SR_TBU:
15357113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TBUE, 1);
153644b781cfSAndrew Turner break;
153744b781cfSAndrew Turner case XGMAC_INT_DMA_CH_SR_RI:
15387113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 1);
153944b781cfSAndrew Turner break;
154044b781cfSAndrew Turner case XGMAC_INT_DMA_CH_SR_RBU:
15417113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 1);
154244b781cfSAndrew Turner break;
154344b781cfSAndrew Turner case XGMAC_INT_DMA_CH_SR_RPS:
15447113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RSE, 1);
154544b781cfSAndrew Turner break;
154644b781cfSAndrew Turner case XGMAC_INT_DMA_CH_SR_TI_RI:
15477113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 1);
15487113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 1);
154944b781cfSAndrew Turner break;
155044b781cfSAndrew Turner case XGMAC_INT_DMA_CH_SR_FBE:
15517113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 1);
155244b781cfSAndrew Turner break;
155344b781cfSAndrew Turner case XGMAC_INT_DMA_ALL:
15547113afc8SEmmanuel Vadot channel->curr_ier |= channel->saved_ier;
155544b781cfSAndrew Turner break;
155644b781cfSAndrew Turner default:
15577113afc8SEmmanuel Vadot return (-1);
155844b781cfSAndrew Turner }
155944b781cfSAndrew Turner
15607113afc8SEmmanuel Vadot XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, channel->curr_ier);
156144b781cfSAndrew Turner
15627113afc8SEmmanuel Vadot axgbe_printf(1, "enable_int: DMA_CH_IER write - 0x%x\n",
15637113afc8SEmmanuel Vadot channel->curr_ier);
15647113afc8SEmmanuel Vadot
15657113afc8SEmmanuel Vadot return (0);
156644b781cfSAndrew Turner }
156744b781cfSAndrew Turner
15687113afc8SEmmanuel Vadot static int
xgbe_disable_int(struct xgbe_channel * channel,enum xgbe_int int_id)15697113afc8SEmmanuel Vadot xgbe_disable_int(struct xgbe_channel *channel, enum xgbe_int int_id)
157044b781cfSAndrew Turner {
15717113afc8SEmmanuel Vadot struct xgbe_prv_data *pdata = channel->pdata;
157244b781cfSAndrew Turner
15737113afc8SEmmanuel Vadot axgbe_printf(1, "disable_int: DMA_CH_IER read - 0x%x\n",
15747113afc8SEmmanuel Vadot channel->curr_ier);
157544b781cfSAndrew Turner
157644b781cfSAndrew Turner switch (int_id) {
157744b781cfSAndrew Turner case XGMAC_INT_DMA_CH_SR_TI:
15787113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 0);
157944b781cfSAndrew Turner break;
158044b781cfSAndrew Turner case XGMAC_INT_DMA_CH_SR_TPS:
15817113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TXSE, 0);
158244b781cfSAndrew Turner break;
158344b781cfSAndrew Turner case XGMAC_INT_DMA_CH_SR_TBU:
15847113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TBUE, 0);
158544b781cfSAndrew Turner break;
158644b781cfSAndrew Turner case XGMAC_INT_DMA_CH_SR_RI:
15877113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 0);
158844b781cfSAndrew Turner break;
158944b781cfSAndrew Turner case XGMAC_INT_DMA_CH_SR_RBU:
15907113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 0);
159144b781cfSAndrew Turner break;
159244b781cfSAndrew Turner case XGMAC_INT_DMA_CH_SR_RPS:
15937113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RSE, 0);
159444b781cfSAndrew Turner break;
159544b781cfSAndrew Turner case XGMAC_INT_DMA_CH_SR_TI_RI:
15967113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 0);
15977113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 0);
159844b781cfSAndrew Turner break;
159944b781cfSAndrew Turner case XGMAC_INT_DMA_CH_SR_FBE:
16007113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 0);
160144b781cfSAndrew Turner break;
160244b781cfSAndrew Turner case XGMAC_INT_DMA_ALL:
16037113afc8SEmmanuel Vadot channel->saved_ier = channel->curr_ier;
16047113afc8SEmmanuel Vadot channel->curr_ier = 0;
160544b781cfSAndrew Turner break;
160644b781cfSAndrew Turner default:
16077113afc8SEmmanuel Vadot return (-1);
160844b781cfSAndrew Turner }
160944b781cfSAndrew Turner
16107113afc8SEmmanuel Vadot XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, channel->curr_ier);
161144b781cfSAndrew Turner
16127113afc8SEmmanuel Vadot axgbe_printf(1, "disable_int: DMA_CH_IER write - 0x%x\n",
16137113afc8SEmmanuel Vadot channel->curr_ier);
16147113afc8SEmmanuel Vadot
16157113afc8SEmmanuel Vadot return (0);
161644b781cfSAndrew Turner }
161744b781cfSAndrew Turner
16187113afc8SEmmanuel Vadot static int
__xgbe_exit(struct xgbe_prv_data * pdata)16197113afc8SEmmanuel Vadot __xgbe_exit(struct xgbe_prv_data *pdata)
162044b781cfSAndrew Turner {
162144b781cfSAndrew Turner unsigned int count = 2000;
162244b781cfSAndrew Turner
162344b781cfSAndrew Turner /* Issue a software reset */
162444b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, DMA_MR, SWR, 1);
16259c6d6488SAndrew Turner DELAY(10);
162644b781cfSAndrew Turner
162744b781cfSAndrew Turner /* Poll Until Poll Condition */
162844b781cfSAndrew Turner while (--count && XGMAC_IOREAD_BITS(pdata, DMA_MR, SWR))
16299c6d6488SAndrew Turner DELAY(500);
163044b781cfSAndrew Turner
163144b781cfSAndrew Turner if (!count)
16327113afc8SEmmanuel Vadot return (-EBUSY);
163344b781cfSAndrew Turner
16347113afc8SEmmanuel Vadot return (0);
163544b781cfSAndrew Turner }
163644b781cfSAndrew Turner
16377113afc8SEmmanuel Vadot static int
xgbe_exit(struct xgbe_prv_data * pdata)16387113afc8SEmmanuel Vadot xgbe_exit(struct xgbe_prv_data *pdata)
16397113afc8SEmmanuel Vadot {
16407113afc8SEmmanuel Vadot int ret;
16417113afc8SEmmanuel Vadot
16427113afc8SEmmanuel Vadot /* To guard against possible incorrectly generated interrupts,
16437113afc8SEmmanuel Vadot * issue the software reset twice.
16447113afc8SEmmanuel Vadot */
16457113afc8SEmmanuel Vadot ret = __xgbe_exit(pdata);
16467113afc8SEmmanuel Vadot if (ret) {
16477113afc8SEmmanuel Vadot axgbe_error("%s: exit error %d\n", __func__, ret);
16487113afc8SEmmanuel Vadot return (ret);
16497113afc8SEmmanuel Vadot }
16507113afc8SEmmanuel Vadot
16517113afc8SEmmanuel Vadot return (__xgbe_exit(pdata));
16527113afc8SEmmanuel Vadot }
16537113afc8SEmmanuel Vadot
16547113afc8SEmmanuel Vadot static int
xgbe_flush_tx_queues(struct xgbe_prv_data * pdata)16557113afc8SEmmanuel Vadot xgbe_flush_tx_queues(struct xgbe_prv_data *pdata)
165644b781cfSAndrew Turner {
165744b781cfSAndrew Turner unsigned int i, count;
165844b781cfSAndrew Turner
165944b781cfSAndrew Turner if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) < 0x21)
16607113afc8SEmmanuel Vadot return (0);
166144b781cfSAndrew Turner
166244b781cfSAndrew Turner for (i = 0; i < pdata->tx_q_count; i++)
166344b781cfSAndrew Turner XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, FTQ, 1);
166444b781cfSAndrew Turner
166544b781cfSAndrew Turner /* Poll Until Poll Condition */
166644b781cfSAndrew Turner for (i = 0; i < pdata->tx_q_count; i++) {
166744b781cfSAndrew Turner count = 2000;
166844b781cfSAndrew Turner while (--count && XGMAC_MTL_IOREAD_BITS(pdata, i,
166944b781cfSAndrew Turner MTL_Q_TQOMR, FTQ))
16709c6d6488SAndrew Turner DELAY(500);
167144b781cfSAndrew Turner
167244b781cfSAndrew Turner if (!count)
16737113afc8SEmmanuel Vadot return (-EBUSY);
167444b781cfSAndrew Turner }
167544b781cfSAndrew Turner
16767113afc8SEmmanuel Vadot return (0);
167744b781cfSAndrew Turner }
167844b781cfSAndrew Turner
16797113afc8SEmmanuel Vadot static void
xgbe_config_dma_bus(struct xgbe_prv_data * pdata)16807113afc8SEmmanuel Vadot xgbe_config_dma_bus(struct xgbe_prv_data *pdata)
168144b781cfSAndrew Turner {
16827113afc8SEmmanuel Vadot unsigned int sbmr;
16837113afc8SEmmanuel Vadot
16847113afc8SEmmanuel Vadot sbmr = XGMAC_IOREAD(pdata, DMA_SBMR);
16857113afc8SEmmanuel Vadot
168644b781cfSAndrew Turner /* Set enhanced addressing mode */
16877113afc8SEmmanuel Vadot XGMAC_SET_BITS(sbmr, DMA_SBMR, EAME, 1);
168844b781cfSAndrew Turner
168944b781cfSAndrew Turner /* Set the System Bus mode */
16907113afc8SEmmanuel Vadot XGMAC_SET_BITS(sbmr, DMA_SBMR, UNDEF, 1);
16917113afc8SEmmanuel Vadot XGMAC_SET_BITS(sbmr, DMA_SBMR, BLEN, pdata->blen >> 2);
16927113afc8SEmmanuel Vadot XGMAC_SET_BITS(sbmr, DMA_SBMR, AAL, pdata->aal);
16937113afc8SEmmanuel Vadot XGMAC_SET_BITS(sbmr, DMA_SBMR, RD_OSR_LMT, pdata->rd_osr_limit - 1);
16947113afc8SEmmanuel Vadot XGMAC_SET_BITS(sbmr, DMA_SBMR, WR_OSR_LMT, pdata->wr_osr_limit - 1);
16957113afc8SEmmanuel Vadot
16967113afc8SEmmanuel Vadot XGMAC_IOWRITE(pdata, DMA_SBMR, sbmr);
16977113afc8SEmmanuel Vadot
16987113afc8SEmmanuel Vadot /* Set descriptor fetching threshold */
16997113afc8SEmmanuel Vadot if (pdata->vdata->tx_desc_prefetch)
17007113afc8SEmmanuel Vadot XGMAC_IOWRITE_BITS(pdata, DMA_TXEDMACR, TDPS,
17017113afc8SEmmanuel Vadot pdata->vdata->tx_desc_prefetch);
17027113afc8SEmmanuel Vadot
17037113afc8SEmmanuel Vadot if (pdata->vdata->rx_desc_prefetch)
17047113afc8SEmmanuel Vadot XGMAC_IOWRITE_BITS(pdata, DMA_RXEDMACR, RDPS,
17057113afc8SEmmanuel Vadot pdata->vdata->rx_desc_prefetch);
170644b781cfSAndrew Turner }
170744b781cfSAndrew Turner
17087113afc8SEmmanuel Vadot static void
xgbe_config_dma_cache(struct xgbe_prv_data * pdata)17097113afc8SEmmanuel Vadot xgbe_config_dma_cache(struct xgbe_prv_data *pdata)
171044b781cfSAndrew Turner {
17117113afc8SEmmanuel Vadot XGMAC_IOWRITE(pdata, DMA_AXIARCR, pdata->arcr);
17127113afc8SEmmanuel Vadot XGMAC_IOWRITE(pdata, DMA_AXIAWCR, pdata->awcr);
17137113afc8SEmmanuel Vadot if (pdata->awarcr)
17147113afc8SEmmanuel Vadot XGMAC_IOWRITE(pdata, DMA_AXIAWARCR, pdata->awarcr);
171544b781cfSAndrew Turner }
171644b781cfSAndrew Turner
17177113afc8SEmmanuel Vadot static void
xgbe_config_mtl_mode(struct xgbe_prv_data * pdata)17187113afc8SEmmanuel Vadot xgbe_config_mtl_mode(struct xgbe_prv_data *pdata)
171944b781cfSAndrew Turner {
172044b781cfSAndrew Turner unsigned int i;
172144b781cfSAndrew Turner
172244b781cfSAndrew Turner /* Set Tx to weighted round robin scheduling algorithm */
172344b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_WRR);
172444b781cfSAndrew Turner
172544b781cfSAndrew Turner /* Set Tx traffic classes to use WRR algorithm with equal weights */
172644b781cfSAndrew Turner for (i = 0; i < pdata->hw_feat.tc_cnt; i++) {
172744b781cfSAndrew Turner XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
172844b781cfSAndrew Turner MTL_TSA_ETS);
172944b781cfSAndrew Turner XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, 1);
173044b781cfSAndrew Turner }
173144b781cfSAndrew Turner
173244b781cfSAndrew Turner /* Set Rx to strict priority algorithm */
173344b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MTL_OMR, RAA, MTL_RAA_SP);
173444b781cfSAndrew Turner }
173544b781cfSAndrew Turner
17367113afc8SEmmanuel Vadot static void
xgbe_queue_flow_control_threshold(struct xgbe_prv_data * pdata,unsigned int queue,unsigned int q_fifo_size)17377113afc8SEmmanuel Vadot xgbe_queue_flow_control_threshold(struct xgbe_prv_data *pdata,
17387113afc8SEmmanuel Vadot unsigned int queue, unsigned int q_fifo_size)
17397113afc8SEmmanuel Vadot {
17407113afc8SEmmanuel Vadot unsigned int frame_fifo_size;
17417113afc8SEmmanuel Vadot unsigned int rfa, rfd;
17427113afc8SEmmanuel Vadot
17437113afc8SEmmanuel Vadot frame_fifo_size = XGMAC_FLOW_CONTROL_ALIGN(xgbe_get_max_frame(pdata));
17447113afc8SEmmanuel Vadot axgbe_printf(1, "%s: queue %d q_fifo_size %d frame_fifo_size 0x%x\n",
17457113afc8SEmmanuel Vadot __func__, queue, q_fifo_size, frame_fifo_size);
17467113afc8SEmmanuel Vadot
17477113afc8SEmmanuel Vadot /* TODO - add pfc/ets related support */
17487113afc8SEmmanuel Vadot
17497113afc8SEmmanuel Vadot /* This path deals with just maximum frame sizes which are
17507113afc8SEmmanuel Vadot * limited to a jumbo frame of 9,000 (plus headers, etc.)
17517113afc8SEmmanuel Vadot * so we can never exceed the maximum allowable RFA/RFD
17527113afc8SEmmanuel Vadot * values.
17537113afc8SEmmanuel Vadot */
17547113afc8SEmmanuel Vadot if (q_fifo_size <= 2048) {
17557113afc8SEmmanuel Vadot /* rx_rfd to zero to signal no flow control */
17567113afc8SEmmanuel Vadot pdata->rx_rfa[queue] = 0;
17577113afc8SEmmanuel Vadot pdata->rx_rfd[queue] = 0;
17587113afc8SEmmanuel Vadot return;
17597113afc8SEmmanuel Vadot }
17607113afc8SEmmanuel Vadot
17617113afc8SEmmanuel Vadot if (q_fifo_size <= 4096) {
17627113afc8SEmmanuel Vadot /* Between 2048 and 4096 */
17637113afc8SEmmanuel Vadot pdata->rx_rfa[queue] = 0; /* Full - 1024 bytes */
17647113afc8SEmmanuel Vadot pdata->rx_rfd[queue] = 1; /* Full - 1536 bytes */
17657113afc8SEmmanuel Vadot return;
17667113afc8SEmmanuel Vadot }
17677113afc8SEmmanuel Vadot
17687113afc8SEmmanuel Vadot if (q_fifo_size <= frame_fifo_size) {
17697113afc8SEmmanuel Vadot /* Between 4096 and max-frame */
17707113afc8SEmmanuel Vadot pdata->rx_rfa[queue] = 2; /* Full - 2048 bytes */
17717113afc8SEmmanuel Vadot pdata->rx_rfd[queue] = 5; /* Full - 3584 bytes */
17727113afc8SEmmanuel Vadot return;
17737113afc8SEmmanuel Vadot }
17747113afc8SEmmanuel Vadot
17757113afc8SEmmanuel Vadot if (q_fifo_size <= (frame_fifo_size * 3)) {
17767113afc8SEmmanuel Vadot /* Between max-frame and 3 max-frames,
17777113afc8SEmmanuel Vadot * trigger if we get just over a frame of data and
17787113afc8SEmmanuel Vadot * resume when we have just under half a frame left.
17797113afc8SEmmanuel Vadot */
17807113afc8SEmmanuel Vadot rfa = q_fifo_size - frame_fifo_size;
17817113afc8SEmmanuel Vadot rfd = rfa + (frame_fifo_size / 2);
17827113afc8SEmmanuel Vadot } else {
17837113afc8SEmmanuel Vadot /* Above 3 max-frames - trigger when just over
17847113afc8SEmmanuel Vadot * 2 frames of space available
17857113afc8SEmmanuel Vadot */
17867113afc8SEmmanuel Vadot rfa = frame_fifo_size * 2;
17877113afc8SEmmanuel Vadot rfa += XGMAC_FLOW_CONTROL_UNIT;
17887113afc8SEmmanuel Vadot rfd = rfa + frame_fifo_size;
17897113afc8SEmmanuel Vadot }
17907113afc8SEmmanuel Vadot
17917113afc8SEmmanuel Vadot pdata->rx_rfa[queue] = XGMAC_FLOW_CONTROL_VALUE(rfa);
17927113afc8SEmmanuel Vadot pdata->rx_rfd[queue] = XGMAC_FLOW_CONTROL_VALUE(rfd);
17937113afc8SEmmanuel Vadot axgbe_printf(1, "%s: forced queue %d rfa 0x%x rfd 0x%x\n", __func__,
17947113afc8SEmmanuel Vadot queue, pdata->rx_rfa[queue], pdata->rx_rfd[queue]);
17957113afc8SEmmanuel Vadot }
17967113afc8SEmmanuel Vadot
17977113afc8SEmmanuel Vadot static void
xgbe_calculate_flow_control_threshold(struct xgbe_prv_data * pdata,unsigned int * fifo)17987113afc8SEmmanuel Vadot xgbe_calculate_flow_control_threshold(struct xgbe_prv_data *pdata,
17997113afc8SEmmanuel Vadot unsigned int *fifo)
18007113afc8SEmmanuel Vadot {
18017113afc8SEmmanuel Vadot unsigned int q_fifo_size;
18027113afc8SEmmanuel Vadot unsigned int i;
18037113afc8SEmmanuel Vadot
18047113afc8SEmmanuel Vadot for (i = 0; i < pdata->rx_q_count; i++) {
18057113afc8SEmmanuel Vadot q_fifo_size = (fifo[i] + 1) * XGMAC_FIFO_UNIT;
18067113afc8SEmmanuel Vadot
18077113afc8SEmmanuel Vadot axgbe_printf(1, "%s: fifo[%d] - 0x%x q_fifo_size 0x%x\n",
18087113afc8SEmmanuel Vadot __func__, i, fifo[i], q_fifo_size);
18097113afc8SEmmanuel Vadot xgbe_queue_flow_control_threshold(pdata, i, q_fifo_size);
18107113afc8SEmmanuel Vadot }
18117113afc8SEmmanuel Vadot }
18127113afc8SEmmanuel Vadot
18137113afc8SEmmanuel Vadot static void
xgbe_config_flow_control_threshold(struct xgbe_prv_data * pdata)18147113afc8SEmmanuel Vadot xgbe_config_flow_control_threshold(struct xgbe_prv_data *pdata)
18157113afc8SEmmanuel Vadot {
18167113afc8SEmmanuel Vadot unsigned int i;
18177113afc8SEmmanuel Vadot
18187113afc8SEmmanuel Vadot for (i = 0; i < pdata->rx_q_count; i++) {
18197113afc8SEmmanuel Vadot axgbe_printf(1, "%s: queue %d rfa %d rfd %d\n", __func__, i,
18207113afc8SEmmanuel Vadot pdata->rx_rfa[i], pdata->rx_rfd[i]);
18217113afc8SEmmanuel Vadot
18227113afc8SEmmanuel Vadot XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFA,
18237113afc8SEmmanuel Vadot pdata->rx_rfa[i]);
18247113afc8SEmmanuel Vadot XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFD,
18257113afc8SEmmanuel Vadot pdata->rx_rfd[i]);
18267113afc8SEmmanuel Vadot
18277113afc8SEmmanuel Vadot axgbe_printf(1, "%s: MTL_Q_RQFCR 0x%x\n", __func__,
18287113afc8SEmmanuel Vadot XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQFCR));
18297113afc8SEmmanuel Vadot }
18307113afc8SEmmanuel Vadot }
18317113afc8SEmmanuel Vadot
18327113afc8SEmmanuel Vadot static unsigned int
xgbe_get_tx_fifo_size(struct xgbe_prv_data * pdata)18337113afc8SEmmanuel Vadot xgbe_get_tx_fifo_size(struct xgbe_prv_data *pdata)
18347113afc8SEmmanuel Vadot {
18357113afc8SEmmanuel Vadot /* The configured value may not be the actual amount of fifo RAM */
18367113afc8SEmmanuel Vadot return (min_t(unsigned int, pdata->tx_max_fifo_size,
18377113afc8SEmmanuel Vadot pdata->hw_feat.tx_fifo_size));
18387113afc8SEmmanuel Vadot }
18397113afc8SEmmanuel Vadot
18407113afc8SEmmanuel Vadot static unsigned int
xgbe_get_rx_fifo_size(struct xgbe_prv_data * pdata)18417113afc8SEmmanuel Vadot xgbe_get_rx_fifo_size(struct xgbe_prv_data *pdata)
18427113afc8SEmmanuel Vadot {
18437113afc8SEmmanuel Vadot /* The configured value may not be the actual amount of fifo RAM */
18447113afc8SEmmanuel Vadot return (min_t(unsigned int, pdata->rx_max_fifo_size,
18457113afc8SEmmanuel Vadot pdata->hw_feat.rx_fifo_size));
18467113afc8SEmmanuel Vadot }
18477113afc8SEmmanuel Vadot
18487113afc8SEmmanuel Vadot static void
xgbe_calculate_equal_fifo(unsigned int fifo_size,unsigned int queue_count,unsigned int * fifo)18497113afc8SEmmanuel Vadot xgbe_calculate_equal_fifo(unsigned int fifo_size, unsigned int queue_count,
18507113afc8SEmmanuel Vadot unsigned int *fifo)
185144b781cfSAndrew Turner {
185244b781cfSAndrew Turner unsigned int q_fifo_size;
185344b781cfSAndrew Turner unsigned int p_fifo;
18547113afc8SEmmanuel Vadot unsigned int i;
185544b781cfSAndrew Turner
18567113afc8SEmmanuel Vadot q_fifo_size = fifo_size / queue_count;
185744b781cfSAndrew Turner
18587113afc8SEmmanuel Vadot /* Calculate the fifo setting by dividing the queue's fifo size
18597113afc8SEmmanuel Vadot * by the fifo allocation increment (with 0 representing the
18607113afc8SEmmanuel Vadot * base allocation increment so decrement the result by 1).
186144b781cfSAndrew Turner */
18627113afc8SEmmanuel Vadot p_fifo = q_fifo_size / XGMAC_FIFO_UNIT;
186344b781cfSAndrew Turner if (p_fifo)
186444b781cfSAndrew Turner p_fifo--;
186544b781cfSAndrew Turner
18667113afc8SEmmanuel Vadot /* Distribute the fifo equally amongst the queues */
18677113afc8SEmmanuel Vadot for (i = 0; i < queue_count; i++)
18687113afc8SEmmanuel Vadot fifo[i] = p_fifo;
186944b781cfSAndrew Turner }
187044b781cfSAndrew Turner
18717113afc8SEmmanuel Vadot static unsigned int
xgbe_set_nonprio_fifos(unsigned int fifo_size,unsigned int queue_count,unsigned int * fifo)18727113afc8SEmmanuel Vadot xgbe_set_nonprio_fifos(unsigned int fifo_size, unsigned int queue_count,
18737113afc8SEmmanuel Vadot unsigned int *fifo)
187444b781cfSAndrew Turner {
187544b781cfSAndrew Turner unsigned int i;
187644b781cfSAndrew Turner
18777113afc8SEmmanuel Vadot MPASS(powerof2(XGMAC_FIFO_MIN_ALLOC));
187844b781cfSAndrew Turner
18797113afc8SEmmanuel Vadot if (queue_count <= IEEE_8021QAZ_MAX_TCS)
18807113afc8SEmmanuel Vadot return (fifo_size);
18817113afc8SEmmanuel Vadot
18827113afc8SEmmanuel Vadot /* Rx queues 9 and up are for specialized packets,
18837113afc8SEmmanuel Vadot * such as PTP or DCB control packets, etc. and
18847113afc8SEmmanuel Vadot * don't require a large fifo
18857113afc8SEmmanuel Vadot */
18867113afc8SEmmanuel Vadot for (i = IEEE_8021QAZ_MAX_TCS; i < queue_count; i++) {
18877113afc8SEmmanuel Vadot fifo[i] = (XGMAC_FIFO_MIN_ALLOC / XGMAC_FIFO_UNIT) - 1;
18887113afc8SEmmanuel Vadot fifo_size -= XGMAC_FIFO_MIN_ALLOC;
188944b781cfSAndrew Turner }
189044b781cfSAndrew Turner
18917113afc8SEmmanuel Vadot return (fifo_size);
18927113afc8SEmmanuel Vadot }
18937113afc8SEmmanuel Vadot
18947113afc8SEmmanuel Vadot static void
xgbe_config_tx_fifo_size(struct xgbe_prv_data * pdata)18957113afc8SEmmanuel Vadot xgbe_config_tx_fifo_size(struct xgbe_prv_data *pdata)
189644b781cfSAndrew Turner {
189744b781cfSAndrew Turner unsigned int fifo_size;
18987113afc8SEmmanuel Vadot unsigned int fifo[XGBE_MAX_QUEUES];
189944b781cfSAndrew Turner unsigned int i;
190044b781cfSAndrew Turner
19017113afc8SEmmanuel Vadot fifo_size = xgbe_get_tx_fifo_size(pdata);
19027113afc8SEmmanuel Vadot axgbe_printf(1, "%s: fifo_size 0x%x\n", __func__, fifo_size);
190344b781cfSAndrew Turner
19047113afc8SEmmanuel Vadot xgbe_calculate_equal_fifo(fifo_size, pdata->tx_q_count, fifo);
19057113afc8SEmmanuel Vadot
19067113afc8SEmmanuel Vadot for (i = 0; i < pdata->tx_q_count; i++) {
19077113afc8SEmmanuel Vadot XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TQS, fifo[i]);
19087113afc8SEmmanuel Vadot axgbe_printf(1, "Tx q %d FIFO Size 0x%x\n", i,
19097113afc8SEmmanuel Vadot XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TQOMR));
191044b781cfSAndrew Turner }
191144b781cfSAndrew Turner
19127113afc8SEmmanuel Vadot axgbe_printf(1, "%d Tx hardware queues, %d byte fifo per queue\n",
19137113afc8SEmmanuel Vadot pdata->tx_q_count, ((fifo[0] + 1) * XGMAC_FIFO_UNIT));
19147113afc8SEmmanuel Vadot }
19157113afc8SEmmanuel Vadot
19167113afc8SEmmanuel Vadot static void
xgbe_config_rx_fifo_size(struct xgbe_prv_data * pdata)19177113afc8SEmmanuel Vadot xgbe_config_rx_fifo_size(struct xgbe_prv_data *pdata)
19187113afc8SEmmanuel Vadot {
19197113afc8SEmmanuel Vadot unsigned int fifo_size;
19207113afc8SEmmanuel Vadot unsigned int fifo[XGBE_MAX_QUEUES];
19217113afc8SEmmanuel Vadot unsigned int prio_queues;
19227113afc8SEmmanuel Vadot unsigned int i;
19237113afc8SEmmanuel Vadot
19247113afc8SEmmanuel Vadot /* TODO - add pfc/ets related support */
19257113afc8SEmmanuel Vadot
19267113afc8SEmmanuel Vadot /* Clear any DCB related fifo/queue information */
19277113afc8SEmmanuel Vadot fifo_size = xgbe_get_rx_fifo_size(pdata);
19287113afc8SEmmanuel Vadot prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count);
19297113afc8SEmmanuel Vadot axgbe_printf(1, "%s: fifo_size 0x%x rx_q_cnt %d prio %d\n", __func__,
19307113afc8SEmmanuel Vadot fifo_size, pdata->rx_q_count, prio_queues);
19317113afc8SEmmanuel Vadot
19327113afc8SEmmanuel Vadot /* Assign a minimum fifo to the non-VLAN priority queues */
19337113afc8SEmmanuel Vadot fifo_size = xgbe_set_nonprio_fifos(fifo_size, pdata->rx_q_count, fifo);
19347113afc8SEmmanuel Vadot
19357113afc8SEmmanuel Vadot xgbe_calculate_equal_fifo(fifo_size, prio_queues, fifo);
19367113afc8SEmmanuel Vadot
19377113afc8SEmmanuel Vadot for (i = 0; i < pdata->rx_q_count; i++) {
19387113afc8SEmmanuel Vadot XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RQS, fifo[i]);
19397113afc8SEmmanuel Vadot axgbe_printf(1, "Rx q %d FIFO Size 0x%x\n", i,
19407113afc8SEmmanuel Vadot XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQOMR));
19417113afc8SEmmanuel Vadot }
19427113afc8SEmmanuel Vadot
19437113afc8SEmmanuel Vadot xgbe_calculate_flow_control_threshold(pdata, fifo);
19447113afc8SEmmanuel Vadot xgbe_config_flow_control_threshold(pdata);
19457113afc8SEmmanuel Vadot
19467113afc8SEmmanuel Vadot axgbe_printf(1, "%u Rx hardware queues, %u byte fifo/queue\n",
19477113afc8SEmmanuel Vadot pdata->rx_q_count, ((fifo[0] + 1) * XGMAC_FIFO_UNIT));
19487113afc8SEmmanuel Vadot }
19497113afc8SEmmanuel Vadot
19507113afc8SEmmanuel Vadot static void
xgbe_config_queue_mapping(struct xgbe_prv_data * pdata)19517113afc8SEmmanuel Vadot xgbe_config_queue_mapping(struct xgbe_prv_data *pdata)
195244b781cfSAndrew Turner {
195344b781cfSAndrew Turner unsigned int qptc, qptc_extra, queue;
195444b781cfSAndrew Turner unsigned int prio_queues;
195544b781cfSAndrew Turner unsigned int ppq, ppq_extra, prio;
195644b781cfSAndrew Turner unsigned int mask;
195744b781cfSAndrew Turner unsigned int i, j, reg, reg_val;
195844b781cfSAndrew Turner
195944b781cfSAndrew Turner /* Map the MTL Tx Queues to Traffic Classes
196044b781cfSAndrew Turner * Note: Tx Queues >= Traffic Classes
196144b781cfSAndrew Turner */
196244b781cfSAndrew Turner qptc = pdata->tx_q_count / pdata->hw_feat.tc_cnt;
196344b781cfSAndrew Turner qptc_extra = pdata->tx_q_count % pdata->hw_feat.tc_cnt;
196444b781cfSAndrew Turner
196544b781cfSAndrew Turner for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) {
196644b781cfSAndrew Turner for (j = 0; j < qptc; j++) {
19677113afc8SEmmanuel Vadot axgbe_printf(1, "TXq%u mapped to TC%u\n", queue, i);
196844b781cfSAndrew Turner XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR,
196944b781cfSAndrew Turner Q2TCMAP, i);
197044b781cfSAndrew Turner pdata->q2tc_map[queue++] = i;
197144b781cfSAndrew Turner }
197244b781cfSAndrew Turner
197344b781cfSAndrew Turner if (i < qptc_extra) {
19747113afc8SEmmanuel Vadot axgbe_printf(1, "TXq%u mapped to TC%u\n", queue, i);
197544b781cfSAndrew Turner XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR,
197644b781cfSAndrew Turner Q2TCMAP, i);
197744b781cfSAndrew Turner pdata->q2tc_map[queue++] = i;
197844b781cfSAndrew Turner }
197944b781cfSAndrew Turner }
198044b781cfSAndrew Turner
198144b781cfSAndrew Turner /* Map the 8 VLAN priority values to available MTL Rx queues */
19827113afc8SEmmanuel Vadot prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count);
198344b781cfSAndrew Turner ppq = IEEE_8021QAZ_MAX_TCS / prio_queues;
198444b781cfSAndrew Turner ppq_extra = IEEE_8021QAZ_MAX_TCS % prio_queues;
198544b781cfSAndrew Turner
198644b781cfSAndrew Turner reg = MAC_RQC2R;
198744b781cfSAndrew Turner reg_val = 0;
198844b781cfSAndrew Turner for (i = 0, prio = 0; i < prio_queues;) {
198944b781cfSAndrew Turner mask = 0;
199044b781cfSAndrew Turner for (j = 0; j < ppq; j++) {
19917113afc8SEmmanuel Vadot axgbe_printf(1, "PRIO%u mapped to RXq%u\n", prio, i);
199244b781cfSAndrew Turner mask |= (1 << prio);
199344b781cfSAndrew Turner pdata->prio2q_map[prio++] = i;
199444b781cfSAndrew Turner }
199544b781cfSAndrew Turner
199644b781cfSAndrew Turner if (i < ppq_extra) {
19977113afc8SEmmanuel Vadot axgbe_printf(1, "PRIO%u mapped to RXq%u\n", prio, i);
199844b781cfSAndrew Turner mask |= (1 << prio);
199944b781cfSAndrew Turner pdata->prio2q_map[prio++] = i;
200044b781cfSAndrew Turner }
200144b781cfSAndrew Turner
200244b781cfSAndrew Turner reg_val |= (mask << ((i++ % MAC_RQC2_Q_PER_REG) << 3));
200344b781cfSAndrew Turner
200444b781cfSAndrew Turner if ((i % MAC_RQC2_Q_PER_REG) && (i != prio_queues))
200544b781cfSAndrew Turner continue;
200644b781cfSAndrew Turner
200744b781cfSAndrew Turner XGMAC_IOWRITE(pdata, reg, reg_val);
200844b781cfSAndrew Turner reg += MAC_RQC2_INC;
200944b781cfSAndrew Turner reg_val = 0;
201044b781cfSAndrew Turner }
201144b781cfSAndrew Turner
201244b781cfSAndrew Turner /* Select dynamic mapping of MTL Rx queue to DMA Rx channel */
201344b781cfSAndrew Turner reg = MTL_RQDCM0R;
201444b781cfSAndrew Turner reg_val = 0;
201544b781cfSAndrew Turner for (i = 0; i < pdata->rx_q_count;) {
201644b781cfSAndrew Turner reg_val |= (0x80 << ((i++ % MTL_RQDCM_Q_PER_REG) << 3));
201744b781cfSAndrew Turner
201844b781cfSAndrew Turner if ((i % MTL_RQDCM_Q_PER_REG) && (i != pdata->rx_q_count))
201944b781cfSAndrew Turner continue;
202044b781cfSAndrew Turner
202144b781cfSAndrew Turner XGMAC_IOWRITE(pdata, reg, reg_val);
202244b781cfSAndrew Turner
202344b781cfSAndrew Turner reg += MTL_RQDCM_INC;
202444b781cfSAndrew Turner reg_val = 0;
202544b781cfSAndrew Turner }
202644b781cfSAndrew Turner }
202744b781cfSAndrew Turner
20287113afc8SEmmanuel Vadot static void
xgbe_config_mac_address(struct xgbe_prv_data * pdata)20297113afc8SEmmanuel Vadot xgbe_config_mac_address(struct xgbe_prv_data *pdata)
203044b781cfSAndrew Turner {
2031402810d3SJustin Hibbits xgbe_set_mac_address(pdata, if_getlladdr(pdata->netdev));
20327113afc8SEmmanuel Vadot
20332b8df536SStephan de Wit /*
20342b8df536SStephan de Wit * Promisc mode does not work as intended. Multicast traffic
20352b8df536SStephan de Wit * is triggering the filter, so enable Receive All.
20362b8df536SStephan de Wit */
20372b8df536SStephan de Wit XGMAC_IOWRITE_BITS(pdata, MAC_PFR, RA, 1);
20382b8df536SStephan de Wit
20397113afc8SEmmanuel Vadot /* Filtering is done using perfect filtering and hash filtering */
20407113afc8SEmmanuel Vadot if (pdata->hw_feat.hash_table_size) {
20417113afc8SEmmanuel Vadot XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1);
20427113afc8SEmmanuel Vadot XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1);
20437113afc8SEmmanuel Vadot XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HMC, 1);
20447113afc8SEmmanuel Vadot }
204544b781cfSAndrew Turner }
204644b781cfSAndrew Turner
20477113afc8SEmmanuel Vadot static void
xgbe_config_jumbo_enable(struct xgbe_prv_data * pdata)20487113afc8SEmmanuel Vadot xgbe_config_jumbo_enable(struct xgbe_prv_data *pdata)
204944b781cfSAndrew Turner {
205044b781cfSAndrew Turner unsigned int val;
205144b781cfSAndrew Turner
20529c6d6488SAndrew Turner val = (if_getmtu(pdata->netdev) > XGMAC_STD_PACKET_MTU) ? 1 : 0;
205344b781cfSAndrew Turner
205444b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val);
205544b781cfSAndrew Turner }
205644b781cfSAndrew Turner
20577113afc8SEmmanuel Vadot static void
xgbe_config_mac_speed(struct xgbe_prv_data * pdata)20587113afc8SEmmanuel Vadot xgbe_config_mac_speed(struct xgbe_prv_data *pdata)
205944b781cfSAndrew Turner {
20607113afc8SEmmanuel Vadot xgbe_set_speed(pdata, pdata->phy_speed);
206144b781cfSAndrew Turner }
206244b781cfSAndrew Turner
20637113afc8SEmmanuel Vadot static void
xgbe_config_checksum_offload(struct xgbe_prv_data * pdata)20647113afc8SEmmanuel Vadot xgbe_config_checksum_offload(struct xgbe_prv_data *pdata)
206544b781cfSAndrew Turner {
20667113afc8SEmmanuel Vadot if ((if_getcapenable(pdata->netdev) & IFCAP_RXCSUM))
206744b781cfSAndrew Turner xgbe_enable_rx_csum(pdata);
206844b781cfSAndrew Turner else
206944b781cfSAndrew Turner xgbe_disable_rx_csum(pdata);
207044b781cfSAndrew Turner }
207144b781cfSAndrew Turner
20727113afc8SEmmanuel Vadot static void
xgbe_config_vlan_support(struct xgbe_prv_data * pdata)20737113afc8SEmmanuel Vadot xgbe_config_vlan_support(struct xgbe_prv_data *pdata)
207444b781cfSAndrew Turner {
207544b781cfSAndrew Turner /* Indicate that VLAN Tx CTAGs come from context descriptors */
207644b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0);
207744b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1);
207844b781cfSAndrew Turner
207944b781cfSAndrew Turner /* Set the current VLAN Hash Table register value */
208044b781cfSAndrew Turner xgbe_update_vlan_hash_table(pdata);
208144b781cfSAndrew Turner
20827113afc8SEmmanuel Vadot if ((if_getcapenable(pdata->netdev) & IFCAP_VLAN_HWFILTER)) {
20837113afc8SEmmanuel Vadot axgbe_printf(1, "Enabling rx vlan filtering\n");
20847113afc8SEmmanuel Vadot xgbe_enable_rx_vlan_filtering(pdata);
20857113afc8SEmmanuel Vadot } else {
20867113afc8SEmmanuel Vadot axgbe_printf(1, "Disabling rx vlan filtering\n");
208744b781cfSAndrew Turner xgbe_disable_rx_vlan_filtering(pdata);
208844b781cfSAndrew Turner }
208944b781cfSAndrew Turner
20907113afc8SEmmanuel Vadot if ((if_getcapenable(pdata->netdev) & IFCAP_VLAN_HWTAGGING)) {
20917113afc8SEmmanuel Vadot axgbe_printf(1, "Enabling rx vlan stripping\n");
20927113afc8SEmmanuel Vadot xgbe_enable_rx_vlan_stripping(pdata);
20937113afc8SEmmanuel Vadot } else {
20947113afc8SEmmanuel Vadot axgbe_printf(1, "Disabling rx vlan stripping\n");
20957113afc8SEmmanuel Vadot xgbe_disable_rx_vlan_stripping(pdata);
20967113afc8SEmmanuel Vadot }
20977113afc8SEmmanuel Vadot }
20987113afc8SEmmanuel Vadot
20997113afc8SEmmanuel Vadot static uint64_t
xgbe_mmc_read(struct xgbe_prv_data * pdata,unsigned int reg_lo)21007113afc8SEmmanuel Vadot xgbe_mmc_read(struct xgbe_prv_data *pdata, unsigned int reg_lo)
210144b781cfSAndrew Turner {
210244b781cfSAndrew Turner bool read_hi;
21037113afc8SEmmanuel Vadot uint64_t val;
210444b781cfSAndrew Turner
21057113afc8SEmmanuel Vadot if (pdata->vdata->mmc_64bit) {
21067113afc8SEmmanuel Vadot switch (reg_lo) {
21077113afc8SEmmanuel Vadot /* These registers are always 32 bit */
21087113afc8SEmmanuel Vadot case MMC_RXRUNTERROR:
21097113afc8SEmmanuel Vadot case MMC_RXJABBERERROR:
21107113afc8SEmmanuel Vadot case MMC_RXUNDERSIZE_G:
21117113afc8SEmmanuel Vadot case MMC_RXOVERSIZE_G:
21127113afc8SEmmanuel Vadot case MMC_RXWATCHDOGERROR:
21137113afc8SEmmanuel Vadot read_hi = false;
21147113afc8SEmmanuel Vadot break;
21157113afc8SEmmanuel Vadot
21167113afc8SEmmanuel Vadot default:
21177113afc8SEmmanuel Vadot read_hi = true;
21187113afc8SEmmanuel Vadot }
21197113afc8SEmmanuel Vadot } else {
212044b781cfSAndrew Turner switch (reg_lo) {
212144b781cfSAndrew Turner /* These registers are always 64 bit */
212244b781cfSAndrew Turner case MMC_TXOCTETCOUNT_GB_LO:
212344b781cfSAndrew Turner case MMC_TXOCTETCOUNT_G_LO:
212444b781cfSAndrew Turner case MMC_RXOCTETCOUNT_GB_LO:
212544b781cfSAndrew Turner case MMC_RXOCTETCOUNT_G_LO:
212644b781cfSAndrew Turner read_hi = true;
212744b781cfSAndrew Turner break;
212844b781cfSAndrew Turner
212944b781cfSAndrew Turner default:
213044b781cfSAndrew Turner read_hi = false;
213144b781cfSAndrew Turner }
21327113afc8SEmmanuel Vadot }
213344b781cfSAndrew Turner
213444b781cfSAndrew Turner val = XGMAC_IOREAD(pdata, reg_lo);
213544b781cfSAndrew Turner
213644b781cfSAndrew Turner if (read_hi)
21377113afc8SEmmanuel Vadot val |= ((uint64_t)XGMAC_IOREAD(pdata, reg_lo + 4) << 32);
213844b781cfSAndrew Turner
21397113afc8SEmmanuel Vadot return (val);
214044b781cfSAndrew Turner }
214144b781cfSAndrew Turner
21427113afc8SEmmanuel Vadot static void
xgbe_tx_mmc_int(struct xgbe_prv_data * pdata)21437113afc8SEmmanuel Vadot xgbe_tx_mmc_int(struct xgbe_prv_data *pdata)
214444b781cfSAndrew Turner {
214544b781cfSAndrew Turner struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
214644b781cfSAndrew Turner unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_TISR);
214744b781cfSAndrew Turner
214844b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_GB))
214944b781cfSAndrew Turner stats->txoctetcount_gb +=
215044b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO);
215144b781cfSAndrew Turner
215244b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_GB))
215344b781cfSAndrew Turner stats->txframecount_gb +=
215444b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO);
215544b781cfSAndrew Turner
215644b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_G))
215744b781cfSAndrew Turner stats->txbroadcastframes_g +=
215844b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO);
215944b781cfSAndrew Turner
216044b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_G))
216144b781cfSAndrew Turner stats->txmulticastframes_g +=
216244b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO);
216344b781cfSAndrew Turner
216444b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX64OCTETS_GB))
216544b781cfSAndrew Turner stats->tx64octets_gb +=
216644b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO);
216744b781cfSAndrew Turner
216844b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX65TO127OCTETS_GB))
216944b781cfSAndrew Turner stats->tx65to127octets_gb +=
217044b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO);
217144b781cfSAndrew Turner
217244b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX128TO255OCTETS_GB))
217344b781cfSAndrew Turner stats->tx128to255octets_gb +=
217444b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO);
217544b781cfSAndrew Turner
217644b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX256TO511OCTETS_GB))
217744b781cfSAndrew Turner stats->tx256to511octets_gb +=
217844b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO);
217944b781cfSAndrew Turner
218044b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX512TO1023OCTETS_GB))
218144b781cfSAndrew Turner stats->tx512to1023octets_gb +=
218244b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO);
218344b781cfSAndrew Turner
218444b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX1024TOMAXOCTETS_GB))
218544b781cfSAndrew Turner stats->tx1024tomaxoctets_gb +=
218644b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO);
218744b781cfSAndrew Turner
218844b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNICASTFRAMES_GB))
218944b781cfSAndrew Turner stats->txunicastframes_gb +=
219044b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO);
219144b781cfSAndrew Turner
219244b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_GB))
219344b781cfSAndrew Turner stats->txmulticastframes_gb +=
219444b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO);
219544b781cfSAndrew Turner
219644b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_GB))
219744b781cfSAndrew Turner stats->txbroadcastframes_g +=
219844b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO);
219944b781cfSAndrew Turner
220044b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNDERFLOWERROR))
220144b781cfSAndrew Turner stats->txunderflowerror +=
220244b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO);
220344b781cfSAndrew Turner
220444b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_G))
220544b781cfSAndrew Turner stats->txoctetcount_g +=
220644b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO);
220744b781cfSAndrew Turner
220844b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_G))
220944b781cfSAndrew Turner stats->txframecount_g +=
221044b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO);
221144b781cfSAndrew Turner
221244b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXPAUSEFRAMES))
221344b781cfSAndrew Turner stats->txpauseframes +=
221444b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO);
221544b781cfSAndrew Turner
221644b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXVLANFRAMES_G))
221744b781cfSAndrew Turner stats->txvlanframes_g +=
221844b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO);
221944b781cfSAndrew Turner }
222044b781cfSAndrew Turner
22217113afc8SEmmanuel Vadot static void
xgbe_rx_mmc_int(struct xgbe_prv_data * pdata)22227113afc8SEmmanuel Vadot xgbe_rx_mmc_int(struct xgbe_prv_data *pdata)
222344b781cfSAndrew Turner {
222444b781cfSAndrew Turner struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
222544b781cfSAndrew Turner unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_RISR);
222644b781cfSAndrew Turner
222744b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFRAMECOUNT_GB))
222844b781cfSAndrew Turner stats->rxframecount_gb +=
222944b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO);
223044b781cfSAndrew Turner
223144b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_GB))
223244b781cfSAndrew Turner stats->rxoctetcount_gb +=
223344b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO);
223444b781cfSAndrew Turner
223544b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_G))
223644b781cfSAndrew Turner stats->rxoctetcount_g +=
223744b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO);
223844b781cfSAndrew Turner
223944b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXBROADCASTFRAMES_G))
224044b781cfSAndrew Turner stats->rxbroadcastframes_g +=
224144b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO);
224244b781cfSAndrew Turner
224344b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXMULTICASTFRAMES_G))
224444b781cfSAndrew Turner stats->rxmulticastframes_g +=
224544b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO);
224644b781cfSAndrew Turner
224744b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXCRCERROR))
224844b781cfSAndrew Turner stats->rxcrcerror +=
224944b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO);
225044b781cfSAndrew Turner
225144b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXRUNTERROR))
225244b781cfSAndrew Turner stats->rxrunterror +=
225344b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXRUNTERROR);
225444b781cfSAndrew Turner
225544b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXJABBERERROR))
225644b781cfSAndrew Turner stats->rxjabbererror +=
225744b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXJABBERERROR);
225844b781cfSAndrew Turner
225944b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNDERSIZE_G))
226044b781cfSAndrew Turner stats->rxundersize_g +=
226144b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G);
226244b781cfSAndrew Turner
226344b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOVERSIZE_G))
226444b781cfSAndrew Turner stats->rxoversize_g +=
226544b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G);
226644b781cfSAndrew Turner
226744b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX64OCTETS_GB))
226844b781cfSAndrew Turner stats->rx64octets_gb +=
226944b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO);
227044b781cfSAndrew Turner
227144b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX65TO127OCTETS_GB))
227244b781cfSAndrew Turner stats->rx65to127octets_gb +=
227344b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO);
227444b781cfSAndrew Turner
227544b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX128TO255OCTETS_GB))
227644b781cfSAndrew Turner stats->rx128to255octets_gb +=
227744b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO);
227844b781cfSAndrew Turner
227944b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX256TO511OCTETS_GB))
228044b781cfSAndrew Turner stats->rx256to511octets_gb +=
228144b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO);
228244b781cfSAndrew Turner
228344b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX512TO1023OCTETS_GB))
228444b781cfSAndrew Turner stats->rx512to1023octets_gb +=
228544b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO);
228644b781cfSAndrew Turner
228744b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX1024TOMAXOCTETS_GB))
228844b781cfSAndrew Turner stats->rx1024tomaxoctets_gb +=
228944b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO);
229044b781cfSAndrew Turner
229144b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNICASTFRAMES_G))
229244b781cfSAndrew Turner stats->rxunicastframes_g +=
229344b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO);
229444b781cfSAndrew Turner
229544b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXLENGTHERROR))
229644b781cfSAndrew Turner stats->rxlengtherror +=
229744b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO);
229844b781cfSAndrew Turner
229944b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOUTOFRANGETYPE))
230044b781cfSAndrew Turner stats->rxoutofrangetype +=
230144b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO);
230244b781cfSAndrew Turner
230344b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXPAUSEFRAMES))
230444b781cfSAndrew Turner stats->rxpauseframes +=
230544b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO);
230644b781cfSAndrew Turner
230744b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFIFOOVERFLOW))
230844b781cfSAndrew Turner stats->rxfifooverflow +=
230944b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO);
231044b781cfSAndrew Turner
231144b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXVLANFRAMES_GB))
231244b781cfSAndrew Turner stats->rxvlanframes_gb +=
231344b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO);
231444b781cfSAndrew Turner
231544b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXWATCHDOGERROR))
231644b781cfSAndrew Turner stats->rxwatchdogerror +=
231744b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR);
231844b781cfSAndrew Turner }
231944b781cfSAndrew Turner
23207113afc8SEmmanuel Vadot static void
xgbe_read_mmc_stats(struct xgbe_prv_data * pdata)23217113afc8SEmmanuel Vadot xgbe_read_mmc_stats(struct xgbe_prv_data *pdata)
232244b781cfSAndrew Turner {
232344b781cfSAndrew Turner struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
232444b781cfSAndrew Turner
232544b781cfSAndrew Turner /* Freeze counters */
232644b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1);
232744b781cfSAndrew Turner
232844b781cfSAndrew Turner stats->txoctetcount_gb +=
232944b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO);
233044b781cfSAndrew Turner
233144b781cfSAndrew Turner stats->txframecount_gb +=
233244b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO);
233344b781cfSAndrew Turner
233444b781cfSAndrew Turner stats->txbroadcastframes_g +=
233544b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO);
233644b781cfSAndrew Turner
233744b781cfSAndrew Turner stats->txmulticastframes_g +=
233844b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO);
233944b781cfSAndrew Turner
234044b781cfSAndrew Turner stats->tx64octets_gb +=
234144b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO);
234244b781cfSAndrew Turner
234344b781cfSAndrew Turner stats->tx65to127octets_gb +=
234444b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO);
234544b781cfSAndrew Turner
234644b781cfSAndrew Turner stats->tx128to255octets_gb +=
234744b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO);
234844b781cfSAndrew Turner
234944b781cfSAndrew Turner stats->tx256to511octets_gb +=
235044b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO);
235144b781cfSAndrew Turner
235244b781cfSAndrew Turner stats->tx512to1023octets_gb +=
235344b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO);
235444b781cfSAndrew Turner
235544b781cfSAndrew Turner stats->tx1024tomaxoctets_gb +=
235644b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO);
235744b781cfSAndrew Turner
235844b781cfSAndrew Turner stats->txunicastframes_gb +=
235944b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO);
236044b781cfSAndrew Turner
236144b781cfSAndrew Turner stats->txmulticastframes_gb +=
236244b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO);
236344b781cfSAndrew Turner
23647113afc8SEmmanuel Vadot stats->txbroadcastframes_gb +=
236544b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO);
236644b781cfSAndrew Turner
236744b781cfSAndrew Turner stats->txunderflowerror +=
236844b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO);
236944b781cfSAndrew Turner
237044b781cfSAndrew Turner stats->txoctetcount_g +=
237144b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO);
237244b781cfSAndrew Turner
237344b781cfSAndrew Turner stats->txframecount_g +=
237444b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO);
237544b781cfSAndrew Turner
237644b781cfSAndrew Turner stats->txpauseframes +=
237744b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO);
237844b781cfSAndrew Turner
237944b781cfSAndrew Turner stats->txvlanframes_g +=
238044b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO);
238144b781cfSAndrew Turner
238244b781cfSAndrew Turner stats->rxframecount_gb +=
238344b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO);
238444b781cfSAndrew Turner
238544b781cfSAndrew Turner stats->rxoctetcount_gb +=
238644b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO);
238744b781cfSAndrew Turner
238844b781cfSAndrew Turner stats->rxoctetcount_g +=
238944b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO);
239044b781cfSAndrew Turner
239144b781cfSAndrew Turner stats->rxbroadcastframes_g +=
239244b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO);
239344b781cfSAndrew Turner
239444b781cfSAndrew Turner stats->rxmulticastframes_g +=
239544b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO);
239644b781cfSAndrew Turner
239744b781cfSAndrew Turner stats->rxcrcerror +=
239844b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO);
239944b781cfSAndrew Turner
240044b781cfSAndrew Turner stats->rxrunterror +=
240144b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXRUNTERROR);
240244b781cfSAndrew Turner
240344b781cfSAndrew Turner stats->rxjabbererror +=
240444b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXJABBERERROR);
240544b781cfSAndrew Turner
240644b781cfSAndrew Turner stats->rxundersize_g +=
240744b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G);
240844b781cfSAndrew Turner
240944b781cfSAndrew Turner stats->rxoversize_g +=
241044b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G);
241144b781cfSAndrew Turner
241244b781cfSAndrew Turner stats->rx64octets_gb +=
241344b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO);
241444b781cfSAndrew Turner
241544b781cfSAndrew Turner stats->rx65to127octets_gb +=
241644b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO);
241744b781cfSAndrew Turner
241844b781cfSAndrew Turner stats->rx128to255octets_gb +=
241944b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO);
242044b781cfSAndrew Turner
242144b781cfSAndrew Turner stats->rx256to511octets_gb +=
242244b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO);
242344b781cfSAndrew Turner
242444b781cfSAndrew Turner stats->rx512to1023octets_gb +=
242544b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO);
242644b781cfSAndrew Turner
242744b781cfSAndrew Turner stats->rx1024tomaxoctets_gb +=
242844b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO);
242944b781cfSAndrew Turner
243044b781cfSAndrew Turner stats->rxunicastframes_g +=
243144b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO);
243244b781cfSAndrew Turner
243344b781cfSAndrew Turner stats->rxlengtherror +=
243444b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO);
243544b781cfSAndrew Turner
243644b781cfSAndrew Turner stats->rxoutofrangetype +=
243744b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO);
243844b781cfSAndrew Turner
243944b781cfSAndrew Turner stats->rxpauseframes +=
244044b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO);
244144b781cfSAndrew Turner
244244b781cfSAndrew Turner stats->rxfifooverflow +=
244344b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO);
244444b781cfSAndrew Turner
244544b781cfSAndrew Turner stats->rxvlanframes_gb +=
244644b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO);
244744b781cfSAndrew Turner
244844b781cfSAndrew Turner stats->rxwatchdogerror +=
244944b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR);
245044b781cfSAndrew Turner
245144b781cfSAndrew Turner /* Un-freeze counters */
245244b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0);
245344b781cfSAndrew Turner }
245444b781cfSAndrew Turner
24557113afc8SEmmanuel Vadot static void
xgbe_config_mmc(struct xgbe_prv_data * pdata)24567113afc8SEmmanuel Vadot xgbe_config_mmc(struct xgbe_prv_data *pdata)
245744b781cfSAndrew Turner {
245844b781cfSAndrew Turner /* Set counters to reset on read */
245944b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MMC_CR, ROR, 1);
246044b781cfSAndrew Turner
246144b781cfSAndrew Turner /* Reset the counters */
246244b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MMC_CR, CR, 1);
246344b781cfSAndrew Turner }
246444b781cfSAndrew Turner
24657113afc8SEmmanuel Vadot static void
xgbe_txq_prepare_tx_stop(struct xgbe_prv_data * pdata,unsigned int queue)24667113afc8SEmmanuel Vadot xgbe_txq_prepare_tx_stop(struct xgbe_prv_data *pdata, unsigned int queue)
24677113afc8SEmmanuel Vadot {
24687113afc8SEmmanuel Vadot unsigned int tx_status;
24697113afc8SEmmanuel Vadot unsigned long tx_timeout;
24707113afc8SEmmanuel Vadot
24717113afc8SEmmanuel Vadot /* The Tx engine cannot be stopped if it is actively processing
24727113afc8SEmmanuel Vadot * packets. Wait for the Tx queue to empty the Tx fifo. Don't
24737113afc8SEmmanuel Vadot * wait forever though...
24747113afc8SEmmanuel Vadot */
24757113afc8SEmmanuel Vadot tx_timeout = ticks + (XGBE_DMA_STOP_TIMEOUT * hz);
24767113afc8SEmmanuel Vadot while (ticks < tx_timeout) {
24777113afc8SEmmanuel Vadot tx_status = XGMAC_MTL_IOREAD(pdata, queue, MTL_Q_TQDR);
24787113afc8SEmmanuel Vadot if ((XGMAC_GET_BITS(tx_status, MTL_Q_TQDR, TRCSTS) != 1) &&
24797113afc8SEmmanuel Vadot (XGMAC_GET_BITS(tx_status, MTL_Q_TQDR, TXQSTS) == 0))
24807113afc8SEmmanuel Vadot break;
24817113afc8SEmmanuel Vadot
24827113afc8SEmmanuel Vadot DELAY(500);
24837113afc8SEmmanuel Vadot }
24847113afc8SEmmanuel Vadot
24857113afc8SEmmanuel Vadot if (ticks >= tx_timeout)
24867113afc8SEmmanuel Vadot axgbe_printf(1, "timed out waiting for Tx queue %u to empty\n",
24877113afc8SEmmanuel Vadot queue);
24887113afc8SEmmanuel Vadot }
24897113afc8SEmmanuel Vadot
24907113afc8SEmmanuel Vadot static void
xgbe_prepare_tx_stop(struct xgbe_prv_data * pdata,unsigned int queue)24917113afc8SEmmanuel Vadot xgbe_prepare_tx_stop(struct xgbe_prv_data *pdata, unsigned int queue)
249244b781cfSAndrew Turner {
249344b781cfSAndrew Turner unsigned int tx_dsr, tx_pos, tx_qidx;
249444b781cfSAndrew Turner unsigned int tx_status;
249544b781cfSAndrew Turner unsigned long tx_timeout;
249644b781cfSAndrew Turner
24977113afc8SEmmanuel Vadot if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) > 0x20)
24987113afc8SEmmanuel Vadot return (xgbe_txq_prepare_tx_stop(pdata, queue));
24997113afc8SEmmanuel Vadot
250044b781cfSAndrew Turner /* Calculate the status register to read and the position within */
25017113afc8SEmmanuel Vadot if (queue < DMA_DSRX_FIRST_QUEUE) {
250244b781cfSAndrew Turner tx_dsr = DMA_DSR0;
25037113afc8SEmmanuel Vadot tx_pos = (queue * DMA_DSR_Q_WIDTH) + DMA_DSR0_TPS_START;
250444b781cfSAndrew Turner } else {
25057113afc8SEmmanuel Vadot tx_qidx = queue - DMA_DSRX_FIRST_QUEUE;
250644b781cfSAndrew Turner
250744b781cfSAndrew Turner tx_dsr = DMA_DSR1 + ((tx_qidx / DMA_DSRX_QPR) * DMA_DSRX_INC);
250844b781cfSAndrew Turner tx_pos = ((tx_qidx % DMA_DSRX_QPR) * DMA_DSR_Q_WIDTH) +
250944b781cfSAndrew Turner DMA_DSRX_TPS_START;
251044b781cfSAndrew Turner }
251144b781cfSAndrew Turner
251244b781cfSAndrew Turner /* The Tx engine cannot be stopped if it is actively processing
251344b781cfSAndrew Turner * descriptors. Wait for the Tx engine to enter the stopped or
251444b781cfSAndrew Turner * suspended state. Don't wait forever though...
251544b781cfSAndrew Turner */
25169c6d6488SAndrew Turner tx_timeout = ticks + (XGBE_DMA_STOP_TIMEOUT * hz);
25179c6d6488SAndrew Turner while (ticks < tx_timeout) {
251844b781cfSAndrew Turner tx_status = XGMAC_IOREAD(pdata, tx_dsr);
251944b781cfSAndrew Turner tx_status = GET_BITS(tx_status, tx_pos, DMA_DSR_TPS_WIDTH);
252044b781cfSAndrew Turner if ((tx_status == DMA_TPS_STOPPED) ||
252144b781cfSAndrew Turner (tx_status == DMA_TPS_SUSPENDED))
252244b781cfSAndrew Turner break;
252344b781cfSAndrew Turner
25249c6d6488SAndrew Turner DELAY(500);
252544b781cfSAndrew Turner }
25267113afc8SEmmanuel Vadot
25277113afc8SEmmanuel Vadot if (ticks >= tx_timeout)
25287113afc8SEmmanuel Vadot axgbe_printf(1, "timed out waiting for Tx DMA channel %u to stop\n",
25297113afc8SEmmanuel Vadot queue);
253044b781cfSAndrew Turner }
253144b781cfSAndrew Turner
25327113afc8SEmmanuel Vadot static void
xgbe_enable_tx(struct xgbe_prv_data * pdata)25337113afc8SEmmanuel Vadot xgbe_enable_tx(struct xgbe_prv_data *pdata)
253444b781cfSAndrew Turner {
253544b781cfSAndrew Turner unsigned int i;
253644b781cfSAndrew Turner
253744b781cfSAndrew Turner /* Enable each Tx DMA channel */
25387113afc8SEmmanuel Vadot for (i = 0; i < pdata->channel_count; i++) {
25397113afc8SEmmanuel Vadot if (!pdata->channel[i]->tx_ring)
254044b781cfSAndrew Turner break;
254144b781cfSAndrew Turner
25427113afc8SEmmanuel Vadot XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1);
254344b781cfSAndrew Turner }
254444b781cfSAndrew Turner
254544b781cfSAndrew Turner /* Enable each Tx queue */
254644b781cfSAndrew Turner for (i = 0; i < pdata->tx_q_count; i++)
254744b781cfSAndrew Turner XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN,
254844b781cfSAndrew Turner MTL_Q_ENABLED);
254944b781cfSAndrew Turner
255044b781cfSAndrew Turner /* Enable MAC Tx */
255144b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1);
255244b781cfSAndrew Turner }
255344b781cfSAndrew Turner
25547113afc8SEmmanuel Vadot static void
xgbe_disable_tx(struct xgbe_prv_data * pdata)25557113afc8SEmmanuel Vadot xgbe_disable_tx(struct xgbe_prv_data *pdata)
255644b781cfSAndrew Turner {
255744b781cfSAndrew Turner unsigned int i;
255844b781cfSAndrew Turner
255944b781cfSAndrew Turner /* Prepare for Tx DMA channel stop */
25607113afc8SEmmanuel Vadot for (i = 0; i < pdata->tx_q_count; i++)
25617113afc8SEmmanuel Vadot xgbe_prepare_tx_stop(pdata, i);
256244b781cfSAndrew Turner
256344b781cfSAndrew Turner /* Disable MAC Tx */
256444b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0);
256544b781cfSAndrew Turner
256644b781cfSAndrew Turner /* Disable each Tx queue */
256744b781cfSAndrew Turner for (i = 0; i < pdata->tx_q_count; i++)
256844b781cfSAndrew Turner XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 0);
256944b781cfSAndrew Turner
257044b781cfSAndrew Turner /* Disable each Tx DMA channel */
25717113afc8SEmmanuel Vadot for (i = 0; i < pdata->channel_count; i++) {
25727113afc8SEmmanuel Vadot if (!pdata->channel[i]->tx_ring)
257344b781cfSAndrew Turner break;
257444b781cfSAndrew Turner
25757113afc8SEmmanuel Vadot XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0);
257644b781cfSAndrew Turner }
257744b781cfSAndrew Turner }
257844b781cfSAndrew Turner
25797113afc8SEmmanuel Vadot static void
xgbe_prepare_rx_stop(struct xgbe_prv_data * pdata,unsigned int queue)25807113afc8SEmmanuel Vadot xgbe_prepare_rx_stop(struct xgbe_prv_data *pdata, unsigned int queue)
258144b781cfSAndrew Turner {
258244b781cfSAndrew Turner unsigned int rx_status;
258344b781cfSAndrew Turner unsigned long rx_timeout;
258444b781cfSAndrew Turner
258544b781cfSAndrew Turner /* The Rx engine cannot be stopped if it is actively processing
258644b781cfSAndrew Turner * packets. Wait for the Rx queue to empty the Rx fifo. Don't
258744b781cfSAndrew Turner * wait forever though...
258844b781cfSAndrew Turner */
25899c6d6488SAndrew Turner rx_timeout = ticks + (XGBE_DMA_STOP_TIMEOUT * hz);
25909c6d6488SAndrew Turner while (ticks < rx_timeout) {
259144b781cfSAndrew Turner rx_status = XGMAC_MTL_IOREAD(pdata, queue, MTL_Q_RQDR);
259244b781cfSAndrew Turner if ((XGMAC_GET_BITS(rx_status, MTL_Q_RQDR, PRXQ) == 0) &&
259344b781cfSAndrew Turner (XGMAC_GET_BITS(rx_status, MTL_Q_RQDR, RXQSTS) == 0))
259444b781cfSAndrew Turner break;
259544b781cfSAndrew Turner
25969c6d6488SAndrew Turner DELAY(500);
259744b781cfSAndrew Turner }
25987113afc8SEmmanuel Vadot
25997113afc8SEmmanuel Vadot if (ticks >= rx_timeout)
26007113afc8SEmmanuel Vadot axgbe_printf(1, "timed out waiting for Rx queue %d to empty\n",
26017113afc8SEmmanuel Vadot queue);
260244b781cfSAndrew Turner }
260344b781cfSAndrew Turner
26047113afc8SEmmanuel Vadot static void
xgbe_enable_rx(struct xgbe_prv_data * pdata)26057113afc8SEmmanuel Vadot xgbe_enable_rx(struct xgbe_prv_data *pdata)
260644b781cfSAndrew Turner {
260744b781cfSAndrew Turner unsigned int reg_val, i;
260844b781cfSAndrew Turner
260944b781cfSAndrew Turner /* Enable each Rx DMA channel */
26107113afc8SEmmanuel Vadot for (i = 0; i < pdata->channel_count; i++) {
26117113afc8SEmmanuel Vadot if (!pdata->channel[i]->rx_ring)
261244b781cfSAndrew Turner break;
261344b781cfSAndrew Turner
26147113afc8SEmmanuel Vadot XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1);
261544b781cfSAndrew Turner }
261644b781cfSAndrew Turner
261744b781cfSAndrew Turner /* Enable each Rx queue */
261844b781cfSAndrew Turner reg_val = 0;
261944b781cfSAndrew Turner for (i = 0; i < pdata->rx_q_count; i++)
262044b781cfSAndrew Turner reg_val |= (0x02 << (i << 1));
262144b781cfSAndrew Turner XGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val);
262244b781cfSAndrew Turner
262344b781cfSAndrew Turner /* Enable MAC Rx */
262444b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 1);
262544b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1);
262644b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1);
262744b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1);
262844b781cfSAndrew Turner }
262944b781cfSAndrew Turner
26307113afc8SEmmanuel Vadot static void
xgbe_disable_rx(struct xgbe_prv_data * pdata)26317113afc8SEmmanuel Vadot xgbe_disable_rx(struct xgbe_prv_data *pdata)
263244b781cfSAndrew Turner {
263344b781cfSAndrew Turner unsigned int i;
263444b781cfSAndrew Turner
263544b781cfSAndrew Turner /* Disable MAC Rx */
263644b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0);
263744b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 0);
263844b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 0);
263944b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 0);
264044b781cfSAndrew Turner
264144b781cfSAndrew Turner /* Prepare for Rx DMA channel stop */
264244b781cfSAndrew Turner for (i = 0; i < pdata->rx_q_count; i++)
264344b781cfSAndrew Turner xgbe_prepare_rx_stop(pdata, i);
264444b781cfSAndrew Turner
264544b781cfSAndrew Turner /* Disable each Rx queue */
264644b781cfSAndrew Turner XGMAC_IOWRITE(pdata, MAC_RQC0R, 0);
264744b781cfSAndrew Turner
264844b781cfSAndrew Turner /* Disable each Rx DMA channel */
26497113afc8SEmmanuel Vadot for (i = 0; i < pdata->channel_count; i++) {
26507113afc8SEmmanuel Vadot if (!pdata->channel[i]->rx_ring)
265144b781cfSAndrew Turner break;
265244b781cfSAndrew Turner
26537113afc8SEmmanuel Vadot XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0);
265444b781cfSAndrew Turner }
265544b781cfSAndrew Turner }
265644b781cfSAndrew Turner
26577113afc8SEmmanuel Vadot static void
xgbe_powerup_tx(struct xgbe_prv_data * pdata)26587113afc8SEmmanuel Vadot xgbe_powerup_tx(struct xgbe_prv_data *pdata)
265944b781cfSAndrew Turner {
266044b781cfSAndrew Turner unsigned int i;
266144b781cfSAndrew Turner
266244b781cfSAndrew Turner /* Enable each Tx DMA channel */
26637113afc8SEmmanuel Vadot for (i = 0; i < pdata->channel_count; i++) {
26647113afc8SEmmanuel Vadot if (!pdata->channel[i]->tx_ring)
266544b781cfSAndrew Turner break;
266644b781cfSAndrew Turner
26677113afc8SEmmanuel Vadot XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1);
266844b781cfSAndrew Turner }
266944b781cfSAndrew Turner
267044b781cfSAndrew Turner /* Enable MAC Tx */
267144b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1);
267244b781cfSAndrew Turner }
267344b781cfSAndrew Turner
26747113afc8SEmmanuel Vadot static void
xgbe_powerdown_tx(struct xgbe_prv_data * pdata)26757113afc8SEmmanuel Vadot xgbe_powerdown_tx(struct xgbe_prv_data *pdata)
267644b781cfSAndrew Turner {
267744b781cfSAndrew Turner unsigned int i;
267844b781cfSAndrew Turner
267944b781cfSAndrew Turner /* Prepare for Tx DMA channel stop */
26807113afc8SEmmanuel Vadot for (i = 0; i < pdata->tx_q_count; i++)
26817113afc8SEmmanuel Vadot xgbe_prepare_tx_stop(pdata, i);
268244b781cfSAndrew Turner
268344b781cfSAndrew Turner /* Disable MAC Tx */
268444b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0);
268544b781cfSAndrew Turner
268644b781cfSAndrew Turner /* Disable each Tx DMA channel */
26877113afc8SEmmanuel Vadot for (i = 0; i < pdata->channel_count; i++) {
26887113afc8SEmmanuel Vadot if (!pdata->channel[i]->tx_ring)
268944b781cfSAndrew Turner break;
269044b781cfSAndrew Turner
26917113afc8SEmmanuel Vadot XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0);
269244b781cfSAndrew Turner }
269344b781cfSAndrew Turner }
269444b781cfSAndrew Turner
26957113afc8SEmmanuel Vadot static void
xgbe_powerup_rx(struct xgbe_prv_data * pdata)26967113afc8SEmmanuel Vadot xgbe_powerup_rx(struct xgbe_prv_data *pdata)
269744b781cfSAndrew Turner {
269844b781cfSAndrew Turner unsigned int i;
269944b781cfSAndrew Turner
270044b781cfSAndrew Turner /* Enable each Rx DMA channel */
27017113afc8SEmmanuel Vadot for (i = 0; i < pdata->channel_count; i++) {
27027113afc8SEmmanuel Vadot if (!pdata->channel[i]->rx_ring)
270344b781cfSAndrew Turner break;
270444b781cfSAndrew Turner
27057113afc8SEmmanuel Vadot XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1);
270644b781cfSAndrew Turner }
270744b781cfSAndrew Turner }
270844b781cfSAndrew Turner
27097113afc8SEmmanuel Vadot static void
xgbe_powerdown_rx(struct xgbe_prv_data * pdata)27107113afc8SEmmanuel Vadot xgbe_powerdown_rx(struct xgbe_prv_data *pdata)
271144b781cfSAndrew Turner {
271244b781cfSAndrew Turner unsigned int i;
271344b781cfSAndrew Turner
271444b781cfSAndrew Turner /* Disable each Rx DMA channel */
27157113afc8SEmmanuel Vadot for (i = 0; i < pdata->channel_count; i++) {
27167113afc8SEmmanuel Vadot if (!pdata->channel[i]->rx_ring)
271744b781cfSAndrew Turner break;
271844b781cfSAndrew Turner
27197113afc8SEmmanuel Vadot XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0);
272044b781cfSAndrew Turner }
272144b781cfSAndrew Turner }
272244b781cfSAndrew Turner
27237113afc8SEmmanuel Vadot static int
xgbe_init(struct xgbe_prv_data * pdata)27247113afc8SEmmanuel Vadot xgbe_init(struct xgbe_prv_data *pdata)
272544b781cfSAndrew Turner {
272644b781cfSAndrew Turner struct xgbe_desc_if *desc_if = &pdata->desc_if;
272744b781cfSAndrew Turner int ret;
272844b781cfSAndrew Turner
272944b781cfSAndrew Turner /* Flush Tx queues */
273044b781cfSAndrew Turner ret = xgbe_flush_tx_queues(pdata);
27317113afc8SEmmanuel Vadot if (ret) {
27327113afc8SEmmanuel Vadot axgbe_error("error flushing TX queues\n");
27337113afc8SEmmanuel Vadot return (ret);
27347113afc8SEmmanuel Vadot }
273544b781cfSAndrew Turner
273644b781cfSAndrew Turner /*
273744b781cfSAndrew Turner * Initialize DMA related features
273844b781cfSAndrew Turner */
273944b781cfSAndrew Turner xgbe_config_dma_bus(pdata);
274044b781cfSAndrew Turner xgbe_config_dma_cache(pdata);
274144b781cfSAndrew Turner xgbe_config_osp_mode(pdata);
27427113afc8SEmmanuel Vadot xgbe_config_pbl_val(pdata);
274344b781cfSAndrew Turner xgbe_config_rx_coalesce(pdata);
274444b781cfSAndrew Turner xgbe_config_tx_coalesce(pdata);
274544b781cfSAndrew Turner xgbe_config_rx_buffer_size(pdata);
274644b781cfSAndrew Turner xgbe_config_tso_mode(pdata);
274744b781cfSAndrew Turner xgbe_config_sph_mode(pdata);
274844b781cfSAndrew Turner xgbe_config_rss(pdata);
274944b781cfSAndrew Turner desc_if->wrapper_tx_desc_init(pdata);
275044b781cfSAndrew Turner desc_if->wrapper_rx_desc_init(pdata);
275144b781cfSAndrew Turner xgbe_enable_dma_interrupts(pdata);
275244b781cfSAndrew Turner
275344b781cfSAndrew Turner /*
275444b781cfSAndrew Turner * Initialize MTL related features
275544b781cfSAndrew Turner */
275644b781cfSAndrew Turner xgbe_config_mtl_mode(pdata);
275744b781cfSAndrew Turner xgbe_config_queue_mapping(pdata);
275844b781cfSAndrew Turner xgbe_config_tsf_mode(pdata, pdata->tx_sf_mode);
275944b781cfSAndrew Turner xgbe_config_rsf_mode(pdata, pdata->rx_sf_mode);
276044b781cfSAndrew Turner xgbe_config_tx_threshold(pdata, pdata->tx_threshold);
276144b781cfSAndrew Turner xgbe_config_rx_threshold(pdata, pdata->rx_threshold);
276244b781cfSAndrew Turner xgbe_config_tx_fifo_size(pdata);
276344b781cfSAndrew Turner xgbe_config_rx_fifo_size(pdata);
276444b781cfSAndrew Turner /*TODO: Error Packet and undersized good Packet forwarding enable
276544b781cfSAndrew Turner (FEP and FUP)
276644b781cfSAndrew Turner */
276744b781cfSAndrew Turner xgbe_enable_mtl_interrupts(pdata);
276844b781cfSAndrew Turner
276944b781cfSAndrew Turner /*
277044b781cfSAndrew Turner * Initialize MAC related features
277144b781cfSAndrew Turner */
277244b781cfSAndrew Turner xgbe_config_mac_address(pdata);
277344b781cfSAndrew Turner xgbe_config_rx_mode(pdata);
277444b781cfSAndrew Turner xgbe_config_jumbo_enable(pdata);
277544b781cfSAndrew Turner xgbe_config_flow_control(pdata);
277644b781cfSAndrew Turner xgbe_config_mac_speed(pdata);
277744b781cfSAndrew Turner xgbe_config_checksum_offload(pdata);
277844b781cfSAndrew Turner xgbe_config_vlan_support(pdata);
277944b781cfSAndrew Turner xgbe_config_mmc(pdata);
278044b781cfSAndrew Turner xgbe_enable_mac_interrupts(pdata);
278144b781cfSAndrew Turner
27827113afc8SEmmanuel Vadot return (0);
278344b781cfSAndrew Turner }
278444b781cfSAndrew Turner
27857113afc8SEmmanuel Vadot void
xgbe_init_function_ptrs_dev(struct xgbe_hw_if * hw_if)27867113afc8SEmmanuel Vadot xgbe_init_function_ptrs_dev(struct xgbe_hw_if *hw_if)
278744b781cfSAndrew Turner {
278844b781cfSAndrew Turner
278944b781cfSAndrew Turner hw_if->tx_complete = xgbe_tx_complete;
279044b781cfSAndrew Turner
279144b781cfSAndrew Turner hw_if->set_mac_address = xgbe_set_mac_address;
279244b781cfSAndrew Turner hw_if->config_rx_mode = xgbe_config_rx_mode;
279344b781cfSAndrew Turner
279444b781cfSAndrew Turner hw_if->enable_rx_csum = xgbe_enable_rx_csum;
279544b781cfSAndrew Turner hw_if->disable_rx_csum = xgbe_disable_rx_csum;
279644b781cfSAndrew Turner
279744b781cfSAndrew Turner hw_if->enable_rx_vlan_stripping = xgbe_enable_rx_vlan_stripping;
279844b781cfSAndrew Turner hw_if->disable_rx_vlan_stripping = xgbe_disable_rx_vlan_stripping;
279944b781cfSAndrew Turner hw_if->enable_rx_vlan_filtering = xgbe_enable_rx_vlan_filtering;
280044b781cfSAndrew Turner hw_if->disable_rx_vlan_filtering = xgbe_disable_rx_vlan_filtering;
280144b781cfSAndrew Turner hw_if->update_vlan_hash_table = xgbe_update_vlan_hash_table;
280244b781cfSAndrew Turner
280344b781cfSAndrew Turner hw_if->read_mmd_regs = xgbe_read_mmd_regs;
280444b781cfSAndrew Turner hw_if->write_mmd_regs = xgbe_write_mmd_regs;
280544b781cfSAndrew Turner
28067113afc8SEmmanuel Vadot hw_if->set_speed = xgbe_set_speed;
28077113afc8SEmmanuel Vadot
28087113afc8SEmmanuel Vadot hw_if->set_ext_mii_mode = xgbe_set_ext_mii_mode;
28097113afc8SEmmanuel Vadot hw_if->read_ext_mii_regs = xgbe_read_ext_mii_regs;
28107113afc8SEmmanuel Vadot hw_if->write_ext_mii_regs = xgbe_write_ext_mii_regs;
28117113afc8SEmmanuel Vadot
28127113afc8SEmmanuel Vadot hw_if->set_gpio = xgbe_set_gpio;
28137113afc8SEmmanuel Vadot hw_if->clr_gpio = xgbe_clr_gpio;
281444b781cfSAndrew Turner
281544b781cfSAndrew Turner hw_if->enable_tx = xgbe_enable_tx;
281644b781cfSAndrew Turner hw_if->disable_tx = xgbe_disable_tx;
281744b781cfSAndrew Turner hw_if->enable_rx = xgbe_enable_rx;
281844b781cfSAndrew Turner hw_if->disable_rx = xgbe_disable_rx;
281944b781cfSAndrew Turner
282044b781cfSAndrew Turner hw_if->powerup_tx = xgbe_powerup_tx;
282144b781cfSAndrew Turner hw_if->powerdown_tx = xgbe_powerdown_tx;
282244b781cfSAndrew Turner hw_if->powerup_rx = xgbe_powerup_rx;
282344b781cfSAndrew Turner hw_if->powerdown_rx = xgbe_powerdown_rx;
282444b781cfSAndrew Turner
282544b781cfSAndrew Turner hw_if->dev_read = xgbe_dev_read;
282644b781cfSAndrew Turner hw_if->enable_int = xgbe_enable_int;
282744b781cfSAndrew Turner hw_if->disable_int = xgbe_disable_int;
282844b781cfSAndrew Turner hw_if->init = xgbe_init;
282944b781cfSAndrew Turner hw_if->exit = xgbe_exit;
283044b781cfSAndrew Turner
283144b781cfSAndrew Turner /* Descriptor related Sequences have to be initialized here */
283244b781cfSAndrew Turner hw_if->tx_desc_init = xgbe_tx_desc_init;
283344b781cfSAndrew Turner hw_if->rx_desc_init = xgbe_rx_desc_init;
283444b781cfSAndrew Turner hw_if->tx_desc_reset = xgbe_tx_desc_reset;
283544b781cfSAndrew Turner hw_if->is_last_desc = xgbe_is_last_desc;
283644b781cfSAndrew Turner hw_if->is_context_desc = xgbe_is_context_desc;
283744b781cfSAndrew Turner
283844b781cfSAndrew Turner /* For FLOW ctrl */
283944b781cfSAndrew Turner hw_if->config_tx_flow_control = xgbe_config_tx_flow_control;
284044b781cfSAndrew Turner hw_if->config_rx_flow_control = xgbe_config_rx_flow_control;
284144b781cfSAndrew Turner
284244b781cfSAndrew Turner /* For RX coalescing */
284344b781cfSAndrew Turner hw_if->config_rx_coalesce = xgbe_config_rx_coalesce;
284444b781cfSAndrew Turner hw_if->config_tx_coalesce = xgbe_config_tx_coalesce;
284544b781cfSAndrew Turner hw_if->usec_to_riwt = xgbe_usec_to_riwt;
284644b781cfSAndrew Turner hw_if->riwt_to_usec = xgbe_riwt_to_usec;
284744b781cfSAndrew Turner
284844b781cfSAndrew Turner /* For RX and TX threshold config */
284944b781cfSAndrew Turner hw_if->config_rx_threshold = xgbe_config_rx_threshold;
285044b781cfSAndrew Turner hw_if->config_tx_threshold = xgbe_config_tx_threshold;
285144b781cfSAndrew Turner
285244b781cfSAndrew Turner /* For RX and TX Store and Forward Mode config */
285344b781cfSAndrew Turner hw_if->config_rsf_mode = xgbe_config_rsf_mode;
285444b781cfSAndrew Turner hw_if->config_tsf_mode = xgbe_config_tsf_mode;
285544b781cfSAndrew Turner
285644b781cfSAndrew Turner /* For TX DMA Operating on Second Frame config */
285744b781cfSAndrew Turner hw_if->config_osp_mode = xgbe_config_osp_mode;
285844b781cfSAndrew Turner
285944b781cfSAndrew Turner /* For MMC statistics support */
286044b781cfSAndrew Turner hw_if->tx_mmc_int = xgbe_tx_mmc_int;
286144b781cfSAndrew Turner hw_if->rx_mmc_int = xgbe_rx_mmc_int;
286244b781cfSAndrew Turner hw_if->read_mmc_stats = xgbe_read_mmc_stats;
286344b781cfSAndrew Turner
286444b781cfSAndrew Turner /* For Receive Side Scaling */
28657113afc8SEmmanuel Vadot hw_if->enable_rss = xgbe_enable_rss;
286644b781cfSAndrew Turner hw_if->disable_rss = xgbe_disable_rss;
28677113afc8SEmmanuel Vadot hw_if->set_rss_hash_key = xgbe_set_rss_hash_key;
28687113afc8SEmmanuel Vadot hw_if->set_rss_lookup_table = xgbe_set_rss_lookup_table;
286944b781cfSAndrew Turner }
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