144b781cfSAndrew Turner /* 244b781cfSAndrew Turner * AMD 10Gb Ethernet driver 344b781cfSAndrew Turner * 47113afc8SEmmanuel Vadot * Copyright (c) 2014-2016,2020 Advanced Micro Devices, Inc. 57113afc8SEmmanuel Vadot * 644b781cfSAndrew Turner * This file is available to you under your choice of the following two 744b781cfSAndrew Turner * licenses: 844b781cfSAndrew Turner * 944b781cfSAndrew Turner * License 1: GPLv2 1044b781cfSAndrew Turner * 1144b781cfSAndrew Turner * This file is free software; you may copy, redistribute and/or modify 1244b781cfSAndrew Turner * it under the terms of the GNU General Public License as published by 1344b781cfSAndrew Turner * the Free Software Foundation, either version 2 of the License, or (at 1444b781cfSAndrew Turner * your option) any later version. 1544b781cfSAndrew Turner * 1644b781cfSAndrew Turner * This file is distributed in the hope that it will be useful, but 1744b781cfSAndrew Turner * WITHOUT ANY WARRANTY; without even the implied warranty of 1844b781cfSAndrew Turner * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 1944b781cfSAndrew Turner * General Public License for more details. 2044b781cfSAndrew Turner * 2144b781cfSAndrew Turner * You should have received a copy of the GNU General Public License 2244b781cfSAndrew Turner * along with this program. If not, see <http://www.gnu.org/licenses/>. 2344b781cfSAndrew Turner * 2444b781cfSAndrew Turner * This file incorporates work covered by the following copyright and 2544b781cfSAndrew Turner * permission notice: 2644b781cfSAndrew Turner * The Synopsys DWC ETHER XGMAC Software Driver and documentation 2744b781cfSAndrew Turner * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 2844b781cfSAndrew Turner * Inc. unless otherwise expressly agreed to in writing between Synopsys 2944b781cfSAndrew Turner * and you. 3044b781cfSAndrew Turner * 3144b781cfSAndrew Turner * The Software IS NOT an item of Licensed Software or Licensed Product 3244b781cfSAndrew Turner * under any End User Software License Agreement or Agreement for Licensed 3344b781cfSAndrew Turner * Product with Synopsys or any supplement thereto. Permission is hereby 3444b781cfSAndrew Turner * granted, free of charge, to any person obtaining a copy of this software 3544b781cfSAndrew Turner * annotated with this license and the Software, to deal in the Software 3644b781cfSAndrew Turner * without restriction, including without limitation the rights to use, 3744b781cfSAndrew Turner * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 3844b781cfSAndrew Turner * of the Software, and to permit persons to whom the Software is furnished 3944b781cfSAndrew Turner * to do so, subject to the following conditions: 4044b781cfSAndrew Turner * 4144b781cfSAndrew Turner * The above copyright notice and this permission notice shall be included 4244b781cfSAndrew Turner * in all copies or substantial portions of the Software. 4344b781cfSAndrew Turner * 4444b781cfSAndrew Turner * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 4544b781cfSAndrew Turner * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 4644b781cfSAndrew Turner * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 4744b781cfSAndrew Turner * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 4844b781cfSAndrew Turner * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 4944b781cfSAndrew Turner * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 5044b781cfSAndrew Turner * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 5144b781cfSAndrew Turner * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 5244b781cfSAndrew Turner * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 5344b781cfSAndrew Turner * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 5444b781cfSAndrew Turner * THE POSSIBILITY OF SUCH DAMAGE. 5544b781cfSAndrew Turner * 5644b781cfSAndrew Turner * 5744b781cfSAndrew Turner * License 2: Modified BSD 5844b781cfSAndrew Turner * 5944b781cfSAndrew Turner * Redistribution and use in source and binary forms, with or without 6044b781cfSAndrew Turner * modification, are permitted provided that the following conditions are met: 6144b781cfSAndrew Turner * * Redistributions of source code must retain the above copyright 6244b781cfSAndrew Turner * notice, this list of conditions and the following disclaimer. 6344b781cfSAndrew Turner * * Redistributions in binary form must reproduce the above copyright 6444b781cfSAndrew Turner * notice, this list of conditions and the following disclaimer in the 6544b781cfSAndrew Turner * documentation and/or other materials provided with the distribution. 6644b781cfSAndrew Turner * * Neither the name of Advanced Micro Devices, Inc. nor the 6744b781cfSAndrew Turner * names of its contributors may be used to endorse or promote products 6844b781cfSAndrew Turner * derived from this software without specific prior written permission. 6944b781cfSAndrew Turner * 7044b781cfSAndrew Turner * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 7144b781cfSAndrew Turner * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 7244b781cfSAndrew Turner * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 7344b781cfSAndrew Turner * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 7444b781cfSAndrew Turner * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 7544b781cfSAndrew Turner * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 7644b781cfSAndrew Turner * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 7744b781cfSAndrew Turner * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 7844b781cfSAndrew Turner * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 7944b781cfSAndrew Turner * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 8044b781cfSAndrew Turner * 8144b781cfSAndrew Turner * This file incorporates work covered by the following copyright and 8244b781cfSAndrew Turner * permission notice: 8344b781cfSAndrew Turner * The Synopsys DWC ETHER XGMAC Software Driver and documentation 8444b781cfSAndrew Turner * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 8544b781cfSAndrew Turner * Inc. unless otherwise expressly agreed to in writing between Synopsys 8644b781cfSAndrew Turner * and you. 8744b781cfSAndrew Turner * 8844b781cfSAndrew Turner * The Software IS NOT an item of Licensed Software or Licensed Product 8944b781cfSAndrew Turner * under any End User Software License Agreement or Agreement for Licensed 9044b781cfSAndrew Turner * Product with Synopsys or any supplement thereto. Permission is hereby 9144b781cfSAndrew Turner * granted, free of charge, to any person obtaining a copy of this software 9244b781cfSAndrew Turner * annotated with this license and the Software, to deal in the Software 9344b781cfSAndrew Turner * without restriction, including without limitation the rights to use, 9444b781cfSAndrew Turner * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 9544b781cfSAndrew Turner * of the Software, and to permit persons to whom the Software is furnished 9644b781cfSAndrew Turner * to do so, subject to the following conditions: 9744b781cfSAndrew Turner * 9844b781cfSAndrew Turner * The above copyright notice and this permission notice shall be included 9944b781cfSAndrew Turner * in all copies or substantial portions of the Software. 10044b781cfSAndrew Turner * 10144b781cfSAndrew Turner * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 10244b781cfSAndrew Turner * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 10344b781cfSAndrew Turner * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 10444b781cfSAndrew Turner * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 10544b781cfSAndrew Turner * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 10644b781cfSAndrew Turner * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 10744b781cfSAndrew Turner * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 10844b781cfSAndrew Turner * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 10944b781cfSAndrew Turner * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 11044b781cfSAndrew Turner * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 11144b781cfSAndrew Turner * THE POSSIBILITY OF SUCH DAMAGE. 11244b781cfSAndrew Turner */ 11344b781cfSAndrew Turner 1149c6d6488SAndrew Turner #include <sys/cdefs.h> 1159c6d6488SAndrew Turner __FBSDID("$FreeBSD$"); 1169c6d6488SAndrew Turner 11744b781cfSAndrew Turner #include "xgbe.h" 11844b781cfSAndrew Turner #include "xgbe-common.h" 11944b781cfSAndrew Turner 1209c6d6488SAndrew Turner #include <net/if_dl.h> 1219c6d6488SAndrew Turner 1227113afc8SEmmanuel Vadot static inline unsigned int xgbe_get_max_frame(struct xgbe_prv_data *pdata) 1237113afc8SEmmanuel Vadot { 1247113afc8SEmmanuel Vadot return (if_getmtu(pdata->netdev) + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); 1257113afc8SEmmanuel Vadot } 1267113afc8SEmmanuel Vadot 1277113afc8SEmmanuel Vadot static unsigned int 1287113afc8SEmmanuel Vadot xgbe_usec_to_riwt(struct xgbe_prv_data *pdata, unsigned int usec) 12944b781cfSAndrew Turner { 13044b781cfSAndrew Turner unsigned long rate; 13144b781cfSAndrew Turner unsigned int ret; 13244b781cfSAndrew Turner 13344b781cfSAndrew Turner rate = pdata->sysclk_rate; 13444b781cfSAndrew Turner 13544b781cfSAndrew Turner /* 13644b781cfSAndrew Turner * Convert the input usec value to the watchdog timer value. Each 13744b781cfSAndrew Turner * watchdog timer value is equivalent to 256 clock cycles. 13844b781cfSAndrew Turner * Calculate the required value as: 13944b781cfSAndrew Turner * ( usec * ( system_clock_mhz / 10^6 ) / 256 14044b781cfSAndrew Turner */ 14144b781cfSAndrew Turner ret = (usec * (rate / 1000000)) / 256; 14244b781cfSAndrew Turner 1437113afc8SEmmanuel Vadot return (ret); 14444b781cfSAndrew Turner } 14544b781cfSAndrew Turner 1467113afc8SEmmanuel Vadot static unsigned int 1477113afc8SEmmanuel Vadot xgbe_riwt_to_usec(struct xgbe_prv_data *pdata, unsigned int riwt) 14844b781cfSAndrew Turner { 14944b781cfSAndrew Turner unsigned long rate; 15044b781cfSAndrew Turner unsigned int ret; 15144b781cfSAndrew Turner 15244b781cfSAndrew Turner rate = pdata->sysclk_rate; 15344b781cfSAndrew Turner 15444b781cfSAndrew Turner /* 15544b781cfSAndrew Turner * Convert the input watchdog timer value to the usec value. Each 15644b781cfSAndrew Turner * watchdog timer value is equivalent to 256 clock cycles. 15744b781cfSAndrew Turner * Calculate the required value as: 15844b781cfSAndrew Turner * ( riwt * 256 ) / ( system_clock_mhz / 10^6 ) 15944b781cfSAndrew Turner */ 16044b781cfSAndrew Turner ret = (riwt * 256) / (rate / 1000000); 16144b781cfSAndrew Turner 1627113afc8SEmmanuel Vadot return (ret); 16344b781cfSAndrew Turner } 16444b781cfSAndrew Turner 1657113afc8SEmmanuel Vadot static int 1667113afc8SEmmanuel Vadot xgbe_config_pbl_val(struct xgbe_prv_data *pdata) 16744b781cfSAndrew Turner { 1687113afc8SEmmanuel Vadot unsigned int pblx8, pbl; 16944b781cfSAndrew Turner unsigned int i; 17044b781cfSAndrew Turner 1717113afc8SEmmanuel Vadot pblx8 = DMA_PBL_X8_DISABLE; 1727113afc8SEmmanuel Vadot pbl = pdata->pbl; 17344b781cfSAndrew Turner 1747113afc8SEmmanuel Vadot if (pdata->pbl > 32) { 1757113afc8SEmmanuel Vadot pblx8 = DMA_PBL_X8_ENABLE; 1767113afc8SEmmanuel Vadot pbl >>= 3; 17744b781cfSAndrew Turner } 17844b781cfSAndrew Turner 1797113afc8SEmmanuel Vadot for (i = 0; i < pdata->channel_count; i++) { 1807113afc8SEmmanuel Vadot XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, PBLX8, 1817113afc8SEmmanuel Vadot pblx8); 1827113afc8SEmmanuel Vadot 1837113afc8SEmmanuel Vadot if (pdata->channel[i]->tx_ring) 1847113afc8SEmmanuel Vadot XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, 1857113afc8SEmmanuel Vadot PBL, pbl); 1867113afc8SEmmanuel Vadot 1877113afc8SEmmanuel Vadot if (pdata->channel[i]->rx_ring) 1887113afc8SEmmanuel Vadot XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, 1897113afc8SEmmanuel Vadot PBL, pbl); 19044b781cfSAndrew Turner } 19144b781cfSAndrew Turner 1927113afc8SEmmanuel Vadot return (0); 1937113afc8SEmmanuel Vadot } 1947113afc8SEmmanuel Vadot 1957113afc8SEmmanuel Vadot static int 1967113afc8SEmmanuel Vadot xgbe_config_osp_mode(struct xgbe_prv_data *pdata) 19744b781cfSAndrew Turner { 19844b781cfSAndrew Turner unsigned int i; 19944b781cfSAndrew Turner 2007113afc8SEmmanuel Vadot for (i = 0; i < pdata->channel_count; i++) { 2017113afc8SEmmanuel Vadot if (!pdata->channel[i]->tx_ring) 20244b781cfSAndrew Turner break; 20344b781cfSAndrew Turner 2047113afc8SEmmanuel Vadot XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, OSP, 20544b781cfSAndrew Turner pdata->tx_osp_mode); 20644b781cfSAndrew Turner } 20744b781cfSAndrew Turner 2087113afc8SEmmanuel Vadot return (0); 20944b781cfSAndrew Turner } 21044b781cfSAndrew Turner 2117113afc8SEmmanuel Vadot static int 2127113afc8SEmmanuel Vadot xgbe_config_rsf_mode(struct xgbe_prv_data *pdata, unsigned int val) 21344b781cfSAndrew Turner { 21444b781cfSAndrew Turner unsigned int i; 21544b781cfSAndrew Turner 21644b781cfSAndrew Turner for (i = 0; i < pdata->rx_q_count; i++) 21744b781cfSAndrew Turner XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RSF, val); 21844b781cfSAndrew Turner 2197113afc8SEmmanuel Vadot return (0); 22044b781cfSAndrew Turner } 22144b781cfSAndrew Turner 2227113afc8SEmmanuel Vadot static int 2237113afc8SEmmanuel Vadot xgbe_config_tsf_mode(struct xgbe_prv_data *pdata, unsigned int val) 22444b781cfSAndrew Turner { 22544b781cfSAndrew Turner unsigned int i; 22644b781cfSAndrew Turner 22744b781cfSAndrew Turner for (i = 0; i < pdata->tx_q_count; i++) 22844b781cfSAndrew Turner XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TSF, val); 22944b781cfSAndrew Turner 2307113afc8SEmmanuel Vadot return (0); 23144b781cfSAndrew Turner } 23244b781cfSAndrew Turner 2337113afc8SEmmanuel Vadot static int 2347113afc8SEmmanuel Vadot xgbe_config_rx_threshold(struct xgbe_prv_data *pdata, unsigned int val) 23544b781cfSAndrew Turner { 23644b781cfSAndrew Turner unsigned int i; 23744b781cfSAndrew Turner 23844b781cfSAndrew Turner for (i = 0; i < pdata->rx_q_count; i++) 23944b781cfSAndrew Turner XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RTC, val); 24044b781cfSAndrew Turner 2417113afc8SEmmanuel Vadot return (0); 24244b781cfSAndrew Turner } 24344b781cfSAndrew Turner 2447113afc8SEmmanuel Vadot static int 2457113afc8SEmmanuel Vadot xgbe_config_tx_threshold(struct xgbe_prv_data *pdata, unsigned int val) 24644b781cfSAndrew Turner { 24744b781cfSAndrew Turner unsigned int i; 24844b781cfSAndrew Turner 24944b781cfSAndrew Turner for (i = 0; i < pdata->tx_q_count; i++) 25044b781cfSAndrew Turner XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TTC, val); 25144b781cfSAndrew Turner 2527113afc8SEmmanuel Vadot return (0); 25344b781cfSAndrew Turner } 25444b781cfSAndrew Turner 2557113afc8SEmmanuel Vadot static int 2567113afc8SEmmanuel Vadot xgbe_config_rx_coalesce(struct xgbe_prv_data *pdata) 25744b781cfSAndrew Turner { 25844b781cfSAndrew Turner unsigned int i; 25944b781cfSAndrew Turner 2607113afc8SEmmanuel Vadot for (i = 0; i < pdata->channel_count; i++) { 2617113afc8SEmmanuel Vadot if (!pdata->channel[i]->rx_ring) 26244b781cfSAndrew Turner break; 26344b781cfSAndrew Turner 2647113afc8SEmmanuel Vadot XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RIWT, RWT, 26544b781cfSAndrew Turner pdata->rx_riwt); 26644b781cfSAndrew Turner } 26744b781cfSAndrew Turner 2687113afc8SEmmanuel Vadot return (0); 26944b781cfSAndrew Turner } 27044b781cfSAndrew Turner 2717113afc8SEmmanuel Vadot static int 2727113afc8SEmmanuel Vadot xgbe_config_tx_coalesce(struct xgbe_prv_data *pdata) 27344b781cfSAndrew Turner { 2747113afc8SEmmanuel Vadot return (0); 27544b781cfSAndrew Turner } 27644b781cfSAndrew Turner 2777113afc8SEmmanuel Vadot static void 2787113afc8SEmmanuel Vadot xgbe_config_rx_buffer_size(struct xgbe_prv_data *pdata) 27944b781cfSAndrew Turner { 28044b781cfSAndrew Turner unsigned int i; 28144b781cfSAndrew Turner 2827113afc8SEmmanuel Vadot for (i = 0; i < pdata->channel_count; i++) { 2837113afc8SEmmanuel Vadot if (!pdata->channel[i]->rx_ring) 28444b781cfSAndrew Turner break; 28544b781cfSAndrew Turner 2867113afc8SEmmanuel Vadot XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, RBSZ, 28744b781cfSAndrew Turner pdata->rx_buf_size); 28844b781cfSAndrew Turner } 28944b781cfSAndrew Turner } 29044b781cfSAndrew Turner 2917113afc8SEmmanuel Vadot static void 2927113afc8SEmmanuel Vadot xgbe_config_tso_mode(struct xgbe_prv_data *pdata) 29344b781cfSAndrew Turner { 29444b781cfSAndrew Turner unsigned int i; 29544b781cfSAndrew Turner 2967113afc8SEmmanuel Vadot for (i = 0; i < pdata->channel_count; i++) { 2977113afc8SEmmanuel Vadot if (!pdata->channel[i]->tx_ring) 29844b781cfSAndrew Turner break; 29944b781cfSAndrew Turner 3007113afc8SEmmanuel Vadot axgbe_printf(0, "Enabling TSO in channel %d\n", i); 3017113afc8SEmmanuel Vadot XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, TSE, 1); 30244b781cfSAndrew Turner } 30344b781cfSAndrew Turner } 30444b781cfSAndrew Turner 3057113afc8SEmmanuel Vadot static void 3067113afc8SEmmanuel Vadot xgbe_config_sph_mode(struct xgbe_prv_data *pdata) 30744b781cfSAndrew Turner { 30844b781cfSAndrew Turner unsigned int i; 30944b781cfSAndrew Turner 3107113afc8SEmmanuel Vadot for (i = 0; i < pdata->channel_count; i++) { 3117113afc8SEmmanuel Vadot if (!pdata->channel[i]->rx_ring) 31244b781cfSAndrew Turner break; 31344b781cfSAndrew Turner 3147113afc8SEmmanuel Vadot XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, SPH, 1); 31544b781cfSAndrew Turner } 31644b781cfSAndrew Turner 31744b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_RCR, HDSMS, XGBE_SPH_HDSMS_SIZE); 31844b781cfSAndrew Turner } 31944b781cfSAndrew Turner 3207113afc8SEmmanuel Vadot static int 3217113afc8SEmmanuel Vadot xgbe_write_rss_reg(struct xgbe_prv_data *pdata, unsigned int type, 3227113afc8SEmmanuel Vadot unsigned int index, unsigned int val) 3237113afc8SEmmanuel Vadot { 3247113afc8SEmmanuel Vadot unsigned int wait; 3257113afc8SEmmanuel Vadot int ret = 0; 3267113afc8SEmmanuel Vadot 3277113afc8SEmmanuel Vadot mtx_lock(&pdata->rss_mutex); 3287113afc8SEmmanuel Vadot 3297113afc8SEmmanuel Vadot if (XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) { 3307113afc8SEmmanuel Vadot ret = -EBUSY; 3317113afc8SEmmanuel Vadot goto unlock; 3327113afc8SEmmanuel Vadot } 3337113afc8SEmmanuel Vadot 3347113afc8SEmmanuel Vadot XGMAC_IOWRITE(pdata, MAC_RSSDR, val); 3357113afc8SEmmanuel Vadot 3367113afc8SEmmanuel Vadot XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, RSSIA, index); 3377113afc8SEmmanuel Vadot XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, ADDRT, type); 3387113afc8SEmmanuel Vadot XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, CT, 0); 3397113afc8SEmmanuel Vadot XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, OB, 1); 3407113afc8SEmmanuel Vadot 3417113afc8SEmmanuel Vadot wait = 1000; 3427113afc8SEmmanuel Vadot while (wait--) { 3437113afc8SEmmanuel Vadot if (!XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) 3447113afc8SEmmanuel Vadot goto unlock; 3457113afc8SEmmanuel Vadot 3467113afc8SEmmanuel Vadot DELAY(1000); 3477113afc8SEmmanuel Vadot } 3487113afc8SEmmanuel Vadot 3497113afc8SEmmanuel Vadot ret = -EBUSY; 3507113afc8SEmmanuel Vadot 3517113afc8SEmmanuel Vadot unlock: 3527113afc8SEmmanuel Vadot mtx_unlock(&pdata->rss_mutex); 3537113afc8SEmmanuel Vadot 3547113afc8SEmmanuel Vadot return (ret); 3557113afc8SEmmanuel Vadot } 3567113afc8SEmmanuel Vadot 3577113afc8SEmmanuel Vadot static int 3587113afc8SEmmanuel Vadot xgbe_write_rss_hash_key(struct xgbe_prv_data *pdata) 3597113afc8SEmmanuel Vadot { 3607113afc8SEmmanuel Vadot unsigned int key_regs = sizeof(pdata->rss_key) / sizeof(uint32_t); 3617113afc8SEmmanuel Vadot unsigned int *key = (unsigned int *)&pdata->rss_key; 3627113afc8SEmmanuel Vadot int ret; 3637113afc8SEmmanuel Vadot 3647113afc8SEmmanuel Vadot while (key_regs--) { 3657113afc8SEmmanuel Vadot ret = xgbe_write_rss_reg(pdata, XGBE_RSS_HASH_KEY_TYPE, 3667113afc8SEmmanuel Vadot key_regs, *key++); 3677113afc8SEmmanuel Vadot if (ret) 3687113afc8SEmmanuel Vadot return (ret); 3697113afc8SEmmanuel Vadot } 3707113afc8SEmmanuel Vadot 3717113afc8SEmmanuel Vadot return (0); 3727113afc8SEmmanuel Vadot } 3737113afc8SEmmanuel Vadot 3747113afc8SEmmanuel Vadot static int 3757113afc8SEmmanuel Vadot xgbe_write_rss_lookup_table(struct xgbe_prv_data *pdata) 3767113afc8SEmmanuel Vadot { 3777113afc8SEmmanuel Vadot unsigned int i; 3787113afc8SEmmanuel Vadot int ret; 3797113afc8SEmmanuel Vadot 3807113afc8SEmmanuel Vadot for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) { 3817113afc8SEmmanuel Vadot ret = xgbe_write_rss_reg(pdata, XGBE_RSS_LOOKUP_TABLE_TYPE, i, 3827113afc8SEmmanuel Vadot pdata->rss_table[i]); 3837113afc8SEmmanuel Vadot if (ret) 3847113afc8SEmmanuel Vadot return (ret); 3857113afc8SEmmanuel Vadot } 3867113afc8SEmmanuel Vadot 3877113afc8SEmmanuel Vadot return (0); 3887113afc8SEmmanuel Vadot } 3897113afc8SEmmanuel Vadot 3907113afc8SEmmanuel Vadot static int 3917113afc8SEmmanuel Vadot xgbe_set_rss_hash_key(struct xgbe_prv_data *pdata, const uint8_t *key) 3927113afc8SEmmanuel Vadot { 3937113afc8SEmmanuel Vadot memcpy(pdata->rss_key, key, sizeof(pdata->rss_key)); 3947113afc8SEmmanuel Vadot 3957113afc8SEmmanuel Vadot return (xgbe_write_rss_hash_key(pdata)); 3967113afc8SEmmanuel Vadot } 3977113afc8SEmmanuel Vadot 3987113afc8SEmmanuel Vadot static int 3997113afc8SEmmanuel Vadot xgbe_set_rss_lookup_table(struct xgbe_prv_data *pdata, const uint32_t *table) 4007113afc8SEmmanuel Vadot { 4017113afc8SEmmanuel Vadot unsigned int i; 4027113afc8SEmmanuel Vadot 4037113afc8SEmmanuel Vadot for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) 4047113afc8SEmmanuel Vadot XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, table[i]); 4057113afc8SEmmanuel Vadot 4067113afc8SEmmanuel Vadot return (xgbe_write_rss_lookup_table(pdata)); 4077113afc8SEmmanuel Vadot } 4087113afc8SEmmanuel Vadot 4097113afc8SEmmanuel Vadot static int 4107113afc8SEmmanuel Vadot xgbe_enable_rss(struct xgbe_prv_data *pdata) 4117113afc8SEmmanuel Vadot { 4127113afc8SEmmanuel Vadot int ret; 4137113afc8SEmmanuel Vadot 4147113afc8SEmmanuel Vadot if (!pdata->hw_feat.rss) 4157113afc8SEmmanuel Vadot return (-EOPNOTSUPP); 4167113afc8SEmmanuel Vadot 4177113afc8SEmmanuel Vadot /* Program the hash key */ 4187113afc8SEmmanuel Vadot ret = xgbe_write_rss_hash_key(pdata); 4197113afc8SEmmanuel Vadot if (ret) 4207113afc8SEmmanuel Vadot return (ret); 4217113afc8SEmmanuel Vadot 4227113afc8SEmmanuel Vadot /* Program the lookup table */ 4237113afc8SEmmanuel Vadot ret = xgbe_write_rss_lookup_table(pdata); 4247113afc8SEmmanuel Vadot if (ret) 4257113afc8SEmmanuel Vadot return (ret); 4267113afc8SEmmanuel Vadot 4277113afc8SEmmanuel Vadot /* Set the RSS options */ 4287113afc8SEmmanuel Vadot XGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options); 4297113afc8SEmmanuel Vadot 4307113afc8SEmmanuel Vadot /* Enable RSS */ 4317113afc8SEmmanuel Vadot XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 1); 4327113afc8SEmmanuel Vadot 4337113afc8SEmmanuel Vadot axgbe_printf(0, "RSS Enabled\n"); 4347113afc8SEmmanuel Vadot 4357113afc8SEmmanuel Vadot return (0); 4367113afc8SEmmanuel Vadot } 4377113afc8SEmmanuel Vadot 4387113afc8SEmmanuel Vadot static int 4397113afc8SEmmanuel Vadot xgbe_disable_rss(struct xgbe_prv_data *pdata) 44044b781cfSAndrew Turner { 44144b781cfSAndrew Turner if (!pdata->hw_feat.rss) 4427113afc8SEmmanuel Vadot return (-EOPNOTSUPP); 44344b781cfSAndrew Turner 44444b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 0); 44544b781cfSAndrew Turner 4467113afc8SEmmanuel Vadot axgbe_printf(0, "RSS Disabled\n"); 4477113afc8SEmmanuel Vadot 4487113afc8SEmmanuel Vadot return (0); 44944b781cfSAndrew Turner } 45044b781cfSAndrew Turner 4517113afc8SEmmanuel Vadot static void 4527113afc8SEmmanuel Vadot xgbe_config_rss(struct xgbe_prv_data *pdata) 45344b781cfSAndrew Turner { 4547113afc8SEmmanuel Vadot int ret; 45544b781cfSAndrew Turner 45644b781cfSAndrew Turner if (!pdata->hw_feat.rss) 45744b781cfSAndrew Turner return; 45844b781cfSAndrew Turner 4597113afc8SEmmanuel Vadot /* Check if the interface has RSS capability */ 4607113afc8SEmmanuel Vadot if (pdata->enable_rss) 4617113afc8SEmmanuel Vadot ret = xgbe_enable_rss(pdata); 4627113afc8SEmmanuel Vadot else 4637113afc8SEmmanuel Vadot ret = xgbe_disable_rss(pdata); 4647113afc8SEmmanuel Vadot 4657113afc8SEmmanuel Vadot if (ret) 4667113afc8SEmmanuel Vadot axgbe_error("error configuring RSS, RSS disabled\n"); 46744b781cfSAndrew Turner } 46844b781cfSAndrew Turner 4697113afc8SEmmanuel Vadot static int 4707113afc8SEmmanuel Vadot xgbe_disable_tx_flow_control(struct xgbe_prv_data *pdata) 47144b781cfSAndrew Turner { 47244b781cfSAndrew Turner unsigned int max_q_count, q_count; 47344b781cfSAndrew Turner unsigned int reg, reg_val; 47444b781cfSAndrew Turner unsigned int i; 47544b781cfSAndrew Turner 47644b781cfSAndrew Turner /* Clear MTL flow control */ 47744b781cfSAndrew Turner for (i = 0; i < pdata->rx_q_count; i++) 47844b781cfSAndrew Turner XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 0); 47944b781cfSAndrew Turner 48044b781cfSAndrew Turner /* Clear MAC flow control */ 48144b781cfSAndrew Turner max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES; 48244b781cfSAndrew Turner q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count); 48344b781cfSAndrew Turner reg = MAC_Q0TFCR; 48444b781cfSAndrew Turner for (i = 0; i < q_count; i++) { 48544b781cfSAndrew Turner reg_val = XGMAC_IOREAD(pdata, reg); 48644b781cfSAndrew Turner XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 0); 48744b781cfSAndrew Turner XGMAC_IOWRITE(pdata, reg, reg_val); 48844b781cfSAndrew Turner 48944b781cfSAndrew Turner reg += MAC_QTFCR_INC; 49044b781cfSAndrew Turner } 49144b781cfSAndrew Turner 4927113afc8SEmmanuel Vadot return (0); 49344b781cfSAndrew Turner } 49444b781cfSAndrew Turner 4957113afc8SEmmanuel Vadot static int 4967113afc8SEmmanuel Vadot xgbe_enable_tx_flow_control(struct xgbe_prv_data *pdata) 49744b781cfSAndrew Turner { 49844b781cfSAndrew Turner unsigned int max_q_count, q_count; 49944b781cfSAndrew Turner unsigned int reg, reg_val; 50044b781cfSAndrew Turner unsigned int i; 50144b781cfSAndrew Turner 50244b781cfSAndrew Turner /* Set MTL flow control */ 50344b781cfSAndrew Turner for (i = 0; i < pdata->rx_q_count; i++) { 5047113afc8SEmmanuel Vadot unsigned int ehfc = 0; 5057113afc8SEmmanuel Vadot 5067113afc8SEmmanuel Vadot if (pdata->rx_rfd[i]) { 5077113afc8SEmmanuel Vadot /* Flow control thresholds are established */ 5087113afc8SEmmanuel Vadot /* TODO - enable pfc/ets support */ 5097113afc8SEmmanuel Vadot ehfc = 1; 5107113afc8SEmmanuel Vadot } 5117113afc8SEmmanuel Vadot 5127113afc8SEmmanuel Vadot XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, ehfc); 5137113afc8SEmmanuel Vadot 5147113afc8SEmmanuel Vadot axgbe_printf(1, "flow control %s for RXq%u\n", 5157113afc8SEmmanuel Vadot ehfc ? "enabled" : "disabled", i); 51644b781cfSAndrew Turner } 51744b781cfSAndrew Turner 51844b781cfSAndrew Turner /* Set MAC flow control */ 51944b781cfSAndrew Turner max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES; 52044b781cfSAndrew Turner q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count); 52144b781cfSAndrew Turner reg = MAC_Q0TFCR; 52244b781cfSAndrew Turner for (i = 0; i < q_count; i++) { 52344b781cfSAndrew Turner reg_val = XGMAC_IOREAD(pdata, reg); 52444b781cfSAndrew Turner 52544b781cfSAndrew Turner /* Enable transmit flow control */ 52644b781cfSAndrew Turner XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 1); 5277113afc8SEmmanuel Vadot 52844b781cfSAndrew Turner /* Set pause time */ 52944b781cfSAndrew Turner XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, 0xffff); 53044b781cfSAndrew Turner 53144b781cfSAndrew Turner XGMAC_IOWRITE(pdata, reg, reg_val); 53244b781cfSAndrew Turner 53344b781cfSAndrew Turner reg += MAC_QTFCR_INC; 53444b781cfSAndrew Turner } 53544b781cfSAndrew Turner 5367113afc8SEmmanuel Vadot return (0); 53744b781cfSAndrew Turner } 53844b781cfSAndrew Turner 5397113afc8SEmmanuel Vadot static int 5407113afc8SEmmanuel Vadot xgbe_disable_rx_flow_control(struct xgbe_prv_data *pdata) 54144b781cfSAndrew Turner { 54244b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 0); 54344b781cfSAndrew Turner 5447113afc8SEmmanuel Vadot return (0); 54544b781cfSAndrew Turner } 54644b781cfSAndrew Turner 5477113afc8SEmmanuel Vadot static int 5487113afc8SEmmanuel Vadot xgbe_enable_rx_flow_control(struct xgbe_prv_data *pdata) 54944b781cfSAndrew Turner { 55044b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 1); 55144b781cfSAndrew Turner 5527113afc8SEmmanuel Vadot return (0); 55344b781cfSAndrew Turner } 55444b781cfSAndrew Turner 5557113afc8SEmmanuel Vadot static int 5567113afc8SEmmanuel Vadot xgbe_config_tx_flow_control(struct xgbe_prv_data *pdata) 55744b781cfSAndrew Turner { 5589c6d6488SAndrew Turner if (pdata->tx_pause) 55944b781cfSAndrew Turner xgbe_enable_tx_flow_control(pdata); 56044b781cfSAndrew Turner else 56144b781cfSAndrew Turner xgbe_disable_tx_flow_control(pdata); 56244b781cfSAndrew Turner 5637113afc8SEmmanuel Vadot return (0); 56444b781cfSAndrew Turner } 56544b781cfSAndrew Turner 5667113afc8SEmmanuel Vadot static int 5677113afc8SEmmanuel Vadot xgbe_config_rx_flow_control(struct xgbe_prv_data *pdata) 56844b781cfSAndrew Turner { 5699c6d6488SAndrew Turner if (pdata->rx_pause) 57044b781cfSAndrew Turner xgbe_enable_rx_flow_control(pdata); 57144b781cfSAndrew Turner else 57244b781cfSAndrew Turner xgbe_disable_rx_flow_control(pdata); 57344b781cfSAndrew Turner 5747113afc8SEmmanuel Vadot return (0); 57544b781cfSAndrew Turner } 57644b781cfSAndrew Turner 5777113afc8SEmmanuel Vadot static void 5787113afc8SEmmanuel Vadot xgbe_config_flow_control(struct xgbe_prv_data *pdata) 57944b781cfSAndrew Turner { 58044b781cfSAndrew Turner xgbe_config_tx_flow_control(pdata); 58144b781cfSAndrew Turner xgbe_config_rx_flow_control(pdata); 58244b781cfSAndrew Turner 5839c6d6488SAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0); 58444b781cfSAndrew Turner } 58544b781cfSAndrew Turner 5867113afc8SEmmanuel Vadot static void 5877113afc8SEmmanuel Vadot xgbe_enable_dma_interrupts(struct xgbe_prv_data *pdata) 58844b781cfSAndrew Turner { 58944b781cfSAndrew Turner struct xgbe_channel *channel; 5907113afc8SEmmanuel Vadot unsigned int i, ver; 59144b781cfSAndrew Turner 5927113afc8SEmmanuel Vadot /* Set the interrupt mode if supported */ 5937113afc8SEmmanuel Vadot if (pdata->channel_irq_mode) 5947113afc8SEmmanuel Vadot XGMAC_IOWRITE_BITS(pdata, DMA_MR, INTM, 5957113afc8SEmmanuel Vadot pdata->channel_irq_mode); 5967113afc8SEmmanuel Vadot 5977113afc8SEmmanuel Vadot ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER); 5987113afc8SEmmanuel Vadot 5997113afc8SEmmanuel Vadot for (i = 0; i < pdata->channel_count; i++) { 6007113afc8SEmmanuel Vadot channel = pdata->channel[i]; 6017113afc8SEmmanuel Vadot 60244b781cfSAndrew Turner /* Clear all the interrupts which are set */ 6037113afc8SEmmanuel Vadot XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, 6047113afc8SEmmanuel Vadot XGMAC_DMA_IOREAD(channel, DMA_CH_SR)); 60544b781cfSAndrew Turner 60644b781cfSAndrew Turner /* Clear all interrupt enable bits */ 6077113afc8SEmmanuel Vadot channel->curr_ier = 0; 60844b781cfSAndrew Turner 60944b781cfSAndrew Turner /* Enable following interrupts 61044b781cfSAndrew Turner * NIE - Normal Interrupt Summary Enable 61144b781cfSAndrew Turner * AIE - Abnormal Interrupt Summary Enable 61244b781cfSAndrew Turner * FBEE - Fatal Bus Error Enable 61344b781cfSAndrew Turner */ 6147113afc8SEmmanuel Vadot if (ver < 0x21) { 6157113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, NIE20, 1); 6167113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, AIE20, 1); 6177113afc8SEmmanuel Vadot } else { 6187113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, NIE, 1); 6197113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, AIE, 1); 6207113afc8SEmmanuel Vadot } 6217113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 1); 62244b781cfSAndrew Turner 62344b781cfSAndrew Turner if (channel->tx_ring) { 62444b781cfSAndrew Turner /* Enable the following Tx interrupts 62544b781cfSAndrew Turner * TIE - Transmit Interrupt Enable (unless using 6267113afc8SEmmanuel Vadot * per channel interrupts in edge triggered 6277113afc8SEmmanuel Vadot * mode) 62844b781cfSAndrew Turner */ 6297113afc8SEmmanuel Vadot if (!pdata->per_channel_irq || pdata->channel_irq_mode) 6307113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, 6317113afc8SEmmanuel Vadot DMA_CH_IER, TIE, 1); 63244b781cfSAndrew Turner } 63344b781cfSAndrew Turner if (channel->rx_ring) { 63444b781cfSAndrew Turner /* Enable following Rx interrupts 63544b781cfSAndrew Turner * RBUE - Receive Buffer Unavailable Enable 63644b781cfSAndrew Turner * RIE - Receive Interrupt Enable (unless using 6377113afc8SEmmanuel Vadot * per channel interrupts in edge triggered 6387113afc8SEmmanuel Vadot * mode) 63944b781cfSAndrew Turner */ 6407113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 1); 6417113afc8SEmmanuel Vadot if (!pdata->per_channel_irq || pdata->channel_irq_mode) 6427113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, 6437113afc8SEmmanuel Vadot DMA_CH_IER, RIE, 1); 64444b781cfSAndrew Turner } 64544b781cfSAndrew Turner 6467113afc8SEmmanuel Vadot XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, channel->curr_ier); 64744b781cfSAndrew Turner } 64844b781cfSAndrew Turner } 64944b781cfSAndrew Turner 6507113afc8SEmmanuel Vadot static void 6517113afc8SEmmanuel Vadot xgbe_enable_mtl_interrupts(struct xgbe_prv_data *pdata) 65244b781cfSAndrew Turner { 65344b781cfSAndrew Turner unsigned int mtl_q_isr; 65444b781cfSAndrew Turner unsigned int q_count, i; 65544b781cfSAndrew Turner 65644b781cfSAndrew Turner q_count = max(pdata->hw_feat.tx_q_cnt, pdata->hw_feat.rx_q_cnt); 65744b781cfSAndrew Turner for (i = 0; i < q_count; i++) { 65844b781cfSAndrew Turner /* Clear all the interrupts which are set */ 65944b781cfSAndrew Turner mtl_q_isr = XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR); 66044b781cfSAndrew Turner XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_ISR, mtl_q_isr); 66144b781cfSAndrew Turner 66244b781cfSAndrew Turner /* No MTL interrupts to be enabled */ 66344b781cfSAndrew Turner XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_IER, 0); 66444b781cfSAndrew Turner } 66544b781cfSAndrew Turner } 66644b781cfSAndrew Turner 6677113afc8SEmmanuel Vadot static void 6687113afc8SEmmanuel Vadot xgbe_enable_mac_interrupts(struct xgbe_prv_data *pdata) 66944b781cfSAndrew Turner { 67044b781cfSAndrew Turner unsigned int mac_ier = 0; 67144b781cfSAndrew Turner 67244b781cfSAndrew Turner /* Enable Timestamp interrupt */ 67344b781cfSAndrew Turner XGMAC_SET_BITS(mac_ier, MAC_IER, TSIE, 1); 67444b781cfSAndrew Turner 67544b781cfSAndrew Turner XGMAC_IOWRITE(pdata, MAC_IER, mac_ier); 67644b781cfSAndrew Turner 67744b781cfSAndrew Turner /* Enable all counter interrupts */ 67844b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MMC_RIER, ALL_INTERRUPTS, 0xffffffff); 67944b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MMC_TIER, ALL_INTERRUPTS, 0xffffffff); 6807113afc8SEmmanuel Vadot 6817113afc8SEmmanuel Vadot /* Enable MDIO single command completion interrupt */ 6827113afc8SEmmanuel Vadot XGMAC_IOWRITE_BITS(pdata, MAC_MDIOIER, SNGLCOMPIE, 1); 68344b781cfSAndrew Turner } 68444b781cfSAndrew Turner 6857113afc8SEmmanuel Vadot static int 6867113afc8SEmmanuel Vadot xgbe_set_speed(struct xgbe_prv_data *pdata, int speed) 68744b781cfSAndrew Turner { 6887113afc8SEmmanuel Vadot unsigned int ss; 68944b781cfSAndrew Turner 6907113afc8SEmmanuel Vadot switch (speed) { 6917113afc8SEmmanuel Vadot case SPEED_1000: 6927113afc8SEmmanuel Vadot ss = 0x03; 6937113afc8SEmmanuel Vadot break; 6947113afc8SEmmanuel Vadot case SPEED_2500: 6957113afc8SEmmanuel Vadot ss = 0x02; 6967113afc8SEmmanuel Vadot break; 6977113afc8SEmmanuel Vadot case SPEED_10000: 6987113afc8SEmmanuel Vadot ss = 0x00; 6997113afc8SEmmanuel Vadot break; 7007113afc8SEmmanuel Vadot default: 7017113afc8SEmmanuel Vadot return (-EINVAL); 70244b781cfSAndrew Turner } 70344b781cfSAndrew Turner 7047113afc8SEmmanuel Vadot if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) != ss) 7057113afc8SEmmanuel Vadot XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, ss); 70644b781cfSAndrew Turner 7077113afc8SEmmanuel Vadot return (0); 70844b781cfSAndrew Turner } 70944b781cfSAndrew Turner 7107113afc8SEmmanuel Vadot static int 7117113afc8SEmmanuel Vadot xgbe_enable_rx_vlan_stripping(struct xgbe_prv_data *pdata) 71244b781cfSAndrew Turner { 71344b781cfSAndrew Turner /* Put the VLAN tag in the Rx descriptor */ 71444b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLRXS, 1); 71544b781cfSAndrew Turner 71644b781cfSAndrew Turner /* Don't check the VLAN type */ 71744b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, DOVLTC, 1); 71844b781cfSAndrew Turner 71944b781cfSAndrew Turner /* Check only C-TAG (0x8100) packets */ 72044b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERSVLM, 0); 72144b781cfSAndrew Turner 72244b781cfSAndrew Turner /* Don't consider an S-TAG (0x88A8) packet as a VLAN packet */ 72344b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ESVL, 0); 72444b781cfSAndrew Turner 72544b781cfSAndrew Turner /* Enable VLAN tag stripping */ 72644b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0x3); 72744b781cfSAndrew Turner 7287113afc8SEmmanuel Vadot axgbe_printf(0, "VLAN Stripping Enabled\n"); 7297113afc8SEmmanuel Vadot 7307113afc8SEmmanuel Vadot return (0); 73144b781cfSAndrew Turner } 73244b781cfSAndrew Turner 7337113afc8SEmmanuel Vadot static int 7347113afc8SEmmanuel Vadot xgbe_disable_rx_vlan_stripping(struct xgbe_prv_data *pdata) 73544b781cfSAndrew Turner { 73644b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0); 73744b781cfSAndrew Turner 7387113afc8SEmmanuel Vadot axgbe_printf(0, "VLAN Stripping Disabled\n"); 7397113afc8SEmmanuel Vadot 7407113afc8SEmmanuel Vadot return (0); 74144b781cfSAndrew Turner } 74244b781cfSAndrew Turner 7437113afc8SEmmanuel Vadot static int 7447113afc8SEmmanuel Vadot xgbe_enable_rx_vlan_filtering(struct xgbe_prv_data *pdata) 74544b781cfSAndrew Turner { 74644b781cfSAndrew Turner /* Enable VLAN filtering */ 74744b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1); 74844b781cfSAndrew Turner 74944b781cfSAndrew Turner /* Enable VLAN Hash Table filtering */ 75044b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTHM, 1); 75144b781cfSAndrew Turner 75244b781cfSAndrew Turner /* Disable VLAN tag inverse matching */ 75344b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTIM, 0); 75444b781cfSAndrew Turner 75544b781cfSAndrew Turner /* Only filter on the lower 12-bits of the VLAN tag */ 75644b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ETV, 1); 75744b781cfSAndrew Turner 75844b781cfSAndrew Turner /* In order for the VLAN Hash Table filtering to be effective, 75944b781cfSAndrew Turner * the VLAN tag identifier in the VLAN Tag Register must not 76044b781cfSAndrew Turner * be zero. Set the VLAN tag identifier to "1" to enable the 76144b781cfSAndrew Turner * VLAN Hash Table filtering. This implies that a VLAN tag of 76244b781cfSAndrew Turner * 1 will always pass filtering. 76344b781cfSAndrew Turner */ 76444b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VL, 1); 76544b781cfSAndrew Turner 7667113afc8SEmmanuel Vadot axgbe_printf(0, "VLAN filtering Enabled\n"); 7677113afc8SEmmanuel Vadot 7687113afc8SEmmanuel Vadot return (0); 76944b781cfSAndrew Turner } 77044b781cfSAndrew Turner 7717113afc8SEmmanuel Vadot static int 7727113afc8SEmmanuel Vadot xgbe_disable_rx_vlan_filtering(struct xgbe_prv_data *pdata) 77344b781cfSAndrew Turner { 77444b781cfSAndrew Turner /* Disable VLAN filtering */ 77544b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0); 77644b781cfSAndrew Turner 7777113afc8SEmmanuel Vadot axgbe_printf(0, "VLAN filtering Disabled\n"); 7787113afc8SEmmanuel Vadot 7797113afc8SEmmanuel Vadot return (0); 78044b781cfSAndrew Turner } 78144b781cfSAndrew Turner 7827113afc8SEmmanuel Vadot static uint32_t 7837113afc8SEmmanuel Vadot xgbe_vid_crc32_le(__le16 vid_le) 78444b781cfSAndrew Turner { 7857113afc8SEmmanuel Vadot uint32_t crc = ~0; 7867113afc8SEmmanuel Vadot uint32_t temp = 0; 7877113afc8SEmmanuel Vadot unsigned char *data = (unsigned char *)&vid_le; 7887113afc8SEmmanuel Vadot unsigned char data_byte = 0; 7897113afc8SEmmanuel Vadot int i, bits; 7907113afc8SEmmanuel Vadot 7917113afc8SEmmanuel Vadot bits = get_bitmask_order(VLAN_VID_MASK); 7927113afc8SEmmanuel Vadot for (i = 0; i < bits; i++) { 7937113afc8SEmmanuel Vadot if ((i % 8) == 0) 7947113afc8SEmmanuel Vadot data_byte = data[i / 8]; 7957113afc8SEmmanuel Vadot 7967113afc8SEmmanuel Vadot temp = ((crc & 1) ^ data_byte) & 1; 7977113afc8SEmmanuel Vadot crc >>= 1; 7987113afc8SEmmanuel Vadot data_byte >>= 1; 7997113afc8SEmmanuel Vadot 8007113afc8SEmmanuel Vadot if (temp) 8017113afc8SEmmanuel Vadot crc ^= CRC32_POLY_LE; 8027113afc8SEmmanuel Vadot } 8037113afc8SEmmanuel Vadot 8047113afc8SEmmanuel Vadot return (crc); 8057113afc8SEmmanuel Vadot } 8067113afc8SEmmanuel Vadot 8077113afc8SEmmanuel Vadot static int 8087113afc8SEmmanuel Vadot xgbe_update_vlan_hash_table(struct xgbe_prv_data *pdata) 8097113afc8SEmmanuel Vadot { 8107113afc8SEmmanuel Vadot uint32_t crc; 8117113afc8SEmmanuel Vadot uint16_t vid; 8127113afc8SEmmanuel Vadot uint16_t vlan_hash_table = 0; 8137113afc8SEmmanuel Vadot __le16 vid_le = 0; 8147113afc8SEmmanuel Vadot 8157113afc8SEmmanuel Vadot axgbe_printf(1, "%s: Before updating VLANHTR 0x%x\n", __func__, 8167113afc8SEmmanuel Vadot XGMAC_IOREAD(pdata, MAC_VLANHTR)); 8177113afc8SEmmanuel Vadot 8187113afc8SEmmanuel Vadot /* Generate the VLAN Hash Table value */ 8197113afc8SEmmanuel Vadot for_each_set_bit(vid, pdata->active_vlans, VLAN_NVID) { 8207113afc8SEmmanuel Vadot 8217113afc8SEmmanuel Vadot /* Get the CRC32 value of the VLAN ID */ 8227113afc8SEmmanuel Vadot vid_le = cpu_to_le16(vid); 8237113afc8SEmmanuel Vadot crc = bitrev32(~xgbe_vid_crc32_le(vid_le)) >> 28; 8247113afc8SEmmanuel Vadot 8257113afc8SEmmanuel Vadot vlan_hash_table |= (1 << crc); 8267113afc8SEmmanuel Vadot axgbe_printf(1, "%s: vid 0x%x vid_le 0x%x crc 0x%x " 8277113afc8SEmmanuel Vadot "vlan_hash_table 0x%x\n", __func__, vid, vid_le, crc, 8287113afc8SEmmanuel Vadot vlan_hash_table); 8297113afc8SEmmanuel Vadot } 83044b781cfSAndrew Turner 83144b781cfSAndrew Turner /* Set the VLAN Hash Table filtering register */ 83244b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_VLANHTR, VLHT, vlan_hash_table); 83344b781cfSAndrew Turner 8347113afc8SEmmanuel Vadot axgbe_printf(1, "%s: After updating VLANHTR 0x%x\n", __func__, 8357113afc8SEmmanuel Vadot XGMAC_IOREAD(pdata, MAC_VLANHTR)); 8367113afc8SEmmanuel Vadot 8377113afc8SEmmanuel Vadot return (0); 83844b781cfSAndrew Turner } 83944b781cfSAndrew Turner 8407113afc8SEmmanuel Vadot static int 8417113afc8SEmmanuel Vadot xgbe_set_promiscuous_mode(struct xgbe_prv_data *pdata, unsigned int enable) 84244b781cfSAndrew Turner { 84344b781cfSAndrew Turner unsigned int val = enable ? 1 : 0; 84444b781cfSAndrew Turner 84544b781cfSAndrew Turner if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == val) 8467113afc8SEmmanuel Vadot return (0); 8477113afc8SEmmanuel Vadot 8487113afc8SEmmanuel Vadot axgbe_printf(1, "%s promiscous mode\n", enable? "entering" : "leaving"); 84944b781cfSAndrew Turner 85044b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, val); 85144b781cfSAndrew Turner 85244b781cfSAndrew Turner /* Hardware will still perform VLAN filtering in promiscuous mode */ 8537113afc8SEmmanuel Vadot if (enable) { 8547113afc8SEmmanuel Vadot axgbe_printf(1, "Disabling rx vlan filtering\n"); 85544b781cfSAndrew Turner xgbe_disable_rx_vlan_filtering(pdata); 8567113afc8SEmmanuel Vadot } else { 8577113afc8SEmmanuel Vadot if ((if_getcapenable(pdata->netdev) & IFCAP_VLAN_HWFILTER)) { 8587113afc8SEmmanuel Vadot axgbe_printf(1, "Enabling rx vlan filtering\n"); 8597113afc8SEmmanuel Vadot xgbe_enable_rx_vlan_filtering(pdata); 8607113afc8SEmmanuel Vadot } 86144b781cfSAndrew Turner } 86244b781cfSAndrew Turner 8637113afc8SEmmanuel Vadot return (0); 8647113afc8SEmmanuel Vadot } 8657113afc8SEmmanuel Vadot 8667113afc8SEmmanuel Vadot static int 8677113afc8SEmmanuel Vadot xgbe_set_all_multicast_mode(struct xgbe_prv_data *pdata, unsigned int enable) 86844b781cfSAndrew Turner { 86944b781cfSAndrew Turner unsigned int val = enable ? 1 : 0; 87044b781cfSAndrew Turner 87144b781cfSAndrew Turner if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PM) == val) 8727113afc8SEmmanuel Vadot return (0); 87344b781cfSAndrew Turner 8747113afc8SEmmanuel Vadot axgbe_printf(1,"%s allmulti mode\n", enable ? "entering" : "leaving"); 87544b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, val); 87644b781cfSAndrew Turner 8777113afc8SEmmanuel Vadot return (0); 87844b781cfSAndrew Turner } 87944b781cfSAndrew Turner 8807113afc8SEmmanuel Vadot static void 8817113afc8SEmmanuel Vadot xgbe_set_mac_reg(struct xgbe_prv_data *pdata, char *addr, unsigned int *mac_reg) 88244b781cfSAndrew Turner { 88344b781cfSAndrew Turner unsigned int mac_addr_hi, mac_addr_lo; 8847113afc8SEmmanuel Vadot uint8_t *mac_addr; 88544b781cfSAndrew Turner 88644b781cfSAndrew Turner mac_addr_lo = 0; 88744b781cfSAndrew Turner mac_addr_hi = 0; 88844b781cfSAndrew Turner 8899c6d6488SAndrew Turner if (addr) { 8907113afc8SEmmanuel Vadot mac_addr = (uint8_t *)&mac_addr_lo; 8919c6d6488SAndrew Turner mac_addr[0] = addr[0]; 8929c6d6488SAndrew Turner mac_addr[1] = addr[1]; 8939c6d6488SAndrew Turner mac_addr[2] = addr[2]; 8949c6d6488SAndrew Turner mac_addr[3] = addr[3]; 8957113afc8SEmmanuel Vadot mac_addr = (uint8_t *)&mac_addr_hi; 8969c6d6488SAndrew Turner mac_addr[0] = addr[4]; 8979c6d6488SAndrew Turner mac_addr[1] = addr[5]; 89844b781cfSAndrew Turner 8997113afc8SEmmanuel Vadot axgbe_printf(1, "adding mac address %pM at %#x\n", addr, *mac_reg); 9007113afc8SEmmanuel Vadot 90144b781cfSAndrew Turner XGMAC_SET_BITS(mac_addr_hi, MAC_MACA1HR, AE, 1); 90244b781cfSAndrew Turner } 90344b781cfSAndrew Turner 90444b781cfSAndrew Turner XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_hi); 90544b781cfSAndrew Turner *mac_reg += MAC_MACA_INC; 90644b781cfSAndrew Turner XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_lo); 90744b781cfSAndrew Turner *mac_reg += MAC_MACA_INC; 90844b781cfSAndrew Turner } 90944b781cfSAndrew Turner 9107113afc8SEmmanuel Vadot static void 9117113afc8SEmmanuel Vadot xgbe_set_mac_addn_addrs(struct xgbe_prv_data *pdata) 91244b781cfSAndrew Turner { 91344b781cfSAndrew Turner unsigned int mac_reg; 91444b781cfSAndrew Turner unsigned int addn_macs; 91544b781cfSAndrew Turner 91644b781cfSAndrew Turner mac_reg = MAC_MACA1HR; 91744b781cfSAndrew Turner addn_macs = pdata->hw_feat.addn_mac; 91844b781cfSAndrew Turner 9199c6d6488SAndrew Turner xgbe_set_mac_reg(pdata, pdata->mac_addr, &mac_reg); 92044b781cfSAndrew Turner addn_macs--; 92144b781cfSAndrew Turner 92244b781cfSAndrew Turner /* Clear remaining additional MAC address entries */ 92344b781cfSAndrew Turner while (addn_macs--) 92444b781cfSAndrew Turner xgbe_set_mac_reg(pdata, NULL, &mac_reg); 92544b781cfSAndrew Turner } 92644b781cfSAndrew Turner 9277113afc8SEmmanuel Vadot static int 9287113afc8SEmmanuel Vadot xgbe_add_mac_addresses(struct xgbe_prv_data *pdata) 92944b781cfSAndrew Turner { 9307113afc8SEmmanuel Vadot /* TODO - add support to set mac hash table */ 93144b781cfSAndrew Turner xgbe_set_mac_addn_addrs(pdata); 93244b781cfSAndrew Turner 9337113afc8SEmmanuel Vadot return (0); 93444b781cfSAndrew Turner } 93544b781cfSAndrew Turner 9367113afc8SEmmanuel Vadot static int 9377113afc8SEmmanuel Vadot xgbe_set_mac_address(struct xgbe_prv_data *pdata, uint8_t *addr) 93844b781cfSAndrew Turner { 93944b781cfSAndrew Turner unsigned int mac_addr_hi, mac_addr_lo; 94044b781cfSAndrew Turner 94144b781cfSAndrew Turner mac_addr_hi = (addr[5] << 8) | (addr[4] << 0); 94244b781cfSAndrew Turner mac_addr_lo = (addr[3] << 24) | (addr[2] << 16) | 94344b781cfSAndrew Turner (addr[1] << 8) | (addr[0] << 0); 94444b781cfSAndrew Turner 94544b781cfSAndrew Turner XGMAC_IOWRITE(pdata, MAC_MACA0HR, mac_addr_hi); 94644b781cfSAndrew Turner XGMAC_IOWRITE(pdata, MAC_MACA0LR, mac_addr_lo); 94744b781cfSAndrew Turner 9487113afc8SEmmanuel Vadot return (0); 94944b781cfSAndrew Turner } 95044b781cfSAndrew Turner 9517113afc8SEmmanuel Vadot static int 9527113afc8SEmmanuel Vadot xgbe_config_rx_mode(struct xgbe_prv_data *pdata) 95344b781cfSAndrew Turner { 95444b781cfSAndrew Turner unsigned int pr_mode, am_mode; 95544b781cfSAndrew Turner 9567113afc8SEmmanuel Vadot pr_mode = ((pdata->netdev->if_drv_flags & IFF_PPROMISC) != 0); 9577113afc8SEmmanuel Vadot am_mode = ((pdata->netdev->if_drv_flags & IFF_ALLMULTI) != 0); 95844b781cfSAndrew Turner 95944b781cfSAndrew Turner xgbe_set_promiscuous_mode(pdata, pr_mode); 96044b781cfSAndrew Turner xgbe_set_all_multicast_mode(pdata, am_mode); 96144b781cfSAndrew Turner 96244b781cfSAndrew Turner xgbe_add_mac_addresses(pdata); 96344b781cfSAndrew Turner 9647113afc8SEmmanuel Vadot return (0); 96544b781cfSAndrew Turner } 96644b781cfSAndrew Turner 9677113afc8SEmmanuel Vadot static int 9687113afc8SEmmanuel Vadot xgbe_clr_gpio(struct xgbe_prv_data *pdata, unsigned int gpio) 9697113afc8SEmmanuel Vadot { 9707113afc8SEmmanuel Vadot unsigned int reg; 9717113afc8SEmmanuel Vadot 9727113afc8SEmmanuel Vadot if (gpio > 15) 9737113afc8SEmmanuel Vadot return (-EINVAL); 9747113afc8SEmmanuel Vadot 9757113afc8SEmmanuel Vadot reg = XGMAC_IOREAD(pdata, MAC_GPIOSR); 9767113afc8SEmmanuel Vadot 9777113afc8SEmmanuel Vadot reg &= ~(1 << (gpio + 16)); 9787113afc8SEmmanuel Vadot XGMAC_IOWRITE(pdata, MAC_GPIOSR, reg); 9797113afc8SEmmanuel Vadot 9807113afc8SEmmanuel Vadot return (0); 9817113afc8SEmmanuel Vadot } 9827113afc8SEmmanuel Vadot 9837113afc8SEmmanuel Vadot static int 9847113afc8SEmmanuel Vadot xgbe_set_gpio(struct xgbe_prv_data *pdata, unsigned int gpio) 9857113afc8SEmmanuel Vadot { 9867113afc8SEmmanuel Vadot unsigned int reg; 9877113afc8SEmmanuel Vadot 9887113afc8SEmmanuel Vadot if (gpio > 15) 9897113afc8SEmmanuel Vadot return (-EINVAL); 9907113afc8SEmmanuel Vadot 9917113afc8SEmmanuel Vadot reg = XGMAC_IOREAD(pdata, MAC_GPIOSR); 9927113afc8SEmmanuel Vadot 9937113afc8SEmmanuel Vadot reg |= (1 << (gpio + 16)); 9947113afc8SEmmanuel Vadot XGMAC_IOWRITE(pdata, MAC_GPIOSR, reg); 9957113afc8SEmmanuel Vadot 9967113afc8SEmmanuel Vadot return (0); 9977113afc8SEmmanuel Vadot } 9987113afc8SEmmanuel Vadot 9997113afc8SEmmanuel Vadot static int 10007113afc8SEmmanuel Vadot xgbe_read_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad, int mmd_reg) 10017113afc8SEmmanuel Vadot { 10027113afc8SEmmanuel Vadot unsigned long flags; 10037113afc8SEmmanuel Vadot unsigned int mmd_address, index, offset; 10047113afc8SEmmanuel Vadot int mmd_data; 10057113afc8SEmmanuel Vadot 10067113afc8SEmmanuel Vadot if (mmd_reg & MII_ADDR_C45) 10077113afc8SEmmanuel Vadot mmd_address = mmd_reg & ~MII_ADDR_C45; 10087113afc8SEmmanuel Vadot else 10097113afc8SEmmanuel Vadot mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); 10107113afc8SEmmanuel Vadot 10117113afc8SEmmanuel Vadot /* The PCS registers are accessed using mmio. The underlying 10127113afc8SEmmanuel Vadot * management interface uses indirect addressing to access the MMD 10137113afc8SEmmanuel Vadot * register sets. This requires accessing of the PCS register in two 10147113afc8SEmmanuel Vadot * phases, an address phase and a data phase. 10157113afc8SEmmanuel Vadot * 10167113afc8SEmmanuel Vadot * The mmio interface is based on 16-bit offsets and values. All 10177113afc8SEmmanuel Vadot * register offsets must therefore be adjusted by left shifting the 10187113afc8SEmmanuel Vadot * offset 1 bit and reading 16 bits of data. 10197113afc8SEmmanuel Vadot */ 10207113afc8SEmmanuel Vadot mmd_address <<= 1; 10217113afc8SEmmanuel Vadot index = mmd_address & ~pdata->xpcs_window_mask; 10227113afc8SEmmanuel Vadot offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask); 10237113afc8SEmmanuel Vadot 10247113afc8SEmmanuel Vadot spin_lock_irqsave(&pdata->xpcs_lock, flags); 10257113afc8SEmmanuel Vadot XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index); 10267113afc8SEmmanuel Vadot mmd_data = XPCS16_IOREAD(pdata, offset); 10277113afc8SEmmanuel Vadot spin_unlock_irqrestore(&pdata->xpcs_lock, flags); 10287113afc8SEmmanuel Vadot 10297113afc8SEmmanuel Vadot return (mmd_data); 10307113afc8SEmmanuel Vadot } 10317113afc8SEmmanuel Vadot 10327113afc8SEmmanuel Vadot static void 10337113afc8SEmmanuel Vadot xgbe_write_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad, int mmd_reg, 10347113afc8SEmmanuel Vadot int mmd_data) 10357113afc8SEmmanuel Vadot { 10367113afc8SEmmanuel Vadot unsigned long flags; 10377113afc8SEmmanuel Vadot unsigned int mmd_address, index, offset; 10387113afc8SEmmanuel Vadot 10397113afc8SEmmanuel Vadot if (mmd_reg & MII_ADDR_C45) 10407113afc8SEmmanuel Vadot mmd_address = mmd_reg & ~MII_ADDR_C45; 10417113afc8SEmmanuel Vadot else 10427113afc8SEmmanuel Vadot mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); 10437113afc8SEmmanuel Vadot 10447113afc8SEmmanuel Vadot /* The PCS registers are accessed using mmio. The underlying 10457113afc8SEmmanuel Vadot * management interface uses indirect addressing to access the MMD 10467113afc8SEmmanuel Vadot * register sets. This requires accessing of the PCS register in two 10477113afc8SEmmanuel Vadot * phases, an address phase and a data phase. 10487113afc8SEmmanuel Vadot * 10497113afc8SEmmanuel Vadot * The mmio interface is based on 16-bit offsets and values. All 10507113afc8SEmmanuel Vadot * register offsets must therefore be adjusted by left shifting the 10517113afc8SEmmanuel Vadot * offset 1 bit and writing 16 bits of data. 10527113afc8SEmmanuel Vadot */ 10537113afc8SEmmanuel Vadot mmd_address <<= 1; 10547113afc8SEmmanuel Vadot index = mmd_address & ~pdata->xpcs_window_mask; 10557113afc8SEmmanuel Vadot offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask); 10567113afc8SEmmanuel Vadot 10577113afc8SEmmanuel Vadot spin_lock_irqsave(&pdata->xpcs_lock, flags); 10587113afc8SEmmanuel Vadot XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index); 10597113afc8SEmmanuel Vadot XPCS16_IOWRITE(pdata, offset, mmd_data); 10607113afc8SEmmanuel Vadot spin_unlock_irqrestore(&pdata->xpcs_lock, flags); 10617113afc8SEmmanuel Vadot } 10627113afc8SEmmanuel Vadot 10637113afc8SEmmanuel Vadot static int 10647113afc8SEmmanuel Vadot xgbe_read_mmd_regs_v1(struct xgbe_prv_data *pdata, int prtad, int mmd_reg) 106544b781cfSAndrew Turner { 106644b781cfSAndrew Turner unsigned long flags; 106744b781cfSAndrew Turner unsigned int mmd_address; 106844b781cfSAndrew Turner int mmd_data; 106944b781cfSAndrew Turner 107044b781cfSAndrew Turner if (mmd_reg & MII_ADDR_C45) 107144b781cfSAndrew Turner mmd_address = mmd_reg & ~MII_ADDR_C45; 107244b781cfSAndrew Turner else 107344b781cfSAndrew Turner mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); 107444b781cfSAndrew Turner 107544b781cfSAndrew Turner /* The PCS registers are accessed using mmio. The underlying APB3 107644b781cfSAndrew Turner * management interface uses indirect addressing to access the MMD 107744b781cfSAndrew Turner * register sets. This requires accessing of the PCS register in two 107844b781cfSAndrew Turner * phases, an address phase and a data phase. 107944b781cfSAndrew Turner * 108044b781cfSAndrew Turner * The mmio interface is based on 32-bit offsets and values. All 108144b781cfSAndrew Turner * register offsets must therefore be adjusted by left shifting the 108244b781cfSAndrew Turner * offset 2 bits and reading 32 bits of data. 108344b781cfSAndrew Turner */ 108444b781cfSAndrew Turner spin_lock_irqsave(&pdata->xpcs_lock, flags); 10857113afc8SEmmanuel Vadot XPCS32_IOWRITE(pdata, PCS_V1_WINDOW_SELECT, mmd_address >> 8); 10867113afc8SEmmanuel Vadot mmd_data = XPCS32_IOREAD(pdata, (mmd_address & 0xff) << 2); 108744b781cfSAndrew Turner spin_unlock_irqrestore(&pdata->xpcs_lock, flags); 108844b781cfSAndrew Turner 10897113afc8SEmmanuel Vadot return (mmd_data); 109044b781cfSAndrew Turner } 109144b781cfSAndrew Turner 10927113afc8SEmmanuel Vadot static void 10937113afc8SEmmanuel Vadot xgbe_write_mmd_regs_v1(struct xgbe_prv_data *pdata, int prtad, int mmd_reg, 10947113afc8SEmmanuel Vadot int mmd_data) 109544b781cfSAndrew Turner { 109644b781cfSAndrew Turner unsigned int mmd_address; 109744b781cfSAndrew Turner unsigned long flags; 109844b781cfSAndrew Turner 109944b781cfSAndrew Turner if (mmd_reg & MII_ADDR_C45) 110044b781cfSAndrew Turner mmd_address = mmd_reg & ~MII_ADDR_C45; 110144b781cfSAndrew Turner else 110244b781cfSAndrew Turner mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); 110344b781cfSAndrew Turner 110444b781cfSAndrew Turner /* The PCS registers are accessed using mmio. The underlying APB3 110544b781cfSAndrew Turner * management interface uses indirect addressing to access the MMD 110644b781cfSAndrew Turner * register sets. This requires accessing of the PCS register in two 110744b781cfSAndrew Turner * phases, an address phase and a data phase. 110844b781cfSAndrew Turner * 110944b781cfSAndrew Turner * The mmio interface is based on 32-bit offsets and values. All 111044b781cfSAndrew Turner * register offsets must therefore be adjusted by left shifting the 11117113afc8SEmmanuel Vadot * offset 2 bits and writing 32 bits of data. 111244b781cfSAndrew Turner */ 111344b781cfSAndrew Turner spin_lock_irqsave(&pdata->xpcs_lock, flags); 11147113afc8SEmmanuel Vadot XPCS32_IOWRITE(pdata, PCS_V1_WINDOW_SELECT, mmd_address >> 8); 11157113afc8SEmmanuel Vadot XPCS32_IOWRITE(pdata, (mmd_address & 0xff) << 2, mmd_data); 111644b781cfSAndrew Turner spin_unlock_irqrestore(&pdata->xpcs_lock, flags); 111744b781cfSAndrew Turner } 111844b781cfSAndrew Turner 11197113afc8SEmmanuel Vadot static int 11207113afc8SEmmanuel Vadot xgbe_read_mmd_regs(struct xgbe_prv_data *pdata, int prtad, int mmd_reg) 112144b781cfSAndrew Turner { 11227113afc8SEmmanuel Vadot switch (pdata->vdata->xpcs_access) { 11237113afc8SEmmanuel Vadot case XGBE_XPCS_ACCESS_V1: 11247113afc8SEmmanuel Vadot return (xgbe_read_mmd_regs_v1(pdata, prtad, mmd_reg)); 11257113afc8SEmmanuel Vadot 11267113afc8SEmmanuel Vadot case XGBE_XPCS_ACCESS_V2: 11277113afc8SEmmanuel Vadot default: 11287113afc8SEmmanuel Vadot return (xgbe_read_mmd_regs_v2(pdata, prtad, mmd_reg)); 11297113afc8SEmmanuel Vadot } 113044b781cfSAndrew Turner } 113144b781cfSAndrew Turner 11327113afc8SEmmanuel Vadot static void 11337113afc8SEmmanuel Vadot xgbe_write_mmd_regs(struct xgbe_prv_data *pdata, int prtad, int mmd_reg, 11347113afc8SEmmanuel Vadot int mmd_data) 11357113afc8SEmmanuel Vadot { 11367113afc8SEmmanuel Vadot switch (pdata->vdata->xpcs_access) { 11377113afc8SEmmanuel Vadot case XGBE_XPCS_ACCESS_V1: 11387113afc8SEmmanuel Vadot return (xgbe_write_mmd_regs_v1(pdata, prtad, mmd_reg, mmd_data)); 11397113afc8SEmmanuel Vadot 11407113afc8SEmmanuel Vadot case XGBE_XPCS_ACCESS_V2: 11417113afc8SEmmanuel Vadot default: 11427113afc8SEmmanuel Vadot return (xgbe_write_mmd_regs_v2(pdata, prtad, mmd_reg, mmd_data)); 11437113afc8SEmmanuel Vadot } 11447113afc8SEmmanuel Vadot } 11457113afc8SEmmanuel Vadot 11467113afc8SEmmanuel Vadot static unsigned int 11477113afc8SEmmanuel Vadot xgbe_create_mdio_sca(int port, int reg) 11487113afc8SEmmanuel Vadot { 11497113afc8SEmmanuel Vadot unsigned int mdio_sca, da; 11507113afc8SEmmanuel Vadot 11517113afc8SEmmanuel Vadot da = (reg & MII_ADDR_C45) ? reg >> 16 : 0; 11527113afc8SEmmanuel Vadot 11537113afc8SEmmanuel Vadot mdio_sca = 0; 11547113afc8SEmmanuel Vadot XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, RA, reg); 11557113afc8SEmmanuel Vadot XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, PA, port); 11567113afc8SEmmanuel Vadot XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, DA, da); 11577113afc8SEmmanuel Vadot 11587113afc8SEmmanuel Vadot return (mdio_sca); 11597113afc8SEmmanuel Vadot } 11607113afc8SEmmanuel Vadot 11617113afc8SEmmanuel Vadot static int 11627113afc8SEmmanuel Vadot xgbe_write_ext_mii_regs(struct xgbe_prv_data *pdata, int addr, int reg, 11637113afc8SEmmanuel Vadot uint16_t val) 11647113afc8SEmmanuel Vadot { 11657113afc8SEmmanuel Vadot unsigned int mdio_sca, mdio_sccd; 11667113afc8SEmmanuel Vadot 11677113afc8SEmmanuel Vadot mtx_lock_spin(&pdata->mdio_mutex); 11687113afc8SEmmanuel Vadot 11697113afc8SEmmanuel Vadot mdio_sca = xgbe_create_mdio_sca(addr, reg); 11707113afc8SEmmanuel Vadot XGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca); 11717113afc8SEmmanuel Vadot 11727113afc8SEmmanuel Vadot mdio_sccd = 0; 11737113afc8SEmmanuel Vadot XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, DATA, val); 11747113afc8SEmmanuel Vadot XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, CMD, 1); 11757113afc8SEmmanuel Vadot XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, BUSY, 1); 11767113afc8SEmmanuel Vadot XGMAC_IOWRITE(pdata, MAC_MDIOSCCDR, mdio_sccd); 11777113afc8SEmmanuel Vadot 11787113afc8SEmmanuel Vadot if (msleep_spin(pdata, &pdata->mdio_mutex, "mdio_xfer", hz / 8) == 11797113afc8SEmmanuel Vadot EWOULDBLOCK) { 11807113afc8SEmmanuel Vadot axgbe_error("%s: MDIO write error\n", __func__); 11817113afc8SEmmanuel Vadot mtx_unlock_spin(&pdata->mdio_mutex); 11827113afc8SEmmanuel Vadot return (-ETIMEDOUT); 11837113afc8SEmmanuel Vadot } 11847113afc8SEmmanuel Vadot 11857113afc8SEmmanuel Vadot mtx_unlock_spin(&pdata->mdio_mutex); 11867113afc8SEmmanuel Vadot return (0); 11877113afc8SEmmanuel Vadot } 11887113afc8SEmmanuel Vadot 11897113afc8SEmmanuel Vadot static int 11907113afc8SEmmanuel Vadot xgbe_read_ext_mii_regs(struct xgbe_prv_data *pdata, int addr, int reg) 11917113afc8SEmmanuel Vadot { 11927113afc8SEmmanuel Vadot unsigned int mdio_sca, mdio_sccd; 11937113afc8SEmmanuel Vadot 11947113afc8SEmmanuel Vadot mtx_lock_spin(&pdata->mdio_mutex); 11957113afc8SEmmanuel Vadot 11967113afc8SEmmanuel Vadot mdio_sca = xgbe_create_mdio_sca(addr, reg); 11977113afc8SEmmanuel Vadot XGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca); 11987113afc8SEmmanuel Vadot 11997113afc8SEmmanuel Vadot mdio_sccd = 0; 12007113afc8SEmmanuel Vadot XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, CMD, 3); 12017113afc8SEmmanuel Vadot XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, BUSY, 1); 12027113afc8SEmmanuel Vadot XGMAC_IOWRITE(pdata, MAC_MDIOSCCDR, mdio_sccd); 12037113afc8SEmmanuel Vadot 12047113afc8SEmmanuel Vadot if (msleep_spin(pdata, &pdata->mdio_mutex, "mdio_xfer", hz / 8) == 12057113afc8SEmmanuel Vadot EWOULDBLOCK) { 12067113afc8SEmmanuel Vadot axgbe_error("%s: MDIO read error\n", __func__); 12077113afc8SEmmanuel Vadot mtx_unlock_spin(&pdata->mdio_mutex); 12087113afc8SEmmanuel Vadot return (-ETIMEDOUT); 12097113afc8SEmmanuel Vadot } 12107113afc8SEmmanuel Vadot 12117113afc8SEmmanuel Vadot mtx_unlock_spin(&pdata->mdio_mutex); 12127113afc8SEmmanuel Vadot 12137113afc8SEmmanuel Vadot return (XGMAC_IOREAD_BITS(pdata, MAC_MDIOSCCDR, DATA)); 12147113afc8SEmmanuel Vadot } 12157113afc8SEmmanuel Vadot 12167113afc8SEmmanuel Vadot static int 12177113afc8SEmmanuel Vadot xgbe_set_ext_mii_mode(struct xgbe_prv_data *pdata, unsigned int port, 12187113afc8SEmmanuel Vadot enum xgbe_mdio_mode mode) 12197113afc8SEmmanuel Vadot { 12207113afc8SEmmanuel Vadot unsigned int reg_val = XGMAC_IOREAD(pdata, MAC_MDIOCL22R); 12217113afc8SEmmanuel Vadot 12227113afc8SEmmanuel Vadot switch (mode) { 12237113afc8SEmmanuel Vadot case XGBE_MDIO_MODE_CL22: 12247113afc8SEmmanuel Vadot if (port > XGMAC_MAX_C22_PORT) 12257113afc8SEmmanuel Vadot return (-EINVAL); 12267113afc8SEmmanuel Vadot reg_val |= (1 << port); 12277113afc8SEmmanuel Vadot break; 12287113afc8SEmmanuel Vadot case XGBE_MDIO_MODE_CL45: 12297113afc8SEmmanuel Vadot break; 12307113afc8SEmmanuel Vadot default: 12317113afc8SEmmanuel Vadot return (-EINVAL); 12327113afc8SEmmanuel Vadot } 12337113afc8SEmmanuel Vadot 12347113afc8SEmmanuel Vadot XGMAC_IOWRITE(pdata, MAC_MDIOCL22R, reg_val); 12357113afc8SEmmanuel Vadot 12367113afc8SEmmanuel Vadot return (0); 12377113afc8SEmmanuel Vadot } 12387113afc8SEmmanuel Vadot 12397113afc8SEmmanuel Vadot static int 12407113afc8SEmmanuel Vadot xgbe_tx_complete(struct xgbe_ring_desc *rdesc) 12417113afc8SEmmanuel Vadot { 12427113afc8SEmmanuel Vadot return (!XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN)); 12437113afc8SEmmanuel Vadot } 12447113afc8SEmmanuel Vadot 12457113afc8SEmmanuel Vadot static int 12467113afc8SEmmanuel Vadot xgbe_disable_rx_csum(struct xgbe_prv_data *pdata) 124744b781cfSAndrew Turner { 124844b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 0); 124944b781cfSAndrew Turner 12507113afc8SEmmanuel Vadot axgbe_printf(0, "Receive checksum offload Disabled\n"); 12517113afc8SEmmanuel Vadot return (0); 125244b781cfSAndrew Turner } 125344b781cfSAndrew Turner 12547113afc8SEmmanuel Vadot static int 12557113afc8SEmmanuel Vadot xgbe_enable_rx_csum(struct xgbe_prv_data *pdata) 125644b781cfSAndrew Turner { 125744b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 1); 125844b781cfSAndrew Turner 12597113afc8SEmmanuel Vadot axgbe_printf(0, "Receive checksum offload Enabled\n"); 12607113afc8SEmmanuel Vadot return (0); 126144b781cfSAndrew Turner } 126244b781cfSAndrew Turner 12637113afc8SEmmanuel Vadot static void 12647113afc8SEmmanuel Vadot xgbe_tx_desc_reset(struct xgbe_ring_data *rdata) 126544b781cfSAndrew Turner { 126644b781cfSAndrew Turner struct xgbe_ring_desc *rdesc = rdata->rdesc; 126744b781cfSAndrew Turner 126844b781cfSAndrew Turner /* Reset the Tx descriptor 126944b781cfSAndrew Turner * Set buffer 1 (lo) address to zero 127044b781cfSAndrew Turner * Set buffer 1 (hi) address to zero 127144b781cfSAndrew Turner * Reset all other control bits (IC, TTSE, B2L & B1L) 127244b781cfSAndrew Turner * Reset all other control bits (OWN, CTXT, FD, LD, CPC, CIC, etc) 127344b781cfSAndrew Turner */ 127444b781cfSAndrew Turner rdesc->desc0 = 0; 127544b781cfSAndrew Turner rdesc->desc1 = 0; 127644b781cfSAndrew Turner rdesc->desc2 = 0; 127744b781cfSAndrew Turner rdesc->desc3 = 0; 127844b781cfSAndrew Turner 12797113afc8SEmmanuel Vadot wmb(); 128044b781cfSAndrew Turner } 128144b781cfSAndrew Turner 12827113afc8SEmmanuel Vadot static void 12837113afc8SEmmanuel Vadot xgbe_tx_desc_init(struct xgbe_channel *channel) 128444b781cfSAndrew Turner { 128544b781cfSAndrew Turner struct xgbe_ring *ring = channel->tx_ring; 128644b781cfSAndrew Turner struct xgbe_ring_data *rdata; 128744b781cfSAndrew Turner int i; 128844b781cfSAndrew Turner int start_index = ring->cur; 128944b781cfSAndrew Turner 129044b781cfSAndrew Turner /* Initialze all descriptors */ 129144b781cfSAndrew Turner for (i = 0; i < ring->rdesc_count; i++) { 129244b781cfSAndrew Turner rdata = XGBE_GET_DESC_DATA(ring, i); 129344b781cfSAndrew Turner 129444b781cfSAndrew Turner /* Initialize Tx descriptor */ 129544b781cfSAndrew Turner xgbe_tx_desc_reset(rdata); 129644b781cfSAndrew Turner } 129744b781cfSAndrew Turner 129844b781cfSAndrew Turner /* Update the total number of Tx descriptors */ 129944b781cfSAndrew Turner XGMAC_DMA_IOWRITE(channel, DMA_CH_TDRLR, ring->rdesc_count - 1); 130044b781cfSAndrew Turner 130144b781cfSAndrew Turner /* Update the starting address of descriptor ring */ 130244b781cfSAndrew Turner rdata = XGBE_GET_DESC_DATA(ring, start_index); 130344b781cfSAndrew Turner XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_HI, 13049c6d6488SAndrew Turner upper_32_bits(rdata->rdata_paddr)); 130544b781cfSAndrew Turner XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_LO, 13069c6d6488SAndrew Turner lower_32_bits(rdata->rdata_paddr)); 130744b781cfSAndrew Turner } 130844b781cfSAndrew Turner 13097113afc8SEmmanuel Vadot static void 13107113afc8SEmmanuel Vadot xgbe_rx_desc_init(struct xgbe_channel *channel) 131144b781cfSAndrew Turner { 131244b781cfSAndrew Turner struct xgbe_ring *ring = channel->rx_ring; 131344b781cfSAndrew Turner struct xgbe_ring_data *rdata; 131444b781cfSAndrew Turner unsigned int start_index = ring->cur; 131544b781cfSAndrew Turner 13167113afc8SEmmanuel Vadot /* 13177113afc8SEmmanuel Vadot * Just set desc_count and the starting address of the desc list 13187113afc8SEmmanuel Vadot * here. Rest will be done as part of the txrx path. 13197113afc8SEmmanuel Vadot */ 13209c6d6488SAndrew Turner 132144b781cfSAndrew Turner /* Update the total number of Rx descriptors */ 132244b781cfSAndrew Turner XGMAC_DMA_IOWRITE(channel, DMA_CH_RDRLR, ring->rdesc_count - 1); 132344b781cfSAndrew Turner 132444b781cfSAndrew Turner /* Update the starting address of descriptor ring */ 132544b781cfSAndrew Turner rdata = XGBE_GET_DESC_DATA(ring, start_index); 132644b781cfSAndrew Turner XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_HI, 13279c6d6488SAndrew Turner upper_32_bits(rdata->rdata_paddr)); 132844b781cfSAndrew Turner XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_LO, 13299c6d6488SAndrew Turner lower_32_bits(rdata->rdata_paddr)); 133044b781cfSAndrew Turner } 133144b781cfSAndrew Turner 13327113afc8SEmmanuel Vadot static int 13337113afc8SEmmanuel Vadot xgbe_dev_read(struct xgbe_channel *channel) 133444b781cfSAndrew Turner { 133544b781cfSAndrew Turner struct xgbe_prv_data *pdata = channel->pdata; 133644b781cfSAndrew Turner struct xgbe_ring *ring = channel->rx_ring; 133744b781cfSAndrew Turner struct xgbe_ring_data *rdata; 133844b781cfSAndrew Turner struct xgbe_ring_desc *rdesc; 133944b781cfSAndrew Turner struct xgbe_packet_data *packet = &ring->packet_data; 13407113afc8SEmmanuel Vadot unsigned int err, etlt, l34t; 134144b781cfSAndrew Turner 13427113afc8SEmmanuel Vadot axgbe_printf(1, "-->xgbe_dev_read: cur = %d\n", ring->cur); 134344b781cfSAndrew Turner 134444b781cfSAndrew Turner rdata = XGBE_GET_DESC_DATA(ring, ring->cur); 134544b781cfSAndrew Turner rdesc = rdata->rdesc; 134644b781cfSAndrew Turner 134744b781cfSAndrew Turner /* Check for data availability */ 134844b781cfSAndrew Turner if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN)) 13497113afc8SEmmanuel Vadot return (1); 135044b781cfSAndrew Turner 13517113afc8SEmmanuel Vadot rmb(); 13527113afc8SEmmanuel Vadot 13537113afc8SEmmanuel Vadot if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CTXT)) { 13547113afc8SEmmanuel Vadot /* TODO - Timestamp Context Descriptor */ 13557113afc8SEmmanuel Vadot 13567113afc8SEmmanuel Vadot XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 13577113afc8SEmmanuel Vadot CONTEXT, 1); 13587113afc8SEmmanuel Vadot XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 13597113afc8SEmmanuel Vadot CONTEXT_NEXT, 0); 13607113afc8SEmmanuel Vadot return (0); 13617113afc8SEmmanuel Vadot } 136244b781cfSAndrew Turner 136344b781cfSAndrew Turner /* Normal Descriptor, be sure Context Descriptor bit is off */ 136444b781cfSAndrew Turner XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, CONTEXT, 0); 136544b781cfSAndrew Turner 136644b781cfSAndrew Turner /* Indicate if a Context Descriptor is next */ 136744b781cfSAndrew Turner if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CDA)) 136844b781cfSAndrew Turner XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 136944b781cfSAndrew Turner CONTEXT_NEXT, 1); 137044b781cfSAndrew Turner 137144b781cfSAndrew Turner /* Get the header length */ 137244b781cfSAndrew Turner if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, FD)) { 13737113afc8SEmmanuel Vadot XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 13747113afc8SEmmanuel Vadot FIRST, 1); 137544b781cfSAndrew Turner rdata->rx.hdr_len = XGMAC_GET_BITS_LE(rdesc->desc2, 137644b781cfSAndrew Turner RX_NORMAL_DESC2, HL); 13777113afc8SEmmanuel Vadot if (rdata->rx.hdr_len) 13787113afc8SEmmanuel Vadot pdata->ext_stats.rx_split_header_packets++; 13797113afc8SEmmanuel Vadot } else 13807113afc8SEmmanuel Vadot XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 13817113afc8SEmmanuel Vadot FIRST, 0); 13827113afc8SEmmanuel Vadot 13837113afc8SEmmanuel Vadot /* Get the RSS hash */ 13847113afc8SEmmanuel Vadot if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, RSV)) { 13857113afc8SEmmanuel Vadot XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 13867113afc8SEmmanuel Vadot RSS_HASH, 1); 13877113afc8SEmmanuel Vadot 13887113afc8SEmmanuel Vadot packet->rss_hash = le32_to_cpu(rdesc->desc1); 13897113afc8SEmmanuel Vadot 13907113afc8SEmmanuel Vadot l34t = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, L34T); 13917113afc8SEmmanuel Vadot switch (l34t) { 13927113afc8SEmmanuel Vadot case RX_DESC3_L34T_IPV4_TCP: 13937113afc8SEmmanuel Vadot packet->rss_hash_type = M_HASHTYPE_RSS_TCP_IPV4; 13947113afc8SEmmanuel Vadot break; 13957113afc8SEmmanuel Vadot case RX_DESC3_L34T_IPV4_UDP: 13967113afc8SEmmanuel Vadot packet->rss_hash_type = M_HASHTYPE_RSS_UDP_IPV4; 13977113afc8SEmmanuel Vadot break; 13987113afc8SEmmanuel Vadot case RX_DESC3_L34T_IPV6_TCP: 13997113afc8SEmmanuel Vadot packet->rss_hash_type = M_HASHTYPE_RSS_TCP_IPV6; 14007113afc8SEmmanuel Vadot break; 14017113afc8SEmmanuel Vadot case RX_DESC3_L34T_IPV6_UDP: 14027113afc8SEmmanuel Vadot packet->rss_hash_type = M_HASHTYPE_RSS_UDP_IPV6; 14037113afc8SEmmanuel Vadot break; 14047113afc8SEmmanuel Vadot default: 14057113afc8SEmmanuel Vadot packet->rss_hash_type = M_HASHTYPE_OPAQUE; 14067113afc8SEmmanuel Vadot break; 14077113afc8SEmmanuel Vadot } 140844b781cfSAndrew Turner } 140944b781cfSAndrew Turner 141044b781cfSAndrew Turner /* Not all the data has been transferred for this packet */ 14117113afc8SEmmanuel Vadot if (!XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, LD)) { 14127113afc8SEmmanuel Vadot /* This is not the last of the data for this packet */ 141344b781cfSAndrew Turner XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 14147113afc8SEmmanuel Vadot LAST, 0); 14157113afc8SEmmanuel Vadot return (0); 141644b781cfSAndrew Turner } 141744b781cfSAndrew Turner 141844b781cfSAndrew Turner /* This is the last of the data for this packet */ 141944b781cfSAndrew Turner XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 14207113afc8SEmmanuel Vadot LAST, 1); 14217113afc8SEmmanuel Vadot 14227113afc8SEmmanuel Vadot /* Get the packet length */ 14237113afc8SEmmanuel Vadot rdata->rx.len = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, PL); 14247113afc8SEmmanuel Vadot 14257113afc8SEmmanuel Vadot /* Set checksum done indicator as appropriate */ 14267113afc8SEmmanuel Vadot /* TODO - add tunneling support */ 14277113afc8SEmmanuel Vadot XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 14287113afc8SEmmanuel Vadot CSUM_DONE, 1); 142944b781cfSAndrew Turner 143044b781cfSAndrew Turner /* Check for errors (only valid in last descriptor) */ 143144b781cfSAndrew Turner err = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ES); 143244b781cfSAndrew Turner etlt = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ETLT); 14337113afc8SEmmanuel Vadot axgbe_printf(1, "%s: err=%u, etlt=%#x\n", __func__, err, etlt); 143444b781cfSAndrew Turner 14357113afc8SEmmanuel Vadot if (!err || !etlt) { 14367113afc8SEmmanuel Vadot /* No error if err is 0 or etlt is 0 */ 14377113afc8SEmmanuel Vadot if (etlt == 0x09) { 14387113afc8SEmmanuel Vadot XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 14397113afc8SEmmanuel Vadot VLAN_CTAG, 1); 14407113afc8SEmmanuel Vadot packet->vlan_ctag = XGMAC_GET_BITS_LE(rdesc->desc0, 14417113afc8SEmmanuel Vadot RX_NORMAL_DESC0, OVT); 14427113afc8SEmmanuel Vadot axgbe_printf(1, "vlan-ctag=%#06x\n", packet->vlan_ctag); 14437113afc8SEmmanuel Vadot } 14447113afc8SEmmanuel Vadot } else { 14457113afc8SEmmanuel Vadot unsigned int tnp = XGMAC_GET_BITS(packet->attributes, 14467113afc8SEmmanuel Vadot RX_PACKET_ATTRIBUTES, TNP); 14477113afc8SEmmanuel Vadot 14487113afc8SEmmanuel Vadot if ((etlt == 0x05) || (etlt == 0x06)) { 14497113afc8SEmmanuel Vadot axgbe_printf(1, "%s: err1 l34t %d err 0x%x etlt 0x%x\n", 14507113afc8SEmmanuel Vadot __func__, l34t, err, etlt); 145144b781cfSAndrew Turner XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 145244b781cfSAndrew Turner CSUM_DONE, 0); 14537113afc8SEmmanuel Vadot XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 14547113afc8SEmmanuel Vadot TNPCSUM_DONE, 0); 14557113afc8SEmmanuel Vadot pdata->ext_stats.rx_csum_errors++; 14567113afc8SEmmanuel Vadot } else if (tnp && ((etlt == 0x09) || (etlt == 0x0a))) { 14577113afc8SEmmanuel Vadot axgbe_printf(1, "%s: err2 l34t %d err 0x%x etlt 0x%x\n", 14587113afc8SEmmanuel Vadot __func__, l34t, err, etlt); 14597113afc8SEmmanuel Vadot XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 14607113afc8SEmmanuel Vadot CSUM_DONE, 0); 14617113afc8SEmmanuel Vadot XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 14627113afc8SEmmanuel Vadot TNPCSUM_DONE, 0); 14637113afc8SEmmanuel Vadot pdata->ext_stats.rx_vxlan_csum_errors++; 14647113afc8SEmmanuel Vadot } else { 14657113afc8SEmmanuel Vadot axgbe_printf(1, "%s: tnp %d l34t %d err 0x%x etlt 0x%x\n", 14667113afc8SEmmanuel Vadot __func__, tnp, l34t, err, etlt); 14677113afc8SEmmanuel Vadot axgbe_printf(1, "%s: Channel: %d SR 0x%x DSR 0x%x \n", 14687113afc8SEmmanuel Vadot __func__, channel->queue_index, 14697113afc8SEmmanuel Vadot XGMAC_DMA_IOREAD(channel, DMA_CH_SR), 14707113afc8SEmmanuel Vadot XGMAC_DMA_IOREAD(channel, DMA_CH_DSR)); 14717113afc8SEmmanuel Vadot axgbe_printf(1, "%s: ring cur %d dirty %d\n", 14727113afc8SEmmanuel Vadot __func__, ring->cur, ring->dirty); 14737113afc8SEmmanuel Vadot axgbe_printf(1, "%s: Desc 0x%08x-0x%08x-0x%08x-0x%08x\n", 14747113afc8SEmmanuel Vadot __func__, rdesc->desc0, rdesc->desc1, rdesc->desc2, 14757113afc8SEmmanuel Vadot rdesc->desc3); 147644b781cfSAndrew Turner XGMAC_SET_BITS(packet->errors, RX_PACKET_ERRORS, 147744b781cfSAndrew Turner FRAME, 1); 147844b781cfSAndrew Turner } 147944b781cfSAndrew Turner } 148044b781cfSAndrew Turner 14817113afc8SEmmanuel Vadot axgbe_printf(1, "<--xgbe_dev_read: %s - descriptor=%u (cur=%d)\n", 14827113afc8SEmmanuel Vadot channel->name, ring->cur & (ring->rdesc_count - 1), ring->cur); 14837113afc8SEmmanuel Vadot 14847113afc8SEmmanuel Vadot return (0); 14857113afc8SEmmanuel Vadot } 14867113afc8SEmmanuel Vadot 14877113afc8SEmmanuel Vadot static int 14887113afc8SEmmanuel Vadot xgbe_is_context_desc(struct xgbe_ring_desc *rdesc) 148944b781cfSAndrew Turner { 149044b781cfSAndrew Turner /* Rx and Tx share CTXT bit, so check TDES3.CTXT bit */ 14917113afc8SEmmanuel Vadot return (XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT)); 149244b781cfSAndrew Turner } 149344b781cfSAndrew Turner 14947113afc8SEmmanuel Vadot static int 14957113afc8SEmmanuel Vadot xgbe_is_last_desc(struct xgbe_ring_desc *rdesc) 149644b781cfSAndrew Turner { 149744b781cfSAndrew Turner /* Rx and Tx share LD bit, so check TDES3.LD bit */ 14987113afc8SEmmanuel Vadot return (XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD)); 149944b781cfSAndrew Turner } 150044b781cfSAndrew Turner 15017113afc8SEmmanuel Vadot static int 15027113afc8SEmmanuel Vadot xgbe_enable_int(struct xgbe_channel *channel, enum xgbe_int int_id) 150344b781cfSAndrew Turner { 15047113afc8SEmmanuel Vadot struct xgbe_prv_data *pdata = channel->pdata; 150544b781cfSAndrew Turner 15067113afc8SEmmanuel Vadot axgbe_printf(1, "enable_int: DMA_CH_IER read - 0x%x\n", 15077113afc8SEmmanuel Vadot channel->curr_ier); 150844b781cfSAndrew Turner 150944b781cfSAndrew Turner switch (int_id) { 151044b781cfSAndrew Turner case XGMAC_INT_DMA_CH_SR_TI: 15117113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 1); 151244b781cfSAndrew Turner break; 151344b781cfSAndrew Turner case XGMAC_INT_DMA_CH_SR_TPS: 15147113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TXSE, 1); 151544b781cfSAndrew Turner break; 151644b781cfSAndrew Turner case XGMAC_INT_DMA_CH_SR_TBU: 15177113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TBUE, 1); 151844b781cfSAndrew Turner break; 151944b781cfSAndrew Turner case XGMAC_INT_DMA_CH_SR_RI: 15207113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 1); 152144b781cfSAndrew Turner break; 152244b781cfSAndrew Turner case XGMAC_INT_DMA_CH_SR_RBU: 15237113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 1); 152444b781cfSAndrew Turner break; 152544b781cfSAndrew Turner case XGMAC_INT_DMA_CH_SR_RPS: 15267113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RSE, 1); 152744b781cfSAndrew Turner break; 152844b781cfSAndrew Turner case XGMAC_INT_DMA_CH_SR_TI_RI: 15297113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 1); 15307113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 1); 153144b781cfSAndrew Turner break; 153244b781cfSAndrew Turner case XGMAC_INT_DMA_CH_SR_FBE: 15337113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 1); 153444b781cfSAndrew Turner break; 153544b781cfSAndrew Turner case XGMAC_INT_DMA_ALL: 15367113afc8SEmmanuel Vadot channel->curr_ier |= channel->saved_ier; 153744b781cfSAndrew Turner break; 153844b781cfSAndrew Turner default: 15397113afc8SEmmanuel Vadot return (-1); 154044b781cfSAndrew Turner } 154144b781cfSAndrew Turner 15427113afc8SEmmanuel Vadot XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, channel->curr_ier); 154344b781cfSAndrew Turner 15447113afc8SEmmanuel Vadot axgbe_printf(1, "enable_int: DMA_CH_IER write - 0x%x\n", 15457113afc8SEmmanuel Vadot channel->curr_ier); 15467113afc8SEmmanuel Vadot 15477113afc8SEmmanuel Vadot return (0); 154844b781cfSAndrew Turner } 154944b781cfSAndrew Turner 15507113afc8SEmmanuel Vadot static int 15517113afc8SEmmanuel Vadot xgbe_disable_int(struct xgbe_channel *channel, enum xgbe_int int_id) 155244b781cfSAndrew Turner { 15537113afc8SEmmanuel Vadot struct xgbe_prv_data *pdata = channel->pdata; 155444b781cfSAndrew Turner 15557113afc8SEmmanuel Vadot axgbe_printf(1, "disable_int: DMA_CH_IER read - 0x%x\n", 15567113afc8SEmmanuel Vadot channel->curr_ier); 155744b781cfSAndrew Turner 155844b781cfSAndrew Turner switch (int_id) { 155944b781cfSAndrew Turner case XGMAC_INT_DMA_CH_SR_TI: 15607113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 0); 156144b781cfSAndrew Turner break; 156244b781cfSAndrew Turner case XGMAC_INT_DMA_CH_SR_TPS: 15637113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TXSE, 0); 156444b781cfSAndrew Turner break; 156544b781cfSAndrew Turner case XGMAC_INT_DMA_CH_SR_TBU: 15667113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TBUE, 0); 156744b781cfSAndrew Turner break; 156844b781cfSAndrew Turner case XGMAC_INT_DMA_CH_SR_RI: 15697113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 0); 157044b781cfSAndrew Turner break; 157144b781cfSAndrew Turner case XGMAC_INT_DMA_CH_SR_RBU: 15727113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 0); 157344b781cfSAndrew Turner break; 157444b781cfSAndrew Turner case XGMAC_INT_DMA_CH_SR_RPS: 15757113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RSE, 0); 157644b781cfSAndrew Turner break; 157744b781cfSAndrew Turner case XGMAC_INT_DMA_CH_SR_TI_RI: 15787113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 0); 15797113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 0); 158044b781cfSAndrew Turner break; 158144b781cfSAndrew Turner case XGMAC_INT_DMA_CH_SR_FBE: 15827113afc8SEmmanuel Vadot XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 0); 158344b781cfSAndrew Turner break; 158444b781cfSAndrew Turner case XGMAC_INT_DMA_ALL: 15857113afc8SEmmanuel Vadot channel->saved_ier = channel->curr_ier; 15867113afc8SEmmanuel Vadot channel->curr_ier = 0; 158744b781cfSAndrew Turner break; 158844b781cfSAndrew Turner default: 15897113afc8SEmmanuel Vadot return (-1); 159044b781cfSAndrew Turner } 159144b781cfSAndrew Turner 15927113afc8SEmmanuel Vadot XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, channel->curr_ier); 159344b781cfSAndrew Turner 15947113afc8SEmmanuel Vadot axgbe_printf(1, "disable_int: DMA_CH_IER write - 0x%x\n", 15957113afc8SEmmanuel Vadot channel->curr_ier); 15967113afc8SEmmanuel Vadot 15977113afc8SEmmanuel Vadot return (0); 159844b781cfSAndrew Turner } 159944b781cfSAndrew Turner 16007113afc8SEmmanuel Vadot static int 16017113afc8SEmmanuel Vadot __xgbe_exit(struct xgbe_prv_data *pdata) 160244b781cfSAndrew Turner { 160344b781cfSAndrew Turner unsigned int count = 2000; 160444b781cfSAndrew Turner 160544b781cfSAndrew Turner /* Issue a software reset */ 160644b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, DMA_MR, SWR, 1); 16079c6d6488SAndrew Turner DELAY(10); 160844b781cfSAndrew Turner 160944b781cfSAndrew Turner /* Poll Until Poll Condition */ 161044b781cfSAndrew Turner while (--count && XGMAC_IOREAD_BITS(pdata, DMA_MR, SWR)) 16119c6d6488SAndrew Turner DELAY(500); 161244b781cfSAndrew Turner 161344b781cfSAndrew Turner if (!count) 16147113afc8SEmmanuel Vadot return (-EBUSY); 161544b781cfSAndrew Turner 16167113afc8SEmmanuel Vadot return (0); 161744b781cfSAndrew Turner } 161844b781cfSAndrew Turner 16197113afc8SEmmanuel Vadot static int 16207113afc8SEmmanuel Vadot xgbe_exit(struct xgbe_prv_data *pdata) 16217113afc8SEmmanuel Vadot { 16227113afc8SEmmanuel Vadot int ret; 16237113afc8SEmmanuel Vadot 16247113afc8SEmmanuel Vadot /* To guard against possible incorrectly generated interrupts, 16257113afc8SEmmanuel Vadot * issue the software reset twice. 16267113afc8SEmmanuel Vadot */ 16277113afc8SEmmanuel Vadot ret = __xgbe_exit(pdata); 16287113afc8SEmmanuel Vadot if (ret) { 16297113afc8SEmmanuel Vadot axgbe_error("%s: exit error %d\n", __func__, ret); 16307113afc8SEmmanuel Vadot return (ret); 16317113afc8SEmmanuel Vadot } 16327113afc8SEmmanuel Vadot 16337113afc8SEmmanuel Vadot return (__xgbe_exit(pdata)); 16347113afc8SEmmanuel Vadot } 16357113afc8SEmmanuel Vadot 16367113afc8SEmmanuel Vadot static int 16377113afc8SEmmanuel Vadot xgbe_flush_tx_queues(struct xgbe_prv_data *pdata) 163844b781cfSAndrew Turner { 163944b781cfSAndrew Turner unsigned int i, count; 164044b781cfSAndrew Turner 164144b781cfSAndrew Turner if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) < 0x21) 16427113afc8SEmmanuel Vadot return (0); 164344b781cfSAndrew Turner 164444b781cfSAndrew Turner for (i = 0; i < pdata->tx_q_count; i++) 164544b781cfSAndrew Turner XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, FTQ, 1); 164644b781cfSAndrew Turner 164744b781cfSAndrew Turner /* Poll Until Poll Condition */ 164844b781cfSAndrew Turner for (i = 0; i < pdata->tx_q_count; i++) { 164944b781cfSAndrew Turner count = 2000; 165044b781cfSAndrew Turner while (--count && XGMAC_MTL_IOREAD_BITS(pdata, i, 165144b781cfSAndrew Turner MTL_Q_TQOMR, FTQ)) 16529c6d6488SAndrew Turner DELAY(500); 165344b781cfSAndrew Turner 165444b781cfSAndrew Turner if (!count) 16557113afc8SEmmanuel Vadot return (-EBUSY); 165644b781cfSAndrew Turner } 165744b781cfSAndrew Turner 16587113afc8SEmmanuel Vadot return (0); 165944b781cfSAndrew Turner } 166044b781cfSAndrew Turner 16617113afc8SEmmanuel Vadot static void 16627113afc8SEmmanuel Vadot xgbe_config_dma_bus(struct xgbe_prv_data *pdata) 166344b781cfSAndrew Turner { 16647113afc8SEmmanuel Vadot unsigned int sbmr; 16657113afc8SEmmanuel Vadot 16667113afc8SEmmanuel Vadot sbmr = XGMAC_IOREAD(pdata, DMA_SBMR); 16677113afc8SEmmanuel Vadot 166844b781cfSAndrew Turner /* Set enhanced addressing mode */ 16697113afc8SEmmanuel Vadot XGMAC_SET_BITS(sbmr, DMA_SBMR, EAME, 1); 167044b781cfSAndrew Turner 167144b781cfSAndrew Turner /* Set the System Bus mode */ 16727113afc8SEmmanuel Vadot XGMAC_SET_BITS(sbmr, DMA_SBMR, UNDEF, 1); 16737113afc8SEmmanuel Vadot XGMAC_SET_BITS(sbmr, DMA_SBMR, BLEN, pdata->blen >> 2); 16747113afc8SEmmanuel Vadot XGMAC_SET_BITS(sbmr, DMA_SBMR, AAL, pdata->aal); 16757113afc8SEmmanuel Vadot XGMAC_SET_BITS(sbmr, DMA_SBMR, RD_OSR_LMT, pdata->rd_osr_limit - 1); 16767113afc8SEmmanuel Vadot XGMAC_SET_BITS(sbmr, DMA_SBMR, WR_OSR_LMT, pdata->wr_osr_limit - 1); 16777113afc8SEmmanuel Vadot 16787113afc8SEmmanuel Vadot XGMAC_IOWRITE(pdata, DMA_SBMR, sbmr); 16797113afc8SEmmanuel Vadot 16807113afc8SEmmanuel Vadot /* Set descriptor fetching threshold */ 16817113afc8SEmmanuel Vadot if (pdata->vdata->tx_desc_prefetch) 16827113afc8SEmmanuel Vadot XGMAC_IOWRITE_BITS(pdata, DMA_TXEDMACR, TDPS, 16837113afc8SEmmanuel Vadot pdata->vdata->tx_desc_prefetch); 16847113afc8SEmmanuel Vadot 16857113afc8SEmmanuel Vadot if (pdata->vdata->rx_desc_prefetch) 16867113afc8SEmmanuel Vadot XGMAC_IOWRITE_BITS(pdata, DMA_RXEDMACR, RDPS, 16877113afc8SEmmanuel Vadot pdata->vdata->rx_desc_prefetch); 168844b781cfSAndrew Turner } 168944b781cfSAndrew Turner 16907113afc8SEmmanuel Vadot static void 16917113afc8SEmmanuel Vadot xgbe_config_dma_cache(struct xgbe_prv_data *pdata) 169244b781cfSAndrew Turner { 16937113afc8SEmmanuel Vadot XGMAC_IOWRITE(pdata, DMA_AXIARCR, pdata->arcr); 16947113afc8SEmmanuel Vadot XGMAC_IOWRITE(pdata, DMA_AXIAWCR, pdata->awcr); 16957113afc8SEmmanuel Vadot if (pdata->awarcr) 16967113afc8SEmmanuel Vadot XGMAC_IOWRITE(pdata, DMA_AXIAWARCR, pdata->awarcr); 169744b781cfSAndrew Turner } 169844b781cfSAndrew Turner 16997113afc8SEmmanuel Vadot static void 17007113afc8SEmmanuel Vadot xgbe_config_mtl_mode(struct xgbe_prv_data *pdata) 170144b781cfSAndrew Turner { 170244b781cfSAndrew Turner unsigned int i; 170344b781cfSAndrew Turner 170444b781cfSAndrew Turner /* Set Tx to weighted round robin scheduling algorithm */ 170544b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_WRR); 170644b781cfSAndrew Turner 170744b781cfSAndrew Turner /* Set Tx traffic classes to use WRR algorithm with equal weights */ 170844b781cfSAndrew Turner for (i = 0; i < pdata->hw_feat.tc_cnt; i++) { 170944b781cfSAndrew Turner XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, 171044b781cfSAndrew Turner MTL_TSA_ETS); 171144b781cfSAndrew Turner XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, 1); 171244b781cfSAndrew Turner } 171344b781cfSAndrew Turner 171444b781cfSAndrew Turner /* Set Rx to strict priority algorithm */ 171544b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MTL_OMR, RAA, MTL_RAA_SP); 171644b781cfSAndrew Turner } 171744b781cfSAndrew Turner 17187113afc8SEmmanuel Vadot static void 17197113afc8SEmmanuel Vadot xgbe_queue_flow_control_threshold(struct xgbe_prv_data *pdata, 17207113afc8SEmmanuel Vadot unsigned int queue, unsigned int q_fifo_size) 17217113afc8SEmmanuel Vadot { 17227113afc8SEmmanuel Vadot unsigned int frame_fifo_size; 17237113afc8SEmmanuel Vadot unsigned int rfa, rfd; 17247113afc8SEmmanuel Vadot 17257113afc8SEmmanuel Vadot frame_fifo_size = XGMAC_FLOW_CONTROL_ALIGN(xgbe_get_max_frame(pdata)); 17267113afc8SEmmanuel Vadot axgbe_printf(1, "%s: queue %d q_fifo_size %d frame_fifo_size 0x%x\n", 17277113afc8SEmmanuel Vadot __func__, queue, q_fifo_size, frame_fifo_size); 17287113afc8SEmmanuel Vadot 17297113afc8SEmmanuel Vadot /* TODO - add pfc/ets related support */ 17307113afc8SEmmanuel Vadot 17317113afc8SEmmanuel Vadot /* This path deals with just maximum frame sizes which are 17327113afc8SEmmanuel Vadot * limited to a jumbo frame of 9,000 (plus headers, etc.) 17337113afc8SEmmanuel Vadot * so we can never exceed the maximum allowable RFA/RFD 17347113afc8SEmmanuel Vadot * values. 17357113afc8SEmmanuel Vadot */ 17367113afc8SEmmanuel Vadot if (q_fifo_size <= 2048) { 17377113afc8SEmmanuel Vadot /* rx_rfd to zero to signal no flow control */ 17387113afc8SEmmanuel Vadot pdata->rx_rfa[queue] = 0; 17397113afc8SEmmanuel Vadot pdata->rx_rfd[queue] = 0; 17407113afc8SEmmanuel Vadot return; 17417113afc8SEmmanuel Vadot } 17427113afc8SEmmanuel Vadot 17437113afc8SEmmanuel Vadot if (q_fifo_size <= 4096) { 17447113afc8SEmmanuel Vadot /* Between 2048 and 4096 */ 17457113afc8SEmmanuel Vadot pdata->rx_rfa[queue] = 0; /* Full - 1024 bytes */ 17467113afc8SEmmanuel Vadot pdata->rx_rfd[queue] = 1; /* Full - 1536 bytes */ 17477113afc8SEmmanuel Vadot return; 17487113afc8SEmmanuel Vadot } 17497113afc8SEmmanuel Vadot 17507113afc8SEmmanuel Vadot if (q_fifo_size <= frame_fifo_size) { 17517113afc8SEmmanuel Vadot /* Between 4096 and max-frame */ 17527113afc8SEmmanuel Vadot pdata->rx_rfa[queue] = 2; /* Full - 2048 bytes */ 17537113afc8SEmmanuel Vadot pdata->rx_rfd[queue] = 5; /* Full - 3584 bytes */ 17547113afc8SEmmanuel Vadot return; 17557113afc8SEmmanuel Vadot } 17567113afc8SEmmanuel Vadot 17577113afc8SEmmanuel Vadot if (q_fifo_size <= (frame_fifo_size * 3)) { 17587113afc8SEmmanuel Vadot /* Between max-frame and 3 max-frames, 17597113afc8SEmmanuel Vadot * trigger if we get just over a frame of data and 17607113afc8SEmmanuel Vadot * resume when we have just under half a frame left. 17617113afc8SEmmanuel Vadot */ 17627113afc8SEmmanuel Vadot rfa = q_fifo_size - frame_fifo_size; 17637113afc8SEmmanuel Vadot rfd = rfa + (frame_fifo_size / 2); 17647113afc8SEmmanuel Vadot } else { 17657113afc8SEmmanuel Vadot /* Above 3 max-frames - trigger when just over 17667113afc8SEmmanuel Vadot * 2 frames of space available 17677113afc8SEmmanuel Vadot */ 17687113afc8SEmmanuel Vadot rfa = frame_fifo_size * 2; 17697113afc8SEmmanuel Vadot rfa += XGMAC_FLOW_CONTROL_UNIT; 17707113afc8SEmmanuel Vadot rfd = rfa + frame_fifo_size; 17717113afc8SEmmanuel Vadot } 17727113afc8SEmmanuel Vadot 17737113afc8SEmmanuel Vadot pdata->rx_rfa[queue] = XGMAC_FLOW_CONTROL_VALUE(rfa); 17747113afc8SEmmanuel Vadot pdata->rx_rfd[queue] = XGMAC_FLOW_CONTROL_VALUE(rfd); 17757113afc8SEmmanuel Vadot axgbe_printf(1, "%s: forced queue %d rfa 0x%x rfd 0x%x\n", __func__, 17767113afc8SEmmanuel Vadot queue, pdata->rx_rfa[queue], pdata->rx_rfd[queue]); 17777113afc8SEmmanuel Vadot } 17787113afc8SEmmanuel Vadot 17797113afc8SEmmanuel Vadot static void 17807113afc8SEmmanuel Vadot xgbe_calculate_flow_control_threshold(struct xgbe_prv_data *pdata, 17817113afc8SEmmanuel Vadot unsigned int *fifo) 17827113afc8SEmmanuel Vadot { 17837113afc8SEmmanuel Vadot unsigned int q_fifo_size; 17847113afc8SEmmanuel Vadot unsigned int i; 17857113afc8SEmmanuel Vadot 17867113afc8SEmmanuel Vadot for (i = 0; i < pdata->rx_q_count; i++) { 17877113afc8SEmmanuel Vadot q_fifo_size = (fifo[i] + 1) * XGMAC_FIFO_UNIT; 17887113afc8SEmmanuel Vadot 17897113afc8SEmmanuel Vadot axgbe_printf(1, "%s: fifo[%d] - 0x%x q_fifo_size 0x%x\n", 17907113afc8SEmmanuel Vadot __func__, i, fifo[i], q_fifo_size); 17917113afc8SEmmanuel Vadot xgbe_queue_flow_control_threshold(pdata, i, q_fifo_size); 17927113afc8SEmmanuel Vadot } 17937113afc8SEmmanuel Vadot } 17947113afc8SEmmanuel Vadot 17957113afc8SEmmanuel Vadot static void 17967113afc8SEmmanuel Vadot xgbe_config_flow_control_threshold(struct xgbe_prv_data *pdata) 17977113afc8SEmmanuel Vadot { 17987113afc8SEmmanuel Vadot unsigned int i; 17997113afc8SEmmanuel Vadot 18007113afc8SEmmanuel Vadot for (i = 0; i < pdata->rx_q_count; i++) { 18017113afc8SEmmanuel Vadot axgbe_printf(1, "%s: queue %d rfa %d rfd %d\n", __func__, i, 18027113afc8SEmmanuel Vadot pdata->rx_rfa[i], pdata->rx_rfd[i]); 18037113afc8SEmmanuel Vadot 18047113afc8SEmmanuel Vadot XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFA, 18057113afc8SEmmanuel Vadot pdata->rx_rfa[i]); 18067113afc8SEmmanuel Vadot XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFD, 18077113afc8SEmmanuel Vadot pdata->rx_rfd[i]); 18087113afc8SEmmanuel Vadot 18097113afc8SEmmanuel Vadot axgbe_printf(1, "%s: MTL_Q_RQFCR 0x%x\n", __func__, 18107113afc8SEmmanuel Vadot XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQFCR)); 18117113afc8SEmmanuel Vadot } 18127113afc8SEmmanuel Vadot } 18137113afc8SEmmanuel Vadot 18147113afc8SEmmanuel Vadot static unsigned int 18157113afc8SEmmanuel Vadot xgbe_get_tx_fifo_size(struct xgbe_prv_data *pdata) 18167113afc8SEmmanuel Vadot { 18177113afc8SEmmanuel Vadot /* The configured value may not be the actual amount of fifo RAM */ 18187113afc8SEmmanuel Vadot return (min_t(unsigned int, pdata->tx_max_fifo_size, 18197113afc8SEmmanuel Vadot pdata->hw_feat.tx_fifo_size)); 18207113afc8SEmmanuel Vadot } 18217113afc8SEmmanuel Vadot 18227113afc8SEmmanuel Vadot static unsigned int 18237113afc8SEmmanuel Vadot xgbe_get_rx_fifo_size(struct xgbe_prv_data *pdata) 18247113afc8SEmmanuel Vadot { 18257113afc8SEmmanuel Vadot /* The configured value may not be the actual amount of fifo RAM */ 18267113afc8SEmmanuel Vadot return (min_t(unsigned int, pdata->rx_max_fifo_size, 18277113afc8SEmmanuel Vadot pdata->hw_feat.rx_fifo_size)); 18287113afc8SEmmanuel Vadot } 18297113afc8SEmmanuel Vadot 18307113afc8SEmmanuel Vadot static void 18317113afc8SEmmanuel Vadot xgbe_calculate_equal_fifo(unsigned int fifo_size, unsigned int queue_count, 18327113afc8SEmmanuel Vadot unsigned int *fifo) 183344b781cfSAndrew Turner { 183444b781cfSAndrew Turner unsigned int q_fifo_size; 183544b781cfSAndrew Turner unsigned int p_fifo; 18367113afc8SEmmanuel Vadot unsigned int i; 183744b781cfSAndrew Turner 18387113afc8SEmmanuel Vadot q_fifo_size = fifo_size / queue_count; 183944b781cfSAndrew Turner 18407113afc8SEmmanuel Vadot /* Calculate the fifo setting by dividing the queue's fifo size 18417113afc8SEmmanuel Vadot * by the fifo allocation increment (with 0 representing the 18427113afc8SEmmanuel Vadot * base allocation increment so decrement the result by 1). 184344b781cfSAndrew Turner */ 18447113afc8SEmmanuel Vadot p_fifo = q_fifo_size / XGMAC_FIFO_UNIT; 184544b781cfSAndrew Turner if (p_fifo) 184644b781cfSAndrew Turner p_fifo--; 184744b781cfSAndrew Turner 18487113afc8SEmmanuel Vadot /* Distribute the fifo equally amongst the queues */ 18497113afc8SEmmanuel Vadot for (i = 0; i < queue_count; i++) 18507113afc8SEmmanuel Vadot fifo[i] = p_fifo; 185144b781cfSAndrew Turner } 185244b781cfSAndrew Turner 18537113afc8SEmmanuel Vadot static unsigned int 18547113afc8SEmmanuel Vadot xgbe_set_nonprio_fifos(unsigned int fifo_size, unsigned int queue_count, 18557113afc8SEmmanuel Vadot unsigned int *fifo) 185644b781cfSAndrew Turner { 185744b781cfSAndrew Turner unsigned int i; 185844b781cfSAndrew Turner 18597113afc8SEmmanuel Vadot MPASS(powerof2(XGMAC_FIFO_MIN_ALLOC)); 186044b781cfSAndrew Turner 18617113afc8SEmmanuel Vadot if (queue_count <= IEEE_8021QAZ_MAX_TCS) 18627113afc8SEmmanuel Vadot return (fifo_size); 18637113afc8SEmmanuel Vadot 18647113afc8SEmmanuel Vadot /* Rx queues 9 and up are for specialized packets, 18657113afc8SEmmanuel Vadot * such as PTP or DCB control packets, etc. and 18667113afc8SEmmanuel Vadot * don't require a large fifo 18677113afc8SEmmanuel Vadot */ 18687113afc8SEmmanuel Vadot for (i = IEEE_8021QAZ_MAX_TCS; i < queue_count; i++) { 18697113afc8SEmmanuel Vadot fifo[i] = (XGMAC_FIFO_MIN_ALLOC / XGMAC_FIFO_UNIT) - 1; 18707113afc8SEmmanuel Vadot fifo_size -= XGMAC_FIFO_MIN_ALLOC; 187144b781cfSAndrew Turner } 187244b781cfSAndrew Turner 18737113afc8SEmmanuel Vadot return (fifo_size); 18747113afc8SEmmanuel Vadot } 18757113afc8SEmmanuel Vadot 18767113afc8SEmmanuel Vadot static void 18777113afc8SEmmanuel Vadot xgbe_config_tx_fifo_size(struct xgbe_prv_data *pdata) 187844b781cfSAndrew Turner { 187944b781cfSAndrew Turner unsigned int fifo_size; 18807113afc8SEmmanuel Vadot unsigned int fifo[XGBE_MAX_QUEUES]; 188144b781cfSAndrew Turner unsigned int i; 188244b781cfSAndrew Turner 18837113afc8SEmmanuel Vadot fifo_size = xgbe_get_tx_fifo_size(pdata); 18847113afc8SEmmanuel Vadot axgbe_printf(1, "%s: fifo_size 0x%x\n", __func__, fifo_size); 188544b781cfSAndrew Turner 18867113afc8SEmmanuel Vadot xgbe_calculate_equal_fifo(fifo_size, pdata->tx_q_count, fifo); 18877113afc8SEmmanuel Vadot 18887113afc8SEmmanuel Vadot for (i = 0; i < pdata->tx_q_count; i++) { 18897113afc8SEmmanuel Vadot XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TQS, fifo[i]); 18907113afc8SEmmanuel Vadot axgbe_printf(1, "Tx q %d FIFO Size 0x%x\n", i, 18917113afc8SEmmanuel Vadot XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TQOMR)); 189244b781cfSAndrew Turner } 189344b781cfSAndrew Turner 18947113afc8SEmmanuel Vadot axgbe_printf(1, "%d Tx hardware queues, %d byte fifo per queue\n", 18957113afc8SEmmanuel Vadot pdata->tx_q_count, ((fifo[0] + 1) * XGMAC_FIFO_UNIT)); 18967113afc8SEmmanuel Vadot } 18977113afc8SEmmanuel Vadot 18987113afc8SEmmanuel Vadot static void 18997113afc8SEmmanuel Vadot xgbe_config_rx_fifo_size(struct xgbe_prv_data *pdata) 19007113afc8SEmmanuel Vadot { 19017113afc8SEmmanuel Vadot unsigned int fifo_size; 19027113afc8SEmmanuel Vadot unsigned int fifo[XGBE_MAX_QUEUES]; 19037113afc8SEmmanuel Vadot unsigned int prio_queues; 19047113afc8SEmmanuel Vadot unsigned int i; 19057113afc8SEmmanuel Vadot 19067113afc8SEmmanuel Vadot /* TODO - add pfc/ets related support */ 19077113afc8SEmmanuel Vadot 19087113afc8SEmmanuel Vadot /* Clear any DCB related fifo/queue information */ 19097113afc8SEmmanuel Vadot fifo_size = xgbe_get_rx_fifo_size(pdata); 19107113afc8SEmmanuel Vadot prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); 19117113afc8SEmmanuel Vadot axgbe_printf(1, "%s: fifo_size 0x%x rx_q_cnt %d prio %d\n", __func__, 19127113afc8SEmmanuel Vadot fifo_size, pdata->rx_q_count, prio_queues); 19137113afc8SEmmanuel Vadot 19147113afc8SEmmanuel Vadot /* Assign a minimum fifo to the non-VLAN priority queues */ 19157113afc8SEmmanuel Vadot fifo_size = xgbe_set_nonprio_fifos(fifo_size, pdata->rx_q_count, fifo); 19167113afc8SEmmanuel Vadot 19177113afc8SEmmanuel Vadot xgbe_calculate_equal_fifo(fifo_size, prio_queues, fifo); 19187113afc8SEmmanuel Vadot 19197113afc8SEmmanuel Vadot for (i = 0; i < pdata->rx_q_count; i++) { 19207113afc8SEmmanuel Vadot XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RQS, fifo[i]); 19217113afc8SEmmanuel Vadot axgbe_printf(1, "Rx q %d FIFO Size 0x%x\n", i, 19227113afc8SEmmanuel Vadot XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQOMR)); 19237113afc8SEmmanuel Vadot } 19247113afc8SEmmanuel Vadot 19257113afc8SEmmanuel Vadot xgbe_calculate_flow_control_threshold(pdata, fifo); 19267113afc8SEmmanuel Vadot xgbe_config_flow_control_threshold(pdata); 19277113afc8SEmmanuel Vadot 19287113afc8SEmmanuel Vadot axgbe_printf(1, "%u Rx hardware queues, %u byte fifo/queue\n", 19297113afc8SEmmanuel Vadot pdata->rx_q_count, ((fifo[0] + 1) * XGMAC_FIFO_UNIT)); 19307113afc8SEmmanuel Vadot } 19317113afc8SEmmanuel Vadot 19327113afc8SEmmanuel Vadot static void 19337113afc8SEmmanuel Vadot xgbe_config_queue_mapping(struct xgbe_prv_data *pdata) 193444b781cfSAndrew Turner { 193544b781cfSAndrew Turner unsigned int qptc, qptc_extra, queue; 193644b781cfSAndrew Turner unsigned int prio_queues; 193744b781cfSAndrew Turner unsigned int ppq, ppq_extra, prio; 193844b781cfSAndrew Turner unsigned int mask; 193944b781cfSAndrew Turner unsigned int i, j, reg, reg_val; 194044b781cfSAndrew Turner 194144b781cfSAndrew Turner /* Map the MTL Tx Queues to Traffic Classes 194244b781cfSAndrew Turner * Note: Tx Queues >= Traffic Classes 194344b781cfSAndrew Turner */ 194444b781cfSAndrew Turner qptc = pdata->tx_q_count / pdata->hw_feat.tc_cnt; 194544b781cfSAndrew Turner qptc_extra = pdata->tx_q_count % pdata->hw_feat.tc_cnt; 194644b781cfSAndrew Turner 194744b781cfSAndrew Turner for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) { 194844b781cfSAndrew Turner for (j = 0; j < qptc; j++) { 19497113afc8SEmmanuel Vadot axgbe_printf(1, "TXq%u mapped to TC%u\n", queue, i); 195044b781cfSAndrew Turner XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, 195144b781cfSAndrew Turner Q2TCMAP, i); 195244b781cfSAndrew Turner pdata->q2tc_map[queue++] = i; 195344b781cfSAndrew Turner } 195444b781cfSAndrew Turner 195544b781cfSAndrew Turner if (i < qptc_extra) { 19567113afc8SEmmanuel Vadot axgbe_printf(1, "TXq%u mapped to TC%u\n", queue, i); 195744b781cfSAndrew Turner XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, 195844b781cfSAndrew Turner Q2TCMAP, i); 195944b781cfSAndrew Turner pdata->q2tc_map[queue++] = i; 196044b781cfSAndrew Turner } 196144b781cfSAndrew Turner } 196244b781cfSAndrew Turner 196344b781cfSAndrew Turner /* Map the 8 VLAN priority values to available MTL Rx queues */ 19647113afc8SEmmanuel Vadot prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); 196544b781cfSAndrew Turner ppq = IEEE_8021QAZ_MAX_TCS / prio_queues; 196644b781cfSAndrew Turner ppq_extra = IEEE_8021QAZ_MAX_TCS % prio_queues; 196744b781cfSAndrew Turner 196844b781cfSAndrew Turner reg = MAC_RQC2R; 196944b781cfSAndrew Turner reg_val = 0; 197044b781cfSAndrew Turner for (i = 0, prio = 0; i < prio_queues;) { 197144b781cfSAndrew Turner mask = 0; 197244b781cfSAndrew Turner for (j = 0; j < ppq; j++) { 19737113afc8SEmmanuel Vadot axgbe_printf(1, "PRIO%u mapped to RXq%u\n", prio, i); 197444b781cfSAndrew Turner mask |= (1 << prio); 197544b781cfSAndrew Turner pdata->prio2q_map[prio++] = i; 197644b781cfSAndrew Turner } 197744b781cfSAndrew Turner 197844b781cfSAndrew Turner if (i < ppq_extra) { 19797113afc8SEmmanuel Vadot axgbe_printf(1, "PRIO%u mapped to RXq%u\n", prio, i); 198044b781cfSAndrew Turner mask |= (1 << prio); 198144b781cfSAndrew Turner pdata->prio2q_map[prio++] = i; 198244b781cfSAndrew Turner } 198344b781cfSAndrew Turner 198444b781cfSAndrew Turner reg_val |= (mask << ((i++ % MAC_RQC2_Q_PER_REG) << 3)); 198544b781cfSAndrew Turner 198644b781cfSAndrew Turner if ((i % MAC_RQC2_Q_PER_REG) && (i != prio_queues)) 198744b781cfSAndrew Turner continue; 198844b781cfSAndrew Turner 198944b781cfSAndrew Turner XGMAC_IOWRITE(pdata, reg, reg_val); 199044b781cfSAndrew Turner reg += MAC_RQC2_INC; 199144b781cfSAndrew Turner reg_val = 0; 199244b781cfSAndrew Turner } 199344b781cfSAndrew Turner 199444b781cfSAndrew Turner /* Select dynamic mapping of MTL Rx queue to DMA Rx channel */ 199544b781cfSAndrew Turner reg = MTL_RQDCM0R; 199644b781cfSAndrew Turner reg_val = 0; 199744b781cfSAndrew Turner for (i = 0; i < pdata->rx_q_count;) { 199844b781cfSAndrew Turner reg_val |= (0x80 << ((i++ % MTL_RQDCM_Q_PER_REG) << 3)); 199944b781cfSAndrew Turner 200044b781cfSAndrew Turner if ((i % MTL_RQDCM_Q_PER_REG) && (i != pdata->rx_q_count)) 200144b781cfSAndrew Turner continue; 200244b781cfSAndrew Turner 200344b781cfSAndrew Turner XGMAC_IOWRITE(pdata, reg, reg_val); 200444b781cfSAndrew Turner 200544b781cfSAndrew Turner reg += MTL_RQDCM_INC; 200644b781cfSAndrew Turner reg_val = 0; 200744b781cfSAndrew Turner } 200844b781cfSAndrew Turner } 200944b781cfSAndrew Turner 20107113afc8SEmmanuel Vadot static void 20117113afc8SEmmanuel Vadot xgbe_config_mac_address(struct xgbe_prv_data *pdata) 201244b781cfSAndrew Turner { 20139c6d6488SAndrew Turner xgbe_set_mac_address(pdata, IF_LLADDR(pdata->netdev)); 20147113afc8SEmmanuel Vadot 20157113afc8SEmmanuel Vadot /* Filtering is done using perfect filtering and hash filtering */ 20167113afc8SEmmanuel Vadot if (pdata->hw_feat.hash_table_size) { 20177113afc8SEmmanuel Vadot XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1); 20187113afc8SEmmanuel Vadot XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1); 20197113afc8SEmmanuel Vadot XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HMC, 1); 20207113afc8SEmmanuel Vadot } 202144b781cfSAndrew Turner } 202244b781cfSAndrew Turner 20237113afc8SEmmanuel Vadot static void 20247113afc8SEmmanuel Vadot xgbe_config_jumbo_enable(struct xgbe_prv_data *pdata) 202544b781cfSAndrew Turner { 202644b781cfSAndrew Turner unsigned int val; 202744b781cfSAndrew Turner 20289c6d6488SAndrew Turner val = (if_getmtu(pdata->netdev) > XGMAC_STD_PACKET_MTU) ? 1 : 0; 202944b781cfSAndrew Turner 203044b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val); 203144b781cfSAndrew Turner } 203244b781cfSAndrew Turner 20337113afc8SEmmanuel Vadot static void 20347113afc8SEmmanuel Vadot xgbe_config_mac_speed(struct xgbe_prv_data *pdata) 203544b781cfSAndrew Turner { 20367113afc8SEmmanuel Vadot xgbe_set_speed(pdata, pdata->phy_speed); 203744b781cfSAndrew Turner } 203844b781cfSAndrew Turner 20397113afc8SEmmanuel Vadot static void 20407113afc8SEmmanuel Vadot xgbe_config_checksum_offload(struct xgbe_prv_data *pdata) 204144b781cfSAndrew Turner { 20427113afc8SEmmanuel Vadot if ((if_getcapenable(pdata->netdev) & IFCAP_RXCSUM)) 204344b781cfSAndrew Turner xgbe_enable_rx_csum(pdata); 204444b781cfSAndrew Turner else 204544b781cfSAndrew Turner xgbe_disable_rx_csum(pdata); 204644b781cfSAndrew Turner } 204744b781cfSAndrew Turner 20487113afc8SEmmanuel Vadot static void 20497113afc8SEmmanuel Vadot xgbe_config_vlan_support(struct xgbe_prv_data *pdata) 205044b781cfSAndrew Turner { 205144b781cfSAndrew Turner /* Indicate that VLAN Tx CTAGs come from context descriptors */ 205244b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0); 205344b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1); 205444b781cfSAndrew Turner 205544b781cfSAndrew Turner /* Set the current VLAN Hash Table register value */ 205644b781cfSAndrew Turner xgbe_update_vlan_hash_table(pdata); 205744b781cfSAndrew Turner 20587113afc8SEmmanuel Vadot if ((if_getcapenable(pdata->netdev) & IFCAP_VLAN_HWFILTER)) { 20597113afc8SEmmanuel Vadot axgbe_printf(1, "Enabling rx vlan filtering\n"); 20607113afc8SEmmanuel Vadot xgbe_enable_rx_vlan_filtering(pdata); 20617113afc8SEmmanuel Vadot } else { 20627113afc8SEmmanuel Vadot axgbe_printf(1, "Disabling rx vlan filtering\n"); 206344b781cfSAndrew Turner xgbe_disable_rx_vlan_filtering(pdata); 206444b781cfSAndrew Turner } 206544b781cfSAndrew Turner 20667113afc8SEmmanuel Vadot if ((if_getcapenable(pdata->netdev) & IFCAP_VLAN_HWTAGGING)) { 20677113afc8SEmmanuel Vadot axgbe_printf(1, "Enabling rx vlan stripping\n"); 20687113afc8SEmmanuel Vadot xgbe_enable_rx_vlan_stripping(pdata); 20697113afc8SEmmanuel Vadot } else { 20707113afc8SEmmanuel Vadot axgbe_printf(1, "Disabling rx vlan stripping\n"); 20717113afc8SEmmanuel Vadot xgbe_disable_rx_vlan_stripping(pdata); 20727113afc8SEmmanuel Vadot } 20737113afc8SEmmanuel Vadot } 20747113afc8SEmmanuel Vadot 20757113afc8SEmmanuel Vadot static uint64_t 20767113afc8SEmmanuel Vadot xgbe_mmc_read(struct xgbe_prv_data *pdata, unsigned int reg_lo) 207744b781cfSAndrew Turner { 207844b781cfSAndrew Turner bool read_hi; 20797113afc8SEmmanuel Vadot uint64_t val; 208044b781cfSAndrew Turner 20817113afc8SEmmanuel Vadot if (pdata->vdata->mmc_64bit) { 20827113afc8SEmmanuel Vadot switch (reg_lo) { 20837113afc8SEmmanuel Vadot /* These registers are always 32 bit */ 20847113afc8SEmmanuel Vadot case MMC_RXRUNTERROR: 20857113afc8SEmmanuel Vadot case MMC_RXJABBERERROR: 20867113afc8SEmmanuel Vadot case MMC_RXUNDERSIZE_G: 20877113afc8SEmmanuel Vadot case MMC_RXOVERSIZE_G: 20887113afc8SEmmanuel Vadot case MMC_RXWATCHDOGERROR: 20897113afc8SEmmanuel Vadot read_hi = false; 20907113afc8SEmmanuel Vadot break; 20917113afc8SEmmanuel Vadot 20927113afc8SEmmanuel Vadot default: 20937113afc8SEmmanuel Vadot read_hi = true; 20947113afc8SEmmanuel Vadot } 20957113afc8SEmmanuel Vadot } else { 209644b781cfSAndrew Turner switch (reg_lo) { 209744b781cfSAndrew Turner /* These registers are always 64 bit */ 209844b781cfSAndrew Turner case MMC_TXOCTETCOUNT_GB_LO: 209944b781cfSAndrew Turner case MMC_TXOCTETCOUNT_G_LO: 210044b781cfSAndrew Turner case MMC_RXOCTETCOUNT_GB_LO: 210144b781cfSAndrew Turner case MMC_RXOCTETCOUNT_G_LO: 210244b781cfSAndrew Turner read_hi = true; 210344b781cfSAndrew Turner break; 210444b781cfSAndrew Turner 210544b781cfSAndrew Turner default: 210644b781cfSAndrew Turner read_hi = false; 210744b781cfSAndrew Turner } 21087113afc8SEmmanuel Vadot } 210944b781cfSAndrew Turner 211044b781cfSAndrew Turner val = XGMAC_IOREAD(pdata, reg_lo); 211144b781cfSAndrew Turner 211244b781cfSAndrew Turner if (read_hi) 21137113afc8SEmmanuel Vadot val |= ((uint64_t)XGMAC_IOREAD(pdata, reg_lo + 4) << 32); 211444b781cfSAndrew Turner 21157113afc8SEmmanuel Vadot return (val); 211644b781cfSAndrew Turner } 211744b781cfSAndrew Turner 21187113afc8SEmmanuel Vadot static void 21197113afc8SEmmanuel Vadot xgbe_tx_mmc_int(struct xgbe_prv_data *pdata) 212044b781cfSAndrew Turner { 212144b781cfSAndrew Turner struct xgbe_mmc_stats *stats = &pdata->mmc_stats; 212244b781cfSAndrew Turner unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_TISR); 212344b781cfSAndrew Turner 212444b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_GB)) 212544b781cfSAndrew Turner stats->txoctetcount_gb += 212644b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO); 212744b781cfSAndrew Turner 212844b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_GB)) 212944b781cfSAndrew Turner stats->txframecount_gb += 213044b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO); 213144b781cfSAndrew Turner 213244b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_G)) 213344b781cfSAndrew Turner stats->txbroadcastframes_g += 213444b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO); 213544b781cfSAndrew Turner 213644b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_G)) 213744b781cfSAndrew Turner stats->txmulticastframes_g += 213844b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO); 213944b781cfSAndrew Turner 214044b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX64OCTETS_GB)) 214144b781cfSAndrew Turner stats->tx64octets_gb += 214244b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO); 214344b781cfSAndrew Turner 214444b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX65TO127OCTETS_GB)) 214544b781cfSAndrew Turner stats->tx65to127octets_gb += 214644b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO); 214744b781cfSAndrew Turner 214844b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX128TO255OCTETS_GB)) 214944b781cfSAndrew Turner stats->tx128to255octets_gb += 215044b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO); 215144b781cfSAndrew Turner 215244b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX256TO511OCTETS_GB)) 215344b781cfSAndrew Turner stats->tx256to511octets_gb += 215444b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO); 215544b781cfSAndrew Turner 215644b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX512TO1023OCTETS_GB)) 215744b781cfSAndrew Turner stats->tx512to1023octets_gb += 215844b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO); 215944b781cfSAndrew Turner 216044b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX1024TOMAXOCTETS_GB)) 216144b781cfSAndrew Turner stats->tx1024tomaxoctets_gb += 216244b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); 216344b781cfSAndrew Turner 216444b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNICASTFRAMES_GB)) 216544b781cfSAndrew Turner stats->txunicastframes_gb += 216644b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO); 216744b781cfSAndrew Turner 216844b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_GB)) 216944b781cfSAndrew Turner stats->txmulticastframes_gb += 217044b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO); 217144b781cfSAndrew Turner 217244b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_GB)) 217344b781cfSAndrew Turner stats->txbroadcastframes_g += 217444b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO); 217544b781cfSAndrew Turner 217644b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNDERFLOWERROR)) 217744b781cfSAndrew Turner stats->txunderflowerror += 217844b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO); 217944b781cfSAndrew Turner 218044b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_G)) 218144b781cfSAndrew Turner stats->txoctetcount_g += 218244b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO); 218344b781cfSAndrew Turner 218444b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_G)) 218544b781cfSAndrew Turner stats->txframecount_g += 218644b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO); 218744b781cfSAndrew Turner 218844b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXPAUSEFRAMES)) 218944b781cfSAndrew Turner stats->txpauseframes += 219044b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO); 219144b781cfSAndrew Turner 219244b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXVLANFRAMES_G)) 219344b781cfSAndrew Turner stats->txvlanframes_g += 219444b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO); 219544b781cfSAndrew Turner } 219644b781cfSAndrew Turner 21977113afc8SEmmanuel Vadot static void 21987113afc8SEmmanuel Vadot xgbe_rx_mmc_int(struct xgbe_prv_data *pdata) 219944b781cfSAndrew Turner { 220044b781cfSAndrew Turner struct xgbe_mmc_stats *stats = &pdata->mmc_stats; 220144b781cfSAndrew Turner unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_RISR); 220244b781cfSAndrew Turner 220344b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFRAMECOUNT_GB)) 220444b781cfSAndrew Turner stats->rxframecount_gb += 220544b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO); 220644b781cfSAndrew Turner 220744b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_GB)) 220844b781cfSAndrew Turner stats->rxoctetcount_gb += 220944b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO); 221044b781cfSAndrew Turner 221144b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_G)) 221244b781cfSAndrew Turner stats->rxoctetcount_g += 221344b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO); 221444b781cfSAndrew Turner 221544b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXBROADCASTFRAMES_G)) 221644b781cfSAndrew Turner stats->rxbroadcastframes_g += 221744b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO); 221844b781cfSAndrew Turner 221944b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXMULTICASTFRAMES_G)) 222044b781cfSAndrew Turner stats->rxmulticastframes_g += 222144b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO); 222244b781cfSAndrew Turner 222344b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXCRCERROR)) 222444b781cfSAndrew Turner stats->rxcrcerror += 222544b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO); 222644b781cfSAndrew Turner 222744b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXRUNTERROR)) 222844b781cfSAndrew Turner stats->rxrunterror += 222944b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXRUNTERROR); 223044b781cfSAndrew Turner 223144b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXJABBERERROR)) 223244b781cfSAndrew Turner stats->rxjabbererror += 223344b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXJABBERERROR); 223444b781cfSAndrew Turner 223544b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNDERSIZE_G)) 223644b781cfSAndrew Turner stats->rxundersize_g += 223744b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G); 223844b781cfSAndrew Turner 223944b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOVERSIZE_G)) 224044b781cfSAndrew Turner stats->rxoversize_g += 224144b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G); 224244b781cfSAndrew Turner 224344b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX64OCTETS_GB)) 224444b781cfSAndrew Turner stats->rx64octets_gb += 224544b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO); 224644b781cfSAndrew Turner 224744b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX65TO127OCTETS_GB)) 224844b781cfSAndrew Turner stats->rx65to127octets_gb += 224944b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO); 225044b781cfSAndrew Turner 225144b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX128TO255OCTETS_GB)) 225244b781cfSAndrew Turner stats->rx128to255octets_gb += 225344b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO); 225444b781cfSAndrew Turner 225544b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX256TO511OCTETS_GB)) 225644b781cfSAndrew Turner stats->rx256to511octets_gb += 225744b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO); 225844b781cfSAndrew Turner 225944b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX512TO1023OCTETS_GB)) 226044b781cfSAndrew Turner stats->rx512to1023octets_gb += 226144b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO); 226244b781cfSAndrew Turner 226344b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX1024TOMAXOCTETS_GB)) 226444b781cfSAndrew Turner stats->rx1024tomaxoctets_gb += 226544b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); 226644b781cfSAndrew Turner 226744b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNICASTFRAMES_G)) 226844b781cfSAndrew Turner stats->rxunicastframes_g += 226944b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO); 227044b781cfSAndrew Turner 227144b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXLENGTHERROR)) 227244b781cfSAndrew Turner stats->rxlengtherror += 227344b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO); 227444b781cfSAndrew Turner 227544b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOUTOFRANGETYPE)) 227644b781cfSAndrew Turner stats->rxoutofrangetype += 227744b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO); 227844b781cfSAndrew Turner 227944b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXPAUSEFRAMES)) 228044b781cfSAndrew Turner stats->rxpauseframes += 228144b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO); 228244b781cfSAndrew Turner 228344b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFIFOOVERFLOW)) 228444b781cfSAndrew Turner stats->rxfifooverflow += 228544b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO); 228644b781cfSAndrew Turner 228744b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXVLANFRAMES_GB)) 228844b781cfSAndrew Turner stats->rxvlanframes_gb += 228944b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO); 229044b781cfSAndrew Turner 229144b781cfSAndrew Turner if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXWATCHDOGERROR)) 229244b781cfSAndrew Turner stats->rxwatchdogerror += 229344b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR); 229444b781cfSAndrew Turner } 229544b781cfSAndrew Turner 22967113afc8SEmmanuel Vadot static void 22977113afc8SEmmanuel Vadot xgbe_read_mmc_stats(struct xgbe_prv_data *pdata) 229844b781cfSAndrew Turner { 229944b781cfSAndrew Turner struct xgbe_mmc_stats *stats = &pdata->mmc_stats; 230044b781cfSAndrew Turner 230144b781cfSAndrew Turner /* Freeze counters */ 230244b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1); 230344b781cfSAndrew Turner 230444b781cfSAndrew Turner stats->txoctetcount_gb += 230544b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO); 230644b781cfSAndrew Turner 230744b781cfSAndrew Turner stats->txframecount_gb += 230844b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO); 230944b781cfSAndrew Turner 231044b781cfSAndrew Turner stats->txbroadcastframes_g += 231144b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO); 231244b781cfSAndrew Turner 231344b781cfSAndrew Turner stats->txmulticastframes_g += 231444b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO); 231544b781cfSAndrew Turner 231644b781cfSAndrew Turner stats->tx64octets_gb += 231744b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO); 231844b781cfSAndrew Turner 231944b781cfSAndrew Turner stats->tx65to127octets_gb += 232044b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO); 232144b781cfSAndrew Turner 232244b781cfSAndrew Turner stats->tx128to255octets_gb += 232344b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO); 232444b781cfSAndrew Turner 232544b781cfSAndrew Turner stats->tx256to511octets_gb += 232644b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO); 232744b781cfSAndrew Turner 232844b781cfSAndrew Turner stats->tx512to1023octets_gb += 232944b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO); 233044b781cfSAndrew Turner 233144b781cfSAndrew Turner stats->tx1024tomaxoctets_gb += 233244b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); 233344b781cfSAndrew Turner 233444b781cfSAndrew Turner stats->txunicastframes_gb += 233544b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO); 233644b781cfSAndrew Turner 233744b781cfSAndrew Turner stats->txmulticastframes_gb += 233844b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO); 233944b781cfSAndrew Turner 23407113afc8SEmmanuel Vadot stats->txbroadcastframes_gb += 234144b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO); 234244b781cfSAndrew Turner 234344b781cfSAndrew Turner stats->txunderflowerror += 234444b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO); 234544b781cfSAndrew Turner 234644b781cfSAndrew Turner stats->txoctetcount_g += 234744b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO); 234844b781cfSAndrew Turner 234944b781cfSAndrew Turner stats->txframecount_g += 235044b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO); 235144b781cfSAndrew Turner 235244b781cfSAndrew Turner stats->txpauseframes += 235344b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO); 235444b781cfSAndrew Turner 235544b781cfSAndrew Turner stats->txvlanframes_g += 235644b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO); 235744b781cfSAndrew Turner 235844b781cfSAndrew Turner stats->rxframecount_gb += 235944b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO); 236044b781cfSAndrew Turner 236144b781cfSAndrew Turner stats->rxoctetcount_gb += 236244b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO); 236344b781cfSAndrew Turner 236444b781cfSAndrew Turner stats->rxoctetcount_g += 236544b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO); 236644b781cfSAndrew Turner 236744b781cfSAndrew Turner stats->rxbroadcastframes_g += 236844b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO); 236944b781cfSAndrew Turner 237044b781cfSAndrew Turner stats->rxmulticastframes_g += 237144b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO); 237244b781cfSAndrew Turner 237344b781cfSAndrew Turner stats->rxcrcerror += 237444b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO); 237544b781cfSAndrew Turner 237644b781cfSAndrew Turner stats->rxrunterror += 237744b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXRUNTERROR); 237844b781cfSAndrew Turner 237944b781cfSAndrew Turner stats->rxjabbererror += 238044b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXJABBERERROR); 238144b781cfSAndrew Turner 238244b781cfSAndrew Turner stats->rxundersize_g += 238344b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G); 238444b781cfSAndrew Turner 238544b781cfSAndrew Turner stats->rxoversize_g += 238644b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G); 238744b781cfSAndrew Turner 238844b781cfSAndrew Turner stats->rx64octets_gb += 238944b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO); 239044b781cfSAndrew Turner 239144b781cfSAndrew Turner stats->rx65to127octets_gb += 239244b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO); 239344b781cfSAndrew Turner 239444b781cfSAndrew Turner stats->rx128to255octets_gb += 239544b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO); 239644b781cfSAndrew Turner 239744b781cfSAndrew Turner stats->rx256to511octets_gb += 239844b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO); 239944b781cfSAndrew Turner 240044b781cfSAndrew Turner stats->rx512to1023octets_gb += 240144b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO); 240244b781cfSAndrew Turner 240344b781cfSAndrew Turner stats->rx1024tomaxoctets_gb += 240444b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); 240544b781cfSAndrew Turner 240644b781cfSAndrew Turner stats->rxunicastframes_g += 240744b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO); 240844b781cfSAndrew Turner 240944b781cfSAndrew Turner stats->rxlengtherror += 241044b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO); 241144b781cfSAndrew Turner 241244b781cfSAndrew Turner stats->rxoutofrangetype += 241344b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO); 241444b781cfSAndrew Turner 241544b781cfSAndrew Turner stats->rxpauseframes += 241644b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO); 241744b781cfSAndrew Turner 241844b781cfSAndrew Turner stats->rxfifooverflow += 241944b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO); 242044b781cfSAndrew Turner 242144b781cfSAndrew Turner stats->rxvlanframes_gb += 242244b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO); 242344b781cfSAndrew Turner 242444b781cfSAndrew Turner stats->rxwatchdogerror += 242544b781cfSAndrew Turner xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR); 242644b781cfSAndrew Turner 242744b781cfSAndrew Turner /* Un-freeze counters */ 242844b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0); 242944b781cfSAndrew Turner } 243044b781cfSAndrew Turner 24317113afc8SEmmanuel Vadot static void 24327113afc8SEmmanuel Vadot xgbe_config_mmc(struct xgbe_prv_data *pdata) 243344b781cfSAndrew Turner { 243444b781cfSAndrew Turner /* Set counters to reset on read */ 243544b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MMC_CR, ROR, 1); 243644b781cfSAndrew Turner 243744b781cfSAndrew Turner /* Reset the counters */ 243844b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MMC_CR, CR, 1); 243944b781cfSAndrew Turner } 244044b781cfSAndrew Turner 24417113afc8SEmmanuel Vadot static void 24427113afc8SEmmanuel Vadot xgbe_txq_prepare_tx_stop(struct xgbe_prv_data *pdata, unsigned int queue) 24437113afc8SEmmanuel Vadot { 24447113afc8SEmmanuel Vadot unsigned int tx_status; 24457113afc8SEmmanuel Vadot unsigned long tx_timeout; 24467113afc8SEmmanuel Vadot 24477113afc8SEmmanuel Vadot /* The Tx engine cannot be stopped if it is actively processing 24487113afc8SEmmanuel Vadot * packets. Wait for the Tx queue to empty the Tx fifo. Don't 24497113afc8SEmmanuel Vadot * wait forever though... 24507113afc8SEmmanuel Vadot */ 24517113afc8SEmmanuel Vadot tx_timeout = ticks + (XGBE_DMA_STOP_TIMEOUT * hz); 24527113afc8SEmmanuel Vadot while (ticks < tx_timeout) { 24537113afc8SEmmanuel Vadot tx_status = XGMAC_MTL_IOREAD(pdata, queue, MTL_Q_TQDR); 24547113afc8SEmmanuel Vadot if ((XGMAC_GET_BITS(tx_status, MTL_Q_TQDR, TRCSTS) != 1) && 24557113afc8SEmmanuel Vadot (XGMAC_GET_BITS(tx_status, MTL_Q_TQDR, TXQSTS) == 0)) 24567113afc8SEmmanuel Vadot break; 24577113afc8SEmmanuel Vadot 24587113afc8SEmmanuel Vadot DELAY(500); 24597113afc8SEmmanuel Vadot } 24607113afc8SEmmanuel Vadot 24617113afc8SEmmanuel Vadot if (ticks >= tx_timeout) 24627113afc8SEmmanuel Vadot axgbe_printf(1, "timed out waiting for Tx queue %u to empty\n", 24637113afc8SEmmanuel Vadot queue); 24647113afc8SEmmanuel Vadot } 24657113afc8SEmmanuel Vadot 24667113afc8SEmmanuel Vadot static void 24677113afc8SEmmanuel Vadot xgbe_prepare_tx_stop(struct xgbe_prv_data *pdata, unsigned int queue) 246844b781cfSAndrew Turner { 246944b781cfSAndrew Turner unsigned int tx_dsr, tx_pos, tx_qidx; 247044b781cfSAndrew Turner unsigned int tx_status; 247144b781cfSAndrew Turner unsigned long tx_timeout; 247244b781cfSAndrew Turner 24737113afc8SEmmanuel Vadot if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) > 0x20) 24747113afc8SEmmanuel Vadot return (xgbe_txq_prepare_tx_stop(pdata, queue)); 24757113afc8SEmmanuel Vadot 247644b781cfSAndrew Turner /* Calculate the status register to read and the position within */ 24777113afc8SEmmanuel Vadot if (queue < DMA_DSRX_FIRST_QUEUE) { 247844b781cfSAndrew Turner tx_dsr = DMA_DSR0; 24797113afc8SEmmanuel Vadot tx_pos = (queue * DMA_DSR_Q_WIDTH) + DMA_DSR0_TPS_START; 248044b781cfSAndrew Turner } else { 24817113afc8SEmmanuel Vadot tx_qidx = queue - DMA_DSRX_FIRST_QUEUE; 248244b781cfSAndrew Turner 248344b781cfSAndrew Turner tx_dsr = DMA_DSR1 + ((tx_qidx / DMA_DSRX_QPR) * DMA_DSRX_INC); 248444b781cfSAndrew Turner tx_pos = ((tx_qidx % DMA_DSRX_QPR) * DMA_DSR_Q_WIDTH) + 248544b781cfSAndrew Turner DMA_DSRX_TPS_START; 248644b781cfSAndrew Turner } 248744b781cfSAndrew Turner 248844b781cfSAndrew Turner /* The Tx engine cannot be stopped if it is actively processing 248944b781cfSAndrew Turner * descriptors. Wait for the Tx engine to enter the stopped or 249044b781cfSAndrew Turner * suspended state. Don't wait forever though... 249144b781cfSAndrew Turner */ 24929c6d6488SAndrew Turner tx_timeout = ticks + (XGBE_DMA_STOP_TIMEOUT * hz); 24939c6d6488SAndrew Turner while (ticks < tx_timeout) { 249444b781cfSAndrew Turner tx_status = XGMAC_IOREAD(pdata, tx_dsr); 249544b781cfSAndrew Turner tx_status = GET_BITS(tx_status, tx_pos, DMA_DSR_TPS_WIDTH); 249644b781cfSAndrew Turner if ((tx_status == DMA_TPS_STOPPED) || 249744b781cfSAndrew Turner (tx_status == DMA_TPS_SUSPENDED)) 249844b781cfSAndrew Turner break; 249944b781cfSAndrew Turner 25009c6d6488SAndrew Turner DELAY(500); 250144b781cfSAndrew Turner } 25027113afc8SEmmanuel Vadot 25037113afc8SEmmanuel Vadot if (ticks >= tx_timeout) 25047113afc8SEmmanuel Vadot axgbe_printf(1, "timed out waiting for Tx DMA channel %u to stop\n", 25057113afc8SEmmanuel Vadot queue); 250644b781cfSAndrew Turner } 250744b781cfSAndrew Turner 25087113afc8SEmmanuel Vadot static void 25097113afc8SEmmanuel Vadot xgbe_enable_tx(struct xgbe_prv_data *pdata) 251044b781cfSAndrew Turner { 251144b781cfSAndrew Turner unsigned int i; 251244b781cfSAndrew Turner 251344b781cfSAndrew Turner /* Enable each Tx DMA channel */ 25147113afc8SEmmanuel Vadot for (i = 0; i < pdata->channel_count; i++) { 25157113afc8SEmmanuel Vadot if (!pdata->channel[i]->tx_ring) 251644b781cfSAndrew Turner break; 251744b781cfSAndrew Turner 25187113afc8SEmmanuel Vadot XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1); 251944b781cfSAndrew Turner } 252044b781cfSAndrew Turner 252144b781cfSAndrew Turner /* Enable each Tx queue */ 252244b781cfSAndrew Turner for (i = 0; i < pdata->tx_q_count; i++) 252344b781cfSAndrew Turner XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 252444b781cfSAndrew Turner MTL_Q_ENABLED); 252544b781cfSAndrew Turner 252644b781cfSAndrew Turner /* Enable MAC Tx */ 252744b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1); 252844b781cfSAndrew Turner } 252944b781cfSAndrew Turner 25307113afc8SEmmanuel Vadot static void 25317113afc8SEmmanuel Vadot xgbe_disable_tx(struct xgbe_prv_data *pdata) 253244b781cfSAndrew Turner { 253344b781cfSAndrew Turner unsigned int i; 253444b781cfSAndrew Turner 253544b781cfSAndrew Turner /* Prepare for Tx DMA channel stop */ 25367113afc8SEmmanuel Vadot for (i = 0; i < pdata->tx_q_count; i++) 25377113afc8SEmmanuel Vadot xgbe_prepare_tx_stop(pdata, i); 253844b781cfSAndrew Turner 253944b781cfSAndrew Turner /* Disable MAC Tx */ 254044b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0); 254144b781cfSAndrew Turner 254244b781cfSAndrew Turner /* Disable each Tx queue */ 254344b781cfSAndrew Turner for (i = 0; i < pdata->tx_q_count; i++) 254444b781cfSAndrew Turner XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 0); 254544b781cfSAndrew Turner 254644b781cfSAndrew Turner /* Disable each Tx DMA channel */ 25477113afc8SEmmanuel Vadot for (i = 0; i < pdata->channel_count; i++) { 25487113afc8SEmmanuel Vadot if (!pdata->channel[i]->tx_ring) 254944b781cfSAndrew Turner break; 255044b781cfSAndrew Turner 25517113afc8SEmmanuel Vadot XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0); 255244b781cfSAndrew Turner } 255344b781cfSAndrew Turner } 255444b781cfSAndrew Turner 25557113afc8SEmmanuel Vadot static void 25567113afc8SEmmanuel Vadot xgbe_prepare_rx_stop(struct xgbe_prv_data *pdata, unsigned int queue) 255744b781cfSAndrew Turner { 255844b781cfSAndrew Turner unsigned int rx_status; 255944b781cfSAndrew Turner unsigned long rx_timeout; 256044b781cfSAndrew Turner 256144b781cfSAndrew Turner /* The Rx engine cannot be stopped if it is actively processing 256244b781cfSAndrew Turner * packets. Wait for the Rx queue to empty the Rx fifo. Don't 256344b781cfSAndrew Turner * wait forever though... 256444b781cfSAndrew Turner */ 25659c6d6488SAndrew Turner rx_timeout = ticks + (XGBE_DMA_STOP_TIMEOUT * hz); 25669c6d6488SAndrew Turner while (ticks < rx_timeout) { 256744b781cfSAndrew Turner rx_status = XGMAC_MTL_IOREAD(pdata, queue, MTL_Q_RQDR); 256844b781cfSAndrew Turner if ((XGMAC_GET_BITS(rx_status, MTL_Q_RQDR, PRXQ) == 0) && 256944b781cfSAndrew Turner (XGMAC_GET_BITS(rx_status, MTL_Q_RQDR, RXQSTS) == 0)) 257044b781cfSAndrew Turner break; 257144b781cfSAndrew Turner 25729c6d6488SAndrew Turner DELAY(500); 257344b781cfSAndrew Turner } 25747113afc8SEmmanuel Vadot 25757113afc8SEmmanuel Vadot if (ticks >= rx_timeout) 25767113afc8SEmmanuel Vadot axgbe_printf(1, "timed out waiting for Rx queue %d to empty\n", 25777113afc8SEmmanuel Vadot queue); 257844b781cfSAndrew Turner } 257944b781cfSAndrew Turner 25807113afc8SEmmanuel Vadot static void 25817113afc8SEmmanuel Vadot xgbe_enable_rx(struct xgbe_prv_data *pdata) 258244b781cfSAndrew Turner { 258344b781cfSAndrew Turner unsigned int reg_val, i; 258444b781cfSAndrew Turner 258544b781cfSAndrew Turner /* Enable each Rx DMA channel */ 25867113afc8SEmmanuel Vadot for (i = 0; i < pdata->channel_count; i++) { 25877113afc8SEmmanuel Vadot if (!pdata->channel[i]->rx_ring) 258844b781cfSAndrew Turner break; 258944b781cfSAndrew Turner 25907113afc8SEmmanuel Vadot XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1); 259144b781cfSAndrew Turner } 259244b781cfSAndrew Turner 259344b781cfSAndrew Turner /* Enable each Rx queue */ 259444b781cfSAndrew Turner reg_val = 0; 259544b781cfSAndrew Turner for (i = 0; i < pdata->rx_q_count; i++) 259644b781cfSAndrew Turner reg_val |= (0x02 << (i << 1)); 259744b781cfSAndrew Turner XGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val); 259844b781cfSAndrew Turner 259944b781cfSAndrew Turner /* Enable MAC Rx */ 260044b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 1); 260144b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1); 260244b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1); 260344b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1); 260444b781cfSAndrew Turner } 260544b781cfSAndrew Turner 26067113afc8SEmmanuel Vadot static void 26077113afc8SEmmanuel Vadot xgbe_disable_rx(struct xgbe_prv_data *pdata) 260844b781cfSAndrew Turner { 260944b781cfSAndrew Turner unsigned int i; 261044b781cfSAndrew Turner 261144b781cfSAndrew Turner /* Disable MAC Rx */ 261244b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0); 261344b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 0); 261444b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 0); 261544b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 0); 261644b781cfSAndrew Turner 261744b781cfSAndrew Turner /* Prepare for Rx DMA channel stop */ 261844b781cfSAndrew Turner for (i = 0; i < pdata->rx_q_count; i++) 261944b781cfSAndrew Turner xgbe_prepare_rx_stop(pdata, i); 262044b781cfSAndrew Turner 262144b781cfSAndrew Turner /* Disable each Rx queue */ 262244b781cfSAndrew Turner XGMAC_IOWRITE(pdata, MAC_RQC0R, 0); 262344b781cfSAndrew Turner 262444b781cfSAndrew Turner /* Disable each Rx DMA channel */ 26257113afc8SEmmanuel Vadot for (i = 0; i < pdata->channel_count; i++) { 26267113afc8SEmmanuel Vadot if (!pdata->channel[i]->rx_ring) 262744b781cfSAndrew Turner break; 262844b781cfSAndrew Turner 26297113afc8SEmmanuel Vadot XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0); 263044b781cfSAndrew Turner } 263144b781cfSAndrew Turner } 263244b781cfSAndrew Turner 26337113afc8SEmmanuel Vadot static void 26347113afc8SEmmanuel Vadot xgbe_powerup_tx(struct xgbe_prv_data *pdata) 263544b781cfSAndrew Turner { 263644b781cfSAndrew Turner unsigned int i; 263744b781cfSAndrew Turner 263844b781cfSAndrew Turner /* Enable each Tx DMA channel */ 26397113afc8SEmmanuel Vadot for (i = 0; i < pdata->channel_count; i++) { 26407113afc8SEmmanuel Vadot if (!pdata->channel[i]->tx_ring) 264144b781cfSAndrew Turner break; 264244b781cfSAndrew Turner 26437113afc8SEmmanuel Vadot XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1); 264444b781cfSAndrew Turner } 264544b781cfSAndrew Turner 264644b781cfSAndrew Turner /* Enable MAC Tx */ 264744b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1); 264844b781cfSAndrew Turner } 264944b781cfSAndrew Turner 26507113afc8SEmmanuel Vadot static void 26517113afc8SEmmanuel Vadot xgbe_powerdown_tx(struct xgbe_prv_data *pdata) 265244b781cfSAndrew Turner { 265344b781cfSAndrew Turner unsigned int i; 265444b781cfSAndrew Turner 265544b781cfSAndrew Turner /* Prepare for Tx DMA channel stop */ 26567113afc8SEmmanuel Vadot for (i = 0; i < pdata->tx_q_count; i++) 26577113afc8SEmmanuel Vadot xgbe_prepare_tx_stop(pdata, i); 265844b781cfSAndrew Turner 265944b781cfSAndrew Turner /* Disable MAC Tx */ 266044b781cfSAndrew Turner XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0); 266144b781cfSAndrew Turner 266244b781cfSAndrew Turner /* Disable each Tx DMA channel */ 26637113afc8SEmmanuel Vadot for (i = 0; i < pdata->channel_count; i++) { 26647113afc8SEmmanuel Vadot if (!pdata->channel[i]->tx_ring) 266544b781cfSAndrew Turner break; 266644b781cfSAndrew Turner 26677113afc8SEmmanuel Vadot XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0); 266844b781cfSAndrew Turner } 266944b781cfSAndrew Turner } 267044b781cfSAndrew Turner 26717113afc8SEmmanuel Vadot static void 26727113afc8SEmmanuel Vadot xgbe_powerup_rx(struct xgbe_prv_data *pdata) 267344b781cfSAndrew Turner { 267444b781cfSAndrew Turner unsigned int i; 267544b781cfSAndrew Turner 267644b781cfSAndrew Turner /* Enable each Rx DMA channel */ 26777113afc8SEmmanuel Vadot for (i = 0; i < pdata->channel_count; i++) { 26787113afc8SEmmanuel Vadot if (!pdata->channel[i]->rx_ring) 267944b781cfSAndrew Turner break; 268044b781cfSAndrew Turner 26817113afc8SEmmanuel Vadot XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1); 268244b781cfSAndrew Turner } 268344b781cfSAndrew Turner } 268444b781cfSAndrew Turner 26857113afc8SEmmanuel Vadot static void 26867113afc8SEmmanuel Vadot xgbe_powerdown_rx(struct xgbe_prv_data *pdata) 268744b781cfSAndrew Turner { 268844b781cfSAndrew Turner unsigned int i; 268944b781cfSAndrew Turner 269044b781cfSAndrew Turner /* Disable each Rx DMA channel */ 26917113afc8SEmmanuel Vadot for (i = 0; i < pdata->channel_count; i++) { 26927113afc8SEmmanuel Vadot if (!pdata->channel[i]->rx_ring) 269344b781cfSAndrew Turner break; 269444b781cfSAndrew Turner 26957113afc8SEmmanuel Vadot XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0); 269644b781cfSAndrew Turner } 269744b781cfSAndrew Turner } 269844b781cfSAndrew Turner 26997113afc8SEmmanuel Vadot static int 27007113afc8SEmmanuel Vadot xgbe_init(struct xgbe_prv_data *pdata) 270144b781cfSAndrew Turner { 270244b781cfSAndrew Turner struct xgbe_desc_if *desc_if = &pdata->desc_if; 270344b781cfSAndrew Turner int ret; 270444b781cfSAndrew Turner 270544b781cfSAndrew Turner /* Flush Tx queues */ 270644b781cfSAndrew Turner ret = xgbe_flush_tx_queues(pdata); 27077113afc8SEmmanuel Vadot if (ret) { 27087113afc8SEmmanuel Vadot axgbe_error("error flushing TX queues\n"); 27097113afc8SEmmanuel Vadot return (ret); 27107113afc8SEmmanuel Vadot } 271144b781cfSAndrew Turner 271244b781cfSAndrew Turner /* 271344b781cfSAndrew Turner * Initialize DMA related features 271444b781cfSAndrew Turner */ 271544b781cfSAndrew Turner xgbe_config_dma_bus(pdata); 271644b781cfSAndrew Turner xgbe_config_dma_cache(pdata); 271744b781cfSAndrew Turner xgbe_config_osp_mode(pdata); 27187113afc8SEmmanuel Vadot xgbe_config_pbl_val(pdata); 271944b781cfSAndrew Turner xgbe_config_rx_coalesce(pdata); 272044b781cfSAndrew Turner xgbe_config_tx_coalesce(pdata); 272144b781cfSAndrew Turner xgbe_config_rx_buffer_size(pdata); 272244b781cfSAndrew Turner xgbe_config_tso_mode(pdata); 272344b781cfSAndrew Turner xgbe_config_sph_mode(pdata); 272444b781cfSAndrew Turner xgbe_config_rss(pdata); 272544b781cfSAndrew Turner desc_if->wrapper_tx_desc_init(pdata); 272644b781cfSAndrew Turner desc_if->wrapper_rx_desc_init(pdata); 272744b781cfSAndrew Turner xgbe_enable_dma_interrupts(pdata); 272844b781cfSAndrew Turner 272944b781cfSAndrew Turner /* 273044b781cfSAndrew Turner * Initialize MTL related features 273144b781cfSAndrew Turner */ 273244b781cfSAndrew Turner xgbe_config_mtl_mode(pdata); 273344b781cfSAndrew Turner xgbe_config_queue_mapping(pdata); 273444b781cfSAndrew Turner xgbe_config_tsf_mode(pdata, pdata->tx_sf_mode); 273544b781cfSAndrew Turner xgbe_config_rsf_mode(pdata, pdata->rx_sf_mode); 273644b781cfSAndrew Turner xgbe_config_tx_threshold(pdata, pdata->tx_threshold); 273744b781cfSAndrew Turner xgbe_config_rx_threshold(pdata, pdata->rx_threshold); 273844b781cfSAndrew Turner xgbe_config_tx_fifo_size(pdata); 273944b781cfSAndrew Turner xgbe_config_rx_fifo_size(pdata); 274044b781cfSAndrew Turner /*TODO: Error Packet and undersized good Packet forwarding enable 274144b781cfSAndrew Turner (FEP and FUP) 274244b781cfSAndrew Turner */ 274344b781cfSAndrew Turner xgbe_enable_mtl_interrupts(pdata); 274444b781cfSAndrew Turner 274544b781cfSAndrew Turner /* 274644b781cfSAndrew Turner * Initialize MAC related features 274744b781cfSAndrew Turner */ 274844b781cfSAndrew Turner xgbe_config_mac_address(pdata); 274944b781cfSAndrew Turner xgbe_config_rx_mode(pdata); 275044b781cfSAndrew Turner xgbe_config_jumbo_enable(pdata); 275144b781cfSAndrew Turner xgbe_config_flow_control(pdata); 275244b781cfSAndrew Turner xgbe_config_mac_speed(pdata); 275344b781cfSAndrew Turner xgbe_config_checksum_offload(pdata); 275444b781cfSAndrew Turner xgbe_config_vlan_support(pdata); 275544b781cfSAndrew Turner xgbe_config_mmc(pdata); 275644b781cfSAndrew Turner xgbe_enable_mac_interrupts(pdata); 275744b781cfSAndrew Turner 27587113afc8SEmmanuel Vadot return (0); 275944b781cfSAndrew Turner } 276044b781cfSAndrew Turner 27617113afc8SEmmanuel Vadot void 27627113afc8SEmmanuel Vadot xgbe_init_function_ptrs_dev(struct xgbe_hw_if *hw_if) 276344b781cfSAndrew Turner { 276444b781cfSAndrew Turner 276544b781cfSAndrew Turner hw_if->tx_complete = xgbe_tx_complete; 276644b781cfSAndrew Turner 276744b781cfSAndrew Turner hw_if->set_mac_address = xgbe_set_mac_address; 276844b781cfSAndrew Turner hw_if->config_rx_mode = xgbe_config_rx_mode; 276944b781cfSAndrew Turner 277044b781cfSAndrew Turner hw_if->enable_rx_csum = xgbe_enable_rx_csum; 277144b781cfSAndrew Turner hw_if->disable_rx_csum = xgbe_disable_rx_csum; 277244b781cfSAndrew Turner 277344b781cfSAndrew Turner hw_if->enable_rx_vlan_stripping = xgbe_enable_rx_vlan_stripping; 277444b781cfSAndrew Turner hw_if->disable_rx_vlan_stripping = xgbe_disable_rx_vlan_stripping; 277544b781cfSAndrew Turner hw_if->enable_rx_vlan_filtering = xgbe_enable_rx_vlan_filtering; 277644b781cfSAndrew Turner hw_if->disable_rx_vlan_filtering = xgbe_disable_rx_vlan_filtering; 277744b781cfSAndrew Turner hw_if->update_vlan_hash_table = xgbe_update_vlan_hash_table; 277844b781cfSAndrew Turner 277944b781cfSAndrew Turner hw_if->read_mmd_regs = xgbe_read_mmd_regs; 278044b781cfSAndrew Turner hw_if->write_mmd_regs = xgbe_write_mmd_regs; 278144b781cfSAndrew Turner 27827113afc8SEmmanuel Vadot hw_if->set_speed = xgbe_set_speed; 27837113afc8SEmmanuel Vadot 27847113afc8SEmmanuel Vadot hw_if->set_ext_mii_mode = xgbe_set_ext_mii_mode; 27857113afc8SEmmanuel Vadot hw_if->read_ext_mii_regs = xgbe_read_ext_mii_regs; 27867113afc8SEmmanuel Vadot hw_if->write_ext_mii_regs = xgbe_write_ext_mii_regs; 27877113afc8SEmmanuel Vadot 27887113afc8SEmmanuel Vadot hw_if->set_gpio = xgbe_set_gpio; 27897113afc8SEmmanuel Vadot hw_if->clr_gpio = xgbe_clr_gpio; 279044b781cfSAndrew Turner 279144b781cfSAndrew Turner hw_if->enable_tx = xgbe_enable_tx; 279244b781cfSAndrew Turner hw_if->disable_tx = xgbe_disable_tx; 279344b781cfSAndrew Turner hw_if->enable_rx = xgbe_enable_rx; 279444b781cfSAndrew Turner hw_if->disable_rx = xgbe_disable_rx; 279544b781cfSAndrew Turner 279644b781cfSAndrew Turner hw_if->powerup_tx = xgbe_powerup_tx; 279744b781cfSAndrew Turner hw_if->powerdown_tx = xgbe_powerdown_tx; 279844b781cfSAndrew Turner hw_if->powerup_rx = xgbe_powerup_rx; 279944b781cfSAndrew Turner hw_if->powerdown_rx = xgbe_powerdown_rx; 280044b781cfSAndrew Turner 280144b781cfSAndrew Turner hw_if->dev_read = xgbe_dev_read; 280244b781cfSAndrew Turner hw_if->enable_int = xgbe_enable_int; 280344b781cfSAndrew Turner hw_if->disable_int = xgbe_disable_int; 280444b781cfSAndrew Turner hw_if->init = xgbe_init; 280544b781cfSAndrew Turner hw_if->exit = xgbe_exit; 280644b781cfSAndrew Turner 280744b781cfSAndrew Turner /* Descriptor related Sequences have to be initialized here */ 280844b781cfSAndrew Turner hw_if->tx_desc_init = xgbe_tx_desc_init; 280944b781cfSAndrew Turner hw_if->rx_desc_init = xgbe_rx_desc_init; 281044b781cfSAndrew Turner hw_if->tx_desc_reset = xgbe_tx_desc_reset; 281144b781cfSAndrew Turner hw_if->is_last_desc = xgbe_is_last_desc; 281244b781cfSAndrew Turner hw_if->is_context_desc = xgbe_is_context_desc; 281344b781cfSAndrew Turner 281444b781cfSAndrew Turner /* For FLOW ctrl */ 281544b781cfSAndrew Turner hw_if->config_tx_flow_control = xgbe_config_tx_flow_control; 281644b781cfSAndrew Turner hw_if->config_rx_flow_control = xgbe_config_rx_flow_control; 281744b781cfSAndrew Turner 281844b781cfSAndrew Turner /* For RX coalescing */ 281944b781cfSAndrew Turner hw_if->config_rx_coalesce = xgbe_config_rx_coalesce; 282044b781cfSAndrew Turner hw_if->config_tx_coalesce = xgbe_config_tx_coalesce; 282144b781cfSAndrew Turner hw_if->usec_to_riwt = xgbe_usec_to_riwt; 282244b781cfSAndrew Turner hw_if->riwt_to_usec = xgbe_riwt_to_usec; 282344b781cfSAndrew Turner 282444b781cfSAndrew Turner /* For RX and TX threshold config */ 282544b781cfSAndrew Turner hw_if->config_rx_threshold = xgbe_config_rx_threshold; 282644b781cfSAndrew Turner hw_if->config_tx_threshold = xgbe_config_tx_threshold; 282744b781cfSAndrew Turner 282844b781cfSAndrew Turner /* For RX and TX Store and Forward Mode config */ 282944b781cfSAndrew Turner hw_if->config_rsf_mode = xgbe_config_rsf_mode; 283044b781cfSAndrew Turner hw_if->config_tsf_mode = xgbe_config_tsf_mode; 283144b781cfSAndrew Turner 283244b781cfSAndrew Turner /* For TX DMA Operating on Second Frame config */ 283344b781cfSAndrew Turner hw_if->config_osp_mode = xgbe_config_osp_mode; 283444b781cfSAndrew Turner 283544b781cfSAndrew Turner /* For MMC statistics support */ 283644b781cfSAndrew Turner hw_if->tx_mmc_int = xgbe_tx_mmc_int; 283744b781cfSAndrew Turner hw_if->rx_mmc_int = xgbe_rx_mmc_int; 283844b781cfSAndrew Turner hw_if->read_mmc_stats = xgbe_read_mmc_stats; 283944b781cfSAndrew Turner 284044b781cfSAndrew Turner /* For Receive Side Scaling */ 28417113afc8SEmmanuel Vadot hw_if->enable_rss = xgbe_enable_rss; 284244b781cfSAndrew Turner hw_if->disable_rss = xgbe_disable_rss; 28437113afc8SEmmanuel Vadot hw_if->set_rss_hash_key = xgbe_set_rss_hash_key; 28447113afc8SEmmanuel Vadot hw_if->set_rss_lookup_table = xgbe_set_rss_lookup_table; 284544b781cfSAndrew Turner } 2846