1 /*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2016 Landon Fuller <landon@landonf.org> 5 * Copyright (c) 2015 Broadcom Corporation 6 * All rights reserved. 7 * 8 * This file is derived from the pcie_core.h and pcie2_core.h headers 9 * from Broadcom's Linux driver sources as distributed by dd-wrt. 10 * 11 * Permission to use, copy, modify, and/or distribute this software for any 12 * purpose with or without fee is hereby granted, provided that the above 13 * copyright notice and this permission notice appear in all copies. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 16 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 17 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 18 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 19 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 20 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 21 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 22 * 23 * $FreeBSD$ 24 */ 25 26 #ifndef _BHND_CORES_PCIE2_BHND_PCIE2_REG_H_ 27 #define _BHND_CORES_PCIE2_BHND_PCIE2_REG_H_ 28 29 /* 30 * PCIe-Gen2 DMA Constants 31 */ 32 33 #define BHND_PCIE2_DMA64_TRANSLATION 0x8000000000000000 /**< PCIe-Gen2 DMA64 address translation */ 34 #define BHND_PCIE2_DMA64_MASK 0xc000000000000000 /**< PCIe-Gen2 DMA64 translation mask */ 35 36 /* 37 * PCIe-Gen2 Core Registers 38 */ 39 40 #define BHND_PCIE2_CLK_CONTROL 0x000 41 42 #define BHND_PCIE2_RC_PM_CONTROL 0x004 43 #define BHND_PCIE2_RC_PM_STATUS 0x008 44 #define BHND_PCIE2_EP_PM_CONTROL 0x00C 45 #define BHND_PCIE2_EP_PM_STATUS 0x010 46 #define BHND_PCIE2_EP_LTR_CONTROL 0x014 47 #define BHND_PCIE2_EP_LTR_STATUS 0x018 48 #define BHND_PCIE2_EP_OBFF_STATUS 0x01C 49 #define BHND_PCIE2_PCIE_ERR_STATUS 0x020 50 #define BHND_PCIE2_RC_AXI_CONFIG 0x100 51 #define BHND_PCIE2_EP_AXI_CONFIG 0x104 52 #define BHND_PCIE2_RXDEBUG_STATUS0 0x108 53 #define BHND_PCIE2_RXDEBUG_CONTROL0 0x10C 54 55 #define BHND_PCIE2_CONFIGINDADDR 0x120 56 #define BHND_PCIE2_CONFIGINDDATA 0x124 57 58 #define BHND_PCIE2_CFG_ADDR 0x1F8 59 #define BHND_PCIE2_CFG_DATA 0x1FC 60 61 #define BHND_PCIE2_SYS_EQ_PAGE 0x200 62 #define BHND_PCIE2_SYS_MSI_PAGE 0x204 63 #define BHND_PCIE2_SYS_MSI_INTREN 0x208 64 #define BHND_PCIE2_SYS_MSI_CTRL0 0x210 65 #define BHND_PCIE2_SYS_MSI_CTRL1 0x214 66 #define BHND_PCIE2_SYS_MSI_CTRL2 0x218 67 #define BHND_PCIE2_SYS_MSI_CTRL3 0x21C 68 #define BHND_PCIE2_SYS_MSI_CTRL4 0x220 69 #define BHND_PCIE2_SYS_MSI_CTRL5 0x224 70 71 #define BHND_PCIE2_SYS_EQ_HEAD0 0x250 72 #define BHND_PCIE2_SYS_EQ_TAIL0 0x254 73 #define BHND_PCIE2_SYS_EQ_HEAD1 0x258 74 #define BHND_PCIE2_SYS_EQ_TAIL1 0x25C 75 #define BHND_PCIE2_SYS_EQ_HEAD2 0x260 76 #define BHND_PCIE2_SYS_EQ_TAIL2 0x264 77 #define BHND_PCIE2_SYS_EQ_HEAD3 0x268 78 #define BHND_PCIE2_SYS_EQ_TAIL3 0x26C 79 #define BHND_PCIE2_SYS_EQ_HEAD4 0x270 80 #define BHND_PCIE2_SYS_EQ_TAIL4 0x274 81 #define BHND_PCIE2_SYS_EQ_HEAD5 0x278 82 #define BHND_PCIE2_SYS_EQ_TAIL5 0x27C 83 84 #define BHND_PCIE2_SYS_RC_INTX_EN 0x330 85 #define BHND_PCIE2_SYS_RC_INTX_CSR 0x334 86 #define BHND_PCIE2_SYS_MSI_REQ 0x340 87 #define BHND_PCIE2_SYS_HOST_INTR_EN 0x344 88 #define BHND_PCIE2_SYS_HOST_INTR_CSR 0x348 89 #define BHND_PCIE2_SYS_HOST_INTR0 0x350 90 #define BHND_PCIE2_SYS_HOST_INTR1 0x354 91 #define BHND_PCIE2_SYS_HOST_INTR2 0x358 92 #define BHND_PCIE2_SYS_HOST_INTR3 0x35C 93 #define BHND_PCIE2_SYS_EP_INT_EN0 0x360 94 #define BHND_PCIE2_SYS_EP_INT_EN1 0x364 95 #define BHND_PCIE2_SYS_EP_INT_CSR0 0x370 96 #define BHND_PCIE2_SYS_EP_INT_CSR1 0x374 97 98 #define BHND_PCIE2_MDIO_CTL 0x128 /**< mdio control */ 99 #define BHND_PCIE2_MDIO_WRDATA 0x12C /**< mdio data write */ 100 #define BHND_PCIE2_MDIO_RDDATA 0x130 /**< mdio data read */ 101 102 /* DMA doorbell registers (>= rev5) */ 103 #define BHND_PCIE2_DB0_HOST2DEV0 0x140 104 #define BHND_PCIE2_DB0_HOST2DEV1 0x144 105 #define BHND_PCIE2_DB0_DEV2HOST0 0x148 106 #define BHND_PCIE2_DB0_DEV2HOST1 0x14C 107 108 #define BHND_PCIE2_DB1_HOST2DEV0 0x150 109 #define BHND_PCIE2_DB1_HOST2DEV1 0x154 110 #define BHND_PCIE2_DB1_DEV2HOST0 0x158 111 #define BHND_PCIE2_DB1_DEV2HOST1 0x15C 112 113 #define BHND_PCIE2_DB2_HOST2DEV0 0x160 114 #define BHND_PCIE2_DB2_HOST2DEV1 0x164 115 #define BHND_PCIE2_DB2_DEV2HOST0 0x168 116 #define BHND_PCIE2_DB2_DEV2HOST1 0x16C 117 118 #define BHND_PCIE2_DB3_HOST2DEV0 0x170 119 #define BHND_PCIE2_DB3_HOST2DEV1 0x174 120 #define BHND_PCIE2_DB3_DEV2HOST0 0x178 121 #define BHND_PCIE2_DB3_DEV2HOST1 0x17C 122 123 #define BHND_PCIE2_DATAINTF 0x180 124 #define BHND_PCIE2_INTRLAZY0_DEV2HOST 0x188 125 #define BHND_PCIE2_INTRLAZY0_HOST2DEV 0x18c 126 #define BHND_PCIE2_INTSTAT0_HOST2DEV 0x190 127 #define BHND_PCIE2_INTMASK0_HOST2DEV 0x194 128 #define BHND_PCIE2_INTSTAT0_DEV2HOST 0x198 129 #define BHND_PCIE2_INTMASK0_DEV2HOST 0x19c 130 #define BHND_PCIE2_LTR_STATE 0x1A0 131 #define BHND_PCIE2_PWR_INT_STATUS 0x1A4 132 #define BHND_PCIE2_PWR_INT_MASK 0x1A8 133 134 /* DMA channel registers */ 135 #define BHND_PCIE2_DMA0_HOST2DEV_TX 0x200 136 #define BHND_PCIE2_DMA0_HOST2DEV_RX 0x220 137 #define BHND_PCIE2_DMA0_DEV2HOST_TX 0x240 138 #define BHND_PCIE2_DMA0_DEV2HOST_RX 0x260 139 140 #define BHND_PCIE2_DMA1_HOST2DEV_TX 0x280 141 #define BHND_PCIE2_DMA1_HOST2DEV_RX 0x2A0 142 #define BHND_PCIE2_DMA1_DEV2HOST_TX 0x2C0 143 #define BHND_PCIE2_DMA1_DEV2HOST_RX 0x2E0 144 145 #define BHND_PCIE2_DMA2_HOST2DEV_TX 0x300 146 #define BHND_PCIE2_DMA2_HOST2DEV_RX 0x320 147 #define BHND_PCIE2_DMA2_DEV2HOST_TX 0x340 148 #define BHND_PCIE2_DMA2_DEV2HOST_RX 0x360 149 150 #define BHND_PCIE2_DMA3_HOST2DEV_TX 0x380 151 #define BHND_PCIE2_DMA3_HOST2DEV_RX 0x3A0 152 #define BHND_PCIE2_DMA3_DEV2HOST_TX 0x3C0 153 #define BHND_PCIE2_DMA3_DEV2HOST_RX 0x3E0 154 155 #define BHND_PCIE2_PCIE_FUNC0_CFG 0x400 /**< PCIe function 0 config space */ 156 #define BHND_PCIE2_PCIE_FUNC1_CFG 0x500 /**< PCIe function 1 config space */ 157 #define BHND_PCIE2_PCIE_FUNC2_CFG 0x600 /**< PCIe function 2 config space */ 158 #define BHND_PCIE2_PCIE_FUNC3_CFG 0x700 /**< PCIe function 3 config space */ 159 #define BHND_PCIE2_SPROM 0x800 /**< SPROM shadow */ 160 161 #define BHND_PCIE2_FUNC0_IMAP0_0 0xC00 162 #define BHND_PCIE2_FUNC0_IMAP0_1 0xC04 163 #define BHND_PCIE2_FUNC0_IMAP0_2 0xC08 164 #define BHND_PCIE2_FUNC0_IMAP0_3 0xC0C 165 #define BHND_PCIE2_FUNC0_IMAP0_4 0xC10 166 #define BHND_PCIE2_FUNC0_IMAP0_5 0xC14 167 #define BHND_PCIE2_FUNC0_IMAP0_6 0xC18 168 #define BHND_PCIE2_FUNC0_IMAP0_7 0xC1C 169 170 #define BHND_PCIE2_FUNC1_IMAP0_0 0xC20 171 #define BHND_PCIE2_FUNC1_IMAP0_1 0xC24 172 #define BHND_PCIE2_FUNC1_IMAP0_2 0xC28 173 #define BHND_PCIE2_FUNC1_IMAP0_3 0xC2C 174 #define BHND_PCIE2_FUNC1_IMAP0_4 0xC30 175 #define BHND_PCIE2_FUNC1_IMAP0_5 0xC34 176 #define BHND_PCIE2_FUNC1_IMAP0_6 0xC38 177 #define BHND_PCIE2_FUNC1_IMAP0_7 0xC3C 178 179 #define BHND_PCIE2_FUNC0_IMAP1 0xC80 180 #define BHND_PCIE2_FUNC1_IMAP1 0xC88 181 #define BHND_PCIE2_FUNC0_IMAP2 0xCC0 182 #define BHND_PCIE2_FUNC1_IMAP2 0xCC8 183 184 #define BHND_PCIE2_IARR0_LOWER 0xD00 185 #define BHND_PCIE2_IARR0_UPPER 0xD04 186 #define BHND_PCIE2_IARR1_LOWER 0xD08 187 #define BHND_PCIE2_IARR1_UPPER 0xD0C 188 #define BHND_PCIE2_IARR2_LOWER 0xD10 189 #define BHND_PCIE2_IARR2_UPPER 0xD14 190 #define BHND_PCIE2_OARR0 0xD20 191 #define BHND_PCIE2_OARR1 0xD28 192 #define BHND_PCIE2_OARR2 0xD30 193 #define BHND_PCIE2_OMAP0_LOWER 0xD40 194 #define BHND_PCIE2_OMAP0_UPPER 0xD44 195 #define BHND_PCIE2_OMAP1_LOWER 0xD48 196 #define BHND_PCIE2_OMAP1_UPPER 0xD4C 197 #define BHND_PCIE2_OMAP2_LOWER 0xD50 198 #define BHND_PCIE2_OMAP2_UPPER 0xD54 199 #define BHND_PCIE2_FUNC1_IARR1_SIZE 0xD58 200 #define BHND_PCIE2_FUNC1_IARR2_SIZE 0xD5C 201 #define BHND_PCIE2_MEM_CONTROL 0xF00 202 #define BHND_PCIE2_MEM_ECC_ERRLOG0 0xF04 203 #define BHND_PCIE2_MEM_ECC_ERRLOG1 0xF08 204 #define BHND_PCIE2_LINK_STATUS 0xF0C 205 #define BHND_PCIE2_STRAP_STATUS 0xF10 206 #define BHND_PCIE2_RESET_STATUS 0xF14 207 #define BHND_PCIE2_RESETEN_IN_LINKDOWN 0xF18 208 #define BHND_PCIE2_MISC_INTR_EN 0xF1C 209 #define BHND_PCIE2_TX_DEBUG_CFG 0xF20 210 #define BHND_PCIE2_MISC_CONFIG 0xF24 211 #define BHND_PCIE2_MISC_STATUS 0xF28 212 #define BHND_PCIE2_INTR_EN 0xF30 213 #define BHND_PCIE2_INTR_CLEAR 0xF34 214 #define BHND_PCIE2_INTR_STATUS 0xF38 215 216 /* BHND_PCIE2_MDIO_CTL */ 217 #define BHND_PCIE2_MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */ 218 #define BHND_PCIE2_MDIOCTL_DIVISOR_VAL 0x2 219 #define BHND_PCIE2_MDIOCTL_REGADDR_SHIFT 8 /* Regaddr shift */ 220 #define BHND_PCIE2_MDIOCTL_REGADDR_MASK 0x00FFFF00 /* Regaddr Mask */ 221 #define BHND_PCIE2_MDIOCTL_DEVADDR_SHIFT 24 /* Physmedia devaddr shift */ 222 #define BHND_PCIE2_MDIOCTL_DEVADDR_MASK 0x0f000000 /* Physmedia devaddr Mask */ 223 #define BHND_PCIE2_MDIOCTL_SLAVE_BYPASS 0x10000000 /* IP slave bypass */ 224 #define BHND_PCIE2_MDIOCTL_READ 0x20000000 /* IP slave bypass */ 225 226 /* BHND_PCIE2_MDIO_DATA */ 227 #define BHND_PCIE2_MDIODATA_DONE 0x80000000 /* rd/wr transaction done */ 228 #define BHND_PCIE2_MDIODATA_MASK 0x7FFFFFFF /* rd/wr transaction data */ 229 #define BHND_PCIE2_MDIODATA_DEVADDR_SHIFT 4 /* Physmedia devaddr shift */ 230 231 /* BHND_PCIE2_DMA[0-4]_HOST2DEV_(TX|RX) per-channel register offsets */ 232 #define BHND_PCIE2_DMA_CTRL 0x0 /**< enable, et al */ 233 #define BHND_PCIE2_DMA_PTR 0x4 /**< last descriptor posted to chip */ 234 #define BHND_PCIE2_DMA_ADDRL 0x8 /**< descriptor ring base address low 32-bits (8K aligned) */ 235 #define BHND_PCIE2_DMA_ADDRH 0xC /**< descriptor ring base address bits 63:32 (8K aligned) */ 236 #define BHND_PCIE2_DMA_STATUS0 0x10 /**< current descriptor, xmt state */ 237 #define BHND_PCIE2_DMA_STATUS1 0x10 /**< active descriptor, xmt error */ 238 239 #endif /* _BHND_CORES_PCIE2_BHND_PCIE2_REG_H_ */ 240