1 /* 2 * Copyright (c) 2007 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Sepherosa Ziehau <sepherosa@gmail.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * 3. Neither the name of The DragonFly Project nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific, prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * $DragonFly: src/sys/dev/netif/bwi/bwirf.c,v 1.9 2008/08/21 12:19:33 swildner Exp $ 35 */ 36 37 #include <sys/cdefs.h> 38 __FBSDID("$FreeBSD$"); 39 40 #include "opt_inet.h" 41 #include "opt_bwi.h" 42 #include "opt_wlan.h" 43 44 #include <sys/param.h> 45 #include <sys/endian.h> 46 #include <sys/kernel.h> 47 #include <sys/bus.h> 48 #include <sys/malloc.h> 49 #include <sys/proc.h> 50 #include <sys/rman.h> 51 #include <sys/socket.h> 52 #include <sys/sockio.h> 53 #include <sys/sysctl.h> 54 #include <sys/systm.h> 55 56 #include <net/if.h> 57 #include <net/if_var.h> 58 #include <net/if_dl.h> 59 #include <net/if_media.h> 60 #include <net/if_types.h> 61 #include <net/if_arp.h> 62 #include <net/ethernet.h> 63 #include <net/if_llc.h> 64 65 #include <net80211/ieee80211_var.h> 66 #include <net80211/ieee80211_radiotap.h> 67 #include <net80211/ieee80211_amrr.h> 68 69 #include <machine/bus.h> 70 71 #include <dev/bwi/bitops.h> 72 #include <dev/bwi/if_bwireg.h> 73 #include <dev/bwi/if_bwivar.h> 74 #include <dev/bwi/bwimac.h> 75 #include <dev/bwi/bwirf.h> 76 #include <dev/bwi/bwiphy.h> 77 78 #define RF_LO_WRITE(mac, lo) bwi_rf_lo_write((mac), (lo)) 79 80 #define BWI_RF_2GHZ_CHAN(chan) \ 81 (ieee80211_ieee2mhz((chan), IEEE80211_CHAN_2GHZ) - 2400) 82 83 #define BWI_DEFAULT_IDLE_TSSI 52 84 85 struct rf_saveregs { 86 uint16_t phy_01; 87 uint16_t phy_03; 88 uint16_t phy_0a; 89 uint16_t phy_15; 90 uint16_t phy_2a; 91 uint16_t phy_30; 92 uint16_t phy_35; 93 uint16_t phy_60; 94 uint16_t phy_429; 95 uint16_t phy_802; 96 uint16_t phy_811; 97 uint16_t phy_812; 98 uint16_t phy_814; 99 uint16_t phy_815; 100 101 uint16_t rf_43; 102 uint16_t rf_52; 103 uint16_t rf_7a; 104 }; 105 106 #define SAVE_RF_REG(mac, regs, n) (regs)->rf_##n = RF_READ((mac), 0x##n) 107 #define RESTORE_RF_REG(mac, regs, n) RF_WRITE((mac), 0x##n, (regs)->rf_##n) 108 109 #define SAVE_PHY_REG(mac, regs, n) (regs)->phy_##n = PHY_READ((mac), 0x##n) 110 #define RESTORE_PHY_REG(mac, regs, n) PHY_WRITE((mac), 0x##n, (regs)->phy_##n) 111 112 static int bwi_rf_calc_txpower(int8_t *, uint8_t, const int16_t[]); 113 static void bwi_rf_work_around(struct bwi_mac *, u_int); 114 static int bwi_rf_gain_max_reached(struct bwi_mac *, int); 115 static uint16_t bwi_rf_calibval(struct bwi_mac *); 116 static uint16_t bwi_rf_get_tp_ctrl2(struct bwi_mac *); 117 118 static void bwi_rf_lo_update_11b(struct bwi_mac *); 119 static uint16_t bwi_rf_lo_measure_11b(struct bwi_mac *); 120 121 static void bwi_rf_lo_update_11g(struct bwi_mac *); 122 static uint32_t bwi_rf_lo_devi_measure(struct bwi_mac *, uint16_t); 123 static void bwi_rf_lo_measure_11g(struct bwi_mac *, 124 const struct bwi_rf_lo *, struct bwi_rf_lo *, uint8_t); 125 static uint8_t _bwi_rf_lo_update_11g(struct bwi_mac *, uint16_t); 126 static void bwi_rf_lo_write(struct bwi_mac *, const struct bwi_rf_lo *); 127 128 static void bwi_rf_set_nrssi_ofs_11g(struct bwi_mac *); 129 static void bwi_rf_calc_nrssi_slope_11b(struct bwi_mac *); 130 static void bwi_rf_calc_nrssi_slope_11g(struct bwi_mac *); 131 static void bwi_rf_set_nrssi_thr_11b(struct bwi_mac *); 132 static void bwi_rf_set_nrssi_thr_11g(struct bwi_mac *); 133 134 static void bwi_rf_init_sw_nrssi_table(struct bwi_mac *); 135 136 static int bwi_rf_calc_rssi_bcm2050(struct bwi_mac *, 137 const struct bwi_rxbuf_hdr *); 138 static int bwi_rf_calc_rssi_bcm2053(struct bwi_mac *, 139 const struct bwi_rxbuf_hdr *); 140 static int bwi_rf_calc_rssi_bcm2060(struct bwi_mac *, 141 const struct bwi_rxbuf_hdr *); 142 static int bwi_rf_calc_noise_bcm2050(struct bwi_mac *); 143 static int bwi_rf_calc_noise_bcm2053(struct bwi_mac *); 144 static int bwi_rf_calc_noise_bcm2060(struct bwi_mac *); 145 146 static void bwi_rf_on_11a(struct bwi_mac *); 147 static void bwi_rf_on_11bg(struct bwi_mac *); 148 149 static void bwi_rf_off_11a(struct bwi_mac *); 150 static void bwi_rf_off_11bg(struct bwi_mac *); 151 static void bwi_rf_off_11g_rev5(struct bwi_mac *); 152 153 static const int8_t bwi_txpower_map_11b[BWI_TSSI_MAX] = 154 { BWI_TXPOWER_MAP_11B }; 155 static const int8_t bwi_txpower_map_11g[BWI_TSSI_MAX] = 156 { BWI_TXPOWER_MAP_11G }; 157 158 static __inline int16_t 159 bwi_nrssi_11g(struct bwi_mac *mac) 160 { 161 int16_t val; 162 163 #define NRSSI_11G_MASK __BITS(13, 8) 164 165 val = (int16_t)__SHIFTOUT(PHY_READ(mac, 0x47f), NRSSI_11G_MASK); 166 if (val >= 32) 167 val -= 64; 168 return val; 169 170 #undef NRSSI_11G_MASK 171 } 172 173 static __inline struct bwi_rf_lo * 174 bwi_get_rf_lo(struct bwi_mac *mac, uint16_t rf_atten, uint16_t bbp_atten) 175 { 176 int n; 177 178 n = rf_atten + (14 * (bbp_atten / 2)); 179 KASSERT(n < BWI_RFLO_MAX, ("n %d", n)); 180 181 return &mac->mac_rf.rf_lo[n]; 182 } 183 184 static __inline int 185 bwi_rf_lo_isused(struct bwi_mac *mac, const struct bwi_rf_lo *lo) 186 { 187 struct bwi_rf *rf = &mac->mac_rf; 188 int idx; 189 190 idx = lo - rf->rf_lo; 191 KASSERT(idx >= 0 && idx < BWI_RFLO_MAX, ("idx %d", idx)); 192 193 return isset(rf->rf_lo_used, idx); 194 } 195 196 void 197 bwi_rf_write(struct bwi_mac *mac, uint16_t ctrl, uint16_t data) 198 { 199 struct bwi_softc *sc = mac->mac_sc; 200 201 CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl); 202 CSR_WRITE_2(sc, BWI_RF_DATA_LO, data); 203 } 204 205 uint16_t 206 bwi_rf_read(struct bwi_mac *mac, uint16_t ctrl) 207 { 208 struct bwi_rf *rf = &mac->mac_rf; 209 struct bwi_softc *sc = mac->mac_sc; 210 211 ctrl |= rf->rf_ctrl_rd; 212 if (rf->rf_ctrl_adj) { 213 /* XXX */ 214 if (ctrl < 0x70) 215 ctrl += 0x80; 216 else if (ctrl < 0x80) 217 ctrl += 0x70; 218 } 219 220 CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl); 221 return CSR_READ_2(sc, BWI_RF_DATA_LO); 222 } 223 224 int 225 bwi_rf_attach(struct bwi_mac *mac) 226 { 227 struct bwi_softc *sc = mac->mac_sc; 228 struct bwi_phy *phy = &mac->mac_phy; 229 struct bwi_rf *rf = &mac->mac_rf; 230 uint16_t type, manu; 231 uint8_t rev; 232 233 /* 234 * Get RF manufacture/type/revision 235 */ 236 if (sc->sc_bbp_id == BWI_BBPID_BCM4317) { 237 /* 238 * Fake a BCM2050 RF 239 */ 240 manu = BWI_RF_MANUFACT_BCM; 241 type = BWI_RF_T_BCM2050; 242 if (sc->sc_bbp_rev == 0) 243 rev = 3; 244 else if (sc->sc_bbp_rev == 1) 245 rev = 4; 246 else 247 rev = 5; 248 } else { 249 uint32_t val; 250 251 CSR_WRITE_2(sc, BWI_RF_CTRL, BWI_RF_CTRL_RFINFO); 252 val = CSR_READ_2(sc, BWI_RF_DATA_HI); 253 val <<= 16; 254 255 CSR_WRITE_2(sc, BWI_RF_CTRL, BWI_RF_CTRL_RFINFO); 256 val |= CSR_READ_2(sc, BWI_RF_DATA_LO); 257 258 manu = __SHIFTOUT(val, BWI_RFINFO_MANUFACT_MASK); 259 type = __SHIFTOUT(val, BWI_RFINFO_TYPE_MASK); 260 rev = __SHIFTOUT(val, BWI_RFINFO_REV_MASK); 261 } 262 device_printf(sc->sc_dev, "RF: manu 0x%03x, type 0x%04x, rev %u\n", 263 manu, type, rev); 264 265 /* 266 * Verify whether the RF is supported 267 */ 268 rf->rf_ctrl_rd = 0; 269 rf->rf_ctrl_adj = 0; 270 switch (phy->phy_mode) { 271 case IEEE80211_MODE_11A: 272 if (manu != BWI_RF_MANUFACT_BCM || 273 type != BWI_RF_T_BCM2060 || 274 rev != 1) { 275 device_printf(sc->sc_dev, "only BCM2060 rev 1 RF " 276 "is supported for 11A PHY\n"); 277 return ENXIO; 278 } 279 rf->rf_ctrl_rd = BWI_RF_CTRL_RD_11A; 280 rf->rf_on = bwi_rf_on_11a; 281 rf->rf_off = bwi_rf_off_11a; 282 rf->rf_calc_rssi = bwi_rf_calc_rssi_bcm2060; 283 rf->rf_calc_noise = bwi_rf_calc_noise_bcm2060; 284 break; 285 case IEEE80211_MODE_11B: 286 if (type == BWI_RF_T_BCM2050) { 287 rf->rf_ctrl_rd = BWI_RF_CTRL_RD_11BG; 288 rf->rf_calc_rssi = bwi_rf_calc_rssi_bcm2050; 289 rf->rf_calc_noise = bwi_rf_calc_noise_bcm2050; 290 } else if (type == BWI_RF_T_BCM2053) { 291 rf->rf_ctrl_adj = 1; 292 rf->rf_calc_rssi = bwi_rf_calc_rssi_bcm2053; 293 rf->rf_calc_noise = bwi_rf_calc_noise_bcm2053; 294 } else { 295 device_printf(sc->sc_dev, "only BCM2050/BCM2053 RF " 296 "is supported for 11B PHY\n"); 297 return ENXIO; 298 } 299 rf->rf_on = bwi_rf_on_11bg; 300 rf->rf_off = bwi_rf_off_11bg; 301 rf->rf_calc_nrssi_slope = bwi_rf_calc_nrssi_slope_11b; 302 rf->rf_set_nrssi_thr = bwi_rf_set_nrssi_thr_11b; 303 if (phy->phy_rev == 6) 304 rf->rf_lo_update = bwi_rf_lo_update_11g; 305 else 306 rf->rf_lo_update = bwi_rf_lo_update_11b; 307 break; 308 case IEEE80211_MODE_11G: 309 if (type != BWI_RF_T_BCM2050) { 310 device_printf(sc->sc_dev, "only BCM2050 RF " 311 "is supported for 11G PHY\n"); 312 return ENXIO; 313 } 314 rf->rf_ctrl_rd = BWI_RF_CTRL_RD_11BG; 315 rf->rf_on = bwi_rf_on_11bg; 316 if (mac->mac_rev >= 5) 317 rf->rf_off = bwi_rf_off_11g_rev5; 318 else 319 rf->rf_off = bwi_rf_off_11bg; 320 rf->rf_calc_nrssi_slope = bwi_rf_calc_nrssi_slope_11g; 321 rf->rf_set_nrssi_thr = bwi_rf_set_nrssi_thr_11g; 322 rf->rf_calc_rssi = bwi_rf_calc_rssi_bcm2050; 323 rf->rf_calc_noise = bwi_rf_calc_noise_bcm2050; 324 rf->rf_lo_update = bwi_rf_lo_update_11g; 325 break; 326 default: 327 device_printf(sc->sc_dev, "unsupported PHY mode\n"); 328 return ENXIO; 329 } 330 331 rf->rf_type = type; 332 rf->rf_rev = rev; 333 rf->rf_manu = manu; 334 rf->rf_curchan = IEEE80211_CHAN_ANY; 335 rf->rf_ant_mode = BWI_ANT_MODE_AUTO; 336 return 0; 337 } 338 339 void 340 bwi_rf_set_chan(struct bwi_mac *mac, u_int chan, int work_around) 341 { 342 struct bwi_softc *sc = mac->mac_sc; 343 344 if (chan == IEEE80211_CHAN_ANY) 345 return; 346 347 MOBJ_WRITE_2(mac, BWI_COMM_MOBJ, BWI_COMM_MOBJ_CHAN, chan); 348 349 /* TODO: 11A */ 350 351 if (work_around) 352 bwi_rf_work_around(mac, chan); 353 354 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan)); 355 356 if (chan == 14) { 357 if (sc->sc_locale == BWI_SPROM_LOCALE_JAPAN) 358 HFLAGS_CLRBITS(mac, BWI_HFLAG_NOT_JAPAN); 359 else 360 HFLAGS_SETBITS(mac, BWI_HFLAG_NOT_JAPAN); 361 CSR_SETBITS_2(sc, BWI_RF_CHAN_EX, (1 << 11)); /* XXX */ 362 } else { 363 CSR_CLRBITS_2(sc, BWI_RF_CHAN_EX, 0x840); /* XXX */ 364 } 365 DELAY(8000); /* DELAY(2000); */ 366 367 mac->mac_rf.rf_curchan = chan; 368 } 369 370 void 371 bwi_rf_get_gains(struct bwi_mac *mac) 372 { 373 #define SAVE_PHY_MAX 15 374 #define SAVE_RF_MAX 3 375 376 static const uint16_t save_rf_regs[SAVE_RF_MAX] = 377 { 0x52, 0x43, 0x7a }; 378 static const uint16_t save_phy_regs[SAVE_PHY_MAX] = { 379 0x0429, 0x0001, 0x0811, 0x0812, 380 0x0814, 0x0815, 0x005a, 0x0059, 381 0x0058, 0x000a, 0x0003, 0x080f, 382 0x0810, 0x002b, 0x0015 383 }; 384 385 struct bwi_softc *sc = mac->mac_sc; 386 struct bwi_phy *phy = &mac->mac_phy; 387 struct bwi_rf *rf = &mac->mac_rf; 388 uint16_t save_phy[SAVE_PHY_MAX]; 389 uint16_t save_rf[SAVE_RF_MAX]; 390 uint16_t trsw; 391 int i, j, loop1_max, loop1, loop2; 392 393 /* 394 * Save PHY/RF registers for later restoration 395 */ 396 for (i = 0; i < SAVE_PHY_MAX; ++i) 397 save_phy[i] = PHY_READ(mac, save_phy_regs[i]); 398 PHY_READ(mac, 0x2d); /* dummy read */ 399 400 for (i = 0; i < SAVE_RF_MAX; ++i) 401 save_rf[i] = RF_READ(mac, save_rf_regs[i]); 402 403 PHY_CLRBITS(mac, 0x429, 0xc000); 404 PHY_SETBITS(mac, 0x1, 0x8000); 405 406 PHY_SETBITS(mac, 0x811, 0x2); 407 PHY_CLRBITS(mac, 0x812, 0x2); 408 PHY_SETBITS(mac, 0x811, 0x1); 409 PHY_CLRBITS(mac, 0x812, 0x1); 410 411 PHY_SETBITS(mac, 0x814, 0x1); 412 PHY_CLRBITS(mac, 0x815, 0x1); 413 PHY_SETBITS(mac, 0x814, 0x2); 414 PHY_CLRBITS(mac, 0x815, 0x2); 415 416 PHY_SETBITS(mac, 0x811, 0xc); 417 PHY_SETBITS(mac, 0x812, 0xc); 418 PHY_SETBITS(mac, 0x811, 0x30); 419 PHY_FILT_SETBITS(mac, 0x812, 0xffcf, 0x10); 420 421 PHY_WRITE(mac, 0x5a, 0x780); 422 PHY_WRITE(mac, 0x59, 0xc810); 423 PHY_WRITE(mac, 0x58, 0xd); 424 PHY_SETBITS(mac, 0xa, 0x2000); 425 426 PHY_SETBITS(mac, 0x814, 0x4); 427 PHY_CLRBITS(mac, 0x815, 0x4); 428 429 PHY_FILT_SETBITS(mac, 0x3, 0xff9f, 0x40); 430 431 if (rf->rf_rev == 8) { 432 loop1_max = 15; 433 RF_WRITE(mac, 0x43, loop1_max); 434 } else { 435 loop1_max = 9; 436 RF_WRITE(mac, 0x52, 0x0); 437 RF_FILT_SETBITS(mac, 0x43, 0xfff0, loop1_max); 438 } 439 440 bwi_phy_set_bbp_atten(mac, 11); 441 442 if (phy->phy_rev >= 3) 443 PHY_WRITE(mac, 0x80f, 0xc020); 444 else 445 PHY_WRITE(mac, 0x80f, 0x8020); 446 PHY_WRITE(mac, 0x810, 0); 447 448 PHY_FILT_SETBITS(mac, 0x2b, 0xffc0, 0x1); 449 PHY_FILT_SETBITS(mac, 0x2b, 0xc0ff, 0x800); 450 PHY_SETBITS(mac, 0x811, 0x100); 451 PHY_CLRBITS(mac, 0x812, 0x3000); 452 453 if ((sc->sc_card_flags & BWI_CARD_F_EXT_LNA) && 454 phy->phy_rev >= 7) { 455 PHY_SETBITS(mac, 0x811, 0x800); 456 PHY_SETBITS(mac, 0x812, 0x8000); 457 } 458 RF_CLRBITS(mac, 0x7a, 0xff08); 459 460 /* 461 * Find out 'loop1/loop2', which will be used to calculate 462 * max loopback gain later 463 */ 464 j = 0; 465 for (i = 0; i < loop1_max; ++i) { 466 for (j = 0; j < 16; ++j) { 467 RF_WRITE(mac, 0x43, i); 468 469 if (bwi_rf_gain_max_reached(mac, j)) 470 goto loop1_exit; 471 } 472 } 473 loop1_exit: 474 loop1 = i; 475 loop2 = j; 476 477 /* 478 * Find out 'trsw', which will be used to calculate 479 * TRSW(TX/RX switch) RX gain later 480 */ 481 if (loop2 >= 8) { 482 PHY_SETBITS(mac, 0x812, 0x30); 483 trsw = 0x1b; 484 for (i = loop2 - 8; i < 16; ++i) { 485 trsw -= 3; 486 if (bwi_rf_gain_max_reached(mac, i)) 487 break; 488 } 489 } else { 490 trsw = 0x18; 491 } 492 493 /* 494 * Restore saved PHY/RF registers 495 */ 496 /* First 4 saved PHY registers need special processing */ 497 for (i = 4; i < SAVE_PHY_MAX; ++i) 498 PHY_WRITE(mac, save_phy_regs[i], save_phy[i]); 499 500 bwi_phy_set_bbp_atten(mac, mac->mac_tpctl.bbp_atten); 501 502 for (i = 0; i < SAVE_RF_MAX; ++i) 503 RF_WRITE(mac, save_rf_regs[i], save_rf[i]); 504 505 PHY_WRITE(mac, save_phy_regs[2], save_phy[2] | 0x3); 506 DELAY(10); 507 PHY_WRITE(mac, save_phy_regs[2], save_phy[2]); 508 PHY_WRITE(mac, save_phy_regs[3], save_phy[3]); 509 PHY_WRITE(mac, save_phy_regs[0], save_phy[0]); 510 PHY_WRITE(mac, save_phy_regs[1], save_phy[1]); 511 512 /* 513 * Calculate gains 514 */ 515 rf->rf_lo_gain = (loop2 * 6) - (loop1 * 4) - 11; 516 rf->rf_rx_gain = trsw * 2; 517 DPRINTF(mac->mac_sc, BWI_DBG_RF | BWI_DBG_INIT, 518 "lo gain: %u, rx gain: %u\n", 519 rf->rf_lo_gain, rf->rf_rx_gain); 520 521 #undef SAVE_RF_MAX 522 #undef SAVE_PHY_MAX 523 } 524 525 void 526 bwi_rf_init(struct bwi_mac *mac) 527 { 528 struct bwi_rf *rf = &mac->mac_rf; 529 530 if (rf->rf_type == BWI_RF_T_BCM2060) { 531 /* TODO: 11A */ 532 } else { 533 if (rf->rf_flags & BWI_RF_F_INITED) 534 RF_WRITE(mac, 0x78, rf->rf_calib); 535 else 536 bwi_rf_init_bcm2050(mac); 537 } 538 } 539 540 static void 541 bwi_rf_off_11a(struct bwi_mac *mac) 542 { 543 RF_WRITE(mac, 0x4, 0xff); 544 RF_WRITE(mac, 0x5, 0xfb); 545 546 PHY_SETBITS(mac, 0x10, 0x8); 547 PHY_SETBITS(mac, 0x11, 0x8); 548 549 PHY_WRITE(mac, 0x15, 0xaa00); 550 } 551 552 static void 553 bwi_rf_off_11bg(struct bwi_mac *mac) 554 { 555 PHY_WRITE(mac, 0x15, 0xaa00); 556 } 557 558 static void 559 bwi_rf_off_11g_rev5(struct bwi_mac *mac) 560 { 561 PHY_SETBITS(mac, 0x811, 0x8c); 562 PHY_CLRBITS(mac, 0x812, 0x8c); 563 } 564 565 static void 566 bwi_rf_work_around(struct bwi_mac *mac, u_int chan) 567 { 568 struct bwi_softc *sc = mac->mac_sc; 569 struct bwi_rf *rf = &mac->mac_rf; 570 571 if (chan == IEEE80211_CHAN_ANY) { 572 device_printf(sc->sc_dev, "%s invalid channel!!\n", __func__); 573 return; 574 } 575 576 if (rf->rf_type != BWI_RF_T_BCM2050 || rf->rf_rev >= 6) 577 return; 578 579 if (chan <= 10) 580 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan + 4)); 581 else 582 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(1)); 583 DELAY(1000); 584 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan)); 585 } 586 587 static __inline struct bwi_rf_lo * 588 bwi_rf_lo_find(struct bwi_mac *mac, const struct bwi_tpctl *tpctl) 589 { 590 uint16_t rf_atten, bbp_atten; 591 int remap_rf_atten; 592 593 remap_rf_atten = 1; 594 if (tpctl == NULL) { 595 bbp_atten = 2; 596 rf_atten = 3; 597 } else { 598 if (tpctl->tp_ctrl1 == 3) 599 remap_rf_atten = 0; 600 601 bbp_atten = tpctl->bbp_atten; 602 rf_atten = tpctl->rf_atten; 603 604 if (bbp_atten > 6) 605 bbp_atten = 6; 606 } 607 608 if (remap_rf_atten) { 609 #define MAP_MAX 10 610 static const uint16_t map[MAP_MAX] = 611 { 11, 10, 11, 12, 13, 12, 13, 12, 13, 12 }; 612 613 #if 0 614 KASSERT(rf_atten < MAP_MAX, ("rf_atten %d", rf_atten)); 615 rf_atten = map[rf_atten]; 616 #else 617 if (rf_atten >= MAP_MAX) { 618 rf_atten = 0; /* XXX */ 619 } else { 620 rf_atten = map[rf_atten]; 621 } 622 #endif 623 #undef MAP_MAX 624 } 625 626 return bwi_get_rf_lo(mac, rf_atten, bbp_atten); 627 } 628 629 void 630 bwi_rf_lo_adjust(struct bwi_mac *mac, const struct bwi_tpctl *tpctl) 631 { 632 const struct bwi_rf_lo *lo; 633 634 lo = bwi_rf_lo_find(mac, tpctl); 635 RF_LO_WRITE(mac, lo); 636 } 637 638 static void 639 bwi_rf_lo_write(struct bwi_mac *mac, const struct bwi_rf_lo *lo) 640 { 641 uint16_t val; 642 643 val = (uint8_t)lo->ctrl_lo; 644 val |= ((uint8_t)lo->ctrl_hi) << 8; 645 646 PHY_WRITE(mac, BWI_PHYR_RF_LO, val); 647 } 648 649 static int 650 bwi_rf_gain_max_reached(struct bwi_mac *mac, int idx) 651 { 652 PHY_FILT_SETBITS(mac, 0x812, 0xf0ff, idx << 8); 653 PHY_FILT_SETBITS(mac, 0x15, 0xfff, 0xa000); 654 PHY_SETBITS(mac, 0x15, 0xf000); 655 656 DELAY(20); 657 658 return (PHY_READ(mac, 0x2d) >= 0xdfc); 659 } 660 661 /* XXX use bitmap array */ 662 static __inline uint16_t 663 bitswap4(uint16_t val) 664 { 665 uint16_t ret; 666 667 ret = (val & 0x8) >> 3; 668 ret |= (val & 0x4) >> 1; 669 ret |= (val & 0x2) << 1; 670 ret |= (val & 0x1) << 3; 671 return ret; 672 } 673 674 static __inline uint16_t 675 bwi_phy812_value(struct bwi_mac *mac, uint16_t lpd) 676 { 677 struct bwi_softc *sc = mac->mac_sc; 678 struct bwi_phy *phy = &mac->mac_phy; 679 struct bwi_rf *rf = &mac->mac_rf; 680 uint16_t lo_gain, ext_lna, loop; 681 682 if ((phy->phy_flags & BWI_PHY_F_LINKED) == 0) 683 return 0; 684 685 lo_gain = rf->rf_lo_gain; 686 if (rf->rf_rev == 8) 687 lo_gain += 0x3e; 688 else 689 lo_gain += 0x26; 690 691 if (lo_gain >= 0x46) { 692 lo_gain -= 0x46; 693 ext_lna = 0x3000; 694 } else if (lo_gain >= 0x3a) { 695 lo_gain -= 0x3a; 696 ext_lna = 0x1000; 697 } else if (lo_gain >= 0x2e) { 698 lo_gain -= 0x2e; 699 ext_lna = 0x2000; 700 } else { 701 lo_gain -= 0x10; 702 ext_lna = 0; 703 } 704 705 for (loop = 0; loop < 16; ++loop) { 706 lo_gain -= (6 * loop); 707 if (lo_gain < 6) 708 break; 709 } 710 711 if (phy->phy_rev >= 7 && (sc->sc_card_flags & BWI_CARD_F_EXT_LNA)) { 712 if (ext_lna) 713 ext_lna |= 0x8000; 714 ext_lna |= (loop << 8); 715 switch (lpd) { 716 case 0x011: 717 return 0x8f92; 718 case 0x001: 719 return (0x8092 | ext_lna); 720 case 0x101: 721 return (0x2092 | ext_lna); 722 case 0x100: 723 return (0x2093 | ext_lna); 724 default: 725 panic("unsupported lpd\n"); 726 } 727 } else { 728 ext_lna |= (loop << 8); 729 switch (lpd) { 730 case 0x011: 731 return 0xf92; 732 case 0x001: 733 case 0x101: 734 return (0x92 | ext_lna); 735 case 0x100: 736 return (0x93 | ext_lna); 737 default: 738 panic("unsupported lpd\n"); 739 } 740 } 741 742 panic("never reached\n"); 743 return 0; 744 } 745 746 void 747 bwi_rf_init_bcm2050(struct bwi_mac *mac) 748 { 749 #define SAVE_RF_MAX 3 750 #define SAVE_PHY_COMM_MAX 4 751 #define SAVE_PHY_11G_MAX 6 752 753 static const uint16_t save_rf_regs[SAVE_RF_MAX] = 754 { 0x0043, 0x0051, 0x0052 }; 755 static const uint16_t save_phy_regs_comm[SAVE_PHY_COMM_MAX] = 756 { 0x0015, 0x005a, 0x0059, 0x0058 }; 757 static const uint16_t save_phy_regs_11g[SAVE_PHY_11G_MAX] = 758 { 0x0811, 0x0812, 0x0814, 0x0815, 0x0429, 0x0802 }; 759 760 uint16_t save_rf[SAVE_RF_MAX]; 761 uint16_t save_phy_comm[SAVE_PHY_COMM_MAX]; 762 uint16_t save_phy_11g[SAVE_PHY_11G_MAX]; 763 uint16_t phyr_35, phyr_30 = 0, rfr_78, phyr_80f = 0, phyr_810 = 0; 764 uint16_t bphy_ctrl = 0, bbp_atten, rf_chan_ex; 765 uint16_t phy812_val; 766 uint16_t calib; 767 uint32_t test_lim, test; 768 struct bwi_softc *sc = mac->mac_sc; 769 struct bwi_phy *phy = &mac->mac_phy; 770 struct bwi_rf *rf = &mac->mac_rf; 771 int i; 772 773 /* 774 * Save registers for later restoring 775 */ 776 for (i = 0; i < SAVE_RF_MAX; ++i) 777 save_rf[i] = RF_READ(mac, save_rf_regs[i]); 778 for (i = 0; i < SAVE_PHY_COMM_MAX; ++i) 779 save_phy_comm[i] = PHY_READ(mac, save_phy_regs_comm[i]); 780 781 if (phy->phy_mode == IEEE80211_MODE_11B) { 782 phyr_30 = PHY_READ(mac, 0x30); 783 bphy_ctrl = CSR_READ_2(sc, BWI_BPHY_CTRL); 784 785 PHY_WRITE(mac, 0x30, 0xff); 786 CSR_WRITE_2(sc, BWI_BPHY_CTRL, 0x3f3f); 787 } else if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) { 788 for (i = 0; i < SAVE_PHY_11G_MAX; ++i) { 789 save_phy_11g[i] = 790 PHY_READ(mac, save_phy_regs_11g[i]); 791 } 792 793 PHY_SETBITS(mac, 0x814, 0x3); 794 PHY_CLRBITS(mac, 0x815, 0x3); 795 PHY_CLRBITS(mac, 0x429, 0x8000); 796 PHY_CLRBITS(mac, 0x802, 0x3); 797 798 phyr_80f = PHY_READ(mac, 0x80f); 799 phyr_810 = PHY_READ(mac, 0x810); 800 801 if (phy->phy_rev >= 3) 802 PHY_WRITE(mac, 0x80f, 0xc020); 803 else 804 PHY_WRITE(mac, 0x80f, 0x8020); 805 PHY_WRITE(mac, 0x810, 0); 806 807 phy812_val = bwi_phy812_value(mac, 0x011); 808 PHY_WRITE(mac, 0x812, phy812_val); 809 if (phy->phy_rev < 7 || 810 (sc->sc_card_flags & BWI_CARD_F_EXT_LNA) == 0) 811 PHY_WRITE(mac, 0x811, 0x1b3); 812 else 813 PHY_WRITE(mac, 0x811, 0x9b3); 814 } 815 CSR_SETBITS_2(sc, BWI_RF_ANTDIV, 0x8000); 816 817 phyr_35 = PHY_READ(mac, 0x35); 818 PHY_CLRBITS(mac, 0x35, 0x80); 819 820 bbp_atten = CSR_READ_2(sc, BWI_BBP_ATTEN); 821 rf_chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX); 822 823 if (phy->phy_version == 0) { 824 CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0x122); 825 } else { 826 if (phy->phy_version >= 2) 827 PHY_FILT_SETBITS(mac, 0x3, 0xffbf, 0x40); 828 CSR_SETBITS_2(sc, BWI_RF_CHAN_EX, 0x2000); 829 } 830 831 calib = bwi_rf_calibval(mac); 832 833 if (phy->phy_mode == IEEE80211_MODE_11B) 834 RF_WRITE(mac, 0x78, 0x26); 835 836 if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) { 837 phy812_val = bwi_phy812_value(mac, 0x011); 838 PHY_WRITE(mac, 0x812, phy812_val); 839 } 840 841 PHY_WRITE(mac, 0x15, 0xbfaf); 842 PHY_WRITE(mac, 0x2b, 0x1403); 843 844 if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) { 845 phy812_val = bwi_phy812_value(mac, 0x001); 846 PHY_WRITE(mac, 0x812, phy812_val); 847 } 848 849 PHY_WRITE(mac, 0x15, 0xbfa0); 850 851 RF_SETBITS(mac, 0x51, 0x4); 852 if (rf->rf_rev == 8) { 853 RF_WRITE(mac, 0x43, 0x1f); 854 } else { 855 RF_WRITE(mac, 0x52, 0); 856 RF_FILT_SETBITS(mac, 0x43, 0xfff0, 0x9); 857 } 858 859 test_lim = 0; 860 PHY_WRITE(mac, 0x58, 0); 861 for (i = 0; i < 16; ++i) { 862 PHY_WRITE(mac, 0x5a, 0x480); 863 PHY_WRITE(mac, 0x59, 0xc810); 864 865 PHY_WRITE(mac, 0x58, 0xd); 866 if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) { 867 phy812_val = bwi_phy812_value(mac, 0x101); 868 PHY_WRITE(mac, 0x812, phy812_val); 869 } 870 PHY_WRITE(mac, 0x15, 0xafb0); 871 DELAY(10); 872 873 if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) { 874 phy812_val = bwi_phy812_value(mac, 0x101); 875 PHY_WRITE(mac, 0x812, phy812_val); 876 } 877 PHY_WRITE(mac, 0x15, 0xefb0); 878 DELAY(10); 879 880 if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) { 881 phy812_val = bwi_phy812_value(mac, 0x100); 882 PHY_WRITE(mac, 0x812, phy812_val); 883 } 884 PHY_WRITE(mac, 0x15, 0xfff0); 885 DELAY(20); 886 887 test_lim += PHY_READ(mac, 0x2d); 888 889 PHY_WRITE(mac, 0x58, 0); 890 if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) { 891 phy812_val = bwi_phy812_value(mac, 0x101); 892 PHY_WRITE(mac, 0x812, phy812_val); 893 } 894 PHY_WRITE(mac, 0x15, 0xafb0); 895 } 896 ++test_lim; 897 test_lim >>= 9; 898 899 DELAY(10); 900 901 test = 0; 902 PHY_WRITE(mac, 0x58, 0); 903 for (i = 0; i < 16; ++i) { 904 int j; 905 906 rfr_78 = (bitswap4(i) << 1) | 0x20; 907 RF_WRITE(mac, 0x78, rfr_78); 908 DELAY(10); 909 910 /* NB: This block is slight different than the above one */ 911 for (j = 0; j < 16; ++j) { 912 PHY_WRITE(mac, 0x5a, 0xd80); 913 PHY_WRITE(mac, 0x59, 0xc810); 914 915 PHY_WRITE(mac, 0x58, 0xd); 916 if ((phy->phy_flags & BWI_PHY_F_LINKED) || 917 phy->phy_rev >= 2) { 918 phy812_val = bwi_phy812_value(mac, 0x101); 919 PHY_WRITE(mac, 0x812, phy812_val); 920 } 921 PHY_WRITE(mac, 0x15, 0xafb0); 922 DELAY(10); 923 924 if ((phy->phy_flags & BWI_PHY_F_LINKED) || 925 phy->phy_rev >= 2) { 926 phy812_val = bwi_phy812_value(mac, 0x101); 927 PHY_WRITE(mac, 0x812, phy812_val); 928 } 929 PHY_WRITE(mac, 0x15, 0xefb0); 930 DELAY(10); 931 932 if ((phy->phy_flags & BWI_PHY_F_LINKED) || 933 phy->phy_rev >= 2) { 934 phy812_val = bwi_phy812_value(mac, 0x100); 935 PHY_WRITE(mac, 0x812, phy812_val); 936 } 937 PHY_WRITE(mac, 0x15, 0xfff0); 938 DELAY(10); 939 940 test += PHY_READ(mac, 0x2d); 941 942 PHY_WRITE(mac, 0x58, 0); 943 if ((phy->phy_flags & BWI_PHY_F_LINKED) || 944 phy->phy_rev >= 2) { 945 phy812_val = bwi_phy812_value(mac, 0x101); 946 PHY_WRITE(mac, 0x812, phy812_val); 947 } 948 PHY_WRITE(mac, 0x15, 0xafb0); 949 } 950 951 ++test; 952 test >>= 8; 953 954 if (test > test_lim) 955 break; 956 } 957 if (i > 15) 958 rf->rf_calib = rfr_78; 959 else 960 rf->rf_calib = calib; 961 if (rf->rf_calib != 0xffff) { 962 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_INIT, 963 "RF calibration value: 0x%04x\n", rf->rf_calib); 964 rf->rf_flags |= BWI_RF_F_INITED; 965 } 966 967 /* 968 * Restore trashes registers 969 */ 970 PHY_WRITE(mac, save_phy_regs_comm[0], save_phy_comm[0]); 971 972 for (i = 0; i < SAVE_RF_MAX; ++i) { 973 int pos = (i + 1) % SAVE_RF_MAX; 974 975 RF_WRITE(mac, save_rf_regs[pos], save_rf[pos]); 976 } 977 for (i = 1; i < SAVE_PHY_COMM_MAX; ++i) 978 PHY_WRITE(mac, save_phy_regs_comm[i], save_phy_comm[i]); 979 980 CSR_WRITE_2(sc, BWI_BBP_ATTEN, bbp_atten); 981 if (phy->phy_version != 0) 982 CSR_WRITE_2(sc, BWI_RF_CHAN_EX, rf_chan_ex); 983 984 PHY_WRITE(mac, 0x35, phyr_35); 985 bwi_rf_work_around(mac, rf->rf_curchan); 986 987 if (phy->phy_mode == IEEE80211_MODE_11B) { 988 PHY_WRITE(mac, 0x30, phyr_30); 989 CSR_WRITE_2(sc, BWI_BPHY_CTRL, bphy_ctrl); 990 } else if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) { 991 /* XXX Spec only says when PHY is linked (gmode) */ 992 CSR_CLRBITS_2(sc, BWI_RF_ANTDIV, 0x8000); 993 994 for (i = 0; i < SAVE_PHY_11G_MAX; ++i) { 995 PHY_WRITE(mac, save_phy_regs_11g[i], 996 save_phy_11g[i]); 997 } 998 999 PHY_WRITE(mac, 0x80f, phyr_80f); 1000 PHY_WRITE(mac, 0x810, phyr_810); 1001 } 1002 1003 #undef SAVE_PHY_11G_MAX 1004 #undef SAVE_PHY_COMM_MAX 1005 #undef SAVE_RF_MAX 1006 } 1007 1008 static uint16_t 1009 bwi_rf_calibval(struct bwi_mac *mac) 1010 { 1011 /* http://bcm-specs.sipsolutions.net/RCCTable */ 1012 static const uint16_t rf_calibvals[] = { 1013 0x2, 0x3, 0x1, 0xf, 0x6, 0x7, 0x5, 0xf, 1014 0xa, 0xb, 0x9, 0xf, 0xe, 0xf, 0xd, 0xf 1015 }; 1016 uint16_t val, calib; 1017 int idx; 1018 1019 val = RF_READ(mac, BWI_RFR_BBP_ATTEN); 1020 idx = __SHIFTOUT(val, BWI_RFR_BBP_ATTEN_CALIB_IDX); 1021 KASSERT(idx < (int)(sizeof(rf_calibvals) / sizeof(rf_calibvals[0])), 1022 ("idx %d", idx)); 1023 1024 calib = rf_calibvals[idx] << 1; 1025 if (val & BWI_RFR_BBP_ATTEN_CALIB_BIT) 1026 calib |= 0x1; 1027 calib |= 0x20; 1028 1029 return calib; 1030 } 1031 1032 static __inline int32_t 1033 _bwi_adjust_devide(int32_t num, int32_t den) 1034 { 1035 if (num < 0) 1036 return (num / den); 1037 else 1038 return (num + den / 2) / den; 1039 } 1040 1041 /* 1042 * http://bcm-specs.sipsolutions.net/TSSI_to_DBM_Table 1043 * "calculating table entries" 1044 */ 1045 static int 1046 bwi_rf_calc_txpower(int8_t *txpwr, uint8_t idx, const int16_t pa_params[]) 1047 { 1048 int32_t m1, m2, f, dbm; 1049 int i; 1050 1051 m1 = _bwi_adjust_devide(16 * pa_params[0] + idx * pa_params[1], 32); 1052 m2 = imax(_bwi_adjust_devide(32768 + idx * pa_params[2], 256), 1); 1053 1054 #define ITER_MAX 16 1055 1056 f = 256; 1057 for (i = 0; i < ITER_MAX; ++i) { 1058 int32_t q, d; 1059 1060 q = _bwi_adjust_devide( 1061 f * 4096 - _bwi_adjust_devide(m2 * f, 16) * f, 2048); 1062 d = abs(q - f); 1063 f = q; 1064 1065 if (d < 2) 1066 break; 1067 } 1068 if (i == ITER_MAX) 1069 return EINVAL; 1070 1071 #undef ITER_MAX 1072 1073 dbm = _bwi_adjust_devide(m1 * f, 8192); 1074 if (dbm < -127) 1075 dbm = -127; 1076 else if (dbm > 128) 1077 dbm = 128; 1078 1079 *txpwr = dbm; 1080 return 0; 1081 } 1082 1083 int 1084 bwi_rf_map_txpower(struct bwi_mac *mac) 1085 { 1086 struct bwi_softc *sc = mac->mac_sc; 1087 struct bwi_rf *rf = &mac->mac_rf; 1088 struct bwi_phy *phy = &mac->mac_phy; 1089 uint16_t sprom_ofs, val, mask; 1090 int16_t pa_params[3]; 1091 int error = 0, i, ant_gain, reg_txpower_max; 1092 1093 /* 1094 * Find out max TX power 1095 */ 1096 val = bwi_read_sprom(sc, BWI_SPROM_MAX_TXPWR); 1097 if (phy->phy_mode == IEEE80211_MODE_11A) { 1098 rf->rf_txpower_max = __SHIFTOUT(val, 1099 BWI_SPROM_MAX_TXPWR_MASK_11A); 1100 } else { 1101 rf->rf_txpower_max = __SHIFTOUT(val, 1102 BWI_SPROM_MAX_TXPWR_MASK_11BG); 1103 1104 if ((sc->sc_card_flags & BWI_CARD_F_PA_GPIO9) && 1105 phy->phy_mode == IEEE80211_MODE_11G) 1106 rf->rf_txpower_max -= 3; 1107 } 1108 if (rf->rf_txpower_max <= 0) { 1109 device_printf(sc->sc_dev, "invalid max txpower in sprom\n"); 1110 rf->rf_txpower_max = 74; 1111 } 1112 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH, 1113 "max txpower from sprom: %d dBm\n", rf->rf_txpower_max); 1114 1115 /* 1116 * Find out region/domain max TX power, which is adjusted 1117 * by antenna gain and 1.5 dBm fluctuation as mentioned 1118 * in v3 spec. 1119 */ 1120 val = bwi_read_sprom(sc, BWI_SPROM_ANT_GAIN); 1121 if (phy->phy_mode == IEEE80211_MODE_11A) 1122 ant_gain = __SHIFTOUT(val, BWI_SPROM_ANT_GAIN_MASK_11A); 1123 else 1124 ant_gain = __SHIFTOUT(val, BWI_SPROM_ANT_GAIN_MASK_11BG); 1125 if (ant_gain == 0xff) { 1126 device_printf(sc->sc_dev, "invalid antenna gain in sprom\n"); 1127 ant_gain = 2; 1128 } 1129 ant_gain *= 4; 1130 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH, 1131 "ant gain %d dBm\n", ant_gain); 1132 1133 reg_txpower_max = 90 - ant_gain - 6; /* XXX magic number */ 1134 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH, 1135 "region/domain max txpower %d dBm\n", reg_txpower_max); 1136 1137 /* 1138 * Force max TX power within region/domain TX power limit 1139 */ 1140 if (rf->rf_txpower_max > reg_txpower_max) 1141 rf->rf_txpower_max = reg_txpower_max; 1142 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH, 1143 "max txpower %d dBm\n", rf->rf_txpower_max); 1144 1145 /* 1146 * Create TSSI to TX power mapping 1147 */ 1148 1149 if (sc->sc_bbp_id == BWI_BBPID_BCM4301 && 1150 rf->rf_type != BWI_RF_T_BCM2050) { 1151 rf->rf_idle_tssi0 = BWI_DEFAULT_IDLE_TSSI; 1152 bcopy(bwi_txpower_map_11b, rf->rf_txpower_map0, 1153 sizeof(rf->rf_txpower_map0)); 1154 goto back; 1155 } 1156 1157 #define IS_VALID_PA_PARAM(p) ((p) != 0 && (p) != -1) 1158 1159 /* 1160 * Extract PA parameters 1161 */ 1162 if (phy->phy_mode == IEEE80211_MODE_11A) 1163 sprom_ofs = BWI_SPROM_PA_PARAM_11A; 1164 else 1165 sprom_ofs = BWI_SPROM_PA_PARAM_11BG; 1166 for (i = 0; i < nitems(pa_params); ++i) 1167 pa_params[i] = (int16_t)bwi_read_sprom(sc, sprom_ofs + (i * 2)); 1168 1169 for (i = 0; i < nitems(pa_params); ++i) { 1170 /* 1171 * If one of the PA parameters from SPROM is not valid, 1172 * fall back to the default values, if there are any. 1173 */ 1174 if (!IS_VALID_PA_PARAM(pa_params[i])) { 1175 const int8_t *txpower_map; 1176 1177 if (phy->phy_mode == IEEE80211_MODE_11A) { 1178 device_printf(sc->sc_dev, 1179 "no tssi2dbm table for 11a PHY\n"); 1180 return ENXIO; 1181 } 1182 1183 if (phy->phy_mode == IEEE80211_MODE_11G) { 1184 DPRINTF(sc, 1185 BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH, 1186 "%s\n", "use default 11g TSSI map"); 1187 txpower_map = bwi_txpower_map_11g; 1188 } else { 1189 DPRINTF(sc, 1190 BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH, 1191 "%s\n", "use default 11b TSSI map"); 1192 txpower_map = bwi_txpower_map_11b; 1193 } 1194 1195 rf->rf_idle_tssi0 = BWI_DEFAULT_IDLE_TSSI; 1196 bcopy(txpower_map, rf->rf_txpower_map0, 1197 sizeof(rf->rf_txpower_map0)); 1198 goto back; 1199 } 1200 } 1201 1202 /* 1203 * All of the PA parameters from SPROM are valid. 1204 */ 1205 1206 /* 1207 * Extract idle TSSI from SPROM. 1208 */ 1209 val = bwi_read_sprom(sc, BWI_SPROM_IDLE_TSSI); 1210 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH, 1211 "sprom idle tssi: 0x%04x\n", val); 1212 1213 if (phy->phy_mode == IEEE80211_MODE_11A) 1214 mask = BWI_SPROM_IDLE_TSSI_MASK_11A; 1215 else 1216 mask = BWI_SPROM_IDLE_TSSI_MASK_11BG; 1217 1218 rf->rf_idle_tssi0 = (int)__SHIFTOUT(val, mask); 1219 if (!IS_VALID_PA_PARAM(rf->rf_idle_tssi0)) 1220 rf->rf_idle_tssi0 = 62; 1221 1222 #undef IS_VALID_PA_PARAM 1223 1224 /* 1225 * Calculate TX power map, which is indexed by TSSI 1226 */ 1227 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_ATTACH | BWI_DBG_TXPOWER, 1228 "%s\n", "TSSI-TX power map:"); 1229 for (i = 0; i < BWI_TSSI_MAX; ++i) { 1230 error = bwi_rf_calc_txpower(&rf->rf_txpower_map0[i], i, 1231 pa_params); 1232 if (error) { 1233 device_printf(sc->sc_dev, 1234 "bwi_rf_calc_txpower failed\n"); 1235 break; 1236 } 1237 1238 #ifdef BWI_DEBUG 1239 if (i != 0 && i % 8 == 0) { 1240 _DPRINTF(sc, 1241 BWI_DBG_RF | BWI_DBG_ATTACH | BWI_DBG_TXPOWER, 1242 "%s\n", ""); 1243 } 1244 #endif 1245 _DPRINTF(sc, BWI_DBG_RF | BWI_DBG_ATTACH | BWI_DBG_TXPOWER, 1246 "%d ", rf->rf_txpower_map0[i]); 1247 } 1248 _DPRINTF(sc, BWI_DBG_RF | BWI_DBG_ATTACH | BWI_DBG_TXPOWER, 1249 "%s\n", ""); 1250 back: 1251 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH, 1252 "idle tssi0: %d\n", rf->rf_idle_tssi0); 1253 return error; 1254 } 1255 1256 static void 1257 bwi_rf_lo_update_11g(struct bwi_mac *mac) 1258 { 1259 struct bwi_softc *sc = mac->mac_sc; 1260 struct bwi_rf *rf = &mac->mac_rf; 1261 struct bwi_phy *phy = &mac->mac_phy; 1262 struct bwi_tpctl *tpctl = &mac->mac_tpctl; 1263 struct rf_saveregs regs; 1264 uint16_t ant_div, chan_ex; 1265 uint8_t devi_ctrl; 1266 u_int orig_chan; 1267 1268 /* 1269 * Save RF/PHY registers for later restoration 1270 */ 1271 orig_chan = rf->rf_curchan; 1272 bzero(®s, sizeof(regs)); 1273 1274 if (phy->phy_flags & BWI_PHY_F_LINKED) { 1275 SAVE_PHY_REG(mac, ®s, 429); 1276 SAVE_PHY_REG(mac, ®s, 802); 1277 1278 PHY_WRITE(mac, 0x429, regs.phy_429 & 0x7fff); 1279 PHY_WRITE(mac, 0x802, regs.phy_802 & 0xfffc); 1280 } 1281 1282 ant_div = CSR_READ_2(sc, BWI_RF_ANTDIV); 1283 CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div | 0x8000); 1284 chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX); 1285 1286 SAVE_PHY_REG(mac, ®s, 15); 1287 SAVE_PHY_REG(mac, ®s, 2a); 1288 SAVE_PHY_REG(mac, ®s, 35); 1289 SAVE_PHY_REG(mac, ®s, 60); 1290 SAVE_RF_REG(mac, ®s, 43); 1291 SAVE_RF_REG(mac, ®s, 7a); 1292 SAVE_RF_REG(mac, ®s, 52); 1293 if (phy->phy_flags & BWI_PHY_F_LINKED) { 1294 SAVE_PHY_REG(mac, ®s, 811); 1295 SAVE_PHY_REG(mac, ®s, 812); 1296 SAVE_PHY_REG(mac, ®s, 814); 1297 SAVE_PHY_REG(mac, ®s, 815); 1298 } 1299 1300 /* Force to channel 6 */ 1301 bwi_rf_set_chan(mac, 6, 0); 1302 1303 if (phy->phy_flags & BWI_PHY_F_LINKED) { 1304 PHY_WRITE(mac, 0x429, regs.phy_429 & 0x7fff); 1305 PHY_WRITE(mac, 0x802, regs.phy_802 & 0xfffc); 1306 bwi_mac_dummy_xmit(mac); 1307 } 1308 RF_WRITE(mac, 0x43, 0x6); 1309 1310 bwi_phy_set_bbp_atten(mac, 2); 1311 1312 CSR_WRITE_2(sc, BWI_RF_CHAN_EX, 0); 1313 1314 PHY_WRITE(mac, 0x2e, 0x7f); 1315 PHY_WRITE(mac, 0x80f, 0x78); 1316 PHY_WRITE(mac, 0x35, regs.phy_35 & 0xff7f); 1317 RF_WRITE(mac, 0x7a, regs.rf_7a & 0xfff0); 1318 PHY_WRITE(mac, 0x2b, 0x203); 1319 PHY_WRITE(mac, 0x2a, 0x8a3); 1320 1321 if (phy->phy_flags & BWI_PHY_F_LINKED) { 1322 PHY_WRITE(mac, 0x814, regs.phy_814 | 0x3); 1323 PHY_WRITE(mac, 0x815, regs.phy_815 & 0xfffc); 1324 PHY_WRITE(mac, 0x811, 0x1b3); 1325 PHY_WRITE(mac, 0x812, 0xb2); 1326 } 1327 1328 if ((sc->sc_flags & BWI_F_RUNNING) == 0) 1329 tpctl->tp_ctrl2 = bwi_rf_get_tp_ctrl2(mac); 1330 PHY_WRITE(mac, 0x80f, 0x8078); 1331 1332 /* 1333 * Measure all RF LO 1334 */ 1335 devi_ctrl = _bwi_rf_lo_update_11g(mac, regs.rf_7a); 1336 1337 /* 1338 * Restore saved RF/PHY registers 1339 */ 1340 if (phy->phy_flags & BWI_PHY_F_LINKED) { 1341 PHY_WRITE(mac, 0x15, 0xe300); 1342 PHY_WRITE(mac, 0x812, (devi_ctrl << 8) | 0xa0); 1343 DELAY(5); 1344 PHY_WRITE(mac, 0x812, (devi_ctrl << 8) | 0xa2); 1345 DELAY(2); 1346 PHY_WRITE(mac, 0x812, (devi_ctrl << 8) | 0xa3); 1347 } else { 1348 PHY_WRITE(mac, 0x15, devi_ctrl | 0xefa0); 1349 } 1350 1351 if ((sc->sc_flags & BWI_F_RUNNING) == 0) 1352 tpctl = NULL; 1353 bwi_rf_lo_adjust(mac, tpctl); 1354 1355 PHY_WRITE(mac, 0x2e, 0x807f); 1356 if (phy->phy_flags & BWI_PHY_F_LINKED) 1357 PHY_WRITE(mac, 0x2f, 0x202); 1358 else 1359 PHY_WRITE(mac, 0x2f, 0x101); 1360 1361 CSR_WRITE_2(sc, BWI_RF_CHAN_EX, chan_ex); 1362 1363 RESTORE_PHY_REG(mac, ®s, 15); 1364 RESTORE_PHY_REG(mac, ®s, 2a); 1365 RESTORE_PHY_REG(mac, ®s, 35); 1366 RESTORE_PHY_REG(mac, ®s, 60); 1367 1368 RESTORE_RF_REG(mac, ®s, 43); 1369 RESTORE_RF_REG(mac, ®s, 7a); 1370 1371 regs.rf_52 &= 0xf0; 1372 regs.rf_52 |= (RF_READ(mac, 0x52) & 0xf); 1373 RF_WRITE(mac, 0x52, regs.rf_52); 1374 1375 CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div); 1376 1377 if (phy->phy_flags & BWI_PHY_F_LINKED) { 1378 RESTORE_PHY_REG(mac, ®s, 811); 1379 RESTORE_PHY_REG(mac, ®s, 812); 1380 RESTORE_PHY_REG(mac, ®s, 814); 1381 RESTORE_PHY_REG(mac, ®s, 815); 1382 RESTORE_PHY_REG(mac, ®s, 429); 1383 RESTORE_PHY_REG(mac, ®s, 802); 1384 } 1385 1386 bwi_rf_set_chan(mac, orig_chan, 1); 1387 } 1388 1389 static uint32_t 1390 bwi_rf_lo_devi_measure(struct bwi_mac *mac, uint16_t ctrl) 1391 { 1392 struct bwi_phy *phy = &mac->mac_phy; 1393 uint32_t devi = 0; 1394 int i; 1395 1396 if (phy->phy_flags & BWI_PHY_F_LINKED) 1397 ctrl <<= 8; 1398 1399 for (i = 0; i < 8; ++i) { 1400 if (phy->phy_flags & BWI_PHY_F_LINKED) { 1401 PHY_WRITE(mac, 0x15, 0xe300); 1402 PHY_WRITE(mac, 0x812, ctrl | 0xb0); 1403 DELAY(5); 1404 PHY_WRITE(mac, 0x812, ctrl | 0xb2); 1405 DELAY(2); 1406 PHY_WRITE(mac, 0x812, ctrl | 0xb3); 1407 DELAY(4); 1408 PHY_WRITE(mac, 0x15, 0xf300); 1409 } else { 1410 PHY_WRITE(mac, 0x15, ctrl | 0xefa0); 1411 DELAY(2); 1412 PHY_WRITE(mac, 0x15, ctrl | 0xefe0); 1413 DELAY(4); 1414 PHY_WRITE(mac, 0x15, ctrl | 0xffe0); 1415 } 1416 DELAY(8); 1417 devi += PHY_READ(mac, 0x2d); 1418 } 1419 return devi; 1420 } 1421 1422 static uint16_t 1423 bwi_rf_get_tp_ctrl2(struct bwi_mac *mac) 1424 { 1425 uint32_t devi_min; 1426 uint16_t tp_ctrl2 = 0; 1427 int i; 1428 1429 RF_WRITE(mac, 0x52, 0); 1430 DELAY(10); 1431 devi_min = bwi_rf_lo_devi_measure(mac, 0); 1432 1433 for (i = 0; i < 16; ++i) { 1434 uint32_t devi; 1435 1436 RF_WRITE(mac, 0x52, i); 1437 DELAY(10); 1438 devi = bwi_rf_lo_devi_measure(mac, 0); 1439 1440 if (devi < devi_min) { 1441 devi_min = devi; 1442 tp_ctrl2 = i; 1443 } 1444 } 1445 return tp_ctrl2; 1446 } 1447 1448 static uint8_t 1449 _bwi_rf_lo_update_11g(struct bwi_mac *mac, uint16_t orig_rf7a) 1450 { 1451 #define RF_ATTEN_LISTSZ 14 1452 #define BBP_ATTEN_MAX 4 /* half */ 1453 1454 static const int rf_atten_list[RF_ATTEN_LISTSZ] = 1455 { 3, 1, 5, 7, 9, 2, 0, 4, 6, 8, 1, 2, 3, 4 }; 1456 static const int rf_atten_init_list[RF_ATTEN_LISTSZ] = 1457 { 0, 3, 1, 5, 7, 3, 2, 0, 4, 6, -1, -1, -1, -1 }; 1458 static const int rf_lo_measure_order[RF_ATTEN_LISTSZ] = 1459 { 3, 1, 5, 7, 9, 2, 0, 4, 6, 8, 10, 11, 12, 13 }; 1460 1461 struct bwi_softc *sc = mac->mac_sc; 1462 struct bwi_rf_lo lo_save, *lo; 1463 uint8_t devi_ctrl = 0; 1464 int idx, adj_rf7a = 0; 1465 1466 bzero(&lo_save, sizeof(lo_save)); 1467 for (idx = 0; idx < RF_ATTEN_LISTSZ; ++idx) { 1468 int init_rf_atten = rf_atten_init_list[idx]; 1469 int rf_atten = rf_atten_list[idx]; 1470 int bbp_atten; 1471 1472 for (bbp_atten = 0; bbp_atten < BBP_ATTEN_MAX; ++bbp_atten) { 1473 uint16_t tp_ctrl2, rf7a; 1474 1475 if ((sc->sc_flags & BWI_F_RUNNING) == 0) { 1476 if (idx == 0) { 1477 bzero(&lo_save, sizeof(lo_save)); 1478 } else if (init_rf_atten < 0) { 1479 lo = bwi_get_rf_lo(mac, 1480 rf_atten, 2 * bbp_atten); 1481 bcopy(lo, &lo_save, sizeof(lo_save)); 1482 } else { 1483 lo = bwi_get_rf_lo(mac, 1484 init_rf_atten, 0); 1485 bcopy(lo, &lo_save, sizeof(lo_save)); 1486 } 1487 1488 devi_ctrl = 0; 1489 adj_rf7a = 0; 1490 1491 /* 1492 * XXX 1493 * Linux driver overflows 'val' 1494 */ 1495 if (init_rf_atten >= 0) { 1496 int val; 1497 1498 val = rf_atten * 2 + bbp_atten; 1499 if (val > 14) { 1500 adj_rf7a = 1; 1501 if (val > 17) 1502 devi_ctrl = 1; 1503 if (val > 19) 1504 devi_ctrl = 2; 1505 } 1506 } 1507 } else { 1508 lo = bwi_get_rf_lo(mac, 1509 rf_atten, 2 * bbp_atten); 1510 if (!bwi_rf_lo_isused(mac, lo)) 1511 continue; 1512 bcopy(lo, &lo_save, sizeof(lo_save)); 1513 1514 devi_ctrl = 3; 1515 adj_rf7a = 0; 1516 } 1517 1518 RF_WRITE(mac, BWI_RFR_ATTEN, rf_atten); 1519 1520 tp_ctrl2 = mac->mac_tpctl.tp_ctrl2; 1521 if (init_rf_atten < 0) 1522 tp_ctrl2 |= (3 << 4); 1523 RF_WRITE(mac, BWI_RFR_TXPWR, tp_ctrl2); 1524 1525 DELAY(10); 1526 1527 bwi_phy_set_bbp_atten(mac, bbp_atten * 2); 1528 1529 rf7a = orig_rf7a & 0xfff0; 1530 if (adj_rf7a) 1531 rf7a |= 0x8; 1532 RF_WRITE(mac, 0x7a, rf7a); 1533 1534 lo = bwi_get_rf_lo(mac, 1535 rf_lo_measure_order[idx], bbp_atten * 2); 1536 bwi_rf_lo_measure_11g(mac, &lo_save, lo, devi_ctrl); 1537 } 1538 } 1539 return devi_ctrl; 1540 1541 #undef RF_ATTEN_LISTSZ 1542 #undef BBP_ATTEN_MAX 1543 } 1544 1545 static void 1546 bwi_rf_lo_measure_11g(struct bwi_mac *mac, const struct bwi_rf_lo *src_lo, 1547 struct bwi_rf_lo *dst_lo, uint8_t devi_ctrl) 1548 { 1549 #define LO_ADJUST_MIN 1 1550 #define LO_ADJUST_MAX 8 1551 #define LO_ADJUST(hi, lo) { .ctrl_hi = hi, .ctrl_lo = lo } 1552 static const struct bwi_rf_lo rf_lo_adjust[LO_ADJUST_MAX] = { 1553 LO_ADJUST(1, 1), 1554 LO_ADJUST(1, 0), 1555 LO_ADJUST(1, -1), 1556 LO_ADJUST(0, -1), 1557 LO_ADJUST(-1, -1), 1558 LO_ADJUST(-1, 0), 1559 LO_ADJUST(-1, 1), 1560 LO_ADJUST(0, 1) 1561 }; 1562 #undef LO_ADJUST 1563 1564 struct bwi_rf_lo lo_min; 1565 uint32_t devi_min; 1566 int found, loop_count, adjust_state; 1567 1568 bcopy(src_lo, &lo_min, sizeof(lo_min)); 1569 RF_LO_WRITE(mac, &lo_min); 1570 devi_min = bwi_rf_lo_devi_measure(mac, devi_ctrl); 1571 1572 loop_count = 12; /* XXX */ 1573 adjust_state = 0; 1574 do { 1575 struct bwi_rf_lo lo_base; 1576 int i, fin; 1577 1578 found = 0; 1579 if (adjust_state == 0) { 1580 i = LO_ADJUST_MIN; 1581 fin = LO_ADJUST_MAX; 1582 } else if (adjust_state % 2 == 0) { 1583 i = adjust_state - 1; 1584 fin = adjust_state + 1; 1585 } else { 1586 i = adjust_state - 2; 1587 fin = adjust_state + 2; 1588 } 1589 1590 if (i < LO_ADJUST_MIN) 1591 i += LO_ADJUST_MAX; 1592 KASSERT(i <= LO_ADJUST_MAX && i >= LO_ADJUST_MIN, ("i %d", i)); 1593 1594 if (fin > LO_ADJUST_MAX) 1595 fin -= LO_ADJUST_MAX; 1596 KASSERT(fin <= LO_ADJUST_MAX && fin >= LO_ADJUST_MIN, 1597 ("fin %d", fin)); 1598 1599 bcopy(&lo_min, &lo_base, sizeof(lo_base)); 1600 for (;;) { 1601 struct bwi_rf_lo lo; 1602 1603 lo.ctrl_hi = lo_base.ctrl_hi + 1604 rf_lo_adjust[i - 1].ctrl_hi; 1605 lo.ctrl_lo = lo_base.ctrl_lo + 1606 rf_lo_adjust[i - 1].ctrl_lo; 1607 1608 if (abs(lo.ctrl_lo) < 9 && abs(lo.ctrl_hi) < 9) { 1609 uint32_t devi; 1610 1611 RF_LO_WRITE(mac, &lo); 1612 devi = bwi_rf_lo_devi_measure(mac, devi_ctrl); 1613 if (devi < devi_min) { 1614 devi_min = devi; 1615 adjust_state = i; 1616 found = 1; 1617 bcopy(&lo, &lo_min, sizeof(lo_min)); 1618 } 1619 } 1620 if (i == fin) 1621 break; 1622 if (i == LO_ADJUST_MAX) 1623 i = LO_ADJUST_MIN; 1624 else 1625 ++i; 1626 } 1627 } while (loop_count-- && found); 1628 1629 bcopy(&lo_min, dst_lo, sizeof(*dst_lo)); 1630 1631 #undef LO_ADJUST_MIN 1632 #undef LO_ADJUST_MAX 1633 } 1634 1635 static void 1636 bwi_rf_calc_nrssi_slope_11b(struct bwi_mac *mac) 1637 { 1638 #define SAVE_RF_MAX 3 1639 #define SAVE_PHY_MAX 8 1640 1641 static const uint16_t save_rf_regs[SAVE_RF_MAX] = 1642 { 0x7a, 0x52, 0x43 }; 1643 static const uint16_t save_phy_regs[SAVE_PHY_MAX] = 1644 { 0x30, 0x26, 0x15, 0x2a, 0x20, 0x5a, 0x59, 0x58 }; 1645 1646 struct bwi_softc *sc = mac->mac_sc; 1647 struct bwi_rf *rf = &mac->mac_rf; 1648 struct bwi_phy *phy = &mac->mac_phy; 1649 uint16_t save_rf[SAVE_RF_MAX]; 1650 uint16_t save_phy[SAVE_PHY_MAX]; 1651 uint16_t ant_div, bbp_atten, chan_ex; 1652 int16_t nrssi[2]; 1653 int i; 1654 1655 /* 1656 * Save RF/PHY registers for later restoration 1657 */ 1658 for (i = 0; i < SAVE_RF_MAX; ++i) 1659 save_rf[i] = RF_READ(mac, save_rf_regs[i]); 1660 for (i = 0; i < SAVE_PHY_MAX; ++i) 1661 save_phy[i] = PHY_READ(mac, save_phy_regs[i]); 1662 1663 ant_div = CSR_READ_2(sc, BWI_RF_ANTDIV); 1664 bbp_atten = CSR_READ_2(sc, BWI_BBP_ATTEN); 1665 chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX); 1666 1667 /* 1668 * Calculate nrssi0 1669 */ 1670 if (phy->phy_rev >= 5) 1671 RF_CLRBITS(mac, 0x7a, 0xff80); 1672 else 1673 RF_CLRBITS(mac, 0x7a, 0xfff0); 1674 PHY_WRITE(mac, 0x30, 0xff); 1675 1676 CSR_WRITE_2(sc, BWI_BPHY_CTRL, 0x7f7f); 1677 1678 PHY_WRITE(mac, 0x26, 0); 1679 PHY_SETBITS(mac, 0x15, 0x20); 1680 PHY_WRITE(mac, 0x2a, 0x8a3); 1681 RF_SETBITS(mac, 0x7a, 0x80); 1682 1683 nrssi[0] = (int16_t)PHY_READ(mac, 0x27); 1684 1685 /* 1686 * Calculate nrssi1 1687 */ 1688 RF_CLRBITS(mac, 0x7a, 0xff80); 1689 if (phy->phy_version >= 2) 1690 CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0x40); 1691 else if (phy->phy_version == 0) 1692 CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0x122); 1693 else 1694 CSR_CLRBITS_2(sc, BWI_RF_CHAN_EX, 0xdfff); 1695 1696 PHY_WRITE(mac, 0x20, 0x3f3f); 1697 PHY_WRITE(mac, 0x15, 0xf330); 1698 1699 RF_WRITE(mac, 0x5a, 0x60); 1700 RF_CLRBITS(mac, 0x43, 0xff0f); 1701 1702 PHY_WRITE(mac, 0x5a, 0x480); 1703 PHY_WRITE(mac, 0x59, 0x810); 1704 PHY_WRITE(mac, 0x58, 0xd); 1705 1706 DELAY(20); 1707 1708 nrssi[1] = (int16_t)PHY_READ(mac, 0x27); 1709 1710 /* 1711 * Restore saved RF/PHY registers 1712 */ 1713 PHY_WRITE(mac, save_phy_regs[0], save_phy[0]); 1714 RF_WRITE(mac, save_rf_regs[0], save_rf[0]); 1715 1716 CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div); 1717 1718 for (i = 1; i < 4; ++i) 1719 PHY_WRITE(mac, save_phy_regs[i], save_phy[i]); 1720 1721 bwi_rf_work_around(mac, rf->rf_curchan); 1722 1723 if (phy->phy_version != 0) 1724 CSR_WRITE_2(sc, BWI_RF_CHAN_EX, chan_ex); 1725 1726 for (; i < SAVE_PHY_MAX; ++i) 1727 PHY_WRITE(mac, save_phy_regs[i], save_phy[i]); 1728 1729 for (i = 1; i < SAVE_RF_MAX; ++i) 1730 RF_WRITE(mac, save_rf_regs[i], save_rf[i]); 1731 1732 /* 1733 * Install calculated narrow RSSI values 1734 */ 1735 if (nrssi[0] == nrssi[1]) 1736 rf->rf_nrssi_slope = 0x10000; 1737 else 1738 rf->rf_nrssi_slope = 0x400000 / (nrssi[0] - nrssi[1]); 1739 if (nrssi[0] <= -4) { 1740 rf->rf_nrssi[0] = nrssi[0]; 1741 rf->rf_nrssi[1] = nrssi[1]; 1742 } 1743 1744 #undef SAVE_RF_MAX 1745 #undef SAVE_PHY_MAX 1746 } 1747 1748 static void 1749 bwi_rf_set_nrssi_ofs_11g(struct bwi_mac *mac) 1750 { 1751 #define SAVE_RF_MAX 2 1752 #define SAVE_PHY_COMM_MAX 10 1753 #define SAVE_PHY6_MAX 8 1754 1755 static const uint16_t save_rf_regs[SAVE_RF_MAX] = 1756 { 0x7a, 0x43 }; 1757 static const uint16_t save_phy_comm_regs[SAVE_PHY_COMM_MAX] = { 1758 0x0001, 0x0811, 0x0812, 0x0814, 1759 0x0815, 0x005a, 0x0059, 0x0058, 1760 0x000a, 0x0003 1761 }; 1762 static const uint16_t save_phy6_regs[SAVE_PHY6_MAX] = { 1763 0x002e, 0x002f, 0x080f, 0x0810, 1764 0x0801, 0x0060, 0x0014, 0x0478 1765 }; 1766 1767 struct bwi_phy *phy = &mac->mac_phy; 1768 uint16_t save_rf[SAVE_RF_MAX]; 1769 uint16_t save_phy_comm[SAVE_PHY_COMM_MAX]; 1770 uint16_t save_phy6[SAVE_PHY6_MAX]; 1771 uint16_t rf7b = 0xffff; 1772 int16_t nrssi; 1773 int i, phy6_idx = 0; 1774 1775 for (i = 0; i < SAVE_PHY_COMM_MAX; ++i) 1776 save_phy_comm[i] = PHY_READ(mac, save_phy_comm_regs[i]); 1777 for (i = 0; i < SAVE_RF_MAX; ++i) 1778 save_rf[i] = RF_READ(mac, save_rf_regs[i]); 1779 1780 PHY_CLRBITS(mac, 0x429, 0x8000); 1781 PHY_FILT_SETBITS(mac, 0x1, 0x3fff, 0x4000); 1782 PHY_SETBITS(mac, 0x811, 0xc); 1783 PHY_FILT_SETBITS(mac, 0x812, 0xfff3, 0x4); 1784 PHY_CLRBITS(mac, 0x802, 0x3); 1785 1786 if (phy->phy_rev >= 6) { 1787 for (i = 0; i < SAVE_PHY6_MAX; ++i) 1788 save_phy6[i] = PHY_READ(mac, save_phy6_regs[i]); 1789 1790 PHY_WRITE(mac, 0x2e, 0); 1791 PHY_WRITE(mac, 0x2f, 0); 1792 PHY_WRITE(mac, 0x80f, 0); 1793 PHY_WRITE(mac, 0x810, 0); 1794 PHY_SETBITS(mac, 0x478, 0x100); 1795 PHY_SETBITS(mac, 0x801, 0x40); 1796 PHY_SETBITS(mac, 0x60, 0x40); 1797 PHY_SETBITS(mac, 0x14, 0x200); 1798 } 1799 1800 RF_SETBITS(mac, 0x7a, 0x70); 1801 RF_SETBITS(mac, 0x7a, 0x80); 1802 1803 DELAY(30); 1804 1805 nrssi = bwi_nrssi_11g(mac); 1806 if (nrssi == 31) { 1807 for (i = 7; i >= 4; --i) { 1808 RF_WRITE(mac, 0x7b, i); 1809 DELAY(20); 1810 nrssi = bwi_nrssi_11g(mac); 1811 if (nrssi < 31 && rf7b == 0xffff) 1812 rf7b = i; 1813 } 1814 if (rf7b == 0xffff) 1815 rf7b = 4; 1816 } else { 1817 struct bwi_gains gains; 1818 1819 RF_CLRBITS(mac, 0x7a, 0xff80); 1820 1821 PHY_SETBITS(mac, 0x814, 0x1); 1822 PHY_CLRBITS(mac, 0x815, 0x1); 1823 PHY_SETBITS(mac, 0x811, 0xc); 1824 PHY_SETBITS(mac, 0x812, 0xc); 1825 PHY_SETBITS(mac, 0x811, 0x30); 1826 PHY_SETBITS(mac, 0x812, 0x30); 1827 PHY_WRITE(mac, 0x5a, 0x480); 1828 PHY_WRITE(mac, 0x59, 0x810); 1829 PHY_WRITE(mac, 0x58, 0xd); 1830 if (phy->phy_version == 0) 1831 PHY_WRITE(mac, 0x3, 0x122); 1832 else 1833 PHY_SETBITS(mac, 0xa, 0x2000); 1834 PHY_SETBITS(mac, 0x814, 0x4); 1835 PHY_CLRBITS(mac, 0x815, 0x4); 1836 PHY_FILT_SETBITS(mac, 0x3, 0xff9f, 0x40); 1837 RF_SETBITS(mac, 0x7a, 0xf); 1838 1839 bzero(&gains, sizeof(gains)); 1840 gains.tbl_gain1 = 3; 1841 gains.tbl_gain2 = 0; 1842 gains.phy_gain = 1; 1843 bwi_set_gains(mac, &gains); 1844 1845 RF_FILT_SETBITS(mac, 0x43, 0xf0, 0xf); 1846 DELAY(30); 1847 1848 nrssi = bwi_nrssi_11g(mac); 1849 if (nrssi == -32) { 1850 for (i = 0; i < 4; ++i) { 1851 RF_WRITE(mac, 0x7b, i); 1852 DELAY(20); 1853 nrssi = bwi_nrssi_11g(mac); 1854 if (nrssi > -31 && rf7b == 0xffff) 1855 rf7b = i; 1856 } 1857 if (rf7b == 0xffff) 1858 rf7b = 3; 1859 } else { 1860 rf7b = 0; 1861 } 1862 } 1863 RF_WRITE(mac, 0x7b, rf7b); 1864 1865 /* 1866 * Restore saved RF/PHY registers 1867 */ 1868 if (phy->phy_rev >= 6) { 1869 for (phy6_idx = 0; phy6_idx < 4; ++phy6_idx) { 1870 PHY_WRITE(mac, save_phy6_regs[phy6_idx], 1871 save_phy6[phy6_idx]); 1872 } 1873 } 1874 1875 /* Saved PHY registers 0, 1, 2 are handled later */ 1876 for (i = 3; i < SAVE_PHY_COMM_MAX; ++i) 1877 PHY_WRITE(mac, save_phy_comm_regs[i], save_phy_comm[i]); 1878 1879 for (i = SAVE_RF_MAX - 1; i >= 0; --i) 1880 RF_WRITE(mac, save_rf_regs[i], save_rf[i]); 1881 1882 PHY_SETBITS(mac, 0x802, 0x3); 1883 PHY_SETBITS(mac, 0x429, 0x8000); 1884 1885 bwi_set_gains(mac, NULL); 1886 1887 if (phy->phy_rev >= 6) { 1888 for (; phy6_idx < SAVE_PHY6_MAX; ++phy6_idx) { 1889 PHY_WRITE(mac, save_phy6_regs[phy6_idx], 1890 save_phy6[phy6_idx]); 1891 } 1892 } 1893 1894 PHY_WRITE(mac, save_phy_comm_regs[0], save_phy_comm[0]); 1895 PHY_WRITE(mac, save_phy_comm_regs[2], save_phy_comm[2]); 1896 PHY_WRITE(mac, save_phy_comm_regs[1], save_phy_comm[1]); 1897 1898 #undef SAVE_RF_MAX 1899 #undef SAVE_PHY_COMM_MAX 1900 #undef SAVE_PHY6_MAX 1901 } 1902 1903 static void 1904 bwi_rf_calc_nrssi_slope_11g(struct bwi_mac *mac) 1905 { 1906 #define SAVE_RF_MAX 3 1907 #define SAVE_PHY_COMM_MAX 4 1908 #define SAVE_PHY3_MAX 8 1909 1910 static const uint16_t save_rf_regs[SAVE_RF_MAX] = 1911 { 0x7a, 0x52, 0x43 }; 1912 static const uint16_t save_phy_comm_regs[SAVE_PHY_COMM_MAX] = 1913 { 0x15, 0x5a, 0x59, 0x58 }; 1914 static const uint16_t save_phy3_regs[SAVE_PHY3_MAX] = { 1915 0x002e, 0x002f, 0x080f, 0x0810, 1916 0x0801, 0x0060, 0x0014, 0x0478 1917 }; 1918 1919 struct bwi_softc *sc = mac->mac_sc; 1920 struct bwi_phy *phy = &mac->mac_phy; 1921 struct bwi_rf *rf = &mac->mac_rf; 1922 uint16_t save_rf[SAVE_RF_MAX]; 1923 uint16_t save_phy_comm[SAVE_PHY_COMM_MAX]; 1924 uint16_t save_phy3[SAVE_PHY3_MAX]; 1925 uint16_t ant_div, bbp_atten, chan_ex; 1926 struct bwi_gains gains; 1927 int16_t nrssi[2]; 1928 int i, phy3_idx = 0; 1929 1930 if (rf->rf_rev >= 9) 1931 return; 1932 else if (rf->rf_rev == 8) 1933 bwi_rf_set_nrssi_ofs_11g(mac); 1934 1935 PHY_CLRBITS(mac, 0x429, 0x8000); 1936 PHY_CLRBITS(mac, 0x802, 0x3); 1937 1938 /* 1939 * Save RF/PHY registers for later restoration 1940 */ 1941 ant_div = CSR_READ_2(sc, BWI_RF_ANTDIV); 1942 CSR_SETBITS_2(sc, BWI_RF_ANTDIV, 0x8000); 1943 1944 for (i = 0; i < SAVE_RF_MAX; ++i) 1945 save_rf[i] = RF_READ(mac, save_rf_regs[i]); 1946 for (i = 0; i < SAVE_PHY_COMM_MAX; ++i) 1947 save_phy_comm[i] = PHY_READ(mac, save_phy_comm_regs[i]); 1948 1949 bbp_atten = CSR_READ_2(sc, BWI_BBP_ATTEN); 1950 chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX); 1951 1952 if (phy->phy_rev >= 3) { 1953 for (i = 0; i < SAVE_PHY3_MAX; ++i) 1954 save_phy3[i] = PHY_READ(mac, save_phy3_regs[i]); 1955 1956 PHY_WRITE(mac, 0x2e, 0); 1957 PHY_WRITE(mac, 0x810, 0); 1958 1959 if (phy->phy_rev == 4 || phy->phy_rev == 6 || 1960 phy->phy_rev == 7) { 1961 PHY_SETBITS(mac, 0x478, 0x100); 1962 PHY_SETBITS(mac, 0x810, 0x40); 1963 } else if (phy->phy_rev == 3 || phy->phy_rev == 5) { 1964 PHY_CLRBITS(mac, 0x810, 0x40); 1965 } 1966 1967 PHY_SETBITS(mac, 0x60, 0x40); 1968 PHY_SETBITS(mac, 0x14, 0x200); 1969 } 1970 1971 /* 1972 * Calculate nrssi0 1973 */ 1974 RF_SETBITS(mac, 0x7a, 0x70); 1975 1976 bzero(&gains, sizeof(gains)); 1977 gains.tbl_gain1 = 0; 1978 gains.tbl_gain2 = 8; 1979 gains.phy_gain = 0; 1980 bwi_set_gains(mac, &gains); 1981 1982 RF_CLRBITS(mac, 0x7a, 0xff08); 1983 if (phy->phy_rev >= 2) { 1984 PHY_FILT_SETBITS(mac, 0x811, 0xffcf, 0x30); 1985 PHY_FILT_SETBITS(mac, 0x812, 0xffcf, 0x10); 1986 } 1987 1988 RF_SETBITS(mac, 0x7a, 0x80); 1989 DELAY(20); 1990 nrssi[0] = bwi_nrssi_11g(mac); 1991 1992 /* 1993 * Calculate nrssi1 1994 */ 1995 RF_CLRBITS(mac, 0x7a, 0xff80); 1996 if (phy->phy_version >= 2) 1997 PHY_FILT_SETBITS(mac, 0x3, 0xff9f, 0x40); 1998 CSR_SETBITS_2(sc, BWI_RF_CHAN_EX, 0x2000); 1999 2000 RF_SETBITS(mac, 0x7a, 0xf); 2001 PHY_WRITE(mac, 0x15, 0xf330); 2002 if (phy->phy_rev >= 2) { 2003 PHY_FILT_SETBITS(mac, 0x812, 0xffcf, 0x20); 2004 PHY_FILT_SETBITS(mac, 0x811, 0xffcf, 0x20); 2005 } 2006 2007 bzero(&gains, sizeof(gains)); 2008 gains.tbl_gain1 = 3; 2009 gains.tbl_gain2 = 0; 2010 gains.phy_gain = 1; 2011 bwi_set_gains(mac, &gains); 2012 2013 if (rf->rf_rev == 8) { 2014 RF_WRITE(mac, 0x43, 0x1f); 2015 } else { 2016 RF_FILT_SETBITS(mac, 0x52, 0xff0f, 0x60); 2017 RF_FILT_SETBITS(mac, 0x43, 0xfff0, 0x9); 2018 } 2019 PHY_WRITE(mac, 0x5a, 0x480); 2020 PHY_WRITE(mac, 0x59, 0x810); 2021 PHY_WRITE(mac, 0x58, 0xd); 2022 DELAY(20); 2023 2024 nrssi[1] = bwi_nrssi_11g(mac); 2025 2026 /* 2027 * Install calculated narrow RSSI values 2028 */ 2029 if (nrssi[1] == nrssi[0]) 2030 rf->rf_nrssi_slope = 0x10000; 2031 else 2032 rf->rf_nrssi_slope = 0x400000 / (nrssi[0] - nrssi[1]); 2033 if (nrssi[0] >= -4) { 2034 rf->rf_nrssi[0] = nrssi[1]; 2035 rf->rf_nrssi[1] = nrssi[0]; 2036 } 2037 2038 /* 2039 * Restore saved RF/PHY registers 2040 */ 2041 if (phy->phy_rev >= 3) { 2042 for (phy3_idx = 0; phy3_idx < 4; ++phy3_idx) { 2043 PHY_WRITE(mac, save_phy3_regs[phy3_idx], 2044 save_phy3[phy3_idx]); 2045 } 2046 } 2047 if (phy->phy_rev >= 2) { 2048 PHY_CLRBITS(mac, 0x812, 0x30); 2049 PHY_CLRBITS(mac, 0x811, 0x30); 2050 } 2051 2052 for (i = 0; i < SAVE_RF_MAX; ++i) 2053 RF_WRITE(mac, save_rf_regs[i], save_rf[i]); 2054 2055 CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div); 2056 CSR_WRITE_2(sc, BWI_BBP_ATTEN, bbp_atten); 2057 CSR_WRITE_2(sc, BWI_RF_CHAN_EX, chan_ex); 2058 2059 for (i = 0; i < SAVE_PHY_COMM_MAX; ++i) 2060 PHY_WRITE(mac, save_phy_comm_regs[i], save_phy_comm[i]); 2061 2062 bwi_rf_work_around(mac, rf->rf_curchan); 2063 PHY_SETBITS(mac, 0x802, 0x3); 2064 bwi_set_gains(mac, NULL); 2065 PHY_SETBITS(mac, 0x429, 0x8000); 2066 2067 if (phy->phy_rev >= 3) { 2068 for (; phy3_idx < SAVE_PHY3_MAX; ++phy3_idx) { 2069 PHY_WRITE(mac, save_phy3_regs[phy3_idx], 2070 save_phy3[phy3_idx]); 2071 } 2072 } 2073 2074 bwi_rf_init_sw_nrssi_table(mac); 2075 bwi_rf_set_nrssi_thr_11g(mac); 2076 2077 #undef SAVE_RF_MAX 2078 #undef SAVE_PHY_COMM_MAX 2079 #undef SAVE_PHY3_MAX 2080 } 2081 2082 static void 2083 bwi_rf_init_sw_nrssi_table(struct bwi_mac *mac) 2084 { 2085 struct bwi_rf *rf = &mac->mac_rf; 2086 int d, i; 2087 2088 d = 0x1f - rf->rf_nrssi[0]; 2089 for (i = 0; i < BWI_NRSSI_TBLSZ; ++i) { 2090 int val; 2091 2092 val = (((i - d) * rf->rf_nrssi_slope) / 0x10000) + 0x3a; 2093 if (val < 0) 2094 val = 0; 2095 else if (val > 0x3f) 2096 val = 0x3f; 2097 2098 rf->rf_nrssi_table[i] = val; 2099 } 2100 } 2101 2102 void 2103 bwi_rf_init_hw_nrssi_table(struct bwi_mac *mac, uint16_t adjust) 2104 { 2105 int i; 2106 2107 for (i = 0; i < BWI_NRSSI_TBLSZ; ++i) { 2108 int16_t val; 2109 2110 val = bwi_nrssi_read(mac, i); 2111 2112 val -= adjust; 2113 if (val < -32) 2114 val = -32; 2115 else if (val > 31) 2116 val = 31; 2117 2118 bwi_nrssi_write(mac, i, val); 2119 } 2120 } 2121 2122 static void 2123 bwi_rf_set_nrssi_thr_11b(struct bwi_mac *mac) 2124 { 2125 struct bwi_rf *rf = &mac->mac_rf; 2126 int32_t thr; 2127 2128 if (rf->rf_type != BWI_RF_T_BCM2050 || 2129 (mac->mac_sc->sc_card_flags & BWI_CARD_F_SW_NRSSI) == 0) 2130 return; 2131 2132 /* 2133 * Calculate nrssi threshold 2134 */ 2135 if (rf->rf_rev >= 6) { 2136 thr = (rf->rf_nrssi[1] - rf->rf_nrssi[0]) * 32; 2137 thr += 20 * (rf->rf_nrssi[0] + 1); 2138 thr /= 40; 2139 } else { 2140 thr = rf->rf_nrssi[1] - 5; 2141 } 2142 if (thr < 0) 2143 thr = 0; 2144 else if (thr > 0x3e) 2145 thr = 0x3e; 2146 2147 PHY_READ(mac, BWI_PHYR_NRSSI_THR_11B); /* dummy read */ 2148 PHY_WRITE(mac, BWI_PHYR_NRSSI_THR_11B, (((uint16_t)thr) << 8) | 0x1c); 2149 2150 if (rf->rf_rev >= 6) { 2151 PHY_WRITE(mac, 0x87, 0xe0d); 2152 PHY_WRITE(mac, 0x86, 0xc0b); 2153 PHY_WRITE(mac, 0x85, 0xa09); 2154 PHY_WRITE(mac, 0x84, 0x808); 2155 PHY_WRITE(mac, 0x83, 0x808); 2156 PHY_WRITE(mac, 0x82, 0x604); 2157 PHY_WRITE(mac, 0x81, 0x302); 2158 PHY_WRITE(mac, 0x80, 0x100); 2159 } 2160 } 2161 2162 static __inline int32_t 2163 _nrssi_threshold(const struct bwi_rf *rf, int32_t val) 2164 { 2165 val *= (rf->rf_nrssi[1] - rf->rf_nrssi[0]); 2166 val += (rf->rf_nrssi[0] << 6); 2167 if (val < 32) 2168 val += 31; 2169 else 2170 val += 32; 2171 val >>= 6; 2172 if (val < -31) 2173 val = -31; 2174 else if (val > 31) 2175 val = 31; 2176 return val; 2177 } 2178 2179 static void 2180 bwi_rf_set_nrssi_thr_11g(struct bwi_mac *mac) 2181 { 2182 int32_t thr1, thr2; 2183 uint16_t thr; 2184 2185 /* 2186 * Find the two nrssi thresholds 2187 */ 2188 if ((mac->mac_phy.phy_flags & BWI_PHY_F_LINKED) == 0 || 2189 (mac->mac_sc->sc_card_flags & BWI_CARD_F_SW_NRSSI) == 0) { 2190 int16_t nrssi; 2191 2192 nrssi = bwi_nrssi_read(mac, 0x20); 2193 if (nrssi >= 32) 2194 nrssi -= 64; 2195 2196 if (nrssi < 3) { 2197 thr1 = 0x2b; 2198 thr2 = 0x27; 2199 } else { 2200 thr1 = 0x2d; 2201 thr2 = 0x2b; 2202 } 2203 } else { 2204 /* TODO Interfere mode */ 2205 thr1 = _nrssi_threshold(&mac->mac_rf, 0x11); 2206 thr2 = _nrssi_threshold(&mac->mac_rf, 0xe); 2207 } 2208 2209 #define NRSSI_THR1_MASK __BITS(5, 0) 2210 #define NRSSI_THR2_MASK __BITS(11, 6) 2211 2212 thr = __SHIFTIN((uint32_t)thr1, NRSSI_THR1_MASK) | 2213 __SHIFTIN((uint32_t)thr2, NRSSI_THR2_MASK); 2214 PHY_FILT_SETBITS(mac, BWI_PHYR_NRSSI_THR_11G, 0xf000, thr); 2215 2216 #undef NRSSI_THR1_MASK 2217 #undef NRSSI_THR2_MASK 2218 } 2219 2220 void 2221 bwi_rf_clear_tssi(struct bwi_mac *mac) 2222 { 2223 /* XXX use function pointer */ 2224 if (mac->mac_phy.phy_mode == IEEE80211_MODE_11A) { 2225 /* TODO:11A */ 2226 } else { 2227 uint16_t val; 2228 int i; 2229 2230 val = __SHIFTIN(BWI_INVALID_TSSI, BWI_LO_TSSI_MASK) | 2231 __SHIFTIN(BWI_INVALID_TSSI, BWI_HI_TSSI_MASK); 2232 2233 for (i = 0; i < 2; ++i) { 2234 MOBJ_WRITE_2(mac, BWI_COMM_MOBJ, 2235 BWI_COMM_MOBJ_TSSI_DS + (i * 2), val); 2236 } 2237 2238 for (i = 0; i < 2; ++i) { 2239 MOBJ_WRITE_2(mac, BWI_COMM_MOBJ, 2240 BWI_COMM_MOBJ_TSSI_OFDM + (i * 2), val); 2241 } 2242 } 2243 } 2244 2245 void 2246 bwi_rf_clear_state(struct bwi_rf *rf) 2247 { 2248 int i; 2249 2250 rf->rf_flags &= ~BWI_RF_CLEAR_FLAGS; 2251 bzero(rf->rf_lo, sizeof(rf->rf_lo)); 2252 bzero(rf->rf_lo_used, sizeof(rf->rf_lo_used)); 2253 2254 rf->rf_nrssi_slope = 0; 2255 rf->rf_nrssi[0] = BWI_INVALID_NRSSI; 2256 rf->rf_nrssi[1] = BWI_INVALID_NRSSI; 2257 2258 for (i = 0; i < BWI_NRSSI_TBLSZ; ++i) 2259 rf->rf_nrssi_table[i] = i; 2260 2261 rf->rf_lo_gain = 0; 2262 rf->rf_rx_gain = 0; 2263 2264 bcopy(rf->rf_txpower_map0, rf->rf_txpower_map, 2265 sizeof(rf->rf_txpower_map)); 2266 rf->rf_idle_tssi = rf->rf_idle_tssi0; 2267 } 2268 2269 static void 2270 bwi_rf_on_11a(struct bwi_mac *mac) 2271 { 2272 /* TODO:11A */ 2273 } 2274 2275 static void 2276 bwi_rf_on_11bg(struct bwi_mac *mac) 2277 { 2278 struct bwi_phy *phy = &mac->mac_phy; 2279 2280 PHY_WRITE(mac, 0x15, 0x8000); 2281 PHY_WRITE(mac, 0x15, 0xcc00); 2282 if (phy->phy_flags & BWI_PHY_F_LINKED) 2283 PHY_WRITE(mac, 0x15, 0xc0); 2284 else 2285 PHY_WRITE(mac, 0x15, 0); 2286 2287 bwi_rf_set_chan(mac, 6 /* XXX */, 1); 2288 } 2289 2290 void 2291 bwi_rf_set_ant_mode(struct bwi_mac *mac, int ant_mode) 2292 { 2293 struct bwi_softc *sc = mac->mac_sc; 2294 struct bwi_phy *phy = &mac->mac_phy; 2295 uint16_t val; 2296 2297 KASSERT(ant_mode == BWI_ANT_MODE_0 || 2298 ant_mode == BWI_ANT_MODE_1 || 2299 ant_mode == BWI_ANT_MODE_AUTO, ("ant_mode %d", ant_mode)); 2300 2301 HFLAGS_CLRBITS(mac, BWI_HFLAG_AUTO_ANTDIV); 2302 2303 if (phy->phy_mode == IEEE80211_MODE_11B) { 2304 /* NOTE: v4/v3 conflicts, take v3 */ 2305 if (mac->mac_rev == 2) 2306 val = BWI_ANT_MODE_AUTO; 2307 else 2308 val = ant_mode; 2309 val <<= 7; 2310 PHY_FILT_SETBITS(mac, 0x3e2, 0xfe7f, val); 2311 } else { /* 11a/g */ 2312 /* XXX reg/value naming */ 2313 val = ant_mode << 7; 2314 PHY_FILT_SETBITS(mac, 0x401, 0x7e7f, val); 2315 2316 if (ant_mode == BWI_ANT_MODE_AUTO) 2317 PHY_CLRBITS(mac, 0x42b, 0x100); 2318 2319 if (phy->phy_mode == IEEE80211_MODE_11A) { 2320 /* TODO:11A */ 2321 } else { /* 11g */ 2322 if (ant_mode == BWI_ANT_MODE_AUTO) 2323 PHY_SETBITS(mac, 0x48c, 0x2000); 2324 else 2325 PHY_CLRBITS(mac, 0x48c, 0x2000); 2326 2327 if (phy->phy_rev >= 2) { 2328 PHY_SETBITS(mac, 0x461, 0x10); 2329 PHY_FILT_SETBITS(mac, 0x4ad, 0xff00, 0x15); 2330 if (phy->phy_rev == 2) { 2331 PHY_WRITE(mac, 0x427, 0x8); 2332 } else { 2333 PHY_FILT_SETBITS(mac, 0x427, 2334 0xff00, 0x8); 2335 } 2336 2337 if (phy->phy_rev >= 6) 2338 PHY_WRITE(mac, 0x49b, 0xdc); 2339 } 2340 } 2341 } 2342 2343 /* XXX v4 set AUTO_ANTDIV unconditionally */ 2344 if (ant_mode == BWI_ANT_MODE_AUTO) 2345 HFLAGS_SETBITS(mac, BWI_HFLAG_AUTO_ANTDIV); 2346 2347 val = ant_mode << 8; 2348 MOBJ_FILT_SETBITS_2(mac, BWI_COMM_MOBJ, BWI_COMM_MOBJ_TX_BEACON, 2349 0xfc3f, val); 2350 MOBJ_FILT_SETBITS_2(mac, BWI_COMM_MOBJ, BWI_COMM_MOBJ_TX_ACK, 2351 0xfc3f, val); 2352 MOBJ_FILT_SETBITS_2(mac, BWI_COMM_MOBJ, BWI_COMM_MOBJ_TX_PROBE_RESP, 2353 0xfc3f, val); 2354 2355 /* XXX what's these */ 2356 if (phy->phy_mode == IEEE80211_MODE_11B) 2357 CSR_SETBITS_2(sc, 0x5e, 0x4); 2358 2359 CSR_WRITE_4(sc, 0x100, 0x1000000); 2360 if (mac->mac_rev < 5) 2361 CSR_WRITE_4(sc, 0x10c, 0x1000000); 2362 2363 mac->mac_rf.rf_ant_mode = ant_mode; 2364 } 2365 2366 int 2367 bwi_rf_get_latest_tssi(struct bwi_mac *mac, int8_t tssi[], uint16_t ofs) 2368 { 2369 int i; 2370 2371 for (i = 0; i < 4; ) { 2372 uint16_t val; 2373 2374 val = MOBJ_READ_2(mac, BWI_COMM_MOBJ, ofs + i); 2375 tssi[i++] = (int8_t)__SHIFTOUT(val, BWI_LO_TSSI_MASK); 2376 tssi[i++] = (int8_t)__SHIFTOUT(val, BWI_HI_TSSI_MASK); 2377 } 2378 2379 for (i = 0; i < 4; ++i) { 2380 if (tssi[i] == BWI_INVALID_TSSI) 2381 return EINVAL; 2382 } 2383 return 0; 2384 } 2385 2386 int 2387 bwi_rf_tssi2dbm(struct bwi_mac *mac, int8_t tssi, int8_t *txpwr) 2388 { 2389 struct bwi_rf *rf = &mac->mac_rf; 2390 int pwr_idx; 2391 2392 pwr_idx = rf->rf_idle_tssi + (int)tssi - rf->rf_base_tssi; 2393 #if 0 2394 if (pwr_idx < 0 || pwr_idx >= BWI_TSSI_MAX) 2395 return EINVAL; 2396 #else 2397 if (pwr_idx < 0) 2398 pwr_idx = 0; 2399 else if (pwr_idx >= BWI_TSSI_MAX) 2400 pwr_idx = BWI_TSSI_MAX - 1; 2401 #endif 2402 2403 *txpwr = rf->rf_txpower_map[pwr_idx]; 2404 return 0; 2405 } 2406 2407 static int 2408 bwi_rf_calc_rssi_bcm2050(struct bwi_mac *mac, const struct bwi_rxbuf_hdr *hdr) 2409 { 2410 uint16_t flags1, flags3; 2411 int rssi, lna_gain; 2412 2413 rssi = hdr->rxh_rssi; 2414 flags1 = le16toh(hdr->rxh_flags1); 2415 flags3 = le16toh(hdr->rxh_flags3); 2416 2417 if (flags1 & BWI_RXH_F1_OFDM) { 2418 if (rssi > 127) 2419 rssi -= 256; 2420 if (flags3 & BWI_RXH_F3_BCM2050_RSSI) 2421 rssi += 17; 2422 else 2423 rssi -= 4; 2424 return rssi; 2425 } 2426 2427 if (mac->mac_sc->sc_card_flags & BWI_CARD_F_SW_NRSSI) { 2428 struct bwi_rf *rf = &mac->mac_rf; 2429 2430 if (rssi >= BWI_NRSSI_TBLSZ) 2431 rssi = BWI_NRSSI_TBLSZ - 1; 2432 2433 rssi = ((31 - (int)rf->rf_nrssi_table[rssi]) * -131) / 128; 2434 rssi -= 67; 2435 } else { 2436 rssi = ((31 - rssi) * -149) / 128; 2437 rssi -= 68; 2438 } 2439 2440 if (mac->mac_phy.phy_mode != IEEE80211_MODE_11G) 2441 return rssi; 2442 2443 if (flags3 & BWI_RXH_F3_BCM2050_RSSI) 2444 rssi += 20; 2445 2446 lna_gain = __SHIFTOUT(le16toh(hdr->rxh_phyinfo), 2447 BWI_RXH_PHYINFO_LNAGAIN); 2448 DPRINTF(mac->mac_sc, BWI_DBG_RF | BWI_DBG_RX, 2449 "lna_gain %d, phyinfo 0x%04x\n", 2450 lna_gain, le16toh(hdr->rxh_phyinfo)); 2451 switch (lna_gain) { 2452 case 0: 2453 rssi += 27; 2454 break; 2455 case 1: 2456 rssi += 6; 2457 break; 2458 case 2: 2459 rssi += 12; 2460 break; 2461 case 3: 2462 /* 2463 * XXX 2464 * According to v3 spec, we should do _nothing_ here, 2465 * but it seems that the result RSSI will be too low 2466 * (relative to what ath(4) says). Raise it a little 2467 * bit. 2468 */ 2469 rssi += 5; 2470 break; 2471 default: 2472 panic("impossible lna gain %d", lna_gain); 2473 } 2474 return rssi; 2475 } 2476 2477 static int 2478 bwi_rf_calc_rssi_bcm2053(struct bwi_mac *mac, const struct bwi_rxbuf_hdr *hdr) 2479 { 2480 uint16_t flags1; 2481 int rssi; 2482 2483 rssi = (((int)hdr->rxh_rssi - 11) * 103) / 64; 2484 2485 flags1 = le16toh(hdr->rxh_flags1); 2486 if (flags1 & BWI_RXH_F1_BCM2053_RSSI) 2487 rssi -= 109; 2488 else 2489 rssi -= 83; 2490 return rssi; 2491 } 2492 2493 static int 2494 bwi_rf_calc_rssi_bcm2060(struct bwi_mac *mac, const struct bwi_rxbuf_hdr *hdr) 2495 { 2496 int rssi; 2497 2498 rssi = hdr->rxh_rssi; 2499 if (rssi > 127) 2500 rssi -= 256; 2501 return rssi; 2502 } 2503 2504 static int 2505 bwi_rf_calc_noise_bcm2050(struct bwi_mac *mac) 2506 { 2507 uint16_t val; 2508 int noise; 2509 2510 val = MOBJ_READ_2(mac, BWI_COMM_MOBJ, BWI_COMM_MOBJ_RF_NOISE); 2511 noise = (int)val; /* XXX check bounds? */ 2512 2513 if (mac->mac_sc->sc_card_flags & BWI_CARD_F_SW_NRSSI) { 2514 struct bwi_rf *rf = &mac->mac_rf; 2515 2516 if (noise >= BWI_NRSSI_TBLSZ) 2517 noise = BWI_NRSSI_TBLSZ - 1; 2518 2519 noise = ((31 - (int)rf->rf_nrssi_table[noise]) * -131) / 128; 2520 noise -= 67; 2521 } else { 2522 noise = ((31 - noise) * -149) / 128; 2523 noise -= 68; 2524 } 2525 return noise; 2526 } 2527 2528 static int 2529 bwi_rf_calc_noise_bcm2053(struct bwi_mac *mac) 2530 { 2531 uint16_t val; 2532 int noise; 2533 2534 val = MOBJ_READ_2(mac, BWI_COMM_MOBJ, BWI_COMM_MOBJ_RF_NOISE); 2535 noise = (int)val; /* XXX check bounds? */ 2536 2537 noise = ((noise - 11) * 103) / 64; 2538 noise -= 109; 2539 return noise; 2540 } 2541 2542 static int 2543 bwi_rf_calc_noise_bcm2060(struct bwi_mac *mac) 2544 { 2545 /* XXX Dont know how to calc */ 2546 return (BWI_NOISE_FLOOR); 2547 } 2548 2549 static uint16_t 2550 bwi_rf_lo_measure_11b(struct bwi_mac *mac) 2551 { 2552 uint16_t val; 2553 int i; 2554 2555 val = 0; 2556 for (i = 0; i < 10; ++i) { 2557 PHY_WRITE(mac, 0x15, 0xafa0); 2558 DELAY(1); 2559 PHY_WRITE(mac, 0x15, 0xefa0); 2560 DELAY(10); 2561 PHY_WRITE(mac, 0x15, 0xffa0); 2562 DELAY(40); 2563 2564 val += PHY_READ(mac, 0x2c); 2565 } 2566 return val; 2567 } 2568 2569 static void 2570 bwi_rf_lo_update_11b(struct bwi_mac *mac) 2571 { 2572 struct bwi_softc *sc = mac->mac_sc; 2573 struct bwi_rf *rf = &mac->mac_rf; 2574 struct rf_saveregs regs; 2575 uint16_t rf_val, phy_val, min_val, val; 2576 uint16_t rf52, bphy_ctrl; 2577 int i; 2578 2579 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_INIT, "%s enter\n", __func__); 2580 2581 bzero(®s, sizeof(regs)); 2582 bphy_ctrl = 0; 2583 2584 /* 2585 * Save RF/PHY registers for later restoration 2586 */ 2587 SAVE_PHY_REG(mac, ®s, 15); 2588 rf52 = RF_READ(mac, 0x52) & 0xfff0; 2589 if (rf->rf_type == BWI_RF_T_BCM2050) { 2590 SAVE_PHY_REG(mac, ®s, 0a); 2591 SAVE_PHY_REG(mac, ®s, 2a); 2592 SAVE_PHY_REG(mac, ®s, 35); 2593 SAVE_PHY_REG(mac, ®s, 03); 2594 SAVE_PHY_REG(mac, ®s, 01); 2595 SAVE_PHY_REG(mac, ®s, 30); 2596 2597 SAVE_RF_REG(mac, ®s, 43); 2598 SAVE_RF_REG(mac, ®s, 7a); 2599 2600 bphy_ctrl = CSR_READ_2(sc, BWI_BPHY_CTRL); 2601 2602 SAVE_RF_REG(mac, ®s, 52); 2603 regs.rf_52 &= 0xf0; 2604 2605 PHY_WRITE(mac, 0x30, 0xff); 2606 CSR_WRITE_2(sc, BWI_PHY_CTRL, 0x3f3f); 2607 PHY_WRITE(mac, 0x35, regs.phy_35 & 0xff7f); 2608 RF_WRITE(mac, 0x7a, regs.rf_7a & 0xfff0); 2609 } 2610 2611 PHY_WRITE(mac, 0x15, 0xb000); 2612 2613 if (rf->rf_type == BWI_RF_T_BCM2050) { 2614 PHY_WRITE(mac, 0x2b, 0x203); 2615 PHY_WRITE(mac, 0x2a, 0x8a3); 2616 } else { 2617 PHY_WRITE(mac, 0x2b, 0x1402); 2618 } 2619 2620 /* 2621 * Setup RF signal 2622 */ 2623 rf_val = 0; 2624 min_val = UINT16_MAX; 2625 2626 for (i = 0; i < 4; ++i) { 2627 RF_WRITE(mac, 0x52, rf52 | i); 2628 bwi_rf_lo_measure_11b(mac); /* Ignore return value */ 2629 } 2630 for (i = 0; i < 10; ++i) { 2631 RF_WRITE(mac, 0x52, rf52 | i); 2632 2633 val = bwi_rf_lo_measure_11b(mac) / 10; 2634 if (val < min_val) { 2635 min_val = val; 2636 rf_val = i; 2637 } 2638 } 2639 RF_WRITE(mac, 0x52, rf52 | rf_val); 2640 2641 /* 2642 * Setup PHY signal 2643 */ 2644 phy_val = 0; 2645 min_val = UINT16_MAX; 2646 2647 for (i = -4; i < 5; i += 2) { 2648 int j; 2649 2650 for (j = -4; j < 5; j += 2) { 2651 uint16_t phy2f; 2652 2653 phy2f = (0x100 * i) + j; 2654 if (j < 0) 2655 phy2f += 0x100; 2656 PHY_WRITE(mac, 0x2f, phy2f); 2657 2658 val = bwi_rf_lo_measure_11b(mac) / 10; 2659 if (val < min_val) { 2660 min_val = val; 2661 phy_val = phy2f; 2662 } 2663 } 2664 } 2665 PHY_WRITE(mac, 0x2f, phy_val + 0x101); 2666 2667 /* 2668 * Restore saved RF/PHY registers 2669 */ 2670 if (rf->rf_type == BWI_RF_T_BCM2050) { 2671 RESTORE_PHY_REG(mac, ®s, 0a); 2672 RESTORE_PHY_REG(mac, ®s, 2a); 2673 RESTORE_PHY_REG(mac, ®s, 35); 2674 RESTORE_PHY_REG(mac, ®s, 03); 2675 RESTORE_PHY_REG(mac, ®s, 01); 2676 RESTORE_PHY_REG(mac, ®s, 30); 2677 2678 RESTORE_RF_REG(mac, ®s, 43); 2679 RESTORE_RF_REG(mac, ®s, 7a); 2680 2681 RF_FILT_SETBITS(mac, 0x52, 0xf, regs.rf_52); 2682 2683 CSR_WRITE_2(sc, BWI_BPHY_CTRL, bphy_ctrl); 2684 } 2685 RESTORE_PHY_REG(mac, ®s, 15); 2686 2687 bwi_rf_work_around(mac, rf->rf_curchan); 2688 } 2689