1 /************************************************************************** 2 SPDX-License-Identifier: BSD-2-Clause 3 4 Copyright (c) 2007-2008, Chelsio Inc. 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Neither the name of the Chelsio Corporation nor the names of its 14 contributors may be used to endorse or promote products derived from 15 this software without specific prior written permission. 16 17 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 21 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 POSSIBILITY OF SUCH DAMAGE. 28 29 $FreeBSD$ 30 31 ***************************************************************************/ 32 #ifndef __CHIOCTL_H__ 33 #define __CHIOCTL_H__ 34 35 /* 36 * Ioctl commands specific to this driver. 37 */ 38 enum { 39 CH_SETREG = 0x40, 40 CH_GETREG, 41 CH_GETMTUTAB, 42 CH_SETMTUTAB, 43 CH_SET_PM, 44 CH_GET_PM, 45 CH_READ_TCAM_WORD, 46 CH_GET_MEM, 47 CH_GET_SGE_CONTEXT, 48 CH_GET_SGE_DESC, 49 CH_LOAD_FW, 50 CH_SET_TRACE_FILTER, 51 CH_GET_QSET_PARAMS, 52 CH_GET_QSET_NUM, 53 CH_SET_PKTSCHED, 54 CH_IFCONF_GETREGS, 55 CH_GET_MIIREG, 56 CH_SET_MIIREG, 57 CH_GET_EEPROM, 58 CH_SET_HW_SCHED, 59 CH_LOAD_BOOT, 60 CH_CLEAR_STATS, 61 CH_GET_UP_LA, 62 CH_GET_UP_IOQS, 63 CH_SET_FILTER, 64 CH_DEL_FILTER, 65 CH_GET_FILTER, 66 }; 67 68 /* statistics categories */ 69 enum { 70 STATS_PORT = 1 << 1, 71 STATS_QUEUE = 1 << 2, 72 }; 73 74 struct ch_reg { 75 uint32_t addr; 76 uint32_t val; 77 }; 78 79 struct ch_cntxt { 80 uint32_t cntxt_type; 81 uint32_t cntxt_id; 82 uint32_t data[4]; 83 }; 84 85 /* context types */ 86 enum { CNTXT_TYPE_EGRESS, CNTXT_TYPE_FL, CNTXT_TYPE_RSP, CNTXT_TYPE_CQ }; 87 88 struct ch_desc { 89 uint32_t queue_num; 90 uint32_t idx; 91 uint32_t size; 92 uint8_t data[128]; 93 }; 94 95 struct ch_mem_range { 96 uint32_t mem_id; 97 uint32_t addr; 98 uint32_t len; 99 uint32_t version; 100 uint8_t *buf; 101 }; 102 103 enum { MEM_CM, MEM_PMRX, MEM_PMTX }; /* ch_mem_range.mem_id values */ 104 105 struct ch_qset_params { 106 uint32_t qset_idx; 107 int32_t txq_size[3]; 108 int32_t rspq_size; 109 int32_t fl_size[2]; 110 int32_t intr_lat; 111 int32_t polling; 112 int32_t lro; 113 int32_t cong_thres; 114 int32_t vector; 115 int32_t qnum; 116 }; 117 118 struct ch_pktsched_params { 119 uint8_t sched; 120 uint8_t idx; 121 uint8_t min; 122 uint8_t max; 123 uint8_t binding; 124 }; 125 126 struct ch_hw_sched { 127 uint8_t sched; 128 int8_t mode; 129 int8_t channel; 130 int32_t kbps; /* rate in Kbps */ 131 int32_t class_ipg; /* tenths of nanoseconds */ 132 int32_t flow_ipg; /* usec */ 133 }; 134 135 struct ch_mtus { 136 uint32_t nmtus; 137 uint16_t mtus[NMTUS]; 138 }; 139 140 struct ch_pm { 141 uint32_t tx_pg_sz; 142 uint32_t tx_num_pg; 143 uint32_t rx_pg_sz; 144 uint32_t rx_num_pg; 145 uint32_t pm_total; 146 }; 147 148 struct ch_tcam_word { 149 uint32_t addr; 150 uint32_t buf[3]; 151 }; 152 153 struct ch_trace { 154 uint32_t sip; 155 uint32_t sip_mask; 156 uint32_t dip; 157 uint32_t dip_mask; 158 uint16_t sport; 159 uint16_t sport_mask; 160 uint16_t dport; 161 uint16_t dport_mask; 162 uint32_t vlan:12; 163 uint32_t vlan_mask:12; 164 uint32_t intf:4; 165 uint32_t intf_mask:4; 166 uint8_t proto; 167 uint8_t proto_mask; 168 uint8_t invert_match:1; 169 uint8_t config_tx:1; 170 uint8_t config_rx:1; 171 uint8_t trace_tx:1; 172 uint8_t trace_rx:1; 173 }; 174 175 #define REGDUMP_SIZE (4 * 1024) 176 177 struct ch_ifconf_regs { 178 uint32_t version; 179 uint32_t len; /* bytes */ 180 uint8_t *data; 181 }; 182 183 struct ch_mii_data { 184 uint32_t phy_id; 185 uint32_t reg_num; 186 uint32_t val_in; 187 uint32_t val_out; 188 }; 189 190 struct ch_eeprom { 191 uint32_t magic; 192 uint32_t offset; 193 uint32_t len; 194 uint8_t *data; 195 }; 196 197 #define LA_BUFSIZE (2 * 1024) 198 struct ch_up_la { 199 uint32_t stopped; 200 uint32_t idx; 201 uint32_t bufsize; 202 uint32_t *data; 203 }; 204 205 struct t3_ioq_entry { 206 uint32_t ioq_cp; 207 uint32_t ioq_pp; 208 uint32_t ioq_alen; 209 uint32_t ioq_stats; 210 }; 211 212 #define IOQS_BUFSIZE (1024) 213 struct ch_up_ioqs { 214 uint32_t ioq_rx_enable; 215 uint32_t ioq_tx_enable; 216 uint32_t ioq_rx_status; 217 uint32_t ioq_tx_status; 218 uint32_t bufsize; 219 struct t3_ioq_entry *data; 220 }; 221 222 struct ch_filter_tuple { 223 uint32_t sip; 224 uint32_t dip; 225 uint16_t sport; 226 uint16_t dport; 227 uint16_t vlan:12; 228 uint16_t vlan_prio:3; 229 }; 230 231 struct ch_filter { 232 uint32_t filter_id; 233 struct ch_filter_tuple val; 234 struct ch_filter_tuple mask; 235 uint16_t mac_addr_idx; 236 uint8_t mac_hit:1; 237 uint8_t proto:2; 238 239 uint8_t want_filter_id:1; 240 uint8_t pass:1; 241 uint8_t rss:1; 242 uint8_t qset; 243 }; 244 245 #define CHELSIO_SETREG _IOW('f', CH_SETREG, struct ch_reg) 246 #define CHELSIO_GETREG _IOWR('f', CH_GETREG, struct ch_reg) 247 #define CHELSIO_GETMTUTAB _IOR('f', CH_GETMTUTAB, struct ch_mtus) 248 #define CHELSIO_SETMTUTAB _IOW('f', CH_SETMTUTAB, struct ch_mtus) 249 #define CHELSIO_SET_PM _IOW('f', CH_SET_PM, struct ch_pm) 250 #define CHELSIO_GET_PM _IOR('f', CH_GET_PM, struct ch_pm) 251 #define CHELSIO_READ_TCAM_WORD _IOWR('f', CH_READ_TCAM_WORD, struct ch_tcam_word) 252 #define CHELSIO_GET_MEM _IOWR('f', CH_GET_MEM, struct ch_mem_range) 253 #define CHELSIO_GET_SGE_CONTEXT _IOWR('f', CH_GET_SGE_CONTEXT, struct ch_cntxt) 254 #define CHELSIO_GET_SGE_DESC _IOWR('f', CH_GET_SGE_DESC, struct ch_desc) 255 #define CHELSIO_LOAD_FW _IOWR('f', CH_LOAD_FW, struct ch_mem_range) 256 #define CHELSIO_SET_TRACE_FILTER _IOW('f', CH_SET_TRACE_FILTER, struct ch_trace) 257 #define CHELSIO_GET_QSET_PARAMS _IOWR('f', CH_GET_QSET_PARAMS, struct ch_qset_params) 258 #define CHELSIO_GET_QSET_NUM _IOR('f', CH_GET_QSET_NUM, struct ch_reg) 259 #define CHELSIO_SET_PKTSCHED _IOW('f', CH_SET_PKTSCHED, struct ch_pktsched_params) 260 #define CHELSIO_SET_HW_SCHED _IOW('f', CH_SET_HW_SCHED, struct ch_hw_sched) 261 #define CHELSIO_LOAD_BOOT _IOW('f', CH_LOAD_BOOT, struct ch_mem_range) 262 #define CHELSIO_CLEAR_STATS _IO('f', CH_CLEAR_STATS) 263 #define CHELSIO_IFCONF_GETREGS _IOWR('f', CH_IFCONF_GETREGS, struct ch_ifconf_regs) 264 #define CHELSIO_GET_MIIREG _IOWR('f', CH_GET_MIIREG, struct ch_mii_data) 265 #define CHELSIO_SET_MIIREG _IOW('f', CH_SET_MIIREG, struct ch_mii_data) 266 #define CHELSIO_GET_EEPROM _IOWR('f', CH_GET_EEPROM, struct ch_eeprom) 267 #define CHELSIO_GET_UP_LA _IOWR('f', CH_GET_UP_LA, struct ch_up_la) 268 #define CHELSIO_GET_UP_IOQS _IOWR('f', CH_GET_UP_IOQS, struct ch_up_ioqs) 269 #define CHELSIO_SET_FILTER _IOW('f', CH_SET_FILTER, struct ch_filter) 270 #define CHELSIO_DEL_FILTER _IOW('f', CH_DEL_FILTER, struct ch_filter) 271 #define CHELSIO_GET_FILTER _IOWR('f', CH_GET_FILTER, struct ch_filter) 272 #endif 273