1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011, 2016 Chelsio Communications, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 * 30 */ 31 32 #ifndef T4_MSG_H 33 #define T4_MSG_H 34 35 enum { 36 CPL_PASS_OPEN_REQ = 0x1, 37 CPL_PASS_ACCEPT_RPL = 0x2, 38 CPL_ACT_OPEN_REQ = 0x3, 39 CPL_SET_TCB = 0x4, 40 CPL_SET_TCB_FIELD = 0x5, 41 CPL_GET_TCB = 0x6, 42 CPL_CLOSE_CON_REQ = 0x8, 43 CPL_CLOSE_LISTSRV_REQ = 0x9, 44 CPL_ABORT_REQ = 0xA, 45 CPL_ABORT_RPL = 0xB, 46 CPL_TX_DATA = 0xC, 47 CPL_RX_DATA_ACK = 0xD, 48 CPL_TX_PKT = 0xE, 49 CPL_RTE_DELETE_REQ = 0xF, 50 CPL_RTE_WRITE_REQ = 0x10, 51 CPL_RTE_READ_REQ = 0x11, 52 CPL_L2T_WRITE_REQ = 0x12, 53 CPL_L2T_READ_REQ = 0x13, 54 CPL_SMT_WRITE_REQ = 0x14, 55 CPL_SMT_READ_REQ = 0x15, 56 CPL_TAG_WRITE_REQ = 0x16, 57 CPL_BARRIER = 0x18, 58 CPL_TID_RELEASE = 0x1A, 59 CPL_TAG_READ_REQ = 0x1B, 60 CPL_SRQ_TABLE_REQ = 0x1C, 61 CPL_TX_PKT_FSO = 0x1E, 62 CPL_TX_DATA_ISO = 0x1F, 63 64 CPL_CLOSE_LISTSRV_RPL = 0x20, 65 CPL_ERROR = 0x21, 66 CPL_GET_TCB_RPL = 0x22, 67 CPL_L2T_WRITE_RPL = 0x23, 68 CPL_PASS_OPEN_RPL = 0x24, 69 CPL_ACT_OPEN_RPL = 0x25, 70 CPL_PEER_CLOSE = 0x26, 71 CPL_RTE_DELETE_RPL = 0x27, 72 CPL_RTE_WRITE_RPL = 0x28, 73 CPL_RX_URG_PKT = 0x29, 74 CPL_TAG_WRITE_RPL = 0x2A, 75 CPL_ABORT_REQ_RSS = 0x2B, 76 CPL_RX_URG_NOTIFY = 0x2C, 77 CPL_ABORT_RPL_RSS = 0x2D, 78 CPL_SMT_WRITE_RPL = 0x2E, 79 CPL_TX_DATA_ACK = 0x2F, 80 81 CPL_RX_PHYS_ADDR = 0x30, 82 CPL_PCMD_READ_RPL = 0x31, 83 CPL_CLOSE_CON_RPL = 0x32, 84 CPL_ISCSI_HDR = 0x33, 85 CPL_L2T_READ_RPL = 0x34, 86 CPL_RDMA_CQE = 0x35, 87 CPL_RDMA_CQE_READ_RSP = 0x36, 88 CPL_RDMA_CQE_ERR = 0x37, 89 CPL_RTE_READ_RPL = 0x38, 90 CPL_RX_DATA = 0x39, 91 CPL_SET_TCB_RPL = 0x3A, 92 CPL_RX_PKT = 0x3B, 93 CPL_TAG_READ_RPL = 0x3C, 94 CPL_HIT_NOTIFY = 0x3D, 95 CPL_PKT_NOTIFY = 0x3E, 96 CPL_RX_DDP_COMPLETE = 0x3F, 97 98 CPL_ACT_ESTABLISH = 0x40, 99 CPL_PASS_ESTABLISH = 0x41, 100 CPL_RX_DATA_DDP = 0x42, 101 CPL_SMT_READ_RPL = 0x43, 102 CPL_PASS_ACCEPT_REQ = 0x44, 103 CPL_RX_ISCSI_CMP = 0x45, 104 CPL_RX_FCOE_DDP = 0x46, 105 CPL_FCOE_HDR = 0x47, 106 CPL_T5_TRACE_PKT = 0x48, 107 CPL_RX_ISCSI_DDP = 0x49, 108 CPL_RX_FCOE_DIF = 0x4A, 109 CPL_RX_DATA_DIF = 0x4B, 110 CPL_ERR_NOTIFY = 0x4D, 111 CPL_RX_TLS_CMP = 0x4E, 112 113 CPL_RDMA_READ_REQ = 0x60, 114 CPL_RX_ISCSI_DIF = 0x60, 115 116 CPL_SET_LE_REQ = 0x80, 117 CPL_PASS_OPEN_REQ6 = 0x81, 118 CPL_ACT_OPEN_REQ6 = 0x83, 119 CPL_TX_TLS_PDU = 0x88, 120 CPL_TX_TLS_SFO = 0x89, 121 122 CPL_TX_SEC_PDU = 0x8A, 123 CPL_TX_TLS_ACK = 0x8B, 124 125 CPL_RDMA_TERMINATE = 0xA2, 126 CPL_RDMA_WRITE = 0xA4, 127 CPL_SGE_EGR_UPDATE = 0xA5, 128 CPL_SET_LE_RPL = 0xA6, 129 CPL_FW2_MSG = 0xA7, 130 CPL_FW2_PLD = 0xA8, 131 CPL_T5_RDMA_READ_REQ = 0xA9, 132 CPL_RDMA_ATOMIC_REQ = 0xAA, 133 CPL_RDMA_ATOMIC_RPL = 0xAB, 134 CPL_RDMA_IMM_DATA = 0xAC, 135 CPL_RDMA_IMM_DATA_SE = 0xAD, 136 CPL_RX_MPS_PKT = 0xAF, 137 138 CPL_TRACE_PKT = 0xB0, 139 CPL_RX2TX_DATA = 0xB1, 140 CPL_TLS_DATA = 0xB1, 141 CPL_ISCSI_DATA = 0xB2, 142 CPL_FCOE_DATA = 0xB3, 143 144 CPL_FW4_MSG = 0xC0, 145 CPL_FW4_PLD = 0xC1, 146 CPL_FW4_ACK = 0xC3, 147 CPL_SRQ_TABLE_RPL = 0xCC, 148 CPL_RX_PHYS_DSGL = 0xD0, 149 150 CPL_FW6_MSG = 0xE0, 151 CPL_FW6_PLD = 0xE1, 152 CPL_TX_TNL_LSO = 0xEC, 153 CPL_TX_PKT_LSO = 0xED, 154 CPL_TX_PKT_XT = 0xEE, 155 156 NUM_CPL_CMDS /* must be last and previous entries must be sorted */ 157 }; 158 159 enum CPL_error { 160 CPL_ERR_NONE = 0, 161 CPL_ERR_TCAM_PARITY = 1, 162 CPL_ERR_TCAM_MISS = 2, 163 CPL_ERR_TCAM_FULL = 3, 164 CPL_ERR_BAD_LENGTH = 15, 165 CPL_ERR_BAD_ROUTE = 18, 166 CPL_ERR_CONN_RESET = 20, 167 CPL_ERR_CONN_EXIST_SYNRECV = 21, 168 CPL_ERR_CONN_EXIST = 22, 169 CPL_ERR_ARP_MISS = 23, 170 CPL_ERR_BAD_SYN = 24, 171 CPL_ERR_CONN_TIMEDOUT = 30, 172 CPL_ERR_XMIT_TIMEDOUT = 31, 173 CPL_ERR_PERSIST_TIMEDOUT = 32, 174 CPL_ERR_FINWAIT2_TIMEDOUT = 33, 175 CPL_ERR_KEEPALIVE_TIMEDOUT = 34, 176 CPL_ERR_RTX_NEG_ADVICE = 35, 177 CPL_ERR_PERSIST_NEG_ADVICE = 36, 178 CPL_ERR_KEEPALV_NEG_ADVICE = 37, 179 CPL_ERR_WAIT_ARP_RPL = 41, 180 CPL_ERR_ABORT_FAILED = 42, 181 CPL_ERR_IWARP_FLM = 50, 182 CPL_CONTAINS_READ_RPL = 60, 183 CPL_CONTAINS_WRITE_RPL = 61, 184 }; 185 186 /* 187 * Some of the error codes above implicitly indicate that there is no TID 188 * allocated with the result of an ACT_OPEN. We use this predicate to make 189 * that explicit. 190 */ 191 static inline int act_open_has_tid(int status) 192 { 193 return (status != CPL_ERR_TCAM_PARITY && 194 status != CPL_ERR_TCAM_MISS && 195 status != CPL_ERR_TCAM_FULL && 196 status != CPL_ERR_CONN_EXIST_SYNRECV && 197 status != CPL_ERR_CONN_EXIST); 198 } 199 200 /* 201 * Convert an ACT_OPEN_RPL status to an errno. 202 */ 203 static inline int 204 act_open_rpl_status_to_errno(int status) 205 { 206 207 switch (status) { 208 case CPL_ERR_CONN_RESET: 209 return (ECONNREFUSED); 210 case CPL_ERR_ARP_MISS: 211 return (EHOSTUNREACH); 212 case CPL_ERR_CONN_TIMEDOUT: 213 return (ETIMEDOUT); 214 case CPL_ERR_TCAM_FULL: 215 return (EAGAIN); 216 case CPL_ERR_CONN_EXIST: 217 return (EAGAIN); 218 default: 219 return (EIO); 220 } 221 } 222 223 224 enum { 225 CPL_CONN_POLICY_AUTO = 0, 226 CPL_CONN_POLICY_ASK = 1, 227 CPL_CONN_POLICY_FILTER = 2, 228 CPL_CONN_POLICY_DENY = 3 229 }; 230 231 enum { 232 ULP_MODE_NONE = 0, 233 ULP_MODE_ISCSI = 2, 234 ULP_MODE_RDMA = 4, 235 ULP_MODE_TCPDDP = 5, 236 ULP_MODE_FCOE = 6, 237 ULP_MODE_TLS = 8, 238 }; 239 240 enum { 241 ULP_CRC_HEADER = 1 << 0, 242 ULP_CRC_DATA = 1 << 1 243 }; 244 245 enum { 246 CPL_PASS_OPEN_ACCEPT, 247 CPL_PASS_OPEN_REJECT, 248 CPL_PASS_OPEN_ACCEPT_TNL 249 }; 250 251 enum { 252 CPL_ABORT_SEND_RST = 0, 253 CPL_ABORT_NO_RST, 254 }; 255 256 enum { /* TX_PKT_XT checksum types */ 257 TX_CSUM_TCP = 0, 258 TX_CSUM_UDP = 1, 259 TX_CSUM_CRC16 = 4, 260 TX_CSUM_CRC32 = 5, 261 TX_CSUM_CRC32C = 6, 262 TX_CSUM_FCOE = 7, 263 TX_CSUM_TCPIP = 8, 264 TX_CSUM_UDPIP = 9, 265 TX_CSUM_TCPIP6 = 10, 266 TX_CSUM_UDPIP6 = 11, 267 TX_CSUM_IP = 12, 268 }; 269 270 enum { /* packet type in CPL_RX_PKT */ 271 PKTYPE_XACT_UCAST = 0, 272 PKTYPE_HASH_UCAST = 1, 273 PKTYPE_XACT_MCAST = 2, 274 PKTYPE_HASH_MCAST = 3, 275 PKTYPE_PROMISC = 4, 276 PKTYPE_HPROMISC = 5, 277 PKTYPE_BCAST = 6 278 }; 279 280 enum { /* DMAC type in CPL_RX_PKT */ 281 DATYPE_UCAST, 282 DATYPE_MCAST, 283 DATYPE_BCAST 284 }; 285 286 enum { /* TCP congestion control algorithms */ 287 CONG_ALG_RENO, 288 CONG_ALG_TAHOE, 289 CONG_ALG_NEWRENO, 290 CONG_ALG_HIGHSPEED 291 }; 292 293 enum { /* RSS hash type */ 294 RSS_HASH_NONE = 0, /* no hash computed */ 295 RSS_HASH_IP = 1, /* IP or IPv6 2-tuple hash */ 296 RSS_HASH_TCP = 2, /* TCP 4-tuple hash */ 297 RSS_HASH_UDP = 3 /* UDP 4-tuple hash */ 298 }; 299 300 enum { /* LE commands */ 301 LE_CMD_READ = 0x4, 302 LE_CMD_WRITE = 0xb 303 }; 304 305 enum { /* LE request size */ 306 LE_SZ_NONE = 0, 307 LE_SZ_33 = 1, 308 LE_SZ_66 = 2, 309 LE_SZ_132 = 3, 310 LE_SZ_264 = 4, 311 LE_SZ_528 = 5 312 }; 313 314 union opcode_tid { 315 __be32 opcode_tid; 316 __u8 opcode; 317 }; 318 319 #define S_CPL_OPCODE 24 320 #define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE) 321 #define G_CPL_OPCODE(x) (((x) >> S_CPL_OPCODE) & 0xFF) 322 #define G_TID(x) ((x) & 0xFFFFFF) 323 324 /* tid is assumed to be 24-bits */ 325 #define MK_OPCODE_TID(opcode, tid) (V_CPL_OPCODE(opcode) | (tid)) 326 327 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) 328 329 /* extract the TID from a CPL command */ 330 #define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd)))) 331 #define GET_OPCODE(cmd) ((cmd)->ot.opcode) 332 333 /* partitioning of TID fields that also carry a queue id */ 334 #define S_TID_TID 0 335 #define M_TID_TID 0x7ff 336 #define V_TID_TID(x) ((x) << S_TID_TID) 337 #define G_TID_TID(x) (((x) >> S_TID_TID) & M_TID_TID) 338 339 #define S_TID_COOKIE 11 340 #define M_TID_COOKIE 0x7 341 #define V_TID_COOKIE(x) ((x) << S_TID_COOKIE) 342 #define G_TID_COOKIE(x) (((x) >> S_TID_COOKIE) & M_TID_COOKIE) 343 344 #define S_TID_QID 14 345 #define M_TID_QID 0x3ff 346 #define V_TID_QID(x) ((x) << S_TID_QID) 347 #define G_TID_QID(x) (((x) >> S_TID_QID) & M_TID_QID) 348 349 union opcode_info { 350 __be64 opcode_info; 351 __u8 opcode; 352 }; 353 354 struct tcp_options { 355 __be16 mss; 356 __u8 wsf; 357 #if defined(__LITTLE_ENDIAN_BITFIELD) 358 __u8 :4; 359 __u8 unknown:1; 360 __u8 ecn:1; 361 __u8 sack:1; 362 __u8 tstamp:1; 363 #else 364 __u8 tstamp:1; 365 __u8 sack:1; 366 __u8 ecn:1; 367 __u8 unknown:1; 368 __u8 :4; 369 #endif 370 }; 371 372 struct rss_header { 373 __u8 opcode; 374 #if defined(__LITTLE_ENDIAN_BITFIELD) 375 __u8 channel:2; 376 __u8 filter_hit:1; 377 __u8 filter_tid:1; 378 __u8 hash_type:2; 379 __u8 ipv6:1; 380 __u8 send2fw:1; 381 #else 382 __u8 send2fw:1; 383 __u8 ipv6:1; 384 __u8 hash_type:2; 385 __u8 filter_tid:1; 386 __u8 filter_hit:1; 387 __u8 channel:2; 388 #endif 389 __be16 qid; 390 __be32 hash_val; 391 }; 392 393 #define S_HASHTYPE 20 394 #define M_HASHTYPE 0x3 395 #define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE) 396 397 #define S_QNUM 0 398 #define M_QNUM 0xFFFF 399 #define G_QNUM(x) (((x) >> S_QNUM) & M_QNUM) 400 401 #if defined(RSS_HDR_VLD) || defined(CHELSIO_FW) 402 # define RSS_HDR struct rss_header rss_hdr; 403 #else 404 # define RSS_HDR 405 #endif 406 407 #ifndef CHELSIO_FW 408 struct work_request_hdr { 409 __be32 wr_hi; 410 __be32 wr_mid; 411 __be64 wr_lo; 412 }; 413 414 /* wr_mid fields */ 415 #define S_WR_LEN16 0 416 #define M_WR_LEN16 0xFF 417 #define V_WR_LEN16(x) ((x) << S_WR_LEN16) 418 #define G_WR_LEN16(x) (((x) >> S_WR_LEN16) & M_WR_LEN16) 419 420 /* wr_hi fields */ 421 #define S_WR_OP 24 422 #define M_WR_OP 0xFF 423 #define V_WR_OP(x) ((__u64)(x) << S_WR_OP) 424 #define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP) 425 426 # define WR_HDR struct work_request_hdr wr 427 # define WR_HDR_SIZE sizeof(struct work_request_hdr) 428 #else 429 # define WR_HDR 430 # define WR_HDR_SIZE 0 431 #endif 432 433 /* option 0 fields */ 434 #define S_ACCEPT_MODE 0 435 #define M_ACCEPT_MODE 0x3 436 #define V_ACCEPT_MODE(x) ((x) << S_ACCEPT_MODE) 437 #define G_ACCEPT_MODE(x) (((x) >> S_ACCEPT_MODE) & M_ACCEPT_MODE) 438 439 #define S_TX_CHAN 2 440 #define M_TX_CHAN 0x3 441 #define V_TX_CHAN(x) ((x) << S_TX_CHAN) 442 #define G_TX_CHAN(x) (((x) >> S_TX_CHAN) & M_TX_CHAN) 443 444 #define S_NO_CONG 4 445 #define V_NO_CONG(x) ((x) << S_NO_CONG) 446 #define F_NO_CONG V_NO_CONG(1U) 447 448 #define S_DELACK 5 449 #define V_DELACK(x) ((x) << S_DELACK) 450 #define F_DELACK V_DELACK(1U) 451 452 #define S_INJECT_TIMER 6 453 #define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER) 454 #define F_INJECT_TIMER V_INJECT_TIMER(1U) 455 456 #define S_NON_OFFLOAD 7 457 #define V_NON_OFFLOAD(x) ((x) << S_NON_OFFLOAD) 458 #define F_NON_OFFLOAD V_NON_OFFLOAD(1U) 459 460 #define S_ULP_MODE 8 461 #define M_ULP_MODE 0xF 462 #define V_ULP_MODE(x) ((x) << S_ULP_MODE) 463 #define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE) 464 465 #define S_RCV_BUFSIZ 12 466 #define M_RCV_BUFSIZ 0x3FFU 467 #define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ) 468 #define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ) 469 470 #define S_DSCP 22 471 #define M_DSCP 0x3F 472 #define V_DSCP(x) ((x) << S_DSCP) 473 #define G_DSCP(x) (((x) >> S_DSCP) & M_DSCP) 474 475 #define S_SMAC_SEL 28 476 #define M_SMAC_SEL 0xFF 477 #define V_SMAC_SEL(x) ((__u64)(x) << S_SMAC_SEL) 478 #define G_SMAC_SEL(x) (((x) >> S_SMAC_SEL) & M_SMAC_SEL) 479 480 #define S_L2T_IDX 36 481 #define M_L2T_IDX 0xFFF 482 #define V_L2T_IDX(x) ((__u64)(x) << S_L2T_IDX) 483 #define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX) 484 485 #define S_TCAM_BYPASS 48 486 #define V_TCAM_BYPASS(x) ((__u64)(x) << S_TCAM_BYPASS) 487 #define F_TCAM_BYPASS V_TCAM_BYPASS(1ULL) 488 489 #define S_NAGLE 49 490 #define V_NAGLE(x) ((__u64)(x) << S_NAGLE) 491 #define F_NAGLE V_NAGLE(1ULL) 492 493 #define S_WND_SCALE 50 494 #define M_WND_SCALE 0xF 495 #define V_WND_SCALE(x) ((__u64)(x) << S_WND_SCALE) 496 #define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE) 497 498 #define S_KEEP_ALIVE 54 499 #define V_KEEP_ALIVE(x) ((__u64)(x) << S_KEEP_ALIVE) 500 #define F_KEEP_ALIVE V_KEEP_ALIVE(1ULL) 501 502 #define S_MAX_RT 55 503 #define M_MAX_RT 0xF 504 #define V_MAX_RT(x) ((__u64)(x) << S_MAX_RT) 505 #define G_MAX_RT(x) (((x) >> S_MAX_RT) & M_MAX_RT) 506 507 #define S_MAX_RT_OVERRIDE 59 508 #define V_MAX_RT_OVERRIDE(x) ((__u64)(x) << S_MAX_RT_OVERRIDE) 509 #define F_MAX_RT_OVERRIDE V_MAX_RT_OVERRIDE(1ULL) 510 511 #define S_MSS_IDX 60 512 #define M_MSS_IDX 0xF 513 #define V_MSS_IDX(x) ((__u64)(x) << S_MSS_IDX) 514 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX) 515 516 /* option 1 fields */ 517 #define S_SYN_RSS_ENABLE 0 518 #define V_SYN_RSS_ENABLE(x) ((x) << S_SYN_RSS_ENABLE) 519 #define F_SYN_RSS_ENABLE V_SYN_RSS_ENABLE(1U) 520 521 #define S_SYN_RSS_USE_HASH 1 522 #define V_SYN_RSS_USE_HASH(x) ((x) << S_SYN_RSS_USE_HASH) 523 #define F_SYN_RSS_USE_HASH V_SYN_RSS_USE_HASH(1U) 524 525 #define S_SYN_RSS_QUEUE 2 526 #define M_SYN_RSS_QUEUE 0x3FF 527 #define V_SYN_RSS_QUEUE(x) ((x) << S_SYN_RSS_QUEUE) 528 #define G_SYN_RSS_QUEUE(x) (((x) >> S_SYN_RSS_QUEUE) & M_SYN_RSS_QUEUE) 529 530 #define S_LISTEN_INTF 12 531 #define M_LISTEN_INTF 0xFF 532 #define V_LISTEN_INTF(x) ((x) << S_LISTEN_INTF) 533 #define G_LISTEN_INTF(x) (((x) >> S_LISTEN_INTF) & M_LISTEN_INTF) 534 535 #define S_LISTEN_FILTER 20 536 #define V_LISTEN_FILTER(x) ((x) << S_LISTEN_FILTER) 537 #define F_LISTEN_FILTER V_LISTEN_FILTER(1U) 538 539 #define S_SYN_DEFENSE 21 540 #define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE) 541 #define F_SYN_DEFENSE V_SYN_DEFENSE(1U) 542 543 #define S_CONN_POLICY 22 544 #define M_CONN_POLICY 0x3 545 #define V_CONN_POLICY(x) ((x) << S_CONN_POLICY) 546 #define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY) 547 548 #define S_T5_FILT_INFO 24 549 #define M_T5_FILT_INFO 0xffffffffffULL 550 #define V_T5_FILT_INFO(x) ((x) << S_T5_FILT_INFO) 551 #define G_T5_FILT_INFO(x) (((x) >> S_T5_FILT_INFO) & M_T5_FILT_INFO) 552 553 #define S_FILT_INFO 28 554 #define M_FILT_INFO 0xfffffffffULL 555 #define V_FILT_INFO(x) ((x) << S_FILT_INFO) 556 #define G_FILT_INFO(x) (((x) >> S_FILT_INFO) & M_FILT_INFO) 557 558 /* option 2 fields */ 559 #define S_RSS_QUEUE 0 560 #define M_RSS_QUEUE 0x3FF 561 #define V_RSS_QUEUE(x) ((x) << S_RSS_QUEUE) 562 #define G_RSS_QUEUE(x) (((x) >> S_RSS_QUEUE) & M_RSS_QUEUE) 563 564 #define S_RSS_QUEUE_VALID 10 565 #define V_RSS_QUEUE_VALID(x) ((x) << S_RSS_QUEUE_VALID) 566 #define F_RSS_QUEUE_VALID V_RSS_QUEUE_VALID(1U) 567 568 #define S_RX_COALESCE_VALID 11 569 #define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID) 570 #define F_RX_COALESCE_VALID V_RX_COALESCE_VALID(1U) 571 572 #define S_RX_COALESCE 12 573 #define M_RX_COALESCE 0x3 574 #define V_RX_COALESCE(x) ((x) << S_RX_COALESCE) 575 #define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE) 576 577 #define S_CONG_CNTRL 14 578 #define M_CONG_CNTRL 0x3 579 #define V_CONG_CNTRL(x) ((x) << S_CONG_CNTRL) 580 #define G_CONG_CNTRL(x) (((x) >> S_CONG_CNTRL) & M_CONG_CNTRL) 581 582 #define S_PACE 16 583 #define M_PACE 0x3 584 #define V_PACE(x) ((x) << S_PACE) 585 #define G_PACE(x) (((x) >> S_PACE) & M_PACE) 586 587 #define S_CONG_CNTRL_VALID 18 588 #define V_CONG_CNTRL_VALID(x) ((x) << S_CONG_CNTRL_VALID) 589 #define F_CONG_CNTRL_VALID V_CONG_CNTRL_VALID(1U) 590 591 #define S_T5_ISS 18 592 #define V_T5_ISS(x) ((x) << S_T5_ISS) 593 #define F_T5_ISS V_T5_ISS(1U) 594 595 #define S_PACE_VALID 19 596 #define V_PACE_VALID(x) ((x) << S_PACE_VALID) 597 #define F_PACE_VALID V_PACE_VALID(1U) 598 599 #define S_RX_FC_DISABLE 20 600 #define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE) 601 #define F_RX_FC_DISABLE V_RX_FC_DISABLE(1U) 602 603 #define S_RX_FC_DDP 21 604 #define V_RX_FC_DDP(x) ((x) << S_RX_FC_DDP) 605 #define F_RX_FC_DDP V_RX_FC_DDP(1U) 606 607 #define S_RX_FC_VALID 22 608 #define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID) 609 #define F_RX_FC_VALID V_RX_FC_VALID(1U) 610 611 #define S_TX_QUEUE 23 612 #define M_TX_QUEUE 0x7 613 #define V_TX_QUEUE(x) ((x) << S_TX_QUEUE) 614 #define G_TX_QUEUE(x) (((x) >> S_TX_QUEUE) & M_TX_QUEUE) 615 616 #define S_RX_CHANNEL 26 617 #define V_RX_CHANNEL(x) ((x) << S_RX_CHANNEL) 618 #define F_RX_CHANNEL V_RX_CHANNEL(1U) 619 620 #define S_CCTRL_ECN 27 621 #define V_CCTRL_ECN(x) ((x) << S_CCTRL_ECN) 622 #define F_CCTRL_ECN V_CCTRL_ECN(1U) 623 624 #define S_WND_SCALE_EN 28 625 #define V_WND_SCALE_EN(x) ((x) << S_WND_SCALE_EN) 626 #define F_WND_SCALE_EN V_WND_SCALE_EN(1U) 627 628 #define S_TSTAMPS_EN 29 629 #define V_TSTAMPS_EN(x) ((x) << S_TSTAMPS_EN) 630 #define F_TSTAMPS_EN V_TSTAMPS_EN(1U) 631 632 #define S_SACK_EN 30 633 #define V_SACK_EN(x) ((x) << S_SACK_EN) 634 #define F_SACK_EN V_SACK_EN(1U) 635 636 #define S_T5_OPT_2_VALID 31 637 #define V_T5_OPT_2_VALID(x) ((x) << S_T5_OPT_2_VALID) 638 #define F_T5_OPT_2_VALID V_T5_OPT_2_VALID(1U) 639 640 struct cpl_pass_open_req { 641 WR_HDR; 642 union opcode_tid ot; 643 __be16 local_port; 644 __be16 peer_port; 645 __be32 local_ip; 646 __be32 peer_ip; 647 __be64 opt0; 648 __be64 opt1; 649 }; 650 651 struct cpl_pass_open_req6 { 652 WR_HDR; 653 union opcode_tid ot; 654 __be16 local_port; 655 __be16 peer_port; 656 __be64 local_ip_hi; 657 __be64 local_ip_lo; 658 __be64 peer_ip_hi; 659 __be64 peer_ip_lo; 660 __be64 opt0; 661 __be64 opt1; 662 }; 663 664 struct cpl_pass_open_rpl { 665 RSS_HDR 666 union opcode_tid ot; 667 __u8 rsvd[3]; 668 __u8 status; 669 }; 670 671 struct cpl_pass_establish { 672 RSS_HDR 673 union opcode_tid ot; 674 __be32 rsvd; 675 __be32 tos_stid; 676 __be16 mac_idx; 677 __be16 tcp_opt; 678 __be32 snd_isn; 679 __be32 rcv_isn; 680 }; 681 682 /* cpl_pass_establish.tos_stid fields */ 683 #define S_PASS_OPEN_TID 0 684 #define M_PASS_OPEN_TID 0xFFFFFF 685 #define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID) 686 #define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID) 687 688 #define S_PASS_OPEN_TOS 24 689 #define M_PASS_OPEN_TOS 0xFF 690 #define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS) 691 #define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS) 692 693 /* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */ 694 #define S_TCPOPT_WSCALE_OK 5 695 #define M_TCPOPT_WSCALE_OK 0x1 696 #define V_TCPOPT_WSCALE_OK(x) ((x) << S_TCPOPT_WSCALE_OK) 697 #define G_TCPOPT_WSCALE_OK(x) (((x) >> S_TCPOPT_WSCALE_OK) & M_TCPOPT_WSCALE_OK) 698 699 #define S_TCPOPT_SACK 6 700 #define M_TCPOPT_SACK 0x1 701 #define V_TCPOPT_SACK(x) ((x) << S_TCPOPT_SACK) 702 #define G_TCPOPT_SACK(x) (((x) >> S_TCPOPT_SACK) & M_TCPOPT_SACK) 703 704 #define S_TCPOPT_TSTAMP 7 705 #define M_TCPOPT_TSTAMP 0x1 706 #define V_TCPOPT_TSTAMP(x) ((x) << S_TCPOPT_TSTAMP) 707 #define G_TCPOPT_TSTAMP(x) (((x) >> S_TCPOPT_TSTAMP) & M_TCPOPT_TSTAMP) 708 709 #define S_TCPOPT_SND_WSCALE 8 710 #define M_TCPOPT_SND_WSCALE 0xF 711 #define V_TCPOPT_SND_WSCALE(x) ((x) << S_TCPOPT_SND_WSCALE) 712 #define G_TCPOPT_SND_WSCALE(x) (((x) >> S_TCPOPT_SND_WSCALE) & M_TCPOPT_SND_WSCALE) 713 714 #define S_TCPOPT_MSS 12 715 #define M_TCPOPT_MSS 0xF 716 #define V_TCPOPT_MSS(x) ((x) << S_TCPOPT_MSS) 717 #define G_TCPOPT_MSS(x) (((x) >> S_TCPOPT_MSS) & M_TCPOPT_MSS) 718 719 struct cpl_pass_accept_req { 720 RSS_HDR 721 union opcode_tid ot; 722 __be16 rsvd; 723 __be16 len; 724 __be32 hdr_len; 725 __be16 vlan; 726 __be16 l2info; 727 __be32 tos_stid; 728 struct tcp_options tcpopt; 729 }; 730 731 /* cpl_pass_accept_req.hdr_len fields */ 732 #define S_SYN_RX_CHAN 0 733 #define M_SYN_RX_CHAN 0xF 734 #define V_SYN_RX_CHAN(x) ((x) << S_SYN_RX_CHAN) 735 #define G_SYN_RX_CHAN(x) (((x) >> S_SYN_RX_CHAN) & M_SYN_RX_CHAN) 736 737 #define S_TCP_HDR_LEN 10 738 #define M_TCP_HDR_LEN 0x3F 739 #define V_TCP_HDR_LEN(x) ((x) << S_TCP_HDR_LEN) 740 #define G_TCP_HDR_LEN(x) (((x) >> S_TCP_HDR_LEN) & M_TCP_HDR_LEN) 741 742 #define S_T6_TCP_HDR_LEN 8 743 #define V_T6_TCP_HDR_LEN(x) ((x) << S_T6_TCP_HDR_LEN) 744 #define G_T6_TCP_HDR_LEN(x) (((x) >> S_T6_TCP_HDR_LEN) & M_TCP_HDR_LEN) 745 746 #define S_IP_HDR_LEN 16 747 #define M_IP_HDR_LEN 0x3FF 748 #define V_IP_HDR_LEN(x) ((x) << S_IP_HDR_LEN) 749 #define G_IP_HDR_LEN(x) (((x) >> S_IP_HDR_LEN) & M_IP_HDR_LEN) 750 751 #define S_T6_IP_HDR_LEN 14 752 #define V_T6_IP_HDR_LEN(x) ((x) << S_T6_IP_HDR_LEN) 753 #define G_T6_IP_HDR_LEN(x) (((x) >> S_T6_IP_HDR_LEN) & M_IP_HDR_LEN) 754 755 #define S_ETH_HDR_LEN 26 756 #define M_ETH_HDR_LEN 0x3F 757 #define V_ETH_HDR_LEN(x) ((x) << S_ETH_HDR_LEN) 758 #define G_ETH_HDR_LEN(x) (((x) >> S_ETH_HDR_LEN) & M_ETH_HDR_LEN) 759 760 #define S_T6_ETH_HDR_LEN 24 761 #define M_T6_ETH_HDR_LEN 0xFF 762 #define V_T6_ETH_HDR_LEN(x) ((x) << S_T6_ETH_HDR_LEN) 763 #define G_T6_ETH_HDR_LEN(x) (((x) >> S_T6_ETH_HDR_LEN) & M_T6_ETH_HDR_LEN) 764 765 /* cpl_pass_accept_req.l2info fields */ 766 #define S_SYN_MAC_IDX 0 767 #define M_SYN_MAC_IDX 0x1FF 768 #define V_SYN_MAC_IDX(x) ((x) << S_SYN_MAC_IDX) 769 #define G_SYN_MAC_IDX(x) (((x) >> S_SYN_MAC_IDX) & M_SYN_MAC_IDX) 770 771 #define S_SYN_XACT_MATCH 9 772 #define V_SYN_XACT_MATCH(x) ((x) << S_SYN_XACT_MATCH) 773 #define F_SYN_XACT_MATCH V_SYN_XACT_MATCH(1U) 774 775 #define S_SYN_INTF 12 776 #define M_SYN_INTF 0xF 777 #define V_SYN_INTF(x) ((x) << S_SYN_INTF) 778 #define G_SYN_INTF(x) (((x) >> S_SYN_INTF) & M_SYN_INTF) 779 780 struct cpl_pass_accept_rpl { 781 WR_HDR; 782 union opcode_tid ot; 783 __be32 opt2; 784 __be64 opt0; 785 }; 786 787 struct cpl_t5_pass_accept_rpl { 788 WR_HDR; 789 union opcode_tid ot; 790 __be32 opt2; 791 __be64 opt0; 792 __be32 iss; 793 union { 794 __be32 rsvd; /* T5 */ 795 __be32 opt3; /* T6 */ 796 } u; 797 }; 798 799 struct cpl_act_open_req { 800 WR_HDR; 801 union opcode_tid ot; 802 __be16 local_port; 803 __be16 peer_port; 804 __be32 local_ip; 805 __be32 peer_ip; 806 __be64 opt0; 807 __be32 params; 808 __be32 opt2; 809 }; 810 811 #define S_FILTER_TUPLE 24 812 #define M_FILTER_TUPLE 0xFFFFFFFFFF 813 #define V_FILTER_TUPLE(x) ((x) << S_FILTER_TUPLE) 814 #define G_FILTER_TUPLE(x) (((x) >> S_FILTER_TUPLE) & M_FILTER_TUPLE) 815 struct cpl_t5_act_open_req { 816 WR_HDR; 817 union opcode_tid ot; 818 __be16 local_port; 819 __be16 peer_port; 820 __be32 local_ip; 821 __be32 peer_ip; 822 __be64 opt0; 823 __be32 iss; 824 __be32 opt2; 825 __be64 params; 826 }; 827 828 struct cpl_t6_act_open_req { 829 WR_HDR; 830 union opcode_tid ot; 831 __be16 local_port; 832 __be16 peer_port; 833 __be32 local_ip; 834 __be32 peer_ip; 835 __be64 opt0; 836 __be32 iss; 837 __be32 opt2; 838 __be64 params; 839 __be32 rsvd2; 840 __be32 opt3; 841 }; 842 843 /* cpl_{t5,t6}_act_open_req.params field */ 844 #define S_AOPEN_FCOEMASK 0 845 #define V_AOPEN_FCOEMASK(x) ((x) << S_AOPEN_FCOEMASK) 846 #define F_AOPEN_FCOEMASK V_AOPEN_FCOEMASK(1U) 847 848 struct cpl_act_open_req6 { 849 WR_HDR; 850 union opcode_tid ot; 851 __be16 local_port; 852 __be16 peer_port; 853 __be64 local_ip_hi; 854 __be64 local_ip_lo; 855 __be64 peer_ip_hi; 856 __be64 peer_ip_lo; 857 __be64 opt0; 858 __be32 params; 859 __be32 opt2; 860 }; 861 862 struct cpl_t5_act_open_req6 { 863 WR_HDR; 864 union opcode_tid ot; 865 __be16 local_port; 866 __be16 peer_port; 867 __be64 local_ip_hi; 868 __be64 local_ip_lo; 869 __be64 peer_ip_hi; 870 __be64 peer_ip_lo; 871 __be64 opt0; 872 __be32 iss; 873 __be32 opt2; 874 __be64 params; 875 }; 876 877 struct cpl_t6_act_open_req6 { 878 WR_HDR; 879 union opcode_tid ot; 880 __be16 local_port; 881 __be16 peer_port; 882 __be64 local_ip_hi; 883 __be64 local_ip_lo; 884 __be64 peer_ip_hi; 885 __be64 peer_ip_lo; 886 __be64 opt0; 887 __be32 iss; 888 __be32 opt2; 889 __be64 params; 890 __be32 rsvd2; 891 __be32 opt3; 892 }; 893 894 struct cpl_act_open_rpl { 895 RSS_HDR 896 union opcode_tid ot; 897 __be32 atid_status; 898 }; 899 900 /* cpl_act_open_rpl.atid_status fields */ 901 #define S_AOPEN_STATUS 0 902 #define M_AOPEN_STATUS 0xFF 903 #define V_AOPEN_STATUS(x) ((x) << S_AOPEN_STATUS) 904 #define G_AOPEN_STATUS(x) (((x) >> S_AOPEN_STATUS) & M_AOPEN_STATUS) 905 906 #define S_AOPEN_ATID 8 907 #define M_AOPEN_ATID 0xFFFFFF 908 #define V_AOPEN_ATID(x) ((x) << S_AOPEN_ATID) 909 #define G_AOPEN_ATID(x) (((x) >> S_AOPEN_ATID) & M_AOPEN_ATID) 910 911 struct cpl_act_establish { 912 RSS_HDR 913 union opcode_tid ot; 914 __be32 rsvd; 915 __be32 tos_atid; 916 __be16 mac_idx; 917 __be16 tcp_opt; 918 __be32 snd_isn; 919 __be32 rcv_isn; 920 }; 921 922 struct cpl_get_tcb { 923 WR_HDR; 924 union opcode_tid ot; 925 __be16 reply_ctrl; 926 __be16 cookie; 927 }; 928 929 /* cpl_get_tcb.reply_ctrl fields */ 930 #define S_QUEUENO 0 931 #define M_QUEUENO 0x3FF 932 #define V_QUEUENO(x) ((x) << S_QUEUENO) 933 #define G_QUEUENO(x) (((x) >> S_QUEUENO) & M_QUEUENO) 934 935 #define S_REPLY_CHAN 14 936 #define V_REPLY_CHAN(x) ((x) << S_REPLY_CHAN) 937 #define F_REPLY_CHAN V_REPLY_CHAN(1U) 938 939 #define S_NO_REPLY 15 940 #define V_NO_REPLY(x) ((x) << S_NO_REPLY) 941 #define F_NO_REPLY V_NO_REPLY(1U) 942 943 struct cpl_get_tcb_rpl { 944 RSS_HDR 945 union opcode_tid ot; 946 __u8 cookie; 947 __u8 status; 948 __be16 len; 949 }; 950 951 struct cpl_set_tcb { 952 WR_HDR; 953 union opcode_tid ot; 954 __be16 reply_ctrl; 955 __be16 cookie; 956 }; 957 958 struct cpl_set_tcb_field { 959 WR_HDR; 960 union opcode_tid ot; 961 __be16 reply_ctrl; 962 __be16 word_cookie; 963 __be64 mask; 964 __be64 val; 965 }; 966 967 struct cpl_set_tcb_field_core { 968 union opcode_tid ot; 969 __be16 reply_ctrl; 970 __be16 word_cookie; 971 __be64 mask; 972 __be64 val; 973 }; 974 975 /* cpl_set_tcb_field.word_cookie fields */ 976 #define S_WORD 0 977 #define M_WORD 0x1F 978 #define V_WORD(x) ((x) << S_WORD) 979 #define G_WORD(x) (((x) >> S_WORD) & M_WORD) 980 981 #define S_COOKIE 5 982 #define M_COOKIE 0x7 983 #define V_COOKIE(x) ((x) << S_COOKIE) 984 #define G_COOKIE(x) (((x) >> S_COOKIE) & M_COOKIE) 985 986 struct cpl_set_tcb_rpl { 987 RSS_HDR 988 union opcode_tid ot; 989 __be16 rsvd; 990 __u8 cookie; 991 __u8 status; 992 __be64 oldval; 993 }; 994 995 struct cpl_close_con_req { 996 WR_HDR; 997 union opcode_tid ot; 998 __be32 rsvd; 999 }; 1000 1001 struct cpl_close_con_rpl { 1002 RSS_HDR 1003 union opcode_tid ot; 1004 __u8 rsvd[3]; 1005 __u8 status; 1006 __be32 snd_nxt; 1007 __be32 rcv_nxt; 1008 }; 1009 1010 struct cpl_close_listsvr_req { 1011 WR_HDR; 1012 union opcode_tid ot; 1013 __be16 reply_ctrl; 1014 __be16 rsvd; 1015 }; 1016 1017 /* additional cpl_close_listsvr_req.reply_ctrl field */ 1018 #define S_LISTSVR_IPV6 14 1019 #define V_LISTSVR_IPV6(x) ((x) << S_LISTSVR_IPV6) 1020 #define F_LISTSVR_IPV6 V_LISTSVR_IPV6(1U) 1021 1022 struct cpl_close_listsvr_rpl { 1023 RSS_HDR 1024 union opcode_tid ot; 1025 __u8 rsvd[3]; 1026 __u8 status; 1027 }; 1028 1029 struct cpl_abort_req_rss { 1030 RSS_HDR 1031 union opcode_tid ot; 1032 __u8 rsvd[3]; 1033 __u8 status; 1034 }; 1035 1036 struct cpl_abort_req_rss6 { 1037 RSS_HDR 1038 union opcode_tid ot; 1039 __u32 srqidx_status; 1040 }; 1041 1042 #define S_ABORT_RSS_STATUS 0 1043 #define M_ABORT_RSS_STATUS 0xff 1044 #define V_ABORT_RSS_STATUS(x) ((x) << S_ABORT_RSS_STATUS) 1045 #define G_ABORT_RSS_STATUS(x) (((x) >> S_ABORT_RSS_STATUS) & M_ABORT_RSS_STATUS) 1046 1047 #define S_ABORT_RSS_SRQIDX 8 1048 #define M_ABORT_RSS_SRQIDX 0xffffff 1049 #define V_ABORT_RSS_SRQIDX(x) ((x) << S_ABORT_RSS_SRQIDX) 1050 #define G_ABORT_RSS_SRQIDX(x) (((x) >> S_ABORT_RSS_SRQIDX) & M_ABORT_RSS_SRQIDX) 1051 1052 1053 /* cpl_abort_req status command code in case of T6, 1054 * bit[0] specifies whether to send RST (0) to remote peer or suppress it (1) 1055 * bit[1] indicates ABORT_REQ was sent after a CLOSE_CON_REQ 1056 * bit[2] specifies whether to disable the mmgr (1) or not (0) 1057 */ 1058 struct cpl_abort_req { 1059 WR_HDR; 1060 union opcode_tid ot; 1061 __be32 rsvd0; 1062 __u8 rsvd1; 1063 __u8 cmd; 1064 __u8 rsvd2[6]; 1065 }; 1066 1067 struct cpl_abort_req_core { 1068 union opcode_tid ot; 1069 __be32 rsvd0; 1070 __u8 rsvd1; 1071 __u8 cmd; 1072 __u8 rsvd2[6]; 1073 }; 1074 1075 struct cpl_abort_rpl_rss { 1076 RSS_HDR 1077 union opcode_tid ot; 1078 __u8 rsvd[3]; 1079 __u8 status; 1080 }; 1081 1082 struct cpl_abort_rpl_rss6 { 1083 RSS_HDR 1084 union opcode_tid ot; 1085 __u32 srqidx_status; 1086 }; 1087 1088 struct cpl_abort_rpl { 1089 WR_HDR; 1090 union opcode_tid ot; 1091 __be32 rsvd0; 1092 __u8 rsvd1; 1093 __u8 cmd; 1094 __u8 rsvd2[6]; 1095 }; 1096 1097 struct cpl_abort_rpl_core { 1098 union opcode_tid ot; 1099 __be32 rsvd0; 1100 __u8 rsvd1; 1101 __u8 cmd; 1102 __u8 rsvd2[6]; 1103 }; 1104 1105 struct cpl_peer_close { 1106 RSS_HDR 1107 union opcode_tid ot; 1108 __be32 rcv_nxt; 1109 }; 1110 1111 struct cpl_tid_release { 1112 WR_HDR; 1113 union opcode_tid ot; 1114 __be32 rsvd; 1115 }; 1116 1117 struct tx_data_wr { 1118 __be32 wr_hi; 1119 __be32 wr_lo; 1120 __be32 len; 1121 __be32 flags; 1122 __be32 sndseq; 1123 __be32 param; 1124 }; 1125 1126 /* tx_data_wr.flags fields */ 1127 #define S_TX_ACK_PAGES 21 1128 #define M_TX_ACK_PAGES 0x7 1129 #define V_TX_ACK_PAGES(x) ((x) << S_TX_ACK_PAGES) 1130 #define G_TX_ACK_PAGES(x) (((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES) 1131 1132 /* tx_data_wr.param fields */ 1133 #define S_TX_PORT 0 1134 #define M_TX_PORT 0x7 1135 #define V_TX_PORT(x) ((x) << S_TX_PORT) 1136 #define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT) 1137 1138 #define S_TX_MSS 4 1139 #define M_TX_MSS 0xF 1140 #define V_TX_MSS(x) ((x) << S_TX_MSS) 1141 #define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS) 1142 1143 #define S_TX_QOS 8 1144 #define M_TX_QOS 0xFF 1145 #define V_TX_QOS(x) ((x) << S_TX_QOS) 1146 #define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS) 1147 1148 #define S_TX_SNDBUF 16 1149 #define M_TX_SNDBUF 0xFFFF 1150 #define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF) 1151 #define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF) 1152 1153 struct cpl_tx_data { 1154 union opcode_tid ot; 1155 __be32 len; 1156 __be32 rsvd; 1157 __be32 flags; 1158 }; 1159 1160 /* cpl_tx_data.flags fields */ 1161 #define S_TX_PROXY 5 1162 #define V_TX_PROXY(x) ((x) << S_TX_PROXY) 1163 #define F_TX_PROXY V_TX_PROXY(1U) 1164 1165 #define S_TX_ULP_SUBMODE 6 1166 #define M_TX_ULP_SUBMODE 0xF 1167 #define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE) 1168 #define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE) 1169 1170 #define S_TX_ULP_MODE 10 1171 #define M_TX_ULP_MODE 0x7 1172 #define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE) 1173 #define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE) 1174 1175 #define S_TX_FORCE 13 1176 #define V_TX_FORCE(x) ((x) << S_TX_FORCE) 1177 #define F_TX_FORCE V_TX_FORCE(1U) 1178 1179 #define S_TX_SHOVE 14 1180 #define V_TX_SHOVE(x) ((x) << S_TX_SHOVE) 1181 #define F_TX_SHOVE V_TX_SHOVE(1U) 1182 1183 #define S_TX_MORE 15 1184 #define V_TX_MORE(x) ((x) << S_TX_MORE) 1185 #define F_TX_MORE V_TX_MORE(1U) 1186 1187 #define S_TX_URG 16 1188 #define V_TX_URG(x) ((x) << S_TX_URG) 1189 #define F_TX_URG V_TX_URG(1U) 1190 1191 #define S_TX_FLUSH 17 1192 #define V_TX_FLUSH(x) ((x) << S_TX_FLUSH) 1193 #define F_TX_FLUSH V_TX_FLUSH(1U) 1194 1195 #define S_TX_SAVE 18 1196 #define V_TX_SAVE(x) ((x) << S_TX_SAVE) 1197 #define F_TX_SAVE V_TX_SAVE(1U) 1198 1199 #define S_TX_TNL 19 1200 #define V_TX_TNL(x) ((x) << S_TX_TNL) 1201 #define F_TX_TNL V_TX_TNL(1U) 1202 1203 #define S_T6_TX_FORCE 20 1204 #define V_T6_TX_FORCE(x) ((x) << S_T6_TX_FORCE) 1205 #define F_T6_TX_FORCE V_T6_TX_FORCE(1U) 1206 1207 /* additional tx_data_wr.flags fields */ 1208 #define S_TX_CPU_IDX 0 1209 #define M_TX_CPU_IDX 0x3F 1210 #define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX) 1211 #define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX) 1212 1213 #define S_TX_CLOSE 17 1214 #define V_TX_CLOSE(x) ((x) << S_TX_CLOSE) 1215 #define F_TX_CLOSE V_TX_CLOSE(1U) 1216 1217 #define S_TX_INIT 18 1218 #define V_TX_INIT(x) ((x) << S_TX_INIT) 1219 #define F_TX_INIT V_TX_INIT(1U) 1220 1221 #define S_TX_IMM_ACK 19 1222 #define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK) 1223 #define F_TX_IMM_ACK V_TX_IMM_ACK(1U) 1224 1225 #define S_TX_IMM_DMA 20 1226 #define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA) 1227 #define F_TX_IMM_DMA V_TX_IMM_DMA(1U) 1228 1229 struct cpl_tx_data_ack { 1230 RSS_HDR 1231 union opcode_tid ot; 1232 __be32 snd_una; 1233 }; 1234 1235 struct cpl_wr_ack { /* XXX */ 1236 RSS_HDR 1237 union opcode_tid ot; 1238 __be16 credits; 1239 __be16 rsvd; 1240 __be32 snd_nxt; 1241 __be32 snd_una; 1242 }; 1243 1244 struct cpl_tx_pkt_core { 1245 __be32 ctrl0; 1246 __be16 pack; 1247 __be16 len; 1248 __be64 ctrl1; 1249 }; 1250 1251 struct cpl_tx_pkt { 1252 WR_HDR; 1253 struct cpl_tx_pkt_core c; 1254 }; 1255 1256 #define cpl_tx_pkt_xt cpl_tx_pkt 1257 1258 /* cpl_tx_pkt_core.ctrl0 fields */ 1259 #define S_TXPKT_VF 0 1260 #define M_TXPKT_VF 0xFF 1261 #define V_TXPKT_VF(x) ((x) << S_TXPKT_VF) 1262 #define G_TXPKT_VF(x) (((x) >> S_TXPKT_VF) & M_TXPKT_VF) 1263 1264 #define S_TXPKT_PF 8 1265 #define M_TXPKT_PF 0x7 1266 #define V_TXPKT_PF(x) ((x) << S_TXPKT_PF) 1267 #define G_TXPKT_PF(x) (((x) >> S_TXPKT_PF) & M_TXPKT_PF) 1268 1269 #define S_TXPKT_VF_VLD 11 1270 #define V_TXPKT_VF_VLD(x) ((x) << S_TXPKT_VF_VLD) 1271 #define F_TXPKT_VF_VLD V_TXPKT_VF_VLD(1U) 1272 1273 #define S_TXPKT_OVLAN_IDX 12 1274 #define M_TXPKT_OVLAN_IDX 0xF 1275 #define V_TXPKT_OVLAN_IDX(x) ((x) << S_TXPKT_OVLAN_IDX) 1276 #define G_TXPKT_OVLAN_IDX(x) (((x) >> S_TXPKT_OVLAN_IDX) & M_TXPKT_OVLAN_IDX) 1277 1278 #define S_TXPKT_T5_OVLAN_IDX 12 1279 #define M_TXPKT_T5_OVLAN_IDX 0x7 1280 #define V_TXPKT_T5_OVLAN_IDX(x) ((x) << S_TXPKT_T5_OVLAN_IDX) 1281 #define G_TXPKT_T5_OVLAN_IDX(x) (((x) >> S_TXPKT_T5_OVLAN_IDX) & \ 1282 M_TXPKT_T5_OVLAN_IDX) 1283 1284 #define S_TXPKT_INTF 16 1285 #define M_TXPKT_INTF 0xF 1286 #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF) 1287 #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF) 1288 1289 #define S_TXPKT_SPECIAL_STAT 20 1290 #define V_TXPKT_SPECIAL_STAT(x) ((x) << S_TXPKT_SPECIAL_STAT) 1291 #define F_TXPKT_SPECIAL_STAT V_TXPKT_SPECIAL_STAT(1U) 1292 1293 #define S_TXPKT_T5_FCS_DIS 21 1294 #define V_TXPKT_T5_FCS_DIS(x) ((x) << S_TXPKT_T5_FCS_DIS) 1295 #define F_TXPKT_T5_FCS_DIS V_TXPKT_T5_FCS_DIS(1U) 1296 1297 #define S_TXPKT_INS_OVLAN 21 1298 #define V_TXPKT_INS_OVLAN(x) ((x) << S_TXPKT_INS_OVLAN) 1299 #define F_TXPKT_INS_OVLAN V_TXPKT_INS_OVLAN(1U) 1300 1301 #define S_TXPKT_T5_INS_OVLAN 15 1302 #define V_TXPKT_T5_INS_OVLAN(x) ((x) << S_TXPKT_T5_INS_OVLAN) 1303 #define F_TXPKT_T5_INS_OVLAN V_TXPKT_T5_INS_OVLAN(1U) 1304 1305 #define S_TXPKT_STAT_DIS 22 1306 #define V_TXPKT_STAT_DIS(x) ((x) << S_TXPKT_STAT_DIS) 1307 #define F_TXPKT_STAT_DIS V_TXPKT_STAT_DIS(1U) 1308 1309 #define S_TXPKT_LOOPBACK 23 1310 #define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK) 1311 #define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U) 1312 1313 #define S_TXPKT_TSTAMP 23 1314 #define V_TXPKT_TSTAMP(x) ((x) << S_TXPKT_TSTAMP) 1315 #define F_TXPKT_TSTAMP V_TXPKT_TSTAMP(1U) 1316 1317 #define S_TXPKT_OPCODE 24 1318 #define M_TXPKT_OPCODE 0xFF 1319 #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE) 1320 #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE) 1321 1322 /* cpl_tx_pkt_core.ctrl1 fields */ 1323 #define S_TXPKT_SA_IDX 0 1324 #define M_TXPKT_SA_IDX 0xFFF 1325 #define V_TXPKT_SA_IDX(x) ((x) << S_TXPKT_SA_IDX) 1326 #define G_TXPKT_SA_IDX(x) (((x) >> S_TXPKT_SA_IDX) & M_TXPKT_SA_IDX) 1327 1328 #define S_TXPKT_CSUM_END 12 1329 #define M_TXPKT_CSUM_END 0xFF 1330 #define V_TXPKT_CSUM_END(x) ((x) << S_TXPKT_CSUM_END) 1331 #define G_TXPKT_CSUM_END(x) (((x) >> S_TXPKT_CSUM_END) & M_TXPKT_CSUM_END) 1332 1333 #define S_TXPKT_CSUM_START 20 1334 #define M_TXPKT_CSUM_START 0x3FF 1335 #define V_TXPKT_CSUM_START(x) ((x) << S_TXPKT_CSUM_START) 1336 #define G_TXPKT_CSUM_START(x) (((x) >> S_TXPKT_CSUM_START) & M_TXPKT_CSUM_START) 1337 1338 #define S_TXPKT_IPHDR_LEN 20 1339 #define M_TXPKT_IPHDR_LEN 0x3FFF 1340 #define V_TXPKT_IPHDR_LEN(x) ((__u64)(x) << S_TXPKT_IPHDR_LEN) 1341 #define G_TXPKT_IPHDR_LEN(x) (((x) >> S_TXPKT_IPHDR_LEN) & M_TXPKT_IPHDR_LEN) 1342 1343 #define M_T6_TXPKT_IPHDR_LEN 0xFFF 1344 #define G_T6_TXPKT_IPHDR_LEN(x) \ 1345 (((x) >> S_TXPKT_IPHDR_LEN) & M_T6_TXPKT_IPHDR_LEN) 1346 1347 #define S_TXPKT_CSUM_LOC 30 1348 #define M_TXPKT_CSUM_LOC 0x3FF 1349 #define V_TXPKT_CSUM_LOC(x) ((__u64)(x) << S_TXPKT_CSUM_LOC) 1350 #define G_TXPKT_CSUM_LOC(x) (((x) >> S_TXPKT_CSUM_LOC) & M_TXPKT_CSUM_LOC) 1351 1352 #define S_TXPKT_ETHHDR_LEN 34 1353 #define M_TXPKT_ETHHDR_LEN 0x3F 1354 #define V_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_TXPKT_ETHHDR_LEN) 1355 #define G_TXPKT_ETHHDR_LEN(x) (((x) >> S_TXPKT_ETHHDR_LEN) & M_TXPKT_ETHHDR_LEN) 1356 1357 #define S_T6_TXPKT_ETHHDR_LEN 32 1358 #define M_T6_TXPKT_ETHHDR_LEN 0xFF 1359 #define V_T6_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_T6_TXPKT_ETHHDR_LEN) 1360 #define G_T6_TXPKT_ETHHDR_LEN(x) \ 1361 (((x) >> S_T6_TXPKT_ETHHDR_LEN) & M_T6_TXPKT_ETHHDR_LEN) 1362 1363 #define S_TXPKT_CSUM_TYPE 40 1364 #define M_TXPKT_CSUM_TYPE 0xF 1365 #define V_TXPKT_CSUM_TYPE(x) ((__u64)(x) << S_TXPKT_CSUM_TYPE) 1366 #define G_TXPKT_CSUM_TYPE(x) (((x) >> S_TXPKT_CSUM_TYPE) & M_TXPKT_CSUM_TYPE) 1367 1368 #define S_TXPKT_VLAN 44 1369 #define M_TXPKT_VLAN 0xFFFF 1370 #define V_TXPKT_VLAN(x) ((__u64)(x) << S_TXPKT_VLAN) 1371 #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN) 1372 1373 #define S_TXPKT_VLAN_VLD 60 1374 #define V_TXPKT_VLAN_VLD(x) ((__u64)(x) << S_TXPKT_VLAN_VLD) 1375 #define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1ULL) 1376 1377 #define S_TXPKT_IPSEC 61 1378 #define V_TXPKT_IPSEC(x) ((__u64)(x) << S_TXPKT_IPSEC) 1379 #define F_TXPKT_IPSEC V_TXPKT_IPSEC(1ULL) 1380 1381 #define S_TXPKT_IPCSUM_DIS 62 1382 #define V_TXPKT_IPCSUM_DIS(x) ((__u64)(x) << S_TXPKT_IPCSUM_DIS) 1383 #define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1ULL) 1384 1385 #define S_TXPKT_L4CSUM_DIS 63 1386 #define V_TXPKT_L4CSUM_DIS(x) ((__u64)(x) << S_TXPKT_L4CSUM_DIS) 1387 #define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1ULL) 1388 1389 struct cpl_tx_pkt_lso_core { 1390 __be32 lso_ctrl; 1391 __be16 ipid_ofst; 1392 __be16 mss; 1393 __be32 seqno_offset; 1394 __be32 len; 1395 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1396 }; 1397 1398 struct cpl_tx_pkt_lso { 1399 WR_HDR; 1400 struct cpl_tx_pkt_lso_core c; 1401 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1402 }; 1403 1404 struct cpl_tx_pkt_ufo_core { 1405 __be16 ethlen; 1406 __be16 iplen; 1407 __be16 udplen; 1408 __be16 mss; 1409 __be32 len; 1410 __be32 r1; 1411 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1412 }; 1413 1414 struct cpl_tx_pkt_ufo { 1415 WR_HDR; 1416 struct cpl_tx_pkt_ufo_core c; 1417 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1418 }; 1419 1420 /* cpl_tx_pkt_lso_core.lso_ctrl fields */ 1421 #define S_LSO_TCPHDR_LEN 0 1422 #define M_LSO_TCPHDR_LEN 0xF 1423 #define V_LSO_TCPHDR_LEN(x) ((x) << S_LSO_TCPHDR_LEN) 1424 #define G_LSO_TCPHDR_LEN(x) (((x) >> S_LSO_TCPHDR_LEN) & M_LSO_TCPHDR_LEN) 1425 1426 #define S_LSO_IPHDR_LEN 4 1427 #define M_LSO_IPHDR_LEN 0xFFF 1428 #define V_LSO_IPHDR_LEN(x) ((x) << S_LSO_IPHDR_LEN) 1429 #define G_LSO_IPHDR_LEN(x) (((x) >> S_LSO_IPHDR_LEN) & M_LSO_IPHDR_LEN) 1430 1431 #define S_LSO_ETHHDR_LEN 16 1432 #define M_LSO_ETHHDR_LEN 0xF 1433 #define V_LSO_ETHHDR_LEN(x) ((x) << S_LSO_ETHHDR_LEN) 1434 #define G_LSO_ETHHDR_LEN(x) (((x) >> S_LSO_ETHHDR_LEN) & M_LSO_ETHHDR_LEN) 1435 1436 #define S_LSO_IPV6 20 1437 #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6) 1438 #define F_LSO_IPV6 V_LSO_IPV6(1U) 1439 1440 #define S_LSO_OFLD_ENCAP 21 1441 #define V_LSO_OFLD_ENCAP(x) ((x) << S_LSO_OFLD_ENCAP) 1442 #define F_LSO_OFLD_ENCAP V_LSO_OFLD_ENCAP(1U) 1443 1444 #define S_LSO_LAST_SLICE 22 1445 #define V_LSO_LAST_SLICE(x) ((x) << S_LSO_LAST_SLICE) 1446 #define F_LSO_LAST_SLICE V_LSO_LAST_SLICE(1U) 1447 1448 #define S_LSO_FIRST_SLICE 23 1449 #define V_LSO_FIRST_SLICE(x) ((x) << S_LSO_FIRST_SLICE) 1450 #define F_LSO_FIRST_SLICE V_LSO_FIRST_SLICE(1U) 1451 1452 #define S_LSO_OPCODE 24 1453 #define M_LSO_OPCODE 0xFF 1454 #define V_LSO_OPCODE(x) ((x) << S_LSO_OPCODE) 1455 #define G_LSO_OPCODE(x) (((x) >> S_LSO_OPCODE) & M_LSO_OPCODE) 1456 1457 #define S_LSO_T5_XFER_SIZE 0 1458 #define M_LSO_T5_XFER_SIZE 0xFFFFFFF 1459 #define V_LSO_T5_XFER_SIZE(x) ((x) << S_LSO_T5_XFER_SIZE) 1460 #define G_LSO_T5_XFER_SIZE(x) (((x) >> S_LSO_T5_XFER_SIZE) & M_LSO_T5_XFER_SIZE) 1461 1462 /* cpl_tx_pkt_lso_core.mss fields */ 1463 #define S_LSO_MSS 0 1464 #define M_LSO_MSS 0x3FFF 1465 #define V_LSO_MSS(x) ((x) << S_LSO_MSS) 1466 #define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS) 1467 1468 #define S_LSO_IPID_SPLIT 15 1469 #define V_LSO_IPID_SPLIT(x) ((x) << S_LSO_IPID_SPLIT) 1470 #define F_LSO_IPID_SPLIT V_LSO_IPID_SPLIT(1U) 1471 1472 struct cpl_tx_pkt_fso { 1473 WR_HDR; 1474 __be32 fso_ctrl; 1475 __be16 seqcnt_ofst; 1476 __be16 mtu; 1477 __be32 param_offset; 1478 __be32 len; 1479 /* encapsulated CPL (TX_PKT or TX_PKT_XT) follows here */ 1480 }; 1481 1482 /* cpl_tx_pkt_fso.fso_ctrl fields different from cpl_tx_pkt_lso.lso_ctrl */ 1483 #define S_FSO_XCHG_CLASS 21 1484 #define V_FSO_XCHG_CLASS(x) ((x) << S_FSO_XCHG_CLASS) 1485 #define F_FSO_XCHG_CLASS V_FSO_XCHG_CLASS(1U) 1486 1487 #define S_FSO_INITIATOR 20 1488 #define V_FSO_INITIATOR(x) ((x) << S_FSO_INITIATOR) 1489 #define F_FSO_INITIATOR V_FSO_INITIATOR(1U) 1490 1491 #define S_FSO_FCHDR_LEN 12 1492 #define M_FSO_FCHDR_LEN 0xF 1493 #define V_FSO_FCHDR_LEN(x) ((x) << S_FSO_FCHDR_LEN) 1494 #define G_FSO_FCHDR_LEN(x) (((x) >> S_FSO_FCHDR_LEN) & M_FSO_FCHDR_LEN) 1495 1496 struct cpl_iscsi_hdr_no_rss { 1497 union opcode_tid ot; 1498 __be16 pdu_len_ddp; 1499 __be16 len; 1500 __be32 seq; 1501 __be16 urg; 1502 __u8 rsvd; 1503 __u8 status; 1504 }; 1505 1506 struct cpl_tx_data_iso { 1507 __be32 op_to_scsi; 1508 __u8 reserved1; 1509 __u8 ahs_len; 1510 __be16 mpdu; 1511 __be32 burst_size; 1512 __be32 len; 1513 __be32 reserved2_seglen_offset; 1514 __be32 datasn_offset; 1515 __be32 buffer_offset; 1516 __be32 reserved3; 1517 1518 /* encapsulated CPL_TX_DATA follows here */ 1519 }; 1520 1521 /* cpl_tx_data_iso.op_to_scsi fields */ 1522 #define S_CPL_TX_DATA_ISO_OP 24 1523 #define M_CPL_TX_DATA_ISO_OP 0xff 1524 #define V_CPL_TX_DATA_ISO_OP(x) ((x) << S_CPL_TX_DATA_ISO_OP) 1525 #define G_CPL_TX_DATA_ISO_OP(x) \ 1526 (((x) >> S_CPL_TX_DATA_ISO_OP) & M_CPL_TX_DATA_ISO_OP) 1527 1528 #define S_CPL_TX_DATA_ISO_FIRST 23 1529 #define M_CPL_TX_DATA_ISO_FIRST 0x1 1530 #define V_CPL_TX_DATA_ISO_FIRST(x) ((x) << S_CPL_TX_DATA_ISO_FIRST) 1531 #define G_CPL_TX_DATA_ISO_FIRST(x) \ 1532 (((x) >> S_CPL_TX_DATA_ISO_FIRST) & M_CPL_TX_DATA_ISO_FIRST) 1533 #define F_CPL_TX_DATA_ISO_FIRST V_CPL_TX_DATA_ISO_FIRST(1U) 1534 1535 #define S_CPL_TX_DATA_ISO_LAST 22 1536 #define M_CPL_TX_DATA_ISO_LAST 0x1 1537 #define V_CPL_TX_DATA_ISO_LAST(x) ((x) << S_CPL_TX_DATA_ISO_LAST) 1538 #define G_CPL_TX_DATA_ISO_LAST(x) \ 1539 (((x) >> S_CPL_TX_DATA_ISO_LAST) & M_CPL_TX_DATA_ISO_LAST) 1540 #define F_CPL_TX_DATA_ISO_LAST V_CPL_TX_DATA_ISO_LAST(1U) 1541 1542 #define S_CPL_TX_DATA_ISO_CPLHDRLEN 21 1543 #define M_CPL_TX_DATA_ISO_CPLHDRLEN 0x1 1544 #define V_CPL_TX_DATA_ISO_CPLHDRLEN(x) ((x) << S_CPL_TX_DATA_ISO_CPLHDRLEN) 1545 #define G_CPL_TX_DATA_ISO_CPLHDRLEN(x) \ 1546 (((x) >> S_CPL_TX_DATA_ISO_CPLHDRLEN) & M_CPL_TX_DATA_ISO_CPLHDRLEN) 1547 #define F_CPL_TX_DATA_ISO_CPLHDRLEN V_CPL_TX_DATA_ISO_CPLHDRLEN(1U) 1548 1549 #define S_CPL_TX_DATA_ISO_HDRCRC 20 1550 #define M_CPL_TX_DATA_ISO_HDRCRC 0x1 1551 #define V_CPL_TX_DATA_ISO_HDRCRC(x) ((x) << S_CPL_TX_DATA_ISO_HDRCRC) 1552 #define G_CPL_TX_DATA_ISO_HDRCRC(x) \ 1553 (((x) >> S_CPL_TX_DATA_ISO_HDRCRC) & M_CPL_TX_DATA_ISO_HDRCRC) 1554 #define F_CPL_TX_DATA_ISO_HDRCRC V_CPL_TX_DATA_ISO_HDRCRC(1U) 1555 1556 #define S_CPL_TX_DATA_ISO_PLDCRC 19 1557 #define M_CPL_TX_DATA_ISO_PLDCRC 0x1 1558 #define V_CPL_TX_DATA_ISO_PLDCRC(x) ((x) << S_CPL_TX_DATA_ISO_PLDCRC) 1559 #define G_CPL_TX_DATA_ISO_PLDCRC(x) \ 1560 (((x) >> S_CPL_TX_DATA_ISO_PLDCRC) & M_CPL_TX_DATA_ISO_PLDCRC) 1561 #define F_CPL_TX_DATA_ISO_PLDCRC V_CPL_TX_DATA_ISO_PLDCRC(1U) 1562 1563 #define S_CPL_TX_DATA_ISO_IMMEDIATE 18 1564 #define M_CPL_TX_DATA_ISO_IMMEDIATE 0x1 1565 #define V_CPL_TX_DATA_ISO_IMMEDIATE(x) ((x) << S_CPL_TX_DATA_ISO_IMMEDIATE) 1566 #define G_CPL_TX_DATA_ISO_IMMEDIATE(x) \ 1567 (((x) >> S_CPL_TX_DATA_ISO_IMMEDIATE) & M_CPL_TX_DATA_ISO_IMMEDIATE) 1568 #define F_CPL_TX_DATA_ISO_IMMEDIATE V_CPL_TX_DATA_ISO_IMMEDIATE(1U) 1569 1570 #define S_CPL_TX_DATA_ISO_SCSI 16 1571 #define M_CPL_TX_DATA_ISO_SCSI 0x3 1572 #define V_CPL_TX_DATA_ISO_SCSI(x) ((x) << S_CPL_TX_DATA_ISO_SCSI) 1573 #define G_CPL_TX_DATA_ISO_SCSI(x) \ 1574 (((x) >> S_CPL_TX_DATA_ISO_SCSI) & M_CPL_TX_DATA_ISO_SCSI) 1575 1576 /* cpl_tx_data_iso.reserved2_seglen_offset fields */ 1577 #define S_CPL_TX_DATA_ISO_SEGLEN_OFFSET 0 1578 #define M_CPL_TX_DATA_ISO_SEGLEN_OFFSET 0xffffff 1579 #define V_CPL_TX_DATA_ISO_SEGLEN_OFFSET(x) \ 1580 ((x) << S_CPL_TX_DATA_ISO_SEGLEN_OFFSET) 1581 #define G_CPL_TX_DATA_ISO_SEGLEN_OFFSET(x) \ 1582 (((x) >> S_CPL_TX_DATA_ISO_SEGLEN_OFFSET) & \ 1583 M_CPL_TX_DATA_ISO_SEGLEN_OFFSET) 1584 1585 struct cpl_iscsi_hdr { 1586 RSS_HDR 1587 union opcode_tid ot; 1588 __be16 pdu_len_ddp; 1589 __be16 len; 1590 __be32 seq; 1591 __be16 urg; 1592 __u8 rsvd; 1593 __u8 status; 1594 }; 1595 1596 /* cpl_iscsi_hdr.pdu_len_ddp fields */ 1597 #define S_ISCSI_PDU_LEN 0 1598 #define M_ISCSI_PDU_LEN 0x7FFF 1599 #define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN) 1600 #define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN) 1601 1602 #define S_ISCSI_DDP 15 1603 #define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP) 1604 #define F_ISCSI_DDP V_ISCSI_DDP(1U) 1605 1606 struct cpl_iscsi_data { 1607 RSS_HDR 1608 union opcode_tid ot; 1609 __u8 rsvd0[2]; 1610 __be16 len; 1611 __be32 seq; 1612 __be16 urg; 1613 __u8 rsvd1; 1614 __u8 status; 1615 }; 1616 1617 struct cpl_rx_data { 1618 RSS_HDR 1619 union opcode_tid ot; 1620 __be16 rsvd; 1621 __be16 len; 1622 __be32 seq; 1623 __be16 urg; 1624 #if defined(__LITTLE_ENDIAN_BITFIELD) 1625 __u8 dack_mode:2; 1626 __u8 psh:1; 1627 __u8 heartbeat:1; 1628 __u8 ddp_off:1; 1629 __u8 :3; 1630 #else 1631 __u8 :3; 1632 __u8 ddp_off:1; 1633 __u8 heartbeat:1; 1634 __u8 psh:1; 1635 __u8 dack_mode:2; 1636 #endif 1637 __u8 status; 1638 }; 1639 1640 struct cpl_fcoe_hdr { 1641 RSS_HDR 1642 union opcode_tid ot; 1643 __be16 oxid; 1644 __be16 len; 1645 __be32 rctl_fctl; 1646 __u8 cs_ctl; 1647 __u8 df_ctl; 1648 __u8 sof; 1649 __u8 eof; 1650 __be16 seq_cnt; 1651 __u8 seq_id; 1652 __u8 type; 1653 __be32 param; 1654 }; 1655 1656 /* cpl_fcoe_hdr.rctl_fctl fields */ 1657 #define S_FCOE_FCHDR_RCTL 24 1658 #define M_FCOE_FCHDR_RCTL 0xff 1659 #define V_FCOE_FCHDR_RCTL(x) ((x) << S_FCOE_FCHDR_RCTL) 1660 #define G_FCOE_FCHDR_RCTL(x) \ 1661 (((x) >> S_FCOE_FCHDR_RCTL) & M_FCOE_FCHDR_RCTL) 1662 1663 #define S_FCOE_FCHDR_FCTL 0 1664 #define M_FCOE_FCHDR_FCTL 0xffffff 1665 #define V_FCOE_FCHDR_FCTL(x) ((x) << S_FCOE_FCHDR_FCTL) 1666 #define G_FCOE_FCHDR_FCTL(x) \ 1667 (((x) >> S_FCOE_FCHDR_FCTL) & M_FCOE_FCHDR_FCTL) 1668 1669 struct cpl_fcoe_data { 1670 RSS_HDR 1671 union opcode_tid ot; 1672 __u8 rsvd0[2]; 1673 __be16 len; 1674 __be32 seq; 1675 __u8 rsvd1[3]; 1676 __u8 status; 1677 }; 1678 1679 struct cpl_rx_urg_notify { 1680 RSS_HDR 1681 union opcode_tid ot; 1682 __be32 seq; 1683 }; 1684 1685 struct cpl_rx_urg_pkt { 1686 RSS_HDR 1687 union opcode_tid ot; 1688 __be16 rsvd; 1689 __be16 len; 1690 }; 1691 1692 struct cpl_rx_data_ack { 1693 WR_HDR; 1694 union opcode_tid ot; 1695 __be32 credit_dack; 1696 }; 1697 1698 struct cpl_rx_data_ack_core { 1699 union opcode_tid ot; 1700 __be32 credit_dack; 1701 }; 1702 1703 /* cpl_rx_data_ack.ack_seq fields */ 1704 #define S_RX_CREDITS 0 1705 #define M_RX_CREDITS 0x3FFFFFF 1706 #define V_RX_CREDITS(x) ((x) << S_RX_CREDITS) 1707 #define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS) 1708 1709 #define S_RX_MODULATE_TX 26 1710 #define V_RX_MODULATE_TX(x) ((x) << S_RX_MODULATE_TX) 1711 #define F_RX_MODULATE_TX V_RX_MODULATE_TX(1U) 1712 1713 #define S_RX_MODULATE_RX 27 1714 #define V_RX_MODULATE_RX(x) ((x) << S_RX_MODULATE_RX) 1715 #define F_RX_MODULATE_RX V_RX_MODULATE_RX(1U) 1716 1717 #define S_RX_FORCE_ACK 28 1718 #define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK) 1719 #define F_RX_FORCE_ACK V_RX_FORCE_ACK(1U) 1720 1721 #define S_RX_DACK_MODE 29 1722 #define M_RX_DACK_MODE 0x3 1723 #define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE) 1724 #define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE) 1725 1726 #define S_RX_DACK_CHANGE 31 1727 #define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE) 1728 #define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U) 1729 1730 struct cpl_rx_ddp_complete { 1731 RSS_HDR 1732 union opcode_tid ot; 1733 __be32 ddp_report; 1734 __be32 rcv_nxt; 1735 __be32 rsvd; 1736 }; 1737 1738 struct cpl_rx_data_ddp { 1739 RSS_HDR 1740 union opcode_tid ot; 1741 __be16 urg; 1742 __be16 len; 1743 __be32 seq; 1744 union { 1745 __be32 nxt_seq; 1746 __be32 ddp_report; 1747 } u; 1748 __be32 ulp_crc; 1749 __be32 ddpvld; 1750 }; 1751 1752 #define cpl_rx_iscsi_ddp cpl_rx_data_ddp 1753 1754 struct cpl_rx_fcoe_ddp { 1755 RSS_HDR 1756 union opcode_tid ot; 1757 __be16 rsvd; 1758 __be16 len; 1759 __be32 seq; 1760 __be32 ddp_report; 1761 __be32 ulp_crc; 1762 __be32 ddpvld; 1763 }; 1764 1765 struct cpl_rx_data_dif { 1766 RSS_HDR 1767 union opcode_tid ot; 1768 __be16 ddp_len; 1769 __be16 msg_len; 1770 __be32 seq; 1771 union { 1772 __be32 nxt_seq; 1773 __be32 ddp_report; 1774 } u; 1775 __be32 err_vec; 1776 __be32 ddpvld; 1777 }; 1778 1779 struct cpl_rx_iscsi_dif { 1780 RSS_HDR 1781 union opcode_tid ot; 1782 __be16 ddp_len; 1783 __be16 msg_len; 1784 __be32 seq; 1785 union { 1786 __be32 nxt_seq; 1787 __be32 ddp_report; 1788 } u; 1789 __be32 ulp_crc; 1790 __be32 ddpvld; 1791 __u8 rsvd0[8]; 1792 __be32 err_vec; 1793 __u8 rsvd1[4]; 1794 }; 1795 1796 struct cpl_rx_iscsi_cmp { 1797 RSS_HDR 1798 union opcode_tid ot; 1799 __be16 pdu_len_ddp; 1800 __be16 len; 1801 __be32 seq; 1802 __be16 urg; 1803 __u8 rsvd; 1804 __u8 status; 1805 __be32 ulp_crc; 1806 __be32 ddpvld; 1807 }; 1808 1809 struct cpl_rx_fcoe_dif { 1810 RSS_HDR 1811 union opcode_tid ot; 1812 __be16 ddp_len; 1813 __be16 msg_len; 1814 __be32 seq; 1815 __be32 ddp_report; 1816 __be32 err_vec; 1817 __be32 ddpvld; 1818 }; 1819 1820 /* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddpvld fields */ 1821 #define S_DDP_VALID 15 1822 #define M_DDP_VALID 0x1FFFF 1823 #define V_DDP_VALID(x) ((x) << S_DDP_VALID) 1824 #define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID) 1825 1826 #define S_DDP_PPOD_MISMATCH 15 1827 #define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH) 1828 #define F_DDP_PPOD_MISMATCH V_DDP_PPOD_MISMATCH(1U) 1829 1830 #define S_DDP_PDU 16 1831 #define V_DDP_PDU(x) ((x) << S_DDP_PDU) 1832 #define F_DDP_PDU V_DDP_PDU(1U) 1833 1834 #define S_DDP_LLIMIT_ERR 17 1835 #define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR) 1836 #define F_DDP_LLIMIT_ERR V_DDP_LLIMIT_ERR(1U) 1837 1838 #define S_DDP_PPOD_PARITY_ERR 18 1839 #define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR) 1840 #define F_DDP_PPOD_PARITY_ERR V_DDP_PPOD_PARITY_ERR(1U) 1841 1842 #define S_DDP_PADDING_ERR 19 1843 #define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR) 1844 #define F_DDP_PADDING_ERR V_DDP_PADDING_ERR(1U) 1845 1846 #define S_DDP_HDRCRC_ERR 20 1847 #define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR) 1848 #define F_DDP_HDRCRC_ERR V_DDP_HDRCRC_ERR(1U) 1849 1850 #define S_DDP_DATACRC_ERR 21 1851 #define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR) 1852 #define F_DDP_DATACRC_ERR V_DDP_DATACRC_ERR(1U) 1853 1854 #define S_DDP_INVALID_TAG 22 1855 #define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG) 1856 #define F_DDP_INVALID_TAG V_DDP_INVALID_TAG(1U) 1857 1858 #define S_DDP_ULIMIT_ERR 23 1859 #define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR) 1860 #define F_DDP_ULIMIT_ERR V_DDP_ULIMIT_ERR(1U) 1861 1862 #define S_DDP_OFFSET_ERR 24 1863 #define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR) 1864 #define F_DDP_OFFSET_ERR V_DDP_OFFSET_ERR(1U) 1865 1866 #define S_DDP_COLOR_ERR 25 1867 #define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR) 1868 #define F_DDP_COLOR_ERR V_DDP_COLOR_ERR(1U) 1869 1870 #define S_DDP_TID_MISMATCH 26 1871 #define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH) 1872 #define F_DDP_TID_MISMATCH V_DDP_TID_MISMATCH(1U) 1873 1874 #define S_DDP_INVALID_PPOD 27 1875 #define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD) 1876 #define F_DDP_INVALID_PPOD V_DDP_INVALID_PPOD(1U) 1877 1878 #define S_DDP_ULP_MODE 28 1879 #define M_DDP_ULP_MODE 0xF 1880 #define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE) 1881 #define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE) 1882 1883 /* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddp_report fields */ 1884 #define S_DDP_OFFSET 0 1885 #define M_DDP_OFFSET 0xFFFFFF 1886 #define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET) 1887 #define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET) 1888 1889 #define S_DDP_DACK_MODE 24 1890 #define M_DDP_DACK_MODE 0x3 1891 #define V_DDP_DACK_MODE(x) ((x) << S_DDP_DACK_MODE) 1892 #define G_DDP_DACK_MODE(x) (((x) >> S_DDP_DACK_MODE) & M_DDP_DACK_MODE) 1893 1894 #define S_DDP_BUF_IDX 26 1895 #define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX) 1896 #define F_DDP_BUF_IDX V_DDP_BUF_IDX(1U) 1897 1898 #define S_DDP_URG 27 1899 #define V_DDP_URG(x) ((x) << S_DDP_URG) 1900 #define F_DDP_URG V_DDP_URG(1U) 1901 1902 #define S_DDP_PSH 28 1903 #define V_DDP_PSH(x) ((x) << S_DDP_PSH) 1904 #define F_DDP_PSH V_DDP_PSH(1U) 1905 1906 #define S_DDP_BUF_COMPLETE 29 1907 #define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE) 1908 #define F_DDP_BUF_COMPLETE V_DDP_BUF_COMPLETE(1U) 1909 1910 #define S_DDP_BUF_TIMED_OUT 30 1911 #define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT) 1912 #define F_DDP_BUF_TIMED_OUT V_DDP_BUF_TIMED_OUT(1U) 1913 1914 #define S_DDP_INV 31 1915 #define V_DDP_INV(x) ((x) << S_DDP_INV) 1916 #define F_DDP_INV V_DDP_INV(1U) 1917 1918 struct cpl_rx_pkt { 1919 RSS_HDR 1920 __u8 opcode; 1921 #if defined(__LITTLE_ENDIAN_BITFIELD) 1922 __u8 iff:4; 1923 __u8 csum_calc:1; 1924 __u8 ipmi_pkt:1; 1925 __u8 vlan_ex:1; 1926 __u8 ip_frag:1; 1927 #else 1928 __u8 ip_frag:1; 1929 __u8 vlan_ex:1; 1930 __u8 ipmi_pkt:1; 1931 __u8 csum_calc:1; 1932 __u8 iff:4; 1933 #endif 1934 __be16 csum; 1935 __be16 vlan; 1936 __be16 len; 1937 __be32 l2info; 1938 __be16 hdr_len; 1939 __be16 err_vec; 1940 }; 1941 1942 /* rx_pkt.l2info fields */ 1943 #define S_RX_ETHHDR_LEN 0 1944 #define M_RX_ETHHDR_LEN 0x1F 1945 #define V_RX_ETHHDR_LEN(x) ((x) << S_RX_ETHHDR_LEN) 1946 #define G_RX_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_ETHHDR_LEN) 1947 1948 #define S_RX_T5_ETHHDR_LEN 0 1949 #define M_RX_T5_ETHHDR_LEN 0x3F 1950 #define V_RX_T5_ETHHDR_LEN(x) ((x) << S_RX_T5_ETHHDR_LEN) 1951 #define G_RX_T5_ETHHDR_LEN(x) (((x) >> S_RX_T5_ETHHDR_LEN) & M_RX_T5_ETHHDR_LEN) 1952 1953 #define M_RX_T6_ETHHDR_LEN 0xFF 1954 #define G_RX_T6_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_T6_ETHHDR_LEN) 1955 1956 #define S_RX_PKTYPE 5 1957 #define M_RX_PKTYPE 0x7 1958 #define V_RX_PKTYPE(x) ((x) << S_RX_PKTYPE) 1959 #define G_RX_PKTYPE(x) (((x) >> S_RX_PKTYPE) & M_RX_PKTYPE) 1960 1961 #define S_RX_T5_DATYPE 6 1962 #define M_RX_T5_DATYPE 0x3 1963 #define V_RX_T5_DATYPE(x) ((x) << S_RX_T5_DATYPE) 1964 #define G_RX_T5_DATYPE(x) (((x) >> S_RX_T5_DATYPE) & M_RX_T5_DATYPE) 1965 1966 #define S_RX_MACIDX 8 1967 #define M_RX_MACIDX 0x1FF 1968 #define V_RX_MACIDX(x) ((x) << S_RX_MACIDX) 1969 #define G_RX_MACIDX(x) (((x) >> S_RX_MACIDX) & M_RX_MACIDX) 1970 1971 #define S_RX_T5_PKTYPE 17 1972 #define M_RX_T5_PKTYPE 0x7 1973 #define V_RX_T5_PKTYPE(x) ((x) << S_RX_T5_PKTYPE) 1974 #define G_RX_T5_PKTYPE(x) (((x) >> S_RX_T5_PKTYPE) & M_RX_T5_PKTYPE) 1975 1976 #define S_RX_DATYPE 18 1977 #define M_RX_DATYPE 0x3 1978 #define V_RX_DATYPE(x) ((x) << S_RX_DATYPE) 1979 #define G_RX_DATYPE(x) (((x) >> S_RX_DATYPE) & M_RX_DATYPE) 1980 1981 #define S_RXF_PSH 20 1982 #define V_RXF_PSH(x) ((x) << S_RXF_PSH) 1983 #define F_RXF_PSH V_RXF_PSH(1U) 1984 1985 #define S_RXF_SYN 21 1986 #define V_RXF_SYN(x) ((x) << S_RXF_SYN) 1987 #define F_RXF_SYN V_RXF_SYN(1U) 1988 1989 #define S_RXF_UDP 22 1990 #define V_RXF_UDP(x) ((x) << S_RXF_UDP) 1991 #define F_RXF_UDP V_RXF_UDP(1U) 1992 1993 #define S_RXF_TCP 23 1994 #define V_RXF_TCP(x) ((x) << S_RXF_TCP) 1995 #define F_RXF_TCP V_RXF_TCP(1U) 1996 1997 #define S_RXF_IP 24 1998 #define V_RXF_IP(x) ((x) << S_RXF_IP) 1999 #define F_RXF_IP V_RXF_IP(1U) 2000 2001 #define S_RXF_IP6 25 2002 #define V_RXF_IP6(x) ((x) << S_RXF_IP6) 2003 #define F_RXF_IP6 V_RXF_IP6(1U) 2004 2005 #define S_RXF_SYN_COOKIE 26 2006 #define V_RXF_SYN_COOKIE(x) ((x) << S_RXF_SYN_COOKIE) 2007 #define F_RXF_SYN_COOKIE V_RXF_SYN_COOKIE(1U) 2008 2009 #define S_RXF_FCOE 26 2010 #define V_RXF_FCOE(x) ((x) << S_RXF_FCOE) 2011 #define F_RXF_FCOE V_RXF_FCOE(1U) 2012 2013 #define S_RXF_LRO 27 2014 #define V_RXF_LRO(x) ((x) << S_RXF_LRO) 2015 #define F_RXF_LRO V_RXF_LRO(1U) 2016 2017 #define S_RX_CHAN 28 2018 #define M_RX_CHAN 0xF 2019 #define V_RX_CHAN(x) ((x) << S_RX_CHAN) 2020 #define G_RX_CHAN(x) (((x) >> S_RX_CHAN) & M_RX_CHAN) 2021 2022 /* rx_pkt.hdr_len fields */ 2023 #define S_RX_TCPHDR_LEN 0 2024 #define M_RX_TCPHDR_LEN 0x3F 2025 #define V_RX_TCPHDR_LEN(x) ((x) << S_RX_TCPHDR_LEN) 2026 #define G_RX_TCPHDR_LEN(x) (((x) >> S_RX_TCPHDR_LEN) & M_RX_TCPHDR_LEN) 2027 2028 #define S_RX_IPHDR_LEN 6 2029 #define M_RX_IPHDR_LEN 0x3FF 2030 #define V_RX_IPHDR_LEN(x) ((x) << S_RX_IPHDR_LEN) 2031 #define G_RX_IPHDR_LEN(x) (((x) >> S_RX_IPHDR_LEN) & M_RX_IPHDR_LEN) 2032 2033 /* rx_pkt.err_vec fields */ 2034 #define S_RXERR_OR 0 2035 #define V_RXERR_OR(x) ((x) << S_RXERR_OR) 2036 #define F_RXERR_OR V_RXERR_OR(1U) 2037 2038 #define S_RXERR_MAC 1 2039 #define V_RXERR_MAC(x) ((x) << S_RXERR_MAC) 2040 #define F_RXERR_MAC V_RXERR_MAC(1U) 2041 2042 #define S_RXERR_IPVERS 2 2043 #define V_RXERR_IPVERS(x) ((x) << S_RXERR_IPVERS) 2044 #define F_RXERR_IPVERS V_RXERR_IPVERS(1U) 2045 2046 #define S_RXERR_FRAG 3 2047 #define V_RXERR_FRAG(x) ((x) << S_RXERR_FRAG) 2048 #define F_RXERR_FRAG V_RXERR_FRAG(1U) 2049 2050 #define S_RXERR_ATTACK 4 2051 #define V_RXERR_ATTACK(x) ((x) << S_RXERR_ATTACK) 2052 #define F_RXERR_ATTACK V_RXERR_ATTACK(1U) 2053 2054 #define S_RXERR_ETHHDR_LEN 5 2055 #define V_RXERR_ETHHDR_LEN(x) ((x) << S_RXERR_ETHHDR_LEN) 2056 #define F_RXERR_ETHHDR_LEN V_RXERR_ETHHDR_LEN(1U) 2057 2058 #define S_RXERR_IPHDR_LEN 6 2059 #define V_RXERR_IPHDR_LEN(x) ((x) << S_RXERR_IPHDR_LEN) 2060 #define F_RXERR_IPHDR_LEN V_RXERR_IPHDR_LEN(1U) 2061 2062 #define S_RXERR_TCPHDR_LEN 7 2063 #define V_RXERR_TCPHDR_LEN(x) ((x) << S_RXERR_TCPHDR_LEN) 2064 #define F_RXERR_TCPHDR_LEN V_RXERR_TCPHDR_LEN(1U) 2065 2066 #define S_RXERR_PKT_LEN 8 2067 #define V_RXERR_PKT_LEN(x) ((x) << S_RXERR_PKT_LEN) 2068 #define F_RXERR_PKT_LEN V_RXERR_PKT_LEN(1U) 2069 2070 #define S_RXERR_TCP_OPT 9 2071 #define V_RXERR_TCP_OPT(x) ((x) << S_RXERR_TCP_OPT) 2072 #define F_RXERR_TCP_OPT V_RXERR_TCP_OPT(1U) 2073 2074 #define S_RXERR_IPCSUM 12 2075 #define V_RXERR_IPCSUM(x) ((x) << S_RXERR_IPCSUM) 2076 #define F_RXERR_IPCSUM V_RXERR_IPCSUM(1U) 2077 2078 #define S_RXERR_CSUM 13 2079 #define V_RXERR_CSUM(x) ((x) << S_RXERR_CSUM) 2080 #define F_RXERR_CSUM V_RXERR_CSUM(1U) 2081 2082 #define S_RXERR_PING 14 2083 #define V_RXERR_PING(x) ((x) << S_RXERR_PING) 2084 #define F_RXERR_PING V_RXERR_PING(1U) 2085 2086 /* In T6, rx_pkt.err_vec indicates 2087 * RxError Error vector (16b) or 2088 * Encapsulating header length (8b), 2089 * Outer encapsulation type (2b) and 2090 * compressed error vector (6b) if CRxPktEnc is 2091 * enabled in TP_OUT_CONFIG 2092 */ 2093 2094 #define S_T6_COMPR_RXERR_VEC 0 2095 #define M_T6_COMPR_RXERR_VEC 0x3F 2096 #define V_T6_COMPR_RXERR_VEC(x) ((x) << S_T6_COMPR_RXERR_VEC) 2097 #define G_T6_COMPR_RXERR_VEC(x) \ 2098 (((x) >> S_T6_COMPR_RXERR_VEC) & M_T6_COMPR_RXERR_VEC) 2099 2100 #define S_T6_COMPR_RXERR_MAC 0 2101 #define V_T6_COMPR_RXERR_MAC(x) ((x) << S_T6_COMPR_RXERR_MAC) 2102 #define F_T6_COMPR_RXERR_MAC V_T6_COMPR_RXERR_MAC(1U) 2103 2104 /* Logical OR of RX_ERROR_PKT_LEN, RX_ERROR_TCP_HDR_LEN 2105 * RX_ERROR_IP_HDR_LEN, RX_ERROR_ETH_HDR_LEN 2106 */ 2107 #define S_T6_COMPR_RXERR_LEN 1 2108 #define V_T6_COMPR_RXERR_LEN(x) ((x) << S_T6_COMPR_RXERR_LEN) 2109 #define F_T6_COMPR_RXERR_LEN V_COMPR_T6_RXERR_LEN(1U) 2110 2111 #define S_T6_COMPR_RXERR_TCP_OPT 2 2112 #define V_T6_COMPR_RXERR_TCP_OPT(x) ((x) << S_T6_COMPR_RXERR_TCP_OPT) 2113 #define F_T6_COMPR_RXERR_TCP_OPT V_T6_COMPR_RXERR_TCP_OPT(1U) 2114 2115 #define S_T6_COMPR_RXERR_IPV6_EXT 3 2116 #define V_T6_COMPR_RXERR_IPV6_EXT(x) ((x) << S_T6_COMPR_RXERR_IPV6_EXT) 2117 #define F_T6_COMPR_RXERR_IPV6_EXT V_T6_COMPR_RXERR_IPV6_EXT(1U) 2118 2119 /* Logical OR of RX_ERROR_CSUM, RX_ERROR_CSIP */ 2120 #define S_T6_COMPR_RXERR_SUM 4 2121 #define V_T6_COMPR_RXERR_SUM(x) ((x) << S_T6_COMPR_RXERR_SUM) 2122 #define F_T6_COMPR_RXERR_SUM V_T6_COMPR_RXERR_SUM(1U) 2123 2124 /* Logical OR of RX_ERROR_FPMA, RX_ERROR_PING_DROP, 2125 * RX_ERROR_ATTACK, RX_ERROR_FRAG,RX_ERROR_IPVERSION 2126 */ 2127 #define S_T6_COMPR_RXERR_MISC 5 2128 #define V_T6_COMPR_RXERR_MISC(x) ((x) << S_T6_COMPR_RXERR_MISC) 2129 #define F_T6_COMPR_RXERR_MISC V_T6_COMPR_RXERR_MISC(1U) 2130 2131 #define S_T6_RX_TNL_TYPE 6 2132 #define M_T6_RX_TNL_TYPE 0x3 2133 #define V_T6_RX_TNL_TYPE(x) ((x) << S_T6_RX_TNL_TYPE) 2134 #define G_T6_RX_TNL_TYPE(x) (((x) >> S_T6_RX_TNL_TYPE) & M_T6_RX_TNL_TYPE) 2135 2136 #define RX_PKT_TNL_TYPE_NVGRE 1 2137 #define RX_PKT_TNL_TYPE_VXLAN 2 2138 #define RX_PKT_TNL_TYPE_GENEVE 3 2139 2140 #define S_T6_RX_TNLHDR_LEN 8 2141 #define M_T6_RX_TNLHDR_LEN 0xFF 2142 #define V_T6_RX_TNLHDR_LEN(x) ((x) << S_T6_RX_TNLHDR_LEN) 2143 #define G_T6_RX_TNLHDR_LEN(x) (((x) >> S_T6_RX_TNLHDR_LEN) & M_T6_RX_TNLHDR_LEN) 2144 2145 struct cpl_trace_pkt { 2146 RSS_HDR 2147 __u8 opcode; 2148 __u8 intf; 2149 #if defined(__LITTLE_ENDIAN_BITFIELD) 2150 __u8 runt:4; 2151 __u8 filter_hit:4; 2152 __u8 :6; 2153 __u8 err:1; 2154 __u8 trunc:1; 2155 #else 2156 __u8 filter_hit:4; 2157 __u8 runt:4; 2158 __u8 trunc:1; 2159 __u8 err:1; 2160 __u8 :6; 2161 #endif 2162 __be16 rsvd; 2163 __be16 len; 2164 __be64 tstamp; 2165 }; 2166 2167 struct cpl_t5_trace_pkt { 2168 RSS_HDR 2169 __u8 opcode; 2170 __u8 intf; 2171 #if defined(__LITTLE_ENDIAN_BITFIELD) 2172 __u8 runt:4; 2173 __u8 filter_hit:4; 2174 __u8 :6; 2175 __u8 err:1; 2176 __u8 trunc:1; 2177 #else 2178 __u8 filter_hit:4; 2179 __u8 runt:4; 2180 __u8 trunc:1; 2181 __u8 err:1; 2182 __u8 :6; 2183 #endif 2184 __be16 rsvd; 2185 __be16 len; 2186 __be64 tstamp; 2187 __be64 rsvd1; 2188 }; 2189 2190 struct cpl_rte_delete_req { 2191 WR_HDR; 2192 union opcode_tid ot; 2193 __be32 params; 2194 }; 2195 2196 /* {cpl_rte_delete_req, cpl_rte_read_req}.params fields */ 2197 #define S_RTE_REQ_LUT_IX 8 2198 #define M_RTE_REQ_LUT_IX 0x7FF 2199 #define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX) 2200 #define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX) 2201 2202 #define S_RTE_REQ_LUT_BASE 19 2203 #define M_RTE_REQ_LUT_BASE 0x7FF 2204 #define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE) 2205 #define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE) 2206 2207 #define S_RTE_READ_REQ_SELECT 31 2208 #define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT) 2209 #define F_RTE_READ_REQ_SELECT V_RTE_READ_REQ_SELECT(1U) 2210 2211 struct cpl_rte_delete_rpl { 2212 RSS_HDR 2213 union opcode_tid ot; 2214 __u8 status; 2215 __u8 rsvd[3]; 2216 }; 2217 2218 struct cpl_rte_write_req { 2219 WR_HDR; 2220 union opcode_tid ot; 2221 __u32 write_sel; 2222 __be32 lut_params; 2223 __be32 l2t_idx; 2224 __be32 netmask; 2225 __be32 faddr; 2226 }; 2227 2228 /* cpl_rte_write_req.write_sel fields */ 2229 #define S_RTE_WR_L2TIDX 31 2230 #define V_RTE_WR_L2TIDX(x) ((x) << S_RTE_WR_L2TIDX) 2231 #define F_RTE_WR_L2TIDX V_RTE_WR_L2TIDX(1U) 2232 2233 #define S_RTE_WR_FADDR 30 2234 #define V_RTE_WR_FADDR(x) ((x) << S_RTE_WR_FADDR) 2235 #define F_RTE_WR_FADDR V_RTE_WR_FADDR(1U) 2236 2237 /* cpl_rte_write_req.lut_params fields */ 2238 #define S_RTE_WR_LUT_IX 10 2239 #define M_RTE_WR_LUT_IX 0x7FF 2240 #define V_RTE_WR_LUT_IX(x) ((x) << S_RTE_WR_LUT_IX) 2241 #define G_RTE_WR_LUT_IX(x) (((x) >> S_RTE_WR_LUT_IX) & M_RTE_WR_LUT_IX) 2242 2243 #define S_RTE_WR_LUT_BASE 21 2244 #define M_RTE_WR_LUT_BASE 0x7FF 2245 #define V_RTE_WR_LUT_BASE(x) ((x) << S_RTE_WR_LUT_BASE) 2246 #define G_RTE_WR_LUT_BASE(x) (((x) >> S_RTE_WR_LUT_BASE) & M_RTE_WR_LUT_BASE) 2247 2248 struct cpl_rte_write_rpl { 2249 RSS_HDR 2250 union opcode_tid ot; 2251 __u8 status; 2252 __u8 rsvd[3]; 2253 }; 2254 2255 struct cpl_rte_read_req { 2256 WR_HDR; 2257 union opcode_tid ot; 2258 __be32 params; 2259 }; 2260 2261 struct cpl_rte_read_rpl { 2262 RSS_HDR 2263 union opcode_tid ot; 2264 __u8 status; 2265 __u8 rsvd; 2266 __be16 l2t_idx; 2267 #if defined(__LITTLE_ENDIAN_BITFIELD) 2268 __u32 :30; 2269 __u32 select:1; 2270 #else 2271 __u32 select:1; 2272 __u32 :30; 2273 #endif 2274 __be32 addr; 2275 }; 2276 2277 struct cpl_l2t_write_req { 2278 WR_HDR; 2279 union opcode_tid ot; 2280 __be16 params; 2281 __be16 l2t_idx; 2282 __be16 vlan; 2283 __u8 dst_mac[6]; 2284 }; 2285 2286 /* cpl_l2t_write_req.params fields */ 2287 #define S_L2T_W_INFO 2 2288 #define M_L2T_W_INFO 0x3F 2289 #define V_L2T_W_INFO(x) ((x) << S_L2T_W_INFO) 2290 #define G_L2T_W_INFO(x) (((x) >> S_L2T_W_INFO) & M_L2T_W_INFO) 2291 2292 #define S_L2T_W_PORT 8 2293 #define M_L2T_W_PORT 0x3 2294 #define V_L2T_W_PORT(x) ((x) << S_L2T_W_PORT) 2295 #define G_L2T_W_PORT(x) (((x) >> S_L2T_W_PORT) & M_L2T_W_PORT) 2296 2297 #define S_L2T_W_LPBK 10 2298 #define V_L2T_W_LPBK(x) ((x) << S_L2T_W_LPBK) 2299 #define F_L2T_W_PKBK V_L2T_W_LPBK(1U) 2300 2301 #define S_L2T_W_ARPMISS 11 2302 #define V_L2T_W_ARPMISS(x) ((x) << S_L2T_W_ARPMISS) 2303 #define F_L2T_W_ARPMISS V_L2T_W_ARPMISS(1U) 2304 2305 #define S_L2T_W_NOREPLY 15 2306 #define V_L2T_W_NOREPLY(x) ((x) << S_L2T_W_NOREPLY) 2307 #define F_L2T_W_NOREPLY V_L2T_W_NOREPLY(1U) 2308 2309 #define CPL_L2T_VLAN_NONE 0xfff 2310 2311 struct cpl_l2t_write_rpl { 2312 RSS_HDR 2313 union opcode_tid ot; 2314 __u8 status; 2315 __u8 rsvd[3]; 2316 }; 2317 2318 struct cpl_l2t_read_req { 2319 WR_HDR; 2320 union opcode_tid ot; 2321 __be32 l2t_idx; 2322 }; 2323 2324 struct cpl_l2t_read_rpl { 2325 RSS_HDR 2326 union opcode_tid ot; 2327 __u8 status; 2328 #if defined(__LITTLE_ENDIAN_BITFIELD) 2329 __u8 :4; 2330 __u8 iff:4; 2331 #else 2332 __u8 iff:4; 2333 __u8 :4; 2334 #endif 2335 __be16 vlan; 2336 __be16 info; 2337 __u8 dst_mac[6]; 2338 }; 2339 2340 struct cpl_srq_table_req { 2341 WR_HDR; 2342 union opcode_tid ot; 2343 __u8 status; 2344 __u8 rsvd[2]; 2345 __u8 idx; 2346 __be64 rsvd_pdid; 2347 __be32 qlen_qbase; 2348 __be16 cur_msn; 2349 __be16 max_msn; 2350 }; 2351 2352 struct cpl_srq_table_rpl { 2353 RSS_HDR 2354 union opcode_tid ot; 2355 __u8 status; 2356 __u8 rsvd[2]; 2357 __u8 idx; 2358 __be64 rsvd_pdid; 2359 __be32 qlen_qbase; 2360 __be16 cur_msn; 2361 __be16 max_msn; 2362 }; 2363 2364 /* cpl_srq_table_{req,rpl}.params fields */ 2365 #define S_SRQT_QLEN 28 2366 #define M_SRQT_QLEN 0xF 2367 #define V_SRQT_QLEN(x) ((x) << S_SRQT_QLEN) 2368 #define G_SRQT_QLEN(x) (((x) >> S_SRQT_QLEN) & M_SRQT_QLEN) 2369 2370 #define S_SRQT_QBASE 0 2371 #define M_SRQT_QBASE 0x3FFFFFF 2372 #define V_SRQT_QBASE(x) ((x) << S_SRQT_QBASE) 2373 #define G_SRQT_QBASE(x) (((x) >> S_SRQT_QBASE) & M_SRQT_QBASE) 2374 2375 #define S_SRQT_PDID 0 2376 #define M_SRQT_PDID 0xFF 2377 #define V_SRQT_PDID(x) ((x) << S_SRQT_PDID) 2378 #define G_SRQT_PDID(x) (((x) >> S_SRQT_PDID) & M_SRQT_PDID) 2379 2380 #define S_SRQT_IDX 0 2381 #define M_SRQT_IDX 0xF 2382 #define V_SRQT_IDX(x) ((x) << S_SRQT_IDX) 2383 #define G_SRQT_IDX(x) (((x) >> S_SRQT_IDX) & M_SRQT_IDX) 2384 2385 struct cpl_smt_write_req { 2386 WR_HDR; 2387 union opcode_tid ot; 2388 __be32 params; 2389 __be16 pfvf1; 2390 __u8 src_mac1[6]; 2391 __be16 pfvf0; 2392 __u8 src_mac0[6]; 2393 }; 2394 2395 struct cpl_t6_smt_write_req { 2396 WR_HDR; 2397 union opcode_tid ot; 2398 __be32 params; 2399 __be64 tag; 2400 __be16 pfvf0; 2401 __u8 src_mac0[6]; 2402 __be32 local_ip; 2403 __be32 rsvd; 2404 }; 2405 2406 struct cpl_smt_write_rpl { 2407 RSS_HDR 2408 union opcode_tid ot; 2409 __u8 status; 2410 __u8 rsvd[3]; 2411 }; 2412 2413 struct cpl_smt_read_req { 2414 WR_HDR; 2415 union opcode_tid ot; 2416 __be32 params; 2417 }; 2418 2419 struct cpl_smt_read_rpl { 2420 RSS_HDR 2421 union opcode_tid ot; 2422 __u8 status; 2423 __u8 ovlan_idx; 2424 __be16 rsvd; 2425 __be16 pfvf1; 2426 __u8 src_mac1[6]; 2427 __be16 pfvf0; 2428 __u8 src_mac0[6]; 2429 }; 2430 2431 /* cpl_smt_{read,write}_req.params fields */ 2432 #define S_SMTW_OVLAN_IDX 16 2433 #define M_SMTW_OVLAN_IDX 0xF 2434 #define V_SMTW_OVLAN_IDX(x) ((x) << S_SMTW_OVLAN_IDX) 2435 #define G_SMTW_OVLAN_IDX(x) (((x) >> S_SMTW_OVLAN_IDX) & M_SMTW_OVLAN_IDX) 2436 2437 #define S_SMTW_IDX 20 2438 #define M_SMTW_IDX 0x7F 2439 #define V_SMTW_IDX(x) ((x) << S_SMTW_IDX) 2440 #define G_SMTW_IDX(x) (((x) >> S_SMTW_IDX) & M_SMTW_IDX) 2441 2442 #define M_T6_SMTW_IDX 0xFF 2443 #define G_T6_SMTW_IDX(x) (((x) >> S_SMTW_IDX) & M_T6_SMTW_IDX) 2444 2445 #define S_SMTW_NORPL 31 2446 #define V_SMTW_NORPL(x) ((x) << S_SMTW_NORPL) 2447 #define F_SMTW_NORPL V_SMTW_NORPL(1U) 2448 2449 /* cpl_smt_{read,write}_req.pfvf? fields */ 2450 #define S_SMTW_VF 0 2451 #define M_SMTW_VF 0xFF 2452 #define V_SMTW_VF(x) ((x) << S_SMTW_VF) 2453 #define G_SMTW_VF(x) (((x) >> S_SMTW_VF) & M_SMTW_VF) 2454 2455 #define S_SMTW_PF 8 2456 #define M_SMTW_PF 0x7 2457 #define V_SMTW_PF(x) ((x) << S_SMTW_PF) 2458 #define G_SMTW_PF(x) (((x) >> S_SMTW_PF) & M_SMTW_PF) 2459 2460 #define S_SMTW_VF_VLD 11 2461 #define V_SMTW_VF_VLD(x) ((x) << S_SMTW_VF_VLD) 2462 #define F_SMTW_VF_VLD V_SMTW_VF_VLD(1U) 2463 2464 struct cpl_tag_write_req { 2465 WR_HDR; 2466 union opcode_tid ot; 2467 __be32 params; 2468 __be64 tag_val; 2469 }; 2470 2471 struct cpl_tag_write_rpl { 2472 RSS_HDR 2473 union opcode_tid ot; 2474 __u8 status; 2475 __u8 rsvd[2]; 2476 __u8 idx; 2477 }; 2478 2479 struct cpl_tag_read_req { 2480 WR_HDR; 2481 union opcode_tid ot; 2482 __be32 params; 2483 }; 2484 2485 struct cpl_tag_read_rpl { 2486 RSS_HDR 2487 union opcode_tid ot; 2488 __u8 status; 2489 #if defined(__LITTLE_ENDIAN_BITFIELD) 2490 __u8 :4; 2491 __u8 tag_len:1; 2492 __u8 :2; 2493 __u8 ins_enable:1; 2494 #else 2495 __u8 ins_enable:1; 2496 __u8 :2; 2497 __u8 tag_len:1; 2498 __u8 :4; 2499 #endif 2500 __u8 rsvd; 2501 __u8 tag_idx; 2502 __be64 tag_val; 2503 }; 2504 2505 /* cpl_tag{read,write}_req.params fields */ 2506 #define S_TAGW_IDX 0 2507 #define M_TAGW_IDX 0x7F 2508 #define V_TAGW_IDX(x) ((x) << S_TAGW_IDX) 2509 #define G_TAGW_IDX(x) (((x) >> S_TAGW_IDX) & M_TAGW_IDX) 2510 2511 #define S_TAGW_LEN 20 2512 #define V_TAGW_LEN(x) ((x) << S_TAGW_LEN) 2513 #define F_TAGW_LEN V_TAGW_LEN(1U) 2514 2515 #define S_TAGW_INS_ENABLE 23 2516 #define V_TAGW_INS_ENABLE(x) ((x) << S_TAGW_INS_ENABLE) 2517 #define F_TAGW_INS_ENABLE V_TAGW_INS_ENABLE(1U) 2518 2519 #define S_TAGW_NORPL 31 2520 #define V_TAGW_NORPL(x) ((x) << S_TAGW_NORPL) 2521 #define F_TAGW_NORPL V_TAGW_NORPL(1U) 2522 2523 struct cpl_barrier { 2524 WR_HDR; 2525 __u8 opcode; 2526 __u8 chan_map; 2527 __be16 rsvd0; 2528 __be32 rsvd1; 2529 }; 2530 2531 /* cpl_barrier.chan_map fields */ 2532 #define S_CHAN_MAP 4 2533 #define M_CHAN_MAP 0xF 2534 #define V_CHAN_MAP(x) ((x) << S_CHAN_MAP) 2535 #define G_CHAN_MAP(x) (((x) >> S_CHAN_MAP) & M_CHAN_MAP) 2536 2537 struct cpl_error { 2538 RSS_HDR 2539 union opcode_tid ot; 2540 __be32 error; 2541 }; 2542 2543 struct cpl_hit_notify { 2544 RSS_HDR 2545 union opcode_tid ot; 2546 __be32 rsvd; 2547 __be32 info; 2548 __be32 reason; 2549 }; 2550 2551 struct cpl_pkt_notify { 2552 RSS_HDR 2553 union opcode_tid ot; 2554 __be16 rsvd; 2555 __be16 len; 2556 __be32 info; 2557 __be32 reason; 2558 }; 2559 2560 /* cpl_{hit,pkt}_notify.info fields */ 2561 #define S_NTFY_MAC_IDX 0 2562 #define M_NTFY_MAC_IDX 0x1FF 2563 #define V_NTFY_MAC_IDX(x) ((x) << S_NTFY_MAC_IDX) 2564 #define G_NTFY_MAC_IDX(x) (((x) >> S_NTFY_MAC_IDX) & M_NTFY_MAC_IDX) 2565 2566 #define S_NTFY_INTF 10 2567 #define M_NTFY_INTF 0xF 2568 #define V_NTFY_INTF(x) ((x) << S_NTFY_INTF) 2569 #define G_NTFY_INTF(x) (((x) >> S_NTFY_INTF) & M_NTFY_INTF) 2570 2571 #define S_NTFY_TCPHDR_LEN 14 2572 #define M_NTFY_TCPHDR_LEN 0xF 2573 #define V_NTFY_TCPHDR_LEN(x) ((x) << S_NTFY_TCPHDR_LEN) 2574 #define G_NTFY_TCPHDR_LEN(x) (((x) >> S_NTFY_TCPHDR_LEN) & M_NTFY_TCPHDR_LEN) 2575 2576 #define S_NTFY_IPHDR_LEN 18 2577 #define M_NTFY_IPHDR_LEN 0x1FF 2578 #define V_NTFY_IPHDR_LEN(x) ((x) << S_NTFY_IPHDR_LEN) 2579 #define G_NTFY_IPHDR_LEN(x) (((x) >> S_NTFY_IPHDR_LEN) & M_NTFY_IPHDR_LEN) 2580 2581 #define S_NTFY_ETHHDR_LEN 27 2582 #define M_NTFY_ETHHDR_LEN 0x1F 2583 #define V_NTFY_ETHHDR_LEN(x) ((x) << S_NTFY_ETHHDR_LEN) 2584 #define G_NTFY_ETHHDR_LEN(x) (((x) >> S_NTFY_ETHHDR_LEN) & M_NTFY_ETHHDR_LEN) 2585 2586 #define S_NTFY_T5_IPHDR_LEN 18 2587 #define M_NTFY_T5_IPHDR_LEN 0xFF 2588 #define V_NTFY_T5_IPHDR_LEN(x) ((x) << S_NTFY_T5_IPHDR_LEN) 2589 #define G_NTFY_T5_IPHDR_LEN(x) (((x) >> S_NTFY_T5_IPHDR_LEN) & M_NTFY_T5_IPHDR_LEN) 2590 2591 #define S_NTFY_T5_ETHHDR_LEN 26 2592 #define M_NTFY_T5_ETHHDR_LEN 0x3F 2593 #define V_NTFY_T5_ETHHDR_LEN(x) ((x) << S_NTFY_T5_ETHHDR_LEN) 2594 #define G_NTFY_T5_ETHHDR_LEN(x) (((x) >> S_NTFY_T5_ETHHDR_LEN) & M_NTFY_T5_ETHHDR_LEN) 2595 2596 struct cpl_rdma_terminate { 2597 RSS_HDR 2598 union opcode_tid ot; 2599 __be16 rsvd; 2600 __be16 len; 2601 }; 2602 2603 struct cpl_set_le_req { 2604 WR_HDR; 2605 union opcode_tid ot; 2606 __be16 reply_ctrl; 2607 __be16 params; 2608 __be64 mask_hi; 2609 __be64 mask_lo; 2610 __be64 val_hi; 2611 __be64 val_lo; 2612 }; 2613 2614 /* cpl_set_le_req.reply_ctrl additional fields */ 2615 #define S_LE_REQ_IP6 13 2616 #define V_LE_REQ_IP6(x) ((x) << S_LE_REQ_IP6) 2617 #define F_LE_REQ_IP6 V_LE_REQ_IP6(1U) 2618 2619 /* cpl_set_le_req.params fields */ 2620 #define S_LE_CHAN 0 2621 #define M_LE_CHAN 0x3 2622 #define V_LE_CHAN(x) ((x) << S_LE_CHAN) 2623 #define G_LE_CHAN(x) (((x) >> S_LE_CHAN) & M_LE_CHAN) 2624 2625 #define S_LE_OFFSET 5 2626 #define M_LE_OFFSET 0x7 2627 #define V_LE_OFFSET(x) ((x) << S_LE_OFFSET) 2628 #define G_LE_OFFSET(x) (((x) >> S_LE_OFFSET) & M_LE_OFFSET) 2629 2630 #define S_LE_MORE 8 2631 #define V_LE_MORE(x) ((x) << S_LE_MORE) 2632 #define F_LE_MORE V_LE_MORE(1U) 2633 2634 #define S_LE_REQSIZE 9 2635 #define M_LE_REQSIZE 0x7 2636 #define V_LE_REQSIZE(x) ((x) << S_LE_REQSIZE) 2637 #define G_LE_REQSIZE(x) (((x) >> S_LE_REQSIZE) & M_LE_REQSIZE) 2638 2639 #define S_LE_REQCMD 12 2640 #define M_LE_REQCMD 0xF 2641 #define V_LE_REQCMD(x) ((x) << S_LE_REQCMD) 2642 #define G_LE_REQCMD(x) (((x) >> S_LE_REQCMD) & M_LE_REQCMD) 2643 2644 struct cpl_set_le_rpl { 2645 RSS_HDR 2646 union opcode_tid ot; 2647 __u8 chan; 2648 __u8 info; 2649 __be16 len; 2650 }; 2651 2652 /* cpl_set_le_rpl.info fields */ 2653 #define S_LE_RSPCMD 0 2654 #define M_LE_RSPCMD 0xF 2655 #define V_LE_RSPCMD(x) ((x) << S_LE_RSPCMD) 2656 #define G_LE_RSPCMD(x) (((x) >> S_LE_RSPCMD) & M_LE_RSPCMD) 2657 2658 #define S_LE_RSPSIZE 4 2659 #define M_LE_RSPSIZE 0x7 2660 #define V_LE_RSPSIZE(x) ((x) << S_LE_RSPSIZE) 2661 #define G_LE_RSPSIZE(x) (((x) >> S_LE_RSPSIZE) & M_LE_RSPSIZE) 2662 2663 #define S_LE_RSPTYPE 7 2664 #define V_LE_RSPTYPE(x) ((x) << S_LE_RSPTYPE) 2665 #define F_LE_RSPTYPE V_LE_RSPTYPE(1U) 2666 2667 struct cpl_sge_egr_update { 2668 RSS_HDR 2669 __be32 opcode_qid; 2670 __be16 cidx; 2671 __be16 pidx; 2672 }; 2673 2674 /* cpl_sge_egr_update.ot fields */ 2675 #define S_AUTOEQU 22 2676 #define M_AUTOEQU 0x1 2677 #define V_AUTOEQU(x) ((x) << S_AUTOEQU) 2678 #define G_AUTOEQU(x) (((x) >> S_AUTOEQU) & M_AUTOEQU) 2679 2680 #define S_EGR_QID 0 2681 #define M_EGR_QID 0x1FFFF 2682 #define V_EGR_QID(x) ((x) << S_EGR_QID) 2683 #define G_EGR_QID(x) (((x) >> S_EGR_QID) & M_EGR_QID) 2684 2685 /* cpl_fw*.type values */ 2686 enum { 2687 FW_TYPE_CMD_RPL = 0, 2688 FW_TYPE_WR_RPL = 1, 2689 FW_TYPE_CQE = 2, 2690 FW_TYPE_OFLD_CONNECTION_WR_RPL = 3, 2691 FW_TYPE_RSSCPL = 4, 2692 FW_TYPE_WRERR_RPL = 5, 2693 FW_TYPE_PI_ERR = 6, 2694 FW_TYPE_TLS_KEY = 7, 2695 }; 2696 2697 struct cpl_fw2_pld { 2698 RSS_HDR 2699 u8 opcode; 2700 u8 rsvd[5]; 2701 __be16 len; 2702 }; 2703 2704 struct cpl_fw4_pld { 2705 RSS_HDR 2706 u8 opcode; 2707 u8 rsvd0[3]; 2708 u8 type; 2709 u8 rsvd1; 2710 __be16 len; 2711 __be64 data; 2712 __be64 rsvd2; 2713 }; 2714 2715 struct cpl_fw6_pld { 2716 RSS_HDR 2717 u8 opcode; 2718 u8 rsvd[5]; 2719 __be16 len; 2720 __be64 data[4]; 2721 }; 2722 2723 struct cpl_fw2_msg { 2724 RSS_HDR 2725 union opcode_info oi; 2726 }; 2727 2728 struct cpl_fw4_msg { 2729 RSS_HDR 2730 u8 opcode; 2731 u8 type; 2732 __be16 rsvd0; 2733 __be32 rsvd1; 2734 __be64 data[2]; 2735 }; 2736 2737 struct cpl_fw4_ack { 2738 RSS_HDR 2739 union opcode_tid ot; 2740 u8 credits; 2741 u8 rsvd0[2]; 2742 u8 flags; 2743 __be32 snd_nxt; 2744 __be32 snd_una; 2745 __be64 rsvd1; 2746 }; 2747 2748 enum { 2749 CPL_FW4_ACK_FLAGS_SEQVAL = 0x1, /* seqn valid */ 2750 CPL_FW4_ACK_FLAGS_CH = 0x2, /* channel change complete */ 2751 CPL_FW4_ACK_FLAGS_FLOWC = 0x4, /* fw_flowc_wr complete */ 2752 }; 2753 2754 #define S_CPL_FW4_ACK_OPCODE 24 2755 #define M_CPL_FW4_ACK_OPCODE 0xff 2756 #define V_CPL_FW4_ACK_OPCODE(x) ((x) << S_CPL_FW4_ACK_OPCODE) 2757 #define G_CPL_FW4_ACK_OPCODE(x) \ 2758 (((x) >> S_CPL_FW4_ACK_OPCODE) & M_CPL_FW4_ACK_OPCODE) 2759 2760 #define S_CPL_FW4_ACK_FLOWID 0 2761 #define M_CPL_FW4_ACK_FLOWID 0xffffff 2762 #define V_CPL_FW4_ACK_FLOWID(x) ((x) << S_CPL_FW4_ACK_FLOWID) 2763 #define G_CPL_FW4_ACK_FLOWID(x) \ 2764 (((x) >> S_CPL_FW4_ACK_FLOWID) & M_CPL_FW4_ACK_FLOWID) 2765 2766 #define S_CPL_FW4_ACK_CR 24 2767 #define M_CPL_FW4_ACK_CR 0xff 2768 #define V_CPL_FW4_ACK_CR(x) ((x) << S_CPL_FW4_ACK_CR) 2769 #define G_CPL_FW4_ACK_CR(x) (((x) >> S_CPL_FW4_ACK_CR) & M_CPL_FW4_ACK_CR) 2770 2771 #define S_CPL_FW4_ACK_SEQVAL 0 2772 #define M_CPL_FW4_ACK_SEQVAL 0x1 2773 #define V_CPL_FW4_ACK_SEQVAL(x) ((x) << S_CPL_FW4_ACK_SEQVAL) 2774 #define G_CPL_FW4_ACK_SEQVAL(x) \ 2775 (((x) >> S_CPL_FW4_ACK_SEQVAL) & M_CPL_FW4_ACK_SEQVAL) 2776 #define F_CPL_FW4_ACK_SEQVAL V_CPL_FW4_ACK_SEQVAL(1U) 2777 2778 struct cpl_fw6_msg { 2779 RSS_HDR 2780 u8 opcode; 2781 u8 type; 2782 __be16 rsvd0; 2783 __be32 rsvd1; 2784 __be64 data[4]; 2785 }; 2786 2787 /* cpl_fw6_msg.type values */ 2788 enum { 2789 FW6_TYPE_CMD_RPL = FW_TYPE_CMD_RPL, 2790 FW6_TYPE_WR_RPL = FW_TYPE_WR_RPL, 2791 FW6_TYPE_CQE = FW_TYPE_CQE, 2792 FW6_TYPE_OFLD_CONNECTION_WR_RPL = FW_TYPE_OFLD_CONNECTION_WR_RPL, 2793 FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL, 2794 FW6_TYPE_WRERR_RPL = FW_TYPE_WRERR_RPL, 2795 FW6_TYPE_PI_ERR = FW_TYPE_PI_ERR, 2796 NUM_FW6_TYPES 2797 }; 2798 2799 struct cpl_fw6_msg_ofld_connection_wr_rpl { 2800 __u64 cookie; 2801 __be32 tid; /* or atid in case of active failure */ 2802 __u8 t_state; 2803 __u8 retval; 2804 __u8 rsvd[2]; 2805 }; 2806 2807 /* ULP_TX opcodes */ 2808 enum { 2809 ULP_TX_MEM_READ = 2, 2810 ULP_TX_MEM_WRITE = 3, 2811 ULP_TX_PKT = 4 2812 }; 2813 2814 enum { 2815 ULP_TX_SC_NOOP = 0x80, 2816 ULP_TX_SC_IMM = 0x81, 2817 ULP_TX_SC_DSGL = 0x82, 2818 ULP_TX_SC_ISGL = 0x83, 2819 ULP_TX_SC_PICTRL = 0x84, 2820 ULP_TX_SC_MEMRD = 0x86 2821 }; 2822 2823 #define S_ULPTX_CMD 24 2824 #define M_ULPTX_CMD 0xFF 2825 #define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD) 2826 2827 #define S_ULPTX_LEN16 0 2828 #define M_ULPTX_LEN16 0xFF 2829 #define V_ULPTX_LEN16(x) ((x) << S_ULPTX_LEN16) 2830 2831 #define S_ULP_TX_SC_MORE 23 2832 #define V_ULP_TX_SC_MORE(x) ((x) << S_ULP_TX_SC_MORE) 2833 #define F_ULP_TX_SC_MORE V_ULP_TX_SC_MORE(1U) 2834 2835 struct ulptx_sge_pair { 2836 __be32 len[2]; 2837 __be64 addr[2]; 2838 }; 2839 2840 struct ulptx_sgl { 2841 __be32 cmd_nsge; 2842 __be32 len0; 2843 __be64 addr0; 2844 #if !(defined C99_NOT_SUPPORTED) 2845 struct ulptx_sge_pair sge[0]; 2846 #endif 2847 }; 2848 2849 struct ulptx_isge { 2850 __be32 stag; 2851 __be32 len; 2852 __be64 target_ofst; 2853 }; 2854 2855 struct ulptx_isgl { 2856 __be32 cmd_nisge; 2857 __be32 rsvd; 2858 #if !(defined C99_NOT_SUPPORTED) 2859 struct ulptx_isge sge[0]; 2860 #endif 2861 }; 2862 2863 struct ulptx_idata { 2864 __be32 cmd_more; 2865 __be32 len; 2866 }; 2867 2868 #define S_ULPTX_NSGE 0 2869 #define M_ULPTX_NSGE 0xFFFF 2870 #define V_ULPTX_NSGE(x) ((x) << S_ULPTX_NSGE) 2871 #define G_ULPTX_NSGE(x) (((x) >> S_ULPTX_NSGE) & M_ULPTX_NSGE) 2872 2873 struct ulptx_sc_memrd { 2874 __be32 cmd_to_len; 2875 __be32 addr; 2876 }; 2877 2878 struct ulp_mem_io { 2879 WR_HDR; 2880 __be32 cmd; 2881 __be32 len16; /* command length */ 2882 __be32 dlen; /* data length in 32-byte units */ 2883 __be32 lock_addr; 2884 }; 2885 2886 /* additional ulp_mem_io.cmd fields */ 2887 #define S_ULP_MEMIO_ORDER 23 2888 #define V_ULP_MEMIO_ORDER(x) ((x) << S_ULP_MEMIO_ORDER) 2889 #define F_ULP_MEMIO_ORDER V_ULP_MEMIO_ORDER(1U) 2890 2891 #define S_T5_ULP_MEMIO_IMM 23 2892 #define V_T5_ULP_MEMIO_IMM(x) ((x) << S_T5_ULP_MEMIO_IMM) 2893 #define F_T5_ULP_MEMIO_IMM V_T5_ULP_MEMIO_IMM(1U) 2894 2895 #define S_T5_ULP_MEMIO_ORDER 22 2896 #define V_T5_ULP_MEMIO_ORDER(x) ((x) << S_T5_ULP_MEMIO_ORDER) 2897 #define F_T5_ULP_MEMIO_ORDER V_T5_ULP_MEMIO_ORDER(1U) 2898 2899 #define S_T5_ULP_MEMIO_FID 4 2900 #define M_T5_ULP_MEMIO_FID 0x7ff 2901 #define V_T5_ULP_MEMIO_FID(x) ((x) << S_T5_ULP_MEMIO_FID) 2902 2903 /* ulp_mem_io.lock_addr fields */ 2904 #define S_ULP_MEMIO_ADDR 0 2905 #define M_ULP_MEMIO_ADDR 0x7FFFFFF 2906 #define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR) 2907 2908 #define S_ULP_MEMIO_LOCK 31 2909 #define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK) 2910 #define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U) 2911 2912 /* ulp_mem_io.dlen fields */ 2913 #define S_ULP_MEMIO_DATA_LEN 0 2914 #define M_ULP_MEMIO_DATA_LEN 0x1F 2915 #define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN) 2916 2917 /* ULP_TXPKT field values */ 2918 enum { 2919 ULP_TXPKT_DEST_TP = 0, 2920 ULP_TXPKT_DEST_SGE, 2921 ULP_TXPKT_DEST_UP, 2922 ULP_TXPKT_DEST_DEVNULL, 2923 }; 2924 2925 struct ulp_txpkt { 2926 __be32 cmd_dest; 2927 __be32 len; 2928 }; 2929 2930 /* ulp_txpkt.cmd_dest fields */ 2931 #define S_ULP_TXPKT_DATAMODIFY 23 2932 #define M_ULP_TXPKT_DATAMODIFY 0x1 2933 #define V_ULP_TXPKT_DATAMODIFY(x) ((x) << S_ULP_TXPKT_DATAMODIFY) 2934 #define G_ULP_TXPKT_DATAMODIFY(x) \ 2935 (((x) >> S_ULP_TXPKT_DATAMODIFY) & M_ULP_TXPKT_DATAMODIFY_) 2936 #define F_ULP_TXPKT_DATAMODIFY V_ULP_TXPKT_DATAMODIFY(1U) 2937 2938 #define S_ULP_TXPKT_CHANNELID 22 2939 #define M_ULP_TXPKT_CHANNELID 0x1 2940 #define V_ULP_TXPKT_CHANNELID(x) ((x) << S_ULP_TXPKT_CHANNELID) 2941 #define G_ULP_TXPKT_CHANNELID(x) \ 2942 (((x) >> S_ULP_TXPKT_CHANNELID) & M_ULP_TXPKT_CHANNELID) 2943 #define F_ULP_TXPKT_CHANNELID V_ULP_TXPKT_CHANNELID(1U) 2944 2945 /* ulp_txpkt.cmd_dest fields */ 2946 #define S_ULP_TXPKT_DEST 16 2947 #define M_ULP_TXPKT_DEST 0x3 2948 #define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST) 2949 2950 #define S_ULP_TXPKT_FID 4 2951 #define M_ULP_TXPKT_FID 0x7ff 2952 #define V_ULP_TXPKT_FID(x) ((x) << S_ULP_TXPKT_FID) 2953 2954 #define S_ULP_TXPKT_RO 3 2955 #define V_ULP_TXPKT_RO(x) ((x) << S_ULP_TXPKT_RO) 2956 #define F_ULP_TXPKT_RO V_ULP_TXPKT_RO(1U) 2957 2958 enum cpl_tx_tnl_lso_type { 2959 TX_TNL_TYPE_OPAQUE, 2960 TX_TNL_TYPE_NVGRE, 2961 TX_TNL_TYPE_VXLAN, 2962 TX_TNL_TYPE_GENEVE, 2963 }; 2964 2965 struct cpl_tx_tnl_lso { 2966 __be32 op_to_IpIdSplitOut; 2967 __be16 IpIdOffsetOut; 2968 __be16 UdpLenSetOut_to_TnlHdrLen; 2969 __be64 r1; 2970 __be32 Flow_to_TcpHdrLen; 2971 __be16 IpIdOffset; 2972 __be16 IpIdSplit_to_Mss; 2973 __be32 TCPSeqOffset; 2974 __be32 EthLenOffset_Size; 2975 /* encapsulated CPL (TX_PKT_XT) follows here */ 2976 }; 2977 2978 #define S_CPL_TX_TNL_LSO_OPCODE 24 2979 #define M_CPL_TX_TNL_LSO_OPCODE 0xff 2980 #define V_CPL_TX_TNL_LSO_OPCODE(x) ((x) << S_CPL_TX_TNL_LSO_OPCODE) 2981 #define G_CPL_TX_TNL_LSO_OPCODE(x) \ 2982 (((x) >> S_CPL_TX_TNL_LSO_OPCODE) & M_CPL_TX_TNL_LSO_OPCODE) 2983 2984 #define S_CPL_TX_TNL_LSO_FIRST 23 2985 #define M_CPL_TX_TNL_LSO_FIRST 0x1 2986 #define V_CPL_TX_TNL_LSO_FIRST(x) ((x) << S_CPL_TX_TNL_LSO_FIRST) 2987 #define G_CPL_TX_TNL_LSO_FIRST(x) \ 2988 (((x) >> S_CPL_TX_TNL_LSO_FIRST) & M_CPL_TX_TNL_LSO_FIRST) 2989 #define F_CPL_TX_TNL_LSO_FIRST V_CPL_TX_TNL_LSO_FIRST(1U) 2990 2991 #define S_CPL_TX_TNL_LSO_LAST 22 2992 #define M_CPL_TX_TNL_LSO_LAST 0x1 2993 #define V_CPL_TX_TNL_LSO_LAST(x) ((x) << S_CPL_TX_TNL_LSO_LAST) 2994 #define G_CPL_TX_TNL_LSO_LAST(x) \ 2995 (((x) >> S_CPL_TX_TNL_LSO_LAST) & M_CPL_TX_TNL_LSO_LAST) 2996 #define F_CPL_TX_TNL_LSO_LAST V_CPL_TX_TNL_LSO_LAST(1U) 2997 2998 #define S_CPL_TX_TNL_LSO_ETHHDRLENXOUT 21 2999 #define M_CPL_TX_TNL_LSO_ETHHDRLENXOUT 0x1 3000 #define V_CPL_TX_TNL_LSO_ETHHDRLENXOUT(x) \ 3001 ((x) << S_CPL_TX_TNL_LSO_ETHHDRLENXOUT) 3002 #define G_CPL_TX_TNL_LSO_ETHHDRLENXOUT(x) \ 3003 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLENXOUT) & M_CPL_TX_TNL_LSO_ETHHDRLENXOUT) 3004 #define F_CPL_TX_TNL_LSO_ETHHDRLENXOUT V_CPL_TX_TNL_LSO_ETHHDRLENXOUT(1U) 3005 3006 #define S_CPL_TX_TNL_LSO_IPV6OUT 20 3007 #define M_CPL_TX_TNL_LSO_IPV6OUT 0x1 3008 #define V_CPL_TX_TNL_LSO_IPV6OUT(x) ((x) << S_CPL_TX_TNL_LSO_IPV6OUT) 3009 #define G_CPL_TX_TNL_LSO_IPV6OUT(x) \ 3010 (((x) >> S_CPL_TX_TNL_LSO_IPV6OUT) & M_CPL_TX_TNL_LSO_IPV6OUT) 3011 #define F_CPL_TX_TNL_LSO_IPV6OUT V_CPL_TX_TNL_LSO_IPV6OUT(1U) 3012 3013 #define S_CPL_TX_TNL_LSO_ETHHDRLENOUT 16 3014 #define M_CPL_TX_TNL_LSO_ETHHDRLENOUT 0xf 3015 #define V_CPL_TX_TNL_LSO_ETHHDRLENOUT(x) \ 3016 ((x) << S_CPL_TX_TNL_LSO_ETHHDRLENOUT) 3017 #define G_CPL_TX_TNL_LSO_ETHHDRLENOUT(x) \ 3018 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLENOUT) & M_CPL_TX_TNL_LSO_ETHHDRLENOUT) 3019 3020 #define S_CPL_TX_TNL_LSO_IPHDRLENOUT 4 3021 #define M_CPL_TX_TNL_LSO_IPHDRLENOUT 0xfff 3022 #define V_CPL_TX_TNL_LSO_IPHDRLENOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPHDRLENOUT) 3023 #define G_CPL_TX_TNL_LSO_IPHDRLENOUT(x) \ 3024 (((x) >> S_CPL_TX_TNL_LSO_IPHDRLENOUT) & M_CPL_TX_TNL_LSO_IPHDRLENOUT) 3025 3026 #define S_CPL_TX_TNL_LSO_IPHDRCHKOUT 3 3027 #define M_CPL_TX_TNL_LSO_IPHDRCHKOUT 0x1 3028 #define V_CPL_TX_TNL_LSO_IPHDRCHKOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPHDRCHKOUT) 3029 #define G_CPL_TX_TNL_LSO_IPHDRCHKOUT(x) \ 3030 (((x) >> S_CPL_TX_TNL_LSO_IPHDRCHKOUT) & M_CPL_TX_TNL_LSO_IPHDRCHKOUT) 3031 #define F_CPL_TX_TNL_LSO_IPHDRCHKOUT V_CPL_TX_TNL_LSO_IPHDRCHKOUT(1U) 3032 3033 #define S_CPL_TX_TNL_LSO_IPLENSETOUT 2 3034 #define M_CPL_TX_TNL_LSO_IPLENSETOUT 0x1 3035 #define V_CPL_TX_TNL_LSO_IPLENSETOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPLENSETOUT) 3036 #define G_CPL_TX_TNL_LSO_IPLENSETOUT(x) \ 3037 (((x) >> S_CPL_TX_TNL_LSO_IPLENSETOUT) & M_CPL_TX_TNL_LSO_IPLENSETOUT) 3038 #define F_CPL_TX_TNL_LSO_IPLENSETOUT V_CPL_TX_TNL_LSO_IPLENSETOUT(1U) 3039 3040 #define S_CPL_TX_TNL_LSO_IPIDINCOUT 1 3041 #define M_CPL_TX_TNL_LSO_IPIDINCOUT 0x1 3042 #define V_CPL_TX_TNL_LSO_IPIDINCOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPIDINCOUT) 3043 #define G_CPL_TX_TNL_LSO_IPIDINCOUT(x) \ 3044 (((x) >> S_CPL_TX_TNL_LSO_IPIDINCOUT) & M_CPL_TX_TNL_LSO_IPIDINCOUT) 3045 #define F_CPL_TX_TNL_LSO_IPIDINCOUT V_CPL_TX_TNL_LSO_IPIDINCOUT(1U) 3046 3047 #define S_CPL_TX_TNL_LSO_IPIDSPLITOUT 0 3048 #define M_CPL_TX_TNL_LSO_IPIDSPLITOUT 0x1 3049 #define V_CPL_TX_TNL_LSO_IPIDSPLITOUT(x) \ 3050 ((x) << S_CPL_TX_TNL_LSO_IPIDSPLITOUT) 3051 #define G_CPL_TX_TNL_LSO_IPIDSPLITOUT(x) \ 3052 (((x) >> S_CPL_TX_TNL_LSO_IPIDSPLITOUT) & M_CPL_TX_TNL_LSO_IPIDSPLITOUT) 3053 #define F_CPL_TX_TNL_LSO_IPIDSPLITOUT V_CPL_TX_TNL_LSO_IPIDSPLITOUT(1U) 3054 3055 #define S_CPL_TX_TNL_LSO_UDPLENSETOUT 15 3056 #define M_CPL_TX_TNL_LSO_UDPLENSETOUT 0x1 3057 #define V_CPL_TX_TNL_LSO_UDPLENSETOUT(x) \ 3058 ((x) << S_CPL_TX_TNL_LSO_UDPLENSETOUT) 3059 #define G_CPL_TX_TNL_LSO_UDPLENSETOUT(x) \ 3060 (((x) >> S_CPL_TX_TNL_LSO_UDPLENSETOUT) & M_CPL_TX_TNL_LSO_UDPLENSETOUT) 3061 #define F_CPL_TX_TNL_LSO_UDPLENSETOUT V_CPL_TX_TNL_LSO_UDPLENSETOUT(1U) 3062 3063 #define S_CPL_TX_TNL_LSO_UDPCHKCLROUT 14 3064 #define M_CPL_TX_TNL_LSO_UDPCHKCLROUT 0x1 3065 #define V_CPL_TX_TNL_LSO_UDPCHKCLROUT(x) \ 3066 ((x) << S_CPL_TX_TNL_LSO_UDPCHKCLROUT) 3067 #define G_CPL_TX_TNL_LSO_UDPCHKCLROUT(x) \ 3068 (((x) >> S_CPL_TX_TNL_LSO_UDPCHKCLROUT) & M_CPL_TX_TNL_LSO_UDPCHKCLROUT) 3069 #define F_CPL_TX_TNL_LSO_UDPCHKCLROUT V_CPL_TX_TNL_LSO_UDPCHKCLROUT(1U) 3070 3071 #define S_CPL_TX_TNL_LSO_TNLTYPE 12 3072 #define M_CPL_TX_TNL_LSO_TNLTYPE 0x3 3073 #define V_CPL_TX_TNL_LSO_TNLTYPE(x) ((x) << S_CPL_TX_TNL_LSO_TNLTYPE) 3074 #define G_CPL_TX_TNL_LSO_TNLTYPE(x) \ 3075 (((x) >> S_CPL_TX_TNL_LSO_TNLTYPE) & M_CPL_TX_TNL_LSO_TNLTYPE) 3076 3077 #define S_CPL_TX_TNL_LSO_TNLHDRLEN 0 3078 #define M_CPL_TX_TNL_LSO_TNLHDRLEN 0xfff 3079 #define V_CPL_TX_TNL_LSO_TNLHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_TNLHDRLEN) 3080 #define G_CPL_TX_TNL_LSO_TNLHDRLEN(x) \ 3081 (((x) >> S_CPL_TX_TNL_LSO_TNLHDRLEN) & M_CPL_TX_TNL_LSO_TNLHDRLEN) 3082 3083 #define S_CPL_TX_TNL_LSO_FLOW 21 3084 #define M_CPL_TX_TNL_LSO_FLOW 0x1 3085 #define V_CPL_TX_TNL_LSO_FLOW(x) ((x) << S_CPL_TX_TNL_LSO_FLOW) 3086 #define G_CPL_TX_TNL_LSO_FLOW(x) \ 3087 (((x) >> S_CPL_TX_TNL_LSO_FLOW) & M_CPL_TX_TNL_LSO_FLOW) 3088 #define F_CPL_TX_TNL_LSO_FLOW V_CPL_TX_TNL_LSO_FLOW(1U) 3089 3090 #define S_CPL_TX_TNL_LSO_IPV6 20 3091 #define M_CPL_TX_TNL_LSO_IPV6 0x1 3092 #define V_CPL_TX_TNL_LSO_IPV6(x) ((x) << S_CPL_TX_TNL_LSO_IPV6) 3093 #define G_CPL_TX_TNL_LSO_IPV6(x) \ 3094 (((x) >> S_CPL_TX_TNL_LSO_IPV6) & M_CPL_TX_TNL_LSO_IPV6) 3095 #define F_CPL_TX_TNL_LSO_IPV6 V_CPL_TX_TNL_LSO_IPV6(1U) 3096 3097 #define S_CPL_TX_TNL_LSO_ETHHDRLEN 16 3098 #define M_CPL_TX_TNL_LSO_ETHHDRLEN 0xf 3099 #define V_CPL_TX_TNL_LSO_ETHHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_ETHHDRLEN) 3100 #define G_CPL_TX_TNL_LSO_ETHHDRLEN(x) \ 3101 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLEN) & M_CPL_TX_TNL_LSO_ETHHDRLEN) 3102 3103 #define S_CPL_TX_TNL_LSO_IPHDRLEN 4 3104 #define M_CPL_TX_TNL_LSO_IPHDRLEN 0xfff 3105 #define V_CPL_TX_TNL_LSO_IPHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_IPHDRLEN) 3106 #define G_CPL_TX_TNL_LSO_IPHDRLEN(x) \ 3107 (((x) >> S_CPL_TX_TNL_LSO_IPHDRLEN) & M_CPL_TX_TNL_LSO_IPHDRLEN) 3108 3109 #define S_CPL_TX_TNL_LSO_TCPHDRLEN 0 3110 #define M_CPL_TX_TNL_LSO_TCPHDRLEN 0xf 3111 #define V_CPL_TX_TNL_LSO_TCPHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_TCPHDRLEN) 3112 #define G_CPL_TX_TNL_LSO_TCPHDRLEN(x) \ 3113 (((x) >> S_CPL_TX_TNL_LSO_TCPHDRLEN) & M_CPL_TX_TNL_LSO_TCPHDRLEN) 3114 3115 #define S_CPL_TX_TNL_LSO_IPIDSPLIT 15 3116 #define M_CPL_TX_TNL_LSO_IPIDSPLIT 0x1 3117 #define V_CPL_TX_TNL_LSO_IPIDSPLIT(x) ((x) << S_CPL_TX_TNL_LSO_IPIDSPLIT) 3118 #define G_CPL_TX_TNL_LSO_IPIDSPLIT(x) \ 3119 (((x) >> S_CPL_TX_TNL_LSO_IPIDSPLIT) & M_CPL_TX_TNL_LSO_IPIDSPLIT) 3120 #define F_CPL_TX_TNL_LSO_IPIDSPLIT V_CPL_TX_TNL_LSO_IPIDSPLIT(1U) 3121 3122 #define S_CPL_TX_TNL_LSO_ETHHDRLENX 14 3123 #define M_CPL_TX_TNL_LSO_ETHHDRLENX 0x1 3124 #define V_CPL_TX_TNL_LSO_ETHHDRLENX(x) ((x) << S_CPL_TX_TNL_LSO_ETHHDRLENX) 3125 #define G_CPL_TX_TNL_LSO_ETHHDRLENX(x) \ 3126 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLENX) & M_CPL_TX_TNL_LSO_ETHHDRLENX) 3127 #define F_CPL_TX_TNL_LSO_ETHHDRLENX V_CPL_TX_TNL_LSO_ETHHDRLENX(1U) 3128 3129 #define S_CPL_TX_TNL_LSO_MSS 0 3130 #define M_CPL_TX_TNL_LSO_MSS 0x3fff 3131 #define V_CPL_TX_TNL_LSO_MSS(x) ((x) << S_CPL_TX_TNL_LSO_MSS) 3132 #define G_CPL_TX_TNL_LSO_MSS(x) \ 3133 (((x) >> S_CPL_TX_TNL_LSO_MSS) & M_CPL_TX_TNL_LSO_MSS) 3134 3135 #define S_CPL_TX_TNL_LSO_ETHLENOFFSET 28 3136 #define M_CPL_TX_TNL_LSO_ETHLENOFFSET 0xf 3137 #define V_CPL_TX_TNL_LSO_ETHLENOFFSET(x) \ 3138 ((x) << S_CPL_TX_TNL_LSO_ETHLENOFFSET) 3139 #define G_CPL_TX_TNL_LSO_ETHLENOFFSET(x) \ 3140 (((x) >> S_CPL_TX_TNL_LSO_ETHLENOFFSET) & M_CPL_TX_TNL_LSO_ETHLENOFFSET) 3141 3142 #define S_CPL_TX_TNL_LSO_SIZE 0 3143 #define M_CPL_TX_TNL_LSO_SIZE 0xfffffff 3144 #define V_CPL_TX_TNL_LSO_SIZE(x) ((x) << S_CPL_TX_TNL_LSO_SIZE) 3145 #define G_CPL_TX_TNL_LSO_SIZE(x) \ 3146 (((x) >> S_CPL_TX_TNL_LSO_SIZE) & M_CPL_TX_TNL_LSO_SIZE) 3147 3148 struct cpl_rx_mps_pkt { 3149 __be32 op_to_r1_hi; 3150 __be32 r1_lo_length; 3151 }; 3152 3153 #define S_CPL_RX_MPS_PKT_OP 24 3154 #define M_CPL_RX_MPS_PKT_OP 0xff 3155 #define V_CPL_RX_MPS_PKT_OP(x) ((x) << S_CPL_RX_MPS_PKT_OP) 3156 #define G_CPL_RX_MPS_PKT_OP(x) \ 3157 (((x) >> S_CPL_RX_MPS_PKT_OP) & M_CPL_RX_MPS_PKT_OP) 3158 3159 #define S_CPL_RX_MPS_PKT_TYPE 20 3160 #define M_CPL_RX_MPS_PKT_TYPE 0xf 3161 #define V_CPL_RX_MPS_PKT_TYPE(x) ((x) << S_CPL_RX_MPS_PKT_TYPE) 3162 #define G_CPL_RX_MPS_PKT_TYPE(x) \ 3163 (((x) >> S_CPL_RX_MPS_PKT_TYPE) & M_CPL_RX_MPS_PKT_TYPE) 3164 3165 /* 3166 * Values for CPL_RX_MPS_PKT_TYPE, a bit-wise orthogonal field. 3167 */ 3168 #define X_CPL_RX_MPS_PKT_TYPE_PAUSE (1 << 0) 3169 #define X_CPL_RX_MPS_PKT_TYPE_PPP (1 << 1) 3170 #define X_CPL_RX_MPS_PKT_TYPE_QFC (1 << 2) 3171 #define X_CPL_RX_MPS_PKT_TYPE_PTP (1 << 3) 3172 3173 struct cpl_tx_tls_sfo { 3174 __be32 op_to_seg_len; 3175 __be32 pld_len; 3176 __be32 type_protover; 3177 __be32 r1_lo; 3178 __be32 seqno_numivs; 3179 __be32 ivgen_hdrlen; 3180 __be64 scmd1; 3181 }; 3182 3183 /* cpl_tx_tls_sfo macros */ 3184 #define S_CPL_TX_TLS_SFO_OPCODE 24 3185 #define M_CPL_TX_TLS_SFO_OPCODE 0xff 3186 #define V_CPL_TX_TLS_SFO_OPCODE(x) ((x) << S_CPL_TX_TLS_SFO_OPCODE) 3187 #define G_CPL_TX_TLS_SFO_OPCODE(x) \ 3188 (((x) >> S_CPL_TX_TLS_SFO_OPCODE) & M_CPL_TX_TLS_SFO_OPCODE) 3189 3190 #define S_CPL_TX_TLS_SFO_DATA_TYPE 20 3191 #define M_CPL_TX_TLS_SFO_DATA_TYPE 0xf 3192 #define V_CPL_TX_TLS_SFO_DATA_TYPE(x) ((x) << S_CPL_TX_TLS_SFO_DATA_TYPE) 3193 #define G_CPL_TX_TLS_SFO_DATA_TYPE(x) \ 3194 (((x) >> S_CPL_TX_TLS_SFO_DATA_TYPE) & M_CPL_TX_TLS_SFO_DATA_TYPE) 3195 3196 #define S_CPL_TX_TLS_SFO_CPL_LEN 16 3197 #define M_CPL_TX_TLS_SFO_CPL_LEN 0xf 3198 #define V_CPL_TX_TLS_SFO_CPL_LEN(x) ((x) << S_CPL_TX_TLS_SFO_CPL_LEN) 3199 #define G_CPL_TX_TLS_SFO_CPL_LEN(x) \ 3200 (((x) >> S_CPL_TX_TLS_SFO_CPL_LEN) & M_CPL_TX_TLS_SFO_CPL_LEN) 3201 3202 #define S_CPL_TX_TLS_SFO_SEG_LEN 0 3203 #define M_CPL_TX_TLS_SFO_SEG_LEN 0xffff 3204 #define V_CPL_TX_TLS_SFO_SEG_LEN(x) ((x) << S_CPL_TX_TLS_SFO_SEG_LEN) 3205 #define G_CPL_TX_TLS_SFO_SEG_LEN(x) \ 3206 (((x) >> S_CPL_TX_TLS_SFO_SEG_LEN) & M_CPL_TX_TLS_SFO_SEG_LEN) 3207 3208 #define S_CPL_TX_TLS_SFO_TYPE 24 3209 #define M_CPL_TX_TLS_SFO_TYPE 0xff 3210 #define V_CPL_TX_TLS_SFO_TYPE(x) ((x) << S_CPL_TX_TLS_SFO_TYPE) 3211 #define G_CPL_TX_TLS_SFO_TYPE(x) \ 3212 (((x) >> S_CPL_TX_TLS_SFO_TYPE) & M_CPL_TX_TLS_SFO_TYPE) 3213 3214 #define S_CPL_TX_TLS_SFO_PROTOVER 8 3215 #define M_CPL_TX_TLS_SFO_PROTOVER 0xffff 3216 #define V_CPL_TX_TLS_SFO_PROTOVER(x) ((x) << S_CPL_TX_TLS_SFO_PROTOVER) 3217 #define G_CPL_TX_TLS_SFO_PROTOVER(x) \ 3218 (((x) >> S_CPL_TX_TLS_SFO_PROTOVER) & M_CPL_TX_TLS_SFO_PROTOVER) 3219 3220 struct cpl_tls_data { 3221 RSS_HDR 3222 union opcode_tid ot; 3223 __be32 length_pkd; 3224 __be32 seq; 3225 __be32 r1; 3226 }; 3227 3228 #define S_CPL_TLS_DATA_OPCODE 24 3229 #define M_CPL_TLS_DATA_OPCODE 0xff 3230 #define V_CPL_TLS_DATA_OPCODE(x) ((x) << S_CPL_TLS_DATA_OPCODE) 3231 #define G_CPL_TLS_DATA_OPCODE(x) \ 3232 (((x) >> S_CPL_TLS_DATA_OPCODE) & M_CPL_TLS_DATA_OPCODE) 3233 3234 #define S_CPL_TLS_DATA_TID 0 3235 #define M_CPL_TLS_DATA_TID 0xffffff 3236 #define V_CPL_TLS_DATA_TID(x) ((x) << S_CPL_TLS_DATA_TID) 3237 #define G_CPL_TLS_DATA_TID(x) \ 3238 (((x) >> S_CPL_TLS_DATA_TID) & M_CPL_TLS_DATA_TID) 3239 3240 #define S_CPL_TLS_DATA_LENGTH 0 3241 #define M_CPL_TLS_DATA_LENGTH 0xffff 3242 #define V_CPL_TLS_DATA_LENGTH(x) ((x) << S_CPL_TLS_DATA_LENGTH) 3243 #define G_CPL_TLS_DATA_LENGTH(x) \ 3244 (((x) >> S_CPL_TLS_DATA_LENGTH) & M_CPL_TLS_DATA_LENGTH) 3245 3246 struct cpl_rx_tls_cmp { 3247 RSS_HDR 3248 union opcode_tid ot; 3249 __be32 pdulength_length; 3250 __be32 seq; 3251 __be32 ddp_report; 3252 __be32 r; 3253 __be32 ddp_valid; 3254 }; 3255 3256 #define S_CPL_RX_TLS_CMP_OPCODE 24 3257 #define M_CPL_RX_TLS_CMP_OPCODE 0xff 3258 #define V_CPL_RX_TLS_CMP_OPCODE(x) ((x) << S_CPL_RX_TLS_CMP_OPCODE) 3259 #define G_CPL_RX_TLS_CMP_OPCODE(x) \ 3260 (((x) >> S_CPL_RX_TLS_CMP_OPCODE) & M_CPL_RX_TLS_CMP_OPCODE) 3261 3262 #define S_CPL_RX_TLS_CMP_TID 0 3263 #define M_CPL_RX_TLS_CMP_TID 0xffffff 3264 #define V_CPL_RX_TLS_CMP_TID(x) ((x) << S_CPL_RX_TLS_CMP_TID) 3265 #define G_CPL_RX_TLS_CMP_TID(x) \ 3266 (((x) >> S_CPL_RX_TLS_CMP_TID) & M_CPL_RX_TLS_CMP_TID) 3267 3268 #define S_CPL_RX_TLS_CMP_PDULENGTH 16 3269 #define M_CPL_RX_TLS_CMP_PDULENGTH 0xffff 3270 #define V_CPL_RX_TLS_CMP_PDULENGTH(x) ((x) << S_CPL_RX_TLS_CMP_PDULENGTH) 3271 #define G_CPL_RX_TLS_CMP_PDULENGTH(x) \ 3272 (((x) >> S_CPL_RX_TLS_CMP_PDULENGTH) & M_CPL_RX_TLS_CMP_PDULENGTH) 3273 3274 #define S_CPL_RX_TLS_CMP_LENGTH 0 3275 #define M_CPL_RX_TLS_CMP_LENGTH 0xffff 3276 #define V_CPL_RX_TLS_CMP_LENGTH(x) ((x) << S_CPL_RX_TLS_CMP_LENGTH) 3277 #define G_CPL_RX_TLS_CMP_LENGTH(x) \ 3278 (((x) >> S_CPL_RX_TLS_CMP_LENGTH) & M_CPL_RX_TLS_CMP_LENGTH) 3279 3280 #define S_SCMD_SEQ_NO_CTRL 29 3281 #define M_SCMD_SEQ_NO_CTRL 0x3 3282 #define V_SCMD_SEQ_NO_CTRL(x) ((x) << S_SCMD_SEQ_NO_CTRL) 3283 #define G_SCMD_SEQ_NO_CTRL(x) \ 3284 (((x) >> S_SCMD_SEQ_NO_CTRL) & M_SCMD_SEQ_NO_CTRL) 3285 3286 /* StsFieldPrsnt- Status field at the end of the TLS PDU */ 3287 #define S_SCMD_STATUS_PRESENT 28 3288 #define M_SCMD_STATUS_PRESENT 0x1 3289 #define V_SCMD_STATUS_PRESENT(x) ((x) << S_SCMD_STATUS_PRESENT) 3290 #define G_SCMD_STATUS_PRESENT(x) \ 3291 (((x) >> S_SCMD_STATUS_PRESENT) & M_SCMD_STATUS_PRESENT) 3292 #define F_SCMD_STATUS_PRESENT V_SCMD_STATUS_PRESENT(1U) 3293 3294 /* ProtoVersion - Protocol Version 0: 1.2, 1:1.1, 2:DTLS, 3:Generic, 3295 * 3-15: Reserved. */ 3296 #define S_SCMD_PROTO_VERSION 24 3297 #define M_SCMD_PROTO_VERSION 0xf 3298 #define V_SCMD_PROTO_VERSION(x) ((x) << S_SCMD_PROTO_VERSION) 3299 #define G_SCMD_PROTO_VERSION(x) \ 3300 (((x) >> S_SCMD_PROTO_VERSION) & M_SCMD_PROTO_VERSION) 3301 3302 /* EncDecCtrl - Encryption/Decryption Control. 0: Encrypt, 1: Decrypt */ 3303 #define S_SCMD_ENC_DEC_CTRL 23 3304 #define M_SCMD_ENC_DEC_CTRL 0x1 3305 #define V_SCMD_ENC_DEC_CTRL(x) ((x) << S_SCMD_ENC_DEC_CTRL) 3306 #define G_SCMD_ENC_DEC_CTRL(x) \ 3307 (((x) >> S_SCMD_ENC_DEC_CTRL) & M_SCMD_ENC_DEC_CTRL) 3308 #define F_SCMD_ENC_DEC_CTRL V_SCMD_ENC_DEC_CTRL(1U) 3309 3310 /* CipherAuthSeqCtrl - Cipher Authentication Sequence Control. */ 3311 #define S_SCMD_CIPH_AUTH_SEQ_CTRL 22 3312 #define M_SCMD_CIPH_AUTH_SEQ_CTRL 0x1 3313 #define V_SCMD_CIPH_AUTH_SEQ_CTRL(x) \ 3314 ((x) << S_SCMD_CIPH_AUTH_SEQ_CTRL) 3315 #define G_SCMD_CIPH_AUTH_SEQ_CTRL(x) \ 3316 (((x) >> S_SCMD_CIPH_AUTH_SEQ_CTRL) & M_SCMD_CIPH_AUTH_SEQ_CTRL) 3317 #define F_SCMD_CIPH_AUTH_SEQ_CTRL V_SCMD_CIPH_AUTH_SEQ_CTRL(1U) 3318 3319 /* CiphMode - Cipher Mode. 0: NOP, 1:AES-CBC, 2:AES-GCM, 3:AES-CTR, 3320 * 4:Generic-AES, 5-15: Reserved. */ 3321 #define S_SCMD_CIPH_MODE 18 3322 #define M_SCMD_CIPH_MODE 0xf 3323 #define V_SCMD_CIPH_MODE(x) ((x) << S_SCMD_CIPH_MODE) 3324 #define G_SCMD_CIPH_MODE(x) \ 3325 (((x) >> S_SCMD_CIPH_MODE) & M_SCMD_CIPH_MODE) 3326 3327 /* AuthMode - Auth Mode. 0: NOP, 1:SHA1, 2:SHA2-224, 3:SHA2-256 3328 * 4-15: Reserved */ 3329 #define S_SCMD_AUTH_MODE 14 3330 #define M_SCMD_AUTH_MODE 0xf 3331 #define V_SCMD_AUTH_MODE(x) ((x) << S_SCMD_AUTH_MODE) 3332 #define G_SCMD_AUTH_MODE(x) \ 3333 (((x) >> S_SCMD_AUTH_MODE) & M_SCMD_AUTH_MODE) 3334 3335 /* HmacCtrl - HMAC Control. 0:NOP, 1:No truncation, 2:Support HMAC Truncation 3336 * per RFC 4366, 3:IPSec 96 bits, 4-7:Reserved 3337 */ 3338 #define S_SCMD_HMAC_CTRL 11 3339 #define M_SCMD_HMAC_CTRL 0x7 3340 #define V_SCMD_HMAC_CTRL(x) ((x) << S_SCMD_HMAC_CTRL) 3341 #define G_SCMD_HMAC_CTRL(x) \ 3342 (((x) >> S_SCMD_HMAC_CTRL) & M_SCMD_HMAC_CTRL) 3343 3344 /* IvSize - IV size in units of 2 bytes */ 3345 #define S_SCMD_IV_SIZE 7 3346 #define M_SCMD_IV_SIZE 0xf 3347 #define V_SCMD_IV_SIZE(x) ((x) << S_SCMD_IV_SIZE) 3348 #define G_SCMD_IV_SIZE(x) \ 3349 (((x) >> S_SCMD_IV_SIZE) & M_SCMD_IV_SIZE) 3350 3351 /* NumIVs - Number of IVs */ 3352 #define S_SCMD_NUM_IVS 0 3353 #define M_SCMD_NUM_IVS 0x7f 3354 #define V_SCMD_NUM_IVS(x) ((x) << S_SCMD_NUM_IVS) 3355 #define G_SCMD_NUM_IVS(x) \ 3356 (((x) >> S_SCMD_NUM_IVS) & M_SCMD_NUM_IVS) 3357 3358 /* EnbDbgId - If this is enabled upper 20 (63:44) bits if SeqNumber 3359 * (below) are used as Cid (connection id for debug status), these 3360 * bits are padded to zero for forming the 64 bit 3361 * sequence number for TLS 3362 */ 3363 #define S_SCMD_ENB_DBGID 31 3364 #define M_SCMD_ENB_DBGID 0x1 3365 #define V_SCMD_ENB_DBGID(x) ((x) << S_SCMD_ENB_DBGID) 3366 #define G_SCMD_ENB_DBGID(x) \ 3367 (((x) >> S_SCMD_ENB_DBGID) & M_SCMD_ENB_DBGID) 3368 3369 /* IV generation in SW. */ 3370 #define S_SCMD_IV_GEN_CTRL 30 3371 #define M_SCMD_IV_GEN_CTRL 0x1 3372 #define V_SCMD_IV_GEN_CTRL(x) ((x) << S_SCMD_IV_GEN_CTRL) 3373 #define G_SCMD_IV_GEN_CTRL(x) \ 3374 (((x) >> S_SCMD_IV_GEN_CTRL) & M_SCMD_IV_GEN_CTRL) 3375 #define F_SCMD_IV_GEN_CTRL V_SCMD_IV_GEN_CTRL(1U) 3376 3377 /* More frags */ 3378 #define S_SCMD_MORE_FRAGS 20 3379 #define M_SCMD_MORE_FRAGS 0x1 3380 #define V_SCMD_MORE_FRAGS(x) ((x) << S_SCMD_MORE_FRAGS) 3381 #define G_SCMD_MORE_FRAGS(x) (((x) >> S_SCMD_MORE_FRAGS) & M_SCMD_MORE_FRAGS) 3382 3383 /*last frag */ 3384 #define S_SCMD_LAST_FRAG 19 3385 #define M_SCMD_LAST_FRAG 0x1 3386 #define V_SCMD_LAST_FRAG(x) ((x) << S_SCMD_LAST_FRAG) 3387 #define G_SCMD_LAST_FRAG(x) (((x) >> S_SCMD_LAST_FRAG) & M_SCMD_LAST_FRAG) 3388 3389 /* TlsCompPdu */ 3390 #define S_SCMD_TLS_COMPPDU 18 3391 #define M_SCMD_TLS_COMPPDU 0x1 3392 #define V_SCMD_TLS_COMPPDU(x) ((x) << S_SCMD_TLS_COMPPDU) 3393 #define G_SCMD_TLS_COMPPDU(x) (((x) >> S_SCMD_TLS_COMPPDU) & M_SCMD_TLS_COMPPDU) 3394 3395 /* KeyCntxtInline - Key context inline after the scmd OR PayloadOnly*/ 3396 #define S_SCMD_KEY_CTX_INLINE 17 3397 #define M_SCMD_KEY_CTX_INLINE 0x1 3398 #define V_SCMD_KEY_CTX_INLINE(x) ((x) << S_SCMD_KEY_CTX_INLINE) 3399 #define G_SCMD_KEY_CTX_INLINE(x) \ 3400 (((x) >> S_SCMD_KEY_CTX_INLINE) & M_SCMD_KEY_CTX_INLINE) 3401 #define F_SCMD_KEY_CTX_INLINE V_SCMD_KEY_CTX_INLINE(1U) 3402 3403 /* TLSFragEnable - 0: Host created TLS PDUs, 1: TLS Framgmentation in ASIC */ 3404 #define S_SCMD_TLS_FRAG_ENABLE 16 3405 #define M_SCMD_TLS_FRAG_ENABLE 0x1 3406 #define V_SCMD_TLS_FRAG_ENABLE(x) ((x) << S_SCMD_TLS_FRAG_ENABLE) 3407 #define G_SCMD_TLS_FRAG_ENABLE(x) \ 3408 (((x) >> S_SCMD_TLS_FRAG_ENABLE) & M_SCMD_TLS_FRAG_ENABLE) 3409 #define F_SCMD_TLS_FRAG_ENABLE V_SCMD_TLS_FRAG_ENABLE(1U) 3410 3411 /* MacOnly - Only send the MAC and discard PDU. This is valid for hash only 3412 * modes, in this case TLS_TX will drop the PDU and only 3413 * send back the MAC bytes. */ 3414 #define S_SCMD_MAC_ONLY 15 3415 #define M_SCMD_MAC_ONLY 0x1 3416 #define V_SCMD_MAC_ONLY(x) ((x) << S_SCMD_MAC_ONLY) 3417 #define G_SCMD_MAC_ONLY(x) \ 3418 (((x) >> S_SCMD_MAC_ONLY) & M_SCMD_MAC_ONLY) 3419 #define F_SCMD_MAC_ONLY V_SCMD_MAC_ONLY(1U) 3420 3421 /* AadIVDrop - Drop the AAD and IV fields. Useful in protocols 3422 * which have complex AAD and IV formations Eg:AES-CCM 3423 */ 3424 #define S_SCMD_AADIVDROP 14 3425 #define M_SCMD_AADIVDROP 0x1 3426 #define V_SCMD_AADIVDROP(x) ((x) << S_SCMD_AADIVDROP) 3427 #define G_SCMD_AADIVDROP(x) \ 3428 (((x) >> S_SCMD_AADIVDROP) & M_SCMD_AADIVDROP) 3429 #define F_SCMD_AADIVDROP V_SCMD_AADIVDROP(1U) 3430 3431 /* HdrLength - Length of all headers excluding TLS header 3432 * present before start of crypto PDU/payload. */ 3433 #define S_SCMD_HDR_LEN 0 3434 #define M_SCMD_HDR_LEN 0x3fff 3435 #define V_SCMD_HDR_LEN(x) ((x) << S_SCMD_HDR_LEN) 3436 #define G_SCMD_HDR_LEN(x) \ 3437 (((x) >> S_SCMD_HDR_LEN) & M_SCMD_HDR_LEN) 3438 3439 struct cpl_tx_sec_pdu { 3440 __be32 op_ivinsrtofst; 3441 __be32 pldlen; 3442 __be32 aadstart_cipherstop_hi; 3443 __be32 cipherstop_lo_authinsert; 3444 __be32 seqno_numivs; 3445 __be32 ivgen_hdrlen; 3446 __be64 scmd1; 3447 }; 3448 3449 #define S_CPL_TX_SEC_PDU_OPCODE 24 3450 #define M_CPL_TX_SEC_PDU_OPCODE 0xff 3451 #define V_CPL_TX_SEC_PDU_OPCODE(x) ((x) << S_CPL_TX_SEC_PDU_OPCODE) 3452 #define G_CPL_TX_SEC_PDU_OPCODE(x) \ 3453 (((x) >> S_CPL_TX_SEC_PDU_OPCODE) & M_CPL_TX_SEC_PDU_OPCODE) 3454 3455 /* RX Channel Id */ 3456 #define S_CPL_TX_SEC_PDU_RXCHID 22 3457 #define M_CPL_TX_SEC_PDU_RXCHID 0x1 3458 #define V_CPL_TX_SEC_PDU_RXCHID(x) ((x) << S_CPL_TX_SEC_PDU_RXCHID) 3459 #define G_CPL_TX_SEC_PDU_RXCHID(x) \ 3460 (((x) >> S_CPL_TX_SEC_PDU_RXCHID) & M_CPL_TX_SEC_PDU_RXCHID) 3461 #define F_CPL_TX_SEC_PDU_RXCHID V_CPL_TX_SEC_PDU_RXCHID(1U) 3462 3463 /* Ack Follows */ 3464 #define S_CPL_TX_SEC_PDU_ACKFOLLOWS 21 3465 #define M_CPL_TX_SEC_PDU_ACKFOLLOWS 0x1 3466 #define V_CPL_TX_SEC_PDU_ACKFOLLOWS(x) ((x) << S_CPL_TX_SEC_PDU_ACKFOLLOWS) 3467 #define G_CPL_TX_SEC_PDU_ACKFOLLOWS(x) \ 3468 (((x) >> S_CPL_TX_SEC_PDU_ACKFOLLOWS) & M_CPL_TX_SEC_PDU_ACKFOLLOWS) 3469 #define F_CPL_TX_SEC_PDU_ACKFOLLOWS V_CPL_TX_SEC_PDU_ACKFOLLOWS(1U) 3470 3471 /* Loopback bit in cpl_tx_sec_pdu */ 3472 #define S_CPL_TX_SEC_PDU_ULPTXLPBK 20 3473 #define M_CPL_TX_SEC_PDU_ULPTXLPBK 0x1 3474 #define V_CPL_TX_SEC_PDU_ULPTXLPBK(x) ((x) << S_CPL_TX_SEC_PDU_ULPTXLPBK) 3475 #define G_CPL_TX_SEC_PDU_ULPTXLPBK(x) \ 3476 (((x) >> S_CPL_TX_SEC_PDU_ULPTXLPBK) & M_CPL_TX_SEC_PDU_ULPTXLPBK) 3477 #define F_CPL_TX_SEC_PDU_ULPTXLPBK V_CPL_TX_SEC_PDU_ULPTXLPBK(1U) 3478 3479 /* Length of cpl header encapsulated */ 3480 #define S_CPL_TX_SEC_PDU_CPLLEN 16 3481 #define M_CPL_TX_SEC_PDU_CPLLEN 0xf 3482 #define V_CPL_TX_SEC_PDU_CPLLEN(x) ((x) << S_CPL_TX_SEC_PDU_CPLLEN) 3483 #define G_CPL_TX_SEC_PDU_CPLLEN(x) \ 3484 (((x) >> S_CPL_TX_SEC_PDU_CPLLEN) & M_CPL_TX_SEC_PDU_CPLLEN) 3485 3486 /* PlaceHolder */ 3487 #define S_CPL_TX_SEC_PDU_PLACEHOLDER 10 3488 #define M_CPL_TX_SEC_PDU_PLACEHOLDER 0x1 3489 #define V_CPL_TX_SEC_PDU_PLACEHOLDER(x) ((x) << S_CPL_TX_SEC_PDU_PLACEHOLDER) 3490 #define G_CPL_TX_SEC_PDU_PLACEHOLDER(x) \ 3491 (((x) >> S_CPL_TX_SEC_PDU_PLACEHOLDER) & \ 3492 M_CPL_TX_SEC_PDU_PLACEHOLDER) 3493 3494 /* IvInsrtOffset: Insertion location for IV */ 3495 #define S_CPL_TX_SEC_PDU_IVINSRTOFST 0 3496 #define M_CPL_TX_SEC_PDU_IVINSRTOFST 0x3ff 3497 #define V_CPL_TX_SEC_PDU_IVINSRTOFST(x) ((x) << S_CPL_TX_SEC_PDU_IVINSRTOFST) 3498 #define G_CPL_TX_SEC_PDU_IVINSRTOFST(x) \ 3499 (((x) >> S_CPL_TX_SEC_PDU_IVINSRTOFST) & \ 3500 M_CPL_TX_SEC_PDU_IVINSRTOFST) 3501 3502 /* AadStartOffset: Offset in bytes for AAD start from 3503 * the first byte following 3504 * the pkt headers (0-255 3505 * bytes) */ 3506 #define S_CPL_TX_SEC_PDU_AADSTART 24 3507 #define M_CPL_TX_SEC_PDU_AADSTART 0xff 3508 #define V_CPL_TX_SEC_PDU_AADSTART(x) ((x) << S_CPL_TX_SEC_PDU_AADSTART) 3509 #define G_CPL_TX_SEC_PDU_AADSTART(x) \ 3510 (((x) >> S_CPL_TX_SEC_PDU_AADSTART) & \ 3511 M_CPL_TX_SEC_PDU_AADSTART) 3512 3513 /* AadStopOffset: offset in bytes for AAD stop/end from the first byte following 3514 * the pkt headers (0-511 bytes) */ 3515 #define S_CPL_TX_SEC_PDU_AADSTOP 15 3516 #define M_CPL_TX_SEC_PDU_AADSTOP 0x1ff 3517 #define V_CPL_TX_SEC_PDU_AADSTOP(x) ((x) << S_CPL_TX_SEC_PDU_AADSTOP) 3518 #define G_CPL_TX_SEC_PDU_AADSTOP(x) \ 3519 (((x) >> S_CPL_TX_SEC_PDU_AADSTOP) & M_CPL_TX_SEC_PDU_AADSTOP) 3520 3521 /* CipherStartOffset: offset in bytes for encryption/decryption start from the 3522 * first byte following the pkt headers (0-1023 3523 * bytes) */ 3524 #define S_CPL_TX_SEC_PDU_CIPHERSTART 5 3525 #define M_CPL_TX_SEC_PDU_CIPHERSTART 0x3ff 3526 #define V_CPL_TX_SEC_PDU_CIPHERSTART(x) ((x) << S_CPL_TX_SEC_PDU_CIPHERSTART) 3527 #define G_CPL_TX_SEC_PDU_CIPHERSTART(x) \ 3528 (((x) >> S_CPL_TX_SEC_PDU_CIPHERSTART) & \ 3529 M_CPL_TX_SEC_PDU_CIPHERSTART) 3530 3531 /* CipherStopOffset: offset in bytes for encryption/decryption end 3532 * from end of the payload of this command (0-511 bytes) */ 3533 #define S_CPL_TX_SEC_PDU_CIPHERSTOP_HI 0 3534 #define M_CPL_TX_SEC_PDU_CIPHERSTOP_HI 0x1f 3535 #define V_CPL_TX_SEC_PDU_CIPHERSTOP_HI(x) \ 3536 ((x) << S_CPL_TX_SEC_PDU_CIPHERSTOP_HI) 3537 #define G_CPL_TX_SEC_PDU_CIPHERSTOP_HI(x) \ 3538 (((x) >> S_CPL_TX_SEC_PDU_CIPHERSTOP_HI) & \ 3539 M_CPL_TX_SEC_PDU_CIPHERSTOP_HI) 3540 3541 #define S_CPL_TX_SEC_PDU_CIPHERSTOP_LO 28 3542 #define M_CPL_TX_SEC_PDU_CIPHERSTOP_LO 0xf 3543 #define V_CPL_TX_SEC_PDU_CIPHERSTOP_LO(x) \ 3544 ((x) << S_CPL_TX_SEC_PDU_CIPHERSTOP_LO) 3545 #define G_CPL_TX_SEC_PDU_CIPHERSTOP_LO(x) \ 3546 (((x) >> S_CPL_TX_SEC_PDU_CIPHERSTOP_LO) & \ 3547 M_CPL_TX_SEC_PDU_CIPHERSTOP_LO) 3548 3549 /* AuthStartOffset: offset in bytes for authentication start from 3550 * the first byte following the pkt headers (0-1023) 3551 * */ 3552 #define S_CPL_TX_SEC_PDU_AUTHSTART 18 3553 #define M_CPL_TX_SEC_PDU_AUTHSTART 0x3ff 3554 #define V_CPL_TX_SEC_PDU_AUTHSTART(x) ((x) << S_CPL_TX_SEC_PDU_AUTHSTART) 3555 #define G_CPL_TX_SEC_PDU_AUTHSTART(x) \ 3556 (((x) >> S_CPL_TX_SEC_PDU_AUTHSTART) & \ 3557 M_CPL_TX_SEC_PDU_AUTHSTART) 3558 3559 /* AuthStopOffset: offset in bytes for authentication 3560 * end from end of the payload of this command (0-511 Bytes) */ 3561 #define S_CPL_TX_SEC_PDU_AUTHSTOP 9 3562 #define M_CPL_TX_SEC_PDU_AUTHSTOP 0x1ff 3563 #define V_CPL_TX_SEC_PDU_AUTHSTOP(x) ((x) << S_CPL_TX_SEC_PDU_AUTHSTOP) 3564 #define G_CPL_TX_SEC_PDU_AUTHSTOP(x) \ 3565 (((x) >> S_CPL_TX_SEC_PDU_AUTHSTOP) & \ 3566 M_CPL_TX_SEC_PDU_AUTHSTOP) 3567 3568 /* AuthInsrtOffset: offset in bytes for authentication insertion 3569 * from end of the payload of this command (0-511 bytes) */ 3570 #define S_CPL_TX_SEC_PDU_AUTHINSERT 0 3571 #define M_CPL_TX_SEC_PDU_AUTHINSERT 0x1ff 3572 #define V_CPL_TX_SEC_PDU_AUTHINSERT(x) ((x) << S_CPL_TX_SEC_PDU_AUTHINSERT) 3573 #define G_CPL_TX_SEC_PDU_AUTHINSERT(x) \ 3574 (((x) >> S_CPL_TX_SEC_PDU_AUTHINSERT) & \ 3575 M_CPL_TX_SEC_PDU_AUTHINSERT) 3576 3577 struct cpl_rx_phys_dsgl { 3578 __be32 op_to_tid; 3579 __be32 pcirlxorder_to_noofsgentr; 3580 struct rss_header rss_hdr_int; 3581 }; 3582 3583 #define S_CPL_RX_PHYS_DSGL_OPCODE 24 3584 #define M_CPL_RX_PHYS_DSGL_OPCODE 0xff 3585 #define V_CPL_RX_PHYS_DSGL_OPCODE(x) ((x) << S_CPL_RX_PHYS_DSGL_OPCODE) 3586 #define G_CPL_RX_PHYS_DSGL_OPCODE(x) \ 3587 (((x) >> S_CPL_RX_PHYS_DSGL_OPCODE) & M_CPL_RX_PHYS_DSGL_OPCODE) 3588 3589 #define S_CPL_RX_PHYS_DSGL_ISRDMA 23 3590 #define M_CPL_RX_PHYS_DSGL_ISRDMA 0x1 3591 #define V_CPL_RX_PHYS_DSGL_ISRDMA(x) ((x) << S_CPL_RX_PHYS_DSGL_ISRDMA) 3592 #define G_CPL_RX_PHYS_DSGL_ISRDMA(x) \ 3593 (((x) >> S_CPL_RX_PHYS_DSGL_ISRDMA) & M_CPL_RX_PHYS_DSGL_ISRDMA) 3594 #define F_CPL_RX_PHYS_DSGL_ISRDMA V_CPL_RX_PHYS_DSGL_ISRDMA(1U) 3595 3596 #define S_CPL_RX_PHYS_DSGL_RSVD1 20 3597 #define M_CPL_RX_PHYS_DSGL_RSVD1 0x7 3598 #define V_CPL_RX_PHYS_DSGL_RSVD1(x) ((x) << S_CPL_RX_PHYS_DSGL_RSVD1) 3599 #define G_CPL_RX_PHYS_DSGL_RSVD1(x) \ 3600 (((x) >> S_CPL_RX_PHYS_DSGL_RSVD1) & M_CPL_RX_PHYS_DSGL_RSVD1) 3601 3602 #define S_CPL_RX_PHYS_DSGL_PCIRLXORDER 31 3603 #define M_CPL_RX_PHYS_DSGL_PCIRLXORDER 0x1 3604 #define V_CPL_RX_PHYS_DSGL_PCIRLXORDER(x) \ 3605 ((x) << S_CPL_RX_PHYS_DSGL_PCIRLXORDER) 3606 #define G_CPL_RX_PHYS_DSGL_PCIRLXORDER(x) \ 3607 (((x) >> S_CPL_RX_PHYS_DSGL_PCIRLXORDER) & \ 3608 M_CPL_RX_PHYS_DSGL_PCIRLXORDER) 3609 #define F_CPL_RX_PHYS_DSGL_PCIRLXORDER V_CPL_RX_PHYS_DSGL_PCIRLXORDER(1U) 3610 3611 #define S_CPL_RX_PHYS_DSGL_PCINOSNOOP 30 3612 #define M_CPL_RX_PHYS_DSGL_PCINOSNOOP 0x1 3613 #define V_CPL_RX_PHYS_DSGL_PCINOSNOOP(x) \ 3614 ((x) << S_CPL_RX_PHYS_DSGL_PCINOSNOOP) 3615 #define G_CPL_RX_PHYS_DSGL_PCINOSNOOP(x) \ 3616 (((x) >> S_CPL_RX_PHYS_DSGL_PCINOSNOOP) & \ 3617 M_CPL_RX_PHYS_DSGL_PCINOSNOOP) 3618 #define F_CPL_RX_PHYS_DSGL_PCINOSNOOP V_CPL_RX_PHYS_DSGL_PCINOSNOOP(1U) 3619 3620 #define S_CPL_RX_PHYS_DSGL_PCITPHNTENB 29 3621 #define M_CPL_RX_PHYS_DSGL_PCITPHNTENB 0x1 3622 #define V_CPL_RX_PHYS_DSGL_PCITPHNTENB(x) \ 3623 ((x) << S_CPL_RX_PHYS_DSGL_PCITPHNTENB) 3624 #define G_CPL_RX_PHYS_DSGL_PCITPHNTENB(x) \ 3625 (((x) >> S_CPL_RX_PHYS_DSGL_PCITPHNTENB) & \ 3626 M_CPL_RX_PHYS_DSGL_PCITPHNTENB) 3627 #define F_CPL_RX_PHYS_DSGL_PCITPHNTENB V_CPL_RX_PHYS_DSGL_PCITPHNTENB(1U) 3628 3629 #define S_CPL_RX_PHYS_DSGL_PCITPHNT 27 3630 #define M_CPL_RX_PHYS_DSGL_PCITPHNT 0x3 3631 #define V_CPL_RX_PHYS_DSGL_PCITPHNT(x) ((x) << S_CPL_RX_PHYS_DSGL_PCITPHNT) 3632 #define G_CPL_RX_PHYS_DSGL_PCITPHNT(x) \ 3633 (((x) >> S_CPL_RX_PHYS_DSGL_PCITPHNT) & \ 3634 M_CPL_RX_PHYS_DSGL_PCITPHNT) 3635 3636 #define S_CPL_RX_PHYS_DSGL_DCAID 16 3637 #define M_CPL_RX_PHYS_DSGL_DCAID 0x7ff 3638 #define V_CPL_RX_PHYS_DSGL_DCAID(x) ((x) << S_CPL_RX_PHYS_DSGL_DCAID) 3639 #define G_CPL_RX_PHYS_DSGL_DCAID(x) \ 3640 (((x) >> S_CPL_RX_PHYS_DSGL_DCAID) & \ 3641 M_CPL_RX_PHYS_DSGL_DCAID) 3642 3643 #define S_CPL_RX_PHYS_DSGL_NOOFSGENTR 0 3644 #define M_CPL_RX_PHYS_DSGL_NOOFSGENTR 0xffff 3645 #define V_CPL_RX_PHYS_DSGL_NOOFSGENTR(x) \ 3646 ((x) << S_CPL_RX_PHYS_DSGL_NOOFSGENTR) 3647 #define G_CPL_RX_PHYS_DSGL_NOOFSGENTR(x) \ 3648 (((x) >> S_CPL_RX_PHYS_DSGL_NOOFSGENTR) & \ 3649 M_CPL_RX_PHYS_DSGL_NOOFSGENTR) 3650 3651 /* CPL_TX_TLS_ACK */ 3652 struct cpl_tx_tls_ack { 3653 __be32 op_to_Rsvd2; 3654 __be32 PldLen; 3655 __be64 Rsvd3; 3656 }; 3657 3658 #define S_CPL_TX_TLS_ACK_OPCODE 24 3659 #define M_CPL_TX_TLS_ACK_OPCODE 0xff 3660 #define V_CPL_TX_TLS_ACK_OPCODE(x) ((x) << S_CPL_TX_TLS_ACK_OPCODE) 3661 #define G_CPL_TX_TLS_ACK_OPCODE(x) \ 3662 (((x) >> S_CPL_TX_TLS_ACK_OPCODE) & M_CPL_TX_TLS_ACK_OPCODE) 3663 3664 #define S_CPL_TX_TLS_ACK_RSVD1 23 3665 #define M_CPL_TX_TLS_ACK_RSVD1 0x1 3666 #define V_CPL_TX_TLS_ACK_RSVD1(x) ((x) << S_CPL_TX_TLS_ACK_RSVD1) 3667 #define G_CPL_TX_TLS_ACK_RSVD1(x) \ 3668 (((x) >> S_CPL_TX_TLS_ACK_RSVD1) & M_CPL_TX_TLS_ACK_RSVD1) 3669 #define F_CPL_TX_TLS_ACK_RSVD1 V_CPL_TX_TLS_ACK_RSVD1(1U) 3670 3671 #define S_CPL_TX_TLS_ACK_RXCHID 22 3672 #define M_CPL_TX_TLS_ACK_RXCHID 0x1 3673 #define V_CPL_TX_TLS_ACK_RXCHID(x) ((x) << S_CPL_TX_TLS_ACK_RXCHID) 3674 #define G_CPL_TX_TLS_ACK_RXCHID(x) \ 3675 (((x) >> S_CPL_TX_TLS_ACK_RXCHID) & M_CPL_TX_TLS_ACK_RXCHID) 3676 #define F_CPL_TX_TLS_ACK_RXCHID V_CPL_TX_TLS_ACK_RXCHID(1U) 3677 3678 #define S_CPL_TX_TLS_ACK_FWMSG 21 3679 #define M_CPL_TX_TLS_ACK_FWMSG 0x1 3680 #define V_CPL_TX_TLS_ACK_FWMSG(x) ((x) << S_CPL_TX_TLS_ACK_FWMSG) 3681 #define G_CPL_TX_TLS_ACK_FWMSG(x) \ 3682 (((x) >> S_CPL_TX_TLS_ACK_FWMSG) & M_CPL_TX_TLS_ACK_FWMSG) 3683 #define F_CPL_TX_TLS_ACK_FWMSG V_CPL_TX_TLS_ACK_FWMSG(1U) 3684 3685 #define S_CPL_TX_TLS_ACK_ULPTXLPBK 20 3686 #define M_CPL_TX_TLS_ACK_ULPTXLPBK 0x1 3687 #define V_CPL_TX_TLS_ACK_ULPTXLPBK(x) ((x) << S_CPL_TX_TLS_ACK_ULPTXLPBK) 3688 #define G_CPL_TX_TLS_ACK_ULPTXLPBK(x) \ 3689 (((x) >> S_CPL_TX_TLS_ACK_ULPTXLPBK) & M_CPL_TX_TLS_ACK_ULPTXLPBK) 3690 #define F_CPL_TX_TLS_ACK_ULPTXLPBK V_CPL_TX_TLS_ACK_ULPTXLPBK(1U) 3691 3692 #define S_CPL_TX_TLS_ACK_CPLLEN 16 3693 #define M_CPL_TX_TLS_ACK_CPLLEN 0xf 3694 #define V_CPL_TX_TLS_ACK_CPLLEN(x) ((x) << S_CPL_TX_TLS_ACK_CPLLEN) 3695 #define G_CPL_TX_TLS_ACK_CPLLEN(x) \ 3696 (((x) >> S_CPL_TX_TLS_ACK_CPLLEN) & M_CPL_TX_TLS_ACK_CPLLEN) 3697 3698 #define S_CPL_TX_TLS_ACK_COMPLONERR 15 3699 #define M_CPL_TX_TLS_ACK_COMPLONERR 0x1 3700 #define V_CPL_TX_TLS_ACK_COMPLONERR(x) ((x) << S_CPL_TX_TLS_ACK_COMPLONERR) 3701 #define G_CPL_TX_TLS_ACK_COMPLONERR(x) \ 3702 (((x) >> S_CPL_TX_TLS_ACK_COMPLONERR) & M_CPL_TX_TLS_ACK_COMPLONERR) 3703 #define F_CPL_TX_TLS_ACK_COMPLONERR V_CPL_TX_TLS_ACK_COMPLONERR(1U) 3704 3705 #define S_CPL_TX_TLS_ACK_LCB 14 3706 #define M_CPL_TX_TLS_ACK_LCB 0x1 3707 #define V_CPL_TX_TLS_ACK_LCB(x) ((x) << S_CPL_TX_TLS_ACK_LCB) 3708 #define G_CPL_TX_TLS_ACK_LCB(x) \ 3709 (((x) >> S_CPL_TX_TLS_ACK_LCB) & M_CPL_TX_TLS_ACK_LCB) 3710 #define F_CPL_TX_TLS_ACK_LCB V_CPL_TX_TLS_ACK_LCB(1U) 3711 3712 #define S_CPL_TX_TLS_ACK_PHASH 13 3713 #define M_CPL_TX_TLS_ACK_PHASH 0x1 3714 #define V_CPL_TX_TLS_ACK_PHASH(x) ((x) << S_CPL_TX_TLS_ACK_PHASH) 3715 #define G_CPL_TX_TLS_ACK_PHASH(x) \ 3716 (((x) >> S_CPL_TX_TLS_ACK_PHASH) & M_CPL_TX_TLS_ACK_PHASH) 3717 #define F_CPL_TX_TLS_ACK_PHASH V_CPL_TX_TLS_ACK_PHASH(1U) 3718 3719 #define S_CPL_TX_TLS_ACK_RSVD2 0 3720 #define M_CPL_TX_TLS_ACK_RSVD2 0x1fff 3721 #define V_CPL_TX_TLS_ACK_RSVD2(x) ((x) << S_CPL_TX_TLS_ACK_RSVD2) 3722 #define G_CPL_TX_TLS_ACK_RSVD2(x) \ 3723 (((x) >> S_CPL_TX_TLS_ACK_RSVD2) & M_CPL_TX_TLS_ACK_RSVD2) 3724 3725 #endif /* T4_MSG_H */ 3726