1a10443e8SNavdeep Parhar# Chelsio T6 Factory Default configuration file. 2a10443e8SNavdeep Parhar# 3a10443e8SNavdeep Parhar# Copyright (C) 2014-2016 Chelsio Communications. All rights reserved. 4a10443e8SNavdeep Parhar# 5a10443e8SNavdeep Parhar# DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES. MODIFICATION OF THIS FILE 6a10443e8SNavdeep Parhar# WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE 7a10443e8SNavdeep Parhar# TO ADAPTERS. 8a10443e8SNavdeep Parhar 9a10443e8SNavdeep Parhar 10a10443e8SNavdeep Parhar# This file provides the default, power-on configuration for 2-port T6-based 11a10443e8SNavdeep Parhar# adapters shipped from the factory. These defaults are designed to address 12a10443e8SNavdeep Parhar# the needs of the vast majority of Terminator customers. The basic idea is to 13a10443e8SNavdeep Parhar# have a default configuration which allows a customer to plug a Terminator 14a10443e8SNavdeep Parhar# adapter in and have it work regardless of OS, driver or application except in 15a10443e8SNavdeep Parhar# the most unusual and/or demanding customer applications. 16a10443e8SNavdeep Parhar# 17a10443e8SNavdeep Parhar# Many of the Terminator resources which are described by this configuration 18a10443e8SNavdeep Parhar# are finite. This requires balancing the configuration/operation needs of 19a10443e8SNavdeep Parhar# device drivers across OSes and a large number of customer application. 20a10443e8SNavdeep Parhar# 21a10443e8SNavdeep Parhar# Some of the more important resources to allocate and their constaints are: 22a10443e8SNavdeep Parhar# 1. Virtual Interfaces: 256. 23a10443e8SNavdeep Parhar# 2. Ingress Queues with Free Lists: 1024. 24a10443e8SNavdeep Parhar# 3. Egress Queues: 128K. 25a10443e8SNavdeep Parhar# 4. MSI-X Vectors: 1088. 26a10443e8SNavdeep Parhar# 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination 27a10443e8SNavdeep Parhar# address matching on Ingress Packets. 28a10443e8SNavdeep Parhar# 29a10443e8SNavdeep Parhar# Some of the important OS/Driver resource needs are: 30a10443e8SNavdeep Parhar# 6. Some OS Drivers will manage all resources through a single Physical 31a10443e8SNavdeep Parhar# Function (currently PF4 but it could be any Physical Function). 32a10443e8SNavdeep Parhar# 7. Some OS Drivers will manage different ports and functions (NIC, 33a10443e8SNavdeep Parhar# storage, etc.) on different Physical Functions. For example, NIC 34a10443e8SNavdeep Parhar# functions for ports 0-1 on PF0-1, FCoE on PF4, iSCSI on PF5, etc. 35a10443e8SNavdeep Parhar# 36a10443e8SNavdeep Parhar# Some of the customer application needs which need to be accommodated: 37a10443e8SNavdeep Parhar# 8. Some customers will want to support large CPU count systems with 38a10443e8SNavdeep Parhar# good scaling. Thus, we'll need to accommodate a number of 39a10443e8SNavdeep Parhar# Ingress Queues and MSI-X Vectors to allow up to some number of CPUs 40a10443e8SNavdeep Parhar# to be involved per port and per application function. For example, 41a10443e8SNavdeep Parhar# in the case where all ports and application functions will be 42a10443e8SNavdeep Parhar# managed via a single Unified PF and we want to accommodate scaling up 43a10443e8SNavdeep Parhar# to 8 CPUs, we would want: 44a10443e8SNavdeep Parhar# 45a10443e8SNavdeep Parhar# 2 ports * 46a10443e8SNavdeep Parhar# 3 application functions (NIC, FCoE, iSCSI) per port * 47a10443e8SNavdeep Parhar# 16 Ingress Queue/MSI-X Vectors per application function 48a10443e8SNavdeep Parhar# 49a10443e8SNavdeep Parhar# for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF. 50a10443e8SNavdeep Parhar# (Plus a few for Firmware Event Queues, etc.) 51a10443e8SNavdeep Parhar# 52a10443e8SNavdeep Parhar# 9. Some customers will want to use PCI-E SR-IOV Capability to allow Virtual 53a10443e8SNavdeep Parhar# Machines to directly access T6 functionality via SR-IOV Virtual Functions 54a10443e8SNavdeep Parhar# and "PCI Device Passthrough" -- this is especially true for the NIC 55a10443e8SNavdeep Parhar# application functionality. 56a10443e8SNavdeep Parhar# 57a10443e8SNavdeep Parhar 58a10443e8SNavdeep Parhar 59a10443e8SNavdeep Parhar# Global configuration settings. 60a10443e8SNavdeep Parhar# 61a10443e8SNavdeep Parhar[global] 62a10443e8SNavdeep Parhar rss_glb_config_mode = basicvirtual 63a10443e8SNavdeep Parhar rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp 64a10443e8SNavdeep Parhar 65a10443e8SNavdeep Parhar # PL_TIMEOUT register 66a10443e8SNavdeep Parhar pl_timeout_value = 200 # the timeout value in units of us 67a10443e8SNavdeep Parhar 68a10443e8SNavdeep Parhar # The following Scatter Gather Engine (SGE) settings assume a 4KB Host 69a10443e8SNavdeep Parhar # Page Size and a 64B L1 Cache Line Size. It programs the 70a10443e8SNavdeep Parhar # EgrStatusPageSize and IngPadBoundary to 64B and the PktShift to 2. 71a10443e8SNavdeep Parhar # If a Master PF Driver finds itself on a machine with different 72a10443e8SNavdeep Parhar # parameters, then the Master PF Driver is responsible for initializing 73a10443e8SNavdeep Parhar # these parameters to appropriate values. 74a10443e8SNavdeep Parhar # 75a10443e8SNavdeep Parhar # Notes: 76a10443e8SNavdeep Parhar # 1. The Free List Buffer Sizes below are raw and the firmware will 77a10443e8SNavdeep Parhar # round them up to the Ingress Padding Boundary. 78a10443e8SNavdeep Parhar # 2. The SGE Timer Values below are expressed below in microseconds. 79a10443e8SNavdeep Parhar # The firmware will convert these values to Core Clock Ticks when 80a10443e8SNavdeep Parhar # it processes the configuration parameters. 81a10443e8SNavdeep Parhar # 82a10443e8SNavdeep Parhar reg[0x1008] = 0x40810/0x21c70 # SGE_CONTROL 83a10443e8SNavdeep Parhar reg[0x100c] = 0x22222222 # SGE_HOST_PAGE_SIZE 84a10443e8SNavdeep Parhar reg[0x10a0] = 0x01040810 # SGE_INGRESS_RX_THRESHOLD 85a10443e8SNavdeep Parhar reg[0x1044] = 4096 # SGE_FL_BUFFER_SIZE0 86a10443e8SNavdeep Parhar reg[0x1048] = 65536 # SGE_FL_BUFFER_SIZE1 87a10443e8SNavdeep Parhar reg[0x104c] = 1536 # SGE_FL_BUFFER_SIZE2 88a10443e8SNavdeep Parhar reg[0x1050] = 9024 # SGE_FL_BUFFER_SIZE3 89a10443e8SNavdeep Parhar reg[0x1054] = 9216 # SGE_FL_BUFFER_SIZE4 90a10443e8SNavdeep Parhar reg[0x1058] = 2048 # SGE_FL_BUFFER_SIZE5 91a10443e8SNavdeep Parhar reg[0x105c] = 128 # SGE_FL_BUFFER_SIZE6 92a10443e8SNavdeep Parhar reg[0x1060] = 8192 # SGE_FL_BUFFER_SIZE7 93a10443e8SNavdeep Parhar reg[0x1064] = 16384 # SGE_FL_BUFFER_SIZE8 94c88fa719SNavdeep Parhar 95a10443e8SNavdeep Parhar sge_timer_value = 5, 10, 20, 50, 100, 200 # SGE_TIMER_VALUE* in usecs 96a10443e8SNavdeep Parhar reg[0x10c4] = 0x20000000/0x20000000 # GK_CONTROL, enable 5th thread 97a10443e8SNavdeep Parhar 98a10443e8SNavdeep Parhar # enable TP_OUT_CONFIG.IPIDSPLITMODE 99a10443e8SNavdeep Parhar reg[0x7d04] = 0x00010000/0x00010000 100a10443e8SNavdeep Parhar 101a10443e8SNavdeep Parhar reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT 102a10443e8SNavdeep Parhar 103a10443e8SNavdeep Parhar #Tick granularities in kbps 104a10443e8SNavdeep Parhar tsch_ticks = 100000, 10000, 1000, 10 105a10443e8SNavdeep Parhar 106a10443e8SNavdeep Parhar # TP_VLAN_PRI_MAP to select filter tuples and enable ServerSram 107a10443e8SNavdeep Parhar # filter control: compact, fcoemask 108a10443e8SNavdeep Parhar # server sram : srvrsram 109a10443e8SNavdeep Parhar # filter tuples : fragmentation, mpshittype, macmatch, ethertype, 110a10443e8SNavdeep Parhar # protocol, tos, vlan, vnic_id, port, fcoe 111a10443e8SNavdeep Parhar # valid filterModes are described the Terminator 5 Data Book 112c88fa719SNavdeep Parhar filterMode = srvrsram, fragmentation, mpshittype, protocol, vlan, port, fcoe 113a10443e8SNavdeep Parhar 114a10443e8SNavdeep Parhar # filter tuples enforced in LE active region (equal to or subset of filterMode) 115c88fa719SNavdeep Parhar filterMask = protocol 116a10443e8SNavdeep Parhar 117a10443e8SNavdeep Parhar # Percentage of dynamic memory (in either the EDRAM or external MEM) 118a10443e8SNavdeep Parhar # to use for TP RX payload 119a10443e8SNavdeep Parhar tp_pmrx = 30 120a10443e8SNavdeep Parhar 121a10443e8SNavdeep Parhar # TP RX payload page size 122a10443e8SNavdeep Parhar tp_pmrx_pagesize = 64K 123a10443e8SNavdeep Parhar 124a10443e8SNavdeep Parhar # TP number of RX channels 125a10443e8SNavdeep Parhar tp_nrxch = 0 # 0 (auto) = 1 126a10443e8SNavdeep Parhar 127a10443e8SNavdeep Parhar # Percentage of dynamic memory (in either the EDRAM or external MEM) 128a10443e8SNavdeep Parhar # to use for TP TX payload 129a10443e8SNavdeep Parhar tp_pmtx = 50 130a10443e8SNavdeep Parhar 131a10443e8SNavdeep Parhar # TP TX payload page size 132a10443e8SNavdeep Parhar tp_pmtx_pagesize = 64K 133a10443e8SNavdeep Parhar 134a10443e8SNavdeep Parhar # TP number of TX channels 135a10443e8SNavdeep Parhar tp_ntxch = 0 # 0 (auto) = equal number of ports 136a10443e8SNavdeep Parhar 137a10443e8SNavdeep Parhar # TP OFLD MTUs 138a10443e8SNavdeep Parhar tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600 139a10443e8SNavdeep Parhar 140a10443e8SNavdeep Parhar # enable TP_OUT_CONFIG.IPIDSPLITMODE and CRXPKTENC 141a10443e8SNavdeep Parhar reg[0x7d04] = 0x00010008/0x00010008 142a10443e8SNavdeep Parhar 143a10443e8SNavdeep Parhar # TP_GLOBAL_CONFIG 144a10443e8SNavdeep Parhar reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable 145a10443e8SNavdeep Parhar 146a10443e8SNavdeep Parhar # TP_PC_CONFIG 147a10443e8SNavdeep Parhar reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError 148a10443e8SNavdeep Parhar 149a10443e8SNavdeep Parhar # TP_PARA_REG0 150a10443e8SNavdeep Parhar reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6 151a10443e8SNavdeep Parhar 152a10443e8SNavdeep Parhar # LE_DB_CONFIG 153a10443e8SNavdeep Parhar reg[0x19c04] = 0x00000000/0x00440000 # LE Server SRAM disabled 154a10443e8SNavdeep Parhar # LE IPv4 compression disabled 155a10443e8SNavdeep Parhar # LE_DB_HASH_CONFIG 156a10443e8SNavdeep Parhar reg[0x19c28] = 0x00800000/0x01f00000 # LE Hash bucket size 8, 157a10443e8SNavdeep Parhar 158a10443e8SNavdeep Parhar # ULP_TX_CONFIG 159a10443e8SNavdeep Parhar reg[0x8dc0] = 0x00000104/0x00000104 # Enable ITT on PI err 160a10443e8SNavdeep Parhar # Enable more error msg for ... 161a10443e8SNavdeep Parhar # TPT error. 162a10443e8SNavdeep Parhar 163a10443e8SNavdeep Parhar # ULP_RX_MISC_FEATURE_ENABLE 164a10443e8SNavdeep Parhar #reg[0x1925c] = 0x01003400/0x01003400 # iscsi tag pi bit 165a10443e8SNavdeep Parhar # Enable offset decrement after ... 166a10443e8SNavdeep Parhar # PI extraction and before DDP 167a10443e8SNavdeep Parhar # ulp insert pi source info in DIF 168a10443e8SNavdeep Parhar # iscsi_eff_offset_en 169a10443e8SNavdeep Parhar 170a10443e8SNavdeep Parhar #Enable iscsi completion moderation feature 171a10443e8SNavdeep Parhar reg[0x1925c] = 0x000041c0/0x000031c0 # Enable offset decrement after 172a10443e8SNavdeep Parhar # PI extraction and before DDP. 173a10443e8SNavdeep Parhar # ulp insert pi source info in 174a10443e8SNavdeep Parhar # DIF. 175a10443e8SNavdeep Parhar # Enable iscsi hdr cmd mode. 176a10443e8SNavdeep Parhar # iscsi force cmd mode. 177a10443e8SNavdeep Parhar # Enable iscsi cmp mode. 178a10443e8SNavdeep Parhar # MC configuration 179a10443e8SNavdeep Parhar #mc_mode_brc[0] = 1 # mc0 - 1: enable BRC, 0: enable RBC 180a10443e8SNavdeep Parhar 181a10443e8SNavdeep Parhar# Some "definitions" to make the rest of this a bit more readable. We support 182a10443e8SNavdeep Parhar# 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets" 183a10443e8SNavdeep Parhar# per function per port ... 184a10443e8SNavdeep Parhar# 185a10443e8SNavdeep Parhar# NMSIX = 1088 # available MSI-X Vectors 186a10443e8SNavdeep Parhar# NVI = 256 # available Virtual Interfaces 187a10443e8SNavdeep Parhar# NMPSTCAM = 336 # MPS TCAM entries 188a10443e8SNavdeep Parhar# 189a10443e8SNavdeep Parhar# NPORTS = 2 # ports 190a10443e8SNavdeep Parhar# NCPUS = 16 # CPUs we want to support scalably 191a10443e8SNavdeep Parhar# NFUNCS = 3 # functions per port (NIC, FCoE, iSCSI) 192a10443e8SNavdeep Parhar 193a10443e8SNavdeep Parhar# Breakdown of Virtual Interface/Queue/Interrupt resources for the "Unified 194a10443e8SNavdeep Parhar# PF" which many OS Drivers will use to manage most or all functions. 195a10443e8SNavdeep Parhar# 196a10443e8SNavdeep Parhar# Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can 197a10443e8SNavdeep Parhar# use Forwarded Interrupt Ingress Queues. For these latter, an Ingress Queue 198a10443e8SNavdeep Parhar# would be created and the Queue ID of a Forwarded Interrupt Ingress Queue 199a10443e8SNavdeep Parhar# will be specified as the "Ingress Queue Asynchronous Destination Index." 200a10443e8SNavdeep Parhar# Thus, the number of MSI-X Vectors assigned to the Unified PF will be less 201a10443e8SNavdeep Parhar# than or equal to the number of Ingress Queues ... 202a10443e8SNavdeep Parhar# 203a10443e8SNavdeep Parhar# NVI_NIC = 4 # NIC access to NPORTS 204a10443e8SNavdeep Parhar# NFLIQ_NIC = 32 # NIC Ingress Queues with Free Lists 205a10443e8SNavdeep Parhar# NETHCTRL_NIC = 32 # NIC Ethernet Control/TX Queues 206a10443e8SNavdeep Parhar# NEQ_NIC = 64 # NIC Egress Queues (FL, ETHCTRL/TX) 207a10443e8SNavdeep Parhar# NMPSTCAM_NIC = 16 # NIC MPS TCAM Entries (NPORTS*4) 208a10443e8SNavdeep Parhar# NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ) 209a10443e8SNavdeep Parhar# 210a10443e8SNavdeep Parhar# NVI_OFLD = 0 # Offload uses NIC function to access ports 211a10443e8SNavdeep Parhar# NFLIQ_OFLD = 16 # Offload Ingress Queues with Free Lists 212a10443e8SNavdeep Parhar# NETHCTRL_OFLD = 0 # Offload Ethernet Control/TX Queues 213a10443e8SNavdeep Parhar# NEQ_OFLD = 16 # Offload Egress Queues (FL) 214a10443e8SNavdeep Parhar# NMPSTCAM_OFLD = 0 # Offload MPS TCAM Entries (uses NIC's) 215a10443e8SNavdeep Parhar# NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ) 216a10443e8SNavdeep Parhar# 217a10443e8SNavdeep Parhar# NVI_RDMA = 0 # RDMA uses NIC function to access ports 218a10443e8SNavdeep Parhar# NFLIQ_RDMA = 4 # RDMA Ingress Queues with Free Lists 219a10443e8SNavdeep Parhar# NETHCTRL_RDMA = 0 # RDMA Ethernet Control/TX Queues 220a10443e8SNavdeep Parhar# NEQ_RDMA = 4 # RDMA Egress Queues (FL) 221a10443e8SNavdeep Parhar# NMPSTCAM_RDMA = 0 # RDMA MPS TCAM Entries (uses NIC's) 222a10443e8SNavdeep Parhar# NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ) 223a10443e8SNavdeep Parhar# 224a10443e8SNavdeep Parhar# NEQ_WD = 128 # Wire Direct TX Queues and FLs 225a10443e8SNavdeep Parhar# NETHCTRL_WD = 64 # Wire Direct TX Queues 226a10443e8SNavdeep Parhar# NFLIQ_WD = 64 ` # Wire Direct Ingress Queues with Free Lists 227a10443e8SNavdeep Parhar# 228a10443e8SNavdeep Parhar# NVI_ISCSI = 4 # ISCSI access to NPORTS 229a10443e8SNavdeep Parhar# NFLIQ_ISCSI = 4 # ISCSI Ingress Queues with Free Lists 230a10443e8SNavdeep Parhar# NETHCTRL_ISCSI = 0 # ISCSI Ethernet Control/TX Queues 231a10443e8SNavdeep Parhar# NEQ_ISCSI = 4 # ISCSI Egress Queues (FL) 232a10443e8SNavdeep Parhar# NMPSTCAM_ISCSI = 4 # ISCSI MPS TCAM Entries (NPORTS) 233a10443e8SNavdeep Parhar# NMSIX_ISCSI = 4 # ISCSI MSI-X Interrupt Vectors (FLIQ) 234a10443e8SNavdeep Parhar# 235a10443e8SNavdeep Parhar# NVI_FCOE = 4 # FCOE access to NPORTS 236a10443e8SNavdeep Parhar# NFLIQ_FCOE = 34 # FCOE Ingress Queues with Free Lists 237a10443e8SNavdeep Parhar# NETHCTRL_FCOE = 32 # FCOE Ethernet Control/TX Queues 238a10443e8SNavdeep Parhar# NEQ_FCOE = 66 # FCOE Egress Queues (FL) 239a10443e8SNavdeep Parhar# NMPSTCAM_FCOE = 32 # FCOE MPS TCAM Entries (NPORTS) 240a10443e8SNavdeep Parhar# NMSIX_FCOE = 34 # FCOE MSI-X Interrupt Vectors (FLIQ) 241a10443e8SNavdeep Parhar 242a10443e8SNavdeep Parhar# Two extra Ingress Queues per function for Firmware Events and Forwarded 243a10443e8SNavdeep Parhar# Interrupts, and two extra interrupts per function for Firmware Events (or a 244a10443e8SNavdeep Parhar# Forwarded Interrupt Queue) and General Interrupts per function. 245a10443e8SNavdeep Parhar# 246a10443e8SNavdeep Parhar# NFLIQ_EXTRA = 6 # "extra" Ingress Queues 2*NFUNCS (Firmware and 247a10443e8SNavdeep Parhar# # Forwarded Interrupts 248a10443e8SNavdeep Parhar# NMSIX_EXTRA = 6 # extra interrupts 2*NFUNCS (Firmware and 249a10443e8SNavdeep Parhar# # General Interrupts 250a10443e8SNavdeep Parhar 251a10443e8SNavdeep Parhar# Microsoft HyperV resources. The HyperV Virtual Ingress Queues will have 252a10443e8SNavdeep Parhar# their interrupts forwarded to another set of Forwarded Interrupt Queues. 253a10443e8SNavdeep Parhar# 254a10443e8SNavdeep Parhar# NVI_HYPERV = 16 # VMs we want to support 255a10443e8SNavdeep Parhar# NVIIQ_HYPERV = 2 # Virtual Ingress Queues with Free Lists per VM 256a10443e8SNavdeep Parhar# NFLIQ_HYPERV = 40 # VIQs + NCPUS Forwarded Interrupt Queues 257a10443e8SNavdeep Parhar# NEQ_HYPERV = 32 # VIQs Free Lists 258a10443e8SNavdeep Parhar# NMPSTCAM_HYPERV = 16 # MPS TCAM Entries (NVI_HYPERV) 259a10443e8SNavdeep Parhar# NMSIX_HYPERV = 8 # NCPUS Forwarded Interrupt Queues 260a10443e8SNavdeep Parhar 261a10443e8SNavdeep Parhar# Adding all of the above Unified PF resource needs together: (NIC + OFLD + 262a10443e8SNavdeep Parhar# RDMA + ISCSI + FCOE + EXTRA + HYPERV) 263a10443e8SNavdeep Parhar# 264a10443e8SNavdeep Parhar# NVI_UNIFIED = 28 265a10443e8SNavdeep Parhar# NFLIQ_UNIFIED = 106 266a10443e8SNavdeep Parhar# NETHCTRL_UNIFIED = 32 267a10443e8SNavdeep Parhar# NEQ_UNIFIED = 124 268a10443e8SNavdeep Parhar# NMPSTCAM_UNIFIED = 40 269a10443e8SNavdeep Parhar# 270a10443e8SNavdeep Parhar# The sum of all the MSI-X resources above is 74 MSI-X Vectors but we'll round 271a10443e8SNavdeep Parhar# that up to 128 to make sure the Unified PF doesn't run out of resources. 272a10443e8SNavdeep Parhar# 273a10443e8SNavdeep Parhar# NMSIX_UNIFIED = 128 274a10443e8SNavdeep Parhar# 275a10443e8SNavdeep Parhar# The Storage PFs could need up to NPORTS*NCPUS + NMSIX_EXTRA MSI-X Vectors 276a10443e8SNavdeep Parhar# which is 34 but they're probably safe with 32. 277a10443e8SNavdeep Parhar# 278a10443e8SNavdeep Parhar# NMSIX_STORAGE = 32 279a10443e8SNavdeep Parhar 280a10443e8SNavdeep Parhar# Note: The UnifiedPF is PF4 which doesn't have any Virtual Functions 281a10443e8SNavdeep Parhar# associated with it. Thus, the MSI-X Vector allocations we give to the 282a10443e8SNavdeep Parhar# UnifiedPF aren't inherited by any Virtual Functions. As a result we can 283a10443e8SNavdeep Parhar# provision many more Virtual Functions than we can if the UnifiedPF were 284a10443e8SNavdeep Parhar# one of PF0-3. 285a10443e8SNavdeep Parhar# 286a10443e8SNavdeep Parhar 287a10443e8SNavdeep Parhar# All of the below PCI-E parameters are actually stored in various *_init.txt 288a10443e8SNavdeep Parhar# files. We include them below essentially as comments. 289a10443e8SNavdeep Parhar# 290a10443e8SNavdeep Parhar# For PF0-3 we assign 8 vectors each for NIC Ingress Queues of the associated 291a10443e8SNavdeep Parhar# ports 0-3. 292a10443e8SNavdeep Parhar# 293a10443e8SNavdeep Parhar# For PF4, the Unified PF, we give it an MSI-X Table Size as outlined above. 294a10443e8SNavdeep Parhar# 295a10443e8SNavdeep Parhar# For PF5-6 we assign enough MSI-X Vectors to support FCoE and iSCSI 296a10443e8SNavdeep Parhar# storage applications across all four possible ports. 297a10443e8SNavdeep Parhar# 298a10443e8SNavdeep Parhar# Additionally, since the UnifiedPF isn't one of the per-port Physical 299a10443e8SNavdeep Parhar# Functions, we give the UnifiedPF and the PF0-3 Physical Functions 300a10443e8SNavdeep Parhar# different PCI Device IDs which will allow Unified and Per-Port Drivers 301a10443e8SNavdeep Parhar# to directly select the type of Physical Function to which they wish to be 302a10443e8SNavdeep Parhar# attached. 303a10443e8SNavdeep Parhar# 304a10443e8SNavdeep Parhar# Note that the actual values used for the PCI-E Intelectual Property will be 305a10443e8SNavdeep Parhar# 1 less than those below since that's the way it "counts" things. For 306a10443e8SNavdeep Parhar# readability, we use the number we actually mean ... 307a10443e8SNavdeep Parhar# 308a10443e8SNavdeep Parhar# PF0_INT = 8 # NCPUS 309a10443e8SNavdeep Parhar# PF1_INT = 8 # NCPUS 310a10443e8SNavdeep Parhar# PF0_3_INT = 32 # PF0_INT + PF1_INT + PF2_INT + PF3_INT 311a10443e8SNavdeep Parhar# 312a10443e8SNavdeep Parhar# PF4_INT = 128 # NMSIX_UNIFIED 313a10443e8SNavdeep Parhar# PF5_INT = 32 # NMSIX_STORAGE 314a10443e8SNavdeep Parhar# PF6_INT = 32 # NMSIX_STORAGE 315a10443e8SNavdeep Parhar# PF7_INT = 0 # Nothing Assigned 316a10443e8SNavdeep Parhar# PF4_7_INT = 192 # PF4_INT + PF5_INT + PF6_INT + PF7_INT 317a10443e8SNavdeep Parhar# 318a10443e8SNavdeep Parhar# PF0_7_INT = 224 # PF0_3_INT + PF4_7_INT 319a10443e8SNavdeep Parhar# 320a10443e8SNavdeep Parhar# With the above we can get 17 VFs/PF0-3 (limited by 336 MPS TCAM entries) 321a10443e8SNavdeep Parhar# but we'll lower that to 16 to make our total 64 and a nice power of 2 ... 322a10443e8SNavdeep Parhar# 323a10443e8SNavdeep Parhar# NVF = 16 324a10443e8SNavdeep Parhar 325a10443e8SNavdeep Parhar 326a10443e8SNavdeep Parhar# For those OSes which manage different ports on different PFs, we need 327a10443e8SNavdeep Parhar# only enough resources to support a single port's NIC application functions 328a10443e8SNavdeep Parhar# on PF0-3. The below assumes that we're only doing NIC with NCPUS "Queue 329a10443e8SNavdeep Parhar# Sets" for ports 0-3. The FCoE and iSCSI functions for such OSes will be 330a10443e8SNavdeep Parhar# managed on the "storage PFs" (see below). 331a10443e8SNavdeep Parhar# 332a10443e8SNavdeep Parhar[function "0"] 333a10443e8SNavdeep Parhar nvf = 16 # NVF on this function 334a10443e8SNavdeep Parhar wx_caps = all # write/execute permissions for all commands 335a10443e8SNavdeep Parhar r_caps = all # read permissions for all commands 336a10443e8SNavdeep Parhar nvi = 1 # 1 port 337a10443e8SNavdeep Parhar niqflint = 8 # NCPUS "Queue Sets" 338a10443e8SNavdeep Parhar nethctrl = 8 # NCPUS "Queue Sets" 339a10443e8SNavdeep Parhar neq = 16 # niqflint + nethctrl Egress Queues 340a10443e8SNavdeep Parhar nexactf = 8 # number of exact MPSTCAM MAC filters 341a10443e8SNavdeep Parhar cmask = all # access to all channels 342a10443e8SNavdeep Parhar pmask = 0x1 # access to only one port 343a10443e8SNavdeep Parhar 344a10443e8SNavdeep Parhar 345a10443e8SNavdeep Parhar[function "1"] 346a10443e8SNavdeep Parhar nvf = 16 # NVF on this function 347a10443e8SNavdeep Parhar wx_caps = all # write/execute permissions for all commands 348a10443e8SNavdeep Parhar r_caps = all # read permissions for all commands 349a10443e8SNavdeep Parhar nvi = 1 # 1 port 350a10443e8SNavdeep Parhar niqflint = 8 # NCPUS "Queue Sets" 351a10443e8SNavdeep Parhar nethctrl = 8 # NCPUS "Queue Sets" 352a10443e8SNavdeep Parhar neq = 16 # niqflint + nethctrl Egress Queues 353a10443e8SNavdeep Parhar nexactf = 8 # number of exact MPSTCAM MAC filters 354a10443e8SNavdeep Parhar cmask = all # access to all channels 355a10443e8SNavdeep Parhar pmask = 0x2 # access to only one port 356a10443e8SNavdeep Parhar 357a10443e8SNavdeep Parhar[function "2"] 358a10443e8SNavdeep Parhar nvf = 16 # NVF on this function 359a10443e8SNavdeep Parhar wx_caps = all # write/execute permissions for all commands 360a10443e8SNavdeep Parhar r_caps = all # read permissions for all commands 361a10443e8SNavdeep Parhar nvi = 1 # 1 port 362a10443e8SNavdeep Parhar niqflint = 8 # NCPUS "Queue Sets" 363a10443e8SNavdeep Parhar nethctrl = 8 # NCPUS "Queue Sets" 364a10443e8SNavdeep Parhar neq = 16 # niqflint + nethctrl Egress Queues 365a10443e8SNavdeep Parhar nexactf = 8 # number of exact MPSTCAM MAC filters 366a10443e8SNavdeep Parhar cmask = all # access to all channels 367a10443e8SNavdeep Parhar pmask = 0x4 # access to only one port 368a10443e8SNavdeep Parhar 369a10443e8SNavdeep Parhar[function "3"] 370a10443e8SNavdeep Parhar nvf = 16 # NVF on this function 371a10443e8SNavdeep Parhar wx_caps = all # write/execute permissions for all commands 372a10443e8SNavdeep Parhar r_caps = all # read permissions for all commands 373a10443e8SNavdeep Parhar nvi = 1 # 1 port 374a10443e8SNavdeep Parhar niqflint = 8 # NCPUS "Queue Sets" 375a10443e8SNavdeep Parhar nethctrl = 8 # NCPUS "Queue Sets" 376a10443e8SNavdeep Parhar neq = 16 # niqflint + nethctrl Egress Queues 377a10443e8SNavdeep Parhar nexactf = 8 # number of exact MPSTCAM MAC filters 378a10443e8SNavdeep Parhar cmask = all # access to all channels 379a10443e8SNavdeep Parhar pmask = 0x8 # access to only one port 380a10443e8SNavdeep Parhar 381a10443e8SNavdeep Parhar 382a10443e8SNavdeep Parhar# Some OS Drivers manage all application functions for all ports via PF4. 383a10443e8SNavdeep Parhar# Thus we need to provide a large number of resources here. For Egress 384a10443e8SNavdeep Parhar# Queues we need to account for both TX Queues as well as Free List Queues 385a10443e8SNavdeep Parhar# (because the host is responsible for producing Free List Buffers for the 386a10443e8SNavdeep Parhar# hardware to consume). 387a10443e8SNavdeep Parhar# 388a10443e8SNavdeep Parhar[function "4"] 389a10443e8SNavdeep Parhar wx_caps = all # write/execute permissions for all commands 390a10443e8SNavdeep Parhar r_caps = all # read permissions for all commands 391a10443e8SNavdeep Parhar nvi = 28 # NVI_UNIFIED 392a10443e8SNavdeep Parhar niqflint = 202 # NFLIQ_UNIFIED + NLFIQ_WD + NFLIQ_CRYPTO (32) 393a10443e8SNavdeep Parhar nethctrl = 100 # NETHCTRL_UNIFIED + NETHCTRL_WD 394a10443e8SNavdeep Parhar neq = 256 # NEQ_UNIFIED + NEQ_WD 395a10443e8SNavdeep Parhar nqpcq = 12288 396a10443e8SNavdeep Parhar nexactf = 40 # NMPSTCAM_UNIFIED 397c88fa719SNavdeep Parhar nrawf = 2 398a10443e8SNavdeep Parhar cmask = all # access to all channels 399a10443e8SNavdeep Parhar pmask = all # access to all four ports ... 400a10443e8SNavdeep Parhar nethofld = 1024 # number of user mode ethernet flow contexts 401a10443e8SNavdeep Parhar ncrypto_lookaside = 16 # Number of lookaside flow contexts 402a10443e8SNavdeep Parhar nclip = 320 # number of clip region entries 403a10443e8SNavdeep Parhar nfilter = 496 # number of filter region entries 404a10443e8SNavdeep Parhar nserver = 496 # number of server region entries 405a10443e8SNavdeep Parhar nhash = 12288 # number of hash region entries 406a10443e8SNavdeep Parhar nhpfilter = 0 # number of high priority filter region entries 407a10443e8SNavdeep Parhar protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif, tlskeys, crypto_lookaside 408a10443e8SNavdeep Parhar tp_l2t = 3072 409a10443e8SNavdeep Parhar tp_ddp = 2 410a10443e8SNavdeep Parhar tp_ddp_iscsi = 2 411a10443e8SNavdeep Parhar tp_tls_key = 3 4123cbaf64fSNavdeep Parhar tp_tls_mxrxsize = 17408 # 16384 + 1024, governs max rx data, pm max xfer len, rx coalesce sizes 413a10443e8SNavdeep Parhar tp_stag = 2 414a10443e8SNavdeep Parhar tp_pbl = 5 415a10443e8SNavdeep Parhar tp_rq = 7 416a10443e8SNavdeep Parhar tp_srq = 128 417a10443e8SNavdeep Parhar 418a10443e8SNavdeep Parhar# We have FCoE and iSCSI storage functions on PF5 and PF6 each of which may 419a10443e8SNavdeep Parhar# need to have Virtual Interfaces on each of the four ports with up to NCPUS 420a10443e8SNavdeep Parhar# "Queue Sets" each. 421a10443e8SNavdeep Parhar# 422a10443e8SNavdeep Parhar[function "5"] 423a10443e8SNavdeep Parhar wx_caps = all # write/execute permissions for all commands 424a10443e8SNavdeep Parhar r_caps = all # read permissions for all commands 425a10443e8SNavdeep Parhar nvi = 4 # NPORTS 426a10443e8SNavdeep Parhar niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA 427a10443e8SNavdeep Parhar nethctrl = 32 # NPORTS*NCPUS 428a10443e8SNavdeep Parhar neq = 64 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) 429a10443e8SNavdeep Parhar nexactf = 16 # (NPORTS *(no of snmc grp + 1 hw mac) + 1 anmc grp)) rounded to 16. 430a10443e8SNavdeep Parhar cmask = all # access to all channels 431a10443e8SNavdeep Parhar pmask = all # access to all four ports ... 432a10443e8SNavdeep Parhar nserver = 16 433a10443e8SNavdeep Parhar nhash = 2048 434a10443e8SNavdeep Parhar tp_l2t = 1020 435a10443e8SNavdeep Parhar nclip = 64 436a10443e8SNavdeep Parhar protocol = iscsi_initiator_fofld 437a10443e8SNavdeep Parhar tp_ddp_iscsi = 2 438a10443e8SNavdeep Parhar iscsi_ntask = 2048 439a10443e8SNavdeep Parhar iscsi_nsess = 2048 440a10443e8SNavdeep Parhar iscsi_nconn_per_session = 1 441a10443e8SNavdeep Parhar iscsi_ninitiator_instance = 64 442a10443e8SNavdeep Parhar 443a10443e8SNavdeep Parhar 444a10443e8SNavdeep Parhar[function "6"] 445a10443e8SNavdeep Parhar wx_caps = all # write/execute permissions for all commands 446a10443e8SNavdeep Parhar r_caps = all # read permissions for all commands 447a10443e8SNavdeep Parhar nvi = 4 # NPORTS 448a10443e8SNavdeep Parhar niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA 449a10443e8SNavdeep Parhar nethctrl = 32 # NPORTS*NCPUS 450a10443e8SNavdeep Parhar neq = 66 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) + 2 (EXTRA) 451a10443e8SNavdeep Parhar nexactf = 32 # NPORTS + adding 28 exact entries for FCoE 452a10443e8SNavdeep Parhar # which is OK since < MIN(SUM PF0..3, PF4) 453a10443e8SNavdeep Parhar # and we never load PF0..3 and PF4 concurrently 454a10443e8SNavdeep Parhar cmask = all # access to all channels 455a10443e8SNavdeep Parhar pmask = all # access to all four ports ... 456a10443e8SNavdeep Parhar nhash = 2048 457a10443e8SNavdeep Parhar tp_l2t = 4 458a10443e8SNavdeep Parhar protocol = fcoe_initiator 459a10443e8SNavdeep Parhar tp_ddp = 2 460a10443e8SNavdeep Parhar fcoe_nfcf = 16 461a10443e8SNavdeep Parhar fcoe_nvnp = 32 462a10443e8SNavdeep Parhar fcoe_nssn = 1024 463a10443e8SNavdeep Parhar 464a10443e8SNavdeep Parhar 465a10443e8SNavdeep Parhar# The following function, 1023, is not an actual PCIE function but is used to 466a10443e8SNavdeep Parhar# configure and reserve firmware internal resources that come from the global 467a10443e8SNavdeep Parhar# resource pool. 468a10443e8SNavdeep Parhar# 469a10443e8SNavdeep Parhar[function "1023"] 470a10443e8SNavdeep Parhar wx_caps = all # write/execute permissions for all commands 471a10443e8SNavdeep Parhar r_caps = all # read permissions for all commands 472a10443e8SNavdeep Parhar nvi = 4 # NVI_UNIFIED 473a10443e8SNavdeep Parhar cmask = all # access to all channels 474a10443e8SNavdeep Parhar pmask = all # access to all four ports ... 475a10443e8SNavdeep Parhar nexactf = 8 # NPORTS + DCBX + 476a10443e8SNavdeep Parhar nfilter = 16 # number of filter region entries 477a10443e8SNavdeep Parhar 478a10443e8SNavdeep Parhar 479a10443e8SNavdeep Parhar# For Virtual functions, we only allow NIC functionality and we only allow 480a10443e8SNavdeep Parhar# access to one port (1 << PF). Note that because of limitations in the 481a10443e8SNavdeep Parhar# Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL 482a10443e8SNavdeep Parhar# and GTS registers, the number of Ingress and Egress Queues must be a power 483a10443e8SNavdeep Parhar# of 2. 484a10443e8SNavdeep Parhar# 485a10443e8SNavdeep Parhar[function "0/*"] # NVF 486a10443e8SNavdeep Parhar wx_caps = 0x82 # DMAQ | VF 487a10443e8SNavdeep Parhar r_caps = 0x86 # DMAQ | VF | PORT 488a10443e8SNavdeep Parhar nvi = 1 # 1 port 489a10443e8SNavdeep Parhar niqflint = 4 # 2 "Queue Sets" + NXIQ 490a10443e8SNavdeep Parhar nethctrl = 2 # 2 "Queue Sets" 491a10443e8SNavdeep Parhar neq = 4 # 2 "Queue Sets" * 2 492a10443e8SNavdeep Parhar nexactf = 4 493a10443e8SNavdeep Parhar cmask = all # access to all channels 494a10443e8SNavdeep Parhar pmask = 0x1 # access to only one port ... 495a10443e8SNavdeep Parhar 496a10443e8SNavdeep Parhar 497a10443e8SNavdeep Parhar[function "1/*"] # NVF 498a10443e8SNavdeep Parhar wx_caps = 0x82 # DMAQ | VF 499a10443e8SNavdeep Parhar r_caps = 0x86 # DMAQ | VF | PORT 500a10443e8SNavdeep Parhar nvi = 1 # 1 port 501a10443e8SNavdeep Parhar niqflint = 4 # 2 "Queue Sets" + NXIQ 502a10443e8SNavdeep Parhar nethctrl = 2 # 2 "Queue Sets" 503a10443e8SNavdeep Parhar neq = 4 # 2 "Queue Sets" * 2 504a10443e8SNavdeep Parhar nexactf = 4 505a10443e8SNavdeep Parhar cmask = all # access to all channels 506a10443e8SNavdeep Parhar pmask = 0x2 # access to only one port ... 507a10443e8SNavdeep Parhar 508a10443e8SNavdeep Parhar[function "2/*"] # NVF 509a10443e8SNavdeep Parhar wx_caps = 0x82 # DMAQ | VF 510a10443e8SNavdeep Parhar r_caps = 0x86 # DMAQ | VF | PORT 511a10443e8SNavdeep Parhar nvi = 1 # 1 port 512a10443e8SNavdeep Parhar niqflint = 4 # 2 "Queue Sets" + NXIQ 513a10443e8SNavdeep Parhar nethctrl = 2 # 2 "Queue Sets" 514a10443e8SNavdeep Parhar neq = 4 # 2 "Queue Sets" * 2 515a10443e8SNavdeep Parhar nexactf = 4 516a10443e8SNavdeep Parhar cmask = all # access to all channels 517a10443e8SNavdeep Parhar pmask = 0x1 # access to only one port ... 518a10443e8SNavdeep Parhar 519a10443e8SNavdeep Parhar 520a10443e8SNavdeep Parhar[function "3/*"] # NVF 521a10443e8SNavdeep Parhar wx_caps = 0x82 # DMAQ | VF 522a10443e8SNavdeep Parhar r_caps = 0x86 # DMAQ | VF | PORT 523a10443e8SNavdeep Parhar nvi = 1 # 1 port 524a10443e8SNavdeep Parhar niqflint = 4 # 2 "Queue Sets" + NXIQ 525a10443e8SNavdeep Parhar nethctrl = 2 # 2 "Queue Sets" 526a10443e8SNavdeep Parhar neq = 4 # 2 "Queue Sets" * 2 527a10443e8SNavdeep Parhar nexactf = 4 528a10443e8SNavdeep Parhar cmask = all # access to all channels 529a10443e8SNavdeep Parhar pmask = 0x2 # access to only one port ... 530a10443e8SNavdeep Parhar 531a10443e8SNavdeep Parhar# MPS features a 196608 bytes ingress buffer that is used for ingress buffering 532a10443e8SNavdeep Parhar# for packets from the wire as well as the loopback path of the L2 switch. The 533a10443e8SNavdeep Parhar# folling params control how the buffer memory is distributed and the L2 flow 534a10443e8SNavdeep Parhar# control settings: 535a10443e8SNavdeep Parhar# 536a10443e8SNavdeep Parhar# bg_mem: %-age of mem to use for port/buffer group 537a10443e8SNavdeep Parhar# lpbk_mem: %-age of port/bg mem to use for loopback 538a10443e8SNavdeep Parhar# hwm: high watermark; bytes available when starting to send pause 539a10443e8SNavdeep Parhar# frames (in units of 0.1 MTU) 540a10443e8SNavdeep Parhar# lwm: low watermark; bytes remaining when sending 'unpause' frame 541a10443e8SNavdeep Parhar# (in inuits of 0.1 MTU) 542a10443e8SNavdeep Parhar# dwm: minimum delta between high and low watermark (in units of 100 543a10443e8SNavdeep Parhar# Bytes) 544a10443e8SNavdeep Parhar# 545a10443e8SNavdeep Parhar[port "0"] 546a10443e8SNavdeep Parhar dcb = ppp, dcbx # configure for DCB PPP and enable DCBX offload 547a10443e8SNavdeep Parhar #bg_mem = 25 548a10443e8SNavdeep Parhar #lpbk_mem = 25 549a10443e8SNavdeep Parhar hwm = 60 550a10443e8SNavdeep Parhar lwm = 15 551a10443e8SNavdeep Parhar dwm = 30 552a10443e8SNavdeep Parhar dcb_app_tlv[0] = 0x8906, ethertype, 3 553a10443e8SNavdeep Parhar dcb_app_tlv[1] = 0x8914, ethertype, 3 554a10443e8SNavdeep Parhar dcb_app_tlv[2] = 3260, socketnum, 5 5553cbaf64fSNavdeep Parhar #aec_retry_cnt = 4 5563cbaf64fSNavdeep Parhar flags = an_dis 557a10443e8SNavdeep Parhar 558a10443e8SNavdeep Parhar 559a10443e8SNavdeep Parhar[port "1"] 560a10443e8SNavdeep Parhar dcb = ppp, dcbx 561a10443e8SNavdeep Parhar #bg_mem = 25 562a10443e8SNavdeep Parhar #lpbk_mem = 25 563a10443e8SNavdeep Parhar hwm = 60 564a10443e8SNavdeep Parhar lwm = 15 565a10443e8SNavdeep Parhar dwm = 30 566a10443e8SNavdeep Parhar dcb_app_tlv[0] = 0x8906, ethertype, 3 567a10443e8SNavdeep Parhar dcb_app_tlv[1] = 0x8914, ethertype, 3 568a10443e8SNavdeep Parhar dcb_app_tlv[2] = 3260, socketnum, 5 5693cbaf64fSNavdeep Parhar #aec_retry_cnt = 4 5703cbaf64fSNavdeep Parhar flags = an_dis 571a10443e8SNavdeep Parhar 572a10443e8SNavdeep Parhar 573a10443e8SNavdeep Parhar[fini] 574c88fa719SNavdeep Parhar version = 0x01000025 575c88fa719SNavdeep Parhar checksum = 0xb23e8983 576a10443e8SNavdeep Parhar 577a10443e8SNavdeep Parhar# Total resources used by above allocations: 578a10443e8SNavdeep Parhar# Virtual Interfaces: 104 579a10443e8SNavdeep Parhar# Ingress Queues/w Free Lists and Interrupts: 526 580a10443e8SNavdeep Parhar# Egress Queues: 702 581a10443e8SNavdeep Parhar# MPS TCAM Entries: 336 582a10443e8SNavdeep Parhar# MSI-X Vectors: 736 583a10443e8SNavdeep Parhar# Virtual Functions: 64 584a10443e8SNavdeep Parhar# 585a10443e8SNavdeep Parhar# $FreeBSD$ 586a10443e8SNavdeep Parhar# 587