1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2009-2013 Chelsio, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 * 33 * $FreeBSD$ 34 */ 35 #ifndef __T4_H__ 36 #define __T4_H__ 37 38 #include "common/t4_regs_values.h" 39 #include "common/t4_regs.h" 40 /* 41 * Fixme: Adding missing defines 42 */ 43 #define SGE_PF_KDOORBELL 0x0 44 #define QID_MASK 0xffff8000U 45 #define QID_SHIFT 15 46 #define QID(x) ((x) << QID_SHIFT) 47 #define DBPRIO 0x00004000U 48 #define PIDX_MASK 0x00003fffU 49 #define PIDX_SHIFT 0 50 #define PIDX(x) ((x) << PIDX_SHIFT) 51 52 #define SGE_PF_GTS 0x4 53 #define INGRESSQID_MASK 0xffff0000U 54 #define INGRESSQID_SHIFT 16 55 #define INGRESSQID(x) ((x) << INGRESSQID_SHIFT) 56 #define TIMERREG_MASK 0x0000e000U 57 #define TIMERREG_SHIFT 13 58 #define TIMERREG(x) ((x) << TIMERREG_SHIFT) 59 #define SEINTARM_MASK 0x00001000U 60 #define SEINTARM_SHIFT 12 61 #define SEINTARM(x) ((x) << SEINTARM_SHIFT) 62 #define CIDXINC_MASK 0x00000fffU 63 #define CIDXINC_SHIFT 0 64 #define CIDXINC(x) ((x) << CIDXINC_SHIFT) 65 66 #define T4_MAX_NUM_PD 65536 67 #define T4_MAX_MR_SIZE (~0ULL) 68 #define T4_PAGESIZE_MASK 0xffffffff000 /* 4KB-8TB */ 69 #define T4_STAG_UNSET 0xffffffff 70 #define T4_FW_MAJ 0 71 #define A_PCIE_MA_SYNC 0x30b4 72 73 struct t4_status_page { 74 __be32 rsvd1; /* flit 0 - hw owns */ 75 __be16 rsvd2; 76 __be16 qid; 77 __be16 cidx; 78 __be16 pidx; 79 u8 qp_err; /* flit 1 - sw owns */ 80 u8 db_off; 81 u8 pad; 82 u16 host_wq_pidx; 83 u16 host_cidx; 84 u16 host_pidx; 85 }; 86 87 #define T4_EQ_ENTRY_SIZE 64 88 89 #define T4_SQ_NUM_SLOTS 5 90 #define T4_SQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_SQ_NUM_SLOTS) 91 #define T4_MAX_SEND_SGE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \ 92 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge)) 93 #define T4_MAX_SEND_INLINE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \ 94 sizeof(struct fw_ri_immd))) 95 #define T4_MAX_WRITE_INLINE ((T4_SQ_NUM_BYTES - \ 96 sizeof(struct fw_ri_rdma_write_wr) - \ 97 sizeof(struct fw_ri_immd))) 98 #define T4_MAX_WRITE_SGE ((T4_SQ_NUM_BYTES - \ 99 sizeof(struct fw_ri_rdma_write_wr) - \ 100 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge)) 101 #define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \ 102 sizeof(struct fw_ri_immd)) & ~31UL) 103 #define T4_MAX_FR_IMMD_DEPTH (T4_MAX_FR_IMMD / sizeof(u64)) 104 #define T4_MAX_FR_DSGL 1024 105 #define T4_MAX_FR_DSGL_DEPTH (T4_MAX_FR_DSGL / sizeof(u64)) 106 #define T4_MAX_FR_FW_DSGL 4096 107 #define T4_MAX_FR_FW_DSGL_DEPTH (T4_MAX_FR_FW_DSGL / sizeof(u64)) 108 109 #define T4_RQ_NUM_SLOTS 2 110 #define T4_RQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_RQ_NUM_SLOTS) 111 #define T4_MAX_RECV_SGE 4 112 113 union t4_wr { 114 struct fw_ri_res_wr res; 115 struct fw_ri_wr ri; 116 struct fw_ri_rdma_write_wr write; 117 struct fw_ri_send_wr send; 118 struct fw_ri_rdma_read_wr read; 119 struct fw_ri_bind_mw_wr bind; 120 struct fw_ri_fr_nsmr_wr fr; 121 struct fw_ri_fr_nsmr_tpte_wr fr_tpte; 122 struct fw_ri_inv_lstag_wr inv; 123 struct t4_status_page status; 124 __be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_SQ_NUM_SLOTS]; 125 }; 126 127 union t4_recv_wr { 128 struct fw_ri_recv_wr recv; 129 struct t4_status_page status; 130 __be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_RQ_NUM_SLOTS]; 131 }; 132 133 static inline void init_wr_hdr(union t4_wr *wqe, u16 wrid, 134 enum fw_wr_opcodes opcode, u8 flags, u8 len16) 135 { 136 wqe->send.opcode = (u8)opcode; 137 wqe->send.flags = flags; 138 wqe->send.wrid = wrid; 139 wqe->send.r1[0] = 0; 140 wqe->send.r1[1] = 0; 141 wqe->send.r1[2] = 0; 142 wqe->send.len16 = len16; 143 } 144 145 /* CQE/AE status codes */ 146 #define T4_ERR_SUCCESS 0x0 147 #define T4_ERR_STAG 0x1 /* STAG invalid: either the */ 148 /* STAG is offlimt, being 0, */ 149 /* or STAG_key mismatch */ 150 #define T4_ERR_PDID 0x2 /* PDID mismatch */ 151 #define T4_ERR_QPID 0x3 /* QPID mismatch */ 152 #define T4_ERR_ACCESS 0x4 /* Invalid access right */ 153 #define T4_ERR_WRAP 0x5 /* Wrap error */ 154 #define T4_ERR_BOUND 0x6 /* base and bounds voilation */ 155 #define T4_ERR_INVALIDATE_SHARED_MR 0x7 /* attempt to invalidate a */ 156 /* shared memory region */ 157 #define T4_ERR_INVALIDATE_MR_WITH_MW_BOUND 0x8 /* attempt to invalidate a */ 158 /* shared memory region */ 159 #define T4_ERR_ECC 0x9 /* ECC error detected */ 160 #define T4_ERR_ECC_PSTAG 0xA /* ECC error detected when */ 161 /* reading PSTAG for a MW */ 162 /* Invalidate */ 163 #define T4_ERR_PBL_ADDR_BOUND 0xB /* pbl addr out of bounds: */ 164 /* software error */ 165 #define T4_ERR_SWFLUSH 0xC /* SW FLUSHED */ 166 #define T4_ERR_CRC 0x10 /* CRC error */ 167 #define T4_ERR_MARKER 0x11 /* Marker error */ 168 #define T4_ERR_PDU_LEN_ERR 0x12 /* invalid PDU length */ 169 #define T4_ERR_OUT_OF_RQE 0x13 /* out of RQE */ 170 #define T4_ERR_DDP_VERSION 0x14 /* wrong DDP version */ 171 #define T4_ERR_RDMA_VERSION 0x15 /* wrong RDMA version */ 172 #define T4_ERR_OPCODE 0x16 /* invalid rdma opcode */ 173 #define T4_ERR_DDP_QUEUE_NUM 0x17 /* invalid ddp queue number */ 174 #define T4_ERR_MSN 0x18 /* MSN error */ 175 #define T4_ERR_TBIT 0x19 /* tag bit not set correctly */ 176 #define T4_ERR_MO 0x1A /* MO not 0 for TERMINATE */ 177 /* or READ_REQ */ 178 #define T4_ERR_MSN_GAP 0x1B 179 #define T4_ERR_MSN_RANGE 0x1C 180 #define T4_ERR_IRD_OVERFLOW 0x1D 181 #define T4_ERR_RQE_ADDR_BOUND 0x1E /* RQE addr out of bounds: */ 182 /* software error */ 183 #define T4_ERR_INTERNAL_ERR 0x1F /* internal error (opcode */ 184 /* mismatch) */ 185 /* 186 * CQE defs 187 */ 188 struct t4_cqe { 189 __be32 header; 190 __be32 len; 191 union { 192 struct { 193 __be32 stag; 194 __be32 msn; 195 } rcqe; 196 struct { 197 u32 stag; 198 u16 nada2; 199 u16 cidx; 200 } scqe; 201 struct { 202 __be32 wrid_hi; 203 __be32 wrid_low; 204 } gen; 205 u64 drain_cookie; 206 } u; 207 __be64 reserved; 208 __be64 bits_type_ts; 209 }; 210 211 /* macros for flit 0 of the cqe */ 212 213 #define S_CQE_QPID 12 214 #define M_CQE_QPID 0xFFFFF 215 #define G_CQE_QPID(x) ((((x) >> S_CQE_QPID)) & M_CQE_QPID) 216 #define V_CQE_QPID(x) ((x)<<S_CQE_QPID) 217 218 #define S_CQE_SWCQE 11 219 #define M_CQE_SWCQE 0x1 220 #define G_CQE_SWCQE(x) ((((x) >> S_CQE_SWCQE)) & M_CQE_SWCQE) 221 #define V_CQE_SWCQE(x) ((x)<<S_CQE_SWCQE) 222 223 #define S_CQE_STATUS 5 224 #define M_CQE_STATUS 0x1F 225 #define G_CQE_STATUS(x) ((((x) >> S_CQE_STATUS)) & M_CQE_STATUS) 226 #define V_CQE_STATUS(x) ((x)<<S_CQE_STATUS) 227 228 #define S_CQE_TYPE 4 229 #define M_CQE_TYPE 0x1 230 #define G_CQE_TYPE(x) ((((x) >> S_CQE_TYPE)) & M_CQE_TYPE) 231 #define V_CQE_TYPE(x) ((x)<<S_CQE_TYPE) 232 233 #define S_CQE_OPCODE 0 234 #define M_CQE_OPCODE 0xF 235 #define G_CQE_OPCODE(x) ((((x) >> S_CQE_OPCODE)) & M_CQE_OPCODE) 236 #define V_CQE_OPCODE(x) ((x)<<S_CQE_OPCODE) 237 238 #define SW_CQE(x) (G_CQE_SWCQE(be32_to_cpu((x)->header))) 239 #define CQE_QPID(x) (G_CQE_QPID(be32_to_cpu((x)->header))) 240 #define CQE_TYPE(x) (G_CQE_TYPE(be32_to_cpu((x)->header))) 241 #define SQ_TYPE(x) (CQE_TYPE((x))) 242 #define RQ_TYPE(x) (!CQE_TYPE((x))) 243 #define CQE_STATUS(x) (G_CQE_STATUS(be32_to_cpu((x)->header))) 244 #define CQE_OPCODE(x) (G_CQE_OPCODE(be32_to_cpu((x)->header))) 245 246 #define CQE_SEND_OPCODE(x)(\ 247 (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND) || \ 248 (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE) || \ 249 (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_INV) || \ 250 (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE_INV)) 251 252 #define CQE_LEN(x) (be32_to_cpu((x)->len)) 253 254 /* used for RQ completion processing */ 255 #define CQE_WRID_STAG(x) (be32_to_cpu((x)->u.rcqe.stag)) 256 #define CQE_WRID_MSN(x) (be32_to_cpu((x)->u.rcqe.msn)) 257 258 /* used for SQ completion processing */ 259 #define CQE_WRID_SQ_IDX(x) ((x)->u.scqe.cidx) 260 #define CQE_WRID_FR_STAG(x) (be32_to_cpu((x)->u.scqe.stag)) 261 262 /* generic accessor macros */ 263 #define CQE_WRID_HI(x) ((x)->u.gen.wrid_hi) 264 #define CQE_WRID_LOW(x) ((x)->u.gen.wrid_low) 265 #define CQE_DRAIN_COOKIE(x) (x)->u.drain_cookie; 266 267 /* macros for flit 3 of the cqe */ 268 #define S_CQE_GENBIT 63 269 #define M_CQE_GENBIT 0x1 270 #define G_CQE_GENBIT(x) (((x) >> S_CQE_GENBIT) & M_CQE_GENBIT) 271 #define V_CQE_GENBIT(x) ((x)<<S_CQE_GENBIT) 272 273 #define S_CQE_OVFBIT 62 274 #define M_CQE_OVFBIT 0x1 275 #define G_CQE_OVFBIT(x) ((((x) >> S_CQE_OVFBIT)) & M_CQE_OVFBIT) 276 277 #define S_CQE_IQTYPE 60 278 #define M_CQE_IQTYPE 0x3 279 #define G_CQE_IQTYPE(x) ((((x) >> S_CQE_IQTYPE)) & M_CQE_IQTYPE) 280 281 #define M_CQE_TS 0x0fffffffffffffffULL 282 #define G_CQE_TS(x) ((x) & M_CQE_TS) 283 284 #define CQE_OVFBIT(x) ((unsigned)G_CQE_OVFBIT(be64_to_cpu((x)->bits_type_ts))) 285 #define CQE_GENBIT(x) ((unsigned)G_CQE_GENBIT(be64_to_cpu((x)->bits_type_ts))) 286 #define CQE_TS(x) (G_CQE_TS(be64_to_cpu((x)->bits_type_ts))) 287 288 struct t4_swsqe { 289 u64 wr_id; 290 struct t4_cqe cqe; 291 int read_len; 292 int opcode; 293 int complete; 294 int signaled; 295 u16 idx; 296 int flushed; 297 struct timespec host_ts; 298 u64 sge_ts; 299 }; 300 301 static inline pgprot_t t4_pgprot_wc(pgprot_t prot) 302 { 303 #if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64) 304 return pgprot_writecombine(prot); 305 #else 306 return pgprot_noncached(prot); 307 #endif 308 } 309 310 enum { 311 T4_SQ_ONCHIP = (1<<0), 312 }; 313 314 struct t4_sq { 315 union t4_wr *queue; 316 bus_addr_t dma_addr; 317 DEFINE_DMA_UNMAP_ADDR(mapping); 318 unsigned long phys_addr; 319 struct t4_swsqe *sw_sq; 320 struct t4_swsqe *oldest_read; 321 void __iomem *bar2_va; 322 u64 bar2_pa; 323 size_t memsize; 324 u32 bar2_qid; 325 u32 qid; 326 u16 in_use; 327 u16 size; 328 u16 cidx; 329 u16 pidx; 330 u16 wq_pidx; 331 u16 wq_pidx_inc; 332 u16 flags; 333 short flush_cidx; 334 }; 335 336 struct t4_swrqe { 337 u64 wr_id; 338 }; 339 340 struct t4_rq { 341 union t4_recv_wr *queue; 342 bus_addr_t dma_addr; 343 DEFINE_DMA_UNMAP_ADDR(mapping); 344 unsigned long phys_addr; 345 struct t4_swrqe *sw_rq; 346 void __iomem *bar2_va; 347 u64 bar2_pa; 348 size_t memsize; 349 u32 bar2_qid; 350 u32 qid; 351 u32 msn; 352 u32 rqt_hwaddr; 353 u16 rqt_size; 354 u16 in_use; 355 u16 size; 356 u16 cidx; 357 u16 pidx; 358 u16 wq_pidx; 359 u16 wq_pidx_inc; 360 }; 361 362 struct t4_wq { 363 struct t4_sq sq; 364 struct t4_rq rq; 365 struct c4iw_rdev *rdev; 366 int flushed; 367 }; 368 369 static inline int t4_rqes_posted(struct t4_wq *wq) 370 { 371 return wq->rq.in_use; 372 } 373 374 static inline int t4_rq_empty(struct t4_wq *wq) 375 { 376 return wq->rq.in_use == 0; 377 } 378 379 static inline int t4_rq_full(struct t4_wq *wq) 380 { 381 return wq->rq.in_use == (wq->rq.size - 1); 382 } 383 384 static inline u32 t4_rq_avail(struct t4_wq *wq) 385 { 386 return wq->rq.size - 1 - wq->rq.in_use; 387 } 388 389 static inline void t4_rq_produce(struct t4_wq *wq, u8 len16) 390 { 391 wq->rq.in_use++; 392 if (++wq->rq.pidx == wq->rq.size) 393 wq->rq.pidx = 0; 394 wq->rq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 395 if (wq->rq.wq_pidx >= wq->rq.size * T4_RQ_NUM_SLOTS) 396 wq->rq.wq_pidx %= wq->rq.size * T4_RQ_NUM_SLOTS; 397 } 398 399 static inline void t4_rq_consume(struct t4_wq *wq) 400 { 401 wq->rq.in_use--; 402 wq->rq.msn++; 403 if (++wq->rq.cidx == wq->rq.size) 404 wq->rq.cidx = 0; 405 } 406 407 static inline u16 t4_rq_host_wq_pidx(struct t4_wq *wq) 408 { 409 return wq->rq.queue[wq->rq.size].status.host_wq_pidx; 410 } 411 412 static inline u16 t4_rq_wq_size(struct t4_wq *wq) 413 { 414 return wq->rq.size * T4_RQ_NUM_SLOTS; 415 } 416 417 static inline int t4_sq_onchip(struct t4_sq *sq) 418 { 419 return sq->flags & T4_SQ_ONCHIP; 420 } 421 422 static inline int t4_sq_empty(struct t4_wq *wq) 423 { 424 return wq->sq.in_use == 0; 425 } 426 427 static inline int t4_sq_full(struct t4_wq *wq) 428 { 429 return wq->sq.in_use == (wq->sq.size - 1); 430 } 431 432 static inline u32 t4_sq_avail(struct t4_wq *wq) 433 { 434 return wq->sq.size - 1 - wq->sq.in_use; 435 } 436 437 static inline void t4_sq_produce(struct t4_wq *wq, u8 len16) 438 { 439 wq->sq.in_use++; 440 if (++wq->sq.pidx == wq->sq.size) 441 wq->sq.pidx = 0; 442 wq->sq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 443 if (wq->sq.wq_pidx >= wq->sq.size * T4_SQ_NUM_SLOTS) 444 wq->sq.wq_pidx %= wq->sq.size * T4_SQ_NUM_SLOTS; 445 } 446 447 static inline void t4_sq_consume(struct t4_wq *wq) 448 { 449 BUG_ON(wq->sq.in_use < 1); 450 if (wq->sq.cidx == wq->sq.flush_cidx) 451 wq->sq.flush_cidx = -1; 452 wq->sq.in_use--; 453 if (++wq->sq.cidx == wq->sq.size) 454 wq->sq.cidx = 0; 455 } 456 457 static inline u16 t4_sq_host_wq_pidx(struct t4_wq *wq) 458 { 459 return wq->sq.queue[wq->sq.size].status.host_wq_pidx; 460 } 461 462 static inline u16 t4_sq_wq_size(struct t4_wq *wq) 463 { 464 return wq->sq.size * T4_SQ_NUM_SLOTS; 465 } 466 467 /* This function copies 64 byte coalesced work request to memory 468 * mapped BAR2 space. For coalesced WRs, the SGE fetches data 469 * from the FIFO instead of from Host. 470 */ 471 static inline void pio_copy(u64 __iomem *dst, u64 *src) 472 { 473 int count = 8; 474 475 while (count) { 476 writeq(*src, dst); 477 src++; 478 dst++; 479 count--; 480 } 481 } 482 483 static inline void 484 t4_ring_sq_db(struct t4_wq *wq, u16 inc, union t4_wr *wqe, u8 wc) 485 { 486 487 /* Flush host queue memory writes. */ 488 wmb(); 489 if (wc && inc == 1 && wq->sq.bar2_qid == 0 && wqe) { 490 CTR2(KTR_IW_CXGBE, "%s: WC wq->sq.pidx = %d", 491 __func__, wq->sq.pidx); 492 pio_copy((u64 __iomem *) 493 ((u64)wq->sq.bar2_va + SGE_UDB_WCDOORBELL), 494 (u64 *)wqe); 495 } else { 496 CTR2(KTR_IW_CXGBE, "%s: DB wq->sq.pidx = %d", 497 __func__, wq->sq.pidx); 498 writel(V_PIDX_T5(inc) | V_QID(wq->sq.bar2_qid), 499 (void __iomem *)((u64)wq->sq.bar2_va + 500 SGE_UDB_KDOORBELL)); 501 } 502 503 /* Flush user doorbell area writes. */ 504 wmb(); 505 return; 506 } 507 508 static inline void 509 t4_ring_rq_db(struct t4_wq *wq, u16 inc, union t4_recv_wr *wqe, u8 wc) 510 { 511 512 /* Flush host queue memory writes. */ 513 wmb(); 514 if (wc && inc == 1 && wq->rq.bar2_qid == 0 && wqe) { 515 CTR2(KTR_IW_CXGBE, "%s: WC wq->rq.pidx = %d", 516 __func__, wq->rq.pidx); 517 pio_copy((u64 __iomem *)((u64)wq->rq.bar2_va + 518 SGE_UDB_WCDOORBELL), (u64 *)wqe); 519 } else { 520 CTR2(KTR_IW_CXGBE, "%s: DB wq->rq.pidx = %d", 521 __func__, wq->rq.pidx); 522 writel(V_PIDX_T5(inc) | V_QID(wq->rq.bar2_qid), 523 (void __iomem *)((u64)wq->rq.bar2_va + 524 SGE_UDB_KDOORBELL)); 525 } 526 527 /* Flush user doorbell area writes. */ 528 wmb(); 529 return; 530 } 531 532 static inline int t4_wq_in_error(struct t4_wq *wq) 533 { 534 return wq->rq.queue[wq->rq.size].status.qp_err; 535 } 536 537 static inline void t4_set_wq_in_error(struct t4_wq *wq) 538 { 539 wq->rq.queue[wq->rq.size].status.qp_err = 1; 540 } 541 542 enum t4_cq_flags { 543 CQ_ARMED = 1, 544 }; 545 546 struct t4_cq { 547 struct t4_cqe *queue; 548 bus_addr_t dma_addr; 549 DEFINE_DMA_UNMAP_ADDR(mapping); 550 struct t4_cqe *sw_queue; 551 void __iomem *bar2_va; 552 u64 bar2_pa; 553 u32 bar2_qid; 554 struct c4iw_rdev *rdev; 555 size_t memsize; 556 __be64 bits_type_ts; 557 u32 cqid; 558 u32 qid_mask; 559 int vector; 560 u16 size; /* including status page */ 561 u16 cidx; 562 u16 sw_pidx; 563 u16 sw_cidx; 564 u16 sw_in_use; 565 u16 cidx_inc; 566 u8 gen; 567 u8 error; 568 unsigned long flags; 569 }; 570 571 static inline void write_gts(struct t4_cq *cq, u32 val) 572 { 573 writel(val | V_INGRESSQID(cq->bar2_qid), 574 (void __iomem *)((u64)cq->bar2_va + SGE_UDB_GTS)); 575 } 576 577 static inline int t4_clear_cq_armed(struct t4_cq *cq) 578 { 579 return test_and_clear_bit(CQ_ARMED, &cq->flags); 580 } 581 582 static inline int t4_arm_cq(struct t4_cq *cq, int se) 583 { 584 u32 val; 585 586 set_bit(CQ_ARMED, &cq->flags); 587 while (cq->cidx_inc > CIDXINC_MASK) { 588 val = SEINTARM(0) | CIDXINC(CIDXINC_MASK) | TIMERREG(7); 589 writel(val | V_INGRESSQID(cq->bar2_qid), 590 (void __iomem *)((u64)cq->bar2_va + SGE_UDB_GTS)); 591 cq->cidx_inc -= CIDXINC_MASK; 592 } 593 val = SEINTARM(se) | CIDXINC(cq->cidx_inc) | TIMERREG(6); 594 writel(val | V_INGRESSQID(cq->bar2_qid), 595 (void __iomem *)((u64)cq->bar2_va + SGE_UDB_GTS)); 596 cq->cidx_inc = 0; 597 return 0; 598 } 599 600 static inline void t4_swcq_produce(struct t4_cq *cq) 601 { 602 cq->sw_in_use++; 603 if (cq->sw_in_use == cq->size) { 604 CTR2(KTR_IW_CXGBE, "%s cxgb4 sw cq overflow cqid %u", 605 __func__, cq->cqid); 606 cq->error = 1; 607 BUG_ON(1); 608 } 609 if (++cq->sw_pidx == cq->size) 610 cq->sw_pidx = 0; 611 } 612 613 static inline void t4_swcq_consume(struct t4_cq *cq) 614 { 615 BUG_ON(cq->sw_in_use < 1); 616 cq->sw_in_use--; 617 if (++cq->sw_cidx == cq->size) 618 cq->sw_cidx = 0; 619 } 620 621 static inline void t4_hwcq_consume(struct t4_cq *cq) 622 { 623 cq->bits_type_ts = cq->queue[cq->cidx].bits_type_ts; 624 if (++cq->cidx_inc == (cq->size >> 4) || cq->cidx_inc == M_CIDXINC) { 625 u32 val; 626 627 val = SEINTARM(0) | CIDXINC(cq->cidx_inc) | TIMERREG(7); 628 write_gts(cq, val); 629 cq->cidx_inc = 0; 630 } 631 if (++cq->cidx == cq->size) { 632 cq->cidx = 0; 633 cq->gen ^= 1; 634 } 635 } 636 637 static inline int t4_valid_cqe(struct t4_cq *cq, struct t4_cqe *cqe) 638 { 639 return (CQE_GENBIT(cqe) == cq->gen); 640 } 641 642 static inline int t4_cq_notempty(struct t4_cq *cq) 643 { 644 return cq->sw_in_use || t4_valid_cqe(cq, &cq->queue[cq->cidx]); 645 } 646 647 static inline int t4_next_hw_cqe(struct t4_cq *cq, struct t4_cqe **cqe) 648 { 649 int ret; 650 u16 prev_cidx; 651 652 if (cq->cidx == 0) 653 prev_cidx = cq->size - 1; 654 else 655 prev_cidx = cq->cidx - 1; 656 657 if (cq->queue[prev_cidx].bits_type_ts != cq->bits_type_ts) { 658 ret = -EOVERFLOW; 659 cq->error = 1; 660 printk(KERN_ERR MOD "cq overflow cqid %u\n", cq->cqid); 661 BUG_ON(1); 662 } else if (t4_valid_cqe(cq, &cq->queue[cq->cidx])) { 663 664 /* Ensure CQE is flushed to memory */ 665 rmb(); 666 *cqe = &cq->queue[cq->cidx]; 667 ret = 0; 668 } else 669 ret = -ENODATA; 670 return ret; 671 } 672 673 static inline struct t4_cqe *t4_next_sw_cqe(struct t4_cq *cq) 674 { 675 if (cq->sw_in_use == cq->size) { 676 CTR2(KTR_IW_CXGBE, "%s cxgb4 sw cq overflow cqid %u", 677 __func__, cq->cqid); 678 cq->error = 1; 679 BUG_ON(1); 680 return NULL; 681 } 682 if (cq->sw_in_use) 683 return &cq->sw_queue[cq->sw_cidx]; 684 return NULL; 685 } 686 687 static inline int t4_next_cqe(struct t4_cq *cq, struct t4_cqe **cqe) 688 { 689 int ret = 0; 690 691 if (cq->error) 692 ret = -ENODATA; 693 else if (cq->sw_in_use) 694 *cqe = &cq->sw_queue[cq->sw_cidx]; 695 else 696 ret = t4_next_hw_cqe(cq, cqe); 697 return ret; 698 } 699 700 static inline int t4_cq_in_error(struct t4_cq *cq) 701 { 702 return ((struct t4_status_page *)&cq->queue[cq->size])->qp_err; 703 } 704 705 static inline void t4_set_cq_in_error(struct t4_cq *cq) 706 { 707 ((struct t4_status_page *)&cq->queue[cq->size])->qp_err = 1; 708 } 709 struct t4_dev_status_page { 710 u8 db_off; 711 u8 wc_supported; 712 u16 pad2; 713 u32 pad3; 714 u64 qp_start; 715 u64 qp_size; 716 u64 cq_start; 717 u64 cq_size; 718 }; 719 #endif 720