1 /*- 2 * Copyright (c) 2014 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 34 #ifdef DEV_NETMAP 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/eventhandler.h> 38 #include <sys/lock.h> 39 #include <sys/mbuf.h> 40 #include <sys/module.h> 41 #include <sys/selinfo.h> 42 #include <sys/socket.h> 43 #include <sys/sockio.h> 44 #include <machine/bus.h> 45 #include <net/ethernet.h> 46 #include <net/if.h> 47 #include <net/if_media.h> 48 #include <net/if_var.h> 49 #include <net/if_clone.h> 50 #include <net/if_types.h> 51 #include <net/netmap.h> 52 #include <dev/netmap/netmap_kern.h> 53 54 #include "common/common.h" 55 #include "common/t4_regs.h" 56 #include "common/t4_regs_values.h" 57 58 extern int fl_pad; /* XXXNM */ 59 60 SYSCTL_NODE(_hw, OID_AUTO, cxgbe, CTLFLAG_RD, 0, "cxgbe netmap parameters"); 61 62 /* 63 * 0 = normal netmap rx 64 * 1 = black hole 65 * 2 = supermassive black hole (buffer packing enabled) 66 */ 67 int black_hole = 0; 68 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_black_hole, CTLFLAG_RDTUN, &black_hole, 0, 69 "Sink incoming packets."); 70 71 int rx_ndesc = 256; 72 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_rx_ndesc, CTLFLAG_RWTUN, 73 &rx_ndesc, 0, "# of rx descriptors after which the hw cidx is updated."); 74 75 int holdoff_tmr_idx = 2; 76 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_holdoff_tmr_idx, CTLFLAG_RWTUN, 77 &holdoff_tmr_idx, 0, "Holdoff timer index for netmap rx queues."); 78 79 /* 80 * Congestion drops. 81 * -1: no congestion feedback (not recommended). 82 * 0: backpressure the channel instead of dropping packets right away. 83 * 1: no backpressure, drop packets for the congested queue immediately. 84 */ 85 static int nm_cong_drop = 1; 86 TUNABLE_INT("hw.cxgbe.nm_cong_drop", &nm_cong_drop); 87 88 static int 89 alloc_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int cong) 90 { 91 int rc, cntxt_id, i; 92 __be32 v; 93 struct adapter *sc = vi->pi->adapter; 94 struct sge_params *sp = &sc->params.sge; 95 struct netmap_adapter *na = NA(vi->ifp); 96 struct fw_iq_cmd c; 97 98 MPASS(na != NULL); 99 MPASS(nm_rxq->iq_desc != NULL); 100 MPASS(nm_rxq->fl_desc != NULL); 101 102 bzero(nm_rxq->iq_desc, vi->qsize_rxq * IQ_ESIZE); 103 bzero(nm_rxq->fl_desc, na->num_rx_desc * EQ_ESIZE + sp->spg_len); 104 105 bzero(&c, sizeof(c)); 106 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 107 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 108 V_FW_IQ_CMD_VFN(0)); 109 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 110 FW_LEN16(c)); 111 MPASS(!forwarding_intr_to_fwq(sc)); 112 KASSERT(nm_rxq->intr_idx < sc->intr_count, 113 ("%s: invalid direct intr_idx %d", __func__, nm_rxq->intr_idx)); 114 v = V_FW_IQ_CMD_IQANDSTINDEX(nm_rxq->intr_idx); 115 c.type_to_iqandstindex = htobe32(v | 116 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 117 V_FW_IQ_CMD_VIID(vi->viid) | 118 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 119 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(vi->pi->tx_chan) | 120 F_FW_IQ_CMD_IQGTSMODE | 121 V_FW_IQ_CMD_IQINTCNTTHRESH(0) | 122 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4)); 123 c.iqsize = htobe16(vi->qsize_rxq); 124 c.iqaddr = htobe64(nm_rxq->iq_ba); 125 if (cong >= 0) { 126 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN | 127 V_FW_IQ_CMD_FL0CNGCHMAP(cong) | F_FW_IQ_CMD_FL0CONGCIF | 128 F_FW_IQ_CMD_FL0CONGEN); 129 } 130 c.iqns_to_fl0congen |= 131 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 132 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 133 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 134 (black_hole == 2 ? F_FW_IQ_CMD_FL0PACKEN : 0)); 135 c.fl0dcaen_to_fl0cidxfthresh = 136 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ? 137 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B) | 138 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ? 139 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B)); 140 c.fl0size = htobe16(na->num_rx_desc / 8 + sp->spg_len / EQ_ESIZE); 141 c.fl0addr = htobe64(nm_rxq->fl_ba); 142 143 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 144 if (rc != 0) { 145 device_printf(sc->dev, 146 "failed to create netmap ingress queue: %d\n", rc); 147 return (rc); 148 } 149 150 nm_rxq->iq_cidx = 0; 151 MPASS(nm_rxq->iq_sidx == vi->qsize_rxq - sp->spg_len / IQ_ESIZE); 152 nm_rxq->iq_gen = F_RSPD_GEN; 153 nm_rxq->iq_cntxt_id = be16toh(c.iqid); 154 nm_rxq->iq_abs_id = be16toh(c.physiqid); 155 cntxt_id = nm_rxq->iq_cntxt_id - sc->sge.iq_start; 156 if (cntxt_id >= sc->sge.niq) { 157 panic ("%s: nm_rxq->iq_cntxt_id (%d) more than the max (%d)", 158 __func__, cntxt_id, sc->sge.niq - 1); 159 } 160 sc->sge.iqmap[cntxt_id] = (void *)nm_rxq; 161 162 nm_rxq->fl_cntxt_id = be16toh(c.fl0id); 163 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0; 164 MPASS(nm_rxq->fl_sidx == na->num_rx_desc); 165 cntxt_id = nm_rxq->fl_cntxt_id - sc->sge.eq_start; 166 if (cntxt_id >= sc->sge.neq) { 167 panic("%s: nm_rxq->fl_cntxt_id (%d) more than the max (%d)", 168 __func__, cntxt_id, sc->sge.neq - 1); 169 } 170 sc->sge.eqmap[cntxt_id] = (void *)nm_rxq; 171 172 nm_rxq->fl_db_val = V_QID(nm_rxq->fl_cntxt_id) | 173 sc->chip_params->sge_fl_db; 174 175 if (chip_id(sc) >= CHELSIO_T5 && cong >= 0) { 176 uint32_t param, val; 177 178 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 179 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 180 V_FW_PARAMS_PARAM_YZ(nm_rxq->iq_cntxt_id); 181 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 182 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 183 V_FW_PARAMS_PARAM_YZ(nm_rxq->iq_cntxt_id); 184 if (cong == 0) 185 val = 1 << 19; 186 else { 187 val = 2 << 19; 188 for (i = 0; i < 4; i++) { 189 if (cong & (1 << i)) 190 val |= 1 << (i << 2); 191 } 192 } 193 194 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 195 if (rc != 0) { 196 /* report error but carry on */ 197 device_printf(sc->dev, 198 "failed to set congestion manager context for " 199 "ingress queue %d: %d\n", nm_rxq->iq_cntxt_id, rc); 200 } 201 } 202 203 t4_write_reg(sc, sc->sge_gts_reg, 204 V_INGRESSQID(nm_rxq->iq_cntxt_id) | 205 V_SEINTARM(V_QINTR_TIMER_IDX(holdoff_tmr_idx))); 206 207 return (rc); 208 } 209 210 static int 211 free_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq) 212 { 213 struct adapter *sc = vi->pi->adapter; 214 int rc; 215 216 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, FW_IQ_TYPE_FL_INT_CAP, 217 nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, 0xffff); 218 if (rc != 0) 219 device_printf(sc->dev, "%s: failed for iq %d, fl %d: %d\n", 220 __func__, nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, rc); 221 nm_rxq->iq_cntxt_id = INVALID_NM_RXQ_CNTXT_ID; 222 return (rc); 223 } 224 225 static int 226 alloc_nm_txq_hwq(struct vi_info *vi, struct sge_nm_txq *nm_txq) 227 { 228 int rc, cntxt_id; 229 size_t len; 230 struct adapter *sc = vi->pi->adapter; 231 struct netmap_adapter *na = NA(vi->ifp); 232 struct fw_eq_eth_cmd c; 233 234 MPASS(na != NULL); 235 MPASS(nm_txq->desc != NULL); 236 237 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len; 238 bzero(nm_txq->desc, len); 239 240 bzero(&c, sizeof(c)); 241 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 242 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 243 V_FW_EQ_ETH_CMD_VFN(0)); 244 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | 245 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 246 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE | 247 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid)); 248 c.fetchszm_to_iqid = 249 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 250 V_FW_EQ_ETH_CMD_PCIECHN(vi->pi->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 251 V_FW_EQ_ETH_CMD_IQID(sc->sge.nm_rxq[nm_txq->iqidx].iq_cntxt_id)); 252 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 253 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 254 V_FW_EQ_ETH_CMD_EQSIZE(len / EQ_ESIZE)); 255 c.eqaddr = htobe64(nm_txq->ba); 256 257 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 258 if (rc != 0) { 259 device_printf(vi->dev, 260 "failed to create netmap egress queue: %d\n", rc); 261 return (rc); 262 } 263 264 nm_txq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 265 cntxt_id = nm_txq->cntxt_id - sc->sge.eq_start; 266 if (cntxt_id >= sc->sge.neq) 267 panic("%s: nm_txq->cntxt_id (%d) more than the max (%d)", __func__, 268 cntxt_id, sc->sge.neq - 1); 269 sc->sge.eqmap[cntxt_id] = (void *)nm_txq; 270 271 nm_txq->pidx = nm_txq->cidx = 0; 272 MPASS(nm_txq->sidx == na->num_tx_desc); 273 nm_txq->equiqidx = nm_txq->equeqidx = nm_txq->dbidx = 0; 274 275 nm_txq->doorbells = sc->doorbells; 276 if (isset(&nm_txq->doorbells, DOORBELL_UDB) || 277 isset(&nm_txq->doorbells, DOORBELL_UDBWC) || 278 isset(&nm_txq->doorbells, DOORBELL_WCWR)) { 279 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 280 uint32_t mask = (1 << s_qpp) - 1; 281 volatile uint8_t *udb; 282 283 udb = sc->udbs_base + UDBS_DB_OFFSET; 284 udb += (nm_txq->cntxt_id >> s_qpp) << PAGE_SHIFT; 285 nm_txq->udb_qid = nm_txq->cntxt_id & mask; 286 if (nm_txq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE) 287 clrbit(&nm_txq->doorbells, DOORBELL_WCWR); 288 else { 289 udb += nm_txq->udb_qid << UDBS_SEG_SHIFT; 290 nm_txq->udb_qid = 0; 291 } 292 nm_txq->udb = (volatile void *)udb; 293 } 294 295 return (rc); 296 } 297 298 static int 299 free_nm_txq_hwq(struct vi_info *vi, struct sge_nm_txq *nm_txq) 300 { 301 struct adapter *sc = vi->pi->adapter; 302 int rc; 303 304 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, nm_txq->cntxt_id); 305 if (rc != 0) 306 device_printf(sc->dev, "%s: failed for eq %d: %d\n", __func__, 307 nm_txq->cntxt_id, rc); 308 nm_txq->cntxt_id = INVALID_NM_TXQ_CNTXT_ID; 309 return (rc); 310 } 311 312 static int 313 cxgbe_netmap_on(struct adapter *sc, struct vi_info *vi, struct ifnet *ifp, 314 struct netmap_adapter *na) 315 { 316 struct netmap_slot *slot; 317 struct netmap_kring *kring; 318 struct sge_nm_rxq *nm_rxq; 319 struct sge_nm_txq *nm_txq; 320 int rc, i, j, hwidx; 321 struct hw_buf_info *hwb; 322 323 ASSERT_SYNCHRONIZED_OP(sc); 324 325 if ((vi->flags & VI_INIT_DONE) == 0 || 326 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 327 return (EAGAIN); 328 329 hwb = &sc->sge.hw_buf_info[0]; 330 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) { 331 if (hwb->size == NETMAP_BUF_SIZE(na)) 332 break; 333 } 334 if (i >= SGE_FLBUF_SIZES) { 335 if_printf(ifp, "no hwidx for netmap buffer size %d.\n", 336 NETMAP_BUF_SIZE(na)); 337 return (ENXIO); 338 } 339 hwidx = i; 340 341 /* Must set caps before calling netmap_reset */ 342 nm_set_native_flags(na); 343 344 for_each_nm_rxq(vi, i, nm_rxq) { 345 struct irq *irq = &sc->irq[vi->first_intr + i]; 346 347 kring = na->rx_rings[nm_rxq->nid]; 348 if (!nm_kring_pending_on(kring) || 349 nm_rxq->iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID) 350 continue; 351 352 alloc_nm_rxq_hwq(vi, nm_rxq, tnl_cong(vi->pi, nm_cong_drop)); 353 nm_rxq->fl_hwidx = hwidx; 354 slot = netmap_reset(na, NR_RX, i, 0); 355 MPASS(slot != NULL); /* XXXNM: error check, not assert */ 356 357 /* We deal with 8 bufs at a time */ 358 MPASS((na->num_rx_desc & 7) == 0); 359 MPASS(na->num_rx_desc == nm_rxq->fl_sidx); 360 for (j = 0; j < nm_rxq->fl_sidx; j++) { 361 uint64_t ba; 362 363 PNMB(na, &slot[j], &ba); 364 MPASS(ba != 0); 365 nm_rxq->fl_desc[j] = htobe64(ba | hwidx); 366 } 367 j = nm_rxq->fl_pidx = nm_rxq->fl_sidx - 8; 368 MPASS((j & 7) == 0); 369 j /= 8; /* driver pidx to hardware pidx */ 370 wmb(); 371 t4_write_reg(sc, sc->sge_kdoorbell_reg, 372 nm_rxq->fl_db_val | V_PIDX(j)); 373 374 atomic_cmpset_int(&irq->nm_state, NM_OFF, NM_ON); 375 } 376 377 for_each_nm_txq(vi, i, nm_txq) { 378 kring = na->tx_rings[nm_txq->nid]; 379 if (!nm_kring_pending_on(kring) || 380 nm_txq->cntxt_id != INVALID_NM_TXQ_CNTXT_ID) 381 continue; 382 383 alloc_nm_txq_hwq(vi, nm_txq); 384 slot = netmap_reset(na, NR_TX, i, 0); 385 MPASS(slot != NULL); /* XXXNM: error check, not assert */ 386 } 387 388 if (vi->nm_rss == NULL) { 389 vi->nm_rss = malloc(vi->rss_size * sizeof(uint16_t), M_CXGBE, 390 M_ZERO | M_WAITOK); 391 } 392 for (i = 0; i < vi->rss_size;) { 393 for_each_nm_rxq(vi, j, nm_rxq) { 394 vi->nm_rss[i++] = nm_rxq->iq_abs_id; 395 if (i == vi->rss_size) 396 break; 397 } 398 } 399 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, 400 vi->nm_rss, vi->rss_size); 401 if (rc != 0) 402 if_printf(ifp, "netmap rss_config failed: %d\n", rc); 403 404 return (rc); 405 } 406 407 static int 408 cxgbe_netmap_off(struct adapter *sc, struct vi_info *vi, struct ifnet *ifp, 409 struct netmap_adapter *na) 410 { 411 struct netmap_kring *kring; 412 int rc, i; 413 struct sge_nm_txq *nm_txq; 414 struct sge_nm_rxq *nm_rxq; 415 416 ASSERT_SYNCHRONIZED_OP(sc); 417 418 if ((vi->flags & VI_INIT_DONE) == 0) 419 return (0); 420 421 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, 422 vi->rss, vi->rss_size); 423 if (rc != 0) 424 if_printf(ifp, "failed to restore RSS config: %d\n", rc); 425 nm_clear_native_flags(na); 426 427 for_each_nm_txq(vi, i, nm_txq) { 428 struct sge_qstat *spg = (void *)&nm_txq->desc[nm_txq->sidx]; 429 430 kring = na->tx_rings[nm_txq->nid]; 431 if (!nm_kring_pending_off(kring) || 432 nm_txq->cntxt_id == INVALID_NM_TXQ_CNTXT_ID) 433 continue; 434 435 /* Wait for hw pidx to catch up ... */ 436 while (be16toh(nm_txq->pidx) != spg->pidx) 437 pause("nmpidx", 1); 438 439 /* ... and then for the cidx. */ 440 while (spg->pidx != spg->cidx) 441 pause("nmcidx", 1); 442 443 free_nm_txq_hwq(vi, nm_txq); 444 } 445 for_each_nm_rxq(vi, i, nm_rxq) { 446 struct irq *irq = &sc->irq[vi->first_intr + i]; 447 448 kring = na->rx_rings[nm_rxq->nid]; 449 if (!nm_kring_pending_off(kring) || 450 nm_rxq->iq_cntxt_id == INVALID_NM_RXQ_CNTXT_ID) 451 continue; 452 453 while (!atomic_cmpset_int(&irq->nm_state, NM_ON, NM_OFF)) 454 pause("nmst", 1); 455 456 free_nm_rxq_hwq(vi, nm_rxq); 457 } 458 459 return (rc); 460 } 461 462 static int 463 cxgbe_netmap_reg(struct netmap_adapter *na, int on) 464 { 465 struct ifnet *ifp = na->ifp; 466 struct vi_info *vi = ifp->if_softc; 467 struct adapter *sc = vi->pi->adapter; 468 int rc; 469 470 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4nmreg"); 471 if (rc != 0) 472 return (rc); 473 if (on) 474 rc = cxgbe_netmap_on(sc, vi, ifp, na); 475 else 476 rc = cxgbe_netmap_off(sc, vi, ifp, na); 477 end_synchronized_op(sc, 0); 478 479 return (rc); 480 } 481 482 /* How many packets can a single type1 WR carry in n descriptors */ 483 static inline int 484 ndesc_to_npkt(const int n) 485 { 486 487 MPASS(n > 0 && n <= SGE_MAX_WR_NDESC); 488 489 return (n * 2 - 1); 490 } 491 #define MAX_NPKT_IN_TYPE1_WR (ndesc_to_npkt(SGE_MAX_WR_NDESC)) 492 493 /* Space (in descriptors) needed for a type1 WR that carries n packets */ 494 static inline int 495 npkt_to_ndesc(const int n) 496 { 497 498 MPASS(n > 0 && n <= MAX_NPKT_IN_TYPE1_WR); 499 500 return ((n + 2) / 2); 501 } 502 503 /* Space (in 16B units) needed for a type1 WR that carries n packets */ 504 static inline int 505 npkt_to_len16(const int n) 506 { 507 508 MPASS(n > 0 && n <= MAX_NPKT_IN_TYPE1_WR); 509 510 return (n * 2 + 1); 511 } 512 513 #define NMIDXDIFF(q, idx) IDXDIFF((q)->pidx, (q)->idx, (q)->sidx) 514 515 static void 516 ring_nm_txq_db(struct adapter *sc, struct sge_nm_txq *nm_txq) 517 { 518 int n; 519 u_int db = nm_txq->doorbells; 520 521 MPASS(nm_txq->pidx != nm_txq->dbidx); 522 523 n = NMIDXDIFF(nm_txq, dbidx); 524 if (n > 1) 525 clrbit(&db, DOORBELL_WCWR); 526 wmb(); 527 528 switch (ffs(db) - 1) { 529 case DOORBELL_UDB: 530 *nm_txq->udb = htole32(V_QID(nm_txq->udb_qid) | V_PIDX(n)); 531 break; 532 533 case DOORBELL_WCWR: { 534 volatile uint64_t *dst, *src; 535 536 /* 537 * Queues whose 128B doorbell segment fits in the page do not 538 * use relative qid (udb_qid is always 0). Only queues with 539 * doorbell segments can do WCWR. 540 */ 541 KASSERT(nm_txq->udb_qid == 0 && n == 1, 542 ("%s: inappropriate doorbell (0x%x, %d, %d) for nm_txq %p", 543 __func__, nm_txq->doorbells, n, nm_txq->pidx, nm_txq)); 544 545 dst = (volatile void *)((uintptr_t)nm_txq->udb + 546 UDBS_WR_OFFSET - UDBS_DB_OFFSET); 547 src = (void *)&nm_txq->desc[nm_txq->dbidx]; 548 while (src != (void *)&nm_txq->desc[nm_txq->dbidx + 1]) 549 *dst++ = *src++; 550 wmb(); 551 break; 552 } 553 554 case DOORBELL_UDBWC: 555 *nm_txq->udb = htole32(V_QID(nm_txq->udb_qid) | V_PIDX(n)); 556 wmb(); 557 break; 558 559 case DOORBELL_KDB: 560 t4_write_reg(sc, sc->sge_kdoorbell_reg, 561 V_QID(nm_txq->cntxt_id) | V_PIDX(n)); 562 break; 563 } 564 nm_txq->dbidx = nm_txq->pidx; 565 } 566 567 int lazy_tx_credit_flush = 1; 568 569 /* 570 * Write work requests to send 'npkt' frames and ring the doorbell to send them 571 * on their way. No need to check for wraparound. 572 */ 573 static void 574 cxgbe_nm_tx(struct adapter *sc, struct sge_nm_txq *nm_txq, 575 struct netmap_kring *kring, int npkt, int npkt_remaining, int txcsum) 576 { 577 struct netmap_ring *ring = kring->ring; 578 struct netmap_slot *slot; 579 const u_int lim = kring->nkr_num_slots - 1; 580 struct fw_eth_tx_pkts_wr *wr = (void *)&nm_txq->desc[nm_txq->pidx]; 581 uint16_t len; 582 uint64_t ba; 583 struct cpl_tx_pkt_core *cpl; 584 struct ulptx_sgl *usgl; 585 int i, n; 586 587 while (npkt) { 588 n = min(npkt, MAX_NPKT_IN_TYPE1_WR); 589 len = 0; 590 591 wr = (void *)&nm_txq->desc[nm_txq->pidx]; 592 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 593 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(npkt_to_len16(n))); 594 wr->npkt = n; 595 wr->r3 = 0; 596 wr->type = 1; 597 cpl = (void *)(wr + 1); 598 599 for (i = 0; i < n; i++) { 600 slot = &ring->slot[kring->nr_hwcur]; 601 PNMB(kring->na, slot, &ba); 602 MPASS(ba != 0); 603 604 cpl->ctrl0 = nm_txq->cpl_ctrl0; 605 cpl->pack = 0; 606 cpl->len = htobe16(slot->len); 607 /* 608 * netmap(4) says "netmap does not use features such as 609 * checksum offloading, TCP segmentation offloading, 610 * encryption, VLAN encapsulation/decapsulation, etc." 611 * 612 * So the ncxl interfaces have tx hardware checksumming 613 * disabled by default. But you can override netmap by 614 * enabling IFCAP_TXCSUM on the interface manully. 615 */ 616 cpl->ctrl1 = txcsum ? 0 : 617 htobe64(F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS); 618 619 usgl = (void *)(cpl + 1); 620 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 621 V_ULPTX_NSGE(1)); 622 usgl->len0 = htobe32(slot->len); 623 usgl->addr0 = htobe64(ba); 624 625 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 626 cpl = (void *)(usgl + 1); 627 MPASS(slot->len + len <= UINT16_MAX); 628 len += slot->len; 629 kring->nr_hwcur = nm_next(kring->nr_hwcur, lim); 630 } 631 wr->plen = htobe16(len); 632 633 npkt -= n; 634 nm_txq->pidx += npkt_to_ndesc(n); 635 MPASS(nm_txq->pidx <= nm_txq->sidx); 636 if (__predict_false(nm_txq->pidx == nm_txq->sidx)) { 637 /* 638 * This routine doesn't know how to write WRs that wrap 639 * around. Make sure it wasn't asked to. 640 */ 641 MPASS(npkt == 0); 642 nm_txq->pidx = 0; 643 } 644 645 if (npkt == 0 && npkt_remaining == 0) { 646 /* All done. */ 647 if (lazy_tx_credit_flush == 0) { 648 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ | 649 F_FW_WR_EQUIQ); 650 nm_txq->equeqidx = nm_txq->pidx; 651 nm_txq->equiqidx = nm_txq->pidx; 652 } 653 ring_nm_txq_db(sc, nm_txq); 654 return; 655 } 656 657 if (NMIDXDIFF(nm_txq, equiqidx) >= nm_txq->sidx / 2) { 658 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ | 659 F_FW_WR_EQUIQ); 660 nm_txq->equeqidx = nm_txq->pidx; 661 nm_txq->equiqidx = nm_txq->pidx; 662 } else if (NMIDXDIFF(nm_txq, equeqidx) >= 64) { 663 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 664 nm_txq->equeqidx = nm_txq->pidx; 665 } 666 if (NMIDXDIFF(nm_txq, dbidx) >= 2 * SGE_MAX_WR_NDESC) 667 ring_nm_txq_db(sc, nm_txq); 668 } 669 670 /* Will get called again. */ 671 MPASS(npkt_remaining); 672 } 673 674 /* How many contiguous free descriptors starting at pidx */ 675 static inline int 676 contiguous_ndesc_available(struct sge_nm_txq *nm_txq) 677 { 678 679 if (nm_txq->cidx > nm_txq->pidx) 680 return (nm_txq->cidx - nm_txq->pidx - 1); 681 else if (nm_txq->cidx > 0) 682 return (nm_txq->sidx - nm_txq->pidx); 683 else 684 return (nm_txq->sidx - nm_txq->pidx - 1); 685 } 686 687 static int 688 reclaim_nm_tx_desc(struct sge_nm_txq *nm_txq) 689 { 690 struct sge_qstat *spg = (void *)&nm_txq->desc[nm_txq->sidx]; 691 uint16_t hw_cidx = spg->cidx; /* snapshot */ 692 struct fw_eth_tx_pkts_wr *wr; 693 int n = 0; 694 695 hw_cidx = be16toh(hw_cidx); 696 697 while (nm_txq->cidx != hw_cidx) { 698 wr = (void *)&nm_txq->desc[nm_txq->cidx]; 699 700 MPASS(wr->op_pkd == htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR))); 701 MPASS(wr->type == 1); 702 MPASS(wr->npkt > 0 && wr->npkt <= MAX_NPKT_IN_TYPE1_WR); 703 704 n += wr->npkt; 705 nm_txq->cidx += npkt_to_ndesc(wr->npkt); 706 707 /* 708 * We never sent a WR that wrapped around so the credits coming 709 * back, WR by WR, should never cause the cidx to wrap around 710 * either. 711 */ 712 MPASS(nm_txq->cidx <= nm_txq->sidx); 713 if (__predict_false(nm_txq->cidx == nm_txq->sidx)) 714 nm_txq->cidx = 0; 715 } 716 717 return (n); 718 } 719 720 static int 721 cxgbe_netmap_txsync(struct netmap_kring *kring, int flags) 722 { 723 struct netmap_adapter *na = kring->na; 724 struct ifnet *ifp = na->ifp; 725 struct vi_info *vi = ifp->if_softc; 726 struct adapter *sc = vi->pi->adapter; 727 struct sge_nm_txq *nm_txq = &sc->sge.nm_txq[vi->first_nm_txq + kring->ring_id]; 728 const u_int head = kring->rhead; 729 u_int reclaimed = 0; 730 int n, d, npkt_remaining, ndesc_remaining, txcsum; 731 732 /* 733 * Tx was at kring->nr_hwcur last time around and now we need to advance 734 * to kring->rhead. Note that the driver's pidx moves independent of 735 * netmap's kring->nr_hwcur (pidx counts descriptors and the relation 736 * between descriptors and frames isn't 1:1). 737 */ 738 739 npkt_remaining = head >= kring->nr_hwcur ? head - kring->nr_hwcur : 740 kring->nkr_num_slots - kring->nr_hwcur + head; 741 txcsum = ifp->if_capenable & (IFCAP_TXCSUM | IFCAP_TXCSUM_IPV6); 742 while (npkt_remaining) { 743 reclaimed += reclaim_nm_tx_desc(nm_txq); 744 ndesc_remaining = contiguous_ndesc_available(nm_txq); 745 /* Can't run out of descriptors with packets still remaining */ 746 MPASS(ndesc_remaining > 0); 747 748 /* # of desc needed to tx all remaining packets */ 749 d = (npkt_remaining / MAX_NPKT_IN_TYPE1_WR) * SGE_MAX_WR_NDESC; 750 if (npkt_remaining % MAX_NPKT_IN_TYPE1_WR) 751 d += npkt_to_ndesc(npkt_remaining % MAX_NPKT_IN_TYPE1_WR); 752 753 if (d <= ndesc_remaining) 754 n = npkt_remaining; 755 else { 756 /* Can't send all, calculate how many can be sent */ 757 n = (ndesc_remaining / SGE_MAX_WR_NDESC) * 758 MAX_NPKT_IN_TYPE1_WR; 759 if (ndesc_remaining % SGE_MAX_WR_NDESC) 760 n += ndesc_to_npkt(ndesc_remaining % SGE_MAX_WR_NDESC); 761 } 762 763 /* Send n packets and update nm_txq->pidx and kring->nr_hwcur */ 764 npkt_remaining -= n; 765 cxgbe_nm_tx(sc, nm_txq, kring, n, npkt_remaining, txcsum); 766 } 767 MPASS(npkt_remaining == 0); 768 MPASS(kring->nr_hwcur == head); 769 MPASS(nm_txq->dbidx == nm_txq->pidx); 770 771 /* 772 * Second part: reclaim buffers for completed transmissions. 773 */ 774 if (reclaimed || flags & NAF_FORCE_RECLAIM || nm_kr_txempty(kring)) { 775 reclaimed += reclaim_nm_tx_desc(nm_txq); 776 kring->nr_hwtail += reclaimed; 777 if (kring->nr_hwtail >= kring->nkr_num_slots) 778 kring->nr_hwtail -= kring->nkr_num_slots; 779 } 780 781 return (0); 782 } 783 784 static int 785 cxgbe_netmap_rxsync(struct netmap_kring *kring, int flags) 786 { 787 struct netmap_adapter *na = kring->na; 788 struct netmap_ring *ring = kring->ring; 789 struct ifnet *ifp = na->ifp; 790 struct vi_info *vi = ifp->if_softc; 791 struct adapter *sc = vi->pi->adapter; 792 struct sge_nm_rxq *nm_rxq = &sc->sge.nm_rxq[vi->first_nm_rxq + kring->ring_id]; 793 u_int const head = kring->rhead; 794 u_int n; 795 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 796 797 if (black_hole) 798 return (0); /* No updates ever. */ 799 800 if (netmap_no_pendintr || force_update) { 801 kring->nr_hwtail = atomic_load_acq_32(&nm_rxq->fl_cidx); 802 kring->nr_kflags &= ~NKR_PENDINTR; 803 } 804 805 /* Userspace done with buffers from kring->nr_hwcur to head */ 806 n = head >= kring->nr_hwcur ? head - kring->nr_hwcur : 807 kring->nkr_num_slots - kring->nr_hwcur + head; 808 n &= ~7U; 809 if (n > 0) { 810 u_int fl_pidx = nm_rxq->fl_pidx; 811 struct netmap_slot *slot = &ring->slot[fl_pidx]; 812 uint64_t ba; 813 int i, dbinc = 0, hwidx = nm_rxq->fl_hwidx; 814 815 /* 816 * We always deal with 8 buffers at a time. We must have 817 * stopped at an 8B boundary (fl_pidx) last time around and we 818 * must have a multiple of 8B buffers to give to the freelist. 819 */ 820 MPASS((fl_pidx & 7) == 0); 821 MPASS((n & 7) == 0); 822 823 IDXINCR(kring->nr_hwcur, n, kring->nkr_num_slots); 824 IDXINCR(nm_rxq->fl_pidx, n, nm_rxq->fl_sidx); 825 826 while (n > 0) { 827 for (i = 0; i < 8; i++, fl_pidx++, slot++) { 828 PNMB(na, slot, &ba); 829 MPASS(ba != 0); 830 nm_rxq->fl_desc[fl_pidx] = htobe64(ba | hwidx); 831 slot->flags &= ~NS_BUF_CHANGED; 832 MPASS(fl_pidx <= nm_rxq->fl_sidx); 833 } 834 n -= 8; 835 if (fl_pidx == nm_rxq->fl_sidx) { 836 fl_pidx = 0; 837 slot = &ring->slot[0]; 838 } 839 if (++dbinc == 8 && n >= 32) { 840 wmb(); 841 t4_write_reg(sc, sc->sge_kdoorbell_reg, 842 nm_rxq->fl_db_val | V_PIDX(dbinc)); 843 dbinc = 0; 844 } 845 } 846 MPASS(nm_rxq->fl_pidx == fl_pidx); 847 848 if (dbinc > 0) { 849 wmb(); 850 t4_write_reg(sc, sc->sge_kdoorbell_reg, 851 nm_rxq->fl_db_val | V_PIDX(dbinc)); 852 } 853 } 854 855 return (0); 856 } 857 858 void 859 cxgbe_nm_attach(struct vi_info *vi) 860 { 861 struct port_info *pi; 862 struct adapter *sc; 863 struct netmap_adapter na; 864 865 MPASS(vi->nnmrxq > 0); 866 MPASS(vi->ifp != NULL); 867 868 pi = vi->pi; 869 sc = pi->adapter; 870 871 bzero(&na, sizeof(na)); 872 873 na.ifp = vi->ifp; 874 na.na_flags = NAF_BDG_MAYSLEEP; 875 876 /* Netmap doesn't know about the space reserved for the status page. */ 877 na.num_tx_desc = vi->qsize_txq - sc->params.sge.spg_len / EQ_ESIZE; 878 879 /* 880 * The freelist's cidx/pidx drives netmap's rx cidx/pidx. So 881 * num_rx_desc is based on the number of buffers that can be held in the 882 * freelist, and not the number of entries in the iq. (These two are 883 * not exactly the same due to the space taken up by the status page). 884 */ 885 na.num_rx_desc = rounddown(vi->qsize_rxq, 8); 886 na.nm_txsync = cxgbe_netmap_txsync; 887 na.nm_rxsync = cxgbe_netmap_rxsync; 888 na.nm_register = cxgbe_netmap_reg; 889 na.num_tx_rings = vi->nnmtxq; 890 na.num_rx_rings = vi->nnmrxq; 891 netmap_attach(&na); 892 } 893 894 void 895 cxgbe_nm_detach(struct vi_info *vi) 896 { 897 898 MPASS(vi->nnmrxq > 0); 899 MPASS(vi->ifp != NULL); 900 901 netmap_detach(vi->ifp); 902 } 903 904 static inline const void * 905 unwrap_nm_fw6_msg(const struct cpl_fw6_msg *cpl) 906 { 907 908 MPASS(cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL); 909 910 /* data[0] is RSS header */ 911 return (&cpl->data[1]); 912 } 913 914 static void 915 handle_nm_sge_egr_update(struct adapter *sc, struct ifnet *ifp, 916 const struct cpl_sge_egr_update *egr) 917 { 918 uint32_t oq; 919 struct sge_nm_txq *nm_txq; 920 921 oq = be32toh(egr->opcode_qid); 922 MPASS(G_CPL_OPCODE(oq) == CPL_SGE_EGR_UPDATE); 923 nm_txq = (void *)sc->sge.eqmap[G_EGR_QID(oq) - sc->sge.eq_start]; 924 925 netmap_tx_irq(ifp, nm_txq->nid); 926 } 927 928 void 929 t4_nm_intr(void *arg) 930 { 931 struct sge_nm_rxq *nm_rxq = arg; 932 struct vi_info *vi = nm_rxq->vi; 933 struct adapter *sc = vi->pi->adapter; 934 struct ifnet *ifp = vi->ifp; 935 struct netmap_adapter *na = NA(ifp); 936 struct netmap_kring *kring = na->rx_rings[nm_rxq->nid]; 937 struct netmap_ring *ring = kring->ring; 938 struct iq_desc *d = &nm_rxq->iq_desc[nm_rxq->iq_cidx]; 939 const void *cpl; 940 uint32_t lq; 941 u_int n = 0, work = 0; 942 uint8_t opcode; 943 uint32_t fl_cidx = atomic_load_acq_32(&nm_rxq->fl_cidx); 944 u_int fl_credits = fl_cidx & 7; 945 946 while ((d->rsp.u.type_gen & F_RSPD_GEN) == nm_rxq->iq_gen) { 947 948 rmb(); 949 950 lq = be32toh(d->rsp.pldbuflen_qid); 951 opcode = d->rss.opcode; 952 cpl = &d->cpl[0]; 953 954 switch (G_RSPD_TYPE(d->rsp.u.type_gen)) { 955 case X_RSPD_TYPE_FLBUF: 956 if (black_hole != 2) { 957 /* No buffer packing so new buf every time */ 958 MPASS(lq & F_RSPD_NEWBUF); 959 } 960 961 /* fall through */ 962 963 case X_RSPD_TYPE_CPL: 964 MPASS(opcode < NUM_CPL_CMDS); 965 966 switch (opcode) { 967 case CPL_FW4_MSG: 968 case CPL_FW6_MSG: 969 cpl = unwrap_nm_fw6_msg(cpl); 970 /* fall through */ 971 case CPL_SGE_EGR_UPDATE: 972 handle_nm_sge_egr_update(sc, ifp, cpl); 973 break; 974 case CPL_RX_PKT: 975 ring->slot[fl_cidx].len = G_RSPD_LEN(lq) - 976 sc->params.sge.fl_pktshift; 977 ring->slot[fl_cidx].flags = 0; 978 fl_cidx += (lq & F_RSPD_NEWBUF) ? 1 : 0; 979 fl_credits += (lq & F_RSPD_NEWBUF) ? 1 : 0; 980 if (__predict_false(fl_cidx == nm_rxq->fl_sidx)) 981 fl_cidx = 0; 982 break; 983 default: 984 panic("%s: unexpected opcode 0x%x on nm_rxq %p", 985 __func__, opcode, nm_rxq); 986 } 987 break; 988 989 case X_RSPD_TYPE_INTR: 990 /* Not equipped to handle forwarded interrupts. */ 991 panic("%s: netmap queue received interrupt for iq %u\n", 992 __func__, lq); 993 994 default: 995 panic("%s: illegal response type %d on nm_rxq %p", 996 __func__, G_RSPD_TYPE(d->rsp.u.type_gen), nm_rxq); 997 } 998 999 d++; 1000 if (__predict_false(++nm_rxq->iq_cidx == nm_rxq->iq_sidx)) { 1001 nm_rxq->iq_cidx = 0; 1002 d = &nm_rxq->iq_desc[0]; 1003 nm_rxq->iq_gen ^= F_RSPD_GEN; 1004 } 1005 1006 if (__predict_false(++n == rx_ndesc)) { 1007 atomic_store_rel_32(&nm_rxq->fl_cidx, fl_cidx); 1008 if (black_hole && fl_credits >= 8) { 1009 fl_credits /= 8; 1010 IDXINCR(nm_rxq->fl_pidx, fl_credits * 8, 1011 nm_rxq->fl_sidx); 1012 t4_write_reg(sc, sc->sge_kdoorbell_reg, 1013 nm_rxq->fl_db_val | V_PIDX(fl_credits)); 1014 fl_credits = fl_cidx & 7; 1015 } else if (!black_hole) { 1016 netmap_rx_irq(ifp, nm_rxq->nid, &work); 1017 MPASS(work != 0); 1018 } 1019 t4_write_reg(sc, sc->sge_gts_reg, 1020 V_CIDXINC(n) | V_INGRESSQID(nm_rxq->iq_cntxt_id) | 1021 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1022 n = 0; 1023 } 1024 } 1025 1026 atomic_store_rel_32(&nm_rxq->fl_cidx, fl_cidx); 1027 if (black_hole) { 1028 fl_credits /= 8; 1029 IDXINCR(nm_rxq->fl_pidx, fl_credits * 8, nm_rxq->fl_sidx); 1030 t4_write_reg(sc, sc->sge_kdoorbell_reg, 1031 nm_rxq->fl_db_val | V_PIDX(fl_credits)); 1032 } else 1033 netmap_rx_irq(ifp, nm_rxq->nid, &work); 1034 1035 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(n) | 1036 V_INGRESSQID((u32)nm_rxq->iq_cntxt_id) | 1037 V_SEINTARM(V_QINTR_TIMER_IDX(holdoff_tmr_idx))); 1038 } 1039 #endif 1040