18cfa0ad2SJack F Vogel /****************************************************************************** 28cfa0ad2SJack F Vogel 36ab6bfe3SJack F Vogel Copyright (c) 2001-2013, Intel Corporation 48cfa0ad2SJack F Vogel All rights reserved. 58cfa0ad2SJack F Vogel 68cfa0ad2SJack F Vogel Redistribution and use in source and binary forms, with or without 78cfa0ad2SJack F Vogel modification, are permitted provided that the following conditions are met: 88cfa0ad2SJack F Vogel 98cfa0ad2SJack F Vogel 1. Redistributions of source code must retain the above copyright notice, 108cfa0ad2SJack F Vogel this list of conditions and the following disclaimer. 118cfa0ad2SJack F Vogel 128cfa0ad2SJack F Vogel 2. Redistributions in binary form must reproduce the above copyright 138cfa0ad2SJack F Vogel notice, this list of conditions and the following disclaimer in the 148cfa0ad2SJack F Vogel documentation and/or other materials provided with the distribution. 158cfa0ad2SJack F Vogel 168cfa0ad2SJack F Vogel 3. Neither the name of the Intel Corporation nor the names of its 178cfa0ad2SJack F Vogel contributors may be used to endorse or promote products derived from 188cfa0ad2SJack F Vogel this software without specific prior written permission. 198cfa0ad2SJack F Vogel 208cfa0ad2SJack F Vogel THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 218cfa0ad2SJack F Vogel AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 228cfa0ad2SJack F Vogel IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 238cfa0ad2SJack F Vogel ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 248cfa0ad2SJack F Vogel LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 258cfa0ad2SJack F Vogel CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 268cfa0ad2SJack F Vogel SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 278cfa0ad2SJack F Vogel INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 288cfa0ad2SJack F Vogel CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 298cfa0ad2SJack F Vogel ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 308cfa0ad2SJack F Vogel POSSIBILITY OF SUCH DAMAGE. 318cfa0ad2SJack F Vogel 328cfa0ad2SJack F Vogel ******************************************************************************/ 338cfa0ad2SJack F Vogel /*$FreeBSD$*/ 348cfa0ad2SJack F Vogel 358cfa0ad2SJack F Vogel #ifndef _E1000_ICH8LAN_H_ 368cfa0ad2SJack F Vogel #define _E1000_ICH8LAN_H_ 378cfa0ad2SJack F Vogel 388cfa0ad2SJack F Vogel #define ICH_FLASH_GFPREG 0x0000 398cfa0ad2SJack F Vogel #define ICH_FLASH_HSFSTS 0x0004 408cfa0ad2SJack F Vogel #define ICH_FLASH_HSFCTL 0x0006 418cfa0ad2SJack F Vogel #define ICH_FLASH_FADDR 0x0008 428cfa0ad2SJack F Vogel #define ICH_FLASH_FDATA0 0x0010 438cfa0ad2SJack F Vogel 44d035aa2dSJack F Vogel /* Requires up to 10 seconds when MNG might be accessing part. */ 45d035aa2dSJack F Vogel #define ICH_FLASH_READ_COMMAND_TIMEOUT 10000000 46d035aa2dSJack F Vogel #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 10000000 47d035aa2dSJack F Vogel #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 10000000 488cfa0ad2SJack F Vogel #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF 498cfa0ad2SJack F Vogel #define ICH_FLASH_CYCLE_REPEAT_COUNT 10 508cfa0ad2SJack F Vogel 518cfa0ad2SJack F Vogel #define ICH_CYCLE_READ 0 528cfa0ad2SJack F Vogel #define ICH_CYCLE_WRITE 2 538cfa0ad2SJack F Vogel #define ICH_CYCLE_ERASE 3 548cfa0ad2SJack F Vogel 558cfa0ad2SJack F Vogel #define FLASH_GFPREG_BASE_MASK 0x1FFF 568cfa0ad2SJack F Vogel #define FLASH_SECTOR_ADDR_SHIFT 12 578cfa0ad2SJack F Vogel 588cfa0ad2SJack F Vogel #define ICH_FLASH_SEG_SIZE_256 256 598cfa0ad2SJack F Vogel #define ICH_FLASH_SEG_SIZE_4K 4096 608cfa0ad2SJack F Vogel #define ICH_FLASH_SEG_SIZE_8K 8192 618cfa0ad2SJack F Vogel #define ICH_FLASH_SEG_SIZE_64K 65536 628cfa0ad2SJack F Vogel 638cfa0ad2SJack F Vogel #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */ 648cfa0ad2SJack F Vogel /* FW established a valid mode */ 658cfa0ad2SJack F Vogel #define E1000_ICH_FWSM_FW_VALID 0x00008000 664dab5c37SJack F Vogel #define E1000_ICH_FWSM_PCIM2PCI 0x01000000 /* ME PCIm-to-PCI active */ 674dab5c37SJack F Vogel #define E1000_ICH_FWSM_PCIM2PCI_COUNT 2000 688cfa0ad2SJack F Vogel 698cfa0ad2SJack F Vogel #define E1000_ICH_MNG_IAMT_MODE 0x2 708cfa0ad2SJack F Vogel 716ab6bfe3SJack F Vogel #define E1000_FWSM_WLOCK_MAC_MASK 0x0380 726ab6bfe3SJack F Vogel #define E1000_FWSM_WLOCK_MAC_SHIFT 7 737d9119bdSJack F Vogel 747d9119bdSJack F Vogel /* Shared Receive Address Registers */ 756ab6bfe3SJack F Vogel #define E1000_SHRAL_PCH_LPT(_i) (0x05408 + ((_i) * 8)) 766ab6bfe3SJack F Vogel #define E1000_SHRAH_PCH_LPT(_i) (0x0540C + ((_i) * 8)) 777d9119bdSJack F Vogel 788cfa0ad2SJack F Vogel #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \ 79d035aa2dSJack F Vogel (ID_LED_OFF1_OFF2 << 8) | \ 80d035aa2dSJack F Vogel (ID_LED_OFF1_ON2 << 4) | \ 818cfa0ad2SJack F Vogel (ID_LED_DEF1_DEF2)) 828cfa0ad2SJack F Vogel 838cfa0ad2SJack F Vogel #define E1000_ICH_NVM_SIG_WORD 0x13 848cfa0ad2SJack F Vogel #define E1000_ICH_NVM_SIG_MASK 0xC000 85d035aa2dSJack F Vogel #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0 86d035aa2dSJack F Vogel #define E1000_ICH_NVM_SIG_VALUE 0x80 878cfa0ad2SJack F Vogel 888cfa0ad2SJack F Vogel #define E1000_ICH8_LAN_INIT_TIMEOUT 1500 898cfa0ad2SJack F Vogel 908cfa0ad2SJack F Vogel #define E1000_FEXTNVM_SW_CONFIG 1 917609433eSJack F Vogel #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* different on ICH8M */ 928cfa0ad2SJack F Vogel 936ab6bfe3SJack F Vogel #define E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK 0x0C000000 946ab6bfe3SJack F Vogel #define E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC 0x08000000 956ab6bfe3SJack F Vogel 967d9119bdSJack F Vogel #define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7 977d9119bdSJack F Vogel #define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7 987d9119bdSJack F Vogel #define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3 997d9119bdSJack F Vogel 1006ab6bfe3SJack F Vogel #define E1000_FEXTNVM6_REQ_PLL_CLK 0x00000100 1017609433eSJack F Vogel #define E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION 0x00000200 1026ab6bfe3SJack F Vogel 1038cfa0ad2SJack F Vogel #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL 1048cfa0ad2SJack F Vogel 1058cfa0ad2SJack F Vogel #define E1000_ICH_RAR_ENTRIES 7 1067609433eSJack F Vogel #define E1000_PCH2_RAR_ENTRIES 11 /* RAR[0-6], SHRA[0-3] */ 1076ab6bfe3SJack F Vogel #define E1000_PCH_LPT_RAR_ENTRIES 12 /* RAR[0], SHRA[0-10] */ 1088cfa0ad2SJack F Vogel 1098cfa0ad2SJack F Vogel #define PHY_PAGE_SHIFT 5 1108cfa0ad2SJack F Vogel #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ 1118cfa0ad2SJack F Vogel ((reg) & MAX_PHY_REG_ADDRESS)) 1128cfa0ad2SJack F Vogel #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */ 1138cfa0ad2SJack F Vogel #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */ 1148cfa0ad2SJack F Vogel 1158cfa0ad2SJack F Vogel #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 1168cfa0ad2SJack F Vogel #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300 1178cfa0ad2SJack F Vogel #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200 1188cfa0ad2SJack F Vogel 119d035aa2dSJack F Vogel /* PHY Wakeup Registers and defines */ 1204dab5c37SJack F Vogel #define BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17) 121d035aa2dSJack F Vogel #define BM_RCTL PHY_REG(BM_WUC_PAGE, 0) 122d035aa2dSJack F Vogel #define BM_WUC PHY_REG(BM_WUC_PAGE, 1) 123d035aa2dSJack F Vogel #define BM_WUFC PHY_REG(BM_WUC_PAGE, 2) 124d035aa2dSJack F Vogel #define BM_WUS PHY_REG(BM_WUC_PAGE, 3) 125d035aa2dSJack F Vogel #define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2))) 126d035aa2dSJack F Vogel #define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2))) 127d035aa2dSJack F Vogel #define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2))) 128d035aa2dSJack F Vogel #define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2))) 129d035aa2dSJack F Vogel #define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1))) 130d035aa2dSJack F Vogel 131d035aa2dSJack F Vogel #define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */ 132d035aa2dSJack F Vogel #define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */ 133d035aa2dSJack F Vogel #define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */ 134d035aa2dSJack F Vogel #define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */ 135d035aa2dSJack F Vogel #define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */ 136d035aa2dSJack F Vogel #define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */ 137d035aa2dSJack F Vogel #define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */ 138d035aa2dSJack F Vogel 1399d81738fSJack F Vogel #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */ 1409d81738fSJack F Vogel #define HV_MUX_DATA_CTRL PHY_REG(776, 16) 1419d81738fSJack F Vogel #define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400 1429d81738fSJack F Vogel #define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004 1434dab5c37SJack F Vogel #define HV_STATS_PAGE 778 1447609433eSJack F Vogel /* Half-duplex collision counts */ 1457609433eSJack F Vogel #define HV_SCC_UPPER PHY_REG(HV_STATS_PAGE, 16) /* Single Collision */ 1464dab5c37SJack F Vogel #define HV_SCC_LOWER PHY_REG(HV_STATS_PAGE, 17) 1477609433eSJack F Vogel #define HV_ECOL_UPPER PHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. */ 1484dab5c37SJack F Vogel #define HV_ECOL_LOWER PHY_REG(HV_STATS_PAGE, 19) 1497609433eSJack F Vogel #define HV_MCC_UPPER PHY_REG(HV_STATS_PAGE, 20) /* Multiple Collision */ 1504dab5c37SJack F Vogel #define HV_MCC_LOWER PHY_REG(HV_STATS_PAGE, 21) 1517609433eSJack F Vogel #define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision */ 1524dab5c37SJack F Vogel #define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24) 1537609433eSJack F Vogel #define HV_COLC_UPPER PHY_REG(HV_STATS_PAGE, 25) /* Collision */ 1544dab5c37SJack F Vogel #define HV_COLC_LOWER PHY_REG(HV_STATS_PAGE, 26) 1554dab5c37SJack F Vogel #define HV_DC_UPPER PHY_REG(HV_STATS_PAGE, 27) /* Defer Count */ 1564dab5c37SJack F Vogel #define HV_DC_LOWER PHY_REG(HV_STATS_PAGE, 28) 1577609433eSJack F Vogel #define HV_TNCRS_UPPER PHY_REG(HV_STATS_PAGE, 29) /* Tx with no CRS */ 1584dab5c37SJack F Vogel #define HV_TNCRS_LOWER PHY_REG(HV_STATS_PAGE, 30) 1599d81738fSJack F Vogel 1604edd8523SJack F Vogel #define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */ 1614edd8523SJack F Vogel 1624edd8523SJack F Vogel #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */ 1634edd8523SJack F Vogel #define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */ 1644edd8523SJack F Vogel 1656ab6bfe3SJack F Vogel /* SMBus Control Phy Register */ 1666ab6bfe3SJack F Vogel #define CV_SMB_CTRL PHY_REG(769, 23) 1676ab6bfe3SJack F Vogel #define CV_SMB_CTRL_FORCE_SMBUS 0x0001 1686ab6bfe3SJack F Vogel 1694edd8523SJack F Vogel /* SMBus Address Phy Register */ 1704edd8523SJack F Vogel #define HV_SMB_ADDR PHY_REG(768, 26) 1717d9119bdSJack F Vogel #define HV_SMB_ADDR_MASK 0x007F 1724edd8523SJack F Vogel #define HV_SMB_ADDR_PEC_EN 0x0200 1734edd8523SJack F Vogel #define HV_SMB_ADDR_VALID 0x0080 1746ab6bfe3SJack F Vogel #define HV_SMB_ADDR_FREQ_MASK 0x1100 1756ab6bfe3SJack F Vogel #define HV_SMB_ADDR_FREQ_LOW_SHIFT 8 1766ab6bfe3SJack F Vogel #define HV_SMB_ADDR_FREQ_HIGH_SHIFT 12 1774edd8523SJack F Vogel 1784edd8523SJack F Vogel /* Strapping Option Register - RO */ 1794edd8523SJack F Vogel #define E1000_STRAP 0x0000C 1804edd8523SJack F Vogel #define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000 1814edd8523SJack F Vogel #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17 1826ab6bfe3SJack F Vogel #define E1000_STRAP_SMT_FREQ_MASK 0x00003000 1836ab6bfe3SJack F Vogel #define E1000_STRAP_SMT_FREQ_SHIFT 12 1844edd8523SJack F Vogel 1854edd8523SJack F Vogel /* OEM Bits Phy Register */ 1864edd8523SJack F Vogel #define HV_OEM_BITS PHY_REG(768, 25) 1874edd8523SJack F Vogel #define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */ 1884edd8523SJack F Vogel #define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */ 1894edd8523SJack F Vogel #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */ 1904edd8523SJack F Vogel 191a69ed8dfSJack F Vogel /* KMRN Mode Control */ 192a69ed8dfSJack F Vogel #define HV_KMRN_MODE_CTRL PHY_REG(769, 16) 193a69ed8dfSJack F Vogel #define HV_KMRN_MDIO_SLOW 0x0400 194a69ed8dfSJack F Vogel 1954dab5c37SJack F Vogel /* KMRN FIFO Control and Status */ 1964dab5c37SJack F Vogel #define HV_KMRN_FIFO_CTRLSTA PHY_REG(770, 16) 1974dab5c37SJack F Vogel #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK 0x7000 1984dab5c37SJack F Vogel #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT 12 1994dab5c37SJack F Vogel 2008ec87fc5SJack F Vogel /* PHY Power Management Control */ 2018ec87fc5SJack F Vogel #define HV_PM_CTRL PHY_REG(770, 17) 2026ab6bfe3SJack F Vogel #define HV_PM_CTRL_PLL_STOP_IN_K1_GIGA 0x100 2038ec87fc5SJack F Vogel 2044dab5c37SJack F Vogel #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in ms */ 2054edd8523SJack F Vogel 2067609433eSJack F Vogel /* Inband Control */ 2077609433eSJack F Vogel #define I217_INBAND_CTRL PHY_REG(770, 18) 2087609433eSJack F Vogel #define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK 0x3F00 2097609433eSJack F Vogel #define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT 8 2107609433eSJack F Vogel 2117609433eSJack F Vogel /* Low Power Idle GPIO Control */ 2127609433eSJack F Vogel #define I217_LPI_GPIO_CTRL PHY_REG(772, 18) 2137609433eSJack F Vogel #define I217_LPI_GPIO_CTRL_AUTO_EN_LPI 0x0800 2147609433eSJack F Vogel 2157d9119bdSJack F Vogel /* PHY Low Power Idle Control */ 2167d9119bdSJack F Vogel #define I82579_LPI_CTRL PHY_REG(772, 20) 2176ab6bfe3SJack F Vogel #define I82579_LPI_CTRL_100_ENABLE 0x2000 2186ab6bfe3SJack F Vogel #define I82579_LPI_CTRL_1000_ENABLE 0x4000 2197d9119bdSJack F Vogel #define I82579_LPI_CTRL_ENABLE_MASK 0x6000 2204dab5c37SJack F Vogel #define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT 0x80 2217d9119bdSJack F Vogel 2227609433eSJack F Vogel /* 82579 DFT Control */ 2237609433eSJack F Vogel #define I82579_DFT_CTRL PHY_REG(769, 20) 2247609433eSJack F Vogel #define I82579_DFT_CTRL_GATE_PHY_RESET 0x0040 /* Gate PHY Reset on MAC Reset */ 2257609433eSJack F Vogel 2266ab6bfe3SJack F Vogel /* Extended Management Interface (EMI) Registers */ 227730d3130SJack F Vogel #define I82579_EMI_ADDR 0x10 228730d3130SJack F Vogel #define I82579_EMI_DATA 0x11 229730d3130SJack F Vogel #define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */ 2306ab6bfe3SJack F Vogel #define I82579_MSE_THRESHOLD 0x084F /* 82579 Mean Square Error Threshold */ 2316ab6bfe3SJack F Vogel #define I82577_MSE_THRESHOLD 0x0887 /* 82577 Mean Square Error Threshold */ 2324dab5c37SJack F Vogel #define I82579_MSE_LINK_DOWN 0x2411 /* MSE count before dropping link */ 2336ab6bfe3SJack F Vogel #define I82579_RX_CONFIG 0x3412 /* Receive configuration */ 2347609433eSJack F Vogel #define I82579_EEE_PCS_STATUS 0x182E /* IEEE MMD Register 3.1 >> 8 */ 2356ab6bfe3SJack F Vogel #define I82579_EEE_CAPABILITY 0x0410 /* IEEE MMD Register 3.20 */ 2366ab6bfe3SJack F Vogel #define I82579_EEE_ADVERTISEMENT 0x040E /* IEEE MMD Register 7.60 */ 2376ab6bfe3SJack F Vogel #define I82579_EEE_LP_ABILITY 0x040F /* IEEE MMD Register 7.61 */ 2387609433eSJack F Vogel #define I82579_EEE_100_SUPPORTED (1 << 1) /* 100BaseTx EEE */ 2397609433eSJack F Vogel #define I82579_EEE_1000_SUPPORTED (1 << 2) /* 1000BaseTx EEE */ 2406ab6bfe3SJack F Vogel #define I217_EEE_PCS_STATUS 0x9401 /* IEEE MMD Register 3.1 */ 2416ab6bfe3SJack F Vogel #define I217_EEE_CAPABILITY 0x8000 /* IEEE MMD Register 3.20 */ 2426ab6bfe3SJack F Vogel #define I217_EEE_ADVERTISEMENT 0x8001 /* IEEE MMD Register 7.60 */ 2436ab6bfe3SJack F Vogel #define I217_EEE_LP_ABILITY 0x8002 /* IEEE MMD Register 7.61 */ 244730d3130SJack F Vogel 2456ab6bfe3SJack F Vogel #define E1000_EEE_RX_LPI_RCVD 0x0400 /* Tx LP idle received */ 2466ab6bfe3SJack F Vogel #define E1000_EEE_TX_LPI_RCVD 0x0800 /* Rx LP idle received */ 2478cfa0ad2SJack F Vogel 2486ab6bfe3SJack F Vogel /* Intel Rapid Start Technology Support */ 2496ab6bfe3SJack F Vogel #define I217_PROXY_CTRL BM_PHY_REG(BM_WUC_PAGE, 70) 2506ab6bfe3SJack F Vogel #define I217_PROXY_CTRL_AUTO_DISABLE 0x0080 2516ab6bfe3SJack F Vogel #define I217_SxCTRL PHY_REG(BM_PORT_CTRL_PAGE, 28) 2526ab6bfe3SJack F Vogel #define I217_SxCTRL_ENABLE_LPI_RESET 0x1000 2536ab6bfe3SJack F Vogel #define I217_CGFREG PHY_REG(772, 29) 2546ab6bfe3SJack F Vogel #define I217_CGFREG_ENABLE_MTA_RESET 0x0002 2556ab6bfe3SJack F Vogel #define I217_MEMPWR PHY_REG(772, 26) 2566ab6bfe3SJack F Vogel #define I217_MEMPWR_DISABLE_SMB_RELEASE 0x0010 2578cfa0ad2SJack F Vogel 2587d9119bdSJack F Vogel /* Receive Address Initial CRC Calculation */ 2597d9119bdSJack F Vogel #define E1000_PCH_RAICC(_n) (0x05F50 + ((_n) * 4)) 2607d9119bdSJack F Vogel 2616ab6bfe3SJack F Vogel /* Latency Tolerance Reporting */ 2626ab6bfe3SJack F Vogel #define E1000_LTRV 0x000F8 2636ab6bfe3SJack F Vogel #define E1000_LTRV_VALUE_MASK 0x000003FF 2646ab6bfe3SJack F Vogel #define E1000_LTRV_SCALE_MAX 5 2656ab6bfe3SJack F Vogel #define E1000_LTRV_SCALE_FACTOR 5 2666ab6bfe3SJack F Vogel #define E1000_LTRV_SCALE_SHIFT 10 2676ab6bfe3SJack F Vogel #define E1000_LTRV_SCALE_MASK 0x00001C00 2686ab6bfe3SJack F Vogel #define E1000_LTRV_REQ_SHIFT 15 2696ab6bfe3SJack F Vogel #define E1000_LTRV_NOSNOOP_SHIFT 16 2706ab6bfe3SJack F Vogel #define E1000_LTRV_SEND (1 << 30) 2716ab6bfe3SJack F Vogel 2726ab6bfe3SJack F Vogel /* Proprietary Latency Tolerance Reporting PCI Capability */ 2736ab6bfe3SJack F Vogel #define E1000_PCI_LTR_CAP_LPT 0xA8 2746ab6bfe3SJack F Vogel 2756ab6bfe3SJack F Vogel /* OBFF Control & Threshold Defines */ 2766ab6bfe3SJack F Vogel #define E1000_SVCR_OFF_EN 0x00000001 2776ab6bfe3SJack F Vogel #define E1000_SVCR_OFF_MASKINT 0x00001000 2786ab6bfe3SJack F Vogel #define E1000_SVCR_OFF_TIMER_MASK 0xFFFF0000 2796ab6bfe3SJack F Vogel #define E1000_SVCR_OFF_TIMER_SHIFT 16 2806ab6bfe3SJack F Vogel #define E1000_SVT_OFF_HWM_MASK 0x0000001F 2816ab6bfe3SJack F Vogel 2828cfa0ad2SJack F Vogel void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 2838cfa0ad2SJack F Vogel bool state); 2848cfa0ad2SJack F Vogel void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw); 2858cfa0ad2SJack F Vogel void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw); 2864dab5c37SJack F Vogel void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw); 2874dab5c37SJack F Vogel void e1000_resume_workarounds_pchlan(struct e1000_hw *hw); 2884edd8523SJack F Vogel s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable); 2897d9119bdSJack F Vogel void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw); 2907d9119bdSJack F Vogel s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable); 2916ab6bfe3SJack F Vogel s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data); 2927609433eSJack F Vogel s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data); 2937609433eSJack F Vogel s32 e1000_set_eee_pchlan(struct e1000_hw *hw); 2947609433eSJack F Vogel void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw); 2956ab6bfe3SJack F Vogel #endif /* _E1000_ICH8LAN_H_ */ 296