18cfa0ad2SJack F Vogel /****************************************************************************** 28cfa0ad2SJack F Vogel 34dab5c37SJack F Vogel Copyright (c) 2001-2011, Intel Corporation 48cfa0ad2SJack F Vogel All rights reserved. 58cfa0ad2SJack F Vogel 68cfa0ad2SJack F Vogel Redistribution and use in source and binary forms, with or without 78cfa0ad2SJack F Vogel modification, are permitted provided that the following conditions are met: 88cfa0ad2SJack F Vogel 98cfa0ad2SJack F Vogel 1. Redistributions of source code must retain the above copyright notice, 108cfa0ad2SJack F Vogel this list of conditions and the following disclaimer. 118cfa0ad2SJack F Vogel 128cfa0ad2SJack F Vogel 2. Redistributions in binary form must reproduce the above copyright 138cfa0ad2SJack F Vogel notice, this list of conditions and the following disclaimer in the 148cfa0ad2SJack F Vogel documentation and/or other materials provided with the distribution. 158cfa0ad2SJack F Vogel 168cfa0ad2SJack F Vogel 3. Neither the name of the Intel Corporation nor the names of its 178cfa0ad2SJack F Vogel contributors may be used to endorse or promote products derived from 188cfa0ad2SJack F Vogel this software without specific prior written permission. 198cfa0ad2SJack F Vogel 208cfa0ad2SJack F Vogel THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 218cfa0ad2SJack F Vogel AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 228cfa0ad2SJack F Vogel IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 238cfa0ad2SJack F Vogel ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 248cfa0ad2SJack F Vogel LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 258cfa0ad2SJack F Vogel CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 268cfa0ad2SJack F Vogel SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 278cfa0ad2SJack F Vogel INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 288cfa0ad2SJack F Vogel CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 298cfa0ad2SJack F Vogel ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 308cfa0ad2SJack F Vogel POSSIBILITY OF SUCH DAMAGE. 318cfa0ad2SJack F Vogel 328cfa0ad2SJack F Vogel ******************************************************************************/ 338cfa0ad2SJack F Vogel /*$FreeBSD$*/ 348cfa0ad2SJack F Vogel 358cfa0ad2SJack F Vogel #include "e1000_api.h" 368cfa0ad2SJack F Vogel 37daf9197cSJack F Vogel static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw); 38d035aa2dSJack F Vogel static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw); 39daf9197cSJack F Vogel 408cfa0ad2SJack F Vogel /** 418cfa0ad2SJack F Vogel * e1000_init_mac_ops_generic - Initialize MAC function pointers 428cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 438cfa0ad2SJack F Vogel * 448cfa0ad2SJack F Vogel * Setups up the function pointers to no-op functions 458cfa0ad2SJack F Vogel **/ 468cfa0ad2SJack F Vogel void e1000_init_mac_ops_generic(struct e1000_hw *hw) 478cfa0ad2SJack F Vogel { 488cfa0ad2SJack F Vogel struct e1000_mac_info *mac = &hw->mac; 498cfa0ad2SJack F Vogel DEBUGFUNC("e1000_init_mac_ops_generic"); 508cfa0ad2SJack F Vogel 518cfa0ad2SJack F Vogel /* General Setup */ 528cfa0ad2SJack F Vogel mac->ops.init_params = e1000_null_ops_generic; 538cfa0ad2SJack F Vogel mac->ops.init_hw = e1000_null_ops_generic; 548cfa0ad2SJack F Vogel mac->ops.reset_hw = e1000_null_ops_generic; 558cfa0ad2SJack F Vogel mac->ops.setup_physical_interface = e1000_null_ops_generic; 568cfa0ad2SJack F Vogel mac->ops.get_bus_info = e1000_null_ops_generic; 57daf9197cSJack F Vogel mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie; 588cfa0ad2SJack F Vogel mac->ops.read_mac_addr = e1000_read_mac_addr_generic; 598cfa0ad2SJack F Vogel mac->ops.config_collision_dist = e1000_config_collision_dist_generic; 608cfa0ad2SJack F Vogel mac->ops.clear_hw_cntrs = e1000_null_mac_generic; 618cfa0ad2SJack F Vogel /* LED */ 628cfa0ad2SJack F Vogel mac->ops.cleanup_led = e1000_null_ops_generic; 638cfa0ad2SJack F Vogel mac->ops.setup_led = e1000_null_ops_generic; 648cfa0ad2SJack F Vogel mac->ops.blink_led = e1000_null_ops_generic; 658cfa0ad2SJack F Vogel mac->ops.led_on = e1000_null_ops_generic; 668cfa0ad2SJack F Vogel mac->ops.led_off = e1000_null_ops_generic; 678cfa0ad2SJack F Vogel /* LINK */ 688cfa0ad2SJack F Vogel mac->ops.setup_link = e1000_null_ops_generic; 698cfa0ad2SJack F Vogel mac->ops.get_link_up_info = e1000_null_link_info; 708cfa0ad2SJack F Vogel mac->ops.check_for_link = e1000_null_ops_generic; 718cfa0ad2SJack F Vogel mac->ops.wait_autoneg = e1000_wait_autoneg_generic; 728cfa0ad2SJack F Vogel /* Management */ 738cfa0ad2SJack F Vogel mac->ops.check_mng_mode = e1000_null_mng_mode; 748cfa0ad2SJack F Vogel mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic; 758cfa0ad2SJack F Vogel mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic; 768cfa0ad2SJack F Vogel mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic; 778cfa0ad2SJack F Vogel /* VLAN, MC, etc. */ 788cfa0ad2SJack F Vogel mac->ops.update_mc_addr_list = e1000_null_update_mc; 798cfa0ad2SJack F Vogel mac->ops.clear_vfta = e1000_null_mac_generic; 808cfa0ad2SJack F Vogel mac->ops.write_vfta = e1000_null_write_vfta; 818cfa0ad2SJack F Vogel mac->ops.rar_set = e1000_rar_set_generic; 828cfa0ad2SJack F Vogel mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic; 838cfa0ad2SJack F Vogel } 848cfa0ad2SJack F Vogel 858cfa0ad2SJack F Vogel /** 868cfa0ad2SJack F Vogel * e1000_null_ops_generic - No-op function, returns 0 878cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 888cfa0ad2SJack F Vogel **/ 898cfa0ad2SJack F Vogel s32 e1000_null_ops_generic(struct e1000_hw *hw) 908cfa0ad2SJack F Vogel { 918cfa0ad2SJack F Vogel DEBUGFUNC("e1000_null_ops_generic"); 928cfa0ad2SJack F Vogel return E1000_SUCCESS; 938cfa0ad2SJack F Vogel } 948cfa0ad2SJack F Vogel 958cfa0ad2SJack F Vogel /** 968cfa0ad2SJack F Vogel * e1000_null_mac_generic - No-op function, return void 978cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 988cfa0ad2SJack F Vogel **/ 998cfa0ad2SJack F Vogel void e1000_null_mac_generic(struct e1000_hw *hw) 1008cfa0ad2SJack F Vogel { 1018cfa0ad2SJack F Vogel DEBUGFUNC("e1000_null_mac_generic"); 1028cfa0ad2SJack F Vogel return; 1038cfa0ad2SJack F Vogel } 1048cfa0ad2SJack F Vogel 1058cfa0ad2SJack F Vogel /** 1068cfa0ad2SJack F Vogel * e1000_null_link_info - No-op function, return 0 1078cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 1088cfa0ad2SJack F Vogel **/ 1098cfa0ad2SJack F Vogel s32 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d) 1108cfa0ad2SJack F Vogel { 1118cfa0ad2SJack F Vogel DEBUGFUNC("e1000_null_link_info"); 1128cfa0ad2SJack F Vogel return E1000_SUCCESS; 1138cfa0ad2SJack F Vogel } 1148cfa0ad2SJack F Vogel 1158cfa0ad2SJack F Vogel /** 1168cfa0ad2SJack F Vogel * e1000_null_mng_mode - No-op function, return FALSE 1178cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 1188cfa0ad2SJack F Vogel **/ 1198cfa0ad2SJack F Vogel bool e1000_null_mng_mode(struct e1000_hw *hw) 1208cfa0ad2SJack F Vogel { 1218cfa0ad2SJack F Vogel DEBUGFUNC("e1000_null_mng_mode"); 1228cfa0ad2SJack F Vogel return FALSE; 1238cfa0ad2SJack F Vogel } 1248cfa0ad2SJack F Vogel 1258cfa0ad2SJack F Vogel /** 1268cfa0ad2SJack F Vogel * e1000_null_update_mc - No-op function, return void 1278cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 1288cfa0ad2SJack F Vogel **/ 129d035aa2dSJack F Vogel void e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a) 1308cfa0ad2SJack F Vogel { 1318cfa0ad2SJack F Vogel DEBUGFUNC("e1000_null_update_mc"); 1328cfa0ad2SJack F Vogel return; 1338cfa0ad2SJack F Vogel } 1348cfa0ad2SJack F Vogel 1358cfa0ad2SJack F Vogel /** 1368cfa0ad2SJack F Vogel * e1000_null_write_vfta - No-op function, return void 1378cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 1388cfa0ad2SJack F Vogel **/ 1398cfa0ad2SJack F Vogel void e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b) 1408cfa0ad2SJack F Vogel { 1418cfa0ad2SJack F Vogel DEBUGFUNC("e1000_null_write_vfta"); 1428cfa0ad2SJack F Vogel return; 1438cfa0ad2SJack F Vogel } 1448cfa0ad2SJack F Vogel 1458cfa0ad2SJack F Vogel /** 1468cfa0ad2SJack F Vogel * e1000_null_rar_set - No-op function, return void 1478cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 1488cfa0ad2SJack F Vogel **/ 1498cfa0ad2SJack F Vogel void e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a) 1508cfa0ad2SJack F Vogel { 1518cfa0ad2SJack F Vogel DEBUGFUNC("e1000_null_rar_set"); 1528cfa0ad2SJack F Vogel return; 1538cfa0ad2SJack F Vogel } 1548cfa0ad2SJack F Vogel 1558cfa0ad2SJack F Vogel /** 1568cfa0ad2SJack F Vogel * e1000_get_bus_info_pci_generic - Get PCI(x) bus information 1578cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 1588cfa0ad2SJack F Vogel * 1598cfa0ad2SJack F Vogel * Determines and stores the system bus information for a particular 1608cfa0ad2SJack F Vogel * network interface. The following bus information is determined and stored: 1618cfa0ad2SJack F Vogel * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function. 1628cfa0ad2SJack F Vogel **/ 1638cfa0ad2SJack F Vogel s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw) 1648cfa0ad2SJack F Vogel { 165daf9197cSJack F Vogel struct e1000_mac_info *mac = &hw->mac; 1668cfa0ad2SJack F Vogel struct e1000_bus_info *bus = &hw->bus; 1678cfa0ad2SJack F Vogel u32 status = E1000_READ_REG(hw, E1000_STATUS); 1688cfa0ad2SJack F Vogel s32 ret_val = E1000_SUCCESS; 1698cfa0ad2SJack F Vogel 1708cfa0ad2SJack F Vogel DEBUGFUNC("e1000_get_bus_info_pci_generic"); 1718cfa0ad2SJack F Vogel 1728cfa0ad2SJack F Vogel /* PCI or PCI-X? */ 1738cfa0ad2SJack F Vogel bus->type = (status & E1000_STATUS_PCIX_MODE) 1748cfa0ad2SJack F Vogel ? e1000_bus_type_pcix 1758cfa0ad2SJack F Vogel : e1000_bus_type_pci; 1768cfa0ad2SJack F Vogel 1778cfa0ad2SJack F Vogel /* Bus speed */ 1788cfa0ad2SJack F Vogel if (bus->type == e1000_bus_type_pci) { 1798cfa0ad2SJack F Vogel bus->speed = (status & E1000_STATUS_PCI66) 1808cfa0ad2SJack F Vogel ? e1000_bus_speed_66 1818cfa0ad2SJack F Vogel : e1000_bus_speed_33; 1828cfa0ad2SJack F Vogel } else { 1838cfa0ad2SJack F Vogel switch (status & E1000_STATUS_PCIX_SPEED) { 1848cfa0ad2SJack F Vogel case E1000_STATUS_PCIX_SPEED_66: 1858cfa0ad2SJack F Vogel bus->speed = e1000_bus_speed_66; 1868cfa0ad2SJack F Vogel break; 1878cfa0ad2SJack F Vogel case E1000_STATUS_PCIX_SPEED_100: 1888cfa0ad2SJack F Vogel bus->speed = e1000_bus_speed_100; 1898cfa0ad2SJack F Vogel break; 1908cfa0ad2SJack F Vogel case E1000_STATUS_PCIX_SPEED_133: 1918cfa0ad2SJack F Vogel bus->speed = e1000_bus_speed_133; 1928cfa0ad2SJack F Vogel break; 1938cfa0ad2SJack F Vogel default: 1948cfa0ad2SJack F Vogel bus->speed = e1000_bus_speed_reserved; 1958cfa0ad2SJack F Vogel break; 1968cfa0ad2SJack F Vogel } 1978cfa0ad2SJack F Vogel } 1988cfa0ad2SJack F Vogel 1998cfa0ad2SJack F Vogel /* Bus width */ 2008cfa0ad2SJack F Vogel bus->width = (status & E1000_STATUS_BUS64) 2018cfa0ad2SJack F Vogel ? e1000_bus_width_64 2028cfa0ad2SJack F Vogel : e1000_bus_width_32; 2038cfa0ad2SJack F Vogel 2048cfa0ad2SJack F Vogel /* Which PCI(-X) function? */ 205daf9197cSJack F Vogel mac->ops.set_lan_id(hw); 2068cfa0ad2SJack F Vogel 2078cfa0ad2SJack F Vogel return ret_val; 2088cfa0ad2SJack F Vogel } 2098cfa0ad2SJack F Vogel 2108cfa0ad2SJack F Vogel /** 2118cfa0ad2SJack F Vogel * e1000_get_bus_info_pcie_generic - Get PCIe bus information 2128cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 2138cfa0ad2SJack F Vogel * 2148cfa0ad2SJack F Vogel * Determines and stores the system bus information for a particular 2158cfa0ad2SJack F Vogel * network interface. The following bus information is determined and stored: 2168cfa0ad2SJack F Vogel * bus speed, bus width, type (PCIe), and PCIe function. 2178cfa0ad2SJack F Vogel **/ 2188cfa0ad2SJack F Vogel s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) 2198cfa0ad2SJack F Vogel { 220daf9197cSJack F Vogel struct e1000_mac_info *mac = &hw->mac; 2218cfa0ad2SJack F Vogel struct e1000_bus_info *bus = &hw->bus; 2228cfa0ad2SJack F Vogel s32 ret_val; 223daf9197cSJack F Vogel u16 pcie_link_status; 2248cfa0ad2SJack F Vogel 2258cfa0ad2SJack F Vogel DEBUGFUNC("e1000_get_bus_info_pcie_generic"); 2268cfa0ad2SJack F Vogel 2278cfa0ad2SJack F Vogel bus->type = e1000_bus_type_pci_express; 2288cfa0ad2SJack F Vogel 2294dab5c37SJack F Vogel ret_val = e1000_read_pcie_cap_reg(hw, PCIE_LINK_STATUS, 2308cfa0ad2SJack F Vogel &pcie_link_status); 2318ec87fc5SJack F Vogel if (ret_val) { 2328cfa0ad2SJack F Vogel bus->width = e1000_bus_width_unknown; 2338ec87fc5SJack F Vogel bus->speed = e1000_bus_speed_unknown; 2348ec87fc5SJack F Vogel } else { 2358ec87fc5SJack F Vogel switch (pcie_link_status & PCIE_LINK_SPEED_MASK) { 2368ec87fc5SJack F Vogel case PCIE_LINK_SPEED_2500: 2378ec87fc5SJack F Vogel bus->speed = e1000_bus_speed_2500; 2388ec87fc5SJack F Vogel break; 2398ec87fc5SJack F Vogel case PCIE_LINK_SPEED_5000: 2408ec87fc5SJack F Vogel bus->speed = e1000_bus_speed_5000; 2418ec87fc5SJack F Vogel break; 2428ec87fc5SJack F Vogel default: 2438ec87fc5SJack F Vogel bus->speed = e1000_bus_speed_unknown; 2448ec87fc5SJack F Vogel break; 2458ec87fc5SJack F Vogel } 2468ec87fc5SJack F Vogel 2478cfa0ad2SJack F Vogel bus->width = (enum e1000_bus_width)((pcie_link_status & 2484dab5c37SJack F Vogel PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT); 2498ec87fc5SJack F Vogel } 2508cfa0ad2SJack F Vogel 251daf9197cSJack F Vogel mac->ops.set_lan_id(hw); 252daf9197cSJack F Vogel 253daf9197cSJack F Vogel return E1000_SUCCESS; 254daf9197cSJack F Vogel } 255daf9197cSJack F Vogel 256daf9197cSJack F Vogel /** 257daf9197cSJack F Vogel * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 258daf9197cSJack F Vogel * 259daf9197cSJack F Vogel * @hw: pointer to the HW structure 260daf9197cSJack F Vogel * 261daf9197cSJack F Vogel * Determines the LAN function id by reading memory-mapped registers 262daf9197cSJack F Vogel * and swaps the port value if requested. 263daf9197cSJack F Vogel **/ 264d035aa2dSJack F Vogel static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) 265daf9197cSJack F Vogel { 266daf9197cSJack F Vogel struct e1000_bus_info *bus = &hw->bus; 267daf9197cSJack F Vogel u32 reg; 268daf9197cSJack F Vogel 269d035aa2dSJack F Vogel /* 270d035aa2dSJack F Vogel * The status register reports the correct function number 271d035aa2dSJack F Vogel * for the device regardless of function swap state. 272d035aa2dSJack F Vogel */ 273daf9197cSJack F Vogel reg = E1000_READ_REG(hw, E1000_STATUS); 274daf9197cSJack F Vogel bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; 275daf9197cSJack F Vogel } 276daf9197cSJack F Vogel 277daf9197cSJack F Vogel /** 278daf9197cSJack F Vogel * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices 279daf9197cSJack F Vogel * @hw: pointer to the HW structure 280daf9197cSJack F Vogel * 281daf9197cSJack F Vogel * Determines the LAN function id by reading PCI config space. 282daf9197cSJack F Vogel **/ 283daf9197cSJack F Vogel void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw) 284daf9197cSJack F Vogel { 285daf9197cSJack F Vogel struct e1000_bus_info *bus = &hw->bus; 286daf9197cSJack F Vogel u16 pci_header_type; 287daf9197cSJack F Vogel u32 status; 288daf9197cSJack F Vogel 2898cfa0ad2SJack F Vogel e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 2908cfa0ad2SJack F Vogel if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) { 2918cfa0ad2SJack F Vogel status = E1000_READ_REG(hw, E1000_STATUS); 2928cfa0ad2SJack F Vogel bus->func = (status & E1000_STATUS_FUNC_MASK) 2938cfa0ad2SJack F Vogel >> E1000_STATUS_FUNC_SHIFT; 2948cfa0ad2SJack F Vogel } else { 2958cfa0ad2SJack F Vogel bus->func = 0; 2968cfa0ad2SJack F Vogel } 297daf9197cSJack F Vogel } 2988cfa0ad2SJack F Vogel 299daf9197cSJack F Vogel /** 300daf9197cSJack F Vogel * e1000_set_lan_id_single_port - Set LAN id for a single port device 301daf9197cSJack F Vogel * @hw: pointer to the HW structure 302daf9197cSJack F Vogel * 303daf9197cSJack F Vogel * Sets the LAN function id to zero for a single port device. 304daf9197cSJack F Vogel **/ 305daf9197cSJack F Vogel void e1000_set_lan_id_single_port(struct e1000_hw *hw) 306daf9197cSJack F Vogel { 307daf9197cSJack F Vogel struct e1000_bus_info *bus = &hw->bus; 308daf9197cSJack F Vogel 309daf9197cSJack F Vogel bus->func = 0; 3108cfa0ad2SJack F Vogel } 3118cfa0ad2SJack F Vogel 3128cfa0ad2SJack F Vogel /** 3138cfa0ad2SJack F Vogel * e1000_clear_vfta_generic - Clear VLAN filter table 3148cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 3158cfa0ad2SJack F Vogel * 3168cfa0ad2SJack F Vogel * Clears the register array which contains the VLAN filter table by 3178cfa0ad2SJack F Vogel * setting all the values to 0. 3188cfa0ad2SJack F Vogel **/ 3198cfa0ad2SJack F Vogel void e1000_clear_vfta_generic(struct e1000_hw *hw) 3208cfa0ad2SJack F Vogel { 3218cfa0ad2SJack F Vogel u32 offset; 3228cfa0ad2SJack F Vogel 3238cfa0ad2SJack F Vogel DEBUGFUNC("e1000_clear_vfta_generic"); 3248cfa0ad2SJack F Vogel 3258cfa0ad2SJack F Vogel for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 3268cfa0ad2SJack F Vogel E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 3278cfa0ad2SJack F Vogel E1000_WRITE_FLUSH(hw); 3288cfa0ad2SJack F Vogel } 3298cfa0ad2SJack F Vogel } 3308cfa0ad2SJack F Vogel 3318cfa0ad2SJack F Vogel /** 3328cfa0ad2SJack F Vogel * e1000_write_vfta_generic - Write value to VLAN filter table 3338cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 3348cfa0ad2SJack F Vogel * @offset: register offset in VLAN filter table 3358cfa0ad2SJack F Vogel * @value: register value written to VLAN filter table 3368cfa0ad2SJack F Vogel * 3378cfa0ad2SJack F Vogel * Writes value at the given offset in the register array which stores 3388cfa0ad2SJack F Vogel * the VLAN filter table. 3398cfa0ad2SJack F Vogel **/ 3408cfa0ad2SJack F Vogel void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) 3418cfa0ad2SJack F Vogel { 3428cfa0ad2SJack F Vogel DEBUGFUNC("e1000_write_vfta_generic"); 3438cfa0ad2SJack F Vogel 3448cfa0ad2SJack F Vogel E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 3458cfa0ad2SJack F Vogel E1000_WRITE_FLUSH(hw); 3468cfa0ad2SJack F Vogel } 3478cfa0ad2SJack F Vogel 3488cfa0ad2SJack F Vogel /** 3498cfa0ad2SJack F Vogel * e1000_init_rx_addrs_generic - Initialize receive address's 3508cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 3518cfa0ad2SJack F Vogel * @rar_count: receive address registers 3528cfa0ad2SJack F Vogel * 3534dab5c37SJack F Vogel * Setup the receive address registers by setting the base receive address 3548cfa0ad2SJack F Vogel * register to the devices MAC address and clearing all the other receive 3558cfa0ad2SJack F Vogel * address registers to 0. 3568cfa0ad2SJack F Vogel **/ 3578cfa0ad2SJack F Vogel void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) 3588cfa0ad2SJack F Vogel { 3598cfa0ad2SJack F Vogel u32 i; 360d035aa2dSJack F Vogel u8 mac_addr[ETH_ADDR_LEN] = {0}; 3618cfa0ad2SJack F Vogel 3628cfa0ad2SJack F Vogel DEBUGFUNC("e1000_init_rx_addrs_generic"); 3638cfa0ad2SJack F Vogel 3648cfa0ad2SJack F Vogel /* Setup the receive address */ 3658cfa0ad2SJack F Vogel DEBUGOUT("Programming MAC Address into RAR[0]\n"); 3668cfa0ad2SJack F Vogel 3678cfa0ad2SJack F Vogel hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 3688cfa0ad2SJack F Vogel 3698cfa0ad2SJack F Vogel /* Zero out the other (rar_entry_count - 1) receive addresses */ 3708cfa0ad2SJack F Vogel DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 371d035aa2dSJack F Vogel for (i = 1; i < rar_count; i++) 372d035aa2dSJack F Vogel hw->mac.ops.rar_set(hw, mac_addr, i); 3738cfa0ad2SJack F Vogel } 3748cfa0ad2SJack F Vogel 3758cfa0ad2SJack F Vogel /** 3768cfa0ad2SJack F Vogel * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr 3778cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 3788cfa0ad2SJack F Vogel * 3798cfa0ad2SJack F Vogel * Checks the nvm for an alternate MAC address. An alternate MAC address 3808cfa0ad2SJack F Vogel * can be setup by pre-boot software and must be treated like a permanent 3818cfa0ad2SJack F Vogel * address and must override the actual permanent MAC address. If an 382d035aa2dSJack F Vogel * alternate MAC address is found it is programmed into RAR0, replacing 383d035aa2dSJack F Vogel * the permanent address that was installed into RAR0 by the Si on reset. 384d035aa2dSJack F Vogel * This function will return SUCCESS unless it encounters an error while 385d035aa2dSJack F Vogel * reading the EEPROM. 3868cfa0ad2SJack F Vogel **/ 3878cfa0ad2SJack F Vogel s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) 3888cfa0ad2SJack F Vogel { 3898cfa0ad2SJack F Vogel u32 i; 3908cfa0ad2SJack F Vogel s32 ret_val = E1000_SUCCESS; 3918cfa0ad2SJack F Vogel u16 offset, nvm_alt_mac_addr_offset, nvm_data; 3928cfa0ad2SJack F Vogel u8 alt_mac_addr[ETH_ADDR_LEN]; 3938cfa0ad2SJack F Vogel 3948cfa0ad2SJack F Vogel DEBUGFUNC("e1000_check_alt_mac_addr_generic"); 3958cfa0ad2SJack F Vogel 3967d9119bdSJack F Vogel ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data); 3977d9119bdSJack F Vogel if (ret_val) 3987d9119bdSJack F Vogel goto out; 3997d9119bdSJack F Vogel 4004dab5c37SJack F Vogel /* not supported on older hardware or 82573 */ 4014dab5c37SJack F Vogel if ((hw->mac.type < e1000_82571) || (hw->mac.type == e1000_82573)) 4024dab5c37SJack F Vogel goto out; 4034dab5c37SJack F Vogel 4044dab5c37SJack F Vogel /* 4054dab5c37SJack F Vogel * Alternate MAC address is handled by the option ROM for 82580 4064dab5c37SJack F Vogel * and newer. SW support not required. 4074dab5c37SJack F Vogel */ 4084dab5c37SJack F Vogel if (hw->mac.type >= e1000_82580) 4097d9119bdSJack F Vogel goto out; 4107d9119bdSJack F Vogel 4118cfa0ad2SJack F Vogel ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, 4128cfa0ad2SJack F Vogel &nvm_alt_mac_addr_offset); 4138cfa0ad2SJack F Vogel if (ret_val) { 4148cfa0ad2SJack F Vogel DEBUGOUT("NVM Read Error\n"); 4158cfa0ad2SJack F Vogel goto out; 4168cfa0ad2SJack F Vogel } 4178cfa0ad2SJack F Vogel 4184dab5c37SJack F Vogel if ((nvm_alt_mac_addr_offset == 0xFFFF) || 4194dab5c37SJack F Vogel (nvm_alt_mac_addr_offset == 0x0000)) 420d035aa2dSJack F Vogel /* There is no Alternate MAC Address */ 4218cfa0ad2SJack F Vogel goto out; 4228cfa0ad2SJack F Vogel 4238cfa0ad2SJack F Vogel if (hw->bus.func == E1000_FUNC_1) 424d035aa2dSJack F Vogel nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; 4254edd8523SJack F Vogel if (hw->bus.func == E1000_FUNC_2) 4264edd8523SJack F Vogel nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2; 4274edd8523SJack F Vogel 4284edd8523SJack F Vogel if (hw->bus.func == E1000_FUNC_3) 4294edd8523SJack F Vogel nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3; 4308cfa0ad2SJack F Vogel for (i = 0; i < ETH_ADDR_LEN; i += 2) { 4318cfa0ad2SJack F Vogel offset = nvm_alt_mac_addr_offset + (i >> 1); 4328cfa0ad2SJack F Vogel ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 4338cfa0ad2SJack F Vogel if (ret_val) { 4348cfa0ad2SJack F Vogel DEBUGOUT("NVM Read Error\n"); 4358cfa0ad2SJack F Vogel goto out; 4368cfa0ad2SJack F Vogel } 4378cfa0ad2SJack F Vogel 4388cfa0ad2SJack F Vogel alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 4398cfa0ad2SJack F Vogel alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 4408cfa0ad2SJack F Vogel } 4418cfa0ad2SJack F Vogel 4428cfa0ad2SJack F Vogel /* if multicast bit is set, the alternate address will not be used */ 4438cfa0ad2SJack F Vogel if (alt_mac_addr[0] & 0x01) { 444d035aa2dSJack F Vogel DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n"); 4458cfa0ad2SJack F Vogel goto out; 4468cfa0ad2SJack F Vogel } 4478cfa0ad2SJack F Vogel 448d035aa2dSJack F Vogel /* 449d035aa2dSJack F Vogel * We have a valid alternate MAC address, and we want to treat it the 450d035aa2dSJack F Vogel * same as the normal permanent MAC address stored by the HW into the 451d035aa2dSJack F Vogel * RAR. Do this by mapping this address into RAR0. 452d035aa2dSJack F Vogel */ 453d035aa2dSJack F Vogel hw->mac.ops.rar_set(hw, alt_mac_addr, 0); 4548cfa0ad2SJack F Vogel 4558cfa0ad2SJack F Vogel out: 4568cfa0ad2SJack F Vogel return ret_val; 4578cfa0ad2SJack F Vogel } 4588cfa0ad2SJack F Vogel 4598cfa0ad2SJack F Vogel /** 4608cfa0ad2SJack F Vogel * e1000_rar_set_generic - Set receive address register 4618cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 4628cfa0ad2SJack F Vogel * @addr: pointer to the receive address 4638cfa0ad2SJack F Vogel * @index: receive address array register 4648cfa0ad2SJack F Vogel * 4658cfa0ad2SJack F Vogel * Sets the receive address array register at index to the address passed 4668cfa0ad2SJack F Vogel * in by addr. 4678cfa0ad2SJack F Vogel **/ 4688cfa0ad2SJack F Vogel void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) 4698cfa0ad2SJack F Vogel { 4708cfa0ad2SJack F Vogel u32 rar_low, rar_high; 4718cfa0ad2SJack F Vogel 4728cfa0ad2SJack F Vogel DEBUGFUNC("e1000_rar_set_generic"); 4738cfa0ad2SJack F Vogel 4748cfa0ad2SJack F Vogel /* 4758cfa0ad2SJack F Vogel * HW expects these in little endian so we reverse the byte order 4768cfa0ad2SJack F Vogel * from network order (big endian) to little endian 4778cfa0ad2SJack F Vogel */ 4784dab5c37SJack F Vogel rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 4798cfa0ad2SJack F Vogel ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 4808cfa0ad2SJack F Vogel 4818cfa0ad2SJack F Vogel rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 4828cfa0ad2SJack F Vogel 4838cfa0ad2SJack F Vogel /* If MAC address zero, no need to set the AV bit */ 484daf9197cSJack F Vogel if (rar_low || rar_high) 4858cfa0ad2SJack F Vogel rar_high |= E1000_RAH_AV; 4868cfa0ad2SJack F Vogel 487d035aa2dSJack F Vogel /* 488d035aa2dSJack F Vogel * Some bridges will combine consecutive 32-bit writes into 489d035aa2dSJack F Vogel * a single burst write, which will malfunction on some parts. 490d035aa2dSJack F Vogel * The flushes avoid this. 491d035aa2dSJack F Vogel */ 4928cfa0ad2SJack F Vogel E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 493d035aa2dSJack F Vogel E1000_WRITE_FLUSH(hw); 4948cfa0ad2SJack F Vogel E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 495d035aa2dSJack F Vogel E1000_WRITE_FLUSH(hw); 4968cfa0ad2SJack F Vogel } 4978cfa0ad2SJack F Vogel 4988cfa0ad2SJack F Vogel /** 4998cfa0ad2SJack F Vogel * e1000_update_mc_addr_list_generic - Update Multicast addresses 5008cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 5018cfa0ad2SJack F Vogel * @mc_addr_list: array of multicast addresses to program 5028cfa0ad2SJack F Vogel * @mc_addr_count: number of multicast addresses to program 5038cfa0ad2SJack F Vogel * 504d035aa2dSJack F Vogel * Updates entire Multicast Table Array. 5058cfa0ad2SJack F Vogel * The caller must have a packed mc_addr_list of multicast addresses. 5068cfa0ad2SJack F Vogel **/ 5078cfa0ad2SJack F Vogel void e1000_update_mc_addr_list_generic(struct e1000_hw *hw, 508d035aa2dSJack F Vogel u8 *mc_addr_list, u32 mc_addr_count) 5098cfa0ad2SJack F Vogel { 510d035aa2dSJack F Vogel u32 hash_value, hash_bit, hash_reg; 511d035aa2dSJack F Vogel int i; 5128cfa0ad2SJack F Vogel 5138cfa0ad2SJack F Vogel DEBUGFUNC("e1000_update_mc_addr_list_generic"); 5148cfa0ad2SJack F Vogel 515d035aa2dSJack F Vogel /* clear mta_shadow */ 516d035aa2dSJack F Vogel memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 5178cfa0ad2SJack F Vogel 518d035aa2dSJack F Vogel /* update mta_shadow from mc_addr_list */ 519d035aa2dSJack F Vogel for (i = 0; (u32) i < mc_addr_count; i++) { 5208cfa0ad2SJack F Vogel hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list); 521d035aa2dSJack F Vogel 522d035aa2dSJack F Vogel hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 523d035aa2dSJack F Vogel hash_bit = hash_value & 0x1F; 524d035aa2dSJack F Vogel 525d035aa2dSJack F Vogel hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); 526d035aa2dSJack F Vogel mc_addr_list += (ETH_ADDR_LEN); 5278cfa0ad2SJack F Vogel } 528d035aa2dSJack F Vogel 529d035aa2dSJack F Vogel /* replace the entire MTA table */ 530d035aa2dSJack F Vogel for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 531d035aa2dSJack F Vogel E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); 532d035aa2dSJack F Vogel E1000_WRITE_FLUSH(hw); 5338cfa0ad2SJack F Vogel } 5348cfa0ad2SJack F Vogel 5358cfa0ad2SJack F Vogel /** 5368cfa0ad2SJack F Vogel * e1000_hash_mc_addr_generic - Generate a multicast hash value 5378cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 5388cfa0ad2SJack F Vogel * @mc_addr: pointer to a multicast address 5398cfa0ad2SJack F Vogel * 5408cfa0ad2SJack F Vogel * Generates a multicast address hash value which is used to determine 541a69ed8dfSJack F Vogel * the multicast filter table array address and new table value. 5428cfa0ad2SJack F Vogel **/ 5438cfa0ad2SJack F Vogel u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) 5448cfa0ad2SJack F Vogel { 5458cfa0ad2SJack F Vogel u32 hash_value, hash_mask; 5468cfa0ad2SJack F Vogel u8 bit_shift = 0; 5478cfa0ad2SJack F Vogel 5488cfa0ad2SJack F Vogel DEBUGFUNC("e1000_hash_mc_addr_generic"); 5498cfa0ad2SJack F Vogel 5508cfa0ad2SJack F Vogel /* Register count multiplied by bits per register */ 5518cfa0ad2SJack F Vogel hash_mask = (hw->mac.mta_reg_count * 32) - 1; 5528cfa0ad2SJack F Vogel 5538cfa0ad2SJack F Vogel /* 5548cfa0ad2SJack F Vogel * For a mc_filter_type of 0, bit_shift is the number of left-shifts 5558cfa0ad2SJack F Vogel * where 0xFF would still fall within the hash mask. 5568cfa0ad2SJack F Vogel */ 5578cfa0ad2SJack F Vogel while (hash_mask >> bit_shift != 0xFF) 5588cfa0ad2SJack F Vogel bit_shift++; 5598cfa0ad2SJack F Vogel 5608cfa0ad2SJack F Vogel /* 5618cfa0ad2SJack F Vogel * The portion of the address that is used for the hash table 5628cfa0ad2SJack F Vogel * is determined by the mc_filter_type setting. 5638cfa0ad2SJack F Vogel * The algorithm is such that there is a total of 8 bits of shifting. 5648cfa0ad2SJack F Vogel * The bit_shift for a mc_filter_type of 0 represents the number of 5658cfa0ad2SJack F Vogel * left-shifts where the MSB of mc_addr[5] would still fall within 5668cfa0ad2SJack F Vogel * the hash_mask. Case 0 does this exactly. Since there are a total 5678cfa0ad2SJack F Vogel * of 8 bits of shifting, then mc_addr[4] will shift right the 5688cfa0ad2SJack F Vogel * remaining number of bits. Thus 8 - bit_shift. The rest of the 5698cfa0ad2SJack F Vogel * cases are a variation of this algorithm...essentially raising the 5708cfa0ad2SJack F Vogel * number of bits to shift mc_addr[5] left, while still keeping the 5718cfa0ad2SJack F Vogel * 8-bit shifting total. 5728cfa0ad2SJack F Vogel * 5738cfa0ad2SJack F Vogel * For example, given the following Destination MAC Address and an 5748cfa0ad2SJack F Vogel * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 5758cfa0ad2SJack F Vogel * we can see that the bit_shift for case 0 is 4. These are the hash 5768cfa0ad2SJack F Vogel * values resulting from each mc_filter_type... 5778cfa0ad2SJack F Vogel * [0] [1] [2] [3] [4] [5] 5788cfa0ad2SJack F Vogel * 01 AA 00 12 34 56 5798cfa0ad2SJack F Vogel * LSB MSB 5808cfa0ad2SJack F Vogel * 5818cfa0ad2SJack F Vogel * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 5828cfa0ad2SJack F Vogel * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 5838cfa0ad2SJack F Vogel * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 5848cfa0ad2SJack F Vogel * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 5858cfa0ad2SJack F Vogel */ 5868cfa0ad2SJack F Vogel switch (hw->mac.mc_filter_type) { 5878cfa0ad2SJack F Vogel default: 5888cfa0ad2SJack F Vogel case 0: 5898cfa0ad2SJack F Vogel break; 5908cfa0ad2SJack F Vogel case 1: 5918cfa0ad2SJack F Vogel bit_shift += 1; 5928cfa0ad2SJack F Vogel break; 5938cfa0ad2SJack F Vogel case 2: 5948cfa0ad2SJack F Vogel bit_shift += 2; 5958cfa0ad2SJack F Vogel break; 5968cfa0ad2SJack F Vogel case 3: 5978cfa0ad2SJack F Vogel bit_shift += 4; 5988cfa0ad2SJack F Vogel break; 5998cfa0ad2SJack F Vogel } 6008cfa0ad2SJack F Vogel 6018cfa0ad2SJack F Vogel hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 6028cfa0ad2SJack F Vogel (((u16) mc_addr[5]) << bit_shift))); 6038cfa0ad2SJack F Vogel 6048cfa0ad2SJack F Vogel return hash_value; 6058cfa0ad2SJack F Vogel } 6068cfa0ad2SJack F Vogel 6078cfa0ad2SJack F Vogel /** 6088cfa0ad2SJack F Vogel * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value 6098cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 6108cfa0ad2SJack F Vogel * 6118cfa0ad2SJack F Vogel * In certain situations, a system BIOS may report that the PCIx maximum 6128cfa0ad2SJack F Vogel * memory read byte count (MMRBC) value is higher than than the actual 6138cfa0ad2SJack F Vogel * value. We check the PCIx command register with the current PCIx status 6148cfa0ad2SJack F Vogel * register. 6158cfa0ad2SJack F Vogel **/ 6168cfa0ad2SJack F Vogel void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw) 6178cfa0ad2SJack F Vogel { 6188cfa0ad2SJack F Vogel u16 cmd_mmrbc; 6198cfa0ad2SJack F Vogel u16 pcix_cmd; 6208cfa0ad2SJack F Vogel u16 pcix_stat_hi_word; 6218cfa0ad2SJack F Vogel u16 stat_mmrbc; 6228cfa0ad2SJack F Vogel 6238cfa0ad2SJack F Vogel DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic"); 6248cfa0ad2SJack F Vogel 6258cfa0ad2SJack F Vogel /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */ 6268cfa0ad2SJack F Vogel if (hw->bus.type != e1000_bus_type_pcix) 6278cfa0ad2SJack F Vogel return; 6288cfa0ad2SJack F Vogel 6298cfa0ad2SJack F Vogel e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 6308cfa0ad2SJack F Vogel e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); 6318cfa0ad2SJack F Vogel cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >> 6328cfa0ad2SJack F Vogel PCIX_COMMAND_MMRBC_SHIFT; 6338cfa0ad2SJack F Vogel stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 6348cfa0ad2SJack F Vogel PCIX_STATUS_HI_MMRBC_SHIFT; 6358cfa0ad2SJack F Vogel if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 6368cfa0ad2SJack F Vogel stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 6378cfa0ad2SJack F Vogel if (cmd_mmrbc > stat_mmrbc) { 6388cfa0ad2SJack F Vogel pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK; 6398cfa0ad2SJack F Vogel pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 6408cfa0ad2SJack F Vogel e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 6418cfa0ad2SJack F Vogel } 6428cfa0ad2SJack F Vogel } 6438cfa0ad2SJack F Vogel 6448cfa0ad2SJack F Vogel /** 6458cfa0ad2SJack F Vogel * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters 6468cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 6478cfa0ad2SJack F Vogel * 6488cfa0ad2SJack F Vogel * Clears the base hardware counters by reading the counter registers. 6498cfa0ad2SJack F Vogel **/ 6508cfa0ad2SJack F Vogel void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw) 6518cfa0ad2SJack F Vogel { 6528cfa0ad2SJack F Vogel DEBUGFUNC("e1000_clear_hw_cntrs_base_generic"); 6538cfa0ad2SJack F Vogel 654daf9197cSJack F Vogel E1000_READ_REG(hw, E1000_CRCERRS); 655daf9197cSJack F Vogel E1000_READ_REG(hw, E1000_SYMERRS); 656daf9197cSJack F Vogel E1000_READ_REG(hw, E1000_MPC); 657daf9197cSJack F Vogel E1000_READ_REG(hw, E1000_SCC); 658daf9197cSJack F Vogel E1000_READ_REG(hw, E1000_ECOL); 659daf9197cSJack F Vogel E1000_READ_REG(hw, E1000_MCC); 660daf9197cSJack F Vogel E1000_READ_REG(hw, E1000_LATECOL); 661daf9197cSJack F Vogel E1000_READ_REG(hw, E1000_COLC); 662daf9197cSJack F Vogel E1000_READ_REG(hw, E1000_DC); 663daf9197cSJack F Vogel E1000_READ_REG(hw, E1000_SEC); 664daf9197cSJack F Vogel E1000_READ_REG(hw, E1000_RLEC); 665daf9197cSJack F Vogel E1000_READ_REG(hw, E1000_XONRXC); 666daf9197cSJack F Vogel E1000_READ_REG(hw, E1000_XONTXC); 667daf9197cSJack F Vogel E1000_READ_REG(hw, E1000_XOFFRXC); 668daf9197cSJack F Vogel E1000_READ_REG(hw, E1000_XOFFTXC); 669daf9197cSJack F Vogel E1000_READ_REG(hw, E1000_FCRUC); 670daf9197cSJack F Vogel E1000_READ_REG(hw, E1000_GPRC); 671daf9197cSJack F Vogel E1000_READ_REG(hw, E1000_BPRC); 672daf9197cSJack F Vogel E1000_READ_REG(hw, E1000_MPRC); 673daf9197cSJack F Vogel E1000_READ_REG(hw, E1000_GPTC); 674daf9197cSJack F Vogel E1000_READ_REG(hw, E1000_GORCL); 675daf9197cSJack F Vogel E1000_READ_REG(hw, E1000_GORCH); 676daf9197cSJack F Vogel E1000_READ_REG(hw, E1000_GOTCL); 677daf9197cSJack F Vogel E1000_READ_REG(hw, E1000_GOTCH); 678daf9197cSJack F Vogel E1000_READ_REG(hw, E1000_RNBC); 679daf9197cSJack F Vogel E1000_READ_REG(hw, E1000_RUC); 680daf9197cSJack F Vogel E1000_READ_REG(hw, E1000_RFC); 681daf9197cSJack F Vogel E1000_READ_REG(hw, E1000_ROC); 682daf9197cSJack F Vogel E1000_READ_REG(hw, E1000_RJC); 683daf9197cSJack F Vogel E1000_READ_REG(hw, E1000_TORL); 684daf9197cSJack F Vogel E1000_READ_REG(hw, E1000_TORH); 685daf9197cSJack F Vogel E1000_READ_REG(hw, E1000_TOTL); 686daf9197cSJack F Vogel E1000_READ_REG(hw, E1000_TOTH); 687daf9197cSJack F Vogel E1000_READ_REG(hw, E1000_TPR); 688daf9197cSJack F Vogel E1000_READ_REG(hw, E1000_TPT); 689daf9197cSJack F Vogel E1000_READ_REG(hw, E1000_MPTC); 690daf9197cSJack F Vogel E1000_READ_REG(hw, E1000_BPTC); 6918cfa0ad2SJack F Vogel } 6928cfa0ad2SJack F Vogel 6938cfa0ad2SJack F Vogel /** 6948cfa0ad2SJack F Vogel * e1000_check_for_copper_link_generic - Check for link (Copper) 6958cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 6968cfa0ad2SJack F Vogel * 6978cfa0ad2SJack F Vogel * Checks to see of the link status of the hardware has changed. If a 6988cfa0ad2SJack F Vogel * change in link status has been detected, then we read the PHY registers 6998cfa0ad2SJack F Vogel * to get the current speed/duplex if link exists. 7008cfa0ad2SJack F Vogel **/ 7018cfa0ad2SJack F Vogel s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw) 7028cfa0ad2SJack F Vogel { 7038cfa0ad2SJack F Vogel struct e1000_mac_info *mac = &hw->mac; 7048cfa0ad2SJack F Vogel s32 ret_val; 7058cfa0ad2SJack F Vogel bool link; 7068cfa0ad2SJack F Vogel 7078cfa0ad2SJack F Vogel DEBUGFUNC("e1000_check_for_copper_link"); 7088cfa0ad2SJack F Vogel 7098cfa0ad2SJack F Vogel /* 7108cfa0ad2SJack F Vogel * We only want to go out to the PHY registers to see if Auto-Neg 7118cfa0ad2SJack F Vogel * has completed and/or if our link status has changed. The 7128cfa0ad2SJack F Vogel * get_link_status flag is set upon receiving a Link Status 7138cfa0ad2SJack F Vogel * Change or Rx Sequence Error interrupt. 7148cfa0ad2SJack F Vogel */ 7158cfa0ad2SJack F Vogel if (!mac->get_link_status) { 7168cfa0ad2SJack F Vogel ret_val = E1000_SUCCESS; 7178cfa0ad2SJack F Vogel goto out; 7188cfa0ad2SJack F Vogel } 7198cfa0ad2SJack F Vogel 7208cfa0ad2SJack F Vogel /* 7218cfa0ad2SJack F Vogel * First we want to see if the MII Status Register reports 7228cfa0ad2SJack F Vogel * link. If so, then we want to get the current speed/duplex 7238cfa0ad2SJack F Vogel * of the PHY. 7248cfa0ad2SJack F Vogel */ 7258cfa0ad2SJack F Vogel ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 7268cfa0ad2SJack F Vogel if (ret_val) 7278cfa0ad2SJack F Vogel goto out; 7288cfa0ad2SJack F Vogel 7298cfa0ad2SJack F Vogel if (!link) 7308cfa0ad2SJack F Vogel goto out; /* No link detected */ 7318cfa0ad2SJack F Vogel 7328cfa0ad2SJack F Vogel mac->get_link_status = FALSE; 7338cfa0ad2SJack F Vogel 7348cfa0ad2SJack F Vogel /* 7358cfa0ad2SJack F Vogel * Check if there was DownShift, must be checked 7368cfa0ad2SJack F Vogel * immediately after link-up 7378cfa0ad2SJack F Vogel */ 7388cfa0ad2SJack F Vogel e1000_check_downshift_generic(hw); 7398cfa0ad2SJack F Vogel 7408cfa0ad2SJack F Vogel /* 7418cfa0ad2SJack F Vogel * If we are forcing speed/duplex, then we simply return since 7428cfa0ad2SJack F Vogel * we have already determined whether we have link or not. 7438cfa0ad2SJack F Vogel */ 7448cfa0ad2SJack F Vogel if (!mac->autoneg) { 7458cfa0ad2SJack F Vogel ret_val = -E1000_ERR_CONFIG; 7468cfa0ad2SJack F Vogel goto out; 7478cfa0ad2SJack F Vogel } 7488cfa0ad2SJack F Vogel 7498cfa0ad2SJack F Vogel /* 7508cfa0ad2SJack F Vogel * Auto-Neg is enabled. Auto Speed Detection takes care 7518cfa0ad2SJack F Vogel * of MAC speed/duplex configuration. So we only need to 7528cfa0ad2SJack F Vogel * configure Collision Distance in the MAC. 7538cfa0ad2SJack F Vogel */ 754a69ed8dfSJack F Vogel mac->ops.config_collision_dist(hw); 7558cfa0ad2SJack F Vogel 7568cfa0ad2SJack F Vogel /* 7578cfa0ad2SJack F Vogel * Configure Flow Control now that Auto-Neg has completed. 7588cfa0ad2SJack F Vogel * First, we need to restore the desired flow control 7598cfa0ad2SJack F Vogel * settings because we may have had to re-autoneg with a 7608cfa0ad2SJack F Vogel * different link partner. 7618cfa0ad2SJack F Vogel */ 7628cfa0ad2SJack F Vogel ret_val = e1000_config_fc_after_link_up_generic(hw); 763daf9197cSJack F Vogel if (ret_val) 7648cfa0ad2SJack F Vogel DEBUGOUT("Error configuring flow control\n"); 7658cfa0ad2SJack F Vogel 7668cfa0ad2SJack F Vogel out: 7678cfa0ad2SJack F Vogel return ret_val; 7688cfa0ad2SJack F Vogel } 7698cfa0ad2SJack F Vogel 7708cfa0ad2SJack F Vogel /** 7718cfa0ad2SJack F Vogel * e1000_check_for_fiber_link_generic - Check for link (Fiber) 7728cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 7738cfa0ad2SJack F Vogel * 7748cfa0ad2SJack F Vogel * Checks for link up on the hardware. If link is not up and we have 7758cfa0ad2SJack F Vogel * a signal, then we need to force link up. 7768cfa0ad2SJack F Vogel **/ 7778cfa0ad2SJack F Vogel s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw) 7788cfa0ad2SJack F Vogel { 7798cfa0ad2SJack F Vogel struct e1000_mac_info *mac = &hw->mac; 7808cfa0ad2SJack F Vogel u32 rxcw; 7818cfa0ad2SJack F Vogel u32 ctrl; 7828cfa0ad2SJack F Vogel u32 status; 7838cfa0ad2SJack F Vogel s32 ret_val = E1000_SUCCESS; 7848cfa0ad2SJack F Vogel 7858cfa0ad2SJack F Vogel DEBUGFUNC("e1000_check_for_fiber_link_generic"); 7868cfa0ad2SJack F Vogel 7878cfa0ad2SJack F Vogel ctrl = E1000_READ_REG(hw, E1000_CTRL); 7888cfa0ad2SJack F Vogel status = E1000_READ_REG(hw, E1000_STATUS); 7898cfa0ad2SJack F Vogel rxcw = E1000_READ_REG(hw, E1000_RXCW); 7908cfa0ad2SJack F Vogel 7918cfa0ad2SJack F Vogel /* 7928cfa0ad2SJack F Vogel * If we don't have link (auto-negotiation failed or link partner 7938cfa0ad2SJack F Vogel * cannot auto-negotiate), the cable is plugged in (we have signal), 7948cfa0ad2SJack F Vogel * and our link partner is not trying to auto-negotiate with us (we 7958cfa0ad2SJack F Vogel * are receiving idles or data), we need to force link up. We also 7968cfa0ad2SJack F Vogel * need to give auto-negotiation time to complete, in case the cable 7978cfa0ad2SJack F Vogel * was just plugged in. The autoneg_failed flag does this. 7988cfa0ad2SJack F Vogel */ 7998cfa0ad2SJack F Vogel /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 8008cfa0ad2SJack F Vogel if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) && 8018cfa0ad2SJack F Vogel (!(rxcw & E1000_RXCW_C))) { 8028cfa0ad2SJack F Vogel if (mac->autoneg_failed == 0) { 8038cfa0ad2SJack F Vogel mac->autoneg_failed = 1; 8048cfa0ad2SJack F Vogel goto out; 8058cfa0ad2SJack F Vogel } 806f0ecc46dSJack F Vogel DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 8078cfa0ad2SJack F Vogel 8088cfa0ad2SJack F Vogel /* Disable auto-negotiation in the TXCW register */ 8098cfa0ad2SJack F Vogel E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 8108cfa0ad2SJack F Vogel 8118cfa0ad2SJack F Vogel /* Force link-up and also force full-duplex. */ 8128cfa0ad2SJack F Vogel ctrl = E1000_READ_REG(hw, E1000_CTRL); 8138cfa0ad2SJack F Vogel ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 8148cfa0ad2SJack F Vogel E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 8158cfa0ad2SJack F Vogel 8168cfa0ad2SJack F Vogel /* Configure Flow Control after forcing link up. */ 8178cfa0ad2SJack F Vogel ret_val = e1000_config_fc_after_link_up_generic(hw); 8188cfa0ad2SJack F Vogel if (ret_val) { 8198cfa0ad2SJack F Vogel DEBUGOUT("Error configuring flow control\n"); 8208cfa0ad2SJack F Vogel goto out; 8218cfa0ad2SJack F Vogel } 8228cfa0ad2SJack F Vogel } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 8238cfa0ad2SJack F Vogel /* 8248cfa0ad2SJack F Vogel * If we are forcing link and we are receiving /C/ ordered 8258cfa0ad2SJack F Vogel * sets, re-enable auto-negotiation in the TXCW register 8268cfa0ad2SJack F Vogel * and disable forced link in the Device Control register 8278cfa0ad2SJack F Vogel * in an attempt to auto-negotiate with our link partner. 8288cfa0ad2SJack F Vogel */ 829f0ecc46dSJack F Vogel DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 8308cfa0ad2SJack F Vogel E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 8318cfa0ad2SJack F Vogel E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 8328cfa0ad2SJack F Vogel 8338cfa0ad2SJack F Vogel mac->serdes_has_link = TRUE; 8348cfa0ad2SJack F Vogel } 8358cfa0ad2SJack F Vogel 8368cfa0ad2SJack F Vogel out: 8378cfa0ad2SJack F Vogel return ret_val; 8388cfa0ad2SJack F Vogel } 8398cfa0ad2SJack F Vogel 8408cfa0ad2SJack F Vogel /** 8418cfa0ad2SJack F Vogel * e1000_check_for_serdes_link_generic - Check for link (Serdes) 8428cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 8438cfa0ad2SJack F Vogel * 8448cfa0ad2SJack F Vogel * Checks for link up on the hardware. If link is not up and we have 8458cfa0ad2SJack F Vogel * a signal, then we need to force link up. 8468cfa0ad2SJack F Vogel **/ 8478cfa0ad2SJack F Vogel s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 8488cfa0ad2SJack F Vogel { 8498cfa0ad2SJack F Vogel struct e1000_mac_info *mac = &hw->mac; 8508cfa0ad2SJack F Vogel u32 rxcw; 8518cfa0ad2SJack F Vogel u32 ctrl; 8528cfa0ad2SJack F Vogel u32 status; 8538cfa0ad2SJack F Vogel s32 ret_val = E1000_SUCCESS; 8548cfa0ad2SJack F Vogel 8558cfa0ad2SJack F Vogel DEBUGFUNC("e1000_check_for_serdes_link_generic"); 8568cfa0ad2SJack F Vogel 8578cfa0ad2SJack F Vogel ctrl = E1000_READ_REG(hw, E1000_CTRL); 8588cfa0ad2SJack F Vogel status = E1000_READ_REG(hw, E1000_STATUS); 8598cfa0ad2SJack F Vogel rxcw = E1000_READ_REG(hw, E1000_RXCW); 8608cfa0ad2SJack F Vogel 8618cfa0ad2SJack F Vogel /* 8628cfa0ad2SJack F Vogel * If we don't have link (auto-negotiation failed or link partner 8638cfa0ad2SJack F Vogel * cannot auto-negotiate), and our link partner is not trying to 8648cfa0ad2SJack F Vogel * auto-negotiate with us (we are receiving idles or data), 8658cfa0ad2SJack F Vogel * we need to force link up. We also need to give auto-negotiation 8668cfa0ad2SJack F Vogel * time to complete. 8678cfa0ad2SJack F Vogel */ 8688cfa0ad2SJack F Vogel /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 8698cfa0ad2SJack F Vogel if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 8708cfa0ad2SJack F Vogel if (mac->autoneg_failed == 0) { 8718cfa0ad2SJack F Vogel mac->autoneg_failed = 1; 8728cfa0ad2SJack F Vogel goto out; 8738cfa0ad2SJack F Vogel } 874f0ecc46dSJack F Vogel DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 8758cfa0ad2SJack F Vogel 8768cfa0ad2SJack F Vogel /* Disable auto-negotiation in the TXCW register */ 8778cfa0ad2SJack F Vogel E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 8788cfa0ad2SJack F Vogel 8798cfa0ad2SJack F Vogel /* Force link-up and also force full-duplex. */ 8808cfa0ad2SJack F Vogel ctrl = E1000_READ_REG(hw, E1000_CTRL); 8818cfa0ad2SJack F Vogel ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 8828cfa0ad2SJack F Vogel E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 8838cfa0ad2SJack F Vogel 8848cfa0ad2SJack F Vogel /* Configure Flow Control after forcing link up. */ 8858cfa0ad2SJack F Vogel ret_val = e1000_config_fc_after_link_up_generic(hw); 8868cfa0ad2SJack F Vogel if (ret_val) { 8878cfa0ad2SJack F Vogel DEBUGOUT("Error configuring flow control\n"); 8888cfa0ad2SJack F Vogel goto out; 8898cfa0ad2SJack F Vogel } 8908cfa0ad2SJack F Vogel } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 8918cfa0ad2SJack F Vogel /* 8928cfa0ad2SJack F Vogel * If we are forcing link and we are receiving /C/ ordered 8938cfa0ad2SJack F Vogel * sets, re-enable auto-negotiation in the TXCW register 8948cfa0ad2SJack F Vogel * and disable forced link in the Device Control register 8958cfa0ad2SJack F Vogel * in an attempt to auto-negotiate with our link partner. 8968cfa0ad2SJack F Vogel */ 897f0ecc46dSJack F Vogel DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 8988cfa0ad2SJack F Vogel E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 8998cfa0ad2SJack F Vogel E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 9008cfa0ad2SJack F Vogel 9018cfa0ad2SJack F Vogel mac->serdes_has_link = TRUE; 9028cfa0ad2SJack F Vogel } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { 9038cfa0ad2SJack F Vogel /* 9048cfa0ad2SJack F Vogel * If we force link for non-auto-negotiation switch, check 9058cfa0ad2SJack F Vogel * link status based on MAC synchronization for internal 9068cfa0ad2SJack F Vogel * serdes media type. 9078cfa0ad2SJack F Vogel */ 9088cfa0ad2SJack F Vogel /* SYNCH bit and IV bit are sticky. */ 9098cfa0ad2SJack F Vogel usec_delay(10); 9108cfa0ad2SJack F Vogel rxcw = E1000_READ_REG(hw, E1000_RXCW); 9118cfa0ad2SJack F Vogel if (rxcw & E1000_RXCW_SYNCH) { 9128cfa0ad2SJack F Vogel if (!(rxcw & E1000_RXCW_IV)) { 9138cfa0ad2SJack F Vogel mac->serdes_has_link = TRUE; 9148cfa0ad2SJack F Vogel DEBUGOUT("SERDES: Link up - forced.\n"); 9158cfa0ad2SJack F Vogel } 9168cfa0ad2SJack F Vogel } else { 9178cfa0ad2SJack F Vogel mac->serdes_has_link = FALSE; 9188cfa0ad2SJack F Vogel DEBUGOUT("SERDES: Link down - force failed.\n"); 9198cfa0ad2SJack F Vogel } 9208cfa0ad2SJack F Vogel } 9218cfa0ad2SJack F Vogel 9228cfa0ad2SJack F Vogel if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { 9238cfa0ad2SJack F Vogel status = E1000_READ_REG(hw, E1000_STATUS); 9248cfa0ad2SJack F Vogel if (status & E1000_STATUS_LU) { 9258cfa0ad2SJack F Vogel /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 9268cfa0ad2SJack F Vogel usec_delay(10); 9278cfa0ad2SJack F Vogel rxcw = E1000_READ_REG(hw, E1000_RXCW); 9288cfa0ad2SJack F Vogel if (rxcw & E1000_RXCW_SYNCH) { 9298cfa0ad2SJack F Vogel if (!(rxcw & E1000_RXCW_IV)) { 9308cfa0ad2SJack F Vogel mac->serdes_has_link = TRUE; 9314dab5c37SJack F Vogel DEBUGOUT("SERDES: Link up - autoneg completed successfully.\n"); 9328cfa0ad2SJack F Vogel } else { 9338cfa0ad2SJack F Vogel mac->serdes_has_link = FALSE; 9344dab5c37SJack F Vogel DEBUGOUT("SERDES: Link down - invalid codewords detected in autoneg.\n"); 9358cfa0ad2SJack F Vogel } 9368cfa0ad2SJack F Vogel } else { 9378cfa0ad2SJack F Vogel mac->serdes_has_link = FALSE; 9388cfa0ad2SJack F Vogel DEBUGOUT("SERDES: Link down - no sync.\n"); 9398cfa0ad2SJack F Vogel } 9408cfa0ad2SJack F Vogel } else { 9418cfa0ad2SJack F Vogel mac->serdes_has_link = FALSE; 9428cfa0ad2SJack F Vogel DEBUGOUT("SERDES: Link down - autoneg failed\n"); 9438cfa0ad2SJack F Vogel } 9448cfa0ad2SJack F Vogel } 9458cfa0ad2SJack F Vogel 9468cfa0ad2SJack F Vogel out: 9478cfa0ad2SJack F Vogel return ret_val; 9488cfa0ad2SJack F Vogel } 9498cfa0ad2SJack F Vogel 9508cfa0ad2SJack F Vogel /** 9518cfa0ad2SJack F Vogel * e1000_setup_link_generic - Setup flow control and link settings 9528cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 9538cfa0ad2SJack F Vogel * 9548cfa0ad2SJack F Vogel * Determines which flow control settings to use, then configures flow 9558cfa0ad2SJack F Vogel * control. Calls the appropriate media-specific link configuration 9568cfa0ad2SJack F Vogel * function. Assuming the adapter has a valid link partner, a valid link 9578cfa0ad2SJack F Vogel * should be established. Assumes the hardware has previously been reset 9588cfa0ad2SJack F Vogel * and the transmitter and receiver are not enabled. 9598cfa0ad2SJack F Vogel **/ 9608cfa0ad2SJack F Vogel s32 e1000_setup_link_generic(struct e1000_hw *hw) 9618cfa0ad2SJack F Vogel { 9628cfa0ad2SJack F Vogel s32 ret_val = E1000_SUCCESS; 9638cfa0ad2SJack F Vogel 9648cfa0ad2SJack F Vogel DEBUGFUNC("e1000_setup_link_generic"); 9658cfa0ad2SJack F Vogel 9668cfa0ad2SJack F Vogel /* 9678cfa0ad2SJack F Vogel * In the case of the phy reset being blocked, we already have a link. 9688cfa0ad2SJack F Vogel * We do not need to set it up again. 9698cfa0ad2SJack F Vogel */ 9704edd8523SJack F Vogel if (e1000_check_reset_block(hw)) 9718cfa0ad2SJack F Vogel goto out; 9728cfa0ad2SJack F Vogel 9738cfa0ad2SJack F Vogel /* 974daf9197cSJack F Vogel * If requested flow control is set to default, set flow control 975daf9197cSJack F Vogel * based on the EEPROM flow control settings. 9768cfa0ad2SJack F Vogel */ 977daf9197cSJack F Vogel if (hw->fc.requested_mode == e1000_fc_default) { 9788cfa0ad2SJack F Vogel ret_val = e1000_set_default_fc_generic(hw); 9798cfa0ad2SJack F Vogel if (ret_val) 9808cfa0ad2SJack F Vogel goto out; 9818cfa0ad2SJack F Vogel } 9828cfa0ad2SJack F Vogel 9838cfa0ad2SJack F Vogel /* 984daf9197cSJack F Vogel * Save off the requested flow control mode for use later. Depending 985daf9197cSJack F Vogel * on the link partner's capabilities, we may or may not use this mode. 9868cfa0ad2SJack F Vogel */ 987daf9197cSJack F Vogel hw->fc.current_mode = hw->fc.requested_mode; 9888cfa0ad2SJack F Vogel 989daf9197cSJack F Vogel DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 990daf9197cSJack F Vogel hw->fc.current_mode); 9918cfa0ad2SJack F Vogel 9928cfa0ad2SJack F Vogel /* Call the necessary media_type subroutine to configure the link. */ 9938cfa0ad2SJack F Vogel ret_val = hw->mac.ops.setup_physical_interface(hw); 9948cfa0ad2SJack F Vogel if (ret_val) 9958cfa0ad2SJack F Vogel goto out; 9968cfa0ad2SJack F Vogel 9978cfa0ad2SJack F Vogel /* 9988cfa0ad2SJack F Vogel * Initialize the flow control address, type, and PAUSE timer 9998cfa0ad2SJack F Vogel * registers to their default values. This is done even if flow 10008cfa0ad2SJack F Vogel * control is disabled, because it does not hurt anything to 10018cfa0ad2SJack F Vogel * initialize these registers. 10028cfa0ad2SJack F Vogel */ 10038cfa0ad2SJack F Vogel DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 10048cfa0ad2SJack F Vogel E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 10058cfa0ad2SJack F Vogel E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 10068cfa0ad2SJack F Vogel E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 10078cfa0ad2SJack F Vogel 10088cfa0ad2SJack F Vogel E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 10098cfa0ad2SJack F Vogel 10108cfa0ad2SJack F Vogel ret_val = e1000_set_fc_watermarks_generic(hw); 10118cfa0ad2SJack F Vogel 10128cfa0ad2SJack F Vogel out: 10138cfa0ad2SJack F Vogel return ret_val; 10148cfa0ad2SJack F Vogel } 10158cfa0ad2SJack F Vogel 10168cfa0ad2SJack F Vogel /** 10178cfa0ad2SJack F Vogel * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes 10188cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 10198cfa0ad2SJack F Vogel * 10208cfa0ad2SJack F Vogel * Configures collision distance and flow control for fiber and serdes 10218cfa0ad2SJack F Vogel * links. Upon successful setup, poll for link. 10228cfa0ad2SJack F Vogel **/ 10238cfa0ad2SJack F Vogel s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) 10248cfa0ad2SJack F Vogel { 1025a69ed8dfSJack F Vogel struct e1000_mac_info *mac = &hw->mac; 10268cfa0ad2SJack F Vogel u32 ctrl; 10278cfa0ad2SJack F Vogel s32 ret_val = E1000_SUCCESS; 10288cfa0ad2SJack F Vogel 10298cfa0ad2SJack F Vogel DEBUGFUNC("e1000_setup_fiber_serdes_link_generic"); 10308cfa0ad2SJack F Vogel 10318cfa0ad2SJack F Vogel ctrl = E1000_READ_REG(hw, E1000_CTRL); 10328cfa0ad2SJack F Vogel 10338cfa0ad2SJack F Vogel /* Take the link out of reset */ 10348cfa0ad2SJack F Vogel ctrl &= ~E1000_CTRL_LRST; 10358cfa0ad2SJack F Vogel 1036a69ed8dfSJack F Vogel mac->ops.config_collision_dist(hw); 10378cfa0ad2SJack F Vogel 10388cfa0ad2SJack F Vogel ret_val = e1000_commit_fc_settings_generic(hw); 10398cfa0ad2SJack F Vogel if (ret_val) 10408cfa0ad2SJack F Vogel goto out; 10418cfa0ad2SJack F Vogel 10428cfa0ad2SJack F Vogel /* 10438cfa0ad2SJack F Vogel * Since auto-negotiation is enabled, take the link out of reset (the 10448cfa0ad2SJack F Vogel * link will be in reset, because we previously reset the chip). This 10458cfa0ad2SJack F Vogel * will restart auto-negotiation. If auto-negotiation is successful 10468cfa0ad2SJack F Vogel * then the link-up status bit will be set and the flow control enable 10478cfa0ad2SJack F Vogel * bits (RFCE and TFCE) will be set according to their negotiated value. 10488cfa0ad2SJack F Vogel */ 10498cfa0ad2SJack F Vogel DEBUGOUT("Auto-negotiation enabled\n"); 10508cfa0ad2SJack F Vogel 10518cfa0ad2SJack F Vogel E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 10528cfa0ad2SJack F Vogel E1000_WRITE_FLUSH(hw); 10538cfa0ad2SJack F Vogel msec_delay(1); 10548cfa0ad2SJack F Vogel 10558cfa0ad2SJack F Vogel /* 10568cfa0ad2SJack F Vogel * For these adapters, the SW definable pin 1 is set when the optics 10578cfa0ad2SJack F Vogel * detect a signal. If we have a signal, then poll for a "Link-Up" 10588cfa0ad2SJack F Vogel * indication. 10598cfa0ad2SJack F Vogel */ 10608cfa0ad2SJack F Vogel if (hw->phy.media_type == e1000_media_type_internal_serdes || 10618cfa0ad2SJack F Vogel (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 10628cfa0ad2SJack F Vogel ret_val = e1000_poll_fiber_serdes_link_generic(hw); 10638cfa0ad2SJack F Vogel } else { 10648cfa0ad2SJack F Vogel DEBUGOUT("No signal detected\n"); 10658cfa0ad2SJack F Vogel } 10668cfa0ad2SJack F Vogel 10678cfa0ad2SJack F Vogel out: 10688cfa0ad2SJack F Vogel return ret_val; 10698cfa0ad2SJack F Vogel } 10708cfa0ad2SJack F Vogel 10718cfa0ad2SJack F Vogel /** 10728cfa0ad2SJack F Vogel * e1000_config_collision_dist_generic - Configure collision distance 10738cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 10748cfa0ad2SJack F Vogel * 10758cfa0ad2SJack F Vogel * Configures the collision distance to the default value and is used 1076a69ed8dfSJack F Vogel * during link setup. 10778cfa0ad2SJack F Vogel **/ 10788cfa0ad2SJack F Vogel void e1000_config_collision_dist_generic(struct e1000_hw *hw) 10798cfa0ad2SJack F Vogel { 10808cfa0ad2SJack F Vogel u32 tctl; 10818cfa0ad2SJack F Vogel 10828cfa0ad2SJack F Vogel DEBUGFUNC("e1000_config_collision_dist_generic"); 10838cfa0ad2SJack F Vogel 10848cfa0ad2SJack F Vogel tctl = E1000_READ_REG(hw, E1000_TCTL); 10858cfa0ad2SJack F Vogel 10868cfa0ad2SJack F Vogel tctl &= ~E1000_TCTL_COLD; 10878cfa0ad2SJack F Vogel tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 10888cfa0ad2SJack F Vogel 10898cfa0ad2SJack F Vogel E1000_WRITE_REG(hw, E1000_TCTL, tctl); 10908cfa0ad2SJack F Vogel E1000_WRITE_FLUSH(hw); 10918cfa0ad2SJack F Vogel } 10928cfa0ad2SJack F Vogel 10938cfa0ad2SJack F Vogel /** 10948cfa0ad2SJack F Vogel * e1000_poll_fiber_serdes_link_generic - Poll for link up 10958cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 10968cfa0ad2SJack F Vogel * 10978cfa0ad2SJack F Vogel * Polls for link up by reading the status register, if link fails to come 10988cfa0ad2SJack F Vogel * up with auto-negotiation, then the link is forced if a signal is detected. 10998cfa0ad2SJack F Vogel **/ 1100b60688beSBjoern A. Zeeb s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) 11018cfa0ad2SJack F Vogel { 11028cfa0ad2SJack F Vogel struct e1000_mac_info *mac = &hw->mac; 11038cfa0ad2SJack F Vogel u32 i, status; 11048cfa0ad2SJack F Vogel s32 ret_val = E1000_SUCCESS; 11058cfa0ad2SJack F Vogel 11068cfa0ad2SJack F Vogel DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); 11078cfa0ad2SJack F Vogel 11088cfa0ad2SJack F Vogel /* 11098cfa0ad2SJack F Vogel * If we have a signal (the cable is plugged in, or assumed TRUE for 11108cfa0ad2SJack F Vogel * serdes media) then poll for a "Link-Up" indication in the Device 11118cfa0ad2SJack F Vogel * Status Register. Time-out if a link isn't seen in 500 milliseconds 11128cfa0ad2SJack F Vogel * seconds (Auto-negotiation should complete in less than 500 11138cfa0ad2SJack F Vogel * milliseconds even if the other end is doing it in SW). 11148cfa0ad2SJack F Vogel */ 11158cfa0ad2SJack F Vogel for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 11168cfa0ad2SJack F Vogel msec_delay(10); 11178cfa0ad2SJack F Vogel status = E1000_READ_REG(hw, E1000_STATUS); 11188cfa0ad2SJack F Vogel if (status & E1000_STATUS_LU) 11198cfa0ad2SJack F Vogel break; 11208cfa0ad2SJack F Vogel } 11218cfa0ad2SJack F Vogel if (i == FIBER_LINK_UP_LIMIT) { 11228cfa0ad2SJack F Vogel DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 11238cfa0ad2SJack F Vogel mac->autoneg_failed = 1; 11248cfa0ad2SJack F Vogel /* 11258cfa0ad2SJack F Vogel * AutoNeg failed to achieve a link, so we'll call 11268cfa0ad2SJack F Vogel * mac->check_for_link. This routine will force the 11278cfa0ad2SJack F Vogel * link up if we detect a signal. This will allow us to 11288cfa0ad2SJack F Vogel * communicate with non-autonegotiating link partners. 11298cfa0ad2SJack F Vogel */ 1130a69ed8dfSJack F Vogel ret_val = mac->ops.check_for_link(hw); 11318cfa0ad2SJack F Vogel if (ret_val) { 11328cfa0ad2SJack F Vogel DEBUGOUT("Error while checking for link\n"); 11338cfa0ad2SJack F Vogel goto out; 11348cfa0ad2SJack F Vogel } 11358cfa0ad2SJack F Vogel mac->autoneg_failed = 0; 11368cfa0ad2SJack F Vogel } else { 11378cfa0ad2SJack F Vogel mac->autoneg_failed = 0; 11388cfa0ad2SJack F Vogel DEBUGOUT("Valid Link Found\n"); 11398cfa0ad2SJack F Vogel } 11408cfa0ad2SJack F Vogel 11418cfa0ad2SJack F Vogel out: 11428cfa0ad2SJack F Vogel return ret_val; 11438cfa0ad2SJack F Vogel } 11448cfa0ad2SJack F Vogel 11458cfa0ad2SJack F Vogel /** 11468cfa0ad2SJack F Vogel * e1000_commit_fc_settings_generic - Configure flow control 11478cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 11488cfa0ad2SJack F Vogel * 11498cfa0ad2SJack F Vogel * Write the flow control settings to the Transmit Config Word Register (TXCW) 11508cfa0ad2SJack F Vogel * base on the flow control settings in e1000_mac_info. 11518cfa0ad2SJack F Vogel **/ 1152b60688beSBjoern A. Zeeb s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) 11538cfa0ad2SJack F Vogel { 11548cfa0ad2SJack F Vogel struct e1000_mac_info *mac = &hw->mac; 11558cfa0ad2SJack F Vogel u32 txcw; 11568cfa0ad2SJack F Vogel s32 ret_val = E1000_SUCCESS; 11578cfa0ad2SJack F Vogel 11588cfa0ad2SJack F Vogel DEBUGFUNC("e1000_commit_fc_settings_generic"); 11598cfa0ad2SJack F Vogel 11608cfa0ad2SJack F Vogel /* 11618cfa0ad2SJack F Vogel * Check for a software override of the flow control settings, and 11628cfa0ad2SJack F Vogel * setup the device accordingly. If auto-negotiation is enabled, then 11638cfa0ad2SJack F Vogel * software will have to set the "PAUSE" bits to the correct value in 11648cfa0ad2SJack F Vogel * the Transmit Config Word Register (TXCW) and re-start auto- 11658cfa0ad2SJack F Vogel * negotiation. However, if auto-negotiation is disabled, then 11668cfa0ad2SJack F Vogel * software will have to manually configure the two flow control enable 11678cfa0ad2SJack F Vogel * bits in the CTRL register. 11688cfa0ad2SJack F Vogel * 11698cfa0ad2SJack F Vogel * The possible values of the "fc" parameter are: 11708cfa0ad2SJack F Vogel * 0: Flow control is completely disabled 11718cfa0ad2SJack F Vogel * 1: Rx flow control is enabled (we can receive pause frames, 11728cfa0ad2SJack F Vogel * but not send pause frames). 11738cfa0ad2SJack F Vogel * 2: Tx flow control is enabled (we can send pause frames but we 11748cfa0ad2SJack F Vogel * do not support receiving pause frames). 11758cfa0ad2SJack F Vogel * 3: Both Rx and Tx flow control (symmetric) are enabled. 11768cfa0ad2SJack F Vogel */ 1177daf9197cSJack F Vogel switch (hw->fc.current_mode) { 11788cfa0ad2SJack F Vogel case e1000_fc_none: 11798cfa0ad2SJack F Vogel /* Flow control completely disabled by a software over-ride. */ 11808cfa0ad2SJack F Vogel txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 11818cfa0ad2SJack F Vogel break; 11828cfa0ad2SJack F Vogel case e1000_fc_rx_pause: 11838cfa0ad2SJack F Vogel /* 11848cfa0ad2SJack F Vogel * Rx Flow control is enabled and Tx Flow control is disabled 11858cfa0ad2SJack F Vogel * by a software over-ride. Since there really isn't a way to 11868cfa0ad2SJack F Vogel * advertise that we are capable of Rx Pause ONLY, we will 1187a69ed8dfSJack F Vogel * advertise that we support both symmetric and asymmetric Rx 11888cfa0ad2SJack F Vogel * PAUSE. Later, we will disable the adapter's ability to send 11898cfa0ad2SJack F Vogel * PAUSE frames. 11908cfa0ad2SJack F Vogel */ 11918cfa0ad2SJack F Vogel txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 11928cfa0ad2SJack F Vogel break; 11938cfa0ad2SJack F Vogel case e1000_fc_tx_pause: 11948cfa0ad2SJack F Vogel /* 11958cfa0ad2SJack F Vogel * Tx Flow control is enabled, and Rx Flow control is disabled, 11968cfa0ad2SJack F Vogel * by a software over-ride. 11978cfa0ad2SJack F Vogel */ 11988cfa0ad2SJack F Vogel txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 11998cfa0ad2SJack F Vogel break; 12008cfa0ad2SJack F Vogel case e1000_fc_full: 12018cfa0ad2SJack F Vogel /* 12028cfa0ad2SJack F Vogel * Flow control (both Rx and Tx) is enabled by a software 12038cfa0ad2SJack F Vogel * over-ride. 12048cfa0ad2SJack F Vogel */ 12058cfa0ad2SJack F Vogel txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 12068cfa0ad2SJack F Vogel break; 12078cfa0ad2SJack F Vogel default: 12088cfa0ad2SJack F Vogel DEBUGOUT("Flow control param set incorrectly\n"); 12098cfa0ad2SJack F Vogel ret_val = -E1000_ERR_CONFIG; 12108cfa0ad2SJack F Vogel goto out; 12118cfa0ad2SJack F Vogel break; 12128cfa0ad2SJack F Vogel } 12138cfa0ad2SJack F Vogel 12148cfa0ad2SJack F Vogel E1000_WRITE_REG(hw, E1000_TXCW, txcw); 12158cfa0ad2SJack F Vogel mac->txcw = txcw; 12168cfa0ad2SJack F Vogel 12178cfa0ad2SJack F Vogel out: 12188cfa0ad2SJack F Vogel return ret_val; 12198cfa0ad2SJack F Vogel } 12208cfa0ad2SJack F Vogel 12218cfa0ad2SJack F Vogel /** 12228cfa0ad2SJack F Vogel * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks 12238cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 12248cfa0ad2SJack F Vogel * 12258cfa0ad2SJack F Vogel * Sets the flow control high/low threshold (watermark) registers. If 12268cfa0ad2SJack F Vogel * flow control XON frame transmission is enabled, then set XON frame 12278cfa0ad2SJack F Vogel * transmission as well. 12288cfa0ad2SJack F Vogel **/ 12298cfa0ad2SJack F Vogel s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw) 12308cfa0ad2SJack F Vogel { 12318cfa0ad2SJack F Vogel u32 fcrtl = 0, fcrth = 0; 12328cfa0ad2SJack F Vogel 12338cfa0ad2SJack F Vogel DEBUGFUNC("e1000_set_fc_watermarks_generic"); 12348cfa0ad2SJack F Vogel 12358cfa0ad2SJack F Vogel /* 12368cfa0ad2SJack F Vogel * Set the flow control receive threshold registers. Normally, 12378cfa0ad2SJack F Vogel * these registers will be set to a default threshold that may be 12388cfa0ad2SJack F Vogel * adjusted later by the driver's runtime code. However, if the 12398cfa0ad2SJack F Vogel * ability to transmit pause frames is not enabled, then these 12408cfa0ad2SJack F Vogel * registers will be set to 0. 12418cfa0ad2SJack F Vogel */ 1242daf9197cSJack F Vogel if (hw->fc.current_mode & e1000_fc_tx_pause) { 12438cfa0ad2SJack F Vogel /* 12448cfa0ad2SJack F Vogel * We need to set up the Receive Threshold high and low water 12458cfa0ad2SJack F Vogel * marks as well as (optionally) enabling the transmission of 12468cfa0ad2SJack F Vogel * XON frames. 12478cfa0ad2SJack F Vogel */ 12488cfa0ad2SJack F Vogel fcrtl = hw->fc.low_water; 12498cfa0ad2SJack F Vogel if (hw->fc.send_xon) 12508cfa0ad2SJack F Vogel fcrtl |= E1000_FCRTL_XONE; 12518cfa0ad2SJack F Vogel 12528cfa0ad2SJack F Vogel fcrth = hw->fc.high_water; 12538cfa0ad2SJack F Vogel } 12548cfa0ad2SJack F Vogel E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); 12558cfa0ad2SJack F Vogel E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); 12568cfa0ad2SJack F Vogel 1257a69ed8dfSJack F Vogel return E1000_SUCCESS; 12588cfa0ad2SJack F Vogel } 12598cfa0ad2SJack F Vogel 12608cfa0ad2SJack F Vogel /** 12618cfa0ad2SJack F Vogel * e1000_set_default_fc_generic - Set flow control default values 12628cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 12638cfa0ad2SJack F Vogel * 12648cfa0ad2SJack F Vogel * Read the EEPROM for the default values for flow control and store the 12658cfa0ad2SJack F Vogel * values. 12668cfa0ad2SJack F Vogel **/ 1267b60688beSBjoern A. Zeeb s32 e1000_set_default_fc_generic(struct e1000_hw *hw) 12688cfa0ad2SJack F Vogel { 12698cfa0ad2SJack F Vogel s32 ret_val = E1000_SUCCESS; 12708cfa0ad2SJack F Vogel u16 nvm_data; 12718cfa0ad2SJack F Vogel 12728cfa0ad2SJack F Vogel DEBUGFUNC("e1000_set_default_fc_generic"); 12738cfa0ad2SJack F Vogel 12748cfa0ad2SJack F Vogel /* 12758cfa0ad2SJack F Vogel * Read and store word 0x0F of the EEPROM. This word contains bits 12768cfa0ad2SJack F Vogel * that determine the hardware's default PAUSE (flow control) mode, 12778cfa0ad2SJack F Vogel * a bit that determines whether the HW defaults to enabling or 12788cfa0ad2SJack F Vogel * disabling auto-negotiation, and the direction of the 12798cfa0ad2SJack F Vogel * SW defined pins. If there is no SW over-ride of the flow 12808cfa0ad2SJack F Vogel * control setting, then the variable hw->fc will 12818cfa0ad2SJack F Vogel * be initialized based on a value in the EEPROM. 12828cfa0ad2SJack F Vogel */ 12838cfa0ad2SJack F Vogel ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); 12848cfa0ad2SJack F Vogel 12858cfa0ad2SJack F Vogel if (ret_val) { 12868cfa0ad2SJack F Vogel DEBUGOUT("NVM Read Error\n"); 12878cfa0ad2SJack F Vogel goto out; 12888cfa0ad2SJack F Vogel } 12898cfa0ad2SJack F Vogel 12908cfa0ad2SJack F Vogel if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) 1291daf9197cSJack F Vogel hw->fc.requested_mode = e1000_fc_none; 12928cfa0ad2SJack F Vogel else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 12938cfa0ad2SJack F Vogel NVM_WORD0F_ASM_DIR) 1294daf9197cSJack F Vogel hw->fc.requested_mode = e1000_fc_tx_pause; 12958cfa0ad2SJack F Vogel else 1296daf9197cSJack F Vogel hw->fc.requested_mode = e1000_fc_full; 12978cfa0ad2SJack F Vogel 12988cfa0ad2SJack F Vogel out: 12998cfa0ad2SJack F Vogel return ret_val; 13008cfa0ad2SJack F Vogel } 13018cfa0ad2SJack F Vogel 13028cfa0ad2SJack F Vogel /** 13038cfa0ad2SJack F Vogel * e1000_force_mac_fc_generic - Force the MAC's flow control settings 13048cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 13058cfa0ad2SJack F Vogel * 13068cfa0ad2SJack F Vogel * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 13078cfa0ad2SJack F Vogel * device control register to reflect the adapter settings. TFCE and RFCE 13088cfa0ad2SJack F Vogel * need to be explicitly set by software when a copper PHY is used because 13098cfa0ad2SJack F Vogel * autonegotiation is managed by the PHY rather than the MAC. Software must 13108cfa0ad2SJack F Vogel * also configure these bits when link is forced on a fiber connection. 13118cfa0ad2SJack F Vogel **/ 13128cfa0ad2SJack F Vogel s32 e1000_force_mac_fc_generic(struct e1000_hw *hw) 13138cfa0ad2SJack F Vogel { 13148cfa0ad2SJack F Vogel u32 ctrl; 13158cfa0ad2SJack F Vogel s32 ret_val = E1000_SUCCESS; 13168cfa0ad2SJack F Vogel 13178cfa0ad2SJack F Vogel DEBUGFUNC("e1000_force_mac_fc_generic"); 13188cfa0ad2SJack F Vogel 13198cfa0ad2SJack F Vogel ctrl = E1000_READ_REG(hw, E1000_CTRL); 13208cfa0ad2SJack F Vogel 13218cfa0ad2SJack F Vogel /* 13228cfa0ad2SJack F Vogel * Because we didn't get link via the internal auto-negotiation 13238cfa0ad2SJack F Vogel * mechanism (we either forced link or we got link via PHY 13248cfa0ad2SJack F Vogel * auto-neg), we have to manually enable/disable transmit an 13258cfa0ad2SJack F Vogel * receive flow control. 13268cfa0ad2SJack F Vogel * 13278cfa0ad2SJack F Vogel * The "Case" statement below enables/disable flow control 1328daf9197cSJack F Vogel * according to the "hw->fc.current_mode" parameter. 13298cfa0ad2SJack F Vogel * 13308cfa0ad2SJack F Vogel * The possible values of the "fc" parameter are: 13318cfa0ad2SJack F Vogel * 0: Flow control is completely disabled 13328cfa0ad2SJack F Vogel * 1: Rx flow control is enabled (we can receive pause 13338cfa0ad2SJack F Vogel * frames but not send pause frames). 13348cfa0ad2SJack F Vogel * 2: Tx flow control is enabled (we can send pause frames 13358cfa0ad2SJack F Vogel * frames but we do not receive pause frames). 13368cfa0ad2SJack F Vogel * 3: Both Rx and Tx flow control (symmetric) is enabled. 13378cfa0ad2SJack F Vogel * other: No other values should be possible at this point. 13388cfa0ad2SJack F Vogel */ 1339daf9197cSJack F Vogel DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode); 13408cfa0ad2SJack F Vogel 1341daf9197cSJack F Vogel switch (hw->fc.current_mode) { 13428cfa0ad2SJack F Vogel case e1000_fc_none: 13438cfa0ad2SJack F Vogel ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 13448cfa0ad2SJack F Vogel break; 13458cfa0ad2SJack F Vogel case e1000_fc_rx_pause: 13468cfa0ad2SJack F Vogel ctrl &= (~E1000_CTRL_TFCE); 13478cfa0ad2SJack F Vogel ctrl |= E1000_CTRL_RFCE; 13488cfa0ad2SJack F Vogel break; 13498cfa0ad2SJack F Vogel case e1000_fc_tx_pause: 13508cfa0ad2SJack F Vogel ctrl &= (~E1000_CTRL_RFCE); 13518cfa0ad2SJack F Vogel ctrl |= E1000_CTRL_TFCE; 13528cfa0ad2SJack F Vogel break; 13538cfa0ad2SJack F Vogel case e1000_fc_full: 13548cfa0ad2SJack F Vogel ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 13558cfa0ad2SJack F Vogel break; 13568cfa0ad2SJack F Vogel default: 13578cfa0ad2SJack F Vogel DEBUGOUT("Flow control param set incorrectly\n"); 13588cfa0ad2SJack F Vogel ret_val = -E1000_ERR_CONFIG; 13598cfa0ad2SJack F Vogel goto out; 13608cfa0ad2SJack F Vogel } 13618cfa0ad2SJack F Vogel 13628cfa0ad2SJack F Vogel E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 13638cfa0ad2SJack F Vogel 13648cfa0ad2SJack F Vogel out: 13658cfa0ad2SJack F Vogel return ret_val; 13668cfa0ad2SJack F Vogel } 13678cfa0ad2SJack F Vogel 13688cfa0ad2SJack F Vogel /** 13698cfa0ad2SJack F Vogel * e1000_config_fc_after_link_up_generic - Configures flow control after link 13708cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 13718cfa0ad2SJack F Vogel * 13728cfa0ad2SJack F Vogel * Checks the status of auto-negotiation after link up to ensure that the 13738cfa0ad2SJack F Vogel * speed and duplex were not forced. If the link needed to be forced, then 13748cfa0ad2SJack F Vogel * flow control needs to be forced also. If auto-negotiation is enabled 13758cfa0ad2SJack F Vogel * and did not fail, then we configure flow control based on our link 13768cfa0ad2SJack F Vogel * partner. 13778cfa0ad2SJack F Vogel **/ 13788cfa0ad2SJack F Vogel s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) 13798cfa0ad2SJack F Vogel { 13808cfa0ad2SJack F Vogel struct e1000_mac_info *mac = &hw->mac; 13818cfa0ad2SJack F Vogel s32 ret_val = E1000_SUCCESS; 13828cfa0ad2SJack F Vogel u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 13838cfa0ad2SJack F Vogel u16 speed, duplex; 13848cfa0ad2SJack F Vogel 13858cfa0ad2SJack F Vogel DEBUGFUNC("e1000_config_fc_after_link_up_generic"); 13868cfa0ad2SJack F Vogel 13878cfa0ad2SJack F Vogel /* 13888cfa0ad2SJack F Vogel * Check for the case where we have fiber media and auto-neg failed 13898cfa0ad2SJack F Vogel * so we had to force link. In this case, we need to force the 13908cfa0ad2SJack F Vogel * configuration of the MAC to match the "fc" parameter. 13918cfa0ad2SJack F Vogel */ 13928cfa0ad2SJack F Vogel if (mac->autoneg_failed) { 13938cfa0ad2SJack F Vogel if (hw->phy.media_type == e1000_media_type_fiber || 13948cfa0ad2SJack F Vogel hw->phy.media_type == e1000_media_type_internal_serdes) 13958cfa0ad2SJack F Vogel ret_val = e1000_force_mac_fc_generic(hw); 13968cfa0ad2SJack F Vogel } else { 13978cfa0ad2SJack F Vogel if (hw->phy.media_type == e1000_media_type_copper) 13988cfa0ad2SJack F Vogel ret_val = e1000_force_mac_fc_generic(hw); 13998cfa0ad2SJack F Vogel } 14008cfa0ad2SJack F Vogel 14018cfa0ad2SJack F Vogel if (ret_val) { 14028cfa0ad2SJack F Vogel DEBUGOUT("Error forcing flow control settings\n"); 14038cfa0ad2SJack F Vogel goto out; 14048cfa0ad2SJack F Vogel } 14058cfa0ad2SJack F Vogel 14068cfa0ad2SJack F Vogel /* 14078cfa0ad2SJack F Vogel * Check for the case where we have copper media and auto-neg is 14088cfa0ad2SJack F Vogel * enabled. In this case, we need to check and see if Auto-Neg 14098cfa0ad2SJack F Vogel * has completed, and if so, how the PHY and link partner has 14108cfa0ad2SJack F Vogel * flow control configured. 14118cfa0ad2SJack F Vogel */ 14128cfa0ad2SJack F Vogel if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 14138cfa0ad2SJack F Vogel /* 14148cfa0ad2SJack F Vogel * Read the MII Status Register and check to see if AutoNeg 14158cfa0ad2SJack F Vogel * has completed. We read this twice because this reg has 14168cfa0ad2SJack F Vogel * some "sticky" (latched) bits. 14178cfa0ad2SJack F Vogel */ 1418daf9197cSJack F Vogel ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 14198cfa0ad2SJack F Vogel if (ret_val) 14208cfa0ad2SJack F Vogel goto out; 1421daf9197cSJack F Vogel ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 14228cfa0ad2SJack F Vogel if (ret_val) 14238cfa0ad2SJack F Vogel goto out; 14248cfa0ad2SJack F Vogel 14258cfa0ad2SJack F Vogel if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 14264dab5c37SJack F Vogel DEBUGOUT("Copper PHY and Auto Neg has not completed.\n"); 14278cfa0ad2SJack F Vogel goto out; 14288cfa0ad2SJack F Vogel } 14298cfa0ad2SJack F Vogel 14308cfa0ad2SJack F Vogel /* 14318cfa0ad2SJack F Vogel * The AutoNeg process has completed, so we now need to 14328cfa0ad2SJack F Vogel * read both the Auto Negotiation Advertisement 14338cfa0ad2SJack F Vogel * Register (Address 4) and the Auto_Negotiation Base 14348cfa0ad2SJack F Vogel * Page Ability Register (Address 5) to determine how 14358cfa0ad2SJack F Vogel * flow control was negotiated. 14368cfa0ad2SJack F Vogel */ 1437daf9197cSJack F Vogel ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, 14388cfa0ad2SJack F Vogel &mii_nway_adv_reg); 14398cfa0ad2SJack F Vogel if (ret_val) 14408cfa0ad2SJack F Vogel goto out; 1441daf9197cSJack F Vogel ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, 14428cfa0ad2SJack F Vogel &mii_nway_lp_ability_reg); 14438cfa0ad2SJack F Vogel if (ret_val) 14448cfa0ad2SJack F Vogel goto out; 14458cfa0ad2SJack F Vogel 14468cfa0ad2SJack F Vogel /* 14478cfa0ad2SJack F Vogel * Two bits in the Auto Negotiation Advertisement Register 14488cfa0ad2SJack F Vogel * (Address 4) and two bits in the Auto Negotiation Base 14498cfa0ad2SJack F Vogel * Page Ability Register (Address 5) determine flow control 14508cfa0ad2SJack F Vogel * for both the PHY and the link partner. The following 14518cfa0ad2SJack F Vogel * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 14528cfa0ad2SJack F Vogel * 1999, describes these PAUSE resolution bits and how flow 14538cfa0ad2SJack F Vogel * control is determined based upon these settings. 14548cfa0ad2SJack F Vogel * NOTE: DC = Don't Care 14558cfa0ad2SJack F Vogel * 14568cfa0ad2SJack F Vogel * LOCAL DEVICE | LINK PARTNER 14578cfa0ad2SJack F Vogel * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 14588cfa0ad2SJack F Vogel *-------|---------|-------|---------|-------------------- 14598cfa0ad2SJack F Vogel * 0 | 0 | DC | DC | e1000_fc_none 14608cfa0ad2SJack F Vogel * 0 | 1 | 0 | DC | e1000_fc_none 14618cfa0ad2SJack F Vogel * 0 | 1 | 1 | 0 | e1000_fc_none 14628cfa0ad2SJack F Vogel * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 14638cfa0ad2SJack F Vogel * 1 | 0 | 0 | DC | e1000_fc_none 14648cfa0ad2SJack F Vogel * 1 | DC | 1 | DC | e1000_fc_full 14658cfa0ad2SJack F Vogel * 1 | 1 | 0 | 0 | e1000_fc_none 14668cfa0ad2SJack F Vogel * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 14678cfa0ad2SJack F Vogel * 14688cfa0ad2SJack F Vogel * Are both PAUSE bits set to 1? If so, this implies 14698cfa0ad2SJack F Vogel * Symmetric Flow Control is enabled at both ends. The 14708cfa0ad2SJack F Vogel * ASM_DIR bits are irrelevant per the spec. 14718cfa0ad2SJack F Vogel * 14728cfa0ad2SJack F Vogel * For Symmetric Flow Control: 14738cfa0ad2SJack F Vogel * 14748cfa0ad2SJack F Vogel * LOCAL DEVICE | LINK PARTNER 14758cfa0ad2SJack F Vogel * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 14768cfa0ad2SJack F Vogel *-------|---------|-------|---------|-------------------- 14778cfa0ad2SJack F Vogel * 1 | DC | 1 | DC | E1000_fc_full 14788cfa0ad2SJack F Vogel * 14798cfa0ad2SJack F Vogel */ 14808cfa0ad2SJack F Vogel if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 14818cfa0ad2SJack F Vogel (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 14828cfa0ad2SJack F Vogel /* 14838cfa0ad2SJack F Vogel * Now we need to check if the user selected Rx ONLY 14848cfa0ad2SJack F Vogel * of pause frames. In this case, we had to advertise 14854edd8523SJack F Vogel * FULL flow control because we could not advertise Rx 14868cfa0ad2SJack F Vogel * ONLY. Hence, we must now check to see if we need to 14878cfa0ad2SJack F Vogel * turn OFF the TRANSMISSION of PAUSE frames. 14888cfa0ad2SJack F Vogel */ 1489daf9197cSJack F Vogel if (hw->fc.requested_mode == e1000_fc_full) { 1490daf9197cSJack F Vogel hw->fc.current_mode = e1000_fc_full; 14914dab5c37SJack F Vogel DEBUGOUT("Flow Control = FULL.\n"); 14928cfa0ad2SJack F Vogel } else { 1493daf9197cSJack F Vogel hw->fc.current_mode = e1000_fc_rx_pause; 14944dab5c37SJack F Vogel DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 14958cfa0ad2SJack F Vogel } 14968cfa0ad2SJack F Vogel } 14978cfa0ad2SJack F Vogel /* 14988cfa0ad2SJack F Vogel * For receiving PAUSE frames ONLY. 14998cfa0ad2SJack F Vogel * 15008cfa0ad2SJack F Vogel * LOCAL DEVICE | LINK PARTNER 15018cfa0ad2SJack F Vogel * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 15028cfa0ad2SJack F Vogel *-------|---------|-------|---------|-------------------- 15038cfa0ad2SJack F Vogel * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 15048cfa0ad2SJack F Vogel */ 15058cfa0ad2SJack F Vogel else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 15068cfa0ad2SJack F Vogel (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 15078cfa0ad2SJack F Vogel (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 15088cfa0ad2SJack F Vogel (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1509daf9197cSJack F Vogel hw->fc.current_mode = e1000_fc_tx_pause; 15104dab5c37SJack F Vogel DEBUGOUT("Flow Control = Tx PAUSE frames only.\n"); 15118cfa0ad2SJack F Vogel } 15128cfa0ad2SJack F Vogel /* 15138cfa0ad2SJack F Vogel * For transmitting PAUSE frames ONLY. 15148cfa0ad2SJack F Vogel * 15158cfa0ad2SJack F Vogel * LOCAL DEVICE | LINK PARTNER 15168cfa0ad2SJack F Vogel * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 15178cfa0ad2SJack F Vogel *-------|---------|-------|---------|-------------------- 15188cfa0ad2SJack F Vogel * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 15198cfa0ad2SJack F Vogel */ 15208cfa0ad2SJack F Vogel else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 15218cfa0ad2SJack F Vogel (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 15228cfa0ad2SJack F Vogel !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 15238cfa0ad2SJack F Vogel (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1524daf9197cSJack F Vogel hw->fc.current_mode = e1000_fc_rx_pause; 15254dab5c37SJack F Vogel DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 15268cfa0ad2SJack F Vogel } else { 15278cfa0ad2SJack F Vogel /* 15288cfa0ad2SJack F Vogel * Per the IEEE spec, at this point flow control 15298cfa0ad2SJack F Vogel * should be disabled. 15308cfa0ad2SJack F Vogel */ 1531daf9197cSJack F Vogel hw->fc.current_mode = e1000_fc_none; 15324dab5c37SJack F Vogel DEBUGOUT("Flow Control = NONE.\n"); 15338cfa0ad2SJack F Vogel } 15348cfa0ad2SJack F Vogel 15358cfa0ad2SJack F Vogel /* 15368cfa0ad2SJack F Vogel * Now we need to do one last check... If we auto- 15378cfa0ad2SJack F Vogel * negotiated to HALF DUPLEX, flow control should not be 15388cfa0ad2SJack F Vogel * enabled per IEEE 802.3 spec. 15398cfa0ad2SJack F Vogel */ 15408cfa0ad2SJack F Vogel ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 15418cfa0ad2SJack F Vogel if (ret_val) { 15428cfa0ad2SJack F Vogel DEBUGOUT("Error getting link speed and duplex\n"); 15438cfa0ad2SJack F Vogel goto out; 15448cfa0ad2SJack F Vogel } 15458cfa0ad2SJack F Vogel 15468cfa0ad2SJack F Vogel if (duplex == HALF_DUPLEX) 1547daf9197cSJack F Vogel hw->fc.current_mode = e1000_fc_none; 15488cfa0ad2SJack F Vogel 15498cfa0ad2SJack F Vogel /* 15508cfa0ad2SJack F Vogel * Now we call a subroutine to actually force the MAC 15518cfa0ad2SJack F Vogel * controller to use the correct flow control settings. 15528cfa0ad2SJack F Vogel */ 15538cfa0ad2SJack F Vogel ret_val = e1000_force_mac_fc_generic(hw); 15548cfa0ad2SJack F Vogel if (ret_val) { 15558cfa0ad2SJack F Vogel DEBUGOUT("Error forcing flow control settings\n"); 15568cfa0ad2SJack F Vogel goto out; 15578cfa0ad2SJack F Vogel } 15588cfa0ad2SJack F Vogel } 15598cfa0ad2SJack F Vogel 15608cfa0ad2SJack F Vogel out: 15618cfa0ad2SJack F Vogel return ret_val; 15628cfa0ad2SJack F Vogel } 15638cfa0ad2SJack F Vogel 15648cfa0ad2SJack F Vogel /** 15658cfa0ad2SJack F Vogel * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex 15668cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 15678cfa0ad2SJack F Vogel * @speed: stores the current speed 15688cfa0ad2SJack F Vogel * @duplex: stores the current duplex 15698cfa0ad2SJack F Vogel * 15708cfa0ad2SJack F Vogel * Read the status register for the current speed/duplex and store the current 15718cfa0ad2SJack F Vogel * speed and duplex for copper connections. 15728cfa0ad2SJack F Vogel **/ 15738cfa0ad2SJack F Vogel s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, 15748cfa0ad2SJack F Vogel u16 *duplex) 15758cfa0ad2SJack F Vogel { 15768cfa0ad2SJack F Vogel u32 status; 15778cfa0ad2SJack F Vogel 15788cfa0ad2SJack F Vogel DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic"); 15798cfa0ad2SJack F Vogel 15808cfa0ad2SJack F Vogel status = E1000_READ_REG(hw, E1000_STATUS); 15818cfa0ad2SJack F Vogel if (status & E1000_STATUS_SPEED_1000) { 15828cfa0ad2SJack F Vogel *speed = SPEED_1000; 15838cfa0ad2SJack F Vogel DEBUGOUT("1000 Mbs, "); 15848cfa0ad2SJack F Vogel } else if (status & E1000_STATUS_SPEED_100) { 15858cfa0ad2SJack F Vogel *speed = SPEED_100; 15868cfa0ad2SJack F Vogel DEBUGOUT("100 Mbs, "); 15878cfa0ad2SJack F Vogel } else { 15888cfa0ad2SJack F Vogel *speed = SPEED_10; 15898cfa0ad2SJack F Vogel DEBUGOUT("10 Mbs, "); 15908cfa0ad2SJack F Vogel } 15918cfa0ad2SJack F Vogel 15928cfa0ad2SJack F Vogel if (status & E1000_STATUS_FD) { 15938cfa0ad2SJack F Vogel *duplex = FULL_DUPLEX; 15948cfa0ad2SJack F Vogel DEBUGOUT("Full Duplex\n"); 15958cfa0ad2SJack F Vogel } else { 15968cfa0ad2SJack F Vogel *duplex = HALF_DUPLEX; 15978cfa0ad2SJack F Vogel DEBUGOUT("Half Duplex\n"); 15988cfa0ad2SJack F Vogel } 15998cfa0ad2SJack F Vogel 16008cfa0ad2SJack F Vogel return E1000_SUCCESS; 16018cfa0ad2SJack F Vogel } 16028cfa0ad2SJack F Vogel 16038cfa0ad2SJack F Vogel /** 16048cfa0ad2SJack F Vogel * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex 16058cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 16068cfa0ad2SJack F Vogel * @speed: stores the current speed 16078cfa0ad2SJack F Vogel * @duplex: stores the current duplex 16088cfa0ad2SJack F Vogel * 16098cfa0ad2SJack F Vogel * Sets the speed and duplex to gigabit full duplex (the only possible option) 16108cfa0ad2SJack F Vogel * for fiber/serdes links. 16118cfa0ad2SJack F Vogel **/ 16128cfa0ad2SJack F Vogel s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw, 16138cfa0ad2SJack F Vogel u16 *speed, u16 *duplex) 16148cfa0ad2SJack F Vogel { 16158cfa0ad2SJack F Vogel DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic"); 16168cfa0ad2SJack F Vogel 16178cfa0ad2SJack F Vogel *speed = SPEED_1000; 16188cfa0ad2SJack F Vogel *duplex = FULL_DUPLEX; 16198cfa0ad2SJack F Vogel 16208cfa0ad2SJack F Vogel return E1000_SUCCESS; 16218cfa0ad2SJack F Vogel } 16228cfa0ad2SJack F Vogel 16238cfa0ad2SJack F Vogel /** 16248cfa0ad2SJack F Vogel * e1000_get_hw_semaphore_generic - Acquire hardware semaphore 16258cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 16268cfa0ad2SJack F Vogel * 16278cfa0ad2SJack F Vogel * Acquire the HW semaphore to access the PHY or NVM 16288cfa0ad2SJack F Vogel **/ 16298cfa0ad2SJack F Vogel s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw) 16308cfa0ad2SJack F Vogel { 16318cfa0ad2SJack F Vogel u32 swsm; 16328cfa0ad2SJack F Vogel s32 ret_val = E1000_SUCCESS; 16338cfa0ad2SJack F Vogel s32 timeout = hw->nvm.word_size + 1; 16348cfa0ad2SJack F Vogel s32 i = 0; 16358cfa0ad2SJack F Vogel 16368cfa0ad2SJack F Vogel DEBUGFUNC("e1000_get_hw_semaphore_generic"); 16378cfa0ad2SJack F Vogel 16388cfa0ad2SJack F Vogel /* Get the SW semaphore */ 16398cfa0ad2SJack F Vogel while (i < timeout) { 16408cfa0ad2SJack F Vogel swsm = E1000_READ_REG(hw, E1000_SWSM); 16418cfa0ad2SJack F Vogel if (!(swsm & E1000_SWSM_SMBI)) 16428cfa0ad2SJack F Vogel break; 16438cfa0ad2SJack F Vogel 16448cfa0ad2SJack F Vogel usec_delay(50); 16458cfa0ad2SJack F Vogel i++; 16468cfa0ad2SJack F Vogel } 16478cfa0ad2SJack F Vogel 16488cfa0ad2SJack F Vogel if (i == timeout) { 16498cfa0ad2SJack F Vogel DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 16508cfa0ad2SJack F Vogel ret_val = -E1000_ERR_NVM; 16518cfa0ad2SJack F Vogel goto out; 16528cfa0ad2SJack F Vogel } 16538cfa0ad2SJack F Vogel 16548cfa0ad2SJack F Vogel /* Get the FW semaphore. */ 16558cfa0ad2SJack F Vogel for (i = 0; i < timeout; i++) { 16568cfa0ad2SJack F Vogel swsm = E1000_READ_REG(hw, E1000_SWSM); 16578cfa0ad2SJack F Vogel E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 16588cfa0ad2SJack F Vogel 16598cfa0ad2SJack F Vogel /* Semaphore acquired if bit latched */ 16608cfa0ad2SJack F Vogel if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 16618cfa0ad2SJack F Vogel break; 16628cfa0ad2SJack F Vogel 16638cfa0ad2SJack F Vogel usec_delay(50); 16648cfa0ad2SJack F Vogel } 16658cfa0ad2SJack F Vogel 16668cfa0ad2SJack F Vogel if (i == timeout) { 16678cfa0ad2SJack F Vogel /* Release semaphores */ 16688cfa0ad2SJack F Vogel e1000_put_hw_semaphore_generic(hw); 16698cfa0ad2SJack F Vogel DEBUGOUT("Driver can't access the NVM\n"); 16708cfa0ad2SJack F Vogel ret_val = -E1000_ERR_NVM; 16718cfa0ad2SJack F Vogel goto out; 16728cfa0ad2SJack F Vogel } 16738cfa0ad2SJack F Vogel 16748cfa0ad2SJack F Vogel out: 16758cfa0ad2SJack F Vogel return ret_val; 16768cfa0ad2SJack F Vogel } 16778cfa0ad2SJack F Vogel 16788cfa0ad2SJack F Vogel /** 16798cfa0ad2SJack F Vogel * e1000_put_hw_semaphore_generic - Release hardware semaphore 16808cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 16818cfa0ad2SJack F Vogel * 16828cfa0ad2SJack F Vogel * Release hardware semaphore used to access the PHY or NVM 16838cfa0ad2SJack F Vogel **/ 16848cfa0ad2SJack F Vogel void e1000_put_hw_semaphore_generic(struct e1000_hw *hw) 16858cfa0ad2SJack F Vogel { 16868cfa0ad2SJack F Vogel u32 swsm; 16878cfa0ad2SJack F Vogel 16888cfa0ad2SJack F Vogel DEBUGFUNC("e1000_put_hw_semaphore_generic"); 16898cfa0ad2SJack F Vogel 16908cfa0ad2SJack F Vogel swsm = E1000_READ_REG(hw, E1000_SWSM); 16918cfa0ad2SJack F Vogel 16928cfa0ad2SJack F Vogel swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 16938cfa0ad2SJack F Vogel 16948cfa0ad2SJack F Vogel E1000_WRITE_REG(hw, E1000_SWSM, swsm); 16958cfa0ad2SJack F Vogel } 16968cfa0ad2SJack F Vogel 16978cfa0ad2SJack F Vogel /** 16988cfa0ad2SJack F Vogel * e1000_get_auto_rd_done_generic - Check for auto read completion 16998cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 17008cfa0ad2SJack F Vogel * 17018cfa0ad2SJack F Vogel * Check EEPROM for Auto Read done bit. 17028cfa0ad2SJack F Vogel **/ 17038cfa0ad2SJack F Vogel s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw) 17048cfa0ad2SJack F Vogel { 17058cfa0ad2SJack F Vogel s32 i = 0; 17068cfa0ad2SJack F Vogel s32 ret_val = E1000_SUCCESS; 17078cfa0ad2SJack F Vogel 17088cfa0ad2SJack F Vogel DEBUGFUNC("e1000_get_auto_rd_done_generic"); 17098cfa0ad2SJack F Vogel 17108cfa0ad2SJack F Vogel while (i < AUTO_READ_DONE_TIMEOUT) { 17118cfa0ad2SJack F Vogel if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) 17128cfa0ad2SJack F Vogel break; 17138cfa0ad2SJack F Vogel msec_delay(1); 17148cfa0ad2SJack F Vogel i++; 17158cfa0ad2SJack F Vogel } 17168cfa0ad2SJack F Vogel 17178cfa0ad2SJack F Vogel if (i == AUTO_READ_DONE_TIMEOUT) { 17188cfa0ad2SJack F Vogel DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 17198cfa0ad2SJack F Vogel ret_val = -E1000_ERR_RESET; 17208cfa0ad2SJack F Vogel goto out; 17218cfa0ad2SJack F Vogel } 17228cfa0ad2SJack F Vogel 17238cfa0ad2SJack F Vogel out: 17248cfa0ad2SJack F Vogel return ret_val; 17258cfa0ad2SJack F Vogel } 17268cfa0ad2SJack F Vogel 17278cfa0ad2SJack F Vogel /** 17288cfa0ad2SJack F Vogel * e1000_valid_led_default_generic - Verify a valid default LED config 17298cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 17308cfa0ad2SJack F Vogel * @data: pointer to the NVM (EEPROM) 17318cfa0ad2SJack F Vogel * 17328cfa0ad2SJack F Vogel * Read the EEPROM for the current default LED configuration. If the 17338cfa0ad2SJack F Vogel * LED configuration is not valid, set to a valid LED configuration. 17348cfa0ad2SJack F Vogel **/ 17358cfa0ad2SJack F Vogel s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data) 17368cfa0ad2SJack F Vogel { 17378cfa0ad2SJack F Vogel s32 ret_val; 17388cfa0ad2SJack F Vogel 17398cfa0ad2SJack F Vogel DEBUGFUNC("e1000_valid_led_default_generic"); 17408cfa0ad2SJack F Vogel 17418cfa0ad2SJack F Vogel ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 17428cfa0ad2SJack F Vogel if (ret_val) { 17438cfa0ad2SJack F Vogel DEBUGOUT("NVM Read Error\n"); 17448cfa0ad2SJack F Vogel goto out; 17458cfa0ad2SJack F Vogel } 17468cfa0ad2SJack F Vogel 17478cfa0ad2SJack F Vogel if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 17488cfa0ad2SJack F Vogel *data = ID_LED_DEFAULT; 17498cfa0ad2SJack F Vogel 17508cfa0ad2SJack F Vogel out: 17518cfa0ad2SJack F Vogel return ret_val; 17528cfa0ad2SJack F Vogel } 17538cfa0ad2SJack F Vogel 17548cfa0ad2SJack F Vogel /** 17558cfa0ad2SJack F Vogel * e1000_id_led_init_generic - 17568cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 17578cfa0ad2SJack F Vogel * 17588cfa0ad2SJack F Vogel **/ 17598cfa0ad2SJack F Vogel s32 e1000_id_led_init_generic(struct e1000_hw *hw) 17608cfa0ad2SJack F Vogel { 17618cfa0ad2SJack F Vogel struct e1000_mac_info *mac = &hw->mac; 17628cfa0ad2SJack F Vogel s32 ret_val; 17638cfa0ad2SJack F Vogel const u32 ledctl_mask = 0x000000FF; 17648cfa0ad2SJack F Vogel const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 17658cfa0ad2SJack F Vogel const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 17668cfa0ad2SJack F Vogel u16 data, i, temp; 17678cfa0ad2SJack F Vogel const u16 led_mask = 0x0F; 17688cfa0ad2SJack F Vogel 17698cfa0ad2SJack F Vogel DEBUGFUNC("e1000_id_led_init_generic"); 17708cfa0ad2SJack F Vogel 17718cfa0ad2SJack F Vogel ret_val = hw->nvm.ops.valid_led_default(hw, &data); 17728cfa0ad2SJack F Vogel if (ret_val) 17738cfa0ad2SJack F Vogel goto out; 17748cfa0ad2SJack F Vogel 17758cfa0ad2SJack F Vogel mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 17768cfa0ad2SJack F Vogel mac->ledctl_mode1 = mac->ledctl_default; 17778cfa0ad2SJack F Vogel mac->ledctl_mode2 = mac->ledctl_default; 17788cfa0ad2SJack F Vogel 17798cfa0ad2SJack F Vogel for (i = 0; i < 4; i++) { 17808cfa0ad2SJack F Vogel temp = (data >> (i << 2)) & led_mask; 17818cfa0ad2SJack F Vogel switch (temp) { 17828cfa0ad2SJack F Vogel case ID_LED_ON1_DEF2: 17838cfa0ad2SJack F Vogel case ID_LED_ON1_ON2: 17848cfa0ad2SJack F Vogel case ID_LED_ON1_OFF2: 17858cfa0ad2SJack F Vogel mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 17868cfa0ad2SJack F Vogel mac->ledctl_mode1 |= ledctl_on << (i << 3); 17878cfa0ad2SJack F Vogel break; 17888cfa0ad2SJack F Vogel case ID_LED_OFF1_DEF2: 17898cfa0ad2SJack F Vogel case ID_LED_OFF1_ON2: 17908cfa0ad2SJack F Vogel case ID_LED_OFF1_OFF2: 17918cfa0ad2SJack F Vogel mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 17928cfa0ad2SJack F Vogel mac->ledctl_mode1 |= ledctl_off << (i << 3); 17938cfa0ad2SJack F Vogel break; 17948cfa0ad2SJack F Vogel default: 17958cfa0ad2SJack F Vogel /* Do nothing */ 17968cfa0ad2SJack F Vogel break; 17978cfa0ad2SJack F Vogel } 17988cfa0ad2SJack F Vogel switch (temp) { 17998cfa0ad2SJack F Vogel case ID_LED_DEF1_ON2: 18008cfa0ad2SJack F Vogel case ID_LED_ON1_ON2: 18018cfa0ad2SJack F Vogel case ID_LED_OFF1_ON2: 18028cfa0ad2SJack F Vogel mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 18038cfa0ad2SJack F Vogel mac->ledctl_mode2 |= ledctl_on << (i << 3); 18048cfa0ad2SJack F Vogel break; 18058cfa0ad2SJack F Vogel case ID_LED_DEF1_OFF2: 18068cfa0ad2SJack F Vogel case ID_LED_ON1_OFF2: 18078cfa0ad2SJack F Vogel case ID_LED_OFF1_OFF2: 18088cfa0ad2SJack F Vogel mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 18098cfa0ad2SJack F Vogel mac->ledctl_mode2 |= ledctl_off << (i << 3); 18108cfa0ad2SJack F Vogel break; 18118cfa0ad2SJack F Vogel default: 18128cfa0ad2SJack F Vogel /* Do nothing */ 18138cfa0ad2SJack F Vogel break; 18148cfa0ad2SJack F Vogel } 18158cfa0ad2SJack F Vogel } 18168cfa0ad2SJack F Vogel 18178cfa0ad2SJack F Vogel out: 18188cfa0ad2SJack F Vogel return ret_val; 18198cfa0ad2SJack F Vogel } 18208cfa0ad2SJack F Vogel 18218cfa0ad2SJack F Vogel /** 18228cfa0ad2SJack F Vogel * e1000_setup_led_generic - Configures SW controllable LED 18238cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 18248cfa0ad2SJack F Vogel * 18258cfa0ad2SJack F Vogel * This prepares the SW controllable LED for use and saves the current state 18268cfa0ad2SJack F Vogel * of the LED so it can be later restored. 18278cfa0ad2SJack F Vogel **/ 18288cfa0ad2SJack F Vogel s32 e1000_setup_led_generic(struct e1000_hw *hw) 18298cfa0ad2SJack F Vogel { 18308cfa0ad2SJack F Vogel u32 ledctl; 18318cfa0ad2SJack F Vogel s32 ret_val = E1000_SUCCESS; 18328cfa0ad2SJack F Vogel 18338cfa0ad2SJack F Vogel DEBUGFUNC("e1000_setup_led_generic"); 18348cfa0ad2SJack F Vogel 18358cfa0ad2SJack F Vogel if (hw->mac.ops.setup_led != e1000_setup_led_generic) { 18368cfa0ad2SJack F Vogel ret_val = -E1000_ERR_CONFIG; 18378cfa0ad2SJack F Vogel goto out; 18388cfa0ad2SJack F Vogel } 18398cfa0ad2SJack F Vogel 18408cfa0ad2SJack F Vogel if (hw->phy.media_type == e1000_media_type_fiber) { 18418cfa0ad2SJack F Vogel ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 18428cfa0ad2SJack F Vogel hw->mac.ledctl_default = ledctl; 18438cfa0ad2SJack F Vogel /* Turn off LED0 */ 18444dab5c37SJack F Vogel ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK | 18458cfa0ad2SJack F Vogel E1000_LEDCTL_LED0_MODE_MASK); 18468cfa0ad2SJack F Vogel ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 18478cfa0ad2SJack F Vogel E1000_LEDCTL_LED0_MODE_SHIFT); 18488cfa0ad2SJack F Vogel E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 18498cfa0ad2SJack F Vogel } else if (hw->phy.media_type == e1000_media_type_copper) { 18508cfa0ad2SJack F Vogel E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 18518cfa0ad2SJack F Vogel } 18528cfa0ad2SJack F Vogel 18538cfa0ad2SJack F Vogel out: 18548cfa0ad2SJack F Vogel return ret_val; 18558cfa0ad2SJack F Vogel } 18568cfa0ad2SJack F Vogel 18578cfa0ad2SJack F Vogel /** 18588cfa0ad2SJack F Vogel * e1000_cleanup_led_generic - Set LED config to default operation 18598cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 18608cfa0ad2SJack F Vogel * 18618cfa0ad2SJack F Vogel * Remove the current LED configuration and set the LED configuration 18628cfa0ad2SJack F Vogel * to the default value, saved from the EEPROM. 18638cfa0ad2SJack F Vogel **/ 18648cfa0ad2SJack F Vogel s32 e1000_cleanup_led_generic(struct e1000_hw *hw) 18658cfa0ad2SJack F Vogel { 18668cfa0ad2SJack F Vogel DEBUGFUNC("e1000_cleanup_led_generic"); 18678cfa0ad2SJack F Vogel 18688cfa0ad2SJack F Vogel E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1869a69ed8dfSJack F Vogel return E1000_SUCCESS; 18708cfa0ad2SJack F Vogel } 18718cfa0ad2SJack F Vogel 18728cfa0ad2SJack F Vogel /** 18738cfa0ad2SJack F Vogel * e1000_blink_led_generic - Blink LED 18748cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 18758cfa0ad2SJack F Vogel * 18768cfa0ad2SJack F Vogel * Blink the LEDs which are set to be on. 18778cfa0ad2SJack F Vogel **/ 18788cfa0ad2SJack F Vogel s32 e1000_blink_led_generic(struct e1000_hw *hw) 18798cfa0ad2SJack F Vogel { 18808cfa0ad2SJack F Vogel u32 ledctl_blink = 0; 18818cfa0ad2SJack F Vogel u32 i; 18828cfa0ad2SJack F Vogel 18838cfa0ad2SJack F Vogel DEBUGFUNC("e1000_blink_led_generic"); 18848cfa0ad2SJack F Vogel 18858cfa0ad2SJack F Vogel if (hw->phy.media_type == e1000_media_type_fiber) { 18868cfa0ad2SJack F Vogel /* always blink LED0 for PCI-E fiber */ 18878cfa0ad2SJack F Vogel ledctl_blink = E1000_LEDCTL_LED0_BLINK | 18888cfa0ad2SJack F Vogel (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 18898cfa0ad2SJack F Vogel } else { 18908cfa0ad2SJack F Vogel /* 18918cfa0ad2SJack F Vogel * set the blink bit for each LED that's "on" (0x0E) 18928cfa0ad2SJack F Vogel * in ledctl_mode2 18938cfa0ad2SJack F Vogel */ 18948cfa0ad2SJack F Vogel ledctl_blink = hw->mac.ledctl_mode2; 18958cfa0ad2SJack F Vogel for (i = 0; i < 4; i++) 18968cfa0ad2SJack F Vogel if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 18978cfa0ad2SJack F Vogel E1000_LEDCTL_MODE_LED_ON) 18988cfa0ad2SJack F Vogel ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << 18998cfa0ad2SJack F Vogel (i * 8)); 19008cfa0ad2SJack F Vogel } 19018cfa0ad2SJack F Vogel 19028cfa0ad2SJack F Vogel E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); 19038cfa0ad2SJack F Vogel 19048cfa0ad2SJack F Vogel return E1000_SUCCESS; 19058cfa0ad2SJack F Vogel } 19068cfa0ad2SJack F Vogel 19078cfa0ad2SJack F Vogel /** 19088cfa0ad2SJack F Vogel * e1000_led_on_generic - Turn LED on 19098cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 19108cfa0ad2SJack F Vogel * 19118cfa0ad2SJack F Vogel * Turn LED on. 19128cfa0ad2SJack F Vogel **/ 19138cfa0ad2SJack F Vogel s32 e1000_led_on_generic(struct e1000_hw *hw) 19148cfa0ad2SJack F Vogel { 19158cfa0ad2SJack F Vogel u32 ctrl; 19168cfa0ad2SJack F Vogel 19178cfa0ad2SJack F Vogel DEBUGFUNC("e1000_led_on_generic"); 19188cfa0ad2SJack F Vogel 19198cfa0ad2SJack F Vogel switch (hw->phy.media_type) { 19208cfa0ad2SJack F Vogel case e1000_media_type_fiber: 19218cfa0ad2SJack F Vogel ctrl = E1000_READ_REG(hw, E1000_CTRL); 19228cfa0ad2SJack F Vogel ctrl &= ~E1000_CTRL_SWDPIN0; 19238cfa0ad2SJack F Vogel ctrl |= E1000_CTRL_SWDPIO0; 19248cfa0ad2SJack F Vogel E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 19258cfa0ad2SJack F Vogel break; 19268cfa0ad2SJack F Vogel case e1000_media_type_copper: 19278cfa0ad2SJack F Vogel E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 19288cfa0ad2SJack F Vogel break; 19298cfa0ad2SJack F Vogel default: 19308cfa0ad2SJack F Vogel break; 19318cfa0ad2SJack F Vogel } 19328cfa0ad2SJack F Vogel 19338cfa0ad2SJack F Vogel return E1000_SUCCESS; 19348cfa0ad2SJack F Vogel } 19358cfa0ad2SJack F Vogel 19368cfa0ad2SJack F Vogel /** 19378cfa0ad2SJack F Vogel * e1000_led_off_generic - Turn LED off 19388cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 19398cfa0ad2SJack F Vogel * 19408cfa0ad2SJack F Vogel * Turn LED off. 19418cfa0ad2SJack F Vogel **/ 19428cfa0ad2SJack F Vogel s32 e1000_led_off_generic(struct e1000_hw *hw) 19438cfa0ad2SJack F Vogel { 19448cfa0ad2SJack F Vogel u32 ctrl; 19458cfa0ad2SJack F Vogel 19468cfa0ad2SJack F Vogel DEBUGFUNC("e1000_led_off_generic"); 19478cfa0ad2SJack F Vogel 19488cfa0ad2SJack F Vogel switch (hw->phy.media_type) { 19498cfa0ad2SJack F Vogel case e1000_media_type_fiber: 19508cfa0ad2SJack F Vogel ctrl = E1000_READ_REG(hw, E1000_CTRL); 19518cfa0ad2SJack F Vogel ctrl |= E1000_CTRL_SWDPIN0; 19528cfa0ad2SJack F Vogel ctrl |= E1000_CTRL_SWDPIO0; 19538cfa0ad2SJack F Vogel E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 19548cfa0ad2SJack F Vogel break; 19558cfa0ad2SJack F Vogel case e1000_media_type_copper: 19568cfa0ad2SJack F Vogel E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 19578cfa0ad2SJack F Vogel break; 19588cfa0ad2SJack F Vogel default: 19598cfa0ad2SJack F Vogel break; 19608cfa0ad2SJack F Vogel } 19618cfa0ad2SJack F Vogel 19628cfa0ad2SJack F Vogel return E1000_SUCCESS; 19638cfa0ad2SJack F Vogel } 19648cfa0ad2SJack F Vogel 19658cfa0ad2SJack F Vogel /** 19668cfa0ad2SJack F Vogel * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities 19678cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 19688cfa0ad2SJack F Vogel * @no_snoop: bitmap of snoop events 19698cfa0ad2SJack F Vogel * 19708cfa0ad2SJack F Vogel * Set the PCI-express register to snoop for events enabled in 'no_snoop'. 19718cfa0ad2SJack F Vogel **/ 19728cfa0ad2SJack F Vogel void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop) 19738cfa0ad2SJack F Vogel { 19748cfa0ad2SJack F Vogel u32 gcr; 19758cfa0ad2SJack F Vogel 19768cfa0ad2SJack F Vogel DEBUGFUNC("e1000_set_pcie_no_snoop_generic"); 19778cfa0ad2SJack F Vogel 19788cfa0ad2SJack F Vogel if (hw->bus.type != e1000_bus_type_pci_express) 19798cfa0ad2SJack F Vogel goto out; 19808cfa0ad2SJack F Vogel 19818cfa0ad2SJack F Vogel if (no_snoop) { 19828cfa0ad2SJack F Vogel gcr = E1000_READ_REG(hw, E1000_GCR); 19838cfa0ad2SJack F Vogel gcr &= ~(PCIE_NO_SNOOP_ALL); 19848cfa0ad2SJack F Vogel gcr |= no_snoop; 19858cfa0ad2SJack F Vogel E1000_WRITE_REG(hw, E1000_GCR, gcr); 19868cfa0ad2SJack F Vogel } 19878cfa0ad2SJack F Vogel out: 19888cfa0ad2SJack F Vogel return; 19898cfa0ad2SJack F Vogel } 19908cfa0ad2SJack F Vogel 19918cfa0ad2SJack F Vogel /** 19928cfa0ad2SJack F Vogel * e1000_disable_pcie_master_generic - Disables PCI-express master access 19938cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 19948cfa0ad2SJack F Vogel * 19954edd8523SJack F Vogel * Returns E1000_SUCCESS if successful, else returns -10 19968cfa0ad2SJack F Vogel * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 19978cfa0ad2SJack F Vogel * the master requests to be disabled. 19988cfa0ad2SJack F Vogel * 19998cfa0ad2SJack F Vogel * Disables PCI-Express master access and verifies there are no pending 20008cfa0ad2SJack F Vogel * requests. 20018cfa0ad2SJack F Vogel **/ 20028cfa0ad2SJack F Vogel s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw) 20038cfa0ad2SJack F Vogel { 20048cfa0ad2SJack F Vogel u32 ctrl; 20058cfa0ad2SJack F Vogel s32 timeout = MASTER_DISABLE_TIMEOUT; 20068cfa0ad2SJack F Vogel s32 ret_val = E1000_SUCCESS; 20078cfa0ad2SJack F Vogel 20088cfa0ad2SJack F Vogel DEBUGFUNC("e1000_disable_pcie_master_generic"); 20098cfa0ad2SJack F Vogel 20108cfa0ad2SJack F Vogel if (hw->bus.type != e1000_bus_type_pci_express) 20118cfa0ad2SJack F Vogel goto out; 20128cfa0ad2SJack F Vogel 20138cfa0ad2SJack F Vogel ctrl = E1000_READ_REG(hw, E1000_CTRL); 20148cfa0ad2SJack F Vogel ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 20158cfa0ad2SJack F Vogel E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 20168cfa0ad2SJack F Vogel 20178cfa0ad2SJack F Vogel while (timeout) { 20188cfa0ad2SJack F Vogel if (!(E1000_READ_REG(hw, E1000_STATUS) & 20198cfa0ad2SJack F Vogel E1000_STATUS_GIO_MASTER_ENABLE)) 20208cfa0ad2SJack F Vogel break; 20218cfa0ad2SJack F Vogel usec_delay(100); 20228cfa0ad2SJack F Vogel timeout--; 20238cfa0ad2SJack F Vogel } 20248cfa0ad2SJack F Vogel 20258cfa0ad2SJack F Vogel if (!timeout) { 20268cfa0ad2SJack F Vogel DEBUGOUT("Master requests are pending.\n"); 20278cfa0ad2SJack F Vogel ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; 20288cfa0ad2SJack F Vogel } 20298cfa0ad2SJack F Vogel 20308cfa0ad2SJack F Vogel out: 20318cfa0ad2SJack F Vogel return ret_val; 20328cfa0ad2SJack F Vogel } 20338cfa0ad2SJack F Vogel 20348cfa0ad2SJack F Vogel /** 20358cfa0ad2SJack F Vogel * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing 20368cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 20378cfa0ad2SJack F Vogel * 20388cfa0ad2SJack F Vogel * Reset the Adaptive Interframe Spacing throttle to default values. 20398cfa0ad2SJack F Vogel **/ 20408cfa0ad2SJack F Vogel void e1000_reset_adaptive_generic(struct e1000_hw *hw) 20418cfa0ad2SJack F Vogel { 20428cfa0ad2SJack F Vogel struct e1000_mac_info *mac = &hw->mac; 20438cfa0ad2SJack F Vogel 20448cfa0ad2SJack F Vogel DEBUGFUNC("e1000_reset_adaptive_generic"); 20458cfa0ad2SJack F Vogel 20468cfa0ad2SJack F Vogel if (!mac->adaptive_ifs) { 20478cfa0ad2SJack F Vogel DEBUGOUT("Not in Adaptive IFS mode!\n"); 20488cfa0ad2SJack F Vogel goto out; 20498cfa0ad2SJack F Vogel } 20508cfa0ad2SJack F Vogel 20518cfa0ad2SJack F Vogel mac->current_ifs_val = 0; 20528cfa0ad2SJack F Vogel mac->ifs_min_val = IFS_MIN; 20538cfa0ad2SJack F Vogel mac->ifs_max_val = IFS_MAX; 20548cfa0ad2SJack F Vogel mac->ifs_step_size = IFS_STEP; 20558cfa0ad2SJack F Vogel mac->ifs_ratio = IFS_RATIO; 20568cfa0ad2SJack F Vogel 20578cfa0ad2SJack F Vogel mac->in_ifs_mode = FALSE; 20588cfa0ad2SJack F Vogel E1000_WRITE_REG(hw, E1000_AIT, 0); 20598cfa0ad2SJack F Vogel out: 20608cfa0ad2SJack F Vogel return; 20618cfa0ad2SJack F Vogel } 20628cfa0ad2SJack F Vogel 20638cfa0ad2SJack F Vogel /** 20648cfa0ad2SJack F Vogel * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing 20658cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 20668cfa0ad2SJack F Vogel * 20678cfa0ad2SJack F Vogel * Update the Adaptive Interframe Spacing Throttle value based on the 20688cfa0ad2SJack F Vogel * time between transmitted packets and time between collisions. 20698cfa0ad2SJack F Vogel **/ 20708cfa0ad2SJack F Vogel void e1000_update_adaptive_generic(struct e1000_hw *hw) 20718cfa0ad2SJack F Vogel { 20728cfa0ad2SJack F Vogel struct e1000_mac_info *mac = &hw->mac; 20738cfa0ad2SJack F Vogel 20748cfa0ad2SJack F Vogel DEBUGFUNC("e1000_update_adaptive_generic"); 20758cfa0ad2SJack F Vogel 20768cfa0ad2SJack F Vogel if (!mac->adaptive_ifs) { 20778cfa0ad2SJack F Vogel DEBUGOUT("Not in Adaptive IFS mode!\n"); 20788cfa0ad2SJack F Vogel goto out; 20798cfa0ad2SJack F Vogel } 20808cfa0ad2SJack F Vogel 20818cfa0ad2SJack F Vogel if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 20828cfa0ad2SJack F Vogel if (mac->tx_packet_delta > MIN_NUM_XMITS) { 20838cfa0ad2SJack F Vogel mac->in_ifs_mode = TRUE; 20848cfa0ad2SJack F Vogel if (mac->current_ifs_val < mac->ifs_max_val) { 20858cfa0ad2SJack F Vogel if (!mac->current_ifs_val) 20868cfa0ad2SJack F Vogel mac->current_ifs_val = mac->ifs_min_val; 20878cfa0ad2SJack F Vogel else 20888cfa0ad2SJack F Vogel mac->current_ifs_val += 20898cfa0ad2SJack F Vogel mac->ifs_step_size; 20904dab5c37SJack F Vogel E1000_WRITE_REG(hw, E1000_AIT, 20914dab5c37SJack F Vogel mac->current_ifs_val); 20928cfa0ad2SJack F Vogel } 20938cfa0ad2SJack F Vogel } 20948cfa0ad2SJack F Vogel } else { 20958cfa0ad2SJack F Vogel if (mac->in_ifs_mode && 20968cfa0ad2SJack F Vogel (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 20978cfa0ad2SJack F Vogel mac->current_ifs_val = 0; 20988cfa0ad2SJack F Vogel mac->in_ifs_mode = FALSE; 20998cfa0ad2SJack F Vogel E1000_WRITE_REG(hw, E1000_AIT, 0); 21008cfa0ad2SJack F Vogel } 21018cfa0ad2SJack F Vogel } 21028cfa0ad2SJack F Vogel out: 21038cfa0ad2SJack F Vogel return; 21048cfa0ad2SJack F Vogel } 21058cfa0ad2SJack F Vogel 21068cfa0ad2SJack F Vogel /** 21078cfa0ad2SJack F Vogel * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings 21088cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 21098cfa0ad2SJack F Vogel * 21108cfa0ad2SJack F Vogel * Verify that when not using auto-negotiation that MDI/MDIx is correctly 21118cfa0ad2SJack F Vogel * set, which is forced to MDI mode only. 21128cfa0ad2SJack F Vogel **/ 21134edd8523SJack F Vogel static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw) 21148cfa0ad2SJack F Vogel { 21158cfa0ad2SJack F Vogel s32 ret_val = E1000_SUCCESS; 21168cfa0ad2SJack F Vogel 21178cfa0ad2SJack F Vogel DEBUGFUNC("e1000_validate_mdi_setting_generic"); 21188cfa0ad2SJack F Vogel 21198cfa0ad2SJack F Vogel if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { 21208cfa0ad2SJack F Vogel DEBUGOUT("Invalid MDI setting detected\n"); 21218cfa0ad2SJack F Vogel hw->phy.mdix = 1; 21228cfa0ad2SJack F Vogel ret_val = -E1000_ERR_CONFIG; 21238cfa0ad2SJack F Vogel goto out; 21248cfa0ad2SJack F Vogel } 21258cfa0ad2SJack F Vogel 21268cfa0ad2SJack F Vogel out: 21278cfa0ad2SJack F Vogel return ret_val; 21288cfa0ad2SJack F Vogel } 21298cfa0ad2SJack F Vogel 21308cfa0ad2SJack F Vogel /** 21318cfa0ad2SJack F Vogel * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register 21328cfa0ad2SJack F Vogel * @hw: pointer to the HW structure 21338cfa0ad2SJack F Vogel * @reg: 32bit register offset such as E1000_SCTL 21348cfa0ad2SJack F Vogel * @offset: register offset to write to 21358cfa0ad2SJack F Vogel * @data: data to write at register offset 21368cfa0ad2SJack F Vogel * 21378cfa0ad2SJack F Vogel * Writes an address/data control type register. There are several of these 21388cfa0ad2SJack F Vogel * and they all have the format address << 8 | data and bit 31 is polled for 21398cfa0ad2SJack F Vogel * completion. 21408cfa0ad2SJack F Vogel **/ 21418cfa0ad2SJack F Vogel s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, 21428cfa0ad2SJack F Vogel u32 offset, u8 data) 21438cfa0ad2SJack F Vogel { 21448cfa0ad2SJack F Vogel u32 i, regvalue = 0; 21458cfa0ad2SJack F Vogel s32 ret_val = E1000_SUCCESS; 21468cfa0ad2SJack F Vogel 21478cfa0ad2SJack F Vogel DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic"); 21488cfa0ad2SJack F Vogel 21498cfa0ad2SJack F Vogel /* Set up the address and data */ 21508cfa0ad2SJack F Vogel regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); 21518cfa0ad2SJack F Vogel E1000_WRITE_REG(hw, reg, regvalue); 21528cfa0ad2SJack F Vogel 21538cfa0ad2SJack F Vogel /* Poll the ready bit to see if the MDI read completed */ 21548cfa0ad2SJack F Vogel for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { 21558cfa0ad2SJack F Vogel usec_delay(5); 21568cfa0ad2SJack F Vogel regvalue = E1000_READ_REG(hw, reg); 21578cfa0ad2SJack F Vogel if (regvalue & E1000_GEN_CTL_READY) 21588cfa0ad2SJack F Vogel break; 21598cfa0ad2SJack F Vogel } 21608cfa0ad2SJack F Vogel if (!(regvalue & E1000_GEN_CTL_READY)) { 21618cfa0ad2SJack F Vogel DEBUGOUT1("Reg %08x did not indicate ready\n", reg); 21628cfa0ad2SJack F Vogel ret_val = -E1000_ERR_PHY; 21638cfa0ad2SJack F Vogel goto out; 21648cfa0ad2SJack F Vogel } 21658cfa0ad2SJack F Vogel 21668cfa0ad2SJack F Vogel out: 21678cfa0ad2SJack F Vogel return ret_val; 21688cfa0ad2SJack F Vogel } 2169