1 /*- 2 * Copyright (c) 2016 Matt Macy <mmacy@nextbsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* $FreeBSD$ */ 28 #include "if_em.h" 29 #include <sys/sbuf.h> 30 #include <machine/_inttypes.h> 31 32 #define em_mac_min e1000_82547 33 #define igb_mac_min e1000_82575 34 35 /********************************************************************* 36 * Driver version: 37 *********************************************************************/ 38 char em_driver_version[] = "7.6.1-k"; 39 40 /********************************************************************* 41 * PCI Device ID Table 42 * 43 * Used by probe to select devices to load on 44 * Last field stores an index into e1000_strings 45 * Last entry must be all 0s 46 * 47 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 48 *********************************************************************/ 49 50 static pci_vendor_info_t em_vendor_info_array[] = 51 { 52 /* Intel(R) PRO/1000 Network Connection - Legacy em*/ 53 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) PRO/1000 Network Connection"), 54 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) PRO/1000 Network Connection"), 55 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) PRO/1000 Network Connection"), 56 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) PRO/1000 Network Connection"), 57 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) PRO/1000 Network Connection"), 58 59 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) PRO/1000 Network Connection"), 60 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) PRO/1000 Network Connection"), 61 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) PRO/1000 Network Connection"), 62 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 63 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) PRO/1000 Network Connection"), 64 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) PRO/1000 Network Connection"), 65 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 66 67 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) PRO/1000 Network Connection"), 68 69 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) PRO/1000 Network Connection"), 70 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) PRO/1000 Network Connection"), 71 72 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) PRO/1000 Network Connection"), 73 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) PRO/1000 Network Connection"), 74 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) PRO/1000 Network Connection"), 75 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) PRO/1000 Network Connection"), 76 77 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) PRO/1000 Network Connection"), 78 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) PRO/1000 Network Connection"), 79 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) PRO/1000 Network Connection"), 80 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) PRO/1000 Network Connection"), 81 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) PRO/1000 Network Connection"), 82 83 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) PRO/1000 Network Connection"), 84 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) PRO/1000 Network Connection"), 85 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 86 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) PRO/1000 Network Connection"), 87 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) PRO/1000 Network Connection"), 88 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) PRO/1000 Network Connection"), 89 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) PRO/1000 Network Connection"), 90 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 91 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) PRO/1000 Network Connection"), 92 93 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) PRO/1000 Network Connection"), 94 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 95 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) PRO/1000 Network Connection"), 96 97 /* Intel(R) PRO/1000 Network Connection - em */ 98 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 Network Connection"), 99 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 Network Connection"), 100 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 Network Connection"), 101 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 Network Connection"), 102 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 Network Connection"), 103 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 104 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 Network Connection"), 105 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 Network Connection"), 106 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 107 PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 Network Connection"), 108 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 Network Connection"), 109 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 Network Connection"), 110 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 Network Connection"), 111 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 Network Connection"), 112 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 Network Connection"), 113 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 Network Connection"), 114 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) PRO/1000 Network Connection"), 115 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) PRO/1000 Network Connection"), 116 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) PRO/1000 Network Connection"), 117 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) PRO/1000 Network Connection"), 118 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) PRO/1000 Network Connection"), 119 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"), 120 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) PRO/1000 Network Connection"), 121 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) PRO/1000 Network Connection"), 122 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) PRO/1000 Network Connection"), 123 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) PRO/1000 Network Connection"), 124 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) PRO/1000 Network Connection"), 125 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) PRO/1000 Network Connection"), 126 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) PRO/1000 Network Connection"), 127 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"), 128 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) PRO/1000 Network Connection"), 129 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) PRO/1000 Network Connection"), 130 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) PRO/1000 Network Connection"), 131 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) PRO/1000 Network Connection"), 132 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) PRO/1000 Network Connection"), 133 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) PRO/1000 Network Connection"), 134 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) PRO/1000 Network Connection"), 135 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) PRO/1000 Network Connection"), 136 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) PRO/1000 Network Connection"), 137 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) PRO/1000 Network Connection"), 138 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) PRO/1000 Network Connection"), 139 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) PRO/1000 Network Connection"), 140 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) PRO/1000 Network Connection"), 141 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) PRO/1000 Network Connection"), 142 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) PRO/1000 Network Connection"), 143 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) PRO/1000 Network Connection"), 144 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) PRO/1000 Network Connection"), 145 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) PRO/1000 Network Connection"), 146 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) PRO/1000 Network Connection"), 147 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) PRO/1000 Network Connection"), 148 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) PRO/1000 Network Connection"), 149 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) PRO/1000 Network Connection"), 150 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) PRO/1000 Network Connection"), 151 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) PRO/1000 Network Connection"), 152 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) PRO/1000 Network Connection"), 153 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) PRO/1000 Network Connection"), 154 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) PRO/1000 Network Connection"), 155 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) PRO/1000 Network Connection"), 156 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) PRO/1000 Network Connection"), 157 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) PRO/1000 Network Connection"), 158 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) PRO/1000 Network Connection"), 159 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) PRO/1000 Network Connection"), 160 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) PRO/1000 Network Connection"), 161 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) PRO/1000 Network Connection"), 162 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) PRO/1000 Network Connection"), 163 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) PRO/1000 Network Connection"), 164 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) PRO/1000 Network Connection"), 165 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) PRO/1000 Network Connection"), 166 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) PRO/1000 Network Connection"), 167 /* required last entry */ 168 PVID_END 169 }; 170 171 static pci_vendor_info_t igb_vendor_info_array[] = 172 { 173 /* Intel(R) PRO/1000 Network Connection - igb */ 174 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 175 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 176 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 177 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 PCI-Express Network Driver"), 178 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 179 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 180 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 181 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 182 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 PCI-Express Network Driver"), 183 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 184 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 PCI-Express Network Driver"), 185 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"), 186 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 187 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 188 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 189 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 190 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) PRO/1000 PCI-Express Network Driver"), 191 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 192 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 193 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 194 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) PRO/1000 PCI-Express Network Driver"), 195 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) PRO/1000 PCI-Express Network Driver"), 196 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 197 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 198 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 199 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 200 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"), 201 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 202 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) PRO/1000 PCI-Express Network Driver"), 203 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) PRO/1000 PCI-Express Network Driver"), 204 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 205 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 206 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 207 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 208 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 209 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 210 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 211 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 212 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 213 /* required last entry */ 214 PVID_END 215 }; 216 217 /********************************************************************* 218 * Function prototypes 219 *********************************************************************/ 220 static void *em_register(device_t dev); 221 static void *igb_register(device_t dev); 222 static int em_if_attach_pre(if_ctx_t ctx); 223 static int em_if_attach_post(if_ctx_t ctx); 224 static int em_if_detach(if_ctx_t ctx); 225 static int em_if_shutdown(if_ctx_t ctx); 226 static int em_if_suspend(if_ctx_t ctx); 227 static int em_if_resume(if_ctx_t ctx); 228 229 static int em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets); 230 static int em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets); 231 static void em_if_queues_free(if_ctx_t ctx); 232 233 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 234 static void em_if_init(if_ctx_t ctx); 235 static void em_if_stop(if_ctx_t ctx); 236 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 237 static int em_if_media_change(if_ctx_t ctx); 238 static int em_if_mtu_set(if_ctx_t ctx, uint32_t mtu); 239 static void em_if_timer(if_ctx_t ctx, uint16_t qid); 240 static void em_if_vlan_register(if_ctx_t ctx, u16 vtag); 241 static void em_if_vlan_unregister(if_ctx_t ctx, u16 vtag); 242 243 static void em_identify_hardware(if_ctx_t ctx); 244 static int em_allocate_pci_resources(if_ctx_t ctx); 245 static void em_free_pci_resources(if_ctx_t ctx); 246 static void em_reset(if_ctx_t ctx); 247 static int em_setup_interface(if_ctx_t ctx); 248 static int em_setup_msix(if_ctx_t ctx); 249 250 static void em_initialize_transmit_unit(if_ctx_t ctx); 251 static void em_initialize_receive_unit(if_ctx_t ctx); 252 253 static void em_if_enable_intr(if_ctx_t ctx); 254 static void em_if_disable_intr(if_ctx_t ctx); 255 static int em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid); 256 static int em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid); 257 static void em_if_multi_set(if_ctx_t ctx); 258 static void em_if_update_admin_status(if_ctx_t ctx); 259 static void em_if_debug(if_ctx_t ctx); 260 static void em_update_stats_counters(struct adapter *); 261 static void em_add_hw_stats(struct adapter *adapter); 262 static int em_if_set_promisc(if_ctx_t ctx, int flags); 263 static void em_setup_vlan_hw_support(struct adapter *); 264 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 265 static void em_print_nvm_info(struct adapter *); 266 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 267 static int em_get_rs(SYSCTL_HANDLER_ARGS); 268 static void em_print_debug_info(struct adapter *); 269 static int em_is_valid_ether_addr(u8 *); 270 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 271 static void em_add_int_delay_sysctl(struct adapter *, const char *, 272 const char *, struct em_int_delay_info *, int, int); 273 /* Management and WOL Support */ 274 static void em_init_manageability(struct adapter *); 275 static void em_release_manageability(struct adapter *); 276 static void em_get_hw_control(struct adapter *); 277 static void em_release_hw_control(struct adapter *); 278 static void em_get_wakeup(if_ctx_t ctx); 279 static void em_enable_wakeup(if_ctx_t ctx); 280 static int em_enable_phy_wakeup(struct adapter *); 281 static void em_disable_aspm(struct adapter *); 282 283 int em_intr(void *arg); 284 static void em_disable_promisc(if_ctx_t ctx); 285 286 /* MSIX handlers */ 287 static int em_if_msix_intr_assign(if_ctx_t, int); 288 static int em_msix_link(void *); 289 static void em_handle_link(void *context); 290 291 static void em_enable_vectors_82574(if_ctx_t); 292 293 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 294 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 295 static void em_if_led_func(if_ctx_t ctx, int onoff); 296 297 static int em_get_regs(SYSCTL_HANDLER_ARGS); 298 299 static void lem_smartspeed(struct adapter *adapter); 300 static void igb_configure_queues(struct adapter *adapter); 301 302 303 /********************************************************************* 304 * FreeBSD Device Interface Entry Points 305 *********************************************************************/ 306 static device_method_t em_methods[] = { 307 /* Device interface */ 308 DEVMETHOD(device_register, em_register), 309 DEVMETHOD(device_probe, iflib_device_probe), 310 DEVMETHOD(device_attach, iflib_device_attach), 311 DEVMETHOD(device_detach, iflib_device_detach), 312 DEVMETHOD(device_shutdown, iflib_device_shutdown), 313 DEVMETHOD(device_suspend, iflib_device_suspend), 314 DEVMETHOD(device_resume, iflib_device_resume), 315 DEVMETHOD_END 316 }; 317 318 static device_method_t igb_methods[] = { 319 /* Device interface */ 320 DEVMETHOD(device_register, igb_register), 321 DEVMETHOD(device_probe, iflib_device_probe), 322 DEVMETHOD(device_attach, iflib_device_attach), 323 DEVMETHOD(device_detach, iflib_device_detach), 324 DEVMETHOD(device_shutdown, iflib_device_shutdown), 325 DEVMETHOD(device_suspend, iflib_device_suspend), 326 DEVMETHOD(device_resume, iflib_device_resume), 327 DEVMETHOD_END 328 }; 329 330 331 static driver_t em_driver = { 332 "em", em_methods, sizeof(struct adapter), 333 }; 334 335 static devclass_t em_devclass; 336 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0); 337 338 MODULE_DEPEND(em, pci, 1, 1, 1); 339 MODULE_DEPEND(em, ether, 1, 1, 1); 340 MODULE_DEPEND(em, iflib, 1, 1, 1); 341 342 static driver_t igb_driver = { 343 "igb", igb_methods, sizeof(struct adapter), 344 }; 345 346 static devclass_t igb_devclass; 347 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0); 348 349 MODULE_DEPEND(igb, pci, 1, 1, 1); 350 MODULE_DEPEND(igb, ether, 1, 1, 1); 351 MODULE_DEPEND(igb, iflib, 1, 1, 1); 352 353 354 static device_method_t em_if_methods[] = { 355 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 356 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 357 DEVMETHOD(ifdi_detach, em_if_detach), 358 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 359 DEVMETHOD(ifdi_suspend, em_if_suspend), 360 DEVMETHOD(ifdi_resume, em_if_resume), 361 DEVMETHOD(ifdi_init, em_if_init), 362 DEVMETHOD(ifdi_stop, em_if_stop), 363 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 364 DEVMETHOD(ifdi_intr_enable, em_if_enable_intr), 365 DEVMETHOD(ifdi_intr_disable, em_if_disable_intr), 366 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 367 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 368 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 369 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 370 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 371 DEVMETHOD(ifdi_media_status, em_if_media_status), 372 DEVMETHOD(ifdi_media_change, em_if_media_change), 373 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 374 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 375 DEVMETHOD(ifdi_timer, em_if_timer), 376 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 377 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 378 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 379 DEVMETHOD(ifdi_led_func, em_if_led_func), 380 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable), 381 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable), 382 DEVMETHOD(ifdi_debug, em_if_debug), 383 DEVMETHOD_END 384 }; 385 386 /* 387 * note that if (adapter->msix_mem) is replaced by: 388 * if (adapter->intr_type == IFLIB_INTR_MSIX) 389 */ 390 static driver_t em_if_driver = { 391 "em_if", em_if_methods, sizeof(struct adapter) 392 }; 393 394 /********************************************************************* 395 * Tunable default values. 396 *********************************************************************/ 397 398 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 399 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 400 #define M_TSO_LEN 66 401 402 #define MAX_INTS_PER_SEC 8000 403 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256)) 404 405 /* Allow common code without TSO */ 406 #ifndef CSUM_TSO 407 #define CSUM_TSO 0 408 #endif 409 410 #define TSO_WORKAROUND 4 411 412 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD, 0, "EM driver parameters"); 413 414 static int em_disable_crc_stripping = 0; 415 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 416 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 417 418 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 419 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 420 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt, 421 0, "Default transmit interrupt delay in usecs"); 422 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt, 423 0, "Default receive interrupt delay in usecs"); 424 425 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 426 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 427 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 428 &em_tx_abs_int_delay_dflt, 0, 429 "Default transmit interrupt delay limit in usecs"); 430 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 431 &em_rx_abs_int_delay_dflt, 0, 432 "Default receive interrupt delay limit in usecs"); 433 434 static int em_smart_pwr_down = FALSE; 435 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down, 436 0, "Set to true to leave smart power down enabled on newer adapters"); 437 438 /* Controls whether promiscuous also shows bad packets */ 439 static int em_debug_sbp = TRUE; 440 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 441 "Show bad packets in promiscuous mode"); 442 443 /* How many packets rxeof tries to clean at a time */ 444 static int em_rx_process_limit = 100; 445 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN, 446 &em_rx_process_limit, 0, 447 "Maximum number of received packets to process " 448 "at a time, -1 means unlimited"); 449 450 /* Energy efficient ethernet - default to OFF */ 451 static int eee_setting = 1; 452 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 453 "Enable Energy Efficient Ethernet"); 454 455 /* 456 ** Tuneable Interrupt rate 457 */ 458 static int em_max_interrupt_rate = 8000; 459 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 460 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 461 462 463 464 /* Global used in WOL setup with multiport cards */ 465 static int global_quad_port_a = 0; 466 467 extern struct if_txrx igb_txrx; 468 extern struct if_txrx em_txrx; 469 extern struct if_txrx lem_txrx; 470 471 static struct if_shared_ctx em_sctx_init = { 472 .isc_magic = IFLIB_MAGIC, 473 .isc_q_align = PAGE_SIZE, 474 .isc_tx_maxsize = EM_TSO_SIZE, 475 .isc_tx_maxsegsize = PAGE_SIZE, 476 .isc_rx_maxsize = MJUM9BYTES, 477 .isc_rx_nsegments = 1, 478 .isc_rx_maxsegsize = MJUM9BYTES, 479 .isc_nfl = 1, 480 .isc_nrxqs = 1, 481 .isc_ntxqs = 1, 482 .isc_admin_intrcnt = 1, 483 .isc_vendor_info = em_vendor_info_array, 484 .isc_driver_version = em_driver_version, 485 .isc_driver = &em_if_driver, 486 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP, 487 488 .isc_nrxd_min = {EM_MIN_RXD}, 489 .isc_ntxd_min = {EM_MIN_TXD}, 490 .isc_nrxd_max = {EM_MAX_RXD}, 491 .isc_ntxd_max = {EM_MAX_TXD}, 492 .isc_nrxd_default = {EM_DEFAULT_RXD}, 493 .isc_ntxd_default = {EM_DEFAULT_TXD}, 494 }; 495 496 if_shared_ctx_t em_sctx = &em_sctx_init; 497 498 499 static struct if_shared_ctx igb_sctx_init = { 500 .isc_magic = IFLIB_MAGIC, 501 .isc_q_align = PAGE_SIZE, 502 .isc_tx_maxsize = EM_TSO_SIZE, 503 .isc_tx_maxsegsize = PAGE_SIZE, 504 .isc_rx_maxsize = MJUM9BYTES, 505 .isc_rx_nsegments = 1, 506 .isc_rx_maxsegsize = MJUM9BYTES, 507 .isc_nfl = 1, 508 .isc_nrxqs = 1, 509 .isc_ntxqs = 1, 510 .isc_admin_intrcnt = 1, 511 .isc_vendor_info = igb_vendor_info_array, 512 .isc_driver_version = em_driver_version, 513 .isc_driver = &em_if_driver, 514 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP, 515 516 .isc_nrxd_min = {EM_MIN_RXD}, 517 .isc_ntxd_min = {EM_MIN_TXD}, 518 .isc_nrxd_max = {EM_MAX_RXD}, 519 .isc_ntxd_max = {EM_MAX_TXD}, 520 .isc_nrxd_default = {EM_DEFAULT_RXD}, 521 .isc_ntxd_default = {EM_DEFAULT_TXD}, 522 }; 523 524 if_shared_ctx_t igb_sctx = &igb_sctx_init; 525 526 /***************************************************************** 527 * 528 * Dump Registers 529 * 530 ****************************************************************/ 531 #define IGB_REGS_LEN 739 532 533 static int em_get_regs(SYSCTL_HANDLER_ARGS) 534 { 535 struct adapter *adapter = (struct adapter *)arg1; 536 struct e1000_hw *hw = &adapter->hw; 537 538 struct sbuf *sb; 539 u32 *regs_buff = (u32 *)malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_NOWAIT); 540 int rc; 541 542 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 543 544 rc = sysctl_wire_old_buffer(req, 0); 545 MPASS(rc == 0); 546 if (rc != 0) 547 return (rc); 548 549 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 550 MPASS(sb != NULL); 551 if (sb == NULL) 552 return (ENOMEM); 553 554 /* General Registers */ 555 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 556 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 557 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 558 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 559 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 560 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 561 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 562 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 563 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 564 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 565 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 566 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 567 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 568 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 569 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 570 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 571 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 572 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 573 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 574 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 575 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 576 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 577 578 sbuf_printf(sb, "General Registers\n"); 579 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 580 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 581 sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]); 582 583 sbuf_printf(sb, "Interrupt Registers\n"); 584 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 585 586 sbuf_printf(sb, "RX Registers\n"); 587 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 588 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 589 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 590 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 591 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 592 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 593 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 594 595 sbuf_printf(sb, "TX Registers\n"); 596 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 597 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 598 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 599 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 600 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 601 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 602 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 603 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 604 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 605 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 606 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 607 608 #ifdef DUMP_DESCS 609 { 610 if_softc_ctx_t scctx = adapter->shared; 611 struct rx_ring *rxr = &rx_que->rxr; 612 struct tx_ring *txr = &tx_que->txr; 613 int ntxd = scctx->isc_ntxd[0]; 614 int nrxd = scctx->isc_nrxd[0]; 615 int j; 616 617 for (j = 0; j < nrxd; j++) { 618 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 619 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 620 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 621 } 622 623 for (j = 0; j < min(ntxd, 256); j++) { 624 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 625 626 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 627 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 628 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0); 629 630 } 631 } 632 #endif 633 634 rc = sbuf_finish(sb); 635 sbuf_delete(sb); 636 return(rc); 637 } 638 639 static void * 640 em_register(device_t dev) 641 { 642 return (em_sctx); 643 } 644 645 static void * 646 igb_register(device_t dev) 647 { 648 return (igb_sctx); 649 } 650 651 static int 652 em_set_num_queues(if_ctx_t ctx) 653 { 654 struct adapter *adapter = iflib_get_softc(ctx); 655 int maxqueues; 656 657 /* Sanity check based on HW */ 658 switch (adapter->hw.mac.type) { 659 case e1000_82576: 660 case e1000_82580: 661 case e1000_i350: 662 case e1000_i354: 663 maxqueues = 8; 664 break; 665 case e1000_i210: 666 case e1000_82575: 667 maxqueues = 4; 668 break; 669 case e1000_i211: 670 case e1000_82574: 671 maxqueues = 2; 672 break; 673 default: 674 maxqueues = 1; 675 break; 676 } 677 678 return (maxqueues); 679 } 680 681 682 #define EM_CAPS \ 683 IFCAP_TSO4 | IFCAP_TXCSUM | IFCAP_LRO | IFCAP_RXCSUM | IFCAP_VLAN_HWFILTER | IFCAP_WOL_MAGIC | \ 684 IFCAP_WOL_MCAST | IFCAP_WOL | IFCAP_VLAN_HWTSO | IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | \ 685 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU; 686 687 #define IGB_CAPS \ 688 IFCAP_TSO4 | IFCAP_TXCSUM | IFCAP_LRO | IFCAP_RXCSUM | IFCAP_VLAN_HWFILTER | IFCAP_WOL_MAGIC | \ 689 IFCAP_WOL_MCAST | IFCAP_WOL | IFCAP_VLAN_HWTSO | IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM | \ 690 IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU | IFCAP_TXCSUM_IPV6 | IFCAP_HWCSUM_IPV6 | IFCAP_JUMBO_MTU; 691 692 /********************************************************************* 693 * Device initialization routine 694 * 695 * The attach entry point is called when the driver is being loaded. 696 * This routine identifies the type of hardware, allocates all resources 697 * and initializes the hardware. 698 * 699 * return 0 on success, positive on failure 700 *********************************************************************/ 701 702 static int 703 em_if_attach_pre(if_ctx_t ctx) 704 { 705 struct adapter *adapter; 706 if_softc_ctx_t scctx; 707 device_t dev; 708 struct e1000_hw *hw; 709 int error = 0; 710 711 INIT_DEBUGOUT("em_if_attach_pre begin"); 712 dev = iflib_get_dev(ctx); 713 adapter = iflib_get_softc(ctx); 714 715 if (resource_disabled("em", device_get_unit(dev))) { 716 device_printf(dev, "Disabled by device hint\n"); 717 return (ENXIO); 718 } 719 720 adapter->ctx = ctx; 721 adapter->dev = adapter->osdep.dev = dev; 722 scctx = adapter->shared = iflib_get_softc_ctx(ctx); 723 adapter->media = iflib_get_media(ctx); 724 hw = &adapter->hw; 725 726 adapter->tx_process_limit = scctx->isc_ntxd[0]; 727 728 /* SYSCTL stuff */ 729 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 730 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 731 OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 732 em_sysctl_nvm_info, "I", "NVM Information"); 733 734 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 735 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 736 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 737 em_sysctl_debug_info, "I", "Debug Information"); 738 739 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 740 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 741 OID_AUTO, "fc", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 742 em_set_flowcntl, "I", "Flow Control"); 743 744 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 745 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 746 OID_AUTO, "reg_dump", CTLTYPE_STRING | CTLFLAG_RD, adapter, 0, 747 em_get_regs, "A", "Dump Registers"); 748 749 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 750 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 751 OID_AUTO, "rs_dump", CTLTYPE_INT | CTLFLAG_RW, adapter, 0, 752 em_get_rs, "I", "Dump RS indexes"); 753 754 /* Determine hardware and mac info */ 755 em_identify_hardware(ctx); 756 757 /* Set isc_msix_bar */ 758 scctx->isc_msix_bar = PCIR_BAR(EM_MSIX_BAR); 759 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 760 scctx->isc_tx_tso_segments_max = scctx->isc_tx_nsegments; 761 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 762 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 763 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 764 device_printf(dev, "attach_pre capping queues at %d\n", scctx->isc_ntxqsets_max); 765 766 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 767 768 769 if (adapter->hw.mac.type >= igb_mac_min) { 770 int try_second_bar; 771 772 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 773 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 774 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); 775 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); 776 scctx->isc_txrx = &igb_txrx; 777 scctx->isc_capenable = IGB_CAPS; 778 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | CSUM_IP6_TCP \ 779 | CSUM_IP6_UDP | CSUM_IP6_TCP; 780 if (adapter->hw.mac.type != e1000_82575) 781 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 782 783 /* 784 ** Some new devices, as with ixgbe, now may 785 ** use a different BAR, so we need to keep 786 ** track of which is used. 787 */ 788 try_second_bar = pci_read_config(dev, scctx->isc_msix_bar, 4); 789 if (try_second_bar == 0) 790 scctx->isc_msix_bar += 4; 791 792 } else if (adapter->hw.mac.type >= em_mac_min) { 793 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 794 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 795 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 796 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); 797 scctx->isc_txrx = &em_txrx; 798 scctx->isc_capenable = EM_CAPS; 799 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 800 } else { 801 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 802 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 803 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 804 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); 805 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 806 scctx->isc_txrx = &lem_txrx; 807 scctx->isc_capenable = EM_CAPS; 808 if (adapter->hw.mac.type < e1000_82543) 809 scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM); 810 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 811 scctx->isc_msix_bar = 0; 812 } 813 814 /* Setup PCI resources */ 815 if (em_allocate_pci_resources(ctx)) { 816 device_printf(dev, "Allocation of PCI resources failed\n"); 817 error = ENXIO; 818 goto err_pci; 819 } 820 821 /* 822 ** For ICH8 and family we need to 823 ** map the flash memory, and this 824 ** must happen after the MAC is 825 ** identified 826 */ 827 if ((hw->mac.type == e1000_ich8lan) || 828 (hw->mac.type == e1000_ich9lan) || 829 (hw->mac.type == e1000_ich10lan) || 830 (hw->mac.type == e1000_pchlan) || 831 (hw->mac.type == e1000_pch2lan) || 832 (hw->mac.type == e1000_pch_lpt)) { 833 int rid = EM_BAR_TYPE_FLASH; 834 adapter->flash = bus_alloc_resource_any(dev, 835 SYS_RES_MEMORY, &rid, RF_ACTIVE); 836 if (adapter->flash == NULL) { 837 device_printf(dev, "Mapping of Flash failed\n"); 838 error = ENXIO; 839 goto err_pci; 840 } 841 /* This is used in the shared code */ 842 hw->flash_address = (u8 *)adapter->flash; 843 adapter->osdep.flash_bus_space_tag = 844 rman_get_bustag(adapter->flash); 845 adapter->osdep.flash_bus_space_handle = 846 rman_get_bushandle(adapter->flash); 847 } 848 /* 849 ** In the new SPT device flash is not a 850 ** separate BAR, rather it is also in BAR0, 851 ** so use the same tag and an offset handle for the 852 ** FLASH read/write macros in the shared code. 853 */ 854 else if (hw->mac.type == e1000_pch_spt) { 855 adapter->osdep.flash_bus_space_tag = 856 adapter->osdep.mem_bus_space_tag; 857 adapter->osdep.flash_bus_space_handle = 858 adapter->osdep.mem_bus_space_handle 859 + E1000_FLASH_BASE_ADDR; 860 } 861 862 /* Do Shared Code initialization */ 863 error = e1000_setup_init_funcs(hw, TRUE); 864 if (error) { 865 device_printf(dev, "Setup of Shared code failed, error %d\n", 866 error); 867 error = ENXIO; 868 goto err_pci; 869 } 870 871 em_setup_msix(ctx); 872 e1000_get_bus_info(hw); 873 874 /* Set up some sysctls for the tunable interrupt delays */ 875 em_add_int_delay_sysctl(adapter, "rx_int_delay", 876 "receive interrupt delay in usecs", &adapter->rx_int_delay, 877 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 878 em_add_int_delay_sysctl(adapter, "tx_int_delay", 879 "transmit interrupt delay in usecs", &adapter->tx_int_delay, 880 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 881 em_add_int_delay_sysctl(adapter, "rx_abs_int_delay", 882 "receive interrupt delay limit in usecs", 883 &adapter->rx_abs_int_delay, 884 E1000_REGISTER(hw, E1000_RADV), 885 em_rx_abs_int_delay_dflt); 886 em_add_int_delay_sysctl(adapter, "tx_abs_int_delay", 887 "transmit interrupt delay limit in usecs", 888 &adapter->tx_abs_int_delay, 889 E1000_REGISTER(hw, E1000_TADV), 890 em_tx_abs_int_delay_dflt); 891 em_add_int_delay_sysctl(adapter, "itr", 892 "interrupt delay limit in usecs/4", 893 &adapter->tx_itr, 894 E1000_REGISTER(hw, E1000_ITR), 895 DEFAULT_ITR); 896 897 hw->mac.autoneg = DO_AUTO_NEG; 898 hw->phy.autoneg_wait_to_complete = FALSE; 899 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 900 901 if (adapter->hw.mac.type < em_mac_min) { 902 e1000_init_script_state_82541(&adapter->hw, TRUE); 903 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE); 904 } 905 /* Copper options */ 906 if (hw->phy.media_type == e1000_media_type_copper) { 907 hw->phy.mdix = AUTO_ALL_MODES; 908 hw->phy.disable_polarity_correction = FALSE; 909 hw->phy.ms_type = EM_MASTER_SLAVE; 910 } 911 912 /* 913 * Set the frame limits assuming 914 * standard ethernet sized frames. 915 */ 916 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 917 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 918 919 /* 920 * This controls when hardware reports transmit completion 921 * status. 922 */ 923 hw->mac.report_tx_early = 1; 924 925 /* Allocate multicast array memory. */ 926 adapter->mta = malloc(sizeof(u8) * ETH_ADDR_LEN * 927 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 928 if (adapter->mta == NULL) { 929 device_printf(dev, "Can not allocate multicast setup array\n"); 930 error = ENOMEM; 931 goto err_late; 932 } 933 934 /* Check SOL/IDER usage */ 935 if (e1000_check_reset_block(hw)) 936 device_printf(dev, "PHY reset is blocked" 937 " due to SOL/IDER session.\n"); 938 939 /* Sysctl for setting Energy Efficient Ethernet */ 940 hw->dev_spec.ich8lan.eee_disable = eee_setting; 941 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 942 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 943 OID_AUTO, "eee_control", CTLTYPE_INT|CTLFLAG_RW, 944 adapter, 0, em_sysctl_eee, "I", 945 "Disable Energy Efficient Ethernet"); 946 947 /* 948 ** Start from a known state, this is 949 ** important in reading the nvm and 950 ** mac from that. 951 */ 952 e1000_reset_hw(hw); 953 954 /* Make sure we have a good EEPROM before we read from it */ 955 if (e1000_validate_nvm_checksum(hw) < 0) { 956 /* 957 ** Some PCI-E parts fail the first check due to 958 ** the link being in sleep state, call it again, 959 ** if it fails a second time its a real issue. 960 */ 961 if (e1000_validate_nvm_checksum(hw) < 0) { 962 device_printf(dev, 963 "The EEPROM Checksum Is Not Valid\n"); 964 error = EIO; 965 goto err_late; 966 } 967 } 968 969 /* Copy the permanent MAC address out of the EEPROM */ 970 if (e1000_read_mac_addr(hw) < 0) { 971 device_printf(dev, "EEPROM read error while reading MAC" 972 " address\n"); 973 error = EIO; 974 goto err_late; 975 } 976 977 if (!em_is_valid_ether_addr(hw->mac.addr)) { 978 device_printf(dev, "Invalid MAC address\n"); 979 error = EIO; 980 goto err_late; 981 } 982 983 /* Disable ULP support */ 984 e1000_disable_ulp_lpt_lp(hw, TRUE); 985 986 /* 987 * Get Wake-on-Lan and Management info for later use 988 */ 989 em_get_wakeup(ctx); 990 991 iflib_set_mac(ctx, hw->mac.addr); 992 993 return (0); 994 995 err_late: 996 em_release_hw_control(adapter); 997 err_pci: 998 em_free_pci_resources(ctx); 999 free(adapter->mta, M_DEVBUF); 1000 1001 return (error); 1002 } 1003 1004 static int 1005 em_if_attach_post(if_ctx_t ctx) 1006 { 1007 struct adapter *adapter = iflib_get_softc(ctx); 1008 struct e1000_hw *hw = &adapter->hw; 1009 int error = 0; 1010 1011 /* Setup OS specific network interface */ 1012 error = em_setup_interface(ctx); 1013 if (error != 0) { 1014 goto err_late; 1015 } 1016 1017 em_reset(ctx); 1018 1019 /* Initialize statistics */ 1020 em_update_stats_counters(adapter); 1021 hw->mac.get_link_status = 1; 1022 em_if_update_admin_status(ctx); 1023 em_add_hw_stats(adapter); 1024 1025 /* Non-AMT based hardware can now take control from firmware */ 1026 if (adapter->has_manage && !adapter->has_amt) 1027 em_get_hw_control(adapter); 1028 1029 INIT_DEBUGOUT("em_if_attach_post: end"); 1030 1031 return (error); 1032 1033 err_late: 1034 em_release_hw_control(adapter); 1035 em_free_pci_resources(ctx); 1036 em_if_queues_free(ctx); 1037 free(adapter->mta, M_DEVBUF); 1038 1039 return (error); 1040 } 1041 1042 /********************************************************************* 1043 * Device removal routine 1044 * 1045 * The detach entry point is called when the driver is being removed. 1046 * This routine stops the adapter and deallocates all the resources 1047 * that were allocated for driver operation. 1048 * 1049 * return 0 on success, positive on failure 1050 *********************************************************************/ 1051 1052 static int 1053 em_if_detach(if_ctx_t ctx) 1054 { 1055 struct adapter *adapter = iflib_get_softc(ctx); 1056 1057 INIT_DEBUGOUT("em_detach: begin"); 1058 1059 e1000_phy_hw_reset(&adapter->hw); 1060 1061 em_release_manageability(adapter); 1062 em_release_hw_control(adapter); 1063 em_free_pci_resources(ctx); 1064 1065 return (0); 1066 } 1067 1068 /********************************************************************* 1069 * 1070 * Shutdown entry point 1071 * 1072 **********************************************************************/ 1073 1074 static int 1075 em_if_shutdown(if_ctx_t ctx) 1076 { 1077 return em_if_suspend(ctx); 1078 } 1079 1080 /* 1081 * Suspend/resume device methods. 1082 */ 1083 static int 1084 em_if_suspend(if_ctx_t ctx) 1085 { 1086 struct adapter *adapter = iflib_get_softc(ctx); 1087 1088 em_release_manageability(adapter); 1089 em_release_hw_control(adapter); 1090 em_enable_wakeup(ctx); 1091 return (0); 1092 } 1093 1094 static int 1095 em_if_resume(if_ctx_t ctx) 1096 { 1097 struct adapter *adapter = iflib_get_softc(ctx); 1098 1099 if (adapter->hw.mac.type == e1000_pch2lan) 1100 e1000_resume_workarounds_pchlan(&adapter->hw); 1101 em_if_init(ctx); 1102 em_init_manageability(adapter); 1103 1104 return(0); 1105 } 1106 1107 static int 1108 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1109 { 1110 int max_frame_size; 1111 struct adapter *adapter = iflib_get_softc(ctx); 1112 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1113 1114 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1115 1116 switch (adapter->hw.mac.type) { 1117 case e1000_82571: 1118 case e1000_82572: 1119 case e1000_ich9lan: 1120 case e1000_ich10lan: 1121 case e1000_pch2lan: 1122 case e1000_pch_lpt: 1123 case e1000_pch_spt: 1124 case e1000_82574: 1125 case e1000_82583: 1126 case e1000_80003es2lan: 1127 /* 9K Jumbo Frame size */ 1128 max_frame_size = 9234; 1129 break; 1130 case e1000_pchlan: 1131 max_frame_size = 4096; 1132 break; 1133 case e1000_82542: 1134 case e1000_ich8lan: 1135 /* Adapters that do not support jumbo frames */ 1136 max_frame_size = ETHER_MAX_LEN; 1137 break; 1138 default: 1139 if (adapter->hw.mac.type >= igb_mac_min) 1140 max_frame_size = 9234; 1141 else /* lem */ 1142 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1143 } 1144 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1145 return (EINVAL); 1146 } 1147 1148 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 1149 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1150 return (0); 1151 } 1152 1153 /********************************************************************* 1154 * Init entry point 1155 * 1156 * This routine is used in two ways. It is used by the stack as 1157 * init entry point in network interface structure. It is also used 1158 * by the driver as a hw/sw initialization routine to get to a 1159 * consistent state. 1160 * 1161 * return 0 on success, positive on failure 1162 **********************************************************************/ 1163 1164 static void 1165 em_if_init(if_ctx_t ctx) 1166 { 1167 struct adapter *adapter = iflib_get_softc(ctx); 1168 struct ifnet *ifp = iflib_get_ifp(ctx); 1169 struct em_tx_queue *tx_que; 1170 int i; 1171 INIT_DEBUGOUT("em_if_init: begin"); 1172 1173 /* Get the latest mac address, User can use a LAA */ 1174 bcopy(if_getlladdr(ifp), adapter->hw.mac.addr, 1175 ETHER_ADDR_LEN); 1176 1177 /* Put the address into the Receive Address Array */ 1178 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1179 1180 /* 1181 * With the 82571 adapter, RAR[0] may be overwritten 1182 * when the other port is reset, we make a duplicate 1183 * in RAR[14] for that eventuality, this assures 1184 * the interface continues to function. 1185 */ 1186 if (adapter->hw.mac.type == e1000_82571) { 1187 e1000_set_laa_state_82571(&adapter->hw, TRUE); 1188 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 1189 E1000_RAR_ENTRIES - 1); 1190 } 1191 1192 1193 /* Initialize the hardware */ 1194 em_reset(ctx); 1195 em_if_update_admin_status(ctx); 1196 1197 for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) { 1198 struct tx_ring *txr = &tx_que->txr; 1199 1200 txr->tx_rs_cidx = txr->tx_rs_pidx = txr->tx_cidx_processed = 0; 1201 } 1202 1203 /* Setup VLAN support, basic and offload if available */ 1204 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 1205 1206 /* Clear bad data from Rx FIFOs */ 1207 if (adapter->hw.mac.type >= igb_mac_min) 1208 e1000_rx_fifo_flush_82575(&adapter->hw); 1209 1210 /* Configure for OS presence */ 1211 em_init_manageability(adapter); 1212 1213 /* Prepare transmit descriptors and buffers */ 1214 em_initialize_transmit_unit(ctx); 1215 1216 /* Setup Multicast table */ 1217 em_if_multi_set(ctx); 1218 1219 /* 1220 * Figure out the desired mbuf 1221 * pool for doing jumbos 1222 */ 1223 if (adapter->hw.mac.max_frame_size <= 2048) 1224 adapter->rx_mbuf_sz = MCLBYTES; 1225 #ifndef CONTIGMALLOC_WORKS 1226 else 1227 adapter->rx_mbuf_sz = MJUMPAGESIZE; 1228 #else 1229 else if (adapter->hw.mac.max_frame_size <= 4096) 1230 adapter->rx_mbuf_sz = MJUMPAGESIZE; 1231 else 1232 adapter->rx_mbuf_sz = MJUM9BYTES; 1233 #endif 1234 em_initialize_receive_unit(ctx); 1235 1236 /* Use real VLAN Filter support? */ 1237 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) { 1238 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 1239 /* Use real VLAN Filter support */ 1240 em_setup_vlan_hw_support(adapter); 1241 else { 1242 u32 ctrl; 1243 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 1244 ctrl |= E1000_CTRL_VME; 1245 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 1246 } 1247 } 1248 1249 /* Don't lose promiscuous settings */ 1250 em_if_set_promisc(ctx, IFF_PROMISC); 1251 e1000_clear_hw_cntrs_base_generic(&adapter->hw); 1252 1253 /* MSI/X configuration for 82574 */ 1254 if (adapter->hw.mac.type == e1000_82574) { 1255 int tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 1256 1257 tmp |= E1000_CTRL_EXT_PBA_CLR; 1258 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp); 1259 /* Set the IVAR - interrupt vector routing. */ 1260 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, adapter->ivars); 1261 } else if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 1262 igb_configure_queues(adapter); 1263 1264 /* this clears any pending interrupts */ 1265 E1000_READ_REG(&adapter->hw, E1000_ICR); 1266 E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC); 1267 1268 /* AMT based hardware can now take control from firmware */ 1269 if (adapter->has_manage && adapter->has_amt) 1270 em_get_hw_control(adapter); 1271 1272 /* Set Energy Efficient Ethernet */ 1273 if (adapter->hw.mac.type >= igb_mac_min && 1274 adapter->hw.phy.media_type == e1000_media_type_copper) { 1275 if (adapter->hw.mac.type == e1000_i354) 1276 e1000_set_eee_i354(&adapter->hw, TRUE, TRUE); 1277 else 1278 e1000_set_eee_i350(&adapter->hw, TRUE, TRUE); 1279 } 1280 } 1281 1282 /********************************************************************* 1283 * 1284 * Fast Legacy/MSI Combined Interrupt Service routine 1285 * 1286 *********************************************************************/ 1287 int 1288 em_intr(void *arg) 1289 { 1290 struct adapter *adapter = arg; 1291 if_ctx_t ctx = adapter->ctx; 1292 u32 reg_icr; 1293 1294 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1295 1296 if (adapter->intr_type != IFLIB_INTR_LEGACY) 1297 goto skip_stray; 1298 /* Hot eject? */ 1299 if (reg_icr == 0xffffffff) 1300 return FILTER_STRAY; 1301 1302 /* Definitely not our interrupt. */ 1303 if (reg_icr == 0x0) 1304 return FILTER_STRAY; 1305 1306 /* 1307 * Starting with the 82571 chip, bit 31 should be used to 1308 * determine whether the interrupt belongs to us. 1309 */ 1310 if (adapter->hw.mac.type >= e1000_82571 && 1311 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1312 return FILTER_STRAY; 1313 1314 skip_stray: 1315 /* Link status change */ 1316 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1317 adapter->hw.mac.get_link_status = 1; 1318 iflib_admin_intr_deferred(ctx); 1319 } 1320 1321 if (reg_icr & E1000_ICR_RXO) 1322 adapter->rx_overruns++; 1323 1324 return (FILTER_SCHEDULE_THREAD); 1325 } 1326 1327 static void 1328 igb_rx_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq) 1329 { 1330 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, rxq->eims); 1331 } 1332 1333 static void 1334 em_rx_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq) 1335 { 1336 E1000_WRITE_REG(&adapter->hw, E1000_IMS, rxq->eims); 1337 } 1338 1339 static void 1340 igb_tx_enable_queue(struct adapter *adapter, struct em_tx_queue *txq) 1341 { 1342 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, txq->eims); 1343 } 1344 1345 static void 1346 em_tx_enable_queue(struct adapter *adapter, struct em_tx_queue *txq) 1347 { 1348 E1000_WRITE_REG(&adapter->hw, E1000_IMS, txq->eims); 1349 } 1350 1351 static int 1352 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1353 { 1354 struct adapter *adapter = iflib_get_softc(ctx); 1355 struct em_rx_queue *rxq = &adapter->rx_queues[rxqid]; 1356 1357 if (adapter->hw.mac.type >= igb_mac_min) 1358 igb_rx_enable_queue(adapter, rxq); 1359 else 1360 em_rx_enable_queue(adapter, rxq); 1361 return (0); 1362 } 1363 1364 static int 1365 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1366 { 1367 struct adapter *adapter = iflib_get_softc(ctx); 1368 struct em_tx_queue *txq = &adapter->tx_queues[txqid]; 1369 1370 if (adapter->hw.mac.type >= igb_mac_min) 1371 igb_tx_enable_queue(adapter, txq); 1372 else 1373 em_tx_enable_queue(adapter, txq); 1374 return (0); 1375 } 1376 1377 /********************************************************************* 1378 * 1379 * MSIX RX Interrupt Service routine 1380 * 1381 **********************************************************************/ 1382 static int 1383 em_msix_que(void *arg) 1384 { 1385 struct em_rx_queue *que = arg; 1386 1387 ++que->irqs; 1388 1389 return (FILTER_SCHEDULE_THREAD); 1390 } 1391 1392 /********************************************************************* 1393 * 1394 * MSIX Link Fast Interrupt Service routine 1395 * 1396 **********************************************************************/ 1397 static int 1398 em_msix_link(void *arg) 1399 { 1400 struct adapter *adapter = arg; 1401 u32 reg_icr; 1402 1403 ++adapter->link_irq; 1404 MPASS(adapter->hw.back != NULL); 1405 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1406 1407 if (reg_icr & E1000_ICR_RXO) 1408 adapter->rx_overruns++; 1409 1410 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1411 em_handle_link(adapter->ctx); 1412 } else { 1413 E1000_WRITE_REG(&adapter->hw, E1000_IMS, 1414 EM_MSIX_LINK | E1000_IMS_LSC); 1415 if (adapter->hw.mac.type >= igb_mac_min) 1416 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask); 1417 } 1418 1419 /* 1420 * Because we must read the ICR for this interrupt 1421 * it may clear other causes using autoclear, for 1422 * this reason we simply create a soft interrupt 1423 * for all these vectors. 1424 */ 1425 if (reg_icr && adapter->hw.mac.type < igb_mac_min) { 1426 E1000_WRITE_REG(&adapter->hw, 1427 E1000_ICS, adapter->ims); 1428 } 1429 1430 return (FILTER_HANDLED); 1431 } 1432 1433 static void 1434 em_handle_link(void *context) 1435 { 1436 if_ctx_t ctx = context; 1437 struct adapter *adapter = iflib_get_softc(ctx); 1438 1439 adapter->hw.mac.get_link_status = 1; 1440 iflib_admin_intr_deferred(ctx); 1441 } 1442 1443 1444 /********************************************************************* 1445 * 1446 * Media Ioctl callback 1447 * 1448 * This routine is called whenever the user queries the status of 1449 * the interface using ifconfig. 1450 * 1451 **********************************************************************/ 1452 static void 1453 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1454 { 1455 struct adapter *adapter = iflib_get_softc(ctx); 1456 u_char fiber_type = IFM_1000_SX; 1457 1458 INIT_DEBUGOUT("em_if_media_status: begin"); 1459 1460 iflib_admin_intr_deferred(ctx); 1461 1462 ifmr->ifm_status = IFM_AVALID; 1463 ifmr->ifm_active = IFM_ETHER; 1464 1465 if (!adapter->link_active) { 1466 return; 1467 } 1468 1469 ifmr->ifm_status |= IFM_ACTIVE; 1470 1471 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 1472 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 1473 if (adapter->hw.mac.type == e1000_82545) 1474 fiber_type = IFM_1000_LX; 1475 ifmr->ifm_active |= fiber_type | IFM_FDX; 1476 } else { 1477 switch (adapter->link_speed) { 1478 case 10: 1479 ifmr->ifm_active |= IFM_10_T; 1480 break; 1481 case 100: 1482 ifmr->ifm_active |= IFM_100_TX; 1483 break; 1484 case 1000: 1485 ifmr->ifm_active |= IFM_1000_T; 1486 break; 1487 } 1488 if (adapter->link_duplex == FULL_DUPLEX) 1489 ifmr->ifm_active |= IFM_FDX; 1490 else 1491 ifmr->ifm_active |= IFM_HDX; 1492 } 1493 } 1494 1495 /********************************************************************* 1496 * 1497 * Media Ioctl callback 1498 * 1499 * This routine is called when the user changes speed/duplex using 1500 * media/mediopt option with ifconfig. 1501 * 1502 **********************************************************************/ 1503 static int 1504 em_if_media_change(if_ctx_t ctx) 1505 { 1506 struct adapter *adapter = iflib_get_softc(ctx); 1507 struct ifmedia *ifm = iflib_get_media(ctx); 1508 1509 INIT_DEBUGOUT("em_if_media_change: begin"); 1510 1511 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1512 return (EINVAL); 1513 1514 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1515 case IFM_AUTO: 1516 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1517 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1518 break; 1519 case IFM_1000_LX: 1520 case IFM_1000_SX: 1521 case IFM_1000_T: 1522 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1523 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1524 break; 1525 case IFM_100_TX: 1526 adapter->hw.mac.autoneg = FALSE; 1527 adapter->hw.phy.autoneg_advertised = 0; 1528 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1529 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1530 else 1531 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1532 break; 1533 case IFM_10_T: 1534 adapter->hw.mac.autoneg = FALSE; 1535 adapter->hw.phy.autoneg_advertised = 0; 1536 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1537 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1538 else 1539 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1540 break; 1541 default: 1542 device_printf(adapter->dev, "Unsupported media type\n"); 1543 } 1544 1545 em_if_init(ctx); 1546 1547 return (0); 1548 } 1549 1550 static int 1551 em_if_set_promisc(if_ctx_t ctx, int flags) 1552 { 1553 struct adapter *adapter = iflib_get_softc(ctx); 1554 u32 reg_rctl; 1555 1556 em_disable_promisc(ctx); 1557 1558 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1559 1560 if (flags & IFF_PROMISC) { 1561 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1562 /* Turn this on if you want to see bad packets */ 1563 if (em_debug_sbp) 1564 reg_rctl |= E1000_RCTL_SBP; 1565 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1566 } else if (flags & IFF_ALLMULTI) { 1567 reg_rctl |= E1000_RCTL_MPE; 1568 reg_rctl &= ~E1000_RCTL_UPE; 1569 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1570 } 1571 return (0); 1572 } 1573 1574 static void 1575 em_disable_promisc(if_ctx_t ctx) 1576 { 1577 struct adapter *adapter = iflib_get_softc(ctx); 1578 struct ifnet *ifp = iflib_get_ifp(ctx); 1579 u32 reg_rctl; 1580 int mcnt = 0; 1581 1582 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1583 reg_rctl &= (~E1000_RCTL_UPE); 1584 if (if_getflags(ifp) & IFF_ALLMULTI) 1585 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1586 else 1587 mcnt = if_multiaddr_count(ifp, MAX_NUM_MULTICAST_ADDRESSES); 1588 /* Don't disable if in MAX groups */ 1589 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1590 reg_rctl &= (~E1000_RCTL_MPE); 1591 reg_rctl &= (~E1000_RCTL_SBP); 1592 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1593 } 1594 1595 1596 /********************************************************************* 1597 * Multicast Update 1598 * 1599 * This routine is called whenever multicast address list is updated. 1600 * 1601 **********************************************************************/ 1602 1603 static void 1604 em_if_multi_set(if_ctx_t ctx) 1605 { 1606 struct adapter *adapter = iflib_get_softc(ctx); 1607 struct ifnet *ifp = iflib_get_ifp(ctx); 1608 u32 reg_rctl = 0; 1609 u8 *mta; /* Multicast array memory */ 1610 int mcnt = 0; 1611 1612 IOCTL_DEBUGOUT("em_set_multi: begin"); 1613 1614 mta = adapter->mta; 1615 bzero(mta, sizeof(u8) * ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1616 1617 if (adapter->hw.mac.type == e1000_82542 && 1618 adapter->hw.revision_id == E1000_REVISION_2) { 1619 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1620 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1621 e1000_pci_clear_mwi(&adapter->hw); 1622 reg_rctl |= E1000_RCTL_RST; 1623 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1624 msec_delay(5); 1625 } 1626 1627 if_multiaddr_array(ifp, mta, &mcnt, MAX_NUM_MULTICAST_ADDRESSES); 1628 1629 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 1630 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1631 reg_rctl |= E1000_RCTL_MPE; 1632 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1633 } else 1634 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt); 1635 1636 if (adapter->hw.mac.type == e1000_82542 && 1637 adapter->hw.revision_id == E1000_REVISION_2) { 1638 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1639 reg_rctl &= ~E1000_RCTL_RST; 1640 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1641 msec_delay(5); 1642 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1643 e1000_pci_set_mwi(&adapter->hw); 1644 } 1645 } 1646 1647 1648 /********************************************************************* 1649 * Timer routine 1650 * 1651 * This routine checks for link status and updates statistics. 1652 * 1653 **********************************************************************/ 1654 1655 static void 1656 em_if_timer(if_ctx_t ctx, uint16_t qid) 1657 { 1658 struct adapter *adapter = iflib_get_softc(ctx); 1659 struct em_rx_queue *que; 1660 int i; 1661 int trigger = 0; 1662 1663 if (qid != 0) 1664 return; 1665 1666 iflib_admin_intr_deferred(ctx); 1667 /* Reset LAA into RAR[0] on 82571 */ 1668 if ((adapter->hw.mac.type == e1000_82571) && 1669 e1000_get_laa_state_82571(&adapter->hw)) 1670 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1671 1672 if (adapter->hw.mac.type < em_mac_min) 1673 lem_smartspeed(adapter); 1674 1675 /* Mask to use in the irq trigger */ 1676 if (adapter->intr_type == IFLIB_INTR_MSIX) { 1677 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) 1678 trigger |= que->eims; 1679 } else { 1680 trigger = E1000_ICS_RXDMT0; 1681 } 1682 } 1683 1684 1685 static void 1686 em_if_update_admin_status(if_ctx_t ctx) 1687 { 1688 struct adapter *adapter = iflib_get_softc(ctx); 1689 struct e1000_hw *hw = &adapter->hw; 1690 struct ifnet *ifp = iflib_get_ifp(ctx); 1691 device_t dev = iflib_get_dev(ctx); 1692 u32 link_check, thstat, ctrl; 1693 1694 link_check = thstat = ctrl = 0; 1695 /* Get the cached link value or read phy for real */ 1696 switch (hw->phy.media_type) { 1697 case e1000_media_type_copper: 1698 if (hw->mac.get_link_status) { 1699 if (hw->mac.type == e1000_pch_spt) 1700 msec_delay(50); 1701 /* Do the work to read phy */ 1702 e1000_check_for_link(hw); 1703 link_check = !hw->mac.get_link_status; 1704 if (link_check) /* ESB2 fix */ 1705 e1000_cfg_on_link_up(hw); 1706 } else { 1707 link_check = TRUE; 1708 } 1709 break; 1710 case e1000_media_type_fiber: 1711 e1000_check_for_link(hw); 1712 link_check = (E1000_READ_REG(hw, E1000_STATUS) & 1713 E1000_STATUS_LU); 1714 break; 1715 case e1000_media_type_internal_serdes: 1716 e1000_check_for_link(hw); 1717 link_check = adapter->hw.mac.serdes_has_link; 1718 break; 1719 /* VF device is type_unknown */ 1720 case e1000_media_type_unknown: 1721 e1000_check_for_link(hw); 1722 link_check = !hw->mac.get_link_status; 1723 /* FALLTHROUGH */ 1724 default: 1725 break; 1726 } 1727 1728 /* Check for thermal downshift or shutdown */ 1729 if (hw->mac.type == e1000_i350) { 1730 thstat = E1000_READ_REG(hw, E1000_THSTAT); 1731 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT); 1732 } 1733 1734 /* Now check for a transition */ 1735 if (link_check && (adapter->link_active == 0)) { 1736 e1000_get_speed_and_duplex(hw, &adapter->link_speed, 1737 &adapter->link_duplex); 1738 /* Check if we must disable SPEED_MODE bit on PCI-E */ 1739 if ((adapter->link_speed != SPEED_1000) && 1740 ((hw->mac.type == e1000_82571) || 1741 (hw->mac.type == e1000_82572))) { 1742 int tarc0; 1743 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1744 tarc0 &= ~TARC_SPEED_MODE_BIT; 1745 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1746 } 1747 if (bootverbose) 1748 device_printf(dev, "Link is up %d Mbps %s\n", 1749 adapter->link_speed, 1750 ((adapter->link_duplex == FULL_DUPLEX) ? 1751 "Full Duplex" : "Half Duplex")); 1752 adapter->link_active = 1; 1753 adapter->smartspeed = 0; 1754 if_setbaudrate(ifp, adapter->link_speed * 1000000); 1755 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) && 1756 (thstat & E1000_THSTAT_LINK_THROTTLE)) 1757 device_printf(dev, "Link: thermal downshift\n"); 1758 /* Delay Link Up for Phy update */ 1759 if (((hw->mac.type == e1000_i210) || 1760 (hw->mac.type == e1000_i211)) && 1761 (hw->phy.id == I210_I_PHY_ID)) 1762 msec_delay(I210_LINK_DELAY); 1763 /* Reset if the media type changed. */ 1764 if ((hw->dev_spec._82575.media_changed) && 1765 (adapter->hw.mac.type >= igb_mac_min)) { 1766 hw->dev_spec._82575.media_changed = false; 1767 adapter->flags |= IGB_MEDIA_RESET; 1768 em_reset(ctx); 1769 } 1770 iflib_link_state_change(ctx, LINK_STATE_UP, ifp->if_baudrate); 1771 printf("Link state changed to up\n"); 1772 } else if (!link_check && (adapter->link_active == 1)) { 1773 if_setbaudrate(ifp, 0); 1774 adapter->link_speed = 0; 1775 adapter->link_duplex = 0; 1776 if (bootverbose) 1777 device_printf(dev, "Link is Down\n"); 1778 adapter->link_active = 0; 1779 iflib_link_state_change(ctx, LINK_STATE_DOWN, ifp->if_baudrate); 1780 printf("link state changed to down\n"); 1781 } 1782 em_update_stats_counters(adapter); 1783 1784 E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK | E1000_IMS_LSC); 1785 } 1786 1787 /********************************************************************* 1788 * 1789 * This routine disables all traffic on the adapter by issuing a 1790 * global reset on the MAC and deallocates TX/RX buffers. 1791 * 1792 * This routine should always be called with BOTH the CORE 1793 * and TX locks. 1794 **********************************************************************/ 1795 1796 static void 1797 em_if_stop(if_ctx_t ctx) 1798 { 1799 struct adapter *adapter = iflib_get_softc(ctx); 1800 1801 INIT_DEBUGOUT("em_stop: begin"); 1802 1803 e1000_reset_hw(&adapter->hw); 1804 if (adapter->hw.mac.type >= e1000_82544) 1805 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, 0); 1806 1807 e1000_led_off(&adapter->hw); 1808 e1000_cleanup_led(&adapter->hw); 1809 } 1810 1811 1812 /********************************************************************* 1813 * 1814 * Determine hardware revision. 1815 * 1816 **********************************************************************/ 1817 static void 1818 em_identify_hardware(if_ctx_t ctx) 1819 { 1820 device_t dev = iflib_get_dev(ctx); 1821 struct adapter *adapter = iflib_get_softc(ctx); 1822 1823 /* Make sure our PCI config space has the necessary stuff set */ 1824 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1825 1826 /* Save off the information about this board */ 1827 adapter->hw.vendor_id = pci_get_vendor(dev); 1828 adapter->hw.device_id = pci_get_device(dev); 1829 adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1830 adapter->hw.subsystem_vendor_id = 1831 pci_read_config(dev, PCIR_SUBVEND_0, 2); 1832 adapter->hw.subsystem_device_id = 1833 pci_read_config(dev, PCIR_SUBDEV_0, 2); 1834 1835 /* Do Shared Code Init and Setup */ 1836 if (e1000_set_mac_type(&adapter->hw)) { 1837 device_printf(dev, "Setup init failure\n"); 1838 return; 1839 } 1840 } 1841 1842 static int 1843 em_allocate_pci_resources(if_ctx_t ctx) 1844 { 1845 struct adapter *adapter = iflib_get_softc(ctx); 1846 device_t dev = iflib_get_dev(ctx); 1847 int rid, val; 1848 1849 rid = PCIR_BAR(0); 1850 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1851 &rid, RF_ACTIVE); 1852 if (adapter->memory == NULL) { 1853 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1854 return (ENXIO); 1855 } 1856 adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory); 1857 adapter->osdep.mem_bus_space_handle = 1858 rman_get_bushandle(adapter->memory); 1859 adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle; 1860 1861 /* Only older adapters use IO mapping */ 1862 if (adapter->hw.mac.type < em_mac_min && 1863 adapter->hw.mac.type > e1000_82543) { 1864 /* Figure our where our IO BAR is ? */ 1865 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 1866 val = pci_read_config(dev, rid, 4); 1867 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 1868 adapter->io_rid = rid; 1869 break; 1870 } 1871 rid += 4; 1872 /* check for 64bit BAR */ 1873 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 1874 rid += 4; 1875 } 1876 if (rid >= PCIR_CIS) { 1877 device_printf(dev, "Unable to locate IO BAR\n"); 1878 return (ENXIO); 1879 } 1880 adapter->ioport = bus_alloc_resource_any(dev, 1881 SYS_RES_IOPORT, &adapter->io_rid, RF_ACTIVE); 1882 if (adapter->ioport == NULL) { 1883 device_printf(dev, "Unable to allocate bus resource: " 1884 "ioport\n"); 1885 return (ENXIO); 1886 } 1887 adapter->hw.io_base = 0; 1888 adapter->osdep.io_bus_space_tag = 1889 rman_get_bustag(adapter->ioport); 1890 adapter->osdep.io_bus_space_handle = 1891 rman_get_bushandle(adapter->ioport); 1892 } 1893 1894 adapter->hw.back = &adapter->osdep; 1895 1896 return (0); 1897 } 1898 1899 /********************************************************************* 1900 * 1901 * Setup the MSIX Interrupt handlers 1902 * 1903 **********************************************************************/ 1904 static int 1905 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 1906 { 1907 struct adapter *adapter = iflib_get_softc(ctx); 1908 struct em_rx_queue *rx_que = adapter->rx_queues; 1909 struct em_tx_queue *tx_que = adapter->tx_queues; 1910 int error, rid, i, vector = 0, rx_vectors; 1911 char buf[16]; 1912 1913 /* First set up ring resources */ 1914 for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) { 1915 rid = vector + 1; 1916 snprintf(buf, sizeof(buf), "rxq%d", i); 1917 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); 1918 if (error) { 1919 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 1920 adapter->rx_num_queues = i + 1; 1921 goto fail; 1922 } 1923 1924 rx_que->msix = vector; 1925 1926 /* 1927 * Set the bit to enable interrupt 1928 * in E1000_IMS -- bits 20 and 21 1929 * are for RX0 and RX1, note this has 1930 * NOTHING to do with the MSIX vector 1931 */ 1932 if (adapter->hw.mac.type == e1000_82574) { 1933 rx_que->eims = 1 << (20 + i); 1934 adapter->ims |= rx_que->eims; 1935 adapter->ivars |= (8 | rx_que->msix) << (i * 4); 1936 } else if (adapter->hw.mac.type == e1000_82575) 1937 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 1938 else 1939 rx_que->eims = 1 << vector; 1940 } 1941 rx_vectors = vector; 1942 1943 vector = 0; 1944 for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) { 1945 rid = vector + 1; 1946 snprintf(buf, sizeof(buf), "txq%d", i); 1947 tx_que = &adapter->tx_queues[i]; 1948 iflib_softirq_alloc_generic(ctx, rid, IFLIB_INTR_TX, tx_que, tx_que->me, buf); 1949 1950 tx_que->msix = (vector % adapter->tx_num_queues); 1951 1952 /* 1953 * Set the bit to enable interrupt 1954 * in E1000_IMS -- bits 22 and 23 1955 * are for TX0 and TX1, note this has 1956 * NOTHING to do with the MSIX vector 1957 */ 1958 if (adapter->hw.mac.type == e1000_82574) { 1959 tx_que->eims = 1 << (22 + i); 1960 adapter->ims |= tx_que->eims; 1961 adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 1962 } else if (adapter->hw.mac.type == e1000_82575) { 1963 tx_que->eims = E1000_EICR_TX_QUEUE0 << (i % adapter->tx_num_queues); 1964 } else { 1965 tx_que->eims = 1 << (i % adapter->tx_num_queues); 1966 } 1967 } 1968 1969 /* Link interrupt */ 1970 rid = rx_vectors + 1; 1971 error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq"); 1972 1973 if (error) { 1974 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 1975 goto fail; 1976 } 1977 adapter->linkvec = rx_vectors; 1978 if (adapter->hw.mac.type < igb_mac_min) { 1979 adapter->ivars |= (8 | rx_vectors) << 16; 1980 adapter->ivars |= 0x80000000; 1981 } 1982 return (0); 1983 fail: 1984 iflib_irq_free(ctx, &adapter->irq); 1985 rx_que = adapter->rx_queues; 1986 for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++) 1987 iflib_irq_free(ctx, &rx_que->que_irq); 1988 return (error); 1989 } 1990 1991 static void 1992 igb_configure_queues(struct adapter *adapter) 1993 { 1994 struct e1000_hw *hw = &adapter->hw; 1995 struct em_rx_queue *rx_que; 1996 struct em_tx_queue *tx_que; 1997 u32 tmp, ivar = 0, newitr = 0; 1998 1999 /* First turn on RSS capability */ 2000 if (adapter->hw.mac.type != e1000_82575) 2001 E1000_WRITE_REG(hw, E1000_GPIE, 2002 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 2003 E1000_GPIE_PBA | E1000_GPIE_NSICR); 2004 2005 /* Turn on MSIX */ 2006 switch (adapter->hw.mac.type) { 2007 case e1000_82580: 2008 case e1000_i350: 2009 case e1000_i354: 2010 case e1000_i210: 2011 case e1000_i211: 2012 case e1000_vfadapt: 2013 case e1000_vfadapt_i350: 2014 /* RX entries */ 2015 for (int i = 0; i < adapter->rx_num_queues; i++) { 2016 u32 index = i >> 1; 2017 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2018 rx_que = &adapter->rx_queues[i]; 2019 if (i & 1) { 2020 ivar &= 0xFF00FFFF; 2021 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2022 } else { 2023 ivar &= 0xFFFFFF00; 2024 ivar |= rx_que->msix | E1000_IVAR_VALID; 2025 } 2026 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2027 } 2028 /* TX entries */ 2029 for (int i = 0; i < adapter->tx_num_queues; i++) { 2030 u32 index = i >> 1; 2031 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2032 tx_que = &adapter->tx_queues[i]; 2033 if (i & 1) { 2034 ivar &= 0x00FFFFFF; 2035 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2036 } else { 2037 ivar &= 0xFFFF00FF; 2038 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2039 } 2040 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2041 adapter->que_mask |= tx_que->eims; 2042 } 2043 2044 /* And for the link interrupt */ 2045 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 2046 adapter->link_mask = 1 << adapter->linkvec; 2047 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2048 break; 2049 case e1000_82576: 2050 /* RX entries */ 2051 for (int i = 0; i < adapter->rx_num_queues; i++) { 2052 u32 index = i & 0x7; /* Each IVAR has two entries */ 2053 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2054 rx_que = &adapter->rx_queues[i]; 2055 if (i < 8) { 2056 ivar &= 0xFFFFFF00; 2057 ivar |= rx_que->msix | E1000_IVAR_VALID; 2058 } else { 2059 ivar &= 0xFF00FFFF; 2060 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2061 } 2062 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2063 adapter->que_mask |= rx_que->eims; 2064 } 2065 /* TX entries */ 2066 for (int i = 0; i < adapter->tx_num_queues; i++) { 2067 u32 index = i & 0x7; /* Each IVAR has two entries */ 2068 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2069 tx_que = &adapter->tx_queues[i]; 2070 if (i < 8) { 2071 ivar &= 0xFFFF00FF; 2072 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2073 } else { 2074 ivar &= 0x00FFFFFF; 2075 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2076 } 2077 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2078 adapter->que_mask |= tx_que->eims; 2079 } 2080 2081 /* And for the link interrupt */ 2082 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 2083 adapter->link_mask = 1 << adapter->linkvec; 2084 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2085 break; 2086 2087 case e1000_82575: 2088 /* enable MSI-X support*/ 2089 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2090 tmp |= E1000_CTRL_EXT_PBA_CLR; 2091 /* Auto-Mask interrupts upon ICR read. */ 2092 tmp |= E1000_CTRL_EXT_EIAME; 2093 tmp |= E1000_CTRL_EXT_IRCA; 2094 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2095 2096 /* Queues */ 2097 for (int i = 0; i < adapter->rx_num_queues; i++) { 2098 rx_que = &adapter->rx_queues[i]; 2099 tmp = E1000_EICR_RX_QUEUE0 << i; 2100 tmp |= E1000_EICR_TX_QUEUE0 << i; 2101 rx_que->eims = tmp; 2102 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 2103 i, rx_que->eims); 2104 adapter->que_mask |= rx_que->eims; 2105 } 2106 2107 /* Link */ 2108 E1000_WRITE_REG(hw, E1000_MSIXBM(adapter->linkvec), 2109 E1000_EIMS_OTHER); 2110 adapter->link_mask |= E1000_EIMS_OTHER; 2111 default: 2112 break; 2113 } 2114 2115 /* Set the starting interrupt rate */ 2116 if (em_max_interrupt_rate > 0) 2117 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC; 2118 2119 if (hw->mac.type == e1000_82575) 2120 newitr |= newitr << 16; 2121 else 2122 newitr |= E1000_EITR_CNT_IGNR; 2123 2124 for (int i = 0; i < adapter->rx_num_queues; i++) { 2125 rx_que = &adapter->rx_queues[i]; 2126 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2127 } 2128 2129 return; 2130 } 2131 2132 static void 2133 em_free_pci_resources(if_ctx_t ctx) 2134 { 2135 struct adapter *adapter = iflib_get_softc(ctx); 2136 struct em_rx_queue *que = adapter->rx_queues; 2137 device_t dev = iflib_get_dev(ctx); 2138 2139 /* Release all msix queue resources */ 2140 if (adapter->intr_type == IFLIB_INTR_MSIX) 2141 iflib_irq_free(ctx, &adapter->irq); 2142 2143 for (int i = 0; i < adapter->rx_num_queues; i++, que++) { 2144 iflib_irq_free(ctx, &que->que_irq); 2145 } 2146 2147 /* First release all the interrupt resources */ 2148 if (adapter->memory != NULL) { 2149 bus_release_resource(dev, SYS_RES_MEMORY, 2150 PCIR_BAR(0), adapter->memory); 2151 adapter->memory = NULL; 2152 } 2153 2154 if (adapter->flash != NULL) { 2155 bus_release_resource(dev, SYS_RES_MEMORY, 2156 EM_FLASH, adapter->flash); 2157 adapter->flash = NULL; 2158 } 2159 if (adapter->ioport != NULL) 2160 bus_release_resource(dev, SYS_RES_IOPORT, 2161 adapter->io_rid, adapter->ioport); 2162 } 2163 2164 /* Setup MSI or MSI/X */ 2165 static int 2166 em_setup_msix(if_ctx_t ctx) 2167 { 2168 struct adapter *adapter = iflib_get_softc(ctx); 2169 2170 if (adapter->hw.mac.type == e1000_82574) { 2171 em_enable_vectors_82574(ctx); 2172 } 2173 return (0); 2174 } 2175 2176 /********************************************************************* 2177 * 2178 * Initialize the hardware to a configuration 2179 * as specified by the adapter structure. 2180 * 2181 **********************************************************************/ 2182 2183 static void 2184 lem_smartspeed(struct adapter *adapter) 2185 { 2186 u16 phy_tmp; 2187 2188 if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) || 2189 adapter->hw.mac.autoneg == 0 || 2190 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2191 return; 2192 2193 if (adapter->smartspeed == 0) { 2194 /* If Master/Slave config fault is asserted twice, 2195 * we assume back-to-back */ 2196 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2197 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2198 return; 2199 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2200 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2201 e1000_read_phy_reg(&adapter->hw, 2202 PHY_1000T_CTRL, &phy_tmp); 2203 if(phy_tmp & CR_1000T_MS_ENABLE) { 2204 phy_tmp &= ~CR_1000T_MS_ENABLE; 2205 e1000_write_phy_reg(&adapter->hw, 2206 PHY_1000T_CTRL, phy_tmp); 2207 adapter->smartspeed++; 2208 if(adapter->hw.mac.autoneg && 2209 !e1000_copper_link_autoneg(&adapter->hw) && 2210 !e1000_read_phy_reg(&adapter->hw, 2211 PHY_CONTROL, &phy_tmp)) { 2212 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2213 MII_CR_RESTART_AUTO_NEG); 2214 e1000_write_phy_reg(&adapter->hw, 2215 PHY_CONTROL, phy_tmp); 2216 } 2217 } 2218 } 2219 return; 2220 } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2221 /* If still no link, perhaps using 2/3 pair cable */ 2222 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 2223 phy_tmp |= CR_1000T_MS_ENABLE; 2224 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp); 2225 if(adapter->hw.mac.autoneg && 2226 !e1000_copper_link_autoneg(&adapter->hw) && 2227 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) { 2228 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2229 MII_CR_RESTART_AUTO_NEG); 2230 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp); 2231 } 2232 } 2233 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2234 if(adapter->smartspeed++ == EM_SMARTSPEED_MAX) 2235 adapter->smartspeed = 0; 2236 } 2237 2238 /********************************************************************* 2239 * 2240 * Initialize the DMA Coalescing feature 2241 * 2242 **********************************************************************/ 2243 static void 2244 igb_init_dmac(struct adapter *adapter, u32 pba) 2245 { 2246 device_t dev = adapter->dev; 2247 struct e1000_hw *hw = &adapter->hw; 2248 u32 dmac, reg = ~E1000_DMACR_DMAC_EN; 2249 u16 hwm; 2250 u16 max_frame_size; 2251 2252 if (hw->mac.type == e1000_i211) 2253 return; 2254 2255 max_frame_size = adapter->shared->isc_max_frame_size; 2256 if (hw->mac.type > e1000_82580) { 2257 2258 if (adapter->dmac == 0) { /* Disabling it */ 2259 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2260 return; 2261 } else 2262 device_printf(dev, "DMA Coalescing enabled\n"); 2263 2264 /* Set starting threshold */ 2265 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0); 2266 2267 hwm = 64 * pba - max_frame_size / 16; 2268 if (hwm < 64 * (pba - 6)) 2269 hwm = 64 * (pba - 6); 2270 reg = E1000_READ_REG(hw, E1000_FCRTC); 2271 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 2272 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 2273 & E1000_FCRTC_RTH_COAL_MASK); 2274 E1000_WRITE_REG(hw, E1000_FCRTC, reg); 2275 2276 2277 dmac = pba - max_frame_size / 512; 2278 if (dmac < pba - 10) 2279 dmac = pba - 10; 2280 reg = E1000_READ_REG(hw, E1000_DMACR); 2281 reg &= ~E1000_DMACR_DMACTHR_MASK; 2282 reg = ((dmac << E1000_DMACR_DMACTHR_SHIFT) 2283 & E1000_DMACR_DMACTHR_MASK); 2284 2285 /* transition to L0x or L1 if available..*/ 2286 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 2287 2288 /* Check if status is 2.5Gb backplane connection 2289 * before configuration of watchdog timer, which is 2290 * in msec values in 12.8usec intervals 2291 * watchdog timer= msec values in 32usec intervals 2292 * for non 2.5Gb connection 2293 */ 2294 if (hw->mac.type == e1000_i354) { 2295 int status = E1000_READ_REG(hw, E1000_STATUS); 2296 if ((status & E1000_STATUS_2P5_SKU) && 2297 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2298 reg |= ((adapter->dmac * 5) >> 6); 2299 else 2300 reg |= (adapter->dmac >> 5); 2301 } else { 2302 reg |= (adapter->dmac >> 5); 2303 } 2304 2305 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2306 2307 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0); 2308 2309 /* Set the interval before transition */ 2310 reg = E1000_READ_REG(hw, E1000_DMCTLX); 2311 if (hw->mac.type == e1000_i350) 2312 reg |= IGB_DMCTLX_DCFLUSH_DIS; 2313 /* 2314 ** in 2.5Gb connection, TTLX unit is 0.4 usec 2315 ** which is 0x4*2 = 0xA. But delay is still 4 usec 2316 */ 2317 if (hw->mac.type == e1000_i354) { 2318 int status = E1000_READ_REG(hw, E1000_STATUS); 2319 if ((status & E1000_STATUS_2P5_SKU) && 2320 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2321 reg |= 0xA; 2322 else 2323 reg |= 0x4; 2324 } else { 2325 reg |= 0x4; 2326 } 2327 2328 E1000_WRITE_REG(hw, E1000_DMCTLX, reg); 2329 2330 /* free space in tx packet buffer to wake from DMA coal */ 2331 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE - 2332 (2 * max_frame_size)) >> 6); 2333 2334 /* make low power state decision controlled by DMA coal */ 2335 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2336 reg &= ~E1000_PCIEMISC_LX_DECISION; 2337 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg); 2338 2339 } else if (hw->mac.type == e1000_82580) { 2340 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2341 E1000_WRITE_REG(hw, E1000_PCIEMISC, 2342 reg & ~E1000_PCIEMISC_LX_DECISION); 2343 E1000_WRITE_REG(hw, E1000_DMACR, 0); 2344 } 2345 } 2346 2347 static void 2348 em_reset(if_ctx_t ctx) 2349 { 2350 device_t dev = iflib_get_dev(ctx); 2351 struct adapter *adapter = iflib_get_softc(ctx); 2352 struct ifnet *ifp = iflib_get_ifp(ctx); 2353 struct e1000_hw *hw = &adapter->hw; 2354 u16 rx_buffer_size; 2355 u32 pba; 2356 2357 INIT_DEBUGOUT("em_reset: begin"); 2358 /* Let the firmware know the OS is in control */ 2359 em_get_hw_control(adapter); 2360 2361 /* Set up smart power down as default off on newer adapters. */ 2362 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 2363 hw->mac.type == e1000_82572)) { 2364 u16 phy_tmp = 0; 2365 2366 /* Speed up time to link by disabling smart power down. */ 2367 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2368 phy_tmp &= ~IGP02E1000_PM_SPD; 2369 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2370 } 2371 2372 /* 2373 * Packet Buffer Allocation (PBA) 2374 * Writing PBA sets the receive portion of the buffer 2375 * the remainder is used for the transmit buffer. 2376 */ 2377 switch (hw->mac.type) { 2378 /* Total Packet Buffer on these is 48K */ 2379 case e1000_82571: 2380 case e1000_82572: 2381 case e1000_80003es2lan: 2382 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2383 break; 2384 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 2385 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2386 break; 2387 case e1000_82574: 2388 case e1000_82583: 2389 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2390 break; 2391 case e1000_ich8lan: 2392 pba = E1000_PBA_8K; 2393 break; 2394 case e1000_ich9lan: 2395 case e1000_ich10lan: 2396 /* Boost Receive side for jumbo frames */ 2397 if (adapter->hw.mac.max_frame_size > 4096) 2398 pba = E1000_PBA_14K; 2399 else 2400 pba = E1000_PBA_10K; 2401 break; 2402 case e1000_pchlan: 2403 case e1000_pch2lan: 2404 case e1000_pch_lpt: 2405 case e1000_pch_spt: 2406 pba = E1000_PBA_26K; 2407 break; 2408 case e1000_82575: 2409 pba = E1000_PBA_32K; 2410 break; 2411 case e1000_82576: 2412 case e1000_vfadapt: 2413 pba = E1000_READ_REG(hw, E1000_RXPBS); 2414 pba &= E1000_RXPBS_SIZE_MASK_82576; 2415 break; 2416 case e1000_82580: 2417 case e1000_i350: 2418 case e1000_i354: 2419 case e1000_vfadapt_i350: 2420 pba = E1000_READ_REG(hw, E1000_RXPBS); 2421 pba = e1000_rxpbs_adjust_82580(pba); 2422 break; 2423 case e1000_i210: 2424 case e1000_i211: 2425 pba = E1000_PBA_34K; 2426 break; 2427 default: 2428 if (adapter->hw.mac.max_frame_size > 8192) 2429 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2430 else 2431 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2432 } 2433 2434 /* Special needs in case of Jumbo frames */ 2435 if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) { 2436 u32 tx_space, min_tx, min_rx; 2437 pba = E1000_READ_REG(hw, E1000_PBA); 2438 tx_space = pba >> 16; 2439 pba &= 0xffff; 2440 min_tx = (adapter->hw.mac.max_frame_size + 2441 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 2442 min_tx = roundup2(min_tx, 1024); 2443 min_tx >>= 10; 2444 min_rx = adapter->hw.mac.max_frame_size; 2445 min_rx = roundup2(min_rx, 1024); 2446 min_rx >>= 10; 2447 if (tx_space < min_tx && 2448 ((min_tx - tx_space) < pba)) { 2449 pba = pba - (min_tx - tx_space); 2450 /* 2451 * if short on rx space, rx wins 2452 * and must trump tx adjustment 2453 */ 2454 if (pba < min_rx) 2455 pba = min_rx; 2456 } 2457 E1000_WRITE_REG(hw, E1000_PBA, pba); 2458 } 2459 2460 if (hw->mac.type < igb_mac_min) 2461 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba); 2462 2463 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 2464 2465 /* 2466 * These parameters control the automatic generation (Tx) and 2467 * response (Rx) to Ethernet PAUSE frames. 2468 * - High water mark should allow for at least two frames to be 2469 * received after sending an XOFF. 2470 * - Low water mark works best when it is very near the high water mark. 2471 * This allows the receiver to restart by sending XON when it has 2472 * drained a bit. Here we use an arbitrary value of 1500 which will 2473 * restart after one full frame is pulled from the buffer. There 2474 * could be several smaller frames in the buffer and if so they will 2475 * not trigger the XON until their total number reduces the buffer 2476 * by 1500. 2477 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2478 */ 2479 rx_buffer_size = (pba & 0xffff) << 10; 2480 hw->fc.high_water = rx_buffer_size - 2481 roundup2(adapter->hw.mac.max_frame_size, 1024); 2482 hw->fc.low_water = hw->fc.high_water - 1500; 2483 2484 if (adapter->fc) /* locally set flow control value? */ 2485 hw->fc.requested_mode = adapter->fc; 2486 else 2487 hw->fc.requested_mode = e1000_fc_full; 2488 2489 if (hw->mac.type == e1000_80003es2lan) 2490 hw->fc.pause_time = 0xFFFF; 2491 else 2492 hw->fc.pause_time = EM_FC_PAUSE_TIME; 2493 2494 hw->fc.send_xon = TRUE; 2495 2496 /* Device specific overrides/settings */ 2497 switch (hw->mac.type) { 2498 case e1000_pchlan: 2499 /* Workaround: no TX flow ctrl for PCH */ 2500 hw->fc.requested_mode = e1000_fc_rx_pause; 2501 hw->fc.pause_time = 0xFFFF; /* override */ 2502 if (if_getmtu(ifp) > ETHERMTU) { 2503 hw->fc.high_water = 0x3500; 2504 hw->fc.low_water = 0x1500; 2505 } else { 2506 hw->fc.high_water = 0x5000; 2507 hw->fc.low_water = 0x3000; 2508 } 2509 hw->fc.refresh_time = 0x1000; 2510 break; 2511 case e1000_pch2lan: 2512 case e1000_pch_lpt: 2513 case e1000_pch_spt: 2514 hw->fc.high_water = 0x5C20; 2515 hw->fc.low_water = 0x5048; 2516 hw->fc.pause_time = 0x0650; 2517 hw->fc.refresh_time = 0x0400; 2518 /* Jumbos need adjusted PBA */ 2519 if (if_getmtu(ifp) > ETHERMTU) 2520 E1000_WRITE_REG(hw, E1000_PBA, 12); 2521 else 2522 E1000_WRITE_REG(hw, E1000_PBA, 26); 2523 break; 2524 case e1000_82575: 2525 case e1000_82576: 2526 /* 8-byte granularity */ 2527 hw->fc.low_water = hw->fc.high_water - 8; 2528 break; 2529 case e1000_82580: 2530 case e1000_i350: 2531 case e1000_i354: 2532 case e1000_i210: 2533 case e1000_i211: 2534 case e1000_vfadapt: 2535 case e1000_vfadapt_i350: 2536 /* 16-byte granularity */ 2537 hw->fc.low_water = hw->fc.high_water - 16; 2538 break; 2539 case e1000_ich9lan: 2540 case e1000_ich10lan: 2541 if (if_getmtu(ifp) > ETHERMTU) { 2542 hw->fc.high_water = 0x2800; 2543 hw->fc.low_water = hw->fc.high_water - 8; 2544 break; 2545 } 2546 /* FALLTHROUGH */ 2547 default: 2548 if (hw->mac.type == e1000_80003es2lan) 2549 hw->fc.pause_time = 0xFFFF; 2550 break; 2551 } 2552 2553 /* Issue a global reset */ 2554 e1000_reset_hw(hw); 2555 if (adapter->hw.mac.type >= igb_mac_min) { 2556 E1000_WRITE_REG(hw, E1000_WUC, 0); 2557 } else { 2558 E1000_WRITE_REG(hw, E1000_WUFC, 0); 2559 em_disable_aspm(adapter); 2560 } 2561 if (adapter->flags & IGB_MEDIA_RESET) { 2562 e1000_setup_init_funcs(hw, TRUE); 2563 e1000_get_bus_info(hw); 2564 adapter->flags &= ~IGB_MEDIA_RESET; 2565 } 2566 /* and a re-init */ 2567 if (e1000_init_hw(hw) < 0) { 2568 device_printf(dev, "Hardware Initialization Failed\n"); 2569 return; 2570 } 2571 if (adapter->hw.mac.type >= igb_mac_min) 2572 igb_init_dmac(adapter, pba); 2573 2574 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 2575 e1000_get_phy_info(hw); 2576 e1000_check_for_link(hw); 2577 } 2578 2579 #define RSSKEYLEN 10 2580 static void 2581 em_initialize_rss_mapping(struct adapter *adapter) 2582 { 2583 uint8_t rss_key[4 * RSSKEYLEN]; 2584 uint32_t reta = 0; 2585 struct e1000_hw *hw = &adapter->hw; 2586 int i; 2587 2588 /* 2589 * Configure RSS key 2590 */ 2591 arc4rand(rss_key, sizeof(rss_key), 0); 2592 for (i = 0; i < RSSKEYLEN; ++i) { 2593 uint32_t rssrk = 0; 2594 2595 rssrk = EM_RSSRK_VAL(rss_key, i); 2596 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 2597 } 2598 2599 /* 2600 * Configure RSS redirect table in following fashion: 2601 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2602 */ 2603 for (i = 0; i < sizeof(reta); ++i) { 2604 uint32_t q; 2605 2606 q = (i % adapter->rx_num_queues) << 7; 2607 reta |= q << (8 * i); 2608 } 2609 2610 for (i = 0; i < 32; ++i) 2611 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 2612 2613 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 2614 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2615 E1000_MRQC_RSS_FIELD_IPV4 | 2616 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 2617 E1000_MRQC_RSS_FIELD_IPV6_EX | 2618 E1000_MRQC_RSS_FIELD_IPV6); 2619 2620 } 2621 2622 static void 2623 igb_initialize_rss_mapping(struct adapter *adapter) 2624 { 2625 struct e1000_hw *hw = &adapter->hw; 2626 int i; 2627 int queue_id; 2628 u32 reta; 2629 u32 rss_key[10], mrqc, shift = 0; 2630 2631 /* XXX? */ 2632 if (adapter->hw.mac.type == e1000_82575) 2633 shift = 6; 2634 2635 /* 2636 * The redirection table controls which destination 2637 * queue each bucket redirects traffic to. 2638 * Each DWORD represents four queues, with the LSB 2639 * being the first queue in the DWORD. 2640 * 2641 * This just allocates buckets to queues using round-robin 2642 * allocation. 2643 * 2644 * NOTE: It Just Happens to line up with the default 2645 * RSS allocation method. 2646 */ 2647 2648 /* Warning FM follows */ 2649 reta = 0; 2650 for (i = 0; i < 128; i++) { 2651 #ifdef RSS 2652 queue_id = rss_get_indirection_to_bucket(i); 2653 /* 2654 * If we have more queues than buckets, we'll 2655 * end up mapping buckets to a subset of the 2656 * queues. 2657 * 2658 * If we have more buckets than queues, we'll 2659 * end up instead assigning multiple buckets 2660 * to queues. 2661 * 2662 * Both are suboptimal, but we need to handle 2663 * the case so we don't go out of bounds 2664 * indexing arrays and such. 2665 */ 2666 queue_id = queue_id % adapter->rx_num_queues; 2667 #else 2668 queue_id = (i % adapter->rx_num_queues); 2669 #endif 2670 /* Adjust if required */ 2671 queue_id = queue_id << shift; 2672 2673 /* 2674 * The low 8 bits are for hash value (n+0); 2675 * The next 8 bits are for hash value (n+1), etc. 2676 */ 2677 reta = reta >> 8; 2678 reta = reta | ( ((uint32_t) queue_id) << 24); 2679 if ((i & 3) == 3) { 2680 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 2681 reta = 0; 2682 } 2683 } 2684 2685 /* Now fill in hash table */ 2686 2687 /* 2688 * MRQC: Multiple Receive Queues Command 2689 * Set queuing to RSS control, number depends on the device. 2690 */ 2691 mrqc = E1000_MRQC_ENABLE_RSS_8Q; 2692 2693 #ifdef RSS 2694 /* XXX ew typecasting */ 2695 rss_getkey((uint8_t *) &rss_key); 2696 #else 2697 arc4rand(&rss_key, sizeof(rss_key), 0); 2698 #endif 2699 for (i = 0; i < 10; i++) 2700 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]); 2701 2702 /* 2703 * Configure the RSS fields to hash upon. 2704 */ 2705 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2706 E1000_MRQC_RSS_FIELD_IPV4_TCP); 2707 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 2708 E1000_MRQC_RSS_FIELD_IPV6_TCP); 2709 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 2710 E1000_MRQC_RSS_FIELD_IPV6_UDP); 2711 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2712 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2713 2714 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2715 } 2716 2717 /********************************************************************* 2718 * 2719 * Setup networking device structure and register an interface. 2720 * 2721 **********************************************************************/ 2722 static int 2723 em_setup_interface(if_ctx_t ctx) 2724 { 2725 struct ifnet *ifp = iflib_get_ifp(ctx); 2726 struct adapter *adapter = iflib_get_softc(ctx); 2727 if_softc_ctx_t scctx = adapter->shared; 2728 uint64_t cap = 0; 2729 2730 INIT_DEBUGOUT("em_setup_interface: begin"); 2731 2732 /* TSO parameters */ 2733 if_sethwtsomax(ifp, IP_MAXPACKET); 2734 /* Take m_pullup(9)'s in em_xmit() w/ TSO into acount. */ 2735 if_sethwtsomaxsegcount(ifp, EM_MAX_SCATTER - 5); 2736 if_sethwtsomaxsegsize(ifp, EM_TSO_SEG_SIZE); 2737 2738 /* Single Queue */ 2739 if (adapter->tx_num_queues == 1) { 2740 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 2741 if_setsendqready(ifp); 2742 } 2743 2744 cap = IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | IFCAP_TSO4; 2745 cap |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU; 2746 2747 /* 2748 * Tell the upper layer(s) we 2749 * support full VLAN capability 2750 */ 2751 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 2752 if_setcapabilitiesbit(ifp, cap, 0); 2753 2754 /* 2755 * Don't turn this on by default, if vlans are 2756 * created on another pseudo device (eg. lagg) 2757 * then vlan events are not passed thru, breaking 2758 * operation, but with HW FILTER off it works. If 2759 * using vlans directly on the em driver you can 2760 * enable this and get full hardware tag filtering. 2761 */ 2762 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWFILTER,0); 2763 2764 /* Enable only WOL MAGIC by default */ 2765 if (adapter->wol) { 2766 if_setcapenablebit(ifp, IFCAP_WOL_MAGIC, 2767 IFCAP_WOL_MCAST| IFCAP_WOL_UCAST); 2768 } else { 2769 if_setcapenablebit(ifp, 0, IFCAP_WOL_MAGIC | 2770 IFCAP_WOL_MCAST| IFCAP_WOL_UCAST); 2771 } 2772 2773 /* 2774 * Specify the media types supported by this adapter and register 2775 * callbacks to update media and link information 2776 */ 2777 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 2778 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 2779 u_char fiber_type = IFM_1000_SX; /* default type */ 2780 2781 if (adapter->hw.mac.type == e1000_82545) 2782 fiber_type = IFM_1000_LX; 2783 ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 2784 ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL); 2785 } else { 2786 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 2787 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 2788 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL); 2789 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 2790 if (adapter->hw.phy.type != e1000_phy_ife) { 2791 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2792 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2793 } 2794 } 2795 ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2796 ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO); 2797 return (0); 2798 } 2799 2800 static int 2801 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 2802 { 2803 struct adapter *adapter = iflib_get_softc(ctx); 2804 if_softc_ctx_t scctx = adapter->shared; 2805 int error = E1000_SUCCESS; 2806 struct em_tx_queue *que; 2807 int i, j; 2808 2809 MPASS(adapter->tx_num_queues > 0); 2810 MPASS(adapter->tx_num_queues == ntxqsets); 2811 2812 /* First allocate the top level queue structs */ 2813 if (!(adapter->tx_queues = 2814 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 2815 adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2816 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2817 return(ENOMEM); 2818 } 2819 2820 for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) { 2821 /* Set up some basics */ 2822 2823 struct tx_ring *txr = &que->txr; 2824 txr->adapter = que->adapter = adapter; 2825 que->me = txr->me = i; 2826 2827 /* Allocate report status array */ 2828 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 2829 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n"); 2830 error = ENOMEM; 2831 goto fail; 2832 } 2833 for (j = 0; j < scctx->isc_ntxd[0]; j++) 2834 txr->tx_rsq[j] = QIDX_INVALID; 2835 /* get the virtual and physical address of the hardware queues */ 2836 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 2837 txr->tx_paddr = paddrs[i*ntxqs]; 2838 } 2839 2840 device_printf(iflib_get_dev(ctx), "allocated for %d tx_queues\n", adapter->tx_num_queues); 2841 return (0); 2842 fail: 2843 em_if_queues_free(ctx); 2844 return (error); 2845 } 2846 2847 static int 2848 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 2849 { 2850 struct adapter *adapter = iflib_get_softc(ctx); 2851 int error = E1000_SUCCESS; 2852 struct em_rx_queue *que; 2853 int i; 2854 2855 MPASS(adapter->rx_num_queues > 0); 2856 MPASS(adapter->rx_num_queues == nrxqsets); 2857 2858 /* First allocate the top level queue structs */ 2859 if (!(adapter->rx_queues = 2860 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 2861 adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2862 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2863 error = ENOMEM; 2864 goto fail; 2865 } 2866 2867 for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) { 2868 /* Set up some basics */ 2869 struct rx_ring *rxr = &que->rxr; 2870 rxr->adapter = que->adapter = adapter; 2871 rxr->que = que; 2872 que->me = rxr->me = i; 2873 2874 /* get the virtual and physical address of the hardware queues */ 2875 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 2876 rxr->rx_paddr = paddrs[i*nrxqs]; 2877 } 2878 2879 device_printf(iflib_get_dev(ctx), "allocated for %d rx_queues\n", adapter->rx_num_queues); 2880 2881 return (0); 2882 fail: 2883 em_if_queues_free(ctx); 2884 return (error); 2885 } 2886 2887 static void 2888 em_if_queues_free(if_ctx_t ctx) 2889 { 2890 struct adapter *adapter = iflib_get_softc(ctx); 2891 struct em_tx_queue *tx_que = adapter->tx_queues; 2892 struct em_rx_queue *rx_que = adapter->rx_queues; 2893 2894 if (tx_que != NULL) { 2895 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 2896 struct tx_ring *txr = &tx_que->txr; 2897 if (txr->tx_rsq == NULL) 2898 break; 2899 2900 free(txr->tx_rsq, M_DEVBUF); 2901 txr->tx_rsq = NULL; 2902 } 2903 free(adapter->tx_queues, M_DEVBUF); 2904 adapter->tx_queues = NULL; 2905 } 2906 2907 if (rx_que != NULL) { 2908 free(adapter->rx_queues, M_DEVBUF); 2909 adapter->rx_queues = NULL; 2910 } 2911 2912 em_release_hw_control(adapter); 2913 2914 if (adapter->mta != NULL) { 2915 free(adapter->mta, M_DEVBUF); 2916 } 2917 } 2918 2919 /********************************************************************* 2920 * 2921 * Enable transmit unit. 2922 * 2923 **********************************************************************/ 2924 static void 2925 em_initialize_transmit_unit(if_ctx_t ctx) 2926 { 2927 struct adapter *adapter = iflib_get_softc(ctx); 2928 if_softc_ctx_t scctx = adapter->shared; 2929 struct em_tx_queue *que; 2930 struct tx_ring *txr; 2931 struct e1000_hw *hw = &adapter->hw; 2932 u32 tctl, txdctl = 0, tarc, tipg = 0; 2933 2934 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 2935 2936 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 2937 u64 bus_addr; 2938 caddr_t offp, endp; 2939 2940 que = &adapter->tx_queues[i]; 2941 txr = &que->txr; 2942 bus_addr = txr->tx_paddr; 2943 2944 /* Clear checksum offload context. */ 2945 offp = (caddr_t)&txr->csum_flags; 2946 endp = (caddr_t)(txr + 1); 2947 bzero(offp, endp - offp); 2948 2949 /* Base and Len of TX Ring */ 2950 E1000_WRITE_REG(hw, E1000_TDLEN(i), 2951 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 2952 E1000_WRITE_REG(hw, E1000_TDBAH(i), 2953 (u32)(bus_addr >> 32)); 2954 E1000_WRITE_REG(hw, E1000_TDBAL(i), 2955 (u32)bus_addr); 2956 /* Init the HEAD/TAIL indices */ 2957 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 2958 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 2959 2960 HW_DEBUGOUT2("Base = %x, Length = %x\n", 2961 E1000_READ_REG(&adapter->hw, E1000_TDBAL(i)), 2962 E1000_READ_REG(&adapter->hw, E1000_TDLEN(i))); 2963 2964 txdctl = 0; /* clear txdctl */ 2965 txdctl |= 0x1f; /* PTHRESH */ 2966 txdctl |= 1 << 8; /* HTHRESH */ 2967 txdctl |= 1 << 16;/* WTHRESH */ 2968 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 2969 txdctl |= E1000_TXDCTL_GRAN; 2970 txdctl |= 1 << 25; /* LWTHRESH */ 2971 2972 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 2973 } 2974 2975 /* Set the default values for the Tx Inter Packet Gap timer */ 2976 switch (adapter->hw.mac.type) { 2977 case e1000_80003es2lan: 2978 tipg = DEFAULT_82543_TIPG_IPGR1; 2979 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 2980 E1000_TIPG_IPGR2_SHIFT; 2981 break; 2982 case e1000_82542: 2983 tipg = DEFAULT_82542_TIPG_IPGT; 2984 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2985 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2986 break; 2987 default: 2988 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 2989 (adapter->hw.phy.media_type == 2990 e1000_media_type_internal_serdes)) 2991 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2992 else 2993 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2994 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2995 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2996 } 2997 2998 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg); 2999 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, adapter->tx_int_delay.value); 3000 3001 if(adapter->hw.mac.type >= e1000_82540) 3002 E1000_WRITE_REG(&adapter->hw, E1000_TADV, 3003 adapter->tx_abs_int_delay.value); 3004 3005 if ((adapter->hw.mac.type == e1000_82571) || 3006 (adapter->hw.mac.type == e1000_82572)) { 3007 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3008 tarc |= TARC_SPEED_MODE_BIT; 3009 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3010 } else if (adapter->hw.mac.type == e1000_80003es2lan) { 3011 /* errata: program both queues to unweighted RR */ 3012 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3013 tarc |= 1; 3014 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3015 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1)); 3016 tarc |= 1; 3017 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 3018 } else if (adapter->hw.mac.type == e1000_82574) { 3019 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3020 tarc |= TARC_ERRATA_BIT; 3021 if ( adapter->tx_num_queues > 1) { 3022 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 3023 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3024 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 3025 } else 3026 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3027 } 3028 3029 if (adapter->tx_int_delay.value > 0) 3030 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 3031 3032 /* Program the Transmit Control Register */ 3033 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 3034 tctl &= ~E1000_TCTL_CT; 3035 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3036 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3037 3038 if (adapter->hw.mac.type >= e1000_82571) 3039 tctl |= E1000_TCTL_MULR; 3040 3041 /* This write will effectively turn on the transmit unit. */ 3042 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 3043 3044 if (hw->mac.type == e1000_pch_spt) { 3045 u32 reg; 3046 reg = E1000_READ_REG(hw, E1000_IOSFPC); 3047 reg |= E1000_RCTL_RDMTS_HEX; 3048 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 3049 reg = E1000_READ_REG(hw, E1000_TARC(0)); 3050 reg |= E1000_TARC0_CB_MULTIQ_3_REQ; 3051 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 3052 } 3053 } 3054 3055 /********************************************************************* 3056 * 3057 * Enable receive unit. 3058 * 3059 **********************************************************************/ 3060 3061 static void 3062 em_initialize_receive_unit(if_ctx_t ctx) 3063 { 3064 struct adapter *adapter = iflib_get_softc(ctx); 3065 if_softc_ctx_t scctx = adapter->shared; 3066 struct ifnet *ifp = iflib_get_ifp(ctx); 3067 struct e1000_hw *hw = &adapter->hw; 3068 struct em_rx_queue *que; 3069 int i; 3070 u32 rctl, rxcsum, rfctl; 3071 3072 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 3073 3074 /* 3075 * Make sure receives are disabled while setting 3076 * up the descriptor ring 3077 */ 3078 rctl = E1000_READ_REG(hw, E1000_RCTL); 3079 /* Do not disable if ever enabled on this hardware */ 3080 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 3081 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3082 3083 /* Setup the Receive Control Register */ 3084 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3085 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3086 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3087 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3088 3089 /* Do not store bad packets */ 3090 rctl &= ~E1000_RCTL_SBP; 3091 3092 /* Enable Long Packet receive */ 3093 if (if_getmtu(ifp) > ETHERMTU) 3094 rctl |= E1000_RCTL_LPE; 3095 else 3096 rctl &= ~E1000_RCTL_LPE; 3097 3098 /* Strip the CRC */ 3099 if (!em_disable_crc_stripping) 3100 rctl |= E1000_RCTL_SECRC; 3101 3102 if (adapter->hw.mac.type >= e1000_82540) { 3103 E1000_WRITE_REG(&adapter->hw, E1000_RADV, 3104 adapter->rx_abs_int_delay.value); 3105 3106 /* 3107 * Set the interrupt throttling rate. Value is calculated 3108 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 3109 */ 3110 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR); 3111 } 3112 E1000_WRITE_REG(&adapter->hw, E1000_RDTR, 3113 adapter->rx_int_delay.value); 3114 3115 /* Use extended rx descriptor formats */ 3116 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3117 rfctl |= E1000_RFCTL_EXTEN; 3118 /* 3119 * When using MSIX interrupts we need to throttle 3120 * using the EITR register (82574 only) 3121 */ 3122 if (hw->mac.type == e1000_82574) { 3123 for (int i = 0; i < 4; i++) 3124 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 3125 DEFAULT_ITR); 3126 /* Disable accelerated acknowledge */ 3127 rfctl |= E1000_RFCTL_ACK_DIS; 3128 } 3129 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 3130 3131 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 3132 if (if_getcapenable(ifp) & IFCAP_RXCSUM && 3133 adapter->hw.mac.type >= e1000_82543) { 3134 if (adapter->tx_num_queues > 1) { 3135 if (adapter->hw.mac.type >= igb_mac_min) { 3136 rxcsum |= E1000_RXCSUM_PCSD; 3137 if (hw->mac.type != e1000_82575) 3138 rxcsum |= E1000_RXCSUM_CRCOFL; 3139 } else 3140 rxcsum |= E1000_RXCSUM_TUOFL | 3141 E1000_RXCSUM_IPOFL | 3142 E1000_RXCSUM_PCSD; 3143 } else { 3144 if (adapter->hw.mac.type >= igb_mac_min) 3145 rxcsum |= E1000_RXCSUM_IPPCSE; 3146 else 3147 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 3148 if (adapter->hw.mac.type > e1000_82575) 3149 rxcsum |= E1000_RXCSUM_CRCOFL; 3150 } 3151 } else 3152 rxcsum &= ~E1000_RXCSUM_TUOFL; 3153 3154 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 3155 3156 if (adapter->rx_num_queues > 1) { 3157 if (adapter->hw.mac.type >= igb_mac_min) 3158 igb_initialize_rss_mapping(adapter); 3159 else 3160 em_initialize_rss_mapping(adapter); 3161 } 3162 3163 /* 3164 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3165 * long latencies are observed, like Lenovo X60. This 3166 * change eliminates the problem, but since having positive 3167 * values in RDTR is a known source of problems on other 3168 * platforms another solution is being sought. 3169 */ 3170 if (hw->mac.type == e1000_82573) 3171 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 3172 3173 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 3174 struct rx_ring *rxr = &que->rxr; 3175 /* Setup the Base and Length of the Rx Descriptor Ring */ 3176 u64 bus_addr = rxr->rx_paddr; 3177 #if 0 3178 u32 rdt = adapter->rx_num_queues -1; /* default */ 3179 #endif 3180 3181 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3182 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended)); 3183 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3184 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3185 /* Setup the Head and Tail Descriptor Pointers */ 3186 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3187 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3188 } 3189 3190 /* 3191 * Set PTHRESH for improved jumbo performance 3192 * According to 10.2.5.11 of Intel 82574 Datasheet, 3193 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3194 * Only write to RXDCTL(1) if there is a need for different 3195 * settings. 3196 */ 3197 3198 if (((adapter->hw.mac.type == e1000_ich9lan) || 3199 (adapter->hw.mac.type == e1000_pch2lan) || 3200 (adapter->hw.mac.type == e1000_ich10lan)) && 3201 (if_getmtu(ifp) > ETHERMTU)) { 3202 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3203 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3204 } else if (adapter->hw.mac.type == e1000_82574) { 3205 for (int i = 0; i < adapter->rx_num_queues; i++) { 3206 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3207 rxdctl |= 0x20; /* PTHRESH */ 3208 rxdctl |= 4 << 8; /* HTHRESH */ 3209 rxdctl |= 4 << 16;/* WTHRESH */ 3210 rxdctl |= 1 << 24; /* Switch to granularity */ 3211 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3212 } 3213 } else if (adapter->hw.mac.type >= igb_mac_min) { 3214 u32 psize, srrctl = 0; 3215 3216 if (if_getmtu(ifp) > ETHERMTU) { 3217 /* Set maximum packet len */ 3218 if (adapter->rx_mbuf_sz <= 4096) { 3219 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3220 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3221 } else if (adapter->rx_mbuf_sz > 4096) { 3222 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3223 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3224 } 3225 psize = scctx->isc_max_frame_size; 3226 /* are we on a vlan? */ 3227 if (ifp->if_vlantrunk != NULL) 3228 psize += VLAN_TAG_SIZE; 3229 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize); 3230 } else { 3231 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3232 rctl |= E1000_RCTL_SZ_2048; 3233 } 3234 3235 /* 3236 * If TX flow control is disabled and there's >1 queue defined, 3237 * enable DROP. 3238 * 3239 * This drops frames rather than hanging the RX MAC for all queues. 3240 */ 3241 if ((adapter->rx_num_queues > 1) && 3242 (adapter->fc == e1000_fc_none || 3243 adapter->fc == e1000_fc_rx_pause)) { 3244 srrctl |= E1000_SRRCTL_DROP_EN; 3245 } 3246 /* Setup the Base and Length of the Rx Descriptor Rings */ 3247 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 3248 struct rx_ring *rxr = &que->rxr; 3249 u64 bus_addr = rxr->rx_paddr; 3250 u32 rxdctl; 3251 3252 #ifdef notyet 3253 /* Configure for header split? -- ignore for now */ 3254 rxr->hdr_split = igb_header_split; 3255 #else 3256 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3257 #endif 3258 3259 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3260 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc)); 3261 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3262 (uint32_t)(bus_addr >> 32)); 3263 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3264 (uint32_t)bus_addr); 3265 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3266 /* Enable this Queue */ 3267 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3268 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3269 rxdctl &= 0xFFF00000; 3270 rxdctl |= IGB_RX_PTHRESH; 3271 rxdctl |= IGB_RX_HTHRESH << 8; 3272 rxdctl |= IGB_RX_WTHRESH << 16; 3273 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3274 } 3275 } else if (adapter->hw.mac.type >= e1000_pch2lan) { 3276 if (if_getmtu(ifp) > ETHERMTU) 3277 e1000_lv_jumbo_workaround_ich8lan(hw, TRUE); 3278 else 3279 e1000_lv_jumbo_workaround_ich8lan(hw, FALSE); 3280 } 3281 3282 /* Make sure VLAN Filters are off */ 3283 rctl &= ~E1000_RCTL_VFE; 3284 3285 if (adapter->hw.mac.type < igb_mac_min) { 3286 if (adapter->rx_mbuf_sz == MCLBYTES) 3287 rctl |= E1000_RCTL_SZ_2048; 3288 else if (adapter->rx_mbuf_sz == MJUMPAGESIZE) 3289 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3290 else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) 3291 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3292 3293 /* ensure we clear use DTYPE of 00 here */ 3294 rctl &= ~0x00000C00; 3295 } 3296 3297 /* Write out the settings */ 3298 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3299 3300 return; 3301 } 3302 3303 static void 3304 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 3305 { 3306 struct adapter *adapter = iflib_get_softc(ctx); 3307 u32 index, bit; 3308 3309 index = (vtag >> 5) & 0x7F; 3310 bit = vtag & 0x1F; 3311 adapter->shadow_vfta[index] |= (1 << bit); 3312 ++adapter->num_vlans; 3313 } 3314 3315 static void 3316 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 3317 { 3318 struct adapter *adapter = iflib_get_softc(ctx); 3319 u32 index, bit; 3320 3321 index = (vtag >> 5) & 0x7F; 3322 bit = vtag & 0x1F; 3323 adapter->shadow_vfta[index] &= ~(1 << bit); 3324 --adapter->num_vlans; 3325 } 3326 3327 static void 3328 em_setup_vlan_hw_support(struct adapter *adapter) 3329 { 3330 struct e1000_hw *hw = &adapter->hw; 3331 u32 reg; 3332 3333 /* 3334 * We get here thru init_locked, meaning 3335 * a soft reset, this has already cleared 3336 * the VFTA and other state, so if there 3337 * have been no vlan's registered do nothing. 3338 */ 3339 if (adapter->num_vlans == 0) 3340 return; 3341 3342 /* 3343 * A soft reset zero's out the VFTA, so 3344 * we need to repopulate it now. 3345 */ 3346 for (int i = 0; i < EM_VFTA_SIZE; i++) 3347 if (adapter->shadow_vfta[i] != 0) 3348 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, 3349 i, adapter->shadow_vfta[i]); 3350 3351 reg = E1000_READ_REG(hw, E1000_CTRL); 3352 reg |= E1000_CTRL_VME; 3353 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3354 3355 /* Enable the Filter Table */ 3356 reg = E1000_READ_REG(hw, E1000_RCTL); 3357 reg &= ~E1000_RCTL_CFIEN; 3358 reg |= E1000_RCTL_VFE; 3359 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3360 } 3361 3362 static void 3363 em_if_enable_intr(if_ctx_t ctx) 3364 { 3365 struct adapter *adapter = iflib_get_softc(ctx); 3366 struct e1000_hw *hw = &adapter->hw; 3367 u32 ims_mask = IMS_ENABLE_MASK; 3368 3369 if (hw->mac.type == e1000_82574) { 3370 E1000_WRITE_REG(hw, EM_EIAC, EM_MSIX_MASK); 3371 ims_mask |= adapter->ims; 3372 } else if (adapter->intr_type == IFLIB_INTR_MSIX && hw->mac.type >= igb_mac_min) { 3373 u32 mask = (adapter->que_mask | adapter->link_mask); 3374 3375 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, mask); 3376 E1000_WRITE_REG(&adapter->hw, E1000_EIAM, mask); 3377 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, mask); 3378 ims_mask = E1000_IMS_LSC; 3379 } 3380 3381 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 3382 } 3383 3384 static void 3385 em_if_disable_intr(if_ctx_t ctx) 3386 { 3387 struct adapter *adapter = iflib_get_softc(ctx); 3388 struct e1000_hw *hw = &adapter->hw; 3389 3390 if (adapter->intr_type == IFLIB_INTR_MSIX) { 3391 if (hw->mac.type >= igb_mac_min) 3392 E1000_WRITE_REG(&adapter->hw, E1000_EIMC, ~0); 3393 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, 0); 3394 } 3395 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); 3396 } 3397 3398 /* 3399 * Bit of a misnomer, what this really means is 3400 * to enable OS management of the system... aka 3401 * to disable special hardware management features 3402 */ 3403 static void 3404 em_init_manageability(struct adapter *adapter) 3405 { 3406 /* A shared code workaround */ 3407 #define E1000_82542_MANC2H E1000_MANC2H 3408 if (adapter->has_manage) { 3409 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H); 3410 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3411 3412 /* disable hardware interception of ARP */ 3413 manc &= ~(E1000_MANC_ARP_EN); 3414 3415 /* enable receiving management packets to the host */ 3416 manc |= E1000_MANC_EN_MNG2HOST; 3417 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3418 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3419 manc2h |= E1000_MNG2HOST_PORT_623; 3420 manc2h |= E1000_MNG2HOST_PORT_664; 3421 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h); 3422 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3423 } 3424 } 3425 3426 /* 3427 * Give control back to hardware management 3428 * controller if there is one. 3429 */ 3430 static void 3431 em_release_manageability(struct adapter *adapter) 3432 { 3433 if (adapter->has_manage) { 3434 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3435 3436 /* re-enable hardware interception of ARP */ 3437 manc |= E1000_MANC_ARP_EN; 3438 manc &= ~E1000_MANC_EN_MNG2HOST; 3439 3440 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3441 } 3442 } 3443 3444 /* 3445 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 3446 * For ASF and Pass Through versions of f/w this means 3447 * that the driver is loaded. For AMT version type f/w 3448 * this means that the network i/f is open. 3449 */ 3450 static void 3451 em_get_hw_control(struct adapter *adapter) 3452 { 3453 u32 ctrl_ext, swsm; 3454 3455 if (adapter->vf_ifp) 3456 return; 3457 3458 if (adapter->hw.mac.type == e1000_82573) { 3459 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3460 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3461 swsm | E1000_SWSM_DRV_LOAD); 3462 return; 3463 } 3464 /* else */ 3465 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3466 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3467 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3468 } 3469 3470 /* 3471 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3472 * For ASF and Pass Through versions of f/w this means that 3473 * the driver is no longer loaded. For AMT versions of the 3474 * f/w this means that the network i/f is closed. 3475 */ 3476 static void 3477 em_release_hw_control(struct adapter *adapter) 3478 { 3479 u32 ctrl_ext, swsm; 3480 3481 if (!adapter->has_manage) 3482 return; 3483 3484 if (adapter->hw.mac.type == e1000_82573) { 3485 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3486 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3487 swsm & ~E1000_SWSM_DRV_LOAD); 3488 return; 3489 } 3490 /* else */ 3491 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3492 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3493 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3494 return; 3495 } 3496 3497 static int 3498 em_is_valid_ether_addr(u8 *addr) 3499 { 3500 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3501 3502 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3503 return (FALSE); 3504 } 3505 3506 return (TRUE); 3507 } 3508 3509 /* 3510 ** Parse the interface capabilities with regard 3511 ** to both system management and wake-on-lan for 3512 ** later use. 3513 */ 3514 static void 3515 em_get_wakeup(if_ctx_t ctx) 3516 { 3517 struct adapter *adapter = iflib_get_softc(ctx); 3518 device_t dev = iflib_get_dev(ctx); 3519 u16 eeprom_data = 0, device_id, apme_mask; 3520 3521 adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw); 3522 apme_mask = EM_EEPROM_APME; 3523 3524 switch (adapter->hw.mac.type) { 3525 case e1000_82542: 3526 case e1000_82543: 3527 break; 3528 case e1000_82544: 3529 e1000_read_nvm(&adapter->hw, 3530 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 3531 apme_mask = EM_82544_APME; 3532 break; 3533 case e1000_82546: 3534 case e1000_82546_rev_3: 3535 if (adapter->hw.bus.func == 1) { 3536 e1000_read_nvm(&adapter->hw, 3537 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3538 break; 3539 } else 3540 e1000_read_nvm(&adapter->hw, 3541 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3542 break; 3543 case e1000_82573: 3544 case e1000_82583: 3545 adapter->has_amt = TRUE; 3546 /* FALLTHROUGH */ 3547 case e1000_82571: 3548 case e1000_82572: 3549 case e1000_80003es2lan: 3550 if (adapter->hw.bus.func == 1) { 3551 e1000_read_nvm(&adapter->hw, 3552 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3553 break; 3554 } else 3555 e1000_read_nvm(&adapter->hw, 3556 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3557 break; 3558 case e1000_ich8lan: 3559 case e1000_ich9lan: 3560 case e1000_ich10lan: 3561 case e1000_pchlan: 3562 case e1000_pch2lan: 3563 case e1000_pch_lpt: 3564 case e1000_pch_spt: 3565 case e1000_82575: /* listing all igb devices */ 3566 case e1000_82576: 3567 case e1000_82580: 3568 case e1000_i350: 3569 case e1000_i354: 3570 case e1000_i210: 3571 case e1000_i211: 3572 case e1000_vfadapt: 3573 case e1000_vfadapt_i350: 3574 apme_mask = E1000_WUC_APME; 3575 adapter->has_amt = TRUE; 3576 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC); 3577 break; 3578 default: 3579 e1000_read_nvm(&adapter->hw, 3580 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3581 break; 3582 } 3583 if (eeprom_data & apme_mask) 3584 adapter->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 3585 /* 3586 * We have the eeprom settings, now apply the special cases 3587 * where the eeprom may be wrong or the board won't support 3588 * wake on lan on a particular port 3589 */ 3590 device_id = pci_get_device(dev); 3591 switch (device_id) { 3592 case E1000_DEV_ID_82546GB_PCIE: 3593 adapter->wol = 0; 3594 break; 3595 case E1000_DEV_ID_82546EB_FIBER: 3596 case E1000_DEV_ID_82546GB_FIBER: 3597 /* Wake events only supported on port A for dual fiber 3598 * regardless of eeprom setting */ 3599 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3600 E1000_STATUS_FUNC_1) 3601 adapter->wol = 0; 3602 break; 3603 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 3604 /* if quad port adapter, disable WoL on all but port A */ 3605 if (global_quad_port_a != 0) 3606 adapter->wol = 0; 3607 /* Reset for multiple quad port adapters */ 3608 if (++global_quad_port_a == 4) 3609 global_quad_port_a = 0; 3610 break; 3611 case E1000_DEV_ID_82571EB_FIBER: 3612 /* Wake events only supported on port A for dual fiber 3613 * regardless of eeprom setting */ 3614 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3615 E1000_STATUS_FUNC_1) 3616 adapter->wol = 0; 3617 break; 3618 case E1000_DEV_ID_82571EB_QUAD_COPPER: 3619 case E1000_DEV_ID_82571EB_QUAD_FIBER: 3620 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 3621 /* if quad port adapter, disable WoL on all but port A */ 3622 if (global_quad_port_a != 0) 3623 adapter->wol = 0; 3624 /* Reset for multiple quad port adapters */ 3625 if (++global_quad_port_a == 4) 3626 global_quad_port_a = 0; 3627 break; 3628 } 3629 return; 3630 } 3631 3632 3633 /* 3634 * Enable PCI Wake On Lan capability 3635 */ 3636 static void 3637 em_enable_wakeup(if_ctx_t ctx) 3638 { 3639 struct adapter *adapter = iflib_get_softc(ctx); 3640 device_t dev = iflib_get_dev(ctx); 3641 if_t ifp = iflib_get_ifp(ctx); 3642 u32 pmc, ctrl, ctrl_ext, rctl, wuc; 3643 u16 status; 3644 3645 if ((pci_find_cap(dev, PCIY_PMG, &pmc) != 0)) 3646 return; 3647 3648 /* Advertise the wakeup capability */ 3649 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 3650 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 3651 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 3652 wuc = E1000_READ_REG(&adapter->hw, E1000_WUC); 3653 wuc |= (E1000_WUC_PME_EN | E1000_WUC_APME); 3654 E1000_WRITE_REG(&adapter->hw, E1000_WUC, wuc); 3655 3656 if ((adapter->hw.mac.type == e1000_ich8lan) || 3657 (adapter->hw.mac.type == e1000_pchlan) || 3658 (adapter->hw.mac.type == e1000_ich9lan) || 3659 (adapter->hw.mac.type == e1000_ich10lan)) 3660 e1000_suspend_workarounds_ich8lan(&adapter->hw); 3661 3662 /* Keep the laser running on Fiber adapters */ 3663 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 3664 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 3665 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3666 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 3667 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext); 3668 } 3669 3670 /* 3671 * Determine type of Wakeup: note that wol 3672 * is set with all bits on by default. 3673 */ 3674 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 3675 adapter->wol &= ~E1000_WUFC_MAG; 3676 3677 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 3678 adapter->wol &= ~E1000_WUFC_EX; 3679 3680 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 3681 adapter->wol &= ~E1000_WUFC_MC; 3682 else { 3683 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 3684 rctl |= E1000_RCTL_MPE; 3685 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); 3686 } 3687 3688 if ( adapter->hw.mac.type >= e1000_pchlan) { 3689 if (em_enable_phy_wakeup(adapter)) 3690 return; 3691 } else { 3692 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 3693 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 3694 } 3695 3696 if (adapter->hw.phy.type == e1000_phy_igp_3) 3697 e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); 3698 3699 /* Request PME */ 3700 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 3701 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3702 if (if_getcapenable(ifp) & IFCAP_WOL) 3703 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3704 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 3705 3706 return; 3707 } 3708 3709 /* 3710 * WOL in the newer chipset interfaces (pchlan) 3711 * require thing to be copied into the phy 3712 */ 3713 static int 3714 em_enable_phy_wakeup(struct adapter *adapter) 3715 { 3716 struct e1000_hw *hw = &adapter->hw; 3717 u32 mreg, ret = 0; 3718 u16 preg; 3719 3720 /* copy MAC RARs to PHY RARs */ 3721 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 3722 3723 /* copy MAC MTA to PHY MTA */ 3724 for (int i = 0; i < adapter->hw.mac.mta_reg_count; i++) { 3725 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 3726 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 3727 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 3728 (u16)((mreg >> 16) & 0xFFFF)); 3729 } 3730 3731 /* configure PHY Rx Control register */ 3732 e1000_read_phy_reg(&adapter->hw, BM_RCTL, &preg); 3733 mreg = E1000_READ_REG(hw, E1000_RCTL); 3734 if (mreg & E1000_RCTL_UPE) 3735 preg |= BM_RCTL_UPE; 3736 if (mreg & E1000_RCTL_MPE) 3737 preg |= BM_RCTL_MPE; 3738 preg &= ~(BM_RCTL_MO_MASK); 3739 if (mreg & E1000_RCTL_MO_3) 3740 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 3741 << BM_RCTL_MO_SHIFT); 3742 if (mreg & E1000_RCTL_BAM) 3743 preg |= BM_RCTL_BAM; 3744 if (mreg & E1000_RCTL_PMCF) 3745 preg |= BM_RCTL_PMCF; 3746 mreg = E1000_READ_REG(hw, E1000_CTRL); 3747 if (mreg & E1000_CTRL_RFCE) 3748 preg |= BM_RCTL_RFCE; 3749 e1000_write_phy_reg(&adapter->hw, BM_RCTL, preg); 3750 3751 /* enable PHY wakeup in MAC register */ 3752 E1000_WRITE_REG(hw, E1000_WUC, 3753 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 3754 E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol); 3755 3756 /* configure and enable PHY wakeup in PHY registers */ 3757 e1000_write_phy_reg(&adapter->hw, BM_WUFC, adapter->wol); 3758 e1000_write_phy_reg(&adapter->hw, BM_WUC, E1000_WUC_PME_EN); 3759 3760 /* activate PHY wakeup */ 3761 ret = hw->phy.ops.acquire(hw); 3762 if (ret) { 3763 printf("Could not acquire PHY\n"); 3764 return ret; 3765 } 3766 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 3767 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 3768 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 3769 if (ret) { 3770 printf("Could not read PHY page 769\n"); 3771 goto out; 3772 } 3773 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 3774 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 3775 if (ret) 3776 printf("Could not set PHY Host Wakeup bit\n"); 3777 out: 3778 hw->phy.ops.release(hw); 3779 3780 return ret; 3781 } 3782 3783 static void 3784 em_if_led_func(if_ctx_t ctx, int onoff) 3785 { 3786 struct adapter *adapter = iflib_get_softc(ctx); 3787 3788 if (onoff) { 3789 e1000_setup_led(&adapter->hw); 3790 e1000_led_on(&adapter->hw); 3791 } else { 3792 e1000_led_off(&adapter->hw); 3793 e1000_cleanup_led(&adapter->hw); 3794 } 3795 } 3796 3797 /* 3798 * Disable the L0S and L1 LINK states 3799 */ 3800 static void 3801 em_disable_aspm(struct adapter *adapter) 3802 { 3803 int base, reg; 3804 u16 link_cap,link_ctrl; 3805 device_t dev = adapter->dev; 3806 3807 switch (adapter->hw.mac.type) { 3808 case e1000_82573: 3809 case e1000_82574: 3810 case e1000_82583: 3811 break; 3812 default: 3813 return; 3814 } 3815 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 3816 return; 3817 reg = base + PCIER_LINK_CAP; 3818 link_cap = pci_read_config(dev, reg, 2); 3819 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 3820 return; 3821 reg = base + PCIER_LINK_CTL; 3822 link_ctrl = pci_read_config(dev, reg, 2); 3823 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 3824 pci_write_config(dev, reg, link_ctrl, 2); 3825 return; 3826 } 3827 3828 /********************************************************************** 3829 * 3830 * Update the board statistics counters. 3831 * 3832 **********************************************************************/ 3833 static void 3834 em_update_stats_counters(struct adapter *adapter) 3835 { 3836 3837 if(adapter->hw.phy.media_type == e1000_media_type_copper || 3838 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) { 3839 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS); 3840 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC); 3841 } 3842 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS); 3843 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC); 3844 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC); 3845 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL); 3846 3847 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC); 3848 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL); 3849 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC); 3850 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC); 3851 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC); 3852 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC); 3853 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC); 3854 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC); 3855 /* 3856 ** For watchdog management we need to know if we have been 3857 ** paused during the last interval, so capture that here. 3858 */ 3859 adapter->shared->isc_pause_frames = adapter->stats.xoffrxc; 3860 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC); 3861 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC); 3862 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64); 3863 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127); 3864 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255); 3865 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511); 3866 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023); 3867 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522); 3868 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC); 3869 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC); 3870 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC); 3871 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC); 3872 3873 /* For the 64-bit byte counters the low dword must be read first. */ 3874 /* Both registers clear on the read of the high dword */ 3875 3876 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCL) + 3877 ((u64)E1000_READ_REG(&adapter->hw, E1000_GORCH) << 32); 3878 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCL) + 3879 ((u64)E1000_READ_REG(&adapter->hw, E1000_GOTCH) << 32); 3880 3881 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC); 3882 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC); 3883 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC); 3884 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC); 3885 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC); 3886 3887 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH); 3888 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH); 3889 3890 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR); 3891 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT); 3892 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64); 3893 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127); 3894 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255); 3895 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511); 3896 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023); 3897 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522); 3898 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC); 3899 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC); 3900 3901 /* Interrupt Counts */ 3902 3903 adapter->stats.iac += E1000_READ_REG(&adapter->hw, E1000_IAC); 3904 adapter->stats.icrxptc += E1000_READ_REG(&adapter->hw, E1000_ICRXPTC); 3905 adapter->stats.icrxatc += E1000_READ_REG(&adapter->hw, E1000_ICRXATC); 3906 adapter->stats.ictxptc += E1000_READ_REG(&adapter->hw, E1000_ICTXPTC); 3907 adapter->stats.ictxatc += E1000_READ_REG(&adapter->hw, E1000_ICTXATC); 3908 adapter->stats.ictxqec += E1000_READ_REG(&adapter->hw, E1000_ICTXQEC); 3909 adapter->stats.ictxqmtc += E1000_READ_REG(&adapter->hw, E1000_ICTXQMTC); 3910 adapter->stats.icrxdmtc += E1000_READ_REG(&adapter->hw, E1000_ICRXDMTC); 3911 adapter->stats.icrxoc += E1000_READ_REG(&adapter->hw, E1000_ICRXOC); 3912 3913 if (adapter->hw.mac.type >= e1000_82543) { 3914 adapter->stats.algnerrc += 3915 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC); 3916 adapter->stats.rxerrc += 3917 E1000_READ_REG(&adapter->hw, E1000_RXERRC); 3918 adapter->stats.tncrs += 3919 E1000_READ_REG(&adapter->hw, E1000_TNCRS); 3920 adapter->stats.cexterr += 3921 E1000_READ_REG(&adapter->hw, E1000_CEXTERR); 3922 adapter->stats.tsctc += 3923 E1000_READ_REG(&adapter->hw, E1000_TSCTC); 3924 adapter->stats.tsctfc += 3925 E1000_READ_REG(&adapter->hw, E1000_TSCTFC); 3926 } 3927 } 3928 3929 static uint64_t 3930 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 3931 { 3932 struct adapter *adapter = iflib_get_softc(ctx); 3933 struct ifnet *ifp = iflib_get_ifp(ctx); 3934 3935 switch (cnt) { 3936 case IFCOUNTER_COLLISIONS: 3937 return (adapter->stats.colc); 3938 case IFCOUNTER_IERRORS: 3939 return (adapter->dropped_pkts + adapter->stats.rxerrc + 3940 adapter->stats.crcerrs + adapter->stats.algnerrc + 3941 adapter->stats.ruc + adapter->stats.roc + 3942 adapter->stats.mpc + adapter->stats.cexterr); 3943 case IFCOUNTER_OERRORS: 3944 return (adapter->stats.ecol + adapter->stats.latecol + 3945 adapter->watchdog_events); 3946 default: 3947 return (if_get_counter_default(ifp, cnt)); 3948 } 3949 } 3950 3951 /* Export a single 32-bit register via a read-only sysctl. */ 3952 static int 3953 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 3954 { 3955 struct adapter *adapter; 3956 u_int val; 3957 3958 adapter = oidp->oid_arg1; 3959 val = E1000_READ_REG(&adapter->hw, oidp->oid_arg2); 3960 return (sysctl_handle_int(oidp, &val, 0, req)); 3961 } 3962 3963 /* 3964 * Add sysctl variables, one per statistic, to the system. 3965 */ 3966 static void 3967 em_add_hw_stats(struct adapter *adapter) 3968 { 3969 device_t dev = iflib_get_dev(adapter->ctx); 3970 struct em_tx_queue *tx_que = adapter->tx_queues; 3971 struct em_rx_queue *rx_que = adapter->rx_queues; 3972 3973 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 3974 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 3975 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 3976 struct e1000_hw_stats *stats = &adapter->stats; 3977 3978 struct sysctl_oid *stat_node, *queue_node, *int_node; 3979 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 3980 3981 #define QUEUE_NAME_LEN 32 3982 char namebuf[QUEUE_NAME_LEN]; 3983 3984 /* Driver Statistics */ 3985 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 3986 CTLFLAG_RD, &adapter->dropped_pkts, 3987 "Driver dropped packets"); 3988 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 3989 CTLFLAG_RD, &adapter->link_irq, 3990 "Link MSIX IRQ Handled"); 3991 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "mbuf_defrag_fail", 3992 CTLFLAG_RD, &adapter->mbuf_defrag_failed, 3993 "Defragmenting mbuf chain failed"); 3994 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "tx_dma_fail", 3995 CTLFLAG_RD, &adapter->no_tx_dma_setup, 3996 "Driver tx dma failure in xmit"); 3997 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 3998 CTLFLAG_RD, &adapter->rx_overruns, 3999 "RX overruns"); 4000 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 4001 CTLFLAG_RD, &adapter->watchdog_events, 4002 "Watchdog timeouts"); 4003 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 4004 CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_CTRL, 4005 em_sysctl_reg_handler, "IU", 4006 "Device Control Register"); 4007 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 4008 CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_RCTL, 4009 em_sysctl_reg_handler, "IU", 4010 "Receiver Control Register"); 4011 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 4012 CTLFLAG_RD, &adapter->hw.fc.high_water, 0, 4013 "Flow Control High Watermark"); 4014 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 4015 CTLFLAG_RD, &adapter->hw.fc.low_water, 0, 4016 "Flow Control Low Watermark"); 4017 4018 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 4019 struct tx_ring *txr = &tx_que->txr; 4020 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 4021 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4022 CTLFLAG_RD, NULL, "TX Queue Name"); 4023 queue_list = SYSCTL_CHILDREN(queue_node); 4024 4025 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 4026 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4027 E1000_TDH(txr->me), 4028 em_sysctl_reg_handler, "IU", 4029 "Transmit Descriptor Head"); 4030 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 4031 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4032 E1000_TDT(txr->me), 4033 em_sysctl_reg_handler, "IU", 4034 "Transmit Descriptor Tail"); 4035 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 4036 CTLFLAG_RD, &txr->tx_irq, 4037 "Queue MSI-X Transmit Interrupts"); 4038 } 4039 4040 for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) { 4041 struct rx_ring *rxr = &rx_que->rxr; 4042 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 4043 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4044 CTLFLAG_RD, NULL, "RX Queue Name"); 4045 queue_list = SYSCTL_CHILDREN(queue_node); 4046 4047 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 4048 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4049 E1000_RDH(rxr->me), 4050 em_sysctl_reg_handler, "IU", 4051 "Receive Descriptor Head"); 4052 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 4053 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4054 E1000_RDT(rxr->me), 4055 em_sysctl_reg_handler, "IU", 4056 "Receive Descriptor Tail"); 4057 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 4058 CTLFLAG_RD, &rxr->rx_irq, 4059 "Queue MSI-X Receive Interrupts"); 4060 } 4061 4062 /* MAC stats get their own sub node */ 4063 4064 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 4065 CTLFLAG_RD, NULL, "Statistics"); 4066 stat_list = SYSCTL_CHILDREN(stat_node); 4067 4068 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 4069 CTLFLAG_RD, &stats->ecol, 4070 "Excessive collisions"); 4071 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 4072 CTLFLAG_RD, &stats->scc, 4073 "Single collisions"); 4074 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 4075 CTLFLAG_RD, &stats->mcc, 4076 "Multiple collisions"); 4077 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 4078 CTLFLAG_RD, &stats->latecol, 4079 "Late collisions"); 4080 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 4081 CTLFLAG_RD, &stats->colc, 4082 "Collision Count"); 4083 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 4084 CTLFLAG_RD, &adapter->stats.symerrs, 4085 "Symbol Errors"); 4086 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 4087 CTLFLAG_RD, &adapter->stats.sec, 4088 "Sequence Errors"); 4089 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 4090 CTLFLAG_RD, &adapter->stats.dc, 4091 "Defer Count"); 4092 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 4093 CTLFLAG_RD, &adapter->stats.mpc, 4094 "Missed Packets"); 4095 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 4096 CTLFLAG_RD, &adapter->stats.rnbc, 4097 "Receive No Buffers"); 4098 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 4099 CTLFLAG_RD, &adapter->stats.ruc, 4100 "Receive Undersize"); 4101 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 4102 CTLFLAG_RD, &adapter->stats.rfc, 4103 "Fragmented Packets Received "); 4104 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 4105 CTLFLAG_RD, &adapter->stats.roc, 4106 "Oversized Packets Received"); 4107 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 4108 CTLFLAG_RD, &adapter->stats.rjc, 4109 "Recevied Jabber"); 4110 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 4111 CTLFLAG_RD, &adapter->stats.rxerrc, 4112 "Receive Errors"); 4113 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 4114 CTLFLAG_RD, &adapter->stats.crcerrs, 4115 "CRC errors"); 4116 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 4117 CTLFLAG_RD, &adapter->stats.algnerrc, 4118 "Alignment Errors"); 4119 /* On 82575 these are collision counts */ 4120 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 4121 CTLFLAG_RD, &adapter->stats.cexterr, 4122 "Collision/Carrier extension errors"); 4123 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 4124 CTLFLAG_RD, &adapter->stats.xonrxc, 4125 "XON Received"); 4126 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 4127 CTLFLAG_RD, &adapter->stats.xontxc, 4128 "XON Transmitted"); 4129 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 4130 CTLFLAG_RD, &adapter->stats.xoffrxc, 4131 "XOFF Received"); 4132 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 4133 CTLFLAG_RD, &adapter->stats.xofftxc, 4134 "XOFF Transmitted"); 4135 4136 /* Packet Reception Stats */ 4137 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 4138 CTLFLAG_RD, &adapter->stats.tpr, 4139 "Total Packets Received "); 4140 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 4141 CTLFLAG_RD, &adapter->stats.gprc, 4142 "Good Packets Received"); 4143 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 4144 CTLFLAG_RD, &adapter->stats.bprc, 4145 "Broadcast Packets Received"); 4146 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 4147 CTLFLAG_RD, &adapter->stats.mprc, 4148 "Multicast Packets Received"); 4149 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 4150 CTLFLAG_RD, &adapter->stats.prc64, 4151 "64 byte frames received "); 4152 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 4153 CTLFLAG_RD, &adapter->stats.prc127, 4154 "65-127 byte frames received"); 4155 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 4156 CTLFLAG_RD, &adapter->stats.prc255, 4157 "128-255 byte frames received"); 4158 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 4159 CTLFLAG_RD, &adapter->stats.prc511, 4160 "256-511 byte frames received"); 4161 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 4162 CTLFLAG_RD, &adapter->stats.prc1023, 4163 "512-1023 byte frames received"); 4164 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 4165 CTLFLAG_RD, &adapter->stats.prc1522, 4166 "1023-1522 byte frames received"); 4167 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 4168 CTLFLAG_RD, &adapter->stats.gorc, 4169 "Good Octets Received"); 4170 4171 /* Packet Transmission Stats */ 4172 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 4173 CTLFLAG_RD, &adapter->stats.gotc, 4174 "Good Octets Transmitted"); 4175 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 4176 CTLFLAG_RD, &adapter->stats.tpt, 4177 "Total Packets Transmitted"); 4178 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 4179 CTLFLAG_RD, &adapter->stats.gptc, 4180 "Good Packets Transmitted"); 4181 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 4182 CTLFLAG_RD, &adapter->stats.bptc, 4183 "Broadcast Packets Transmitted"); 4184 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 4185 CTLFLAG_RD, &adapter->stats.mptc, 4186 "Multicast Packets Transmitted"); 4187 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 4188 CTLFLAG_RD, &adapter->stats.ptc64, 4189 "64 byte frames transmitted "); 4190 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 4191 CTLFLAG_RD, &adapter->stats.ptc127, 4192 "65-127 byte frames transmitted"); 4193 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 4194 CTLFLAG_RD, &adapter->stats.ptc255, 4195 "128-255 byte frames transmitted"); 4196 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 4197 CTLFLAG_RD, &adapter->stats.ptc511, 4198 "256-511 byte frames transmitted"); 4199 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 4200 CTLFLAG_RD, &adapter->stats.ptc1023, 4201 "512-1023 byte frames transmitted"); 4202 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 4203 CTLFLAG_RD, &adapter->stats.ptc1522, 4204 "1024-1522 byte frames transmitted"); 4205 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 4206 CTLFLAG_RD, &adapter->stats.tsctc, 4207 "TSO Contexts Transmitted"); 4208 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 4209 CTLFLAG_RD, &adapter->stats.tsctfc, 4210 "TSO Contexts Failed"); 4211 4212 4213 /* Interrupt Stats */ 4214 4215 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 4216 CTLFLAG_RD, NULL, "Interrupt Statistics"); 4217 int_list = SYSCTL_CHILDREN(int_node); 4218 4219 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 4220 CTLFLAG_RD, &adapter->stats.iac, 4221 "Interrupt Assertion Count"); 4222 4223 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 4224 CTLFLAG_RD, &adapter->stats.icrxptc, 4225 "Interrupt Cause Rx Pkt Timer Expire Count"); 4226 4227 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 4228 CTLFLAG_RD, &adapter->stats.icrxatc, 4229 "Interrupt Cause Rx Abs Timer Expire Count"); 4230 4231 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 4232 CTLFLAG_RD, &adapter->stats.ictxptc, 4233 "Interrupt Cause Tx Pkt Timer Expire Count"); 4234 4235 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 4236 CTLFLAG_RD, &adapter->stats.ictxatc, 4237 "Interrupt Cause Tx Abs Timer Expire Count"); 4238 4239 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 4240 CTLFLAG_RD, &adapter->stats.ictxqec, 4241 "Interrupt Cause Tx Queue Empty Count"); 4242 4243 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 4244 CTLFLAG_RD, &adapter->stats.ictxqmtc, 4245 "Interrupt Cause Tx Queue Min Thresh Count"); 4246 4247 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 4248 CTLFLAG_RD, &adapter->stats.icrxdmtc, 4249 "Interrupt Cause Rx Desc Min Thresh Count"); 4250 4251 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 4252 CTLFLAG_RD, &adapter->stats.icrxoc, 4253 "Interrupt Cause Receiver Overrun Count"); 4254 } 4255 4256 /********************************************************************** 4257 * 4258 * This routine provides a way to dump out the adapter eeprom, 4259 * often a useful debug/service tool. This only dumps the first 4260 * 32 words, stuff that matters is in that extent. 4261 * 4262 **********************************************************************/ 4263 static int 4264 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 4265 { 4266 struct adapter *adapter = (struct adapter *)arg1; 4267 int error; 4268 int result; 4269 4270 result = -1; 4271 error = sysctl_handle_int(oidp, &result, 0, req); 4272 4273 if (error || !req->newptr) 4274 return (error); 4275 4276 /* 4277 * This value will cause a hex dump of the 4278 * first 32 16-bit words of the EEPROM to 4279 * the screen. 4280 */ 4281 if (result == 1) 4282 em_print_nvm_info(adapter); 4283 4284 return (error); 4285 } 4286 4287 static void 4288 em_print_nvm_info(struct adapter *adapter) 4289 { 4290 u16 eeprom_data; 4291 int i, j, row = 0; 4292 4293 /* Its a bit crude, but it gets the job done */ 4294 printf("\nInterface EEPROM Dump:\n"); 4295 printf("Offset\n0x0000 "); 4296 for (i = 0, j = 0; i < 32; i++, j++) { 4297 if (j == 8) { /* Make the offset block */ 4298 j = 0; ++row; 4299 printf("\n0x00%x0 ",row); 4300 } 4301 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data); 4302 printf("%04x ", eeprom_data); 4303 } 4304 printf("\n"); 4305 } 4306 4307 static int 4308 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4309 { 4310 struct em_int_delay_info *info; 4311 struct adapter *adapter; 4312 u32 regval; 4313 int error, usecs, ticks; 4314 4315 info = (struct em_int_delay_info *) arg1; 4316 usecs = info->value; 4317 error = sysctl_handle_int(oidp, &usecs, 0, req); 4318 if (error != 0 || req->newptr == NULL) 4319 return (error); 4320 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 4321 return (EINVAL); 4322 info->value = usecs; 4323 ticks = EM_USECS_TO_TICKS(usecs); 4324 if (info->offset == E1000_ITR) /* units are 256ns here */ 4325 ticks *= 4; 4326 4327 adapter = info->adapter; 4328 4329 regval = E1000_READ_OFFSET(&adapter->hw, info->offset); 4330 regval = (regval & ~0xffff) | (ticks & 0xffff); 4331 /* Handle a few special cases. */ 4332 switch (info->offset) { 4333 case E1000_RDTR: 4334 break; 4335 case E1000_TIDV: 4336 if (ticks == 0) { 4337 adapter->txd_cmd &= ~E1000_TXD_CMD_IDE; 4338 /* Don't write 0 into the TIDV register. */ 4339 regval++; 4340 } else 4341 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 4342 break; 4343 } 4344 E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval); 4345 return (0); 4346 } 4347 4348 static void 4349 em_add_int_delay_sysctl(struct adapter *adapter, const char *name, 4350 const char *description, struct em_int_delay_info *info, 4351 int offset, int value) 4352 { 4353 info->adapter = adapter; 4354 info->offset = offset; 4355 info->value = value; 4356 SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev), 4357 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), 4358 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 4359 info, 0, em_sysctl_int_delay, "I", description); 4360 } 4361 4362 /* 4363 * Set flow control using sysctl: 4364 * Flow control values: 4365 * 0 - off 4366 * 1 - rx pause 4367 * 2 - tx pause 4368 * 3 - full 4369 */ 4370 static int 4371 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 4372 { 4373 int error; 4374 static int input = 3; /* default is full */ 4375 struct adapter *adapter = (struct adapter *) arg1; 4376 4377 error = sysctl_handle_int(oidp, &input, 0, req); 4378 4379 if ((error) || (req->newptr == NULL)) 4380 return (error); 4381 4382 if (input == adapter->fc) /* no change? */ 4383 return (error); 4384 4385 switch (input) { 4386 case e1000_fc_rx_pause: 4387 case e1000_fc_tx_pause: 4388 case e1000_fc_full: 4389 case e1000_fc_none: 4390 adapter->hw.fc.requested_mode = input; 4391 adapter->fc = input; 4392 break; 4393 default: 4394 /* Do nothing */ 4395 return (error); 4396 } 4397 4398 adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode; 4399 e1000_force_mac_fc(&adapter->hw); 4400 return (error); 4401 } 4402 4403 /* 4404 * Manage Energy Efficient Ethernet: 4405 * Control values: 4406 * 0/1 - enabled/disabled 4407 */ 4408 static int 4409 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 4410 { 4411 struct adapter *adapter = (struct adapter *) arg1; 4412 int error, value; 4413 4414 value = adapter->hw.dev_spec.ich8lan.eee_disable; 4415 error = sysctl_handle_int(oidp, &value, 0, req); 4416 if (error || req->newptr == NULL) 4417 return (error); 4418 adapter->hw.dev_spec.ich8lan.eee_disable = (value != 0); 4419 em_if_init(adapter->ctx); 4420 4421 return (0); 4422 } 4423 4424 static int 4425 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4426 { 4427 struct adapter *adapter; 4428 int error; 4429 int result; 4430 4431 result = -1; 4432 error = sysctl_handle_int(oidp, &result, 0, req); 4433 4434 if (error || !req->newptr) 4435 return (error); 4436 4437 if (result == 1) { 4438 adapter = (struct adapter *) arg1; 4439 em_print_debug_info(adapter); 4440 } 4441 4442 return (error); 4443 } 4444 4445 static int 4446 em_get_rs(SYSCTL_HANDLER_ARGS) 4447 { 4448 struct adapter *adapter = (struct adapter *) arg1; 4449 int error; 4450 int result; 4451 4452 result = 0; 4453 error = sysctl_handle_int(oidp, &result, 0, req); 4454 4455 if (error || !req->newptr || result != 1) 4456 return (error); 4457 em_dump_rs(adapter); 4458 4459 return (error); 4460 } 4461 4462 static void 4463 em_if_debug(if_ctx_t ctx) 4464 { 4465 em_dump_rs(iflib_get_softc(ctx)); 4466 } 4467 4468 /* 4469 * This routine is meant to be fluid, add whatever is 4470 * needed for debugging a problem. -jfv 4471 */ 4472 static void 4473 em_print_debug_info(struct adapter *adapter) 4474 { 4475 device_t dev = iflib_get_dev(adapter->ctx); 4476 struct ifnet *ifp = iflib_get_ifp(adapter->ctx); 4477 struct tx_ring *txr = &adapter->tx_queues->txr; 4478 struct rx_ring *rxr = &adapter->rx_queues->rxr; 4479 4480 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 4481 printf("Interface is RUNNING "); 4482 else 4483 printf("Interface is NOT RUNNING\n"); 4484 4485 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 4486 printf("and INACTIVE\n"); 4487 else 4488 printf("and ACTIVE\n"); 4489 4490 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 4491 device_printf(dev, "TX Queue %d ------\n", i); 4492 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 4493 E1000_READ_REG(&adapter->hw, E1000_TDH(i)), 4494 E1000_READ_REG(&adapter->hw, E1000_TDT(i))); 4495 4496 } 4497 for (int j=0; j < adapter->rx_num_queues; j++, rxr++) { 4498 device_printf(dev, "RX Queue %d ------\n", j); 4499 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 4500 E1000_READ_REG(&adapter->hw, E1000_RDH(j)), 4501 E1000_READ_REG(&adapter->hw, E1000_RDT(j))); 4502 } 4503 } 4504 4505 /* 4506 * 82574 only: 4507 * Write a new value to the EEPROM increasing the number of MSIX 4508 * vectors from 3 to 5, for proper multiqueue support. 4509 */ 4510 static void 4511 em_enable_vectors_82574(if_ctx_t ctx) 4512 { 4513 struct adapter *adapter = iflib_get_softc(ctx); 4514 struct e1000_hw *hw = &adapter->hw; 4515 device_t dev = iflib_get_dev(ctx); 4516 u16 edata; 4517 4518 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4519 printf("Current cap: %#06x\n", edata); 4520 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 4521 device_printf(dev, "Writing to eeprom: increasing " 4522 "reported MSIX vectors from 3 to 5...\n"); 4523 edata &= ~(EM_NVM_MSIX_N_MASK); 4524 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 4525 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4526 e1000_update_nvm_checksum(hw); 4527 device_printf(dev, "Writing to eeprom: done\n"); 4528 } 4529 } 4530