1 /*- 2 * Copyright (c) 2015 Semihalf 3 * Copyright (c) 2015 Stormshield 4 * Copyright (c) 2018-2019, Rubicon Communications, LLC (Netgate) 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/errno.h> 35 #include <sys/kernel.h> 36 #include <sys/kthread.h> 37 #include <sys/module.h> 38 #include <sys/taskqueue.h> 39 #include <sys/socket.h> 40 #include <sys/sockio.h> 41 42 #include <net/if.h> 43 #include <net/if_media.h> 44 #include <net/if_types.h> 45 46 #include <dev/etherswitch/etherswitch.h> 47 #include <dev/mii/mii.h> 48 #include <dev/mii/miivar.h> 49 50 #include <dev/ofw/ofw_bus.h> 51 #include <dev/ofw/ofw_bus_subr.h> 52 53 #include "e6000swreg.h" 54 #include "etherswitch_if.h" 55 #include "miibus_if.h" 56 #include "mdio_if.h" 57 58 MALLOC_DECLARE(M_E6000SW); 59 MALLOC_DEFINE(M_E6000SW, "e6000sw", "e6000sw switch"); 60 61 #define E6000SW_LOCK(_sc) sx_xlock(&(_sc)->sx) 62 #define E6000SW_UNLOCK(_sc) sx_unlock(&(_sc)->sx) 63 #define E6000SW_LOCK_ASSERT(_sc, _what) sx_assert(&(_sc)->sx, (_what)) 64 #define E6000SW_TRYLOCK(_sc) sx_tryxlock(&(_sc)->sx) 65 #define E6000SW_WAITREADY(_sc, _reg, _bit) \ 66 e6000sw_waitready((_sc), REG_GLOBAL, (_reg), (_bit)) 67 #define E6000SW_WAITREADY2(_sc, _reg, _bit) \ 68 e6000sw_waitready((_sc), REG_GLOBAL2, (_reg), (_bit)) 69 #define MDIO_READ(dev, addr, reg) \ 70 MDIO_READREG(device_get_parent(dev), (addr), (reg)) 71 #define MDIO_WRITE(dev, addr, reg, val) \ 72 MDIO_WRITEREG(device_get_parent(dev), (addr), (reg), (val)) 73 74 75 typedef struct e6000sw_softc { 76 device_t dev; 77 phandle_t node; 78 79 struct sx sx; 80 struct ifnet *ifp[E6000SW_MAX_PORTS]; 81 char *ifname[E6000SW_MAX_PORTS]; 82 device_t miibus[E6000SW_MAX_PORTS]; 83 struct taskqueue *sc_tq; 84 struct timeout_task sc_tt; 85 86 int vlans[E6000SW_NUM_VLANS]; 87 uint32_t swid; 88 uint32_t vlan_mode; 89 uint32_t cpuports_mask; 90 uint32_t fixed_mask; 91 uint32_t fixed25_mask; 92 uint32_t ports_mask; 93 int phy_base; 94 int sw_addr; 95 int num_ports; 96 } e6000sw_softc_t; 97 98 static etherswitch_info_t etherswitch_info = { 99 .es_nports = 0, 100 .es_nvlangroups = 0, 101 .es_vlan_caps = ETHERSWITCH_VLAN_PORT | ETHERSWITCH_VLAN_DOT1Q, 102 .es_name = "Marvell 6000 series switch" 103 }; 104 105 static void e6000sw_identify(driver_t *, device_t); 106 static int e6000sw_probe(device_t); 107 static int e6000sw_parse_fixed_link(e6000sw_softc_t *, phandle_t, uint32_t); 108 static int e6000sw_parse_ethernet(e6000sw_softc_t *, phandle_t, uint32_t); 109 static int e6000sw_attach(device_t); 110 static int e6000sw_detach(device_t); 111 static int e6000sw_read_xmdio(device_t, int, int, int); 112 static int e6000sw_write_xmdio(device_t, int, int, int, int); 113 static int e6000sw_readphy(device_t, int, int); 114 static int e6000sw_writephy(device_t, int, int, int); 115 static int e6000sw_readphy_locked(device_t, int, int); 116 static int e6000sw_writephy_locked(device_t, int, int, int); 117 static etherswitch_info_t* e6000sw_getinfo(device_t); 118 static int e6000sw_getconf(device_t, etherswitch_conf_t *); 119 static int e6000sw_setconf(device_t, etherswitch_conf_t *); 120 static void e6000sw_lock(device_t); 121 static void e6000sw_unlock(device_t); 122 static int e6000sw_getport(device_t, etherswitch_port_t *); 123 static int e6000sw_setport(device_t, etherswitch_port_t *); 124 static int e6000sw_set_vlan_mode(e6000sw_softc_t *, uint32_t); 125 static int e6000sw_readreg_wrapper(device_t, int); 126 static int e6000sw_writereg_wrapper(device_t, int, int); 127 static int e6000sw_getvgroup_wrapper(device_t, etherswitch_vlangroup_t *); 128 static int e6000sw_setvgroup_wrapper(device_t, etherswitch_vlangroup_t *); 129 static int e6000sw_setvgroup(device_t, etherswitch_vlangroup_t *); 130 static int e6000sw_getvgroup(device_t, etherswitch_vlangroup_t *); 131 static void e6000sw_setup(device_t, e6000sw_softc_t *); 132 static void e6000sw_tick(void *, int); 133 static void e6000sw_set_atustat(device_t, e6000sw_softc_t *, int, int); 134 static int e6000sw_atu_flush(device_t, e6000sw_softc_t *, int); 135 static int e6000sw_vtu_flush(e6000sw_softc_t *); 136 static int e6000sw_vtu_update(e6000sw_softc_t *, int, int, int, int, int); 137 static __inline void e6000sw_writereg(e6000sw_softc_t *, int, int, int); 138 static __inline uint32_t e6000sw_readreg(e6000sw_softc_t *, int, int); 139 static int e6000sw_ifmedia_upd(struct ifnet *); 140 static void e6000sw_ifmedia_sts(struct ifnet *, struct ifmediareq *); 141 static int e6000sw_atu_mac_table(device_t, e6000sw_softc_t *, struct atu_opt *, 142 int); 143 static int e6000sw_get_pvid(e6000sw_softc_t *, int, int *); 144 static void e6000sw_set_pvid(e6000sw_softc_t *, int, int); 145 static __inline bool e6000sw_is_cpuport(e6000sw_softc_t *, int); 146 static __inline bool e6000sw_is_fixedport(e6000sw_softc_t *, int); 147 static __inline bool e6000sw_is_fixed25port(e6000sw_softc_t *, int); 148 static __inline bool e6000sw_is_phyport(e6000sw_softc_t *, int); 149 static __inline bool e6000sw_is_portenabled(e6000sw_softc_t *, int); 150 static __inline struct mii_data *e6000sw_miiforphy(e6000sw_softc_t *, 151 unsigned int); 152 153 static device_method_t e6000sw_methods[] = { 154 /* device interface */ 155 DEVMETHOD(device_identify, e6000sw_identify), 156 DEVMETHOD(device_probe, e6000sw_probe), 157 DEVMETHOD(device_attach, e6000sw_attach), 158 DEVMETHOD(device_detach, e6000sw_detach), 159 160 /* bus interface */ 161 DEVMETHOD(bus_add_child, device_add_child_ordered), 162 163 /* mii interface */ 164 DEVMETHOD(miibus_readreg, e6000sw_readphy_locked), 165 DEVMETHOD(miibus_writereg, e6000sw_writephy_locked), 166 167 /* etherswitch interface */ 168 DEVMETHOD(etherswitch_getinfo, e6000sw_getinfo), 169 DEVMETHOD(etherswitch_getconf, e6000sw_getconf), 170 DEVMETHOD(etherswitch_setconf, e6000sw_setconf), 171 DEVMETHOD(etherswitch_lock, e6000sw_lock), 172 DEVMETHOD(etherswitch_unlock, e6000sw_unlock), 173 DEVMETHOD(etherswitch_getport, e6000sw_getport), 174 DEVMETHOD(etherswitch_setport, e6000sw_setport), 175 DEVMETHOD(etherswitch_readreg, e6000sw_readreg_wrapper), 176 DEVMETHOD(etherswitch_writereg, e6000sw_writereg_wrapper), 177 DEVMETHOD(etherswitch_readphyreg, e6000sw_readphy), 178 DEVMETHOD(etherswitch_writephyreg, e6000sw_writephy), 179 DEVMETHOD(etherswitch_setvgroup, e6000sw_setvgroup_wrapper), 180 DEVMETHOD(etherswitch_getvgroup, e6000sw_getvgroup_wrapper), 181 182 DEVMETHOD_END 183 }; 184 185 DEFINE_CLASS_0(e6000sw, e6000sw_driver, e6000sw_methods, 186 sizeof(e6000sw_softc_t)); 187 188 DRIVER_MODULE(e6000sw, mdio, e6000sw_driver, 0, 0); 189 DRIVER_MODULE(etherswitch, e6000sw, etherswitch_driver, 0, 0); 190 DRIVER_MODULE(miibus, e6000sw, miibus_driver, 0, 0); 191 MODULE_DEPEND(e6000sw, mdio, 1, 1, 1); 192 193 194 static void 195 e6000sw_identify(driver_t *driver, device_t parent) 196 { 197 198 if (device_find_child(parent, "e6000sw", -1) == NULL) 199 BUS_ADD_CHILD(parent, 0, "e6000sw", -1); 200 } 201 202 static int 203 e6000sw_probe(device_t dev) 204 { 205 e6000sw_softc_t *sc; 206 const char *description; 207 phandle_t switch_node; 208 209 sc = device_get_softc(dev); 210 switch_node = ofw_bus_find_compatible(OF_finddevice("/"), 211 "marvell,mv88e6085"); 212 if (switch_node == 0) { 213 switch_node = ofw_bus_find_compatible(OF_finddevice("/"), 214 "marvell,mv88e6190"); 215 216 if (switch_node == 0) 217 return (ENXIO); 218 219 /* 220 * Trust DTS and fix the port register offset for the MV88E6190 221 * detection bellow. 222 */ 223 sc->swid = MV88E6190; 224 } 225 226 if (bootverbose) 227 device_printf(dev, "Found switch_node: 0x%x\n", switch_node); 228 229 sc->dev = dev; 230 sc->node = switch_node; 231 232 if (OF_getencprop(sc->node, "reg", &sc->sw_addr, 233 sizeof(sc->sw_addr)) < 0) 234 return (ENXIO); 235 if (sc->sw_addr < 0 || sc->sw_addr > 32) 236 return (ENXIO); 237 238 /* 239 * Create temporary lock, just to satisfy assertions, 240 * when obtaining the switch ID. Destroy immediately afterwards. 241 */ 242 sx_init(&sc->sx, "e6000sw_tmp"); 243 E6000SW_LOCK(sc); 244 sc->swid = e6000sw_readreg(sc, REG_PORT(sc, 0), SWITCH_ID) & 0xfff0; 245 E6000SW_UNLOCK(sc); 246 sx_destroy(&sc->sx); 247 248 switch (sc->swid) { 249 case MV88E6141: 250 description = "Marvell 88E6141"; 251 sc->phy_base = 0x10; 252 sc->num_ports = 6; 253 break; 254 case MV88E6341: 255 description = "Marvell 88E6341"; 256 sc->phy_base = 0x10; 257 sc->num_ports = 6; 258 break; 259 case MV88E6352: 260 description = "Marvell 88E6352"; 261 sc->num_ports = 7; 262 break; 263 case MV88E6172: 264 description = "Marvell 88E6172"; 265 sc->num_ports = 7; 266 break; 267 case MV88E6176: 268 description = "Marvell 88E6176"; 269 sc->num_ports = 7; 270 break; 271 case MV88E6190: 272 description = "Marvell 88E6190"; 273 sc->num_ports = 11; 274 break; 275 default: 276 device_printf(dev, "Unrecognized device, id 0x%x.\n", sc->swid); 277 return (ENXIO); 278 } 279 280 device_set_desc(dev, description); 281 282 return (BUS_PROBE_DEFAULT); 283 } 284 285 static int 286 e6000sw_parse_fixed_link(e6000sw_softc_t *sc, phandle_t node, uint32_t port) 287 { 288 int speed; 289 phandle_t fixed_link; 290 291 fixed_link = ofw_bus_find_child(node, "fixed-link"); 292 293 if (fixed_link != 0) { 294 sc->fixed_mask |= (1 << port); 295 296 if (OF_getencprop(fixed_link, 297 "speed", &speed, sizeof(speed)) < 0) { 298 device_printf(sc->dev, 299 "Port %d has a fixed-link node without a speed " 300 "property\n", port); 301 return (ENXIO); 302 } 303 if (speed == 2500 && (MVSWITCH(sc, MV88E6141) || 304 MVSWITCH(sc, MV88E6341) || MVSWITCH(sc, MV88E6190))) 305 sc->fixed25_mask |= (1 << port); 306 } 307 308 return (0); 309 } 310 311 static int 312 e6000sw_parse_ethernet(e6000sw_softc_t *sc, phandle_t port_handle, uint32_t port) { 313 phandle_t switch_eth, switch_eth_handle; 314 315 if (OF_getencprop(port_handle, "ethernet", (void*)&switch_eth_handle, 316 sizeof(switch_eth_handle)) > 0) { 317 if (switch_eth_handle > 0) { 318 switch_eth = OF_node_from_xref(switch_eth_handle); 319 320 device_printf(sc->dev, "CPU port at %d\n", port); 321 sc->cpuports_mask |= (1 << port); 322 323 return (e6000sw_parse_fixed_link(sc, switch_eth, port)); 324 } else 325 device_printf(sc->dev, 326 "Port %d has ethernet property but it points " 327 "to an invalid location\n", port); 328 } 329 330 return (0); 331 } 332 333 static int 334 e6000sw_parse_child_fdt(e6000sw_softc_t *sc, phandle_t child, int *pport) 335 { 336 uint32_t port; 337 338 if (pport == NULL) 339 return (ENXIO); 340 341 if (OF_getencprop(child, "reg", (void *)&port, sizeof(port)) < 0) 342 return (ENXIO); 343 if (port >= sc->num_ports) 344 return (ENXIO); 345 *pport = port; 346 347 if (e6000sw_parse_fixed_link(sc, child, port) != 0) 348 return (ENXIO); 349 350 if (e6000sw_parse_ethernet(sc, child, port) != 0) 351 return (ENXIO); 352 353 if ((sc->fixed_mask & (1 << port)) != 0) 354 device_printf(sc->dev, "fixed port at %d\n", port); 355 else 356 device_printf(sc->dev, "PHY at port %d\n", port); 357 358 return (0); 359 } 360 361 static int 362 e6000sw_init_interface(e6000sw_softc_t *sc, int port) 363 { 364 char name[IFNAMSIZ]; 365 366 snprintf(name, IFNAMSIZ, "%sport", device_get_nameunit(sc->dev)); 367 368 sc->ifp[port] = if_alloc(IFT_ETHER); 369 if (sc->ifp[port] == NULL) 370 return (ENOMEM); 371 sc->ifp[port]->if_softc = sc; 372 sc->ifp[port]->if_flags |= IFF_UP | IFF_BROADCAST | 373 IFF_DRV_RUNNING | IFF_SIMPLEX; 374 sc->ifname[port] = malloc(strlen(name) + 1, M_E6000SW, M_NOWAIT); 375 if (sc->ifname[port] == NULL) { 376 if_free(sc->ifp[port]); 377 return (ENOMEM); 378 } 379 memcpy(sc->ifname[port], name, strlen(name) + 1); 380 if_initname(sc->ifp[port], sc->ifname[port], port); 381 382 return (0); 383 } 384 385 static int 386 e6000sw_attach_miibus(e6000sw_softc_t *sc, int port) 387 { 388 int err; 389 390 err = mii_attach(sc->dev, &sc->miibus[port], sc->ifp[port], 391 e6000sw_ifmedia_upd, e6000sw_ifmedia_sts, BMSR_DEFCAPMASK, 392 port + sc->phy_base, MII_OFFSET_ANY, 0); 393 if (err != 0) 394 return (err); 395 396 return (0); 397 } 398 399 static void 400 e6000sw_serdes_power(device_t dev, int port, bool sgmii) 401 { 402 uint32_t reg; 403 404 /* SGMII */ 405 reg = e6000sw_read_xmdio(dev, port, E6000SW_SERDES_DEV, 406 E6000SW_SERDES_SGMII_CTL); 407 if (sgmii) 408 reg &= ~E6000SW_SERDES_PDOWN; 409 else 410 reg |= E6000SW_SERDES_PDOWN; 411 e6000sw_write_xmdio(dev, port, E6000SW_SERDES_DEV, 412 E6000SW_SERDES_SGMII_CTL, reg); 413 414 /* 10GBASE-R/10GBASE-X4/X2 */ 415 reg = e6000sw_read_xmdio(dev, port, E6000SW_SERDES_DEV, 416 E6000SW_SERDES_PCS_CTL1); 417 if (sgmii) 418 reg |= E6000SW_SERDES_PDOWN; 419 else 420 reg &= ~E6000SW_SERDES_PDOWN; 421 e6000sw_write_xmdio(dev, port, E6000SW_SERDES_DEV, 422 E6000SW_SERDES_PCS_CTL1, reg); 423 } 424 425 static int 426 e6000sw_attach(device_t dev) 427 { 428 bool sgmii; 429 e6000sw_softc_t *sc; 430 phandle_t child, ports; 431 int err, port; 432 uint32_t reg; 433 434 err = 0; 435 sc = device_get_softc(dev); 436 437 /* 438 * According to the Linux source code, all of the Switch IDs we support 439 * are multi_chip capable, and should go into multi-chip mode if the 440 * sw_addr != 0. 441 */ 442 if (MVSWITCH_MULTICHIP(sc)) 443 device_printf(dev, "multi-chip addressing mode (%#x)\n", 444 sc->sw_addr); 445 else 446 device_printf(dev, "single-chip addressing mode\n"); 447 448 sx_init(&sc->sx, "e6000sw"); 449 450 E6000SW_LOCK(sc); 451 e6000sw_setup(dev, sc); 452 ports = ofw_bus_find_child(sc->node, "ports"); 453 sc->sc_tq = taskqueue_create("e6000sw_taskq", M_NOWAIT, 454 taskqueue_thread_enqueue, &sc->sc_tq); 455 456 TIMEOUT_TASK_INIT(sc->sc_tq, &sc->sc_tt, 0, e6000sw_tick, sc); 457 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq", 458 device_get_nameunit(dev)); 459 460 if (ports == 0) { 461 device_printf(dev, "failed to parse DTS: no ports found for " 462 "switch\n"); 463 E6000SW_UNLOCK(sc); 464 return (ENXIO); 465 } 466 467 for (child = OF_child(ports); child != 0; child = OF_peer(child)) { 468 err = e6000sw_parse_child_fdt(sc, child, &port); 469 if (err != 0) { 470 device_printf(sc->dev, "failed to parse DTS\n"); 471 goto out_fail; 472 } 473 474 /* Port is in use. */ 475 sc->ports_mask |= (1 << port); 476 477 err = e6000sw_init_interface(sc, port); 478 if (err != 0) { 479 device_printf(sc->dev, "failed to init interface\n"); 480 goto out_fail; 481 } 482 483 if (e6000sw_is_fixedport(sc, port)) { 484 /* Link must be down to change speed force value. */ 485 reg = e6000sw_readreg(sc, REG_PORT(sc, port), 486 PSC_CONTROL); 487 reg &= ~PSC_CONTROL_LINK_UP; 488 reg |= PSC_CONTROL_FORCED_LINK; 489 e6000sw_writereg(sc, REG_PORT(sc, port), PSC_CONTROL, 490 reg); 491 492 /* 493 * Force speed, full-duplex, EEE off and flow-control 494 * on. 495 */ 496 reg &= ~(PSC_CONTROL_SPD2500 | PSC_CONTROL_ALT_SPD | 497 PSC_CONTROL_FORCED_FC | PSC_CONTROL_FC_ON | 498 PSC_CONTROL_FORCED_EEE); 499 if (e6000sw_is_fixed25port(sc, port)) 500 reg |= PSC_CONTROL_SPD2500; 501 else 502 reg |= PSC_CONTROL_SPD1000; 503 if (MVSWITCH(sc, MV88E6190) && 504 e6000sw_is_fixed25port(sc, port)) 505 reg |= PSC_CONTROL_ALT_SPD; 506 reg |= PSC_CONTROL_FORCED_DPX | PSC_CONTROL_FULLDPX | 507 PSC_CONTROL_FORCED_LINK | PSC_CONTROL_LINK_UP | 508 PSC_CONTROL_FORCED_SPD; 509 if (!MVSWITCH(sc, MV88E6190)) 510 reg |= PSC_CONTROL_FORCED_FC | PSC_CONTROL_FC_ON; 511 if (MVSWITCH(sc, MV88E6141) || 512 MVSWITCH(sc, MV88E6341) || 513 MVSWITCH(sc, MV88E6190)) 514 reg |= PSC_CONTROL_FORCED_EEE; 515 e6000sw_writereg(sc, REG_PORT(sc, port), PSC_CONTROL, 516 reg); 517 /* Power on the SERDES interfaces. */ 518 if (MVSWITCH(sc, MV88E6190) && 519 (port == 9 || port == 10)) { 520 if (e6000sw_is_fixed25port(sc, port)) 521 sgmii = false; 522 else 523 sgmii = true; 524 e6000sw_serdes_power(sc->dev, port, sgmii); 525 } 526 } 527 528 /* Don't attach miibus at CPU/fixed ports */ 529 if (!e6000sw_is_phyport(sc, port)) 530 continue; 531 532 err = e6000sw_attach_miibus(sc, port); 533 if (err != 0) { 534 device_printf(sc->dev, "failed to attach miibus\n"); 535 goto out_fail; 536 } 537 } 538 539 etherswitch_info.es_nports = sc->num_ports; 540 541 /* Default to port vlan. */ 542 e6000sw_set_vlan_mode(sc, ETHERSWITCH_VLAN_PORT); 543 544 reg = e6000sw_readreg(sc, REG_GLOBAL, SWITCH_GLOBAL_STATUS); 545 if (reg & SWITCH_GLOBAL_STATUS_IR) 546 device_printf(dev, "switch is ready.\n"); 547 E6000SW_UNLOCK(sc); 548 549 bus_generic_probe(dev); 550 bus_generic_attach(dev); 551 552 taskqueue_enqueue_timeout(sc->sc_tq, &sc->sc_tt, hz); 553 554 return (0); 555 556 out_fail: 557 e6000sw_detach(dev); 558 559 return (err); 560 } 561 562 static int 563 e6000sw_waitready(e6000sw_softc_t *sc, uint32_t phy, uint32_t reg, 564 uint32_t busybit) 565 { 566 int i; 567 568 for (i = 0; i < E6000SW_RETRIES; i++) { 569 if ((e6000sw_readreg(sc, phy, reg) & busybit) == 0) 570 return (0); 571 DELAY(1); 572 } 573 574 return (1); 575 } 576 577 /* XMDIO/Clause 45 access. */ 578 static int 579 e6000sw_read_xmdio(device_t dev, int phy, int devaddr, int devreg) 580 { 581 e6000sw_softc_t *sc; 582 uint32_t reg; 583 584 sc = device_get_softc(dev); 585 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 586 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 587 device_printf(dev, "Timeout while waiting for switch\n"); 588 return (ETIMEDOUT); 589 } 590 591 reg = devaddr & SMI_CMD_REG_ADDR_MASK; 592 reg |= (phy << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK; 593 594 /* Load C45 register address. */ 595 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG, devreg); 596 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG, 597 reg | SMI_CMD_OP_C45_ADDR); 598 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 599 device_printf(dev, "Timeout while waiting for switch\n"); 600 return (ETIMEDOUT); 601 } 602 603 /* Start C45 read operation. */ 604 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG, 605 reg | SMI_CMD_OP_C45_READ); 606 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 607 device_printf(dev, "Timeout while waiting for switch\n"); 608 return (ETIMEDOUT); 609 } 610 611 /* Read C45 data. */ 612 reg = e6000sw_readreg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG); 613 614 return (reg & PHY_DATA_MASK); 615 } 616 617 static int 618 e6000sw_write_xmdio(device_t dev, int phy, int devaddr, int devreg, int val) 619 { 620 e6000sw_softc_t *sc; 621 uint32_t reg; 622 623 sc = device_get_softc(dev); 624 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 625 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 626 device_printf(dev, "Timeout while waiting for switch\n"); 627 return (ETIMEDOUT); 628 } 629 630 reg = devaddr & SMI_CMD_REG_ADDR_MASK; 631 reg |= (phy << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK; 632 633 /* Load C45 register address. */ 634 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG, devreg); 635 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG, 636 reg | SMI_CMD_OP_C45_ADDR); 637 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 638 device_printf(dev, "Timeout while waiting for switch\n"); 639 return (ETIMEDOUT); 640 } 641 642 /* Load data and start the C45 write operation. */ 643 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG, devreg); 644 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG, 645 reg | SMI_CMD_OP_C45_WRITE); 646 647 return (0); 648 } 649 650 static int e6000sw_readphy(device_t dev, int phy, int reg) 651 { 652 e6000sw_softc_t *sc; 653 int ret; 654 655 sc = device_get_softc(dev); 656 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 657 658 E6000SW_LOCK(sc); 659 ret = e6000sw_readphy_locked(dev, phy, reg); 660 E6000SW_UNLOCK(sc); 661 662 return (ret); 663 } 664 665 /* 666 * PHY registers are paged. Put page index in reg 22 (accessible from every 667 * page), then access specific register. 668 */ 669 static int 670 e6000sw_readphy_locked(device_t dev, int phy, int reg) 671 { 672 e6000sw_softc_t *sc; 673 uint32_t val; 674 675 sc = device_get_softc(dev); 676 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 677 678 if (!e6000sw_is_phyport(sc, phy) || reg >= E6000SW_NUM_PHY_REGS) { 679 device_printf(dev, "Wrong register address.\n"); 680 return (EINVAL); 681 } 682 683 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 684 device_printf(dev, "Timeout while waiting for switch\n"); 685 return (ETIMEDOUT); 686 } 687 688 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG, 689 SMI_CMD_OP_C22_READ | (reg & SMI_CMD_REG_ADDR_MASK) | 690 ((phy << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK)); 691 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 692 device_printf(dev, "Timeout while waiting for switch\n"); 693 return (ETIMEDOUT); 694 } 695 696 val = e6000sw_readreg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG); 697 698 return (val & PHY_DATA_MASK); 699 } 700 701 static int e6000sw_writephy(device_t dev, int phy, int reg, int data) 702 { 703 e6000sw_softc_t *sc; 704 int ret; 705 706 sc = device_get_softc(dev); 707 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 708 709 E6000SW_LOCK(sc); 710 ret = e6000sw_writephy_locked(dev, phy, reg, data); 711 E6000SW_UNLOCK(sc); 712 713 return (ret); 714 } 715 716 static int 717 e6000sw_writephy_locked(device_t dev, int phy, int reg, int data) 718 { 719 e6000sw_softc_t *sc; 720 721 sc = device_get_softc(dev); 722 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 723 724 if (!e6000sw_is_phyport(sc, phy) || reg >= E6000SW_NUM_PHY_REGS) { 725 device_printf(dev, "Wrong register address.\n"); 726 return (EINVAL); 727 } 728 729 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 730 device_printf(dev, "Timeout while waiting for switch\n"); 731 return (ETIMEDOUT); 732 } 733 734 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG, 735 data & PHY_DATA_MASK); 736 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG, 737 SMI_CMD_OP_C22_WRITE | (reg & SMI_CMD_REG_ADDR_MASK) | 738 ((phy << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK)); 739 740 return (0); 741 } 742 743 static int 744 e6000sw_detach(device_t dev) 745 { 746 int phy; 747 e6000sw_softc_t *sc; 748 749 sc = device_get_softc(dev); 750 751 if (device_is_attached(dev)) 752 taskqueue_drain_timeout(sc->sc_tq, &sc->sc_tt); 753 754 if (sc->sc_tq != NULL) 755 taskqueue_free(sc->sc_tq); 756 757 device_delete_children(dev); 758 759 sx_destroy(&sc->sx); 760 for (phy = 0; phy < sc->num_ports; phy++) { 761 if (sc->ifp[phy] != NULL) 762 if_free(sc->ifp[phy]); 763 if (sc->ifname[phy] != NULL) 764 free(sc->ifname[phy], M_E6000SW); 765 } 766 767 return (0); 768 } 769 770 static etherswitch_info_t* 771 e6000sw_getinfo(device_t dev) 772 { 773 774 return (ðerswitch_info); 775 } 776 777 static int 778 e6000sw_getconf(device_t dev, etherswitch_conf_t *conf) 779 { 780 struct e6000sw_softc *sc; 781 782 /* Return the VLAN mode. */ 783 sc = device_get_softc(dev); 784 conf->cmd = ETHERSWITCH_CONF_VLAN_MODE; 785 conf->vlan_mode = sc->vlan_mode; 786 787 return (0); 788 } 789 790 static int 791 e6000sw_setconf(device_t dev, etherswitch_conf_t *conf) 792 { 793 struct e6000sw_softc *sc; 794 795 /* Set the VLAN mode. */ 796 sc = device_get_softc(dev); 797 if (conf->cmd & ETHERSWITCH_CONF_VLAN_MODE) { 798 E6000SW_LOCK(sc); 799 e6000sw_set_vlan_mode(sc, conf->vlan_mode); 800 E6000SW_UNLOCK(sc); 801 } 802 803 return (0); 804 } 805 806 static void 807 e6000sw_lock(device_t dev) 808 { 809 struct e6000sw_softc *sc; 810 811 sc = device_get_softc(dev); 812 813 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 814 E6000SW_LOCK(sc); 815 } 816 817 static void 818 e6000sw_unlock(device_t dev) 819 { 820 struct e6000sw_softc *sc; 821 822 sc = device_get_softc(dev); 823 824 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 825 E6000SW_UNLOCK(sc); 826 } 827 828 static int 829 e6000sw_getport(device_t dev, etherswitch_port_t *p) 830 { 831 struct mii_data *mii; 832 int err; 833 struct ifmediareq *ifmr; 834 uint32_t reg; 835 836 e6000sw_softc_t *sc = device_get_softc(dev); 837 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 838 839 if (p->es_port >= sc->num_ports || p->es_port < 0) 840 return (EINVAL); 841 if (!e6000sw_is_portenabled(sc, p->es_port)) 842 return (0); 843 844 E6000SW_LOCK(sc); 845 e6000sw_get_pvid(sc, p->es_port, &p->es_pvid); 846 847 /* Port flags. */ 848 reg = e6000sw_readreg(sc, REG_PORT(sc, p->es_port), PORT_CONTROL2); 849 if (reg & PORT_CONTROL2_DISC_TAGGED) 850 p->es_flags |= ETHERSWITCH_PORT_DROPTAGGED; 851 if (reg & PORT_CONTROL2_DISC_UNTAGGED) 852 p->es_flags |= ETHERSWITCH_PORT_DROPUNTAGGED; 853 854 err = 0; 855 if (e6000sw_is_fixedport(sc, p->es_port)) { 856 if (e6000sw_is_cpuport(sc, p->es_port)) 857 p->es_flags |= ETHERSWITCH_PORT_CPU; 858 ifmr = &p->es_ifmr; 859 ifmr->ifm_status = IFM_ACTIVE | IFM_AVALID; 860 ifmr->ifm_count = 0; 861 if (e6000sw_is_fixed25port(sc, p->es_port)) 862 ifmr->ifm_active = IFM_2500_T; 863 else 864 ifmr->ifm_active = IFM_1000_T; 865 ifmr->ifm_active |= IFM_ETHER | IFM_FDX; 866 ifmr->ifm_current = ifmr->ifm_active; 867 ifmr->ifm_mask = 0; 868 } else { 869 mii = e6000sw_miiforphy(sc, p->es_port); 870 err = ifmedia_ioctl(mii->mii_ifp, &p->es_ifr, 871 &mii->mii_media, SIOCGIFMEDIA); 872 } 873 E6000SW_UNLOCK(sc); 874 875 return (err); 876 } 877 878 static int 879 e6000sw_setport(device_t dev, etherswitch_port_t *p) 880 { 881 e6000sw_softc_t *sc; 882 int err; 883 struct mii_data *mii; 884 uint32_t reg; 885 886 sc = device_get_softc(dev); 887 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 888 889 if (p->es_port >= sc->num_ports || p->es_port < 0) 890 return (EINVAL); 891 if (!e6000sw_is_portenabled(sc, p->es_port)) 892 return (0); 893 894 E6000SW_LOCK(sc); 895 896 /* Port flags. */ 897 reg = e6000sw_readreg(sc, REG_PORT(sc, p->es_port), PORT_CONTROL2); 898 if (p->es_flags & ETHERSWITCH_PORT_DROPTAGGED) 899 reg |= PORT_CONTROL2_DISC_TAGGED; 900 else 901 reg &= ~PORT_CONTROL2_DISC_TAGGED; 902 if (p->es_flags & ETHERSWITCH_PORT_DROPUNTAGGED) 903 reg |= PORT_CONTROL2_DISC_UNTAGGED; 904 else 905 reg &= ~PORT_CONTROL2_DISC_UNTAGGED; 906 e6000sw_writereg(sc, REG_PORT(sc, p->es_port), PORT_CONTROL2, reg); 907 908 err = 0; 909 if (p->es_pvid != 0) 910 e6000sw_set_pvid(sc, p->es_port, p->es_pvid); 911 if (e6000sw_is_phyport(sc, p->es_port)) { 912 mii = e6000sw_miiforphy(sc, p->es_port); 913 err = ifmedia_ioctl(mii->mii_ifp, &p->es_ifr, &mii->mii_media, 914 SIOCSIFMEDIA); 915 } 916 E6000SW_UNLOCK(sc); 917 918 return (err); 919 } 920 921 static __inline void 922 e6000sw_port_vlan_assign(e6000sw_softc_t *sc, int port, uint32_t fid, 923 uint32_t members) 924 { 925 uint32_t reg; 926 927 reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VLAN_MAP); 928 reg &= ~(PORT_MASK(sc) | PORT_VLAN_MAP_FID_MASK); 929 reg |= members & PORT_MASK(sc) & ~(1 << port); 930 reg |= (fid << PORT_VLAN_MAP_FID) & PORT_VLAN_MAP_FID_MASK; 931 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_VLAN_MAP, reg); 932 reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL1); 933 reg &= ~PORT_CONTROL1_FID_MASK; 934 reg |= (fid >> 4) & PORT_CONTROL1_FID_MASK; 935 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_CONTROL1, reg); 936 } 937 938 static int 939 e6000sw_init_vlan(struct e6000sw_softc *sc) 940 { 941 int i, port, ret; 942 uint32_t members; 943 944 /* Disable all ports */ 945 for (port = 0; port < sc->num_ports; port++) { 946 ret = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL); 947 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_CONTROL, 948 (ret & ~PORT_CONTROL_ENABLE)); 949 } 950 951 /* Flush VTU. */ 952 e6000sw_vtu_flush(sc); 953 954 for (port = 0; port < sc->num_ports; port++) { 955 /* Reset the egress and frame mode. */ 956 ret = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL); 957 ret &= ~(PORT_CONTROL_EGRESS | PORT_CONTROL_FRAME); 958 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_CONTROL, ret); 959 960 /* Set the 802.1q mode. */ 961 ret = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL2); 962 ret &= ~PORT_CONTROL2_DOT1Q; 963 if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) 964 ret |= PORT_CONTROL2_DOT1Q; 965 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_CONTROL2, ret); 966 } 967 968 for (port = 0; port < sc->num_ports; port++) { 969 if (!e6000sw_is_portenabled(sc, port)) 970 continue; 971 972 ret = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VID); 973 974 /* Set port priority */ 975 ret &= ~PORT_VID_PRIORITY_MASK; 976 977 /* Set VID map */ 978 ret &= ~PORT_VID_DEF_VID_MASK; 979 if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) 980 ret |= 1; 981 else 982 ret |= (port + 1); 983 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_VID, ret); 984 } 985 986 /* Assign the member ports to each origin port. */ 987 for (port = 0; port < sc->num_ports; port++) { 988 members = 0; 989 if (e6000sw_is_portenabled(sc, port)) { 990 for (i = 0; i < sc->num_ports; i++) { 991 if (i == port || !e6000sw_is_portenabled(sc, i)) 992 continue; 993 members |= (1 << i); 994 } 995 } 996 /* Default to FID 0. */ 997 e6000sw_port_vlan_assign(sc, port, 0, members); 998 } 999 1000 /* Reset internal VLAN table. */ 1001 for (i = 0; i < nitems(sc->vlans); i++) 1002 sc->vlans[i] = 0; 1003 1004 /* Create default VLAN (1). */ 1005 if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) { 1006 sc->vlans[0] = 1; 1007 e6000sw_vtu_update(sc, 0, sc->vlans[0], 1, 0, sc->ports_mask); 1008 } 1009 1010 /* Enable all ports */ 1011 for (port = 0; port < sc->num_ports; port++) { 1012 if (!e6000sw_is_portenabled(sc, port)) 1013 continue; 1014 ret = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL); 1015 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_CONTROL, 1016 (ret | PORT_CONTROL_ENABLE)); 1017 } 1018 1019 return (0); 1020 } 1021 1022 static int 1023 e6000sw_set_vlan_mode(struct e6000sw_softc *sc, uint32_t mode) 1024 { 1025 1026 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 1027 switch (mode) { 1028 case ETHERSWITCH_VLAN_PORT: 1029 sc->vlan_mode = ETHERSWITCH_VLAN_PORT; 1030 etherswitch_info.es_nvlangroups = sc->num_ports; 1031 return (e6000sw_init_vlan(sc)); 1032 break; 1033 case ETHERSWITCH_VLAN_DOT1Q: 1034 sc->vlan_mode = ETHERSWITCH_VLAN_DOT1Q; 1035 etherswitch_info.es_nvlangroups = E6000SW_NUM_VLANS; 1036 return (e6000sw_init_vlan(sc)); 1037 break; 1038 default: 1039 return (EINVAL); 1040 } 1041 } 1042 1043 /* 1044 * Registers in this switch are divided into sections, specified in 1045 * documentation. So as to access any of them, section index and reg index 1046 * is necessary. etherswitchcfg uses only one variable, so indexes were 1047 * compressed into addr_reg: 32 * section_index + reg_index. 1048 */ 1049 static int 1050 e6000sw_readreg_wrapper(device_t dev, int addr_reg) 1051 { 1052 e6000sw_softc_t *sc; 1053 1054 sc = device_get_softc(dev); 1055 if ((addr_reg > (REG_GLOBAL2 * 32 + REG_NUM_MAX)) || 1056 (addr_reg < (REG_PORT(sc, 0) * 32))) { 1057 device_printf(dev, "Wrong register address.\n"); 1058 return (EINVAL); 1059 } 1060 1061 return (e6000sw_readreg(device_get_softc(dev), addr_reg / 32, 1062 addr_reg % 32)); 1063 } 1064 1065 static int 1066 e6000sw_writereg_wrapper(device_t dev, int addr_reg, int val) 1067 { 1068 e6000sw_softc_t *sc; 1069 1070 sc = device_get_softc(dev); 1071 if ((addr_reg > (REG_GLOBAL2 * 32 + REG_NUM_MAX)) || 1072 (addr_reg < (REG_PORT(sc, 0) * 32))) { 1073 device_printf(dev, "Wrong register address.\n"); 1074 return (EINVAL); 1075 } 1076 e6000sw_writereg(device_get_softc(dev), addr_reg / 32, 1077 addr_reg % 32, val); 1078 1079 return (0); 1080 } 1081 1082 /* 1083 * setvgroup/getvgroup called from etherswitchfcg need to be locked, 1084 * while internal calls do not. 1085 */ 1086 static int 1087 e6000sw_setvgroup_wrapper(device_t dev, etherswitch_vlangroup_t *vg) 1088 { 1089 e6000sw_softc_t *sc; 1090 int ret; 1091 1092 sc = device_get_softc(dev); 1093 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 1094 1095 E6000SW_LOCK(sc); 1096 ret = e6000sw_setvgroup(dev, vg); 1097 E6000SW_UNLOCK(sc); 1098 1099 return (ret); 1100 } 1101 1102 static int 1103 e6000sw_getvgroup_wrapper(device_t dev, etherswitch_vlangroup_t *vg) 1104 { 1105 e6000sw_softc_t *sc; 1106 int ret; 1107 1108 sc = device_get_softc(dev); 1109 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 1110 1111 E6000SW_LOCK(sc); 1112 ret = e6000sw_getvgroup(dev, vg); 1113 E6000SW_UNLOCK(sc); 1114 1115 return (ret); 1116 } 1117 1118 static int 1119 e6000sw_set_port_vlan(e6000sw_softc_t *sc, etherswitch_vlangroup_t *vg) 1120 { 1121 uint32_t port; 1122 1123 port = vg->es_vlangroup; 1124 if (port > sc->num_ports) 1125 return (EINVAL); 1126 1127 if (vg->es_member_ports != vg->es_untagged_ports) { 1128 device_printf(sc->dev, "Tagged ports not supported.\n"); 1129 return (EINVAL); 1130 } 1131 1132 e6000sw_port_vlan_assign(sc, port, 0, vg->es_untagged_ports); 1133 vg->es_vid = port | ETHERSWITCH_VID_VALID; 1134 1135 return (0); 1136 } 1137 1138 static int 1139 e6000sw_set_dot1q_vlan(e6000sw_softc_t *sc, etherswitch_vlangroup_t *vg) 1140 { 1141 int i, vlan; 1142 1143 vlan = vg->es_vid & ETHERSWITCH_VID_MASK; 1144 1145 /* Set VLAN to '0' removes it from table. */ 1146 if (vlan == 0) { 1147 e6000sw_vtu_update(sc, VTU_PURGE, 1148 sc->vlans[vg->es_vlangroup], 0, 0, 0); 1149 sc->vlans[vg->es_vlangroup] = 0; 1150 return (0); 1151 } 1152 1153 /* Is this VLAN already in table ? */ 1154 for (i = 0; i < etherswitch_info.es_nvlangroups; i++) 1155 if (i != vg->es_vlangroup && vlan == sc->vlans[i]) 1156 return (EINVAL); 1157 1158 sc->vlans[vg->es_vlangroup] = vlan; 1159 e6000sw_vtu_update(sc, 0, vlan, vg->es_vlangroup + 1, 1160 vg->es_member_ports & sc->ports_mask, 1161 vg->es_untagged_ports & sc->ports_mask); 1162 1163 return (0); 1164 } 1165 1166 static int 1167 e6000sw_setvgroup(device_t dev, etherswitch_vlangroup_t *vg) 1168 { 1169 e6000sw_softc_t *sc; 1170 1171 sc = device_get_softc(dev); 1172 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 1173 1174 if (sc->vlan_mode == ETHERSWITCH_VLAN_PORT) 1175 return (e6000sw_set_port_vlan(sc, vg)); 1176 else if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) 1177 return (e6000sw_set_dot1q_vlan(sc, vg)); 1178 1179 return (EINVAL); 1180 } 1181 1182 static int 1183 e6000sw_get_port_vlan(e6000sw_softc_t *sc, etherswitch_vlangroup_t *vg) 1184 { 1185 uint32_t port, reg; 1186 1187 port = vg->es_vlangroup; 1188 if (port > sc->num_ports) 1189 return (EINVAL); 1190 1191 if (!e6000sw_is_portenabled(sc, port)) { 1192 vg->es_vid = port; 1193 return (0); 1194 } 1195 1196 reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VLAN_MAP); 1197 vg->es_untagged_ports = vg->es_member_ports = reg & PORT_MASK(sc); 1198 vg->es_vid = port | ETHERSWITCH_VID_VALID; 1199 vg->es_fid = (reg & PORT_VLAN_MAP_FID_MASK) >> PORT_VLAN_MAP_FID; 1200 reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL1); 1201 vg->es_fid |= (reg & PORT_CONTROL1_FID_MASK) << 4; 1202 1203 return (0); 1204 } 1205 1206 static int 1207 e6000sw_get_dot1q_vlan(e6000sw_softc_t *sc, etherswitch_vlangroup_t *vg) 1208 { 1209 int i, port; 1210 uint32_t reg; 1211 1212 vg->es_fid = 0; 1213 vg->es_vid = sc->vlans[vg->es_vlangroup]; 1214 vg->es_untagged_ports = vg->es_member_ports = 0; 1215 if (vg->es_vid == 0) 1216 return (0); 1217 1218 if (E6000SW_WAITREADY(sc, VTU_OPERATION, VTU_BUSY)) { 1219 device_printf(sc->dev, "VTU unit is busy, cannot access\n"); 1220 return (EBUSY); 1221 } 1222 1223 e6000sw_writereg(sc, REG_GLOBAL, VTU_VID, vg->es_vid - 1); 1224 1225 reg = e6000sw_readreg(sc, REG_GLOBAL, VTU_OPERATION); 1226 reg &= ~VTU_OP_MASK; 1227 reg |= VTU_GET_NEXT | VTU_BUSY; 1228 e6000sw_writereg(sc, REG_GLOBAL, VTU_OPERATION, reg); 1229 if (E6000SW_WAITREADY(sc, VTU_OPERATION, VTU_BUSY)) { 1230 device_printf(sc->dev, "Timeout while reading\n"); 1231 return (EBUSY); 1232 } 1233 1234 reg = e6000sw_readreg(sc, REG_GLOBAL, VTU_VID); 1235 if (reg == VTU_VID_MASK || (reg & VTU_VID_VALID) == 0) 1236 return (EINVAL); 1237 if ((reg & VTU_VID_MASK) != vg->es_vid) 1238 return (EINVAL); 1239 1240 vg->es_vid |= ETHERSWITCH_VID_VALID; 1241 reg = e6000sw_readreg(sc, REG_GLOBAL, VTU_DATA); 1242 for (i = 0; i < sc->num_ports; i++) { 1243 if (i == VTU_PPREG(sc)) 1244 reg = e6000sw_readreg(sc, REG_GLOBAL, VTU_DATA2); 1245 port = (reg >> VTU_PORT(sc, i)) & VTU_PORT_MASK; 1246 if (port == VTU_PORT_UNTAGGED) { 1247 vg->es_untagged_ports |= (1 << i); 1248 vg->es_member_ports |= (1 << i); 1249 } else if (port == VTU_PORT_TAGGED) 1250 vg->es_member_ports |= (1 << i); 1251 } 1252 1253 return (0); 1254 } 1255 1256 static int 1257 e6000sw_getvgroup(device_t dev, etherswitch_vlangroup_t *vg) 1258 { 1259 e6000sw_softc_t *sc; 1260 1261 sc = device_get_softc(dev); 1262 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 1263 1264 if (sc->vlan_mode == ETHERSWITCH_VLAN_PORT) 1265 return (e6000sw_get_port_vlan(sc, vg)); 1266 else if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) 1267 return (e6000sw_get_dot1q_vlan(sc, vg)); 1268 1269 return (EINVAL); 1270 } 1271 1272 static __inline struct mii_data* 1273 e6000sw_miiforphy(e6000sw_softc_t *sc, unsigned int phy) 1274 { 1275 1276 if (!e6000sw_is_phyport(sc, phy)) 1277 return (NULL); 1278 1279 return (device_get_softc(sc->miibus[phy])); 1280 } 1281 1282 static int 1283 e6000sw_ifmedia_upd(struct ifnet *ifp) 1284 { 1285 e6000sw_softc_t *sc; 1286 struct mii_data *mii; 1287 1288 sc = ifp->if_softc; 1289 mii = e6000sw_miiforphy(sc, ifp->if_dunit); 1290 if (mii == NULL) 1291 return (ENXIO); 1292 mii_mediachg(mii); 1293 1294 return (0); 1295 } 1296 1297 static void 1298 e6000sw_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1299 { 1300 e6000sw_softc_t *sc; 1301 struct mii_data *mii; 1302 1303 sc = ifp->if_softc; 1304 mii = e6000sw_miiforphy(sc, ifp->if_dunit); 1305 1306 if (mii == NULL) 1307 return; 1308 1309 mii_pollstat(mii); 1310 ifmr->ifm_active = mii->mii_media_active; 1311 ifmr->ifm_status = mii->mii_media_status; 1312 } 1313 1314 static int 1315 e6000sw_smi_waitready(e6000sw_softc_t *sc, int phy) 1316 { 1317 int i; 1318 1319 for (i = 0; i < E6000SW_SMI_TIMEOUT; i++) { 1320 if ((MDIO_READ(sc->dev, phy, SMI_CMD) & SMI_CMD_BUSY) == 0) 1321 return (0); 1322 DELAY(1); 1323 } 1324 1325 return (1); 1326 } 1327 1328 static __inline uint32_t 1329 e6000sw_readreg(e6000sw_softc_t *sc, int addr, int reg) 1330 { 1331 1332 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 1333 1334 if (!MVSWITCH_MULTICHIP(sc)) 1335 return (MDIO_READ(sc->dev, addr, reg) & 0xffff); 1336 1337 if (e6000sw_smi_waitready(sc, sc->sw_addr)) { 1338 printf("e6000sw: readreg timeout\n"); 1339 return (0xffff); 1340 } 1341 MDIO_WRITE(sc->dev, sc->sw_addr, SMI_CMD, 1342 SMI_CMD_OP_C22_READ | (reg & SMI_CMD_REG_ADDR_MASK) | 1343 ((addr << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK)); 1344 if (e6000sw_smi_waitready(sc, sc->sw_addr)) { 1345 printf("e6000sw: readreg timeout\n"); 1346 return (0xffff); 1347 } 1348 1349 return (MDIO_READ(sc->dev, sc->sw_addr, SMI_DATA) & 0xffff); 1350 } 1351 1352 static __inline void 1353 e6000sw_writereg(e6000sw_softc_t *sc, int addr, int reg, int val) 1354 { 1355 1356 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 1357 1358 if (!MVSWITCH_MULTICHIP(sc)) { 1359 MDIO_WRITE(sc->dev, addr, reg, val); 1360 return; 1361 } 1362 1363 if (e6000sw_smi_waitready(sc, sc->sw_addr)) { 1364 printf("e6000sw: readreg timeout\n"); 1365 return; 1366 } 1367 MDIO_WRITE(sc->dev, sc->sw_addr, SMI_DATA, val); 1368 MDIO_WRITE(sc->dev, sc->sw_addr, SMI_CMD, 1369 SMI_CMD_OP_C22_WRITE | (reg & SMI_CMD_REG_ADDR_MASK) | 1370 ((addr << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK)); 1371 } 1372 1373 static __inline bool 1374 e6000sw_is_cpuport(e6000sw_softc_t *sc, int port) 1375 { 1376 1377 return ((sc->cpuports_mask & (1 << port)) ? true : false); 1378 } 1379 1380 static __inline bool 1381 e6000sw_is_fixedport(e6000sw_softc_t *sc, int port) 1382 { 1383 1384 return ((sc->fixed_mask & (1 << port)) ? true : false); 1385 } 1386 1387 static __inline bool 1388 e6000sw_is_fixed25port(e6000sw_softc_t *sc, int port) 1389 { 1390 1391 return ((sc->fixed25_mask & (1 << port)) ? true : false); 1392 } 1393 1394 static __inline bool 1395 e6000sw_is_phyport(e6000sw_softc_t *sc, int port) 1396 { 1397 uint32_t phy_mask; 1398 phy_mask = ~(sc->fixed_mask | sc->cpuports_mask); 1399 1400 return ((phy_mask & (1 << port)) ? true : false); 1401 } 1402 1403 static __inline bool 1404 e6000sw_is_portenabled(e6000sw_softc_t *sc, int port) 1405 { 1406 1407 return ((sc->ports_mask & (1 << port)) ? true : false); 1408 } 1409 1410 static __inline void 1411 e6000sw_set_pvid(e6000sw_softc_t *sc, int port, int pvid) 1412 { 1413 uint32_t reg; 1414 1415 reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VID); 1416 reg &= ~PORT_VID_DEF_VID_MASK; 1417 reg |= (pvid & PORT_VID_DEF_VID_MASK); 1418 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_VID, reg); 1419 } 1420 1421 static __inline int 1422 e6000sw_get_pvid(e6000sw_softc_t *sc, int port, int *pvid) 1423 { 1424 1425 if (pvid == NULL) 1426 return (ENXIO); 1427 1428 *pvid = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VID) & 1429 PORT_VID_DEF_VID_MASK; 1430 1431 return (0); 1432 } 1433 1434 /* 1435 * Convert port status to ifmedia. 1436 */ 1437 static void 1438 e6000sw_update_ifmedia(uint16_t portstatus, u_int *media_status, u_int *media_active) 1439 { 1440 *media_active = IFM_ETHER; 1441 *media_status = IFM_AVALID; 1442 1443 if ((portstatus & PORT_STATUS_LINK_MASK) != 0) 1444 *media_status |= IFM_ACTIVE; 1445 else { 1446 *media_active |= IFM_NONE; 1447 return; 1448 } 1449 1450 switch (portstatus & PORT_STATUS_SPEED_MASK) { 1451 case PORT_STATUS_SPEED_10: 1452 *media_active |= IFM_10_T; 1453 break; 1454 case PORT_STATUS_SPEED_100: 1455 *media_active |= IFM_100_TX; 1456 break; 1457 case PORT_STATUS_SPEED_1000: 1458 *media_active |= IFM_1000_T; 1459 break; 1460 } 1461 1462 if ((portstatus & PORT_STATUS_DUPLEX_MASK) == 0) 1463 *media_active |= IFM_FDX; 1464 else 1465 *media_active |= IFM_HDX; 1466 } 1467 1468 static void 1469 e6000sw_tick(void *arg, int p __unused) 1470 { 1471 e6000sw_softc_t *sc; 1472 struct mii_data *mii; 1473 struct mii_softc *miisc; 1474 uint16_t portstatus; 1475 int port; 1476 1477 sc = arg; 1478 1479 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 1480 1481 E6000SW_LOCK(sc); 1482 for (port = 0; port < sc->num_ports; port++) { 1483 /* Tick only on PHY ports */ 1484 if (!e6000sw_is_portenabled(sc, port) || 1485 !e6000sw_is_phyport(sc, port)) 1486 continue; 1487 1488 mii = e6000sw_miiforphy(sc, port); 1489 if (mii == NULL) 1490 continue; 1491 1492 portstatus = e6000sw_readreg(sc, REG_PORT(sc, port), 1493 PORT_STATUS); 1494 1495 e6000sw_update_ifmedia(portstatus, 1496 &mii->mii_media_status, &mii->mii_media_active); 1497 1498 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) { 1499 if (IFM_INST(mii->mii_media.ifm_cur->ifm_media) 1500 != miisc->mii_inst) 1501 continue; 1502 mii_phy_update(miisc, MII_POLLSTAT); 1503 } 1504 } 1505 E6000SW_UNLOCK(sc); 1506 } 1507 1508 static void 1509 e6000sw_setup(device_t dev, e6000sw_softc_t *sc) 1510 { 1511 uint32_t atu_ctrl; 1512 1513 /* Set aging time. */ 1514 atu_ctrl = e6000sw_readreg(sc, REG_GLOBAL, ATU_CONTROL); 1515 atu_ctrl &= ~ATU_CONTROL_AGETIME_MASK; 1516 atu_ctrl |= E6000SW_DEFAULT_AGETIME << ATU_CONTROL_AGETIME; 1517 e6000sw_writereg(sc, REG_GLOBAL, ATU_CONTROL, atu_ctrl); 1518 1519 /* Send all with specific mac address to cpu port */ 1520 e6000sw_writereg(sc, REG_GLOBAL2, MGMT_EN_2x, MGMT_EN_ALL); 1521 e6000sw_writereg(sc, REG_GLOBAL2, MGMT_EN_0x, MGMT_EN_ALL); 1522 1523 /* Disable Remote Management */ 1524 e6000sw_writereg(sc, REG_GLOBAL, SWITCH_GLOBAL_CONTROL2, 0); 1525 1526 /* Disable loopback filter and flow control messages */ 1527 e6000sw_writereg(sc, REG_GLOBAL2, SWITCH_MGMT, 1528 SWITCH_MGMT_PRI_MASK | 1529 (1 << SWITCH_MGMT_RSVD2CPU) | 1530 SWITCH_MGMT_FC_PRI_MASK | 1531 (1 << SWITCH_MGMT_FORCEFLOW)); 1532 1533 e6000sw_atu_flush(dev, sc, NO_OPERATION); 1534 e6000sw_atu_mac_table(dev, sc, NULL, NO_OPERATION); 1535 e6000sw_set_atustat(dev, sc, 0, COUNT_ALL); 1536 } 1537 1538 static void 1539 e6000sw_set_atustat(device_t dev, e6000sw_softc_t *sc, int bin, int flag) 1540 { 1541 1542 e6000sw_readreg(sc, REG_GLOBAL2, ATU_STATS); 1543 e6000sw_writereg(sc, REG_GLOBAL2, ATU_STATS, (bin << ATU_STATS_BIN ) | 1544 (flag << ATU_STATS_FLAG)); 1545 } 1546 1547 static int 1548 e6000sw_atu_mac_table(device_t dev, e6000sw_softc_t *sc, struct atu_opt *atu, 1549 int flag) 1550 { 1551 uint16_t ret_opt; 1552 uint16_t ret_data; 1553 1554 if (flag == NO_OPERATION) 1555 return (0); 1556 else if ((flag & (LOAD_FROM_FIB | PURGE_FROM_FIB | GET_NEXT_IN_FIB | 1557 GET_VIOLATION_DATA | CLEAR_VIOLATION_DATA)) == 0) { 1558 device_printf(dev, "Wrong Opcode for ATU operation\n"); 1559 return (EINVAL); 1560 } 1561 1562 if (E6000SW_WAITREADY(sc, ATU_OPERATION, ATU_UNIT_BUSY)) { 1563 device_printf(dev, "ATU unit is busy, cannot access\n"); 1564 return (EBUSY); 1565 } 1566 1567 ret_opt = e6000sw_readreg(sc, REG_GLOBAL, ATU_OPERATION); 1568 if (flag & LOAD_FROM_FIB) { 1569 ret_data = e6000sw_readreg(sc, REG_GLOBAL, ATU_DATA); 1570 e6000sw_writereg(sc, REG_GLOBAL2, ATU_DATA, (ret_data & 1571 ~ENTRY_STATE)); 1572 } 1573 e6000sw_writereg(sc, REG_GLOBAL, ATU_MAC_ADDR01, atu->mac_01); 1574 e6000sw_writereg(sc, REG_GLOBAL, ATU_MAC_ADDR23, atu->mac_23); 1575 e6000sw_writereg(sc, REG_GLOBAL, ATU_MAC_ADDR45, atu->mac_45); 1576 e6000sw_writereg(sc, REG_GLOBAL, ATU_FID, atu->fid); 1577 1578 e6000sw_writereg(sc, REG_GLOBAL, ATU_OPERATION, 1579 (ret_opt | ATU_UNIT_BUSY | flag)); 1580 1581 if (E6000SW_WAITREADY(sc, ATU_OPERATION, ATU_UNIT_BUSY)) 1582 device_printf(dev, "Timeout while waiting ATU\n"); 1583 else if (flag & GET_NEXT_IN_FIB) { 1584 atu->mac_01 = e6000sw_readreg(sc, REG_GLOBAL, 1585 ATU_MAC_ADDR01); 1586 atu->mac_23 = e6000sw_readreg(sc, REG_GLOBAL, 1587 ATU_MAC_ADDR23); 1588 atu->mac_45 = e6000sw_readreg(sc, REG_GLOBAL, 1589 ATU_MAC_ADDR45); 1590 } 1591 1592 return (0); 1593 } 1594 1595 static int 1596 e6000sw_atu_flush(device_t dev, e6000sw_softc_t *sc, int flag) 1597 { 1598 uint32_t reg; 1599 1600 if (flag == NO_OPERATION) 1601 return (0); 1602 1603 if (E6000SW_WAITREADY(sc, ATU_OPERATION, ATU_UNIT_BUSY)) { 1604 device_printf(dev, "ATU unit is busy, cannot access\n"); 1605 return (EBUSY); 1606 } 1607 reg = e6000sw_readreg(sc, REG_GLOBAL, ATU_OPERATION); 1608 e6000sw_writereg(sc, REG_GLOBAL, ATU_OPERATION, 1609 (reg | ATU_UNIT_BUSY | flag)); 1610 if (E6000SW_WAITREADY(sc, ATU_OPERATION, ATU_UNIT_BUSY)) 1611 device_printf(dev, "Timeout while flushing ATU\n"); 1612 1613 return (0); 1614 } 1615 1616 static int 1617 e6000sw_vtu_flush(e6000sw_softc_t *sc) 1618 { 1619 1620 if (E6000SW_WAITREADY(sc, VTU_OPERATION, VTU_BUSY)) { 1621 device_printf(sc->dev, "VTU unit is busy, cannot access\n"); 1622 return (EBUSY); 1623 } 1624 1625 e6000sw_writereg(sc, REG_GLOBAL, VTU_OPERATION, VTU_FLUSH | VTU_BUSY); 1626 if (E6000SW_WAITREADY(sc, VTU_OPERATION, VTU_BUSY)) { 1627 device_printf(sc->dev, "Timeout while flushing VTU\n"); 1628 return (ETIMEDOUT); 1629 } 1630 1631 return (0); 1632 } 1633 1634 static int 1635 e6000sw_vtu_update(e6000sw_softc_t *sc, int purge, int vid, int fid, 1636 int members, int untagged) 1637 { 1638 int i, op; 1639 uint32_t data[2]; 1640 1641 if (E6000SW_WAITREADY(sc, VTU_OPERATION, VTU_BUSY)) { 1642 device_printf(sc->dev, "VTU unit is busy, cannot access\n"); 1643 return (EBUSY); 1644 } 1645 1646 *data = (vid & VTU_VID_MASK); 1647 if (purge == 0) 1648 *data |= VTU_VID_VALID; 1649 e6000sw_writereg(sc, REG_GLOBAL, VTU_VID, *data); 1650 1651 if (purge == 0) { 1652 data[0] = 0; 1653 data[1] = 0; 1654 for (i = 0; i < sc->num_ports; i++) { 1655 if ((untagged & (1 << i)) != 0) 1656 data[i / VTU_PPREG(sc)] |= 1657 VTU_PORT_UNTAGGED << VTU_PORT(sc, i); 1658 else if ((members & (1 << i)) != 0) 1659 data[i / VTU_PPREG(sc)] |= 1660 VTU_PORT_TAGGED << VTU_PORT(sc, i); 1661 else 1662 data[i / VTU_PPREG(sc)] |= 1663 VTU_PORT_DISCARD << VTU_PORT(sc, i); 1664 } 1665 e6000sw_writereg(sc, REG_GLOBAL, VTU_DATA, data[0]); 1666 e6000sw_writereg(sc, REG_GLOBAL, VTU_DATA2, data[1]); 1667 e6000sw_writereg(sc, REG_GLOBAL, VTU_FID, 1668 fid & VTU_FID_MASK(sc)); 1669 op = VTU_LOAD; 1670 } else 1671 op = VTU_PURGE; 1672 1673 e6000sw_writereg(sc, REG_GLOBAL, VTU_OPERATION, op | VTU_BUSY); 1674 if (E6000SW_WAITREADY(sc, VTU_OPERATION, VTU_BUSY)) { 1675 device_printf(sc->dev, "Timeout while flushing VTU\n"); 1676 return (ETIMEDOUT); 1677 } 1678 1679 return (0); 1680 } 1681