1 /*- 2 * Copyright (c) 2015 Semihalf 3 * Copyright (c) 2015 Stormshield 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef _E6000SWREG_H_ 32 #define _E6000SWREG_H_ 33 34 struct atu_opt { 35 uint16_t mac_01; 36 uint16_t mac_23; 37 uint16_t mac_45; 38 uint16_t fid; 39 }; 40 41 /* 42 * Definitions for the Marvell 88E6000 series Ethernet Switch. 43 */ 44 45 /* 46 * Switch Registers 47 */ 48 #define REG_GLOBAL 0x1b 49 #define REG_GLOBAL2 0x1c 50 #define REG_PORT(p) (0x10 + (p)) 51 52 #define REG_NUM_MAX 31 53 54 /* 55 * Per-Port Switch Registers 56 */ 57 #define PORT_STATUS 0x0 58 #define PORT_STATUS_SPEED_MASK 0x300 59 #define PORT_STATUS_SPEED_10 0 60 #define PORT_STATUS_SPEED_100 1 61 #define PORT_STATUS_SPEED_1000 2 62 #define PORT_STATUS_DUPLEX_MASK (1 << 10) 63 #define PORT_STATUS_LINK_MASK (1 << 11) 64 #define PORT_STATUS_PHY_DETECT_MASK (1 << 12) 65 66 #define PSC_CONTROL 0x1 67 #define SWITCH_ID 0x3 68 #define PORT_CONTROL 0x4 69 #define PORT_CONTROL_1 0x5 70 #define PORT_VLAN_MAP 0x6 71 #define PORT_VID 0x7 72 #define PORT_ASSOCIATION_VECTOR 0xb 73 #define PORT_ATU_CTRL 0xc 74 #define RX_COUNTER 0x12 75 #define TX_COUNTER 0x13 76 77 #define PORT_VID_DEF_VID 0 78 #define PORT_VID_DEF_VID_MASK 0xfff 79 #define PORT_VID_PRIORITY_MASK 0xc00 80 81 #define PORT_CONTROL_ENABLE 0x3 82 83 /* PORT_VLAN fields */ 84 #define PORT_VLAN_MAP_TABLE_MASK 0x7f 85 #define PORT_VLAN_MAP_FID 12 86 #define PORT_VLAN_MAP_FID_MASK 0xf000 87 /* 88 * Switch Global Register 1 accessed via REG_GLOBAL_ADDR 89 */ 90 #define SWITCH_GLOBAL_STATUS 0 91 #define SWITCH_GLOBAL_CONTROL 4 92 #define SWITCH_GLOBAL_CONTROL2 28 93 94 #define MONITOR_CONTROL 26 95 96 /* ATU operation */ 97 #define ATU_FID 1 98 #define ATU_CONTROL 10 99 #define ATU_OPERATION 11 100 #define ATU_DATA 12 101 #define ATU_MAC_ADDR01 13 102 #define ATU_MAC_ADDR23 14 103 #define ATU_MAC_ADDR45 15 104 105 #define ATU_UNIT_BUSY (1 << 15) 106 #define ENTRY_STATE 0xf 107 108 /* ATU_CONTROL fields */ 109 #define ATU_CONTROL_AGETIME 4 110 #define ATU_CONTROL_AGETIME_MASK 0xff0 111 #define ATU_CONTROL_LEARN2ALL 3 112 113 /* ATU opcode */ 114 #define NO_OPERATION (0 << 0) 115 #define FLUSH_ALL (1 << 0) 116 #define FLUSH_NON_STATIC (1 << 1) 117 #define LOAD_FROM_FIB (3 << 0) 118 #define PURGE_FROM_FIB (3 << 0) 119 #define GET_NEXT_IN_FIB (1 << 2) 120 #define FLUSH_ALL_IN_FIB (5 << 0) 121 #define FLUSH_NON_STATIC_IN_FIB (3 << 1) 122 #define GET_VIOLATION_DATA (7 << 0) 123 #define CLEAR_VIOLATION_DATA (7 << 0) 124 125 /* ATU Stats */ 126 #define COUNT_ALL (0 << 0) 127 128 /* 129 * Switch Global Register 2 accessed via REG_GLOBAL2_ADDR 130 */ 131 #define MGMT_EN_2x 2 132 #define MGMT_EN_0x 3 133 #define SWITCH_MGMT 5 134 #define ATU_STATS 14 135 136 #define MGMT_EN_ALL 0xffff 137 138 /* SWITCH_MGMT fields */ 139 140 #define SWITCH_MGMT_PRI 0 141 #define SWITCH_MGMT_PRI_MASK 7 142 #define SWITCH_MGMT_RSVD2CPU 3 143 #define SWITCH_MGMT_FC_PRI 4 144 #define SWITCH_MGMT_FC_PRI_MASK (7 << 4) 145 #define SWITCH_MGMT_FORCEFLOW 7 146 147 /* ATU_STATS fields */ 148 149 #define ATU_STATS_BIN 14 150 #define ATU_STATS_FLAG 12 151 152 /* 153 * PHY registers accessed via 'Switch Global Registers' (REG_GLOBAL2). 154 */ 155 #define SMI_PHY_CMD_REG 0x18 156 #define SMI_PHY_DATA_REG 0x19 157 158 #define PHY_DATA_MASK 0xffff 159 160 #define PHY_CMD_SMI_BUSY 15 161 #define PHY_CMD_MODE 12 162 #define PHY_CMD_MODE_MDIO 1 163 #define PHY_CMD_MODE_XMDIO 0 164 #define PHY_CMD_OPCODE 10 165 #define PHY_CMD_OPCODE_WRITE 1 166 #define PHY_CMD_OPCODE_READ 2 167 #define PHY_CMD_DEV_ADDR 5 168 #define PHY_CMD_DEV_ADDR_MASK 0x3e0 169 #define PHY_CMD_REG_ADDR 0 170 #define PHY_CMD_REG_ADDR_MASK 0x1f 171 172 #define PHY_PAGE_REG 22 173 174 /* 175 * Scratch and Misc register accessed via 176 * 'Switch Global Registers' (REG_GLOBAL2) 177 */ 178 #define SCR_AND_MISC_REG 0x1a 179 180 #define SCR_AND_MISC_PTR_CFG 0x7000 181 #define SCR_AND_MISC_DATA_CFG_MASK 0xf0 182 183 #define E6000SW_NUM_PHY_REGS 29 184 #define E6000SW_NUM_VGROUPS 8 185 #define E6000SW_MAX_PORTS 10 186 #define E6000SW_PORT_NO_VGROUP -1 187 #define E6000SW_DEFAULT_AGETIME 20 188 #define E6000SW_RETRIES 100 189 #define E6000SW_SMI_TIMEOUT 16 190 191 #endif /* _E6000SWREG_H_ */ 192