1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Driver for Freescale Fast Ethernet Controller, found on imx-series SoCs among 35 * others. Also works for the ENET Gigibit controller found on imx6 and imx28, 36 * but the driver doesn't currently use any of the ENET advanced features other 37 * than enabling gigabit. 38 * 39 * The interface name 'fec' is already taken by netgraph's Fast Etherchannel 40 * (netgraph/ng_fec.c), so we use 'ffec'. 41 * 42 * Requires an FDT entry with at least these properties: 43 * fec: ethernet@02188000 { 44 * compatible = "fsl,imxNN-fec"; 45 * reg = <0x02188000 0x4000>; 46 * interrupts = <150 151>; 47 * phy-mode = "rgmii"; 48 * phy-disable-preamble; // optional 49 * }; 50 * The second interrupt number is for IEEE-1588, and is not currently used; it 51 * need not be present. phy-mode must be one of: "mii", "rmii", "rgmii". 52 * There is also an optional property, phy-disable-preamble, which if present 53 * will disable the preamble bits, cutting the size of each mdio transaction 54 * (and thus the busy-wait time) in half. 55 */ 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/bus.h> 60 #include <sys/endian.h> 61 #include <sys/kernel.h> 62 #include <sys/lock.h> 63 #include <sys/malloc.h> 64 #include <sys/mbuf.h> 65 #include <sys/module.h> 66 #include <sys/mutex.h> 67 #include <sys/rman.h> 68 #include <sys/socket.h> 69 #include <sys/sockio.h> 70 #include <sys/sysctl.h> 71 72 #include <machine/bus.h> 73 74 #include <net/bpf.h> 75 #include <net/if.h> 76 #include <net/ethernet.h> 77 #include <net/if_dl.h> 78 #include <net/if_media.h> 79 #include <net/if_types.h> 80 #include <net/if_var.h> 81 #include <net/if_vlan_var.h> 82 83 #include <dev/fdt/fdt_common.h> 84 #include <dev/ffec/if_ffecreg.h> 85 #include <dev/ofw/ofw_bus.h> 86 #include <dev/ofw/ofw_bus_subr.h> 87 #include <dev/mii/mii.h> 88 #include <dev/mii/miivar.h> 89 #include <dev/mii/mii_fdt.h> 90 #include "miibus_if.h" 91 92 /* 93 * There are small differences in the hardware on various SoCs. Not every SoC 94 * we support has its own FECTYPE; most work as GENERIC and only the ones that 95 * need different handling get their own entry. In addition to the types in 96 * this list, there are some flags below that can be ORed into the upper bits. 97 */ 98 enum { 99 FECTYPE_NONE, 100 FECTYPE_GENERIC, 101 FECTYPE_IMX53, 102 FECTYPE_IMX6, /* imx6 and imx7 */ 103 FECTYPE_MVF, 104 }; 105 106 /* 107 * Flags that describe general differences between the FEC hardware in various 108 * SoCs. These are ORed into the FECTYPE enum values in the ofw_compat_data, so 109 * the low 8 bits are reserved for the type enum. In the softc, the type and 110 * flags are put into separate members, so that you don't need to mask the flags 111 * out of the type to compare it. 112 */ 113 #define FECTYPE_MASK 0x000000ff 114 #define FECFLAG_GBE (1 << 8) 115 #define FECFLAG_AVB (1 << 9) 116 #define FECFLAG_RACC (1 << 10) 117 118 /* 119 * Table of supported FDT compat strings and their associated FECTYPE values. 120 */ 121 static struct ofw_compat_data compat_data[] = { 122 {"fsl,imx51-fec", FECTYPE_GENERIC}, 123 {"fsl,imx53-fec", FECTYPE_IMX53}, 124 {"fsl,imx6q-fec", FECTYPE_IMX6 | FECFLAG_RACC | FECFLAG_GBE }, 125 {"fsl,imx6ul-fec", FECTYPE_IMX6 | FECFLAG_RACC }, 126 {"fsl,imx7d-fec", FECTYPE_IMX6 | FECFLAG_RACC | FECFLAG_GBE | 127 FECFLAG_AVB }, 128 {"fsl,mvf600-fec", FECTYPE_MVF | FECFLAG_RACC }, 129 {"fsl,mvf-fec", FECTYPE_MVF}, 130 {NULL, FECTYPE_NONE}, 131 }; 132 133 /* 134 * Driver data and defines. 135 */ 136 #define RX_DESC_COUNT 64 137 #define RX_DESC_SIZE (sizeof(struct ffec_hwdesc) * RX_DESC_COUNT) 138 #define TX_DESC_COUNT 64 139 #define TX_DESC_SIZE (sizeof(struct ffec_hwdesc) * TX_DESC_COUNT) 140 141 #define WATCHDOG_TIMEOUT_SECS 5 142 143 #define MAX_IRQ_COUNT 3 144 145 struct ffec_bufmap { 146 struct mbuf *mbuf; 147 bus_dmamap_t map; 148 }; 149 150 struct ffec_softc { 151 device_t dev; 152 device_t miibus; 153 struct mii_data * mii_softc; 154 struct ifnet *ifp; 155 int if_flags; 156 struct mtx mtx; 157 struct resource *irq_res[MAX_IRQ_COUNT]; 158 struct resource *mem_res; 159 void * intr_cookie[MAX_IRQ_COUNT]; 160 struct callout ffec_callout; 161 mii_contype_t phy_conn_type; 162 uint32_t fecflags; 163 uint8_t fectype; 164 boolean_t link_is_up; 165 boolean_t is_attached; 166 boolean_t is_detaching; 167 int tx_watchdog_count; 168 int rxbuf_align; 169 int txbuf_align; 170 171 bus_dma_tag_t rxdesc_tag; 172 bus_dmamap_t rxdesc_map; 173 struct ffec_hwdesc *rxdesc_ring; 174 bus_addr_t rxdesc_ring_paddr; 175 bus_dma_tag_t rxbuf_tag; 176 struct ffec_bufmap rxbuf_map[RX_DESC_COUNT]; 177 uint32_t rx_idx; 178 179 bus_dma_tag_t txdesc_tag; 180 bus_dmamap_t txdesc_map; 181 struct ffec_hwdesc *txdesc_ring; 182 bus_addr_t txdesc_ring_paddr; 183 bus_dma_tag_t txbuf_tag; 184 struct ffec_bufmap txbuf_map[TX_DESC_COUNT]; 185 uint32_t tx_idx_head; 186 uint32_t tx_idx_tail; 187 int txcount; 188 }; 189 190 static struct resource_spec irq_res_spec[MAX_IRQ_COUNT + 1] = { 191 { SYS_RES_IRQ, 0, RF_ACTIVE }, 192 { SYS_RES_IRQ, 1, RF_ACTIVE | RF_OPTIONAL }, 193 { SYS_RES_IRQ, 2, RF_ACTIVE | RF_OPTIONAL }, 194 RESOURCE_SPEC_END 195 }; 196 197 #define FFEC_LOCK(sc) mtx_lock(&(sc)->mtx) 198 #define FFEC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 199 #define FFEC_LOCK_INIT(sc) mtx_init(&(sc)->mtx, \ 200 device_get_nameunit((sc)->dev), MTX_NETWORK_LOCK, MTX_DEF) 201 #define FFEC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx); 202 #define FFEC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED); 203 #define FFEC_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED); 204 205 static void ffec_init_locked(struct ffec_softc *sc); 206 static void ffec_stop_locked(struct ffec_softc *sc); 207 static void ffec_txstart_locked(struct ffec_softc *sc); 208 static void ffec_txfinish_locked(struct ffec_softc *sc); 209 210 static inline uint16_t 211 RD2(struct ffec_softc *sc, bus_size_t off) 212 { 213 214 return (bus_read_2(sc->mem_res, off)); 215 } 216 217 static inline void 218 WR2(struct ffec_softc *sc, bus_size_t off, uint16_t val) 219 { 220 221 bus_write_2(sc->mem_res, off, val); 222 } 223 224 static inline uint32_t 225 RD4(struct ffec_softc *sc, bus_size_t off) 226 { 227 228 return (bus_read_4(sc->mem_res, off)); 229 } 230 231 static inline void 232 WR4(struct ffec_softc *sc, bus_size_t off, uint32_t val) 233 { 234 235 bus_write_4(sc->mem_res, off, val); 236 } 237 238 static inline uint32_t 239 next_rxidx(struct ffec_softc *sc, uint32_t curidx) 240 { 241 242 return ((curidx == RX_DESC_COUNT - 1) ? 0 : curidx + 1); 243 } 244 245 static inline uint32_t 246 next_txidx(struct ffec_softc *sc, uint32_t curidx) 247 { 248 249 return ((curidx == TX_DESC_COUNT - 1) ? 0 : curidx + 1); 250 } 251 252 static void 253 ffec_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 254 { 255 256 if (error != 0) 257 return; 258 *(bus_addr_t *)arg = segs[0].ds_addr; 259 } 260 261 static void 262 ffec_miigasket_setup(struct ffec_softc *sc) 263 { 264 uint32_t ifmode; 265 266 /* 267 * We only need the gasket for MII and RMII connections on certain SoCs. 268 */ 269 270 switch (sc->fectype) 271 { 272 case FECTYPE_IMX53: 273 break; 274 default: 275 return; 276 } 277 278 switch (sc->phy_conn_type) 279 { 280 case MII_CONTYPE_MII: 281 ifmode = 0; 282 break; 283 case MII_CONTYPE_RMII: 284 ifmode = FEC_MIIGSK_CFGR_IF_MODE_RMII; 285 break; 286 default: 287 return; 288 } 289 290 /* 291 * Disable the gasket, configure for either MII or RMII, then enable. 292 */ 293 294 WR2(sc, FEC_MIIGSK_ENR, 0); 295 while (RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY) 296 continue; 297 298 WR2(sc, FEC_MIIGSK_CFGR, ifmode); 299 300 WR2(sc, FEC_MIIGSK_ENR, FEC_MIIGSK_ENR_EN); 301 while (!(RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY)) 302 continue; 303 } 304 305 static boolean_t 306 ffec_miibus_iowait(struct ffec_softc *sc) 307 { 308 uint32_t timeout; 309 310 for (timeout = 10000; timeout != 0; --timeout) 311 if (RD4(sc, FEC_IER_REG) & FEC_IER_MII) 312 return (true); 313 314 return (false); 315 } 316 317 static int 318 ffec_miibus_readreg(device_t dev, int phy, int reg) 319 { 320 struct ffec_softc *sc; 321 int val; 322 323 sc = device_get_softc(dev); 324 325 WR4(sc, FEC_IER_REG, FEC_IER_MII); 326 327 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_READ | 328 FEC_MMFR_ST_VALUE | FEC_MMFR_TA_VALUE | 329 ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) | 330 ((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK)); 331 332 if (!ffec_miibus_iowait(sc)) { 333 device_printf(dev, "timeout waiting for mii read\n"); 334 return (-1); /* All-ones is a symptom of bad mdio. */ 335 } 336 337 val = RD4(sc, FEC_MMFR_REG) & FEC_MMFR_DATA_MASK; 338 339 return (val); 340 } 341 342 static int 343 ffec_miibus_writereg(device_t dev, int phy, int reg, int val) 344 { 345 struct ffec_softc *sc; 346 347 sc = device_get_softc(dev); 348 349 WR4(sc, FEC_IER_REG, FEC_IER_MII); 350 351 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_WRITE | 352 FEC_MMFR_ST_VALUE | FEC_MMFR_TA_VALUE | 353 ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) | 354 ((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK) | 355 (val & FEC_MMFR_DATA_MASK)); 356 357 if (!ffec_miibus_iowait(sc)) { 358 device_printf(dev, "timeout waiting for mii write\n"); 359 return (-1); 360 } 361 362 return (0); 363 } 364 365 static void 366 ffec_miibus_statchg(device_t dev) 367 { 368 struct ffec_softc *sc; 369 struct mii_data *mii; 370 uint32_t ecr, rcr, tcr; 371 372 /* 373 * Called by the MII bus driver when the PHY establishes link to set the 374 * MAC interface registers. 375 */ 376 377 sc = device_get_softc(dev); 378 379 FFEC_ASSERT_LOCKED(sc); 380 381 mii = sc->mii_softc; 382 383 if (mii->mii_media_status & IFM_ACTIVE) 384 sc->link_is_up = true; 385 else 386 sc->link_is_up = false; 387 388 ecr = RD4(sc, FEC_ECR_REG) & ~FEC_ECR_SPEED; 389 rcr = RD4(sc, FEC_RCR_REG) & ~(FEC_RCR_RMII_10T | FEC_RCR_RMII_MODE | 390 FEC_RCR_RGMII_EN | FEC_RCR_DRT | FEC_RCR_FCE); 391 tcr = RD4(sc, FEC_TCR_REG) & ~FEC_TCR_FDEN; 392 393 rcr |= FEC_RCR_MII_MODE; /* Must always be on even for R[G]MII. */ 394 switch (sc->phy_conn_type) { 395 case MII_CONTYPE_RMII: 396 rcr |= FEC_RCR_RMII_MODE; 397 break; 398 case MII_CONTYPE_RGMII: 399 case MII_CONTYPE_RGMII_ID: 400 case MII_CONTYPE_RGMII_RXID: 401 case MII_CONTYPE_RGMII_TXID: 402 rcr |= FEC_RCR_RGMII_EN; 403 break; 404 default: 405 break; 406 } 407 408 switch (IFM_SUBTYPE(mii->mii_media_active)) { 409 case IFM_1000_T: 410 case IFM_1000_SX: 411 ecr |= FEC_ECR_SPEED; 412 break; 413 case IFM_100_TX: 414 /* Not-FEC_ECR_SPEED + not-FEC_RCR_RMII_10T means 100TX */ 415 break; 416 case IFM_10_T: 417 rcr |= FEC_RCR_RMII_10T; 418 break; 419 case IFM_NONE: 420 sc->link_is_up = false; 421 return; 422 default: 423 sc->link_is_up = false; 424 device_printf(dev, "Unsupported media %u\n", 425 IFM_SUBTYPE(mii->mii_media_active)); 426 return; 427 } 428 429 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 430 tcr |= FEC_TCR_FDEN; 431 else 432 rcr |= FEC_RCR_DRT; 433 434 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FLOW) != 0) 435 rcr |= FEC_RCR_FCE; 436 437 WR4(sc, FEC_RCR_REG, rcr); 438 WR4(sc, FEC_TCR_REG, tcr); 439 WR4(sc, FEC_ECR_REG, ecr); 440 } 441 442 static void 443 ffec_media_status(struct ifnet * ifp, struct ifmediareq *ifmr) 444 { 445 struct ffec_softc *sc; 446 struct mii_data *mii; 447 448 449 sc = ifp->if_softc; 450 mii = sc->mii_softc; 451 FFEC_LOCK(sc); 452 mii_pollstat(mii); 453 ifmr->ifm_active = mii->mii_media_active; 454 ifmr->ifm_status = mii->mii_media_status; 455 FFEC_UNLOCK(sc); 456 } 457 458 static int 459 ffec_media_change_locked(struct ffec_softc *sc) 460 { 461 462 return (mii_mediachg(sc->mii_softc)); 463 } 464 465 static int 466 ffec_media_change(struct ifnet * ifp) 467 { 468 struct ffec_softc *sc; 469 int error; 470 471 sc = ifp->if_softc; 472 473 FFEC_LOCK(sc); 474 error = ffec_media_change_locked(sc); 475 FFEC_UNLOCK(sc); 476 return (error); 477 } 478 479 static void ffec_clear_stats(struct ffec_softc *sc) 480 { 481 uint32_t mibc; 482 483 mibc = RD4(sc, FEC_MIBC_REG); 484 485 /* 486 * On newer hardware the statistic regs are cleared by toggling a bit in 487 * the mib control register. On older hardware the clear procedure is 488 * to disable statistics collection, zero the regs, then re-enable. 489 */ 490 if (sc->fectype == FECTYPE_IMX6 || sc->fectype == FECTYPE_MVF) { 491 WR4(sc, FEC_MIBC_REG, mibc | FEC_MIBC_CLEAR); 492 WR4(sc, FEC_MIBC_REG, mibc & ~FEC_MIBC_CLEAR); 493 } else { 494 WR4(sc, FEC_MIBC_REG, mibc | FEC_MIBC_DIS); 495 496 WR4(sc, FEC_IEEE_R_DROP, 0); 497 WR4(sc, FEC_IEEE_R_MACERR, 0); 498 WR4(sc, FEC_RMON_R_CRC_ALIGN, 0); 499 WR4(sc, FEC_RMON_R_FRAG, 0); 500 WR4(sc, FEC_RMON_R_JAB, 0); 501 WR4(sc, FEC_RMON_R_MC_PKT, 0); 502 WR4(sc, FEC_RMON_R_OVERSIZE, 0); 503 WR4(sc, FEC_RMON_R_PACKETS, 0); 504 WR4(sc, FEC_RMON_R_UNDERSIZE, 0); 505 WR4(sc, FEC_RMON_T_COL, 0); 506 WR4(sc, FEC_RMON_T_CRC_ALIGN, 0); 507 WR4(sc, FEC_RMON_T_FRAG, 0); 508 WR4(sc, FEC_RMON_T_JAB, 0); 509 WR4(sc, FEC_RMON_T_MC_PKT, 0); 510 WR4(sc, FEC_RMON_T_OVERSIZE , 0); 511 WR4(sc, FEC_RMON_T_PACKETS, 0); 512 WR4(sc, FEC_RMON_T_UNDERSIZE, 0); 513 514 WR4(sc, FEC_MIBC_REG, mibc); 515 } 516 } 517 518 static void 519 ffec_harvest_stats(struct ffec_softc *sc) 520 { 521 struct ifnet *ifp; 522 523 ifp = sc->ifp; 524 525 /* 526 * - FEC_IEEE_R_DROP is "dropped due to invalid start frame delimiter" 527 * so it's really just another type of input error. 528 * - FEC_IEEE_R_MACERR is "no receive fifo space"; count as input drops. 529 */ 530 if_inc_counter(ifp, IFCOUNTER_IPACKETS, RD4(sc, FEC_RMON_R_PACKETS)); 531 if_inc_counter(ifp, IFCOUNTER_IMCASTS, RD4(sc, FEC_RMON_R_MC_PKT)); 532 if_inc_counter(ifp, IFCOUNTER_IERRORS, 533 RD4(sc, FEC_RMON_R_CRC_ALIGN) + RD4(sc, FEC_RMON_R_UNDERSIZE) + 534 RD4(sc, FEC_RMON_R_OVERSIZE) + RD4(sc, FEC_RMON_R_FRAG) + 535 RD4(sc, FEC_RMON_R_JAB) + RD4(sc, FEC_IEEE_R_DROP)); 536 537 if_inc_counter(ifp, IFCOUNTER_IQDROPS, RD4(sc, FEC_IEEE_R_MACERR)); 538 539 if_inc_counter(ifp, IFCOUNTER_OPACKETS, RD4(sc, FEC_RMON_T_PACKETS)); 540 if_inc_counter(ifp, IFCOUNTER_OMCASTS, RD4(sc, FEC_RMON_T_MC_PKT)); 541 if_inc_counter(ifp, IFCOUNTER_OERRORS, 542 RD4(sc, FEC_RMON_T_CRC_ALIGN) + RD4(sc, FEC_RMON_T_UNDERSIZE) + 543 RD4(sc, FEC_RMON_T_OVERSIZE) + RD4(sc, FEC_RMON_T_FRAG) + 544 RD4(sc, FEC_RMON_T_JAB)); 545 546 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, RD4(sc, FEC_RMON_T_COL)); 547 548 ffec_clear_stats(sc); 549 } 550 551 static void 552 ffec_tick(void *arg) 553 { 554 struct ffec_softc *sc; 555 struct ifnet *ifp; 556 int link_was_up; 557 558 sc = arg; 559 560 FFEC_ASSERT_LOCKED(sc); 561 562 ifp = sc->ifp; 563 564 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 565 return; 566 567 /* 568 * Typical tx watchdog. If this fires it indicates that we enqueued 569 * packets for output and never got a txdone interrupt for them. Maybe 570 * it's a missed interrupt somehow, just pretend we got one. 571 */ 572 if (sc->tx_watchdog_count > 0) { 573 if (--sc->tx_watchdog_count == 0) { 574 ffec_txfinish_locked(sc); 575 } 576 } 577 578 /* Gather stats from hardware counters. */ 579 ffec_harvest_stats(sc); 580 581 /* Check the media status. */ 582 link_was_up = sc->link_is_up; 583 mii_tick(sc->mii_softc); 584 if (sc->link_is_up && !link_was_up) 585 ffec_txstart_locked(sc); 586 587 /* Schedule another check one second from now. */ 588 callout_reset(&sc->ffec_callout, hz, ffec_tick, sc); 589 } 590 591 inline static uint32_t 592 ffec_setup_txdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr, 593 uint32_t len) 594 { 595 uint32_t nidx; 596 uint32_t flags; 597 598 nidx = next_txidx(sc, idx); 599 600 /* Addr/len 0 means we're clearing the descriptor after xmit done. */ 601 if (paddr == 0 || len == 0) { 602 flags = 0; 603 --sc->txcount; 604 } else { 605 flags = FEC_TXDESC_READY | FEC_TXDESC_L | FEC_TXDESC_TC; 606 ++sc->txcount; 607 } 608 if (nidx == 0) 609 flags |= FEC_TXDESC_WRAP; 610 611 /* 612 * The hardware requires 32-bit physical addresses. We set up the dma 613 * tag to indicate that, so the cast to uint32_t should never lose 614 * significant bits. 615 */ 616 sc->txdesc_ring[idx].buf_paddr = (uint32_t)paddr; 617 sc->txdesc_ring[idx].flags_len = flags | len; /* Must be set last! */ 618 619 return (nidx); 620 } 621 622 static int 623 ffec_setup_txbuf(struct ffec_softc *sc, int idx, struct mbuf **mp) 624 { 625 struct mbuf * m; 626 int error, nsegs; 627 struct bus_dma_segment seg; 628 629 if ((m = m_defrag(*mp, M_NOWAIT)) == NULL) 630 return (ENOMEM); 631 *mp = m; 632 633 error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map, 634 m, &seg, &nsegs, 0); 635 if (error != 0) { 636 return (ENOMEM); 637 } 638 bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map, 639 BUS_DMASYNC_PREWRITE); 640 641 sc->txbuf_map[idx].mbuf = m; 642 ffec_setup_txdesc(sc, idx, seg.ds_addr, seg.ds_len); 643 644 return (0); 645 646 } 647 648 static void 649 ffec_txstart_locked(struct ffec_softc *sc) 650 { 651 struct ifnet *ifp; 652 struct mbuf *m; 653 int enqueued; 654 655 FFEC_ASSERT_LOCKED(sc); 656 657 if (!sc->link_is_up) 658 return; 659 660 ifp = sc->ifp; 661 662 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 663 return; 664 665 enqueued = 0; 666 667 for (;;) { 668 if (sc->txcount == (TX_DESC_COUNT-1)) { 669 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 670 break; 671 } 672 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 673 if (m == NULL) 674 break; 675 if (ffec_setup_txbuf(sc, sc->tx_idx_head, &m) != 0) { 676 IFQ_DRV_PREPEND(&ifp->if_snd, m); 677 break; 678 } 679 BPF_MTAP(ifp, m); 680 sc->tx_idx_head = next_txidx(sc, sc->tx_idx_head); 681 ++enqueued; 682 } 683 684 if (enqueued != 0) { 685 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_PREWRITE); 686 WR4(sc, FEC_TDAR_REG, FEC_TDAR_TDAR); 687 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_POSTWRITE); 688 sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS; 689 } 690 } 691 692 static void 693 ffec_txstart(struct ifnet *ifp) 694 { 695 struct ffec_softc *sc = ifp->if_softc; 696 697 FFEC_LOCK(sc); 698 ffec_txstart_locked(sc); 699 FFEC_UNLOCK(sc); 700 } 701 702 static void 703 ffec_txfinish_locked(struct ffec_softc *sc) 704 { 705 struct ifnet *ifp; 706 struct ffec_hwdesc *desc; 707 struct ffec_bufmap *bmap; 708 boolean_t retired_buffer; 709 710 FFEC_ASSERT_LOCKED(sc); 711 712 /* XXX Can't set PRE|POST right now, but we need both. */ 713 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_PREREAD); 714 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_POSTREAD); 715 ifp = sc->ifp; 716 retired_buffer = false; 717 while (sc->tx_idx_tail != sc->tx_idx_head) { 718 desc = &sc->txdesc_ring[sc->tx_idx_tail]; 719 if (desc->flags_len & FEC_TXDESC_READY) 720 break; 721 retired_buffer = true; 722 bmap = &sc->txbuf_map[sc->tx_idx_tail]; 723 bus_dmamap_sync(sc->txbuf_tag, bmap->map, 724 BUS_DMASYNC_POSTWRITE); 725 bus_dmamap_unload(sc->txbuf_tag, bmap->map); 726 m_freem(bmap->mbuf); 727 bmap->mbuf = NULL; 728 ffec_setup_txdesc(sc, sc->tx_idx_tail, 0, 0); 729 sc->tx_idx_tail = next_txidx(sc, sc->tx_idx_tail); 730 } 731 732 /* 733 * If we retired any buffers, there will be open tx slots available in 734 * the descriptor ring, go try to start some new output. 735 */ 736 if (retired_buffer) { 737 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 738 ffec_txstart_locked(sc); 739 } 740 741 /* If there are no buffers outstanding, muzzle the watchdog. */ 742 if (sc->tx_idx_tail == sc->tx_idx_head) { 743 sc->tx_watchdog_count = 0; 744 } 745 } 746 747 inline static uint32_t 748 ffec_setup_rxdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr) 749 { 750 uint32_t nidx; 751 752 /* 753 * The hardware requires 32-bit physical addresses. We set up the dma 754 * tag to indicate that, so the cast to uint32_t should never lose 755 * significant bits. 756 */ 757 nidx = next_rxidx(sc, idx); 758 sc->rxdesc_ring[idx].buf_paddr = (uint32_t)paddr; 759 sc->rxdesc_ring[idx].flags_len = FEC_RXDESC_EMPTY | 760 ((nidx == 0) ? FEC_RXDESC_WRAP : 0); 761 762 return (nidx); 763 } 764 765 static int 766 ffec_setup_rxbuf(struct ffec_softc *sc, int idx, struct mbuf * m) 767 { 768 int error, nsegs; 769 struct bus_dma_segment seg; 770 771 if (!(sc->fecflags & FECFLAG_RACC)) { 772 /* 773 * The RACC[SHIFT16] feature is not available. So, we need to 774 * leave at least ETHER_ALIGN bytes free at the beginning of the 775 * buffer to allow the data to be re-aligned after receiving it 776 * (by copying it backwards ETHER_ALIGN bytes in the same 777 * buffer). We also have to ensure that the beginning of the 778 * buffer is aligned to the hardware's requirements. 779 */ 780 m_adj(m, roundup(ETHER_ALIGN, sc->rxbuf_align)); 781 } 782 783 error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 784 m, &seg, &nsegs, 0); 785 if (error != 0) { 786 return (error); 787 } 788 789 bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 790 BUS_DMASYNC_PREREAD); 791 792 sc->rxbuf_map[idx].mbuf = m; 793 ffec_setup_rxdesc(sc, idx, seg.ds_addr); 794 795 return (0); 796 } 797 798 static struct mbuf * 799 ffec_alloc_mbufcl(struct ffec_softc *sc) 800 { 801 struct mbuf *m; 802 803 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 804 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 805 806 return (m); 807 } 808 809 static void 810 ffec_rxfinish_onebuf(struct ffec_softc *sc, int len) 811 { 812 struct mbuf *m, *newmbuf; 813 struct ffec_bufmap *bmap; 814 uint8_t *dst, *src; 815 int error; 816 817 /* 818 * First try to get a new mbuf to plug into this slot in the rx ring. 819 * If that fails, drop the current packet and recycle the current 820 * mbuf, which is still mapped and loaded. 821 */ 822 if ((newmbuf = ffec_alloc_mbufcl(sc)) == NULL) { 823 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, 1); 824 ffec_setup_rxdesc(sc, sc->rx_idx, 825 sc->rxdesc_ring[sc->rx_idx].buf_paddr); 826 return; 827 } 828 829 FFEC_UNLOCK(sc); 830 831 bmap = &sc->rxbuf_map[sc->rx_idx]; 832 len -= ETHER_CRC_LEN; 833 bus_dmamap_sync(sc->rxbuf_tag, bmap->map, BUS_DMASYNC_POSTREAD); 834 bus_dmamap_unload(sc->rxbuf_tag, bmap->map); 835 m = bmap->mbuf; 836 bmap->mbuf = NULL; 837 m->m_len = len; 838 m->m_pkthdr.len = len; 839 m->m_pkthdr.rcvif = sc->ifp; 840 841 /* 842 * Align the protocol headers in the receive buffer on a 32-bit 843 * boundary. Newer hardware does the alignment for us. On hardware 844 * that doesn't support this feature, we have to copy-align the data. 845 * 846 * XXX for older hardware, could we speed this up by copying just the 847 * protocol headers into their own small mbuf then chaining the cluster 848 * to it? That way we'd only need to copy like 64 bytes or whatever the 849 * biggest header is, instead of the whole 1530ish-byte frame. 850 */ 851 if (sc->fecflags & FECFLAG_RACC) { 852 m->m_data = mtod(m, uint8_t *) + 2; 853 } else { 854 src = mtod(m, uint8_t*); 855 dst = src - ETHER_ALIGN; 856 bcopy(src, dst, len); 857 m->m_data = dst; 858 } 859 sc->ifp->if_input(sc->ifp, m); 860 861 FFEC_LOCK(sc); 862 863 if ((error = ffec_setup_rxbuf(sc, sc->rx_idx, newmbuf)) != 0) { 864 device_printf(sc->dev, "ffec_setup_rxbuf error %d\n", error); 865 /* XXX Now what? We've got a hole in the rx ring. */ 866 } 867 868 } 869 870 static void 871 ffec_rxfinish_locked(struct ffec_softc *sc) 872 { 873 struct ffec_hwdesc *desc; 874 int len; 875 boolean_t produced_empty_buffer; 876 877 FFEC_ASSERT_LOCKED(sc); 878 879 /* XXX Can't set PRE|POST right now, but we need both. */ 880 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_PREREAD); 881 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_POSTREAD); 882 produced_empty_buffer = false; 883 for (;;) { 884 desc = &sc->rxdesc_ring[sc->rx_idx]; 885 if (desc->flags_len & FEC_RXDESC_EMPTY) 886 break; 887 produced_empty_buffer = true; 888 len = (desc->flags_len & FEC_RXDESC_LEN_MASK); 889 if (len < 64) { 890 /* 891 * Just recycle the descriptor and continue. . 892 */ 893 ffec_setup_rxdesc(sc, sc->rx_idx, 894 sc->rxdesc_ring[sc->rx_idx].buf_paddr); 895 } else if ((desc->flags_len & FEC_RXDESC_L) == 0) { 896 /* 897 * The entire frame is not in this buffer. Impossible. 898 * Recycle the descriptor and continue. 899 * 900 * XXX what's the right way to handle this? Probably we 901 * should stop/init the hardware because this should 902 * just really never happen when we have buffers bigger 903 * than the maximum frame size. 904 */ 905 device_printf(sc->dev, 906 "fec_rxfinish: received frame without LAST bit set"); 907 ffec_setup_rxdesc(sc, sc->rx_idx, 908 sc->rxdesc_ring[sc->rx_idx].buf_paddr); 909 } else if (desc->flags_len & FEC_RXDESC_ERROR_BITS) { 910 /* 911 * Something went wrong with receiving the frame, we 912 * don't care what (the hardware has counted the error 913 * in the stats registers already), we just reuse the 914 * same mbuf, which is still dma-mapped, by resetting 915 * the rx descriptor. 916 */ 917 ffec_setup_rxdesc(sc, sc->rx_idx, 918 sc->rxdesc_ring[sc->rx_idx].buf_paddr); 919 } else { 920 /* 921 * Normal case: a good frame all in one buffer. 922 */ 923 ffec_rxfinish_onebuf(sc, len); 924 } 925 sc->rx_idx = next_rxidx(sc, sc->rx_idx); 926 } 927 928 if (produced_empty_buffer) { 929 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_PREWRITE); 930 WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR); 931 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_POSTWRITE); 932 } 933 } 934 935 static void 936 ffec_get_hwaddr(struct ffec_softc *sc, uint8_t *hwaddr) 937 { 938 uint32_t palr, paur, rnd; 939 940 /* 941 * Try to recover a MAC address from the running hardware. If there's 942 * something non-zero there, assume the bootloader did the right thing 943 * and just use it. 944 * 945 * Otherwise, set the address to a convenient locally assigned address, 946 * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally 947 * assigned bit set, and the broadcast/multicast bit clear. 948 */ 949 palr = RD4(sc, FEC_PALR_REG); 950 paur = RD4(sc, FEC_PAUR_REG) & FEC_PAUR_PADDR2_MASK; 951 if ((palr | paur) != 0) { 952 hwaddr[0] = palr >> 24; 953 hwaddr[1] = palr >> 16; 954 hwaddr[2] = palr >> 8; 955 hwaddr[3] = palr >> 0; 956 hwaddr[4] = paur >> 24; 957 hwaddr[5] = paur >> 16; 958 } else { 959 rnd = arc4random() & 0x00ffffff; 960 hwaddr[0] = 'b'; 961 hwaddr[1] = 's'; 962 hwaddr[2] = 'd'; 963 hwaddr[3] = rnd >> 16; 964 hwaddr[4] = rnd >> 8; 965 hwaddr[5] = rnd >> 0; 966 } 967 968 if (bootverbose) { 969 device_printf(sc->dev, 970 "MAC address %02x:%02x:%02x:%02x:%02x:%02x:\n", 971 hwaddr[0], hwaddr[1], hwaddr[2], 972 hwaddr[3], hwaddr[4], hwaddr[5]); 973 } 974 } 975 976 static void 977 ffec_setup_rxfilter(struct ffec_softc *sc) 978 { 979 struct ifnet *ifp; 980 struct ifmultiaddr *ifma; 981 uint8_t *eaddr; 982 uint32_t crc; 983 uint64_t ghash, ihash; 984 985 FFEC_ASSERT_LOCKED(sc); 986 987 ifp = sc->ifp; 988 989 /* 990 * Set the multicast (group) filter hash. 991 */ 992 if ((ifp->if_flags & IFF_ALLMULTI)) 993 ghash = 0xffffffffffffffffLLU; 994 else { 995 ghash = 0; 996 if_maddr_rlock(ifp); 997 TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) { 998 if (ifma->ifma_addr->sa_family != AF_LINK) 999 continue; 1000 /* 6 bits from MSB in LE CRC32 are used for hash. */ 1001 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 1002 ifma->ifma_addr), ETHER_ADDR_LEN); 1003 ghash |= 1LLU << (((uint8_t *)&crc)[3] >> 2); 1004 } 1005 if_maddr_runlock(ifp); 1006 } 1007 WR4(sc, FEC_GAUR_REG, (uint32_t)(ghash >> 32)); 1008 WR4(sc, FEC_GALR_REG, (uint32_t)ghash); 1009 1010 /* 1011 * Set the individual address filter hash. 1012 * 1013 * XXX Is 0 the right value when promiscuous is off? This hw feature 1014 * seems to support the concept of MAC address aliases, does such a 1015 * thing even exist? 1016 */ 1017 if ((ifp->if_flags & IFF_PROMISC)) 1018 ihash = 0xffffffffffffffffLLU; 1019 else { 1020 ihash = 0; 1021 } 1022 WR4(sc, FEC_IAUR_REG, (uint32_t)(ihash >> 32)); 1023 WR4(sc, FEC_IALR_REG, (uint32_t)ihash); 1024 1025 /* 1026 * Set the primary address. 1027 */ 1028 eaddr = IF_LLADDR(ifp); 1029 WR4(sc, FEC_PALR_REG, (eaddr[0] << 24) | (eaddr[1] << 16) | 1030 (eaddr[2] << 8) | eaddr[3]); 1031 WR4(sc, FEC_PAUR_REG, (eaddr[4] << 24) | (eaddr[5] << 16)); 1032 } 1033 1034 static void 1035 ffec_stop_locked(struct ffec_softc *sc) 1036 { 1037 struct ifnet *ifp; 1038 struct ffec_hwdesc *desc; 1039 struct ffec_bufmap *bmap; 1040 int idx; 1041 1042 FFEC_ASSERT_LOCKED(sc); 1043 1044 ifp = sc->ifp; 1045 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1046 sc->tx_watchdog_count = 0; 1047 1048 /* 1049 * Stop the hardware, mask all interrupts, and clear all current 1050 * interrupt status bits. 1051 */ 1052 WR4(sc, FEC_ECR_REG, RD4(sc, FEC_ECR_REG) & ~FEC_ECR_ETHEREN); 1053 WR4(sc, FEC_IEM_REG, 0x00000000); 1054 WR4(sc, FEC_IER_REG, 0xffffffff); 1055 1056 /* 1057 * Stop the media-check callout. Do not use callout_drain() because 1058 * we're holding a mutex the callout acquires, and if it's currently 1059 * waiting to acquire it, we'd deadlock. If it is waiting now, the 1060 * ffec_tick() routine will return without doing anything when it sees 1061 * that IFF_DRV_RUNNING is not set, so avoiding callout_drain() is safe. 1062 */ 1063 callout_stop(&sc->ffec_callout); 1064 1065 /* 1066 * Discard all untransmitted buffers. Each buffer is simply freed; 1067 * it's as if the bits were transmitted and then lost on the wire. 1068 * 1069 * XXX Is this right? Or should we use IFQ_DRV_PREPEND() to put them 1070 * back on the queue for when we get restarted later? 1071 */ 1072 idx = sc->tx_idx_tail; 1073 while (idx != sc->tx_idx_head) { 1074 desc = &sc->txdesc_ring[idx]; 1075 bmap = &sc->txbuf_map[idx]; 1076 if (desc->buf_paddr != 0) { 1077 bus_dmamap_unload(sc->txbuf_tag, bmap->map); 1078 m_freem(bmap->mbuf); 1079 bmap->mbuf = NULL; 1080 ffec_setup_txdesc(sc, idx, 0, 0); 1081 } 1082 idx = next_txidx(sc, idx); 1083 } 1084 1085 /* 1086 * Discard all unprocessed receive buffers. This amounts to just 1087 * pretending that nothing ever got received into them. We reuse the 1088 * mbuf already mapped for each desc, simply turning the EMPTY flags 1089 * back on so they'll get reused when we start up again. 1090 */ 1091 for (idx = 0; idx < RX_DESC_COUNT; ++idx) { 1092 desc = &sc->rxdesc_ring[idx]; 1093 ffec_setup_rxdesc(sc, idx, desc->buf_paddr); 1094 } 1095 } 1096 1097 static void 1098 ffec_init_locked(struct ffec_softc *sc) 1099 { 1100 struct ifnet *ifp = sc->ifp; 1101 uint32_t maxbuf, maxfl, regval; 1102 1103 FFEC_ASSERT_LOCKED(sc); 1104 1105 /* 1106 * The hardware has a limit of 0x7ff as the max frame length (see 1107 * comments for MRBR below), and we use mbuf clusters as receive 1108 * buffers, and we currently are designed to receive an entire frame 1109 * into a single buffer. 1110 * 1111 * We start with a MCLBYTES-sized cluster, but we have to offset into 1112 * the buffer by ETHER_ALIGN to make room for post-receive re-alignment, 1113 * and then that value has to be rounded up to the hardware's DMA 1114 * alignment requirements, so all in all our buffer is that much smaller 1115 * than MCLBYTES. 1116 * 1117 * The resulting value is used as the frame truncation length and the 1118 * max buffer receive buffer size for now. It'll become more complex 1119 * when we support jumbo frames and receiving fragments of them into 1120 * separate buffers. 1121 */ 1122 maxbuf = MCLBYTES - roundup(ETHER_ALIGN, sc->rxbuf_align); 1123 maxfl = min(maxbuf, 0x7ff); 1124 1125 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1126 return; 1127 1128 /* Mask all interrupts and clear all current interrupt status bits. */ 1129 WR4(sc, FEC_IEM_REG, 0x00000000); 1130 WR4(sc, FEC_IER_REG, 0xffffffff); 1131 1132 /* 1133 * Go set up palr/puar, galr/gaur, ialr/iaur. 1134 */ 1135 ffec_setup_rxfilter(sc); 1136 1137 /* 1138 * TFWR - Transmit FIFO watermark register. 1139 * 1140 * Set the transmit fifo watermark register to "store and forward" mode 1141 * and also set a threshold of 128 bytes in the fifo before transmission 1142 * of a frame begins (to avoid dma underruns). Recent FEC hardware 1143 * supports STRFWD and when that bit is set, the watermark level in the 1144 * low bits is ignored. Older hardware doesn't have STRFWD, but writing 1145 * to that bit is innocuous, and the TWFR bits get used instead. 1146 */ 1147 WR4(sc, FEC_TFWR_REG, FEC_TFWR_STRFWD | FEC_TFWR_TWFR_128BYTE); 1148 1149 /* RCR - Receive control register. 1150 * 1151 * Set max frame length + clean out anything left from u-boot. 1152 */ 1153 WR4(sc, FEC_RCR_REG, (maxfl << FEC_RCR_MAX_FL_SHIFT)); 1154 1155 /* 1156 * TCR - Transmit control register. 1157 * 1158 * Clean out anything left from u-boot. Any necessary values are set in 1159 * ffec_miibus_statchg() based on the media type. 1160 */ 1161 WR4(sc, FEC_TCR_REG, 0); 1162 1163 /* 1164 * OPD - Opcode/pause duration. 1165 * 1166 * XXX These magic numbers come from u-boot. 1167 */ 1168 WR4(sc, FEC_OPD_REG, 0x00010020); 1169 1170 /* 1171 * FRSR - Fifo receive start register. 1172 * 1173 * This register does not exist on imx6, it is present on earlier 1174 * hardware. The u-boot code sets this to a non-default value that's 32 1175 * bytes larger than the default, with no clue as to why. The default 1176 * value should work fine, so there's no code to init it here. 1177 */ 1178 1179 /* 1180 * MRBR - Max RX buffer size. 1181 * 1182 * Note: For hardware prior to imx6 this value cannot exceed 0x07ff, 1183 * but the datasheet says no such thing for imx6. On the imx6, setting 1184 * this to 2K without setting EN1588 resulted in a crazy runaway 1185 * receive loop in the hardware, where every rx descriptor in the ring 1186 * had its EMPTY flag cleared, no completion or error flags set, and a 1187 * length of zero. I think maybe you can only exceed it when EN1588 is 1188 * set, like maybe that's what enables jumbo frames, because in general 1189 * the EN1588 flag seems to be the "enable new stuff" vs. "be legacy- 1190 * compatible" flag. 1191 */ 1192 WR4(sc, FEC_MRBR_REG, maxfl << FEC_MRBR_R_BUF_SIZE_SHIFT); 1193 1194 /* 1195 * FTRL - Frame truncation length. 1196 * 1197 * Must be greater than or equal to the value set in FEC_RCR_MAXFL. 1198 */ 1199 WR4(sc, FEC_FTRL_REG, maxfl); 1200 1201 /* 1202 * RDSR / TDSR descriptor ring pointers. 1203 * 1204 * When we turn on ECR_ETHEREN at the end, the hardware zeroes its 1205 * internal current descriptor index values for both rings, so we zero 1206 * our index values as well. 1207 */ 1208 sc->rx_idx = 0; 1209 sc->tx_idx_head = sc->tx_idx_tail = 0; 1210 sc->txcount = 0; 1211 WR4(sc, FEC_RDSR_REG, sc->rxdesc_ring_paddr); 1212 WR4(sc, FEC_TDSR_REG, sc->txdesc_ring_paddr); 1213 1214 /* 1215 * EIM - interrupt mask register. 1216 * 1217 * We always enable the same set of interrupts while running; unlike 1218 * some drivers there's no need to change the mask on the fly depending 1219 * on what operations are in progress. 1220 */ 1221 WR4(sc, FEC_IEM_REG, FEC_IER_TXF | FEC_IER_RXF | FEC_IER_EBERR); 1222 1223 /* 1224 * MIBC - MIB control (hardware stats); clear all statistics regs, then 1225 * enable collection of statistics. 1226 */ 1227 regval = RD4(sc, FEC_MIBC_REG); 1228 WR4(sc, FEC_MIBC_REG, regval | FEC_MIBC_DIS); 1229 ffec_clear_stats(sc); 1230 WR4(sc, FEC_MIBC_REG, regval & ~FEC_MIBC_DIS); 1231 1232 if (sc->fecflags & FECFLAG_RACC) { 1233 /* 1234 * RACC - Receive Accelerator Function Configuration. 1235 */ 1236 regval = RD4(sc, FEC_RACC_REG); 1237 WR4(sc, FEC_RACC_REG, regval | FEC_RACC_SHIFT16); 1238 } 1239 1240 /* 1241 * ECR - Ethernet control register. 1242 * 1243 * This must happen after all the other config registers are set. If 1244 * we're running on little-endian hardware, also set the flag for byte- 1245 * swapping descriptor ring entries. This flag doesn't exist on older 1246 * hardware, but it can be safely set -- the bit position it occupies 1247 * was unused. 1248 */ 1249 regval = RD4(sc, FEC_ECR_REG); 1250 #if _BYTE_ORDER == _LITTLE_ENDIAN 1251 regval |= FEC_ECR_DBSWP; 1252 #endif 1253 regval |= FEC_ECR_ETHEREN; 1254 WR4(sc, FEC_ECR_REG, regval); 1255 1256 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1257 1258 /* 1259 * Call mii_mediachg() which will call back into ffec_miibus_statchg() to 1260 * set up the remaining config registers based on the current media. 1261 */ 1262 mii_mediachg(sc->mii_softc); 1263 callout_reset(&sc->ffec_callout, hz, ffec_tick, sc); 1264 1265 /* 1266 * Tell the hardware that receive buffers are available. They were made 1267 * available in ffec_attach() or ffec_stop(). 1268 */ 1269 WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR); 1270 } 1271 1272 static void 1273 ffec_init(void *if_softc) 1274 { 1275 struct ffec_softc *sc = if_softc; 1276 1277 FFEC_LOCK(sc); 1278 ffec_init_locked(sc); 1279 FFEC_UNLOCK(sc); 1280 } 1281 1282 static void 1283 ffec_intr(void *arg) 1284 { 1285 struct ffec_softc *sc; 1286 uint32_t ier; 1287 1288 sc = arg; 1289 1290 FFEC_LOCK(sc); 1291 1292 ier = RD4(sc, FEC_IER_REG); 1293 1294 if (ier & FEC_IER_TXF) { 1295 WR4(sc, FEC_IER_REG, FEC_IER_TXF); 1296 ffec_txfinish_locked(sc); 1297 } 1298 1299 if (ier & FEC_IER_RXF) { 1300 WR4(sc, FEC_IER_REG, FEC_IER_RXF); 1301 ffec_rxfinish_locked(sc); 1302 } 1303 1304 /* 1305 * We actually don't care about most errors, because the hardware copes 1306 * with them just fine, discarding the incoming bad frame, or forcing a 1307 * bad CRC onto an outgoing bad frame, and counting the errors in the 1308 * stats registers. The one that really matters is EBERR (DMA bus 1309 * error) because the hardware automatically clears ECR[ETHEREN] and we 1310 * have to restart it here. It should never happen. 1311 */ 1312 if (ier & FEC_IER_EBERR) { 1313 WR4(sc, FEC_IER_REG, FEC_IER_EBERR); 1314 device_printf(sc->dev, 1315 "Ethernet DMA error, restarting controller.\n"); 1316 ffec_stop_locked(sc); 1317 ffec_init_locked(sc); 1318 } 1319 1320 FFEC_UNLOCK(sc); 1321 1322 } 1323 1324 static int 1325 ffec_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1326 { 1327 struct ffec_softc *sc; 1328 struct mii_data *mii; 1329 struct ifreq *ifr; 1330 int mask, error; 1331 1332 sc = ifp->if_softc; 1333 ifr = (struct ifreq *)data; 1334 1335 error = 0; 1336 switch (cmd) { 1337 case SIOCSIFFLAGS: 1338 FFEC_LOCK(sc); 1339 if (ifp->if_flags & IFF_UP) { 1340 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1341 if ((ifp->if_flags ^ sc->if_flags) & 1342 (IFF_PROMISC | IFF_ALLMULTI)) 1343 ffec_setup_rxfilter(sc); 1344 } else { 1345 if (!sc->is_detaching) 1346 ffec_init_locked(sc); 1347 } 1348 } else { 1349 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1350 ffec_stop_locked(sc); 1351 } 1352 sc->if_flags = ifp->if_flags; 1353 FFEC_UNLOCK(sc); 1354 break; 1355 1356 case SIOCADDMULTI: 1357 case SIOCDELMULTI: 1358 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1359 FFEC_LOCK(sc); 1360 ffec_setup_rxfilter(sc); 1361 FFEC_UNLOCK(sc); 1362 } 1363 break; 1364 1365 case SIOCSIFMEDIA: 1366 case SIOCGIFMEDIA: 1367 mii = sc->mii_softc; 1368 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1369 break; 1370 1371 case SIOCSIFCAP: 1372 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 1373 if (mask & IFCAP_VLAN_MTU) { 1374 /* No work to do except acknowledge the change took. */ 1375 ifp->if_capenable ^= IFCAP_VLAN_MTU; 1376 } 1377 break; 1378 1379 default: 1380 error = ether_ioctl(ifp, cmd, data); 1381 break; 1382 } 1383 1384 return (error); 1385 } 1386 1387 static int 1388 ffec_detach(device_t dev) 1389 { 1390 struct ffec_softc *sc; 1391 bus_dmamap_t map; 1392 int idx, irq; 1393 1394 /* 1395 * NB: This function can be called internally to unwind a failure to 1396 * attach. Make sure a resource got allocated/created before destroying. 1397 */ 1398 1399 sc = device_get_softc(dev); 1400 1401 if (sc->is_attached) { 1402 FFEC_LOCK(sc); 1403 sc->is_detaching = true; 1404 ffec_stop_locked(sc); 1405 FFEC_UNLOCK(sc); 1406 callout_drain(&sc->ffec_callout); 1407 ether_ifdetach(sc->ifp); 1408 } 1409 1410 /* XXX no miibus detach? */ 1411 1412 /* Clean up RX DMA resources and free mbufs. */ 1413 for (idx = 0; idx < RX_DESC_COUNT; ++idx) { 1414 if ((map = sc->rxbuf_map[idx].map) != NULL) { 1415 bus_dmamap_unload(sc->rxbuf_tag, map); 1416 bus_dmamap_destroy(sc->rxbuf_tag, map); 1417 m_freem(sc->rxbuf_map[idx].mbuf); 1418 } 1419 } 1420 if (sc->rxbuf_tag != NULL) 1421 bus_dma_tag_destroy(sc->rxbuf_tag); 1422 if (sc->rxdesc_map != NULL) { 1423 bus_dmamap_unload(sc->rxdesc_tag, sc->rxdesc_map); 1424 bus_dmamap_destroy(sc->rxdesc_tag, sc->rxdesc_map); 1425 } 1426 if (sc->rxdesc_tag != NULL) 1427 bus_dma_tag_destroy(sc->rxdesc_tag); 1428 1429 /* Clean up TX DMA resources. */ 1430 for (idx = 0; idx < TX_DESC_COUNT; ++idx) { 1431 if ((map = sc->txbuf_map[idx].map) != NULL) { 1432 /* TX maps are already unloaded. */ 1433 bus_dmamap_destroy(sc->txbuf_tag, map); 1434 } 1435 } 1436 if (sc->txbuf_tag != NULL) 1437 bus_dma_tag_destroy(sc->txbuf_tag); 1438 if (sc->txdesc_map != NULL) { 1439 bus_dmamap_unload(sc->txdesc_tag, sc->txdesc_map); 1440 bus_dmamap_destroy(sc->txdesc_tag, sc->txdesc_map); 1441 } 1442 if (sc->txdesc_tag != NULL) 1443 bus_dma_tag_destroy(sc->txdesc_tag); 1444 1445 /* Release bus resources. */ 1446 for (irq = 0; irq < MAX_IRQ_COUNT; ++irq) { 1447 if (sc->intr_cookie[irq] != NULL) { 1448 bus_teardown_intr(dev, sc->irq_res[irq], 1449 sc->intr_cookie[irq]); 1450 } 1451 } 1452 bus_release_resources(dev, irq_res_spec, sc->irq_res); 1453 1454 if (sc->mem_res != NULL) 1455 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 1456 1457 FFEC_LOCK_DESTROY(sc); 1458 return (0); 1459 } 1460 1461 static int 1462 ffec_attach(device_t dev) 1463 { 1464 struct ffec_softc *sc; 1465 struct ifnet *ifp = NULL; 1466 struct mbuf *m; 1467 void *dummy; 1468 uintptr_t typeflags; 1469 phandle_t ofw_node; 1470 uint32_t idx, mscr; 1471 int error, phynum, rid, irq; 1472 uint8_t eaddr[ETHER_ADDR_LEN]; 1473 1474 sc = device_get_softc(dev); 1475 sc->dev = dev; 1476 1477 FFEC_LOCK_INIT(sc); 1478 1479 /* 1480 * There are differences in the implementation and features of the FEC 1481 * hardware on different SoCs, so figure out what type we are. 1482 */ 1483 typeflags = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 1484 sc->fectype = (uint8_t)(typeflags & FECTYPE_MASK); 1485 sc->fecflags = (uint32_t)(typeflags & ~FECTYPE_MASK); 1486 1487 if (sc->fecflags & FECFLAG_AVB) { 1488 sc->rxbuf_align = 64; 1489 sc->txbuf_align = 1; 1490 } else { 1491 sc->rxbuf_align = 16; 1492 sc->txbuf_align = 16; 1493 } 1494 1495 /* 1496 * We have to be told what kind of electrical connection exists between 1497 * the MAC and PHY or we can't operate correctly. 1498 */ 1499 if ((ofw_node = ofw_bus_get_node(dev)) == -1) { 1500 device_printf(dev, "Impossible: Can't find ofw bus node\n"); 1501 error = ENXIO; 1502 goto out; 1503 } 1504 sc->phy_conn_type = mii_fdt_get_contype(ofw_node); 1505 if (sc->phy_conn_type == MII_CONTYPE_UNKNOWN) { 1506 device_printf(sc->dev, "No valid 'phy-mode' " 1507 "property found in FDT data for device.\n"); 1508 error = ENOATTR; 1509 goto out; 1510 } 1511 1512 callout_init_mtx(&sc->ffec_callout, &sc->mtx, 0); 1513 1514 /* Allocate bus resources for accessing the hardware. */ 1515 rid = 0; 1516 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1517 RF_ACTIVE); 1518 if (sc->mem_res == NULL) { 1519 device_printf(dev, "could not allocate memory resources.\n"); 1520 error = ENOMEM; 1521 goto out; 1522 } 1523 1524 error = bus_alloc_resources(dev, irq_res_spec, sc->irq_res); 1525 if (error != 0) { 1526 device_printf(dev, "could not allocate interrupt resources\n"); 1527 goto out; 1528 } 1529 1530 /* 1531 * Set up TX descriptor ring, descriptors, and dma maps. 1532 */ 1533 error = bus_dma_tag_create( 1534 bus_get_dma_tag(dev), /* Parent tag. */ 1535 FEC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 1536 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1537 BUS_SPACE_MAXADDR, /* highaddr */ 1538 NULL, NULL, /* filter, filterarg */ 1539 TX_DESC_SIZE, 1, /* maxsize, nsegments */ 1540 TX_DESC_SIZE, /* maxsegsize */ 1541 0, /* flags */ 1542 NULL, NULL, /* lockfunc, lockarg */ 1543 &sc->txdesc_tag); 1544 if (error != 0) { 1545 device_printf(sc->dev, 1546 "could not create TX ring DMA tag.\n"); 1547 goto out; 1548 } 1549 1550 error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring, 1551 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->txdesc_map); 1552 if (error != 0) { 1553 device_printf(sc->dev, 1554 "could not allocate TX descriptor ring.\n"); 1555 goto out; 1556 } 1557 1558 error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map, sc->txdesc_ring, 1559 TX_DESC_SIZE, ffec_get1paddr, &sc->txdesc_ring_paddr, 0); 1560 if (error != 0) { 1561 device_printf(sc->dev, 1562 "could not load TX descriptor ring map.\n"); 1563 goto out; 1564 } 1565 1566 error = bus_dma_tag_create( 1567 bus_get_dma_tag(dev), /* Parent tag. */ 1568 sc->txbuf_align, 0, /* alignment, boundary */ 1569 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1570 BUS_SPACE_MAXADDR, /* highaddr */ 1571 NULL, NULL, /* filter, filterarg */ 1572 MCLBYTES, 1, /* maxsize, nsegments */ 1573 MCLBYTES, /* maxsegsize */ 1574 0, /* flags */ 1575 NULL, NULL, /* lockfunc, lockarg */ 1576 &sc->txbuf_tag); 1577 if (error != 0) { 1578 device_printf(sc->dev, 1579 "could not create TX ring DMA tag.\n"); 1580 goto out; 1581 } 1582 1583 for (idx = 0; idx < TX_DESC_COUNT; ++idx) { 1584 error = bus_dmamap_create(sc->txbuf_tag, 0, 1585 &sc->txbuf_map[idx].map); 1586 if (error != 0) { 1587 device_printf(sc->dev, 1588 "could not create TX buffer DMA map.\n"); 1589 goto out; 1590 } 1591 ffec_setup_txdesc(sc, idx, 0, 0); 1592 } 1593 1594 /* 1595 * Set up RX descriptor ring, descriptors, dma maps, and mbufs. 1596 */ 1597 error = bus_dma_tag_create( 1598 bus_get_dma_tag(dev), /* Parent tag. */ 1599 FEC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 1600 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1601 BUS_SPACE_MAXADDR, /* highaddr */ 1602 NULL, NULL, /* filter, filterarg */ 1603 RX_DESC_SIZE, 1, /* maxsize, nsegments */ 1604 RX_DESC_SIZE, /* maxsegsize */ 1605 0, /* flags */ 1606 NULL, NULL, /* lockfunc, lockarg */ 1607 &sc->rxdesc_tag); 1608 if (error != 0) { 1609 device_printf(sc->dev, 1610 "could not create RX ring DMA tag.\n"); 1611 goto out; 1612 } 1613 1614 error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring, 1615 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->rxdesc_map); 1616 if (error != 0) { 1617 device_printf(sc->dev, 1618 "could not allocate RX descriptor ring.\n"); 1619 goto out; 1620 } 1621 1622 error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map, sc->rxdesc_ring, 1623 RX_DESC_SIZE, ffec_get1paddr, &sc->rxdesc_ring_paddr, 0); 1624 if (error != 0) { 1625 device_printf(sc->dev, 1626 "could not load RX descriptor ring map.\n"); 1627 goto out; 1628 } 1629 1630 error = bus_dma_tag_create( 1631 bus_get_dma_tag(dev), /* Parent tag. */ 1632 1, 0, /* alignment, boundary */ 1633 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1634 BUS_SPACE_MAXADDR, /* highaddr */ 1635 NULL, NULL, /* filter, filterarg */ 1636 MCLBYTES, 1, /* maxsize, nsegments */ 1637 MCLBYTES, /* maxsegsize */ 1638 0, /* flags */ 1639 NULL, NULL, /* lockfunc, lockarg */ 1640 &sc->rxbuf_tag); 1641 if (error != 0) { 1642 device_printf(sc->dev, 1643 "could not create RX buf DMA tag.\n"); 1644 goto out; 1645 } 1646 1647 for (idx = 0; idx < RX_DESC_COUNT; ++idx) { 1648 error = bus_dmamap_create(sc->rxbuf_tag, 0, 1649 &sc->rxbuf_map[idx].map); 1650 if (error != 0) { 1651 device_printf(sc->dev, 1652 "could not create RX buffer DMA map.\n"); 1653 goto out; 1654 } 1655 if ((m = ffec_alloc_mbufcl(sc)) == NULL) { 1656 device_printf(dev, "Could not alloc mbuf\n"); 1657 error = ENOMEM; 1658 goto out; 1659 } 1660 if ((error = ffec_setup_rxbuf(sc, idx, m)) != 0) { 1661 device_printf(sc->dev, 1662 "could not create new RX buffer.\n"); 1663 goto out; 1664 } 1665 } 1666 1667 /* Try to get the MAC address from the hardware before resetting it. */ 1668 ffec_get_hwaddr(sc, eaddr); 1669 1670 /* 1671 * Reset the hardware. Disables all interrupts. 1672 * 1673 * When the FEC is connected to the AXI bus (indicated by AVB flag), a 1674 * MAC reset while a bus transaction is pending can hang the bus. 1675 * Instead of resetting, turn off the ENABLE bit, which allows the 1676 * hardware to complete any in-progress transfers (appending a bad CRC 1677 * to any partial packet) and release the AXI bus. This could probably 1678 * be done unconditionally for all hardware variants, but that hasn't 1679 * been tested. 1680 */ 1681 if (sc->fecflags & FECFLAG_AVB) 1682 WR4(sc, FEC_ECR_REG, 0); 1683 else 1684 WR4(sc, FEC_ECR_REG, FEC_ECR_RESET); 1685 1686 /* Setup interrupt handler. */ 1687 for (irq = 0; irq < MAX_IRQ_COUNT; ++irq) { 1688 if (sc->irq_res[irq] != NULL) { 1689 error = bus_setup_intr(dev, sc->irq_res[irq], 1690 INTR_TYPE_NET | INTR_MPSAFE, NULL, ffec_intr, sc, 1691 &sc->intr_cookie[irq]); 1692 if (error != 0) { 1693 device_printf(dev, 1694 "could not setup interrupt handler.\n"); 1695 goto out; 1696 } 1697 } 1698 } 1699 1700 /* 1701 * Set up the PHY control register. 1702 * 1703 * Speed formula for ENET is md_clock = mac_clock / ((N + 1) * 2). 1704 * Speed formula for FEC is md_clock = mac_clock / (N * 2) 1705 * 1706 * XXX - Revisit this... 1707 * 1708 * For a Wandboard imx6 (ENET) I was originally using 4, but the uboot 1709 * code uses 10. Both values seem to work, but I suspect many modern 1710 * PHY parts can do mdio at speeds far above the standard 2.5 MHz. 1711 * 1712 * Different imx manuals use confusingly different terminology (things 1713 * like "system clock" and "internal module clock") with examples that 1714 * use frequencies that have nothing to do with ethernet, giving the 1715 * vague impression that maybe the clock in question is the periphclock 1716 * or something. In fact, on an imx53 development board (FEC), 1717 * measuring the mdio clock at the pin on the PHY and playing with 1718 * various divisors showed that the root speed was 66 MHz (clk_ipg_root 1719 * aka periphclock) and 13 was the right divisor. 1720 * 1721 * All in all, it seems likely that 13 is a safe divisor for now, 1722 * because if we really do need to base it on the peripheral clock 1723 * speed, then we need a platform-independant get-clock-freq API. 1724 */ 1725 mscr = 13 << FEC_MSCR_MII_SPEED_SHIFT; 1726 if (OF_hasprop(ofw_node, "phy-disable-preamble")) { 1727 mscr |= FEC_MSCR_DIS_PRE; 1728 if (bootverbose) 1729 device_printf(dev, "PHY preamble disabled\n"); 1730 } 1731 WR4(sc, FEC_MSCR_REG, mscr); 1732 1733 /* Set up the ethernet interface. */ 1734 sc->ifp = ifp = if_alloc(IFT_ETHER); 1735 1736 ifp->if_softc = sc; 1737 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1738 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1739 ifp->if_capabilities = IFCAP_VLAN_MTU; 1740 ifp->if_capenable = ifp->if_capabilities; 1741 ifp->if_start = ffec_txstart; 1742 ifp->if_ioctl = ffec_ioctl; 1743 ifp->if_init = ffec_init; 1744 IFQ_SET_MAXLEN(&ifp->if_snd, TX_DESC_COUNT - 1); 1745 ifp->if_snd.ifq_drv_maxlen = TX_DESC_COUNT - 1; 1746 IFQ_SET_READY(&ifp->if_snd); 1747 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 1748 1749 #if 0 /* XXX The hardware keeps stats we could use for these. */ 1750 ifp->if_linkmib = &sc->mibdata; 1751 ifp->if_linkmiblen = sizeof(sc->mibdata); 1752 #endif 1753 1754 /* Set up the miigasket hardware (if any). */ 1755 ffec_miigasket_setup(sc); 1756 1757 /* Attach the mii driver. */ 1758 if (fdt_get_phyaddr(ofw_node, dev, &phynum, &dummy) != 0) { 1759 phynum = MII_PHY_ANY; 1760 } 1761 error = mii_attach(dev, &sc->miibus, ifp, ffec_media_change, 1762 ffec_media_status, BMSR_DEFCAPMASK, phynum, MII_OFFSET_ANY, 1763 (sc->fecflags & FECTYPE_MVF) ? MIIF_FORCEANEG : 0); 1764 if (error != 0) { 1765 device_printf(dev, "PHY attach failed\n"); 1766 goto out; 1767 } 1768 sc->mii_softc = device_get_softc(sc->miibus); 1769 1770 /* All ready to run, attach the ethernet interface. */ 1771 ether_ifattach(ifp, eaddr); 1772 sc->is_attached = true; 1773 1774 error = 0; 1775 out: 1776 1777 if (error != 0) 1778 ffec_detach(dev); 1779 1780 return (error); 1781 } 1782 1783 static int 1784 ffec_probe(device_t dev) 1785 { 1786 uintptr_t fectype; 1787 1788 if (!ofw_bus_status_okay(dev)) 1789 return (ENXIO); 1790 1791 fectype = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 1792 if (fectype == FECTYPE_NONE) 1793 return (ENXIO); 1794 1795 device_set_desc(dev, (fectype & FECFLAG_GBE) ? 1796 "Freescale Gigabit Ethernet Controller" : 1797 "Freescale Fast Ethernet Controller"); 1798 1799 return (BUS_PROBE_DEFAULT); 1800 } 1801 1802 1803 static device_method_t ffec_methods[] = { 1804 /* Device interface. */ 1805 DEVMETHOD(device_probe, ffec_probe), 1806 DEVMETHOD(device_attach, ffec_attach), 1807 DEVMETHOD(device_detach, ffec_detach), 1808 1809 /* 1810 DEVMETHOD(device_shutdown, ffec_shutdown), 1811 DEVMETHOD(device_suspend, ffec_suspend), 1812 DEVMETHOD(device_resume, ffec_resume), 1813 */ 1814 1815 /* MII interface. */ 1816 DEVMETHOD(miibus_readreg, ffec_miibus_readreg), 1817 DEVMETHOD(miibus_writereg, ffec_miibus_writereg), 1818 DEVMETHOD(miibus_statchg, ffec_miibus_statchg), 1819 1820 DEVMETHOD_END 1821 }; 1822 1823 static driver_t ffec_driver = { 1824 "ffec", 1825 ffec_methods, 1826 sizeof(struct ffec_softc) 1827 }; 1828 1829 static devclass_t ffec_devclass; 1830 1831 DRIVER_MODULE(ffec, simplebus, ffec_driver, ffec_devclass, 0, 0); 1832 DRIVER_MODULE(miibus, ffec, miibus_driver, miibus_devclass, 0, 0); 1833 1834 MODULE_DEPEND(ffec, ether, 1, 1, 1); 1835 MODULE_DEPEND(ffec, miibus, 1, 1, 1); 1836