1718cf2ccSPedro F. Giffuni /*- 24d846d26SWarner Losh * SPDX-License-Identifier: BSD-2-Clause 3718cf2ccSPedro F. Giffuni * 4d2bd3ab9SScott Long * Copyright (c) 2004-2005 MARVELL SEMICONDUCTOR ISRAEL, LTD. 51713e81bSScott Long * All rights reserved. 61713e81bSScott Long * 71713e81bSScott Long * Redistribution and use in source and binary forms, with or without 81713e81bSScott Long * modification, are permitted provided that the following conditions 91713e81bSScott Long * are met: 101713e81bSScott Long * 1. Redistributions of source code must retain the above copyright 111713e81bSScott Long * notice, this list of conditions and the following disclaimer. 121713e81bSScott Long * 2. Redistributions in binary form must reproduce the above copyright 131713e81bSScott Long * notice, this list of conditions and the following disclaimer in the 141713e81bSScott Long * documentation and/or other materials provided with the distribution. 151713e81bSScott Long * 161713e81bSScott Long * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 171713e81bSScott Long * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 181713e81bSScott Long * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 191713e81bSScott Long * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 201713e81bSScott Long * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 211713e81bSScott Long * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 221713e81bSScott Long * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 231713e81bSScott Long * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 241713e81bSScott Long * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 251713e81bSScott Long * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 261713e81bSScott Long * SUCH DAMAGE. 27f7f3900bSScott Long */ 281713e81bSScott Long #ifndef __INCmvStorageDevh 291713e81bSScott Long #define __INCmvStorageDevh 301713e81bSScott Long 311713e81bSScott Long /* Definitions */ 321713e81bSScott Long 331713e81bSScott Long /* ATA register on the ATA drive*/ 341713e81bSScott Long 351713e81bSScott Long #define MV_EDMA_ATA_FEATURES_ADDR 0x11 361713e81bSScott Long #define MV_EDMA_ATA_SECTOR_COUNT_ADDR 0x12 371713e81bSScott Long #define MV_EDMA_ATA_LBA_LOW_ADDR 0x13 381713e81bSScott Long #define MV_EDMA_ATA_LBA_MID_ADDR 0x14 391713e81bSScott Long #define MV_EDMA_ATA_LBA_HIGH_ADDR 0x15 401713e81bSScott Long #define MV_EDMA_ATA_DEVICE_ADDR 0x16 411713e81bSScott Long #define MV_EDMA_ATA_COMMAND_ADDR 0x17 421713e81bSScott Long 431713e81bSScott Long #define MV_ATA_ERROR_STATUS 0x00000001 /* MV_BIT0 */ 441713e81bSScott Long #define MV_ATA_DATA_REQUEST_STATUS 0x00000008 /* MV_BIT3 */ 451713e81bSScott Long #define MV_ATA_SERVICE_STATUS 0x00000010 /* MV_BIT4 */ 461713e81bSScott Long #define MV_ATA_DEVICE_FAULT_STATUS 0x00000020 /* MV_BIT5 */ 471713e81bSScott Long #define MV_ATA_READY_STATUS 0x00000040 /* MV_BIT6 */ 481713e81bSScott Long #define MV_ATA_BUSY_STATUS 0x00000080 /* MV_BIT7 */ 491713e81bSScott Long 501713e81bSScott Long 511713e81bSScott Long #define MV_ATA_COMMAND_READ_SECTORS 0x20 521713e81bSScott Long #define MV_ATA_COMMAND_READ_SECTORS_EXT 0x24 531713e81bSScott Long #define MV_ATA_COMMAND_READ_VERIFY_SECTORS 0x40 541713e81bSScott Long #define MV_ATA_COMMAND_READ_VERIFY_SECTORS_EXT 0x42 551713e81bSScott Long #define MV_ATA_COMMAND_READ_BUFFER 0xE4 561713e81bSScott Long #define MV_ATA_COMMAND_WRITE_BUFFER 0xE8 571713e81bSScott Long #define MV_ATA_COMMAND_WRITE_SECTORS 0x30 581713e81bSScott Long #define MV_ATA_COMMAND_WRITE_SECTORS_EXT 0x34 591713e81bSScott Long #define MV_ATA_COMMAND_DIAGNOSTIC 0x90 601713e81bSScott Long #define MV_ATA_COMMAND_SMART 0xb0 611713e81bSScott Long #define MV_ATA_COMMAND_READ_MULTIPLE 0xc4 621713e81bSScott Long #define MV_ATA_COMMAND_WRITE_MULTIPLE 0xc5 631713e81bSScott Long #define MV_ATA_COMMAND_STANDBY_IMMEDIATE 0xe0 641713e81bSScott Long #define MV_ATA_COMMAND_IDLE_IMMEDIATE 0xe1 651713e81bSScott Long #define MV_ATA_COMMAND_STANDBY 0xe2 661713e81bSScott Long #define MV_ATA_COMMAND_IDLE 0xe3 671713e81bSScott Long #define MV_ATA_COMMAND_SLEEP 0xe6 681713e81bSScott Long #define MV_ATA_COMMAND_IDENTIFY 0xec 691713e81bSScott Long #define MV_ATA_COMMAND_DEVICE_CONFIG 0xb1 701713e81bSScott Long #define MV_ATA_COMMAND_SET_FEATURES 0xef 711713e81bSScott Long #define MV_ATA_COMMAND_WRITE_DMA 0xca 721713e81bSScott Long #define MV_ATA_COMMAND_WRITE_DMA_EXT 0x35 731713e81bSScott Long #define MV_ATA_COMMAND_WRITE_DMA_QUEUED 0xcc 741713e81bSScott Long #define MV_ATA_COMMAND_WRITE_DMA_QUEUED_EXT 0x36 751713e81bSScott Long #define MV_ATA_COMMAND_WRITE_FPDMA_QUEUED_EXT 0x61 761713e81bSScott Long #define MV_ATA_COMMAND_READ_DMA 0xc8 771713e81bSScott Long #define MV_ATA_COMMAND_READ_DMA_EXT 0x25 781713e81bSScott Long #define MV_ATA_COMMAND_READ_DMA_QUEUED 0xc7 791713e81bSScott Long #define MV_ATA_COMMAND_READ_DMA_QUEUED_EXT 0x26 801713e81bSScott Long #define MV_ATA_COMMAND_READ_FPDMA_QUEUED_EXT 0x60 811713e81bSScott Long #define MV_ATA_COMMAND_FLUSH_CACHE 0xe7 821713e81bSScott Long #define MV_ATA_COMMAND_FLUSH_CACHE_EXT 0xea 831713e81bSScott Long 841713e81bSScott Long 851713e81bSScott Long #define MV_ATA_SET_FEATURES_DISABLE_8_BIT_PIO 0x01 861713e81bSScott Long #define MV_ATA_SET_FEATURES_ENABLE_WCACHE 0x02 /* Enable write cache */ 871713e81bSScott Long #define MV_ATA_SET_FEATURES_TRANSFER 0x03 /* Set transfer mode */ 881713e81bSScott Long #define MV_ATA_TRANSFER_UDMA_0 0x40 891713e81bSScott Long #define MV_ATA_TRANSFER_UDMA_1 0x41 901713e81bSScott Long #define MV_ATA_TRANSFER_UDMA_2 0x42 911713e81bSScott Long #define MV_ATA_TRANSFER_UDMA_3 0x43 921713e81bSScott Long #define MV_ATA_TRANSFER_UDMA_4 0x44 931713e81bSScott Long #define MV_ATA_TRANSFER_UDMA_5 0x45 941713e81bSScott Long #define MV_ATA_TRANSFER_UDMA_6 0x46 951713e81bSScott Long #define MV_ATA_TRANSFER_UDMA_7 0x47 961713e81bSScott Long #define MV_ATA_TRANSFER_PIO_SLOW 0x00 971713e81bSScott Long #define MV_ATA_TRANSFER_PIO_0 0x08 981713e81bSScott Long #define MV_ATA_TRANSFER_PIO_1 0x09 991713e81bSScott Long #define MV_ATA_TRANSFER_PIO_2 0x0A 1001713e81bSScott Long #define MV_ATA_TRANSFER_PIO_3 0x0B 1011713e81bSScott Long #define MV_ATA_TRANSFER_PIO_4 0x0C 1021713e81bSScott Long /* Enable advanced power management */ 1031713e81bSScott Long #define MV_ATA_SET_FEATURES_ENABLE_APM 0x05 1041713e81bSScott Long /* Disable media status notification*/ 1051713e81bSScott Long #define MV_ATA_SET_FEATURES_DISABLE_MSN 0x31 1061713e81bSScott Long /* Disable read look-ahead */ 1071713e81bSScott Long #define MV_ATA_SET_FEATURES_DISABLE_RLA 0x55 1081713e81bSScott Long /* Enable release interrupt */ 1091713e81bSScott Long #define MV_ATA_SET_FEATURES_ENABLE_RI 0x5D 1101713e81bSScott Long /* Enable SERVICE interrupt */ 1111713e81bSScott Long #define MV_ATA_SET_FEATURES_ENABLE_SI 0x5E 1121713e81bSScott Long /* Disable revert power-on defaults */ 1131713e81bSScott Long #define MV_ATA_SET_FEATURES_DISABLE_RPOD 0x66 1141713e81bSScott Long /* Disable write cache */ 1151713e81bSScott Long #define MV_ATA_SET_FEATURES_DISABLE_WCACHE 0x82 1161713e81bSScott Long /* Disable advanced power management*/ 1171713e81bSScott Long #define MV_ATA_SET_FEATURES_DISABLE_APM 0x85 1181713e81bSScott Long /* Enable media status notification */ 1191713e81bSScott Long #define MV_ATA_SET_FEATURES_ENABLE_MSN 0x95 1201713e81bSScott Long /* Enable read look-ahead */ 1211713e81bSScott Long #define MV_ATA_SET_FEATURES_ENABLE_RLA 0xAA 1221713e81bSScott Long /* Enable revert power-on defaults */ 1231713e81bSScott Long #define MV_ATA_SET_FEATURES_ENABLE_RPOD 0xCC 1241713e81bSScott Long /* Disable release interrupt */ 1251713e81bSScott Long #define MV_ATA_SET_FEATURES_DISABLE_RI 0xDD 1261713e81bSScott Long /* Disable SERVICE interrupt */ 1271713e81bSScott Long #define MV_ATA_SET_FEATURES_DISABLE_SI 0xDE 1281713e81bSScott Long 1291713e81bSScott Long /* Defines for parsing the IDENTIFY command results*/ 1301713e81bSScott Long #define IDEN_SERIAL_NUM_OFFSET 10 1311713e81bSScott Long #define IDEN_SERIAL_NUM_SIZE 19-10 1321713e81bSScott Long #define IDEN_FIRMWARE_OFFSET 23 1331713e81bSScott Long #define IDEN_FIRMWARE_SIZE 26-23 1341713e81bSScott Long #define IDEN_MODEL_OFFSET 27 1351713e81bSScott Long #define IDEN_MODEL_SIZE 46-27 1361713e81bSScott Long #define IDEN_CAPACITY_1_OFFSET 49 1371713e81bSScott Long #define IDEN_VALID 53 1381713e81bSScott Long #define IDEN_NUM_OF_ADDRESSABLE_SECTORS 60 1391713e81bSScott Long #define IDEN_PIO_MODE_SPPORTED 64 1401713e81bSScott Long #define IDEN_QUEUE_DEPTH 75 1411713e81bSScott Long #define IDEN_SATA_CAPABILITIES 76 1421713e81bSScott Long #define IDEN_SATA_FEATURES_SUPPORTED 78 1431713e81bSScott Long #define IDEN_SATA_FEATURES_ENABLED 79 1441713e81bSScott Long #define IDEN_ATA_VERSION 80 1451713e81bSScott Long #define IDEN_SUPPORTED_COMMANDS1 82 1461713e81bSScott Long #define IDEN_SUPPORTED_COMMANDS2 83 1471713e81bSScott Long #define IDEN_ENABLED_COMMANDS1 85 1481713e81bSScott Long #define IDEN_ENABLED_COMMANDS2 86 1491713e81bSScott Long #define IDEN_UDMA_MODE 88 1501713e81bSScott Long #define IDEN_SATA_CAPABILITY 76 1511713e81bSScott Long 1521713e81bSScott Long 1531713e81bSScott Long /* Typedefs */ 1541713e81bSScott Long 1551713e81bSScott Long /* Structures */ 1561713e81bSScott Long typedef struct mvStorageDevRegisters 1571713e81bSScott Long { 1581713e81bSScott Long /* Fields set by CORE driver */ 1591713e81bSScott Long MV_U8 errorRegister; 1601713e81bSScott Long MV_U16 sectorCountRegister; 1611713e81bSScott Long MV_U16 lbaLowRegister; 1621713e81bSScott Long MV_U16 lbaMidRegister; 1631713e81bSScott Long MV_U16 lbaHighRegister; 1641713e81bSScott Long MV_U8 deviceRegister; 1651713e81bSScott Long MV_U8 statusRegister; 1661713e81bSScott Long } MV_STORAGE_DEVICE_REGISTERS; 1671713e81bSScott Long 1681713e81bSScott Long /* Bits for HD_ERROR */ 1691713e81bSScott Long #define NM_ERR 0x02 /* media present */ 1701713e81bSScott Long #define ABRT_ERR 0x04 /* Command aborted */ 1711713e81bSScott Long #define MCR_ERR 0x08 /* media change request */ 1721713e81bSScott Long #define IDNF_ERR 0x10 /* ID field not found */ 1731713e81bSScott Long #define MC_ERR 0x20 /* media changed */ 1741713e81bSScott Long #define UNC_ERR 0x40 /* Uncorrect data */ 1751713e81bSScott Long #define WP_ERR 0x40 /* write protect */ 1761713e81bSScott Long #define ICRC_ERR 0x80 /* new meaning: CRC error during transfer */ 1771713e81bSScott Long 1781713e81bSScott Long /* Function */ 1791713e81bSScott Long 1801713e81bSScott Long MV_BOOLEAN HPTLIBAPI mvStorageDevATAExecuteNonUDMACommand(MV_SATA_ADAPTER *pAdapter, 1811713e81bSScott Long MV_U8 channelIndex, 1821713e81bSScott Long MV_NON_UDMA_PROTOCOL protocolType, 1831713e81bSScott Long MV_BOOLEAN isEXT, 1841713e81bSScott Long MV_U16 FAR *bufPtr, MV_U32 count, 1851713e81bSScott Long MV_U16 features, 1861713e81bSScott Long MV_U16 sectorCount, 1871713e81bSScott Long MV_U16 lbaLow, MV_U16 lbaMid, 1881713e81bSScott Long MV_U16 lbaHigh, MV_U8 device, 1891713e81bSScott Long MV_U8 command); 1901713e81bSScott Long 1911713e81bSScott Long MV_BOOLEAN HPTLIBAPI mvStorageDevATAIdentifyDevice(MV_SATA_ADAPTER *pAdapter, 1921713e81bSScott Long MV_U8 channelIndex); 1931713e81bSScott Long 1941713e81bSScott Long MV_BOOLEAN HPTLIBAPI mvStorageDevATASetFeatures(MV_SATA_ADAPTER *pAdapter, 1951713e81bSScott Long MV_U8 channelIndex, MV_U8 subCommand, 1961713e81bSScott Long MV_U8 subCommandSpecific1, 1971713e81bSScott Long MV_U8 subCommandSpecific2, 1981713e81bSScott Long MV_U8 subCommandSpecific3, 1991713e81bSScott Long MV_U8 subCommandSpecific4); 2001713e81bSScott Long 2011713e81bSScott Long MV_BOOLEAN HPTLIBAPI mvStorageDevATAIdleImmediate(MV_SATA_ADAPTER *pAdapter, 2021713e81bSScott Long MV_U8 channelIndex); 2031713e81bSScott Long 2041713e81bSScott Long MV_BOOLEAN HPTLIBAPI mvStorageDevATAFlushWriteCache(MV_SATA_ADAPTER *pAdapter, 2051713e81bSScott Long MV_U8 channelIndex); 2061713e81bSScott Long 2071713e81bSScott Long MV_BOOLEAN HPTLIBAPI mvStorageDevATASoftResetDevice(MV_SATA_ADAPTER *pAdapter, 2081713e81bSScott Long MV_U8 channelIndex); 2091713e81bSScott Long 21064470755SXin LI MV_BOOLEAN HPTLIBAPI mvStorageDevWaitStat(MV_SATA_CHANNEL *pSataChannel, 21164470755SXin LI MV_U8 good, MV_U8 bad, MV_U32 loops, MV_U32 delay); 21264470755SXin LI 2131713e81bSScott Long MV_BOOLEAN HPTLIBAPI mvReadWrite(MV_SATA_CHANNEL *pSataChannel, LBA_T Lba, UCHAR Cmd, void *tmpBuffer); 2141713e81bSScott Long 2151713e81bSScott Long #endif 216