1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright (c) 2023, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /*$FreeBSD$*/ 32 33 #ifndef _ICE_TYPE_H_ 34 #define _ICE_TYPE_H_ 35 36 #include "ice_defs.h" 37 #include "ice_status.h" 38 #include "ice_hw_autogen.h" 39 #include "ice_devids.h" 40 #include "ice_osdep.h" 41 #include "ice_bitops.h" /* Must come before ice_controlq.h */ 42 #include "ice_lan_tx_rx.h" 43 #include "ice_ddp_common.h" 44 #include "ice_controlq.h" 45 #include "ice_flex_type.h" 46 #include "ice_protocol_type.h" 47 #include "ice_vlan_mode.h" 48 #include "ice_fwlog.h" 49 50 static inline bool ice_is_tc_ena(ice_bitmap_t bitmap, u8 tc) 51 { 52 return !!(bitmap & BIT(tc)); 53 } 54 55 /** 56 * DIV_S64 - Divide signed 64-bit value with signed 64-bit divisor 57 * @dividend: value to divide 58 * @divisor: value to divide by 59 * 60 * Use DIV_S64 for any 64-bit divide which operates on signed 64-bit dividends. 61 * Do not use this for unsigned 64-bit dividends as it will not produce 62 * correct results if the dividend is larger than S64_MAX. 63 */ 64 static inline s64 DIV_S64(s64 dividend, s64 divisor) 65 { 66 return dividend / divisor; 67 } 68 69 /** 70 * DIV_U64 - Divide unsigned 64-bit value by unsigned 64-bit divisor 71 * @dividend: value to divide 72 * @divisor: value to divide by 73 * 74 * Use DIV_U64 for any 64-bit divide which operates on unsigned 64-bit 75 * dividends. Do not use this for signed 64-bit dividends as it will not 76 * handle negative values correctly. 77 */ 78 static inline u64 DIV_U64(u64 dividend, u64 divisor) 79 { 80 return dividend / divisor; 81 } 82 83 static inline u64 round_up_64bit(u64 a, u32 b) 84 { 85 return DIV_U64(((a) + (b) / 2), (b)); 86 } 87 88 static inline u32 ice_round_to_num(u32 N, u32 R) 89 { 90 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) : 91 ((((N) + (R) - 1) / (R)) * (R))); 92 } 93 94 /* Driver always calls main vsi_handle first */ 95 #define ICE_MAIN_VSI_HANDLE 0 96 97 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */ 98 #define ICE_MS_TO_GTIME(time) ((time) * 1000) 99 100 /* Data type manipulation macros. */ 101 #define ICE_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF)) 102 #define ICE_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF)) 103 #define ICE_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF)) 104 #define ICE_LO_WORD(x) ((u16)((x) & 0xFFFF)) 105 #define ICE_HI_BYTE(x) ((u8)(((x) >> 8) & 0xFF)) 106 #define ICE_LO_BYTE(x) ((u8)((x) & 0xFF)) 107 108 /* debug masks - set these bits in hw->debug_mask to control output */ 109 #define ICE_DBG_TRACE BIT_ULL(0) /* for function-trace only */ 110 #define ICE_DBG_INIT BIT_ULL(1) 111 #define ICE_DBG_RELEASE BIT_ULL(2) 112 #define ICE_DBG_FW_LOG BIT_ULL(3) 113 #define ICE_DBG_LINK BIT_ULL(4) 114 #define ICE_DBG_PHY BIT_ULL(5) 115 #define ICE_DBG_QCTX BIT_ULL(6) 116 #define ICE_DBG_NVM BIT_ULL(7) 117 #define ICE_DBG_LAN BIT_ULL(8) 118 #define ICE_DBG_FLOW BIT_ULL(9) 119 #define ICE_DBG_DCB BIT_ULL(10) 120 #define ICE_DBG_DIAG BIT_ULL(11) 121 #define ICE_DBG_FD BIT_ULL(12) 122 #define ICE_DBG_SW BIT_ULL(13) 123 #define ICE_DBG_SCHED BIT_ULL(14) 124 125 #define ICE_DBG_RDMA BIT_ULL(15) 126 #define ICE_DBG_PKG BIT_ULL(16) 127 #define ICE_DBG_RES BIT_ULL(17) 128 #define ICE_DBG_AQ_MSG BIT_ULL(24) 129 #define ICE_DBG_AQ_DESC BIT_ULL(25) 130 #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26) 131 #define ICE_DBG_AQ_CMD BIT_ULL(27) 132 #define ICE_DBG_AQ (ICE_DBG_AQ_MSG | \ 133 ICE_DBG_AQ_DESC | \ 134 ICE_DBG_AQ_DESC_BUF | \ 135 ICE_DBG_AQ_CMD) 136 #define ICE_DBG_PARSER BIT_ULL(28) 137 138 #define ICE_DBG_USER BIT_ULL(31) 139 #define ICE_DBG_ALL 0xFFFFFFFFFFFFFFFFULL 140 141 #define IS_UNICAST_ETHER_ADDR(addr) \ 142 ((bool)((((u8 *)(addr))[0] % ((u8)0x2)) == 0)) 143 144 #define IS_MULTICAST_ETHER_ADDR(addr) \ 145 ((bool)((((u8 *)(addr))[0] % ((u8)0x2)) == 1)) 146 147 /* Check whether an address is broadcast. */ 148 #define IS_BROADCAST_ETHER_ADDR(addr) \ 149 ((bool)((((u16 *)(addr))[0] == ((u16)0xffff)))) 150 151 #define IS_ZERO_ETHER_ADDR(addr) \ 152 (((bool)((((u16 *)(addr))[0] == ((u16)0x0)))) && \ 153 ((bool)((((u16 *)(addr))[1] == ((u16)0x0)))) && \ 154 ((bool)((((u16 *)(addr))[2] == ((u16)0x0))))) 155 156 #ifndef IS_ETHER_ADDR_EQUAL 157 #define IS_ETHER_ADDR_EQUAL(addr1, addr2) \ 158 (((bool)((((u16 *)(addr1))[0] == ((u16 *)(addr2))[0]))) && \ 159 ((bool)((((u16 *)(addr1))[1] == ((u16 *)(addr2))[1]))) && \ 160 ((bool)((((u16 *)(addr1))[2] == ((u16 *)(addr2))[2])))) 161 #endif 162 163 enum ice_aq_res_ids { 164 ICE_NVM_RES_ID = 1, 165 ICE_SPD_RES_ID, 166 ICE_CHANGE_LOCK_RES_ID, 167 ICE_GLOBAL_CFG_LOCK_RES_ID 168 }; 169 170 /* FW update timeout definitions are in milliseconds */ 171 #define ICE_NVM_TIMEOUT 180000 172 #define ICE_CHANGE_LOCK_TIMEOUT 1000 173 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 3000 174 175 struct ice_driver_ver { 176 u8 major_ver; 177 u8 minor_ver; 178 u8 build_ver; 179 u8 subbuild_ver; 180 u8 driver_string[32]; 181 }; 182 183 enum ice_fc_mode { 184 ICE_FC_NONE = 0, 185 ICE_FC_RX_PAUSE, 186 ICE_FC_TX_PAUSE, 187 ICE_FC_FULL, 188 ICE_FC_AUTO, 189 ICE_FC_PFC, 190 ICE_FC_DFLT 191 }; 192 193 enum ice_phy_cache_mode { 194 ICE_FC_MODE = 0, 195 ICE_SPEED_MODE, 196 ICE_FEC_MODE 197 }; 198 199 enum ice_fec_mode { 200 ICE_FEC_NONE = 0, 201 ICE_FEC_RS, 202 ICE_FEC_BASER, 203 ICE_FEC_AUTO, 204 ICE_FEC_DIS_AUTO 205 }; 206 207 struct ice_phy_cache_mode_data { 208 union { 209 enum ice_fec_mode curr_user_fec_req; 210 enum ice_fc_mode curr_user_fc_req; 211 u16 curr_user_speed_req; 212 } data; 213 }; 214 215 enum ice_set_fc_aq_failures { 216 ICE_SET_FC_AQ_FAIL_NONE = 0, 217 ICE_SET_FC_AQ_FAIL_GET, 218 ICE_SET_FC_AQ_FAIL_SET, 219 ICE_SET_FC_AQ_FAIL_UPDATE 220 }; 221 222 /* These are structs for managing the hardware information and the operations */ 223 /* MAC types */ 224 enum ice_mac_type { 225 ICE_MAC_UNKNOWN = 0, 226 ICE_MAC_VF, 227 ICE_MAC_E810, 228 ICE_MAC_GENERIC, 229 ICE_MAC_GENERIC_3K, 230 }; 231 232 /* Media Types */ 233 enum ice_media_type { 234 ICE_MEDIA_UNKNOWN = 0, 235 ICE_MEDIA_FIBER, 236 ICE_MEDIA_BASET, 237 ICE_MEDIA_BACKPLANE, 238 ICE_MEDIA_DA, 239 ICE_MEDIA_AUI, 240 }; 241 242 /* Software VSI types. */ 243 enum ice_vsi_type { 244 ICE_VSI_PF = 0, 245 ICE_VSI_VF = 1, 246 ICE_VSI_LB = 6, 247 }; 248 249 struct ice_link_status { 250 /* Refer to ice_aq_phy_type for bits definition */ 251 u64 phy_type_low; 252 u64 phy_type_high; 253 u8 topo_media_conflict; 254 u16 max_frame_size; 255 u16 link_speed; 256 u16 req_speeds; 257 u8 link_cfg_err; 258 u8 lse_ena; /* Link Status Event notification */ 259 u8 link_info; 260 u8 an_info; 261 u8 ext_info; 262 u8 fec_info; 263 u8 pacing; 264 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of 265 * ice_aqc_get_phy_caps structure 266 */ 267 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 268 }; 269 270 /* Different data queue types: These are mainly for SW consumption. */ 271 enum ice_q { 272 ICE_DATA_Q_DOORBELL, 273 ICE_DATA_Q_CMPL, 274 ICE_DATA_Q_QUANTA, 275 ICE_DATA_Q_RX, 276 ICE_DATA_Q_TX, 277 }; 278 279 /* Different reset sources for which a disable queue AQ call has to be made in 280 * order to clean the Tx scheduler as a part of the reset 281 */ 282 enum ice_disq_rst_src { 283 ICE_NO_RESET = 0, 284 ICE_VM_RESET, 285 ICE_VF_RESET, 286 }; 287 288 /* PHY info such as phy_type, etc... */ 289 struct ice_phy_info { 290 struct ice_link_status link_info; 291 struct ice_link_status link_info_old; 292 u64 phy_type_low; 293 u64 phy_type_high; 294 enum ice_media_type media_type; 295 u8 get_link_info; 296 /* Please refer to struct ice_aqc_get_link_status_data to get 297 * detail of enable bit in curr_user_speed_req 298 */ 299 u16 curr_user_speed_req; 300 enum ice_fec_mode curr_user_fec_req; 301 enum ice_fc_mode curr_user_fc_req; 302 struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg; 303 }; 304 305 #define ICE_MAX_NUM_MIRROR_RULES 64 306 307 #define ICE_L2TPV2_FLAGS_CTRL 0x8000 308 #define ICE_L2TPV2_FLAGS_LEN 0x4000 309 #define ICE_L2TPV2_FLAGS_SEQ 0x0800 310 #define ICE_L2TPV2_FLAGS_OFF 0x0200 311 #define ICE_L2TPV2_FLAGS_VER 0x0002 312 313 #define ICE_L2TPV2_PKT_LENGTH 6 314 #define ICE_PPP_PKT_LENGTH 4 315 316 /* Common HW capabilities for SW use */ 317 struct ice_hw_common_caps { 318 /* Write CSR protection */ 319 u64 wr_csr_prot; 320 u32 switching_mode; 321 /* switching mode supported - EVB switching (including cloud) */ 322 #define ICE_NVM_IMAGE_TYPE_EVB 0x0 323 324 /* Manageablity mode & supported protocols over MCTP */ 325 u32 mgmt_mode; 326 #define ICE_MGMT_MODE_PASS_THRU_MODE_M 0xF 327 #define ICE_MGMT_MODE_CTL_INTERFACE_M 0xF0 328 #define ICE_MGMT_MODE_REDIR_SB_INTERFACE_M 0xF00 329 330 u32 mgmt_protocols_mctp; 331 #define ICE_MGMT_MODE_PROTO_RSVD BIT(0) 332 #define ICE_MGMT_MODE_PROTO_PLDM BIT(1) 333 #define ICE_MGMT_MODE_PROTO_OEM BIT(2) 334 #define ICE_MGMT_MODE_PROTO_NC_SI BIT(3) 335 336 u32 os2bmc; 337 u32 valid_functions; 338 /* DCB capabilities */ 339 u32 active_tc_bitmap; 340 u32 maxtc; 341 342 /* RSS related capabilities */ 343 u32 rss_table_size; /* 512 for PFs and 64 for VFs */ 344 u32 rss_table_entry_width; /* RSS Entry width in bits */ 345 346 /* Tx/Rx queues */ 347 u32 num_rxq; /* Number/Total Rx queues */ 348 u32 rxq_first_id; /* First queue ID for Rx queues */ 349 u32 num_txq; /* Number/Total Tx queues */ 350 u32 txq_first_id; /* First queue ID for Tx queues */ 351 352 /* MSI-X vectors */ 353 u32 num_msix_vectors; 354 u32 msix_vector_first_id; 355 356 /* Max MTU for function or device */ 357 u32 max_mtu; 358 359 /* WOL related */ 360 u32 num_wol_proxy_fltr; 361 u32 wol_proxy_vsi_seid; 362 363 /* LED/SDP pin count */ 364 u32 led_pin_num; 365 u32 sdp_pin_num; 366 367 /* LED/SDP - Supports up to 12 LED pins and 8 SDP signals */ 368 #define ICE_MAX_SUPPORTED_GPIO_LED 12 369 #define ICE_MAX_SUPPORTED_GPIO_SDP 8 370 u8 led[ICE_MAX_SUPPORTED_GPIO_LED]; 371 u8 sdp[ICE_MAX_SUPPORTED_GPIO_SDP]; 372 373 /* SR-IOV virtualization */ 374 u8 sr_iov_1_1; /* SR-IOV enabled */ 375 376 /* EVB capabilities */ 377 u8 evb_802_1_qbg; /* Edge Virtual Bridging */ 378 u8 evb_802_1_qbh; /* Bridge Port Extension */ 379 380 u8 dcb; 381 u8 iscsi; 382 u8 mgmt_cem; 383 u8 iwarp; 384 u8 roce_lag; 385 386 /* WoL and APM support */ 387 #define ICE_WOL_SUPPORT_M BIT(0) 388 #define ICE_ACPI_PROG_MTHD_M BIT(1) 389 #define ICE_PROXY_SUPPORT_M BIT(2) 390 u8 apm_wol_support; 391 u8 acpi_prog_mthd; 392 u8 proxy_support; 393 bool sec_rev_disabled; 394 bool update_disabled; 395 bool nvm_unified_update; 396 #define ICE_NVM_MGMT_SEC_REV_DISABLED BIT(0) 397 #define ICE_NVM_MGMT_UPDATE_DISABLED BIT(1) 398 #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3) 399 /* PCIe reset avoidance */ 400 bool pcie_reset_avoidance; /* false: not supported, true: supported */ 401 /* Post update reset restriction */ 402 bool reset_restrict_support; /* false: not supported, true: supported */ 403 404 /* External topology device images within the NVM */ 405 #define ICE_EXT_TOPO_DEV_IMG_COUNT 4 406 u32 ext_topo_dev_img_ver_high[ICE_EXT_TOPO_DEV_IMG_COUNT]; 407 u32 ext_topo_dev_img_ver_low[ICE_EXT_TOPO_DEV_IMG_COUNT]; 408 u8 ext_topo_dev_img_part_num[ICE_EXT_TOPO_DEV_IMG_COUNT]; 409 #define ICE_EXT_TOPO_DEV_IMG_PART_NUM_S 8 410 #define ICE_EXT_TOPO_DEV_IMG_PART_NUM_M \ 411 MAKEMASK(0xFF, ICE_EXT_TOPO_DEV_IMG_PART_NUM_S) 412 bool ext_topo_dev_img_load_en[ICE_EXT_TOPO_DEV_IMG_COUNT]; 413 #define ICE_EXT_TOPO_DEV_IMG_LOAD_EN BIT(0) 414 bool ext_topo_dev_img_prog_en[ICE_EXT_TOPO_DEV_IMG_COUNT]; 415 #define ICE_EXT_TOPO_DEV_IMG_PROG_EN BIT(1) 416 bool tx_sched_topo_comp_mode_en; 417 bool dyn_flattening_en; 418 }; 419 420 #define ICE_NAC_TOPO_PRIMARY_M BIT(0) 421 #define ICE_NAC_TOPO_DUAL_M BIT(1) 422 #define ICE_NAC_TOPO_ID_M MAKEMASK(0xf, 0) 423 424 struct ice_nac_topology { 425 u32 mode; 426 u8 id; 427 }; 428 429 /* Function specific capabilities */ 430 struct ice_hw_func_caps { 431 struct ice_hw_common_caps common_cap; 432 u32 num_allocd_vfs; /* Number of allocated VFs */ 433 u32 vf_base_id; /* Logical ID of the first VF */ 434 u32 guar_num_vsi; 435 }; 436 437 /* Device wide capabilities */ 438 struct ice_hw_dev_caps { 439 struct ice_hw_common_caps common_cap; 440 u32 num_vfs_exposed; /* Total number of VFs exposed */ 441 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */ 442 u32 num_funcs; 443 struct ice_nac_topology nac_topo; 444 }; 445 446 /* Information about MAC such as address, etc... */ 447 struct ice_mac_info { 448 u8 lan_addr[ETH_ALEN]; 449 u8 perm_addr[ETH_ALEN]; 450 u8 port_addr[ETH_ALEN]; 451 u8 wol_addr[ETH_ALEN]; 452 }; 453 454 /* PCI bus types */ 455 enum ice_bus_type { 456 ice_bus_unknown = 0, 457 ice_bus_pci_express, 458 ice_bus_embedded, /* Is device Embedded versus card */ 459 ice_bus_reserved 460 }; 461 462 /* PCI bus speeds */ 463 enum ice_pcie_bus_speed { 464 ice_pcie_speed_unknown = 0xff, 465 ice_pcie_speed_2_5GT = 0x14, 466 ice_pcie_speed_5_0GT = 0x15, 467 ice_pcie_speed_8_0GT = 0x16, 468 ice_pcie_speed_16_0GT = 0x17 469 }; 470 471 /* PCI bus widths */ 472 enum ice_pcie_link_width { 473 ice_pcie_lnk_width_resrv = 0x00, 474 ice_pcie_lnk_x1 = 0x01, 475 ice_pcie_lnk_x2 = 0x02, 476 ice_pcie_lnk_x4 = 0x04, 477 ice_pcie_lnk_x8 = 0x08, 478 ice_pcie_lnk_x12 = 0x0C, 479 ice_pcie_lnk_x16 = 0x10, 480 ice_pcie_lnk_x32 = 0x20, 481 ice_pcie_lnk_width_unknown = 0xff, 482 }; 483 484 /* Reset types used to determine which kind of reset was requested. These 485 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register. 486 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register 487 * because its reset source is different than the other types listed. 488 */ 489 enum ice_reset_req { 490 ICE_RESET_POR = 0, 491 ICE_RESET_INVAL = 0, 492 ICE_RESET_CORER = 1, 493 ICE_RESET_GLOBR = 2, 494 ICE_RESET_EMPR = 3, 495 ICE_RESET_PFR = 4, 496 }; 497 498 /* Bus parameters */ 499 struct ice_bus_info { 500 enum ice_pcie_bus_speed speed; 501 enum ice_pcie_link_width width; 502 enum ice_bus_type type; 503 u16 domain_num; 504 u16 device; 505 u8 func; 506 u8 bus_num; 507 }; 508 509 /* Flow control (FC) parameters */ 510 struct ice_fc_info { 511 enum ice_fc_mode current_mode; /* FC mode in effect */ 512 enum ice_fc_mode req_mode; /* FC mode requested by caller */ 513 }; 514 515 /* Option ROM version information */ 516 struct ice_orom_info { 517 u8 major; /* Major version of OROM */ 518 u8 patch; /* Patch version of OROM */ 519 u16 build; /* Build version of OROM */ 520 u32 srev; /* Security revision */ 521 }; 522 523 /* NVM version information */ 524 struct ice_nvm_info { 525 u32 eetrack; 526 u32 srev; 527 u8 major; 528 u8 minor; 529 }; 530 531 /* Minimum Security Revision information */ 532 struct ice_minsrev_info { 533 u32 nvm; 534 u32 orom; 535 u8 nvm_valid : 1; 536 u8 orom_valid : 1; 537 }; 538 539 /* netlist version information */ 540 struct ice_netlist_info { 541 u32 major; /* major high/low */ 542 u32 minor; /* minor high/low */ 543 u32 type; /* type high/low */ 544 u32 rev; /* revision high/low */ 545 u32 hash; /* SHA-1 hash word */ 546 u16 cust_ver; /* customer version */ 547 }; 548 549 /* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules 550 * of the flash image. 551 */ 552 enum ice_flash_bank { 553 ICE_INVALID_FLASH_BANK, 554 ICE_1ST_FLASH_BANK, 555 ICE_2ND_FLASH_BANK, 556 }; 557 558 /* Enumeration of which flash bank is desired to read from, either the active 559 * bank or the inactive bank. Used to abstract 1st and 2nd bank notion from 560 * code which just wants to read the active or inactive flash bank. 561 */ 562 enum ice_bank_select { 563 ICE_ACTIVE_FLASH_BANK, 564 ICE_INACTIVE_FLASH_BANK, 565 }; 566 567 /* information for accessing NVM, OROM, and Netlist flash banks */ 568 struct ice_bank_info { 569 u32 nvm_ptr; /* Pointer to 1st NVM bank */ 570 u32 nvm_size; /* Size of NVM bank */ 571 u32 orom_ptr; /* Pointer to 1st OROM bank */ 572 u32 orom_size; /* Size of OROM bank */ 573 u32 netlist_ptr; /* Pointer to 1st Netlist bank */ 574 u32 netlist_size; /* Size of Netlist bank */ 575 enum ice_flash_bank nvm_bank; /* Active NVM bank */ 576 enum ice_flash_bank orom_bank; /* Active OROM bank */ 577 enum ice_flash_bank netlist_bank; /* Active Netlist bank */ 578 }; 579 580 /* Flash Chip Information */ 581 struct ice_flash_info { 582 struct ice_orom_info orom; /* Option ROM version info */ 583 struct ice_nvm_info nvm; /* NVM version information */ 584 struct ice_netlist_info netlist;/* Netlist version info */ 585 struct ice_bank_info banks; /* Flash Bank information */ 586 u16 sr_words; /* Shadow RAM size in words */ 587 u32 flash_size; /* Size of available flash in bytes */ 588 u8 blank_nvm_mode; /* is NVM empty (no FW present) */ 589 }; 590 591 struct ice_link_default_override_tlv { 592 u8 options; 593 #define ICE_LINK_OVERRIDE_OPT_M 0x3F 594 #define ICE_LINK_OVERRIDE_STRICT_MODE BIT(0) 595 #define ICE_LINK_OVERRIDE_EPCT_DIS BIT(1) 596 #define ICE_LINK_OVERRIDE_PORT_DIS BIT(2) 597 #define ICE_LINK_OVERRIDE_EN BIT(3) 598 #define ICE_LINK_OVERRIDE_AUTO_LINK_DIS BIT(4) 599 #define ICE_LINK_OVERRIDE_EEE_EN BIT(5) 600 u8 phy_config; 601 #define ICE_LINK_OVERRIDE_PHY_CFG_S 8 602 #define ICE_LINK_OVERRIDE_PHY_CFG_M (0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S) 603 #define ICE_LINK_OVERRIDE_PAUSE_M 0x3 604 #define ICE_LINK_OVERRIDE_LESM_EN BIT(6) 605 #define ICE_LINK_OVERRIDE_AUTO_FEC_EN BIT(7) 606 u8 fec_options; 607 #define ICE_LINK_OVERRIDE_FEC_OPT_M 0xFF 608 u8 rsvd1; 609 u64 phy_type_low; 610 u64 phy_type_high; 611 }; 612 613 #define ICE_NVM_VER_LEN 32 614 615 /* Max number of port to queue branches w.r.t topology */ 616 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS 617 618 #define ice_for_each_traffic_class(_i) \ 619 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++) 620 621 /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects 622 * to driver defined policy for default aggregator 623 */ 624 #define ICE_INVAL_TEID 0xFFFFFFFF 625 #define ICE_DFLT_AGG_ID 0 626 627 struct ice_sched_node { 628 struct ice_sched_node *parent; 629 struct ice_sched_node *sibling; /* next sibling in the same layer */ 630 struct ice_sched_node **children; 631 struct ice_aqc_txsched_elem_data info; 632 u32 agg_id; /* aggregator group ID */ 633 u16 vsi_handle; 634 u8 in_use; /* suspended or in use */ 635 u8 tx_sched_layer; /* Logical Layer (1-9) */ 636 u8 num_children; 637 u8 tc_num; 638 u8 owner; 639 #define ICE_SCHED_NODE_OWNER_LAN 0 640 #define ICE_SCHED_NODE_OWNER_AE 1 641 #define ICE_SCHED_NODE_OWNER_RDMA 2 642 }; 643 644 /* Access Macros for Tx Sched Elements data */ 645 #define ICE_TXSCHED_GET_NODE_TEID(x) LE32_TO_CPU((x)->info.node_teid) 646 #define ICE_TXSCHED_GET_PARENT_TEID(x) LE32_TO_CPU((x)->info.parent_teid) 647 #define ICE_TXSCHED_GET_CIR_RL_ID(x) \ 648 LE16_TO_CPU((x)->info.cir_bw.bw_profile_idx) 649 #define ICE_TXSCHED_GET_EIR_RL_ID(x) \ 650 LE16_TO_CPU((x)->info.eir_bw.bw_profile_idx) 651 #define ICE_TXSCHED_GET_SRL_ID(x) LE16_TO_CPU((x)->info.srl_id) 652 #define ICE_TXSCHED_GET_CIR_BWALLOC(x) \ 653 LE16_TO_CPU((x)->info.cir_bw.bw_alloc) 654 #define ICE_TXSCHED_GET_EIR_BWALLOC(x) \ 655 LE16_TO_CPU((x)->info.eir_bw.bw_alloc) 656 657 struct ice_sched_rl_profile { 658 u32 rate; /* In Kbps */ 659 struct ice_aqc_rl_profile_elem info; 660 }; 661 662 /* The aggregator type determines if identifier is for a VSI group, 663 * aggregator group, aggregator of queues, or queue group. 664 */ 665 enum ice_agg_type { 666 ICE_AGG_TYPE_UNKNOWN = 0, 667 ICE_AGG_TYPE_TC, 668 ICE_AGG_TYPE_AGG, /* aggregator */ 669 ICE_AGG_TYPE_VSI, 670 ICE_AGG_TYPE_QG, 671 ICE_AGG_TYPE_Q 672 }; 673 674 /* Rate limit types */ 675 enum ice_rl_type { 676 ICE_UNKNOWN_BW = 0, 677 ICE_MIN_BW, /* for CIR profile */ 678 ICE_MAX_BW, /* for EIR profile */ 679 ICE_SHARED_BW /* for shared profile */ 680 }; 681 682 #define ICE_SCHED_MIN_BW 500 /* in Kbps */ 683 #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */ 684 #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */ 685 #define ICE_SCHED_NO_PRIORITY 0 686 #define ICE_SCHED_NO_BW_WT 0 687 #define ICE_SCHED_DFLT_RL_PROF_ID 0 688 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF 689 #define ICE_SCHED_DFLT_BW_WT 4 690 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF 691 #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */ 692 693 /* Access Macros for Tx Sched RL Profile data */ 694 #define ICE_TXSCHED_GET_RL_PROF_ID(p) LE16_TO_CPU((p)->info.profile_id) 695 #define ICE_TXSCHED_GET_RL_MBS(p) LE16_TO_CPU((p)->info.max_burst_size) 696 #define ICE_TXSCHED_GET_RL_MULTIPLIER(p) LE16_TO_CPU((p)->info.rl_multiply) 697 #define ICE_TXSCHED_GET_RL_WAKEUP_MV(p) LE16_TO_CPU((p)->info.wake_up_calc) 698 #define ICE_TXSCHED_GET_RL_ENCODE(p) LE16_TO_CPU((p)->info.rl_encode) 699 700 #define ICE_MAX_PORT_PER_PCI_DEV 8 701 702 /* The following tree example shows the naming conventions followed under 703 * ice_port_info struct for default scheduler tree topology. 704 * 705 * A tree on a port 706 * * ---> root node 707 * (TC0)/ / / / \ \ \ \(TC7) ---> num_branches (range:1- 8) 708 * * * * * * * * * | 709 * / | 710 * * | 711 * / |-> num_elements (range:1 - 9) 712 * * | implies num_of_layers 713 * / | 714 * (a)* | 715 * 716 * (a) is the last_node_teid(not of type Leaf). A leaf node is created under 717 * (a) as child node where queues get added, add Tx/Rx queue admin commands; 718 * need TEID of (a) to add queues. 719 * 720 * This tree 721 * -> has 8 branches (one for each TC) 722 * -> First branch (TC0) has 4 elements 723 * -> has 4 layers 724 * -> (a) is the topmost layer node created by firmware on branch 0 725 * 726 * Note: Above asterisk tree covers only basic terminology and scenario. 727 * Refer to the documentation for more info. 728 */ 729 730 /* Data structure for saving BW information */ 731 enum ice_bw_type { 732 ICE_BW_TYPE_PRIO, 733 ICE_BW_TYPE_CIR, 734 ICE_BW_TYPE_CIR_WT, 735 ICE_BW_TYPE_EIR, 736 ICE_BW_TYPE_EIR_WT, 737 ICE_BW_TYPE_SHARED, 738 ICE_BW_TYPE_CNT /* This must be last */ 739 }; 740 741 struct ice_bw { 742 u32 bw; 743 u16 bw_alloc; 744 }; 745 746 struct ice_bw_type_info { 747 ice_declare_bitmap(bw_t_bitmap, ICE_BW_TYPE_CNT); 748 u8 generic; 749 struct ice_bw cir_bw; 750 struct ice_bw eir_bw; 751 u32 shared_bw; 752 }; 753 754 /* VSI queue context structure for given TC */ 755 struct ice_q_ctx { 756 u16 q_handle; 757 u32 q_teid; 758 /* bw_t_info saves queue BW information */ 759 struct ice_bw_type_info bw_t_info; 760 }; 761 762 /* VSI type list entry to locate corresponding VSI/aggregator nodes */ 763 struct ice_sched_vsi_info { 764 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS]; 765 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS]; 766 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS]; 767 u16 max_rdmaq[ICE_MAX_TRAFFIC_CLASS]; 768 /* bw_t_info saves VSI BW information */ 769 struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS]; 770 }; 771 772 /* CEE or IEEE 802.1Qaz ETS Configuration data */ 773 struct ice_dcb_ets_cfg { 774 u8 willing; 775 u8 cbs; 776 u8 maxtcs; 777 u8 prio_table[ICE_MAX_TRAFFIC_CLASS]; 778 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS]; 779 u8 tsatable[ICE_MAX_TRAFFIC_CLASS]; 780 }; 781 782 /* CEE or IEEE 802.1Qaz PFC Configuration data */ 783 struct ice_dcb_pfc_cfg { 784 u8 willing; 785 u8 mbc; 786 u8 pfccap; 787 u8 pfcena; 788 }; 789 790 /* CEE or IEEE 802.1Qaz Application Priority data */ 791 struct ice_dcb_app_priority_table { 792 u16 prot_id; 793 u8 priority; 794 u8 selector; 795 }; 796 797 #define ICE_MAX_USER_PRIORITY 8 798 #define ICE_DCBX_MAX_APPS 64 799 #define ICE_DSCP_NUM_VAL 64 800 #define ICE_LLDPDU_SIZE 1500 801 #define ICE_TLV_STATUS_OPER 0x1 802 #define ICE_TLV_STATUS_SYNC 0x2 803 #define ICE_TLV_STATUS_ERR 0x4 804 #define ICE_APP_PROT_ID_FCOE 0x8906 805 #define ICE_APP_PROT_ID_ISCSI 0x0cbc 806 #define ICE_APP_PROT_ID_ISCSI_860 0x035c 807 #define ICE_APP_PROT_ID_FIP 0x8914 808 #define ICE_APP_SEL_ETHTYPE 0x1 809 #define ICE_APP_SEL_TCPIP 0x2 810 #define ICE_CEE_APP_SEL_ETHTYPE 0x0 811 #define ICE_CEE_APP_SEL_TCPIP 0x1 812 813 struct ice_dcbx_cfg { 814 u32 numapps; 815 u32 tlv_status; /* CEE mode TLV status */ 816 struct ice_dcb_ets_cfg etscfg; 817 struct ice_dcb_ets_cfg etsrec; 818 struct ice_dcb_pfc_cfg pfc; 819 #define ICE_QOS_MODE_VLAN 0x0 820 #define ICE_QOS_MODE_DSCP 0x1 821 u8 pfc_mode; 822 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS]; 823 /* when DSCP mapping defined by user set its bit to 1 */ 824 ice_declare_bitmap(dscp_mapped, ICE_DSCP_NUM_VAL); 825 /* array holding DSCP -> UP/TC values for DSCP L3 QoS mode */ 826 u8 dscp_map[ICE_DSCP_NUM_VAL]; 827 u8 dcbx_mode; 828 #define ICE_DCBX_MODE_CEE 0x1 829 #define ICE_DCBX_MODE_IEEE 0x2 830 u8 app_mode; 831 #define ICE_DCBX_APPS_NON_WILLING 0x1 832 }; 833 834 struct ice_qos_cfg { 835 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */ 836 struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */ 837 struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */ 838 u8 dcbx_status : 3; /* see ICE_DCBX_STATUS_DIS */ 839 u8 is_sw_lldp : 1; 840 }; 841 842 struct ice_port_info { 843 struct ice_sched_node *root; /* Root Node per Port */ 844 struct ice_hw *hw; /* back pointer to HW instance */ 845 u32 last_node_teid; /* scheduler last node info */ 846 u16 sw_id; /* Initial switch ID belongs to port */ 847 u16 pf_vf_num; 848 u8 port_state; 849 #define ICE_SCHED_PORT_STATE_INIT 0x0 850 #define ICE_SCHED_PORT_STATE_READY 0x1 851 u8 lport; 852 #define ICE_LPORT_MASK 0xff 853 struct ice_fc_info fc; 854 struct ice_mac_info mac; 855 struct ice_phy_info phy; 856 struct ice_lock sched_lock; /* protect access to TXSched tree */ 857 struct ice_sched_node * 858 sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM]; 859 struct ice_bw_type_info root_node_bw_t_info; 860 struct ice_bw_type_info tc_node_bw_t_info[ICE_MAX_TRAFFIC_CLASS]; 861 struct ice_qos_cfg qos_cfg; 862 u8 is_vf:1; 863 }; 864 865 struct ice_switch_info { 866 struct LIST_HEAD_TYPE vsi_list_map_head; 867 struct ice_sw_recipe *recp_list; 868 u16 prof_res_bm_init; 869 u16 max_used_prof_index; 870 871 ice_declare_bitmap(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS); 872 }; 873 874 /* Enum defining the different states of the mailbox snapshot in the 875 * PF-VF mailbox overflow detection algorithm. The snapshot can be in 876 * states: 877 * 1. ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT - generate a new static snapshot 878 * within the mailbox buffer. 879 * 2. ICE_MAL_VF_DETECT_STATE_TRAVERSE - iterate through the mailbox snaphot 880 * 3. ICE_MAL_VF_DETECT_STATE_DETECT - track the messages sent per VF via the 881 * mailbox and mark any VFs sending more messages than the threshold limit set. 882 * 4. ICE_MAL_VF_DETECT_STATE_INVALID - Invalid mailbox state set to 0xFFFFFFFF. 883 */ 884 enum ice_mbx_snapshot_state { 885 ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT = 0, 886 ICE_MAL_VF_DETECT_STATE_TRAVERSE, 887 ICE_MAL_VF_DETECT_STATE_DETECT, 888 ICE_MAL_VF_DETECT_STATE_INVALID = 0xFFFFFFFF, 889 }; 890 891 /* Structure to hold information of the static snapshot and the mailbox 892 * buffer data used to generate and track the snapshot. 893 * 1. state: the state of the mailbox snapshot in the malicious VF 894 * detection state handler ice_mbx_vf_state_handler() 895 * 2. head : head of the mailbox snapshot in a circular mailbox buffer 896 * 3. tail : tail of the mailbox snapshot in a circular mailbox buffer 897 * 4. num_iterations: number of messages traversed in circular mailbox buffer 898 * 5. num_msg_proc: number of messages processed in mailbox 899 * 6. num_pending_arq: number of pending asynchronous messages 900 * 7. max_num_msgs_mbx: maximum messages in mailbox for currently 901 * serviced work item or interrupt. 902 */ 903 struct ice_mbx_snap_buffer_data { 904 enum ice_mbx_snapshot_state state; 905 u32 head; 906 u32 tail; 907 u32 num_iterations; 908 u16 num_msg_proc; 909 u16 num_pending_arq; 910 u16 max_num_msgs_mbx; 911 }; 912 913 /* Structure to track messages sent by VFs on mailbox: 914 * 1. vf_cntr : a counter array of VFs to track the number of 915 * asynchronous messages sent by each VF 916 * 2. vfcntr_len : number of entries in VF counter array 917 */ 918 struct ice_mbx_vf_counter { 919 u32 *vf_cntr; 920 u32 vfcntr_len; 921 }; 922 923 /* Structure to hold data relevant to the captured static snapshot 924 * of the PF-VF mailbox. 925 */ 926 struct ice_mbx_snapshot { 927 struct ice_mbx_snap_buffer_data mbx_buf; 928 struct ice_mbx_vf_counter mbx_vf; 929 }; 930 931 /* Structure to hold data to be used for capturing or updating a 932 * static snapshot. 933 * 1. num_msg_proc: number of messages processed in mailbox 934 * 2. num_pending_arq: number of pending asynchronous messages 935 * 3. max_num_msgs_mbx: maximum messages in mailbox for currently 936 * serviced work item or interrupt. 937 * 4. async_watermark_val: An upper threshold set by caller to determine 938 * if the pending arq count is large enough to assume that there is 939 * the possibility of a mailicious VF. 940 */ 941 struct ice_mbx_data { 942 u16 num_msg_proc; 943 u16 num_pending_arq; 944 u16 max_num_msgs_mbx; 945 u16 async_watermark_val; 946 }; 947 948 /* PHY model */ 949 enum ice_phy_model { 950 ICE_PHY_UNSUP = -1, 951 ICE_PHY_E810 = 1, 952 ICE_PHY_E822, 953 }; 954 955 /* Port hardware description */ 956 struct ice_hw { 957 u8 *hw_addr; 958 void *back; 959 struct ice_aqc_layer_props *layer_info; 960 struct ice_port_info *port_info; 961 /* 2D Array for each Tx Sched RL Profile type */ 962 struct ice_sched_rl_profile **cir_profiles; 963 struct ice_sched_rl_profile **eir_profiles; 964 struct ice_sched_rl_profile **srl_profiles; 965 /* PSM clock frequency for calculating RL profile params */ 966 u32 psm_clk_freq; 967 u64 debug_mask; /* BITMAP for debug mask */ 968 enum ice_mac_type mac_type; 969 970 /* pci info */ 971 u16 device_id; 972 u16 vendor_id; 973 u16 subsystem_device_id; 974 u16 subsystem_vendor_id; 975 u8 revision_id; 976 977 u8 pf_id; /* device profile info */ 978 enum ice_phy_model phy_model; 979 980 u16 max_burst_size; /* driver sets this value */ 981 982 /* Tx Scheduler values */ 983 u8 num_tx_sched_layers; 984 u8 num_tx_sched_phys_layers; 985 u8 flattened_layers; 986 u8 max_cgds; 987 u8 sw_entry_point_layer; 988 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 989 struct LIST_HEAD_TYPE agg_list; /* lists all aggregator */ 990 /* List contain profile ID(s) and other params per layer */ 991 struct LIST_HEAD_TYPE rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 992 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI]; 993 u8 evb_veb; /* true for VEB, false for VEPA */ 994 u8 reset_ongoing; /* true if HW is in reset, false otherwise */ 995 struct ice_bus_info bus; 996 struct ice_flash_info flash; 997 struct ice_hw_dev_caps dev_caps; /* device capabilities */ 998 struct ice_hw_func_caps func_caps; /* function capabilities */ 999 1000 struct ice_switch_info *switch_info; /* switch filter lists */ 1001 1002 /* Control Queue info */ 1003 struct ice_ctl_q_info adminq; 1004 struct ice_ctl_q_info mailboxq; 1005 u8 api_branch; /* API branch version */ 1006 u8 api_maj_ver; /* API major version */ 1007 u8 api_min_ver; /* API minor version */ 1008 u8 api_patch; /* API patch version */ 1009 u8 fw_branch; /* firmware branch version */ 1010 u8 fw_maj_ver; /* firmware major version */ 1011 u8 fw_min_ver; /* firmware minor version */ 1012 u8 fw_patch; /* firmware patch version */ 1013 u32 fw_build; /* firmware build number */ 1014 1015 struct ice_fwlog_cfg fwlog_cfg; 1016 bool fwlog_support_ena; /* does hardware support FW logging? */ 1017 1018 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL 1019 * register. Used for determining the ITR/INTRL granularity during 1020 * initialization. 1021 */ 1022 #define ICE_MAX_AGG_BW_200G 0x0 1023 #define ICE_MAX_AGG_BW_100G 0X1 1024 #define ICE_MAX_AGG_BW_50G 0x2 1025 #define ICE_MAX_AGG_BW_25G 0x3 1026 /* ITR granularity for different speeds */ 1027 #define ICE_ITR_GRAN_ABOVE_25 2 1028 #define ICE_ITR_GRAN_MAX_25 4 1029 /* ITR granularity in 1 us */ 1030 u8 itr_gran; 1031 /* INTRL granularity for different speeds */ 1032 #define ICE_INTRL_GRAN_ABOVE_25 4 1033 #define ICE_INTRL_GRAN_MAX_25 8 1034 /* INTRL granularity in 1 us */ 1035 u8 intrl_gran; 1036 1037 /* true if VSIs can share unicast MAC addr */ 1038 u8 umac_shared; 1039 1040 #define ICE_PHY_PER_NAC_E822 1 1041 #define ICE_MAX_QUAD 2 1042 #define ICE_QUADS_PER_PHY_E822 2 1043 #define ICE_PORTS_PER_PHY_E822 8 1044 #define ICE_PORTS_PER_QUAD 4 1045 #define ICE_PORTS_PER_PHY_E810 4 1046 #define ICE_NUM_EXTERNAL_PORTS (ICE_MAX_QUAD * ICE_PORTS_PER_QUAD) 1047 1048 /* Active package version (currently active) */ 1049 struct ice_pkg_ver active_pkg_ver; 1050 u32 pkg_seg_id; 1051 u32 pkg_sign_type; 1052 u32 active_track_id; 1053 u8 pkg_has_signing_seg:1; 1054 u8 active_pkg_name[ICE_PKG_NAME_SIZE]; 1055 u8 active_pkg_in_nvm; 1056 1057 /* Driver's package ver - (from the Ice Metadata section) */ 1058 struct ice_pkg_ver pkg_ver; 1059 u8 pkg_name[ICE_PKG_NAME_SIZE]; 1060 1061 /* Driver's Ice segment format version and id (from the Ice seg) */ 1062 struct ice_pkg_ver ice_seg_fmt_ver; 1063 u8 ice_seg_id[ICE_SEG_ID_SIZE]; 1064 1065 /* Pointer to the ice segment */ 1066 struct ice_seg *seg; 1067 1068 /* Pointer to allocated copy of pkg memory */ 1069 u8 *pkg_copy; 1070 u32 pkg_size; 1071 1072 /* tunneling info */ 1073 struct ice_lock tnl_lock; 1074 struct ice_tunnel_table tnl; 1075 1076 /* HW block tables */ 1077 struct ice_blk_info blk[ICE_BLK_COUNT]; 1078 struct ice_lock fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */ 1079 struct LIST_HEAD_TYPE fl_profs[ICE_BLK_COUNT]; 1080 struct ice_lock rss_locks; /* protect RSS configuration */ 1081 struct LIST_HEAD_TYPE rss_list_head; 1082 struct ice_mbx_snapshot mbx_snapshot; 1083 u8 dvm_ena; 1084 }; 1085 1086 /* Statistics collected by each port, VSI, VEB, and S-channel */ 1087 struct ice_eth_stats { 1088 u64 rx_bytes; /* gorc */ 1089 u64 rx_unicast; /* uprc */ 1090 u64 rx_multicast; /* mprc */ 1091 u64 rx_broadcast; /* bprc */ 1092 u64 rx_discards; /* rdpc */ 1093 u64 rx_unknown_protocol; /* rupp */ 1094 u64 tx_bytes; /* gotc */ 1095 u64 tx_unicast; /* uptc */ 1096 u64 tx_multicast; /* mptc */ 1097 u64 tx_broadcast; /* bptc */ 1098 u64 tx_discards; /* tdpc */ 1099 u64 tx_errors; /* tepc */ 1100 u64 rx_no_desc; /* repc */ 1101 u64 rx_errors; /* repc */ 1102 }; 1103 1104 #define ICE_MAX_UP 8 1105 1106 /* Statistics collected per VEB per User Priority (UP) for up to 8 UPs */ 1107 struct ice_veb_up_stats { 1108 u64 up_rx_pkts[ICE_MAX_UP]; 1109 u64 up_rx_bytes[ICE_MAX_UP]; 1110 u64 up_tx_pkts[ICE_MAX_UP]; 1111 u64 up_tx_bytes[ICE_MAX_UP]; 1112 }; 1113 1114 /* Statistics collected by the MAC */ 1115 struct ice_hw_port_stats { 1116 /* eth stats collected by the port */ 1117 struct ice_eth_stats eth; 1118 /* additional port specific stats */ 1119 u64 tx_dropped_link_down; /* tdold */ 1120 u64 crc_errors; /* crcerrs */ 1121 u64 illegal_bytes; /* illerrc */ 1122 u64 error_bytes; /* errbc */ 1123 u64 mac_local_faults; /* mlfc */ 1124 u64 mac_remote_faults; /* mrfc */ 1125 u64 rx_len_errors; /* rlec */ 1126 u64 link_xon_rx; /* lxonrxc */ 1127 u64 link_xoff_rx; /* lxoffrxc */ 1128 u64 link_xon_tx; /* lxontxc */ 1129 u64 link_xoff_tx; /* lxofftxc */ 1130 u64 priority_xon_rx[8]; /* pxonrxc[8] */ 1131 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */ 1132 u64 priority_xon_tx[8]; /* pxontxc[8] */ 1133 u64 priority_xoff_tx[8]; /* pxofftxc[8] */ 1134 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */ 1135 u64 rx_size_64; /* prc64 */ 1136 u64 rx_size_127; /* prc127 */ 1137 u64 rx_size_255; /* prc255 */ 1138 u64 rx_size_511; /* prc511 */ 1139 u64 rx_size_1023; /* prc1023 */ 1140 u64 rx_size_1522; /* prc1522 */ 1141 u64 rx_size_big; /* prc9522 */ 1142 u64 rx_undersize; /* ruc */ 1143 u64 rx_fragments; /* rfc */ 1144 u64 rx_oversize; /* roc */ 1145 u64 rx_jabber; /* rjc */ 1146 u64 tx_size_64; /* ptc64 */ 1147 u64 tx_size_127; /* ptc127 */ 1148 u64 tx_size_255; /* ptc255 */ 1149 u64 tx_size_511; /* ptc511 */ 1150 u64 tx_size_1023; /* ptc1023 */ 1151 u64 tx_size_1522; /* ptc1522 */ 1152 u64 tx_size_big; /* ptc9522 */ 1153 u64 mac_short_pkt_dropped; /* mspdc */ 1154 /* EEE LPI */ 1155 u32 tx_lpi_status; 1156 u32 rx_lpi_status; 1157 u64 tx_lpi_count; /* etlpic */ 1158 u64 rx_lpi_count; /* erlpic */ 1159 }; 1160 1161 enum ice_sw_fwd_act_type { 1162 ICE_FWD_TO_VSI = 0, 1163 ICE_FWD_TO_VSI_LIST, /* Do not use this when adding filter */ 1164 ICE_FWD_TO_Q, 1165 ICE_FWD_TO_QGRP, 1166 ICE_DROP_PACKET, 1167 ICE_LG_ACTION, 1168 ICE_INVAL_ACT 1169 }; 1170 1171 struct ice_aq_get_set_rss_lut_params { 1172 u16 vsi_handle; /* software VSI handle */ 1173 u16 lut_size; /* size of the LUT buffer */ 1174 u8 lut_type; /* type of the LUT (i.e. VSI, PF, Global) */ 1175 u8 *lut; /* input RSS LUT for set and output RSS LUT for get */ 1176 u8 global_lut_id; /* only valid when lut_type is global */ 1177 }; 1178 1179 /* Checksum and Shadow RAM pointers */ 1180 #define ICE_SR_NVM_CTRL_WORD 0x00 1181 #define ICE_SR_PHY_ANALOG_PTR 0x04 1182 #define ICE_SR_OPTION_ROM_PTR 0x05 1183 #define ICE_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06 1184 #define ICE_SR_AUTO_GENERATED_POINTERS_PTR 0x07 1185 #define ICE_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08 1186 #define ICE_SR_EMP_GLOBAL_MODULE_PTR 0x09 1187 #define ICE_SR_EMP_IMAGE_PTR 0x0B 1188 #define ICE_SR_PE_IMAGE_PTR 0x0C 1189 #define ICE_SR_CSR_PROTECTED_LIST_PTR 0x0D 1190 #define ICE_SR_MNG_CFG_PTR 0x0E 1191 #define ICE_SR_EMP_MODULE_PTR 0x0F 1192 #define ICE_SR_PBA_BLOCK_PTR 0x16 1193 #define ICE_SR_BOOT_CFG_PTR 0x132 1194 #define ICE_SR_NVM_WOL_CFG 0x19 1195 #define ICE_NVM_OROM_VER_OFF 0x02 1196 #define ICE_SR_NVM_DEV_STARTER_VER 0x18 1197 #define ICE_SR_ALTERNATE_SAN_MAC_ADDR_PTR 0x27 1198 #define ICE_SR_PERMANENT_SAN_MAC_ADDR_PTR 0x28 1199 #define ICE_SR_NVM_MAP_VER 0x29 1200 #define ICE_SR_NVM_IMAGE_VER 0x2A 1201 #define ICE_SR_NVM_STRUCTURE_VER 0x2B 1202 #define ICE_SR_NVM_EETRACK_LO 0x2D 1203 #define ICE_SR_NVM_EETRACK_HI 0x2E 1204 #define ICE_NVM_VER_LO_SHIFT 0 1205 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT) 1206 #define ICE_NVM_VER_HI_SHIFT 12 1207 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT) 1208 #define ICE_OEM_EETRACK_ID 0xffffffff 1209 #define ICE_OROM_VER_PATCH_SHIFT 0 1210 #define ICE_OROM_VER_PATCH_MASK (0xff << ICE_OROM_VER_PATCH_SHIFT) 1211 #define ICE_OROM_VER_BUILD_SHIFT 8 1212 #define ICE_OROM_VER_BUILD_MASK (0xffff << ICE_OROM_VER_BUILD_SHIFT) 1213 #define ICE_OROM_VER_SHIFT 24 1214 #define ICE_OROM_VER_MASK (0xff << ICE_OROM_VER_SHIFT) 1215 #define ICE_SR_VPD_PTR 0x2F 1216 #define ICE_SR_PXE_SETUP_PTR 0x30 1217 #define ICE_SR_PXE_CFG_CUST_OPTIONS_PTR 0x31 1218 #define ICE_SR_NVM_ORIGINAL_EETRACK_LO 0x34 1219 #define ICE_SR_NVM_ORIGINAL_EETRACK_HI 0x35 1220 #define ICE_SR_VLAN_CFG_PTR 0x37 1221 #define ICE_SR_POR_REGS_AUTO_LOAD_PTR 0x38 1222 #define ICE_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A 1223 #define ICE_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B 1224 #define ICE_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C 1225 #define ICE_SR_PHY_CFG_SCRIPT_PTR 0x3D 1226 #define ICE_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E 1227 #define ICE_SR_SW_CHECKSUM_WORD 0x3F 1228 #define ICE_SR_PFA_PTR 0x40 1229 #define ICE_SR_1ST_SCRATCH_PAD_PTR 0x41 1230 #define ICE_SR_1ST_NVM_BANK_PTR 0x42 1231 #define ICE_SR_NVM_BANK_SIZE 0x43 1232 #define ICE_SR_1ST_OROM_BANK_PTR 0x44 1233 #define ICE_SR_OROM_BANK_SIZE 0x45 1234 #define ICE_SR_NETLIST_BANK_PTR 0x46 1235 #define ICE_SR_NETLIST_BANK_SIZE 0x47 1236 #define ICE_SR_EMP_SR_SETTINGS_PTR 0x48 1237 #define ICE_SR_CONFIGURATION_METADATA_PTR 0x4D 1238 #define ICE_SR_IMMEDIATE_VALUES_PTR 0x4E 1239 #define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR 0x134 1240 #define ICE_SR_POR_REGISTERS_AUTOLOAD_PTR 0x118 1241 1242 /* CSS Header words */ 1243 #define ICE_NVM_CSS_HDR_LEN_L 0x02 1244 #define ICE_NVM_CSS_HDR_LEN_H 0x03 1245 #define ICE_NVM_CSS_SREV_L 0x14 1246 #define ICE_NVM_CSS_SREV_H 0x15 1247 1248 /* Length of Authentication header section in words */ 1249 #define ICE_NVM_AUTH_HEADER_LEN 0x08 1250 1251 /* The Link Topology Netlist section is stored as a series of words. It is 1252 * stored in the NVM as a TLV, with the first two words containing the type 1253 * and length. 1254 */ 1255 #define ICE_NETLIST_LINK_TOPO_MOD_ID 0x011B 1256 #define ICE_NETLIST_TYPE_OFFSET 0x0000 1257 #define ICE_NETLIST_LEN_OFFSET 0x0001 1258 1259 /* The Link Topology section follows the TLV header. When reading the netlist 1260 * using ice_read_netlist_module, we need to account for the 2-word TLV 1261 * header. 1262 */ 1263 #define ICE_NETLIST_LINK_TOPO_OFFSET(n) ((n) + 2) 1264 1265 #define ICE_LINK_TOPO_MODULE_LEN ICE_NETLIST_LINK_TOPO_OFFSET(0x0000) 1266 #define ICE_LINK_TOPO_NODE_COUNT ICE_NETLIST_LINK_TOPO_OFFSET(0x0001) 1267 1268 #define ICE_LINK_TOPO_NODE_COUNT_M MAKEMASK(0x3FF, 0) 1269 1270 /* The Netlist ID Block is located after all of the Link Topology nodes. */ 1271 #define ICE_NETLIST_ID_BLK_SIZE 0x30 1272 #define ICE_NETLIST_ID_BLK_OFFSET(n) ICE_NETLIST_LINK_TOPO_OFFSET(0x0004 + 2 * (n)) 1273 1274 /* netlist ID block field offsets (word offsets) */ 1275 #define ICE_NETLIST_ID_BLK_MAJOR_VER_LOW 0x02 1276 #define ICE_NETLIST_ID_BLK_MAJOR_VER_HIGH 0x03 1277 #define ICE_NETLIST_ID_BLK_MINOR_VER_LOW 0x04 1278 #define ICE_NETLIST_ID_BLK_MINOR_VER_HIGH 0x05 1279 #define ICE_NETLIST_ID_BLK_TYPE_LOW 0x06 1280 #define ICE_NETLIST_ID_BLK_TYPE_HIGH 0x07 1281 #define ICE_NETLIST_ID_BLK_REV_LOW 0x08 1282 #define ICE_NETLIST_ID_BLK_REV_HIGH 0x09 1283 #define ICE_NETLIST_ID_BLK_SHA_HASH_WORD(n) (0x0A + (n)) 1284 #define ICE_NETLIST_ID_BLK_CUST_VER 0x2F 1285 1286 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */ 1287 #define ICE_SR_VPD_SIZE_WORDS 512 1288 #define ICE_SR_PCIE_ALT_SIZE_WORDS 512 1289 #define ICE_SR_CTRL_WORD_1_S 0x06 1290 #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S) 1291 #define ICE_SR_CTRL_WORD_VALID 0x1 1292 #define ICE_SR_CTRL_WORD_OROM_BANK BIT(3) 1293 #define ICE_SR_CTRL_WORD_NETLIST_BANK BIT(4) 1294 #define ICE_SR_CTRL_WORD_NVM_BANK BIT(5) 1295 1296 #define ICE_SR_NVM_PTR_4KB_UNITS BIT(15) 1297 1298 /* Shadow RAM related */ 1299 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800 1300 #define ICE_SR_BUF_ALIGNMENT 4096 1301 #define ICE_SR_WORDS_IN_1KB 512 1302 /* Checksum should be calculated such that after adding all the words, 1303 * including the checksum word itself, the sum should be 0xBABA. 1304 */ 1305 #define ICE_SR_SW_CHECKSUM_BASE 0xBABA 1306 1307 /* Link override related */ 1308 #define ICE_SR_PFA_LINK_OVERRIDE_WORDS 10 1309 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS 4 1310 #define ICE_SR_PFA_LINK_OVERRIDE_OFFSET 2 1311 #define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET 1 1312 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET 2 1313 #define ICE_FW_API_LINK_OVERRIDE_MAJ 1 1314 #define ICE_FW_API_LINK_OVERRIDE_MIN 5 1315 #define ICE_FW_API_LINK_OVERRIDE_PATCH 2 1316 1317 #define ICE_PBA_FLAG_DFLT 0xFAFA 1318 /* Hash redirection LUT for VSI - maximum array size */ 1319 #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4) 1320 1321 /* 1322 * Defines for values in the VF_PE_DB_SIZE bits in the GLPCI_LBARCTRL register. 1323 * This is needed to determine the BAR0 space for the VFs 1324 */ 1325 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_0KB 0x0 1326 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_8KB 0x1 1327 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_64KB 0x2 1328 1329 /* AQ API version for LLDP_FILTER_CONTROL */ 1330 #define ICE_FW_API_LLDP_FLTR_MAJ 1 1331 #define ICE_FW_API_LLDP_FLTR_MIN 7 1332 #define ICE_FW_API_LLDP_FLTR_PATCH 1 1333 1334 /* AQ API version for report default configuration */ 1335 #define ICE_FW_API_REPORT_DFLT_CFG_MAJ 1 1336 #define ICE_FW_API_REPORT_DFLT_CFG_MIN 7 1337 #define ICE_FW_API_REPORT_DFLT_CFG_PATCH 3 1338 1339 /* FW version for FEC disable in Auto FEC mode */ 1340 #define ICE_FW_FEC_DIS_AUTO_BRANCH 1 1341 #define ICE_FW_FEC_DIS_AUTO_MAJ 7 1342 #define ICE_FW_FEC_DIS_AUTO_MIN 0 1343 #define ICE_FW_FEC_DIS_AUTO_PATCH 5 1344 1345 /* AQ API version for FW health reports */ 1346 #define ICE_FW_API_HEALTH_REPORT_MAJ 1 1347 #define ICE_FW_API_HEALTH_REPORT_MIN 7 1348 #define ICE_FW_API_HEALTH_REPORT_PATCH 6 1349 1350 /* AQ API version for FW auto drop reports */ 1351 #define ICE_FW_API_AUTO_DROP_MAJ 1 1352 #define ICE_FW_API_AUTO_DROP_MIN 4 1353 #endif /* _ICE_TYPE_H_ */ 1354