1 /* 2 * Copyright (c) 2014 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Matthew Dillon <dillon@backplane.com> and was subsequently ported 6 * to FreeBSD by Michael Gmelin <freebsd@grem.de> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in 16 * the documentation and/or other materials provided with the 17 * distribution. 18 * 3. Neither the name of The DragonFly Project nor the names of its 19 * contributors may be used to endorse or promote products derived 20 * from this software without specific, prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * $FreeBSD$ 36 */ 37 /* 38 * Intel fourth generation mobile cpus integrated I2C device. 39 * 40 * Datasheet reference: Section 22. 41 * 42 * http://www.intel.com/content/www/us/en/processors/core/4th-gen-core-family-mobile-i-o-datasheet.html?wapkw=datasheets+4th+generation 43 * 44 * This is a from-scratch driver under the BSD license using the Intel data 45 * sheet and the linux driver for reference. All code is freshly written 46 * without referencing the linux driver code. However, during testing 47 * I am also using the linux driver code as a reference to help resolve any 48 * issues that come. These will be specifically documented in the code. 49 * 50 * This controller is an I2C master only and cannot act as a slave. The IO 51 * voltage should be set by the BIOS. Standard (100Kb/s) and Fast (400Kb/s) 52 * and fast mode plus (1MB/s) is supported. High speed mode (3.4 MB/s) is NOT 53 * supported. 54 */ 55 56 #ifndef _ICHIIC_IG4_REG_H_ 57 #define _ICHIIC_IG4_REG_H_ 58 59 /* 60 * 22.2 MMIO registers can be accessed through BAR0 in PCI mode or through 61 * BAR1 when in ACPI mode. 62 * 63 * Register width is 32-bits 64 * 65 * 22.2 Default Values on device reset are 0 except as specified here: 66 * TAR_ADD 0x00000055 67 * SS_SCL_HCNT 0x00000264 68 * SS_SCL_LCNT 0x000002C2 69 * FS_SCL_HCNT 0x0000006E 70 * FS_SCL_LCNT 0x000000CF 71 * INTR_MASK 0x000008FF 72 * I2C_STA 0x00000006 73 * SDA_HOLD 0x00000001 74 * SDA_SETUP 0x00000064 75 * COMP_PARAM1 0x00FFFF6E 76 * COMP_VER 0x3131352A 77 */ 78 79 #define IG4_REG_CTL 0x0000 /* RW Control Register */ 80 #define IG4_REG_TAR_ADD 0x0004 /* RW Target Address */ 81 #define IG4_REG_DATA_CMD 0x0010 /* RW Data Buffer and Command */ 82 #define IG4_REG_SS_SCL_HCNT 0x0014 /* RW Std Speed clock High Count */ 83 #define IG4_REG_SS_SCL_LCNT 0x0018 /* RW Std Speed clock Low Count */ 84 #define IG4_REG_FS_SCL_HCNT 0x001C /* RW Fast Speed clock High Count */ 85 #define IG4_REG_FS_SCL_LCNT 0x0020 /* RW Fast Speed clock Low Count */ 86 #define IG4_REG_INTR_STAT 0x002C /* RO Interrupt Status */ 87 #define IG4_REG_INTR_MASK 0x0030 /* RW Interrupt Mask */ 88 #define IG4_REG_RAW_INTR_STAT 0x0034 /* RO Raw Interrupt Status */ 89 #define IG4_REG_RX_TL 0x0038 /* RW Receive FIFO Threshold */ 90 #define IG4_REG_TX_TL 0x003C /* RW Transmit FIFO Threshold */ 91 #define IG4_REG_CLR_INTR 0x0040 /* RO Clear Interrupt */ 92 #define IG4_REG_CLR_RX_UNDER 0x0044 /* RO Clear RX_Under Interrupt */ 93 #define IG4_REG_CLR_RX_OVER 0x0048 /* RO Clear RX_Over Interrupt */ 94 #define IG4_REG_CLR_TX_OVER 0x004C /* RO Clear TX_Over Interrupt */ 95 #define IG4_REG_CLR_TX_ABORT 0x0054 /* RO Clear TX_Abort Interrupt */ 96 #define IG4_REG_CLR_ACTIVITY 0x005C /* RO Clear Activity Interrupt */ 97 #define IG4_REG_CLR_STOP_DET 0x0060 /* RO Clear STOP Detection Int */ 98 #define IG4_REG_CLR_START_DET 0x0064 /* RO Clear START Detection Int */ 99 #define IG4_REG_CLR_GEN_CALL 0x0068 /* RO Clear General Call Interrupt */ 100 #define IG4_REG_I2C_EN 0x006C /* RW I2C Enable */ 101 #define IG4_REG_I2C_STA 0x0070 /* RO I2C Status */ 102 #define IG4_REG_TXFLR 0x0074 /* RO Transmit FIFO Level */ 103 #define IG4_REG_RXFLR 0x0078 /* RO Receive FIFO Level */ 104 #define IG4_REG_SDA_HOLD 0x007C /* RW SDA Hold Time Length */ 105 #define IG4_REG_TX_ABRT_SOURCE 0x0080 /* RO Transmit Abort Source */ 106 #define IG4_REG_SLV_DATA_NACK 0x0084 /* RW General Slave Data NACK */ 107 #define IG4_REG_DMA_CTRL 0x0088 /* RW DMA Control */ 108 #define IG4_REG_DMA_TDLR 0x008C /* RW DMA Transmit Data Level */ 109 #define IG4_REG_DMA_RDLR 0x0090 /* RW DMA Receive Data Level */ 110 #define IG4_REG_SDA_SETUP 0x0094 /* RW SDA Setup */ 111 #define IG4_REG_ENABLE_STATUS 0x009C /* RO Enable Status */ 112 #define IG4_REG_COMP_PARAM1 0x00F4 /* RO Component Parameter */ 113 #define IG4_REG_COMP_VER 0x00F8 /* RO Component Version */ 114 #define IG4_REG_COMP_TYPE 0x00FC /* RO Probe width/endian? (linux) */ 115 #define IG4_REG_CLK_PARMS 0x0800 /* RW Clock Parameters */ 116 #define IG4_REG_RESETS 0x0804 /* RW Reset Register */ 117 #define IG4_REG_GENERAL 0x0808 /* RW General Register */ 118 #define IG4_REG_SW_LTR_VALUE 0x0810 /* RW SW LTR Value */ 119 #define IG4_REG_AUTO_LTR_VALUE 0x0814 /* RW Auto LTR Value */ 120 121 /* 122 * CTL - Control Register 22.2.1 123 * Default Value: 0x0000007F. 124 * 125 * RESTARTEN - RW Restart Enable 126 * 10BIT - RW Controller operates in 10-bit mode, else 7-bit 127 * 128 * NOTE: When restart is disabled the controller is incapable of 129 * performing the following functions: 130 * 131 * Sending a START Byte 132 * Performing any high-speed mode op 133 * Performing direction changes in combined format mode 134 * Performing a read operation with a 10-bit address 135 * 136 * Attempting to perform the above operations will result in the 137 * TX_ABORT bit being set in RAW_INTR_STAT. 138 */ 139 #define IG4_CTL_SLAVE_DISABLE 0x0040 /* snarfed from linux */ 140 #define IG4_CTL_RESTARTEN 0x0020 /* Allow Restart when master */ 141 #define IG4_CTL_10BIT 0x0010 /* ctlr accepts 10-bit addresses */ 142 #define IG4_CTL_SPEED_FAST 0x0004 /* snarfed from linux */ 143 #define IG4_CTL_SPEED_STD 0x0002 /* snarfed from linux */ 144 #define IG4_CTL_MASTER 0x0001 /* snarfed from linux */ 145 146 /* 147 * TAR_ADD - Target Address Register 22.2.2 148 * Default Value: 0x00000055F 149 * 150 * 10BIT - RW controller starts its transfers in 10-bit 151 * address mode, else 7-bit. 152 * 153 * SPECIAL - RW Indicates whether software performs a General Call 154 * or START BYTE command. 155 * 156 * 0 Ignore GC_OR_START and use TAR address. 157 * 158 * 1 Perform special I2C Command based on GC_OR_START. 159 * 160 * GC_OR_START - RW (only if SPECIAL is set) 161 * 162 * 0 General Call Address. After issuing a General Call, 163 * only writes may be performed. Attempting to issue 164 * a read command results in IX_ABRT in RAW_INTR_STAT. 165 * The controller remains in General Call mode until 166 * bit 11 (SPECIAL) is cleared. 167 * 168 * 1 START BYTE. 169 * 170 * 171 * IC_TAR - RW when transmitting a general call, these bits are 172 * ignored. To generate a START BYTE, the address 173 * needs to be written into these bits once. 174 * 175 * This register should only be updated when the IIC is disabled (I2C_ENABLE=0) 176 */ 177 #define IG4_TAR_10BIT 0x1000 /* start xfer in 10-bit mode */ 178 #define IG4_TAR_SPECIAL 0x0800 /* Perform special command */ 179 #define IG4_TAR_GC_OR_START 0x0400 /* General Call or Start */ 180 #define IG4_TAR_ADDR_MASK 0x03FF /* Target address */ 181 182 /* 183 * TAR_DATA_CMD - Data Buffer and Command Register 22.2.3 184 * 185 * RESTART - RW This bit controls whether a forced RESTART is 186 * issued before the byte is sent or received. 187 * 188 * 0 If not set a RESTART is only issued if the transfer 189 * direction is changing from the previous command. 190 * 191 * 1 A RESTART is issued before the byte is sent or 192 * received, regardless of whether or not the transfer 193 * direction is changing from the previous command. 194 * 195 * STOP - RW This bit controls whether a STOP is issued after 196 * the byte is sent or received. 197 * 198 * 0 STOP is not issued after this byte, regardless 199 * of whether or not the Tx FIFO is empty. 200 * 201 * 1 STOP is issued after this byte, regardless of 202 * whether or not the Tx FIFO is empty. If the 203 * Tx FIFO is not empty the master immediately tries 204 * to start a new transfer by issuing a START and 205 * arbitrating for the bus. 206 * 207 * i.e. the STOP is issued along with this byte, 208 * within the write stream. 209 * 210 * COMMAND - RW Control whether a read or write is performed. 211 * 212 * 0 WRITE 213 * 214 * 1 READ 215 * 216 * DATA (7:0) - RW Contains the data to be transmitted or received 217 * on the I2C bus. 218 * 219 * NOTE: Writing to this register causes a START + slave + RW to be 220 * issued if the direction has changed or the last data byte was 221 * sent with a STOP. 222 * 223 * NOTE: We control termination? so this register must be written 224 * for each byte we wish to receive. We can then drain the 225 * receive FIFO. 226 */ 227 228 #define IG4_DATA_RESTART 0x0400 /* Force RESTART */ 229 #define IG4_DATA_STOP 0x0200 /* Force STOP[+START] */ 230 #define IG4_DATA_COMMAND_RD 0x0100 /* bus direction 0=write 1=read */ 231 #define IG4_DATA_MASK 0x00FF 232 233 /* 234 * SS_SCL_HCNT - Standard Speed Clock High Count Register 22.2.4 235 * SS_SCL_LCNT - Standard Speed Clock Low Count Register 22.2.5 236 * FS_SCL_HCNT - Fast Speed Clock High Count Register 22.2.6 237 * FS_SCL_LCNT - Fast Speed Clock Low Count Register 22.2.7 238 * 239 * COUNT (15:0) - Set the period count to a value between 6 and 240 * 65525. 241 */ 242 #define IG4_SCL_CLOCK_MASK 0xFFFFU /* count bits in register */ 243 244 /* 245 * INTR_STAT - (RO) Interrupt Status Register 22.2.8 246 * INTR_MASK - (RW) Interrupt Mask Register 22.2.9 247 * RAW_INTR_STAT- (RO) Raw Interrupt Status Register 22.2.10 248 * 249 * GEN_CALL Set only when a general call (broadcast) address 250 * is received and acknowleged, stays set until 251 * cleared by reading CLR_GEN_CALL. 252 * 253 * START_DET Set when a START or RESTART condition has occurred 254 * on the interface. 255 * 256 * STOP_DET Set when a STOP condition has occurred on the 257 * interface. 258 * 259 * ACTIVITY Set by any activity on the interface. Cleared 260 * by reading CLR_ACTIVITY or CLR_INTR. 261 * 262 * TX_ABRT Indicates the controller as a transmitter is 263 * unable to complete the intended action. When set, 264 * the controller will hold the TX FIFO in a reset 265 * state (flushed) until CLR_TX_ABORT is read to 266 * clear the condition. Once cleared, the TX FIFO 267 * will be available again. 268 * 269 * TX_EMPTY Indicates that the transmitter is at or below 270 * the specified TX_TL threshold. Automatically 271 * cleared by HW when the buffer level goes above 272 * the threshold. 273 * 274 * TX_OVER Indicates that the processor attempted to write 275 * to the TX FIFO while the TX FIFO was full. Cleared 276 * by reading CLR_TX_OVER. 277 * 278 * RX_FULL Indicates that the receive FIFO has reached or 279 * exceeded the specified RX_TL threshold. Cleared 280 * by HW when the cpu drains the FIFO to below the 281 * threshold. 282 * 283 * RX_OVER Indicates that the receive FIFO was unable to 284 * accept new data and data was lost. Cleared by 285 * reading CLR_RX_OVER. 286 * 287 * RX_UNDER Indicates that the cpu attempted to read data 288 * from the receive buffer while the RX FIFO was 289 * empty. Cleared by reading CLR_RX_UNDER. 290 * 291 * NOTES ON RAW_INTR_STAT: 292 * 293 * This register can be used to monitor the GEN_CALL, START_DET, 294 * STOP_DET, ACTIVITY, TX_ABRT, TX_EMPTY, TX_OVER, RX_FULL, RX_OVER, 295 * and RX_UNDER bits. The documentation is a bit unclear but presumably 296 * this is the unlatched version. 297 * 298 * Code should test FIFO conditions using the I2C_STA (status) register, 299 * not the interrupt status registers. 300 */ 301 302 #define IG4_INTR_GEN_CALL 0x0800 303 #define IG4_INTR_START_DET 0x0400 304 #define IG4_INTR_STOP_DET 0x0200 305 #define IG4_INTR_ACTIVITY 0x0100 306 #define IG4_INTR_TX_ABRT 0x0040 307 #define IG4_INTR_TX_EMPTY 0x0010 308 #define IG4_INTR_TX_OVER 0x0008 309 #define IG4_INTR_RX_FULL 0x0004 310 #define IG4_INTR_RX_OVER 0x0002 311 #define IG4_INTR_RX_UNDER 0x0001 312 313 /* 314 * RX_TL - (RW) Receive FIFO Threshold Register 22.2.11 315 * TX_TL - (RW) Transmit FIFO Threshold Register 22.2.12 316 * 317 * Specify the receive and transmit FIFO threshold register. The 318 * FIFOs have 16 elements. The valid range is 0-15. Setting a 319 * value greater than 15 causes the actual value to be the maximum 320 * depth of the FIFO. 321 * 322 * Generally speaking since everything is messaged, we can use a 323 * mid-level setting for both parameters and (e.g.) fully drain the 324 * receive FIFO on the STOP_DET condition to handle loose ends. 325 */ 326 #define IG4_FIFO_MASK 0x00FF 327 #define IG4_FIFO_LIMIT 16 328 329 /* 330 * CLR_INTR - (RO) Clear Interrupt Register 22.2.13 331 * CLR_RX_UNDER - (RO) Clear Interrupt Register (specific) 22.2.14 332 * CLR_RX_OVER - (RO) Clear Interrupt Register (specific) 22.2.15 333 * CLR_TX_OVER - (RO) Clear Interrupt Register (specific) 22.2.16 334 * CLR_TX_ABORT - (RO) Clear Interrupt Register (specific) 22.2.17 335 * CLR_ACTIVITY - (RO) Clear Interrupt Register (specific) 22.2.18 336 * CLR_STOP_DET - (RO) Clear Interrupt Register (specific) 22.2.19 337 * CLR_START_DET- (RO) Clear Interrupt Register (specific) 22.2.20 338 * CLR_GEN_CALL - (RO) Clear Interrupt Register (specific) 22.2.21 339 * 340 * CLR_* specific operations clear the appropriate bit in the 341 * RAW_INTR_STAT register. Intel does not really document whether 342 * these operations clear the normal interrupt status register. 343 * 344 * CLR_INTR clears bits in the normal interrupt status register and 345 * presumably also the raw(?) register? Intel is again unclear. 346 * 347 * NOTE: CLR_INTR only clears software-clearable interrupts. Hardware 348 * clearable interrupts are controlled entirely by the hardware. 349 * CLR_INTR also clears the TX_ABRT_SOURCE register. 350 * 351 * NOTE: CLR_TX_ABORT also clears the TX_ABRT_SOURCE register and releases 352 * the TX FIFO from its flushed/reset state, allowing more writes 353 * to the TX FIFO. 354 * 355 * NOTE: CLR_ACTIVITY has no effect if the I2C bus is still active. 356 * Intel documents that the bit is automatically cleared when 357 * there is no further activity on the bus. 358 */ 359 #define IG4_CLR_BIT 0x0001 /* Reflects source */ 360 361 /* 362 * I2C_EN - (RW) I2C Enable Register 22.2.22 363 * 364 * ABORT Software can abort an I2C transfer by setting this 365 * bit. Hardware will clear the bit once the STOP has 366 * been detected. This bit can only be set while the 367 * I2C interface is enabled. 368 * 369 * I2C_ENABLE Enable the controller, else disable it. 370 * (Use I2C_ENABLE_STATUS to poll enable status 371 * & wait for changes) 372 */ 373 #define IG4_I2C_ABORT 0x0002 374 #define IG4_I2C_ENABLE 0x0001 375 376 /* 377 * I2C_STA - (RO) I2C Status Register 22.2.23 378 */ 379 #define IG4_STATUS_ACTIVITY 0x0020 /* Controller is active */ 380 #define IG4_STATUS_RX_FULL 0x0010 /* RX FIFO completely full */ 381 #define IG4_STATUS_RX_NOTEMPTY 0x0008 /* RX FIFO not empty */ 382 #define IG4_STATUS_TX_EMPTY 0x0004 /* TX FIFO completely empty */ 383 #define IG4_STATUS_TX_NOTFULL 0x0002 /* TX FIFO not full */ 384 #define IG4_STATUS_I2C_ACTIVE 0x0001 /* I2C bus is active */ 385 386 /* 387 * TXFLR - (RO) Transmit FIFO Level Register 22.2.24 388 * RXFLR - (RO) Receive FIFO Level Register 22.2.25 389 * 390 * Read the number of entries currently in the Transmit or Receive 391 * FIFOs. Note that for some reason the mask is 9 bits instead of 392 * the 8 bits the fill level controls. 393 */ 394 #define IG4_FIFOLVL_MASK 0x001F 395 396 /* 397 * SDA_HOLD - (RW) SDA Hold Time Length Register 22.2.26 398 * 399 * Set the SDA hold time length register in I2C clocks. 400 */ 401 #define IG4_SDA_HOLD_MASK 0x00FF 402 403 /* 404 * TX_ABRT_SOURCE- (RO) Transmit Abort Source Register 22.2.27 405 * 406 * Indicates the cause of a transmit abort. This can indicate a 407 * software programming error or a device expected address width 408 * mismatch or other issues. The NORESTART conditions and GENCALL_NOACK 409 * can only occur if a programming error was made in the driver software. 410 * 411 * In particular, it should be possible to detect whether any devices 412 * are on the bus by observing the GENCALL_READ status, and it might 413 * be possible to detect ADDR7 vs ADDR10 mismatches. 414 */ 415 #define IG4_ABRTSRC_TRANSFER 0x00010000 /* Abort initiated by user */ 416 #define IG4_ABRTSRC_ARBLOST 0x00001000 /* Arbitration lost */ 417 #define IG4_ABRTSRC_NORESTART_10 0x00000400 /* RESTART disabled */ 418 #define IG4_ABRTSRC_NORESTART_START 0x00000200 /* RESTART disabled */ 419 #define IG4_ABRTSRC_ACKED_START 0x00000080 /* Improper acked START */ 420 #define IG4_ABRTSRC_GENCALL_NOACK 0x00000020 /* Improper GENCALL */ 421 #define IG4_ABRTSRC_GENCALL_READ 0x00000010 /* Nobody acked GENCALL */ 422 #define IG4_ABRTSRC_TXNOACK_DATA 0x00000008 /* data phase no ACK */ 423 #define IG4_ABRTSRC_TXNOACK_ADDR10_2 0x00000004 /* addr10/1 phase no ACK */ 424 #define IG4_ABRTSRC_TXNOACK_ADDR10_1 0x00000002 /* addr10/2 phase no ACK */ 425 #define IG4_ABRTSRC_TXNOACK_ADDR7 0x00000001 /* addr7 phase no ACK */ 426 427 /* 428 * SLV_DATA_NACK - (RW) Generate Slave DATA NACK Register 22.2.28 429 * 430 * When the controller is a receiver a NACK can be generated on 431 * receipt of data. 432 * 433 * NACK_GENERATE Set to 0 for normal NACK/ACK generation. 434 * Set to 1 to generate a NACK after next data 435 * byte received. 436 * 437 */ 438 #define IG4_NACK_GENERATE 0x0001 439 440 /* 441 * DMA_CTRL - (RW) DMA Control Register 22.2.29 442 * 443 * Enables DMA on the transmit and/or receive DMA channel. 444 */ 445 #define IG4_TX_DMA_ENABLE 0x0002 446 #define IG4_RX_DMA_ENABLE 0x0001 447 448 /* 449 * DMA_TDLR - (RW) DMA Transmit Data Level Register 22.2.30 450 * DMA_RDLR - (RW) DMA Receive Data Level Register 22.2.31 451 * 452 * Similar to RX_TL and TX_TL but controls when a DMA burst occurs 453 * to empty or fill the FIFOs. Use the same IG4_FIFO_MASK and 454 * IG4_FIFO_LIMIT defines for RX_RL and TX_TL. 455 */ 456 /* empty */ 457 458 /* 459 * SDA_SETUP - (RW) SDA Setup Time Length Register 22.2.32 460 * 461 * Set the SDA setup time length register in I2C clocks. 462 * The register must be programmed with a value >=2. 463 * (Defaults to 0x64). 464 */ 465 #define IG4_SDA_SETUP_MASK 0x00FF 466 467 /* 468 * ACK_GEN_CALL - (RW) ACK General Call Register 22.2.33 469 * 470 * Control whether the controller responds with a ACK or NACK when 471 * it receives an I2C General Call address. 472 * 473 * If set to 0 a NACK is generated and a General Call interrupt is 474 * NOT generated. Otherwise an ACK + interrupt is generated. 475 */ 476 #define IG4_ACKGC_ACK 0x0001 477 478 /* 479 * ENABLE_STATUS - (RO) Enable Status Registger 22.2.34 480 * 481 * DATA_LOST - Indicates that a slave receiver operation has 482 * been aborted with at least one data byte received 483 * from a transfer due to the I2C controller being 484 * disabled (IG4_I2C_ENABLE -> 0) 485 * 486 * ENABLED - Intel documentation is lacking but I assume this 487 * is a reflection of the IG4_I2C_ENABLE bit in the 488 * I2C_EN register. 489 * 490 */ 491 #define IG4_ENASTAT_DATA_LOST 0x0004 492 #define IG4_ENASTAT_ENABLED 0x0001 493 494 /* 495 * COMP_PARAM1 - (RO) Component Parameter Register 22.2.35 496 * Default Value 0x00FFFF6E 497 * 498 * VALID - Intel documentation is unclear but I believe this 499 * must be read as a 1 to indicate that the rest of 500 * the bits in the register are valid. 501 * 502 * HASDMA - Indicates that the chip is DMA-capable. Presumably 503 * in certain virtualization cases the chip might be 504 * set to not be DMA-capable. 505 * 506 * INTR_IO - Indicates that all interrupts are combined to 507 * generate one interrupt. If not set, interrupts 508 * are individual (more virtualization stuff?) 509 * 510 * HCCNT_RO - Indicates that the clock timing registers are 511 * RW. If not set, the registers are RO. 512 * (more virtualization stuff). 513 * 514 * MAXSPEED - Indicates the maximum speed supported. 515 * 516 * DATAW - Indicates the internal bus width in bits. 517 */ 518 #define IG4_PARAM1_TXFIFO_DEPTH(v) (((v) >> 16) & 0xFF) 519 #define IG4_PARAM1_RXFIFO_DEPTH(v) (((v) >> 8) & 0xFF) 520 #define IG4_PARAM1_CONFIG_VALID 0x00000080 521 #define IG4_PARAM1_CONFIG_HASDMA 0x00000040 522 #define IG4_PARAM1_CONFIG_INTR_IO 0x00000020 523 #define IG4_PARAM1_CONFIG_HCCNT_RO 0x00000010 524 #define IG4_PARAM1_CONFIG_MAXSPEED_MASK 0x0000000C 525 #define IG4_PARAM1_CONFIG_DATAW_MASK 0x00000003 526 527 #define IG4_CONFIG_MAXSPEED_RESERVED00 0x00000000 528 #define IG4_CONFIG_MAXSPEED_STANDARD 0x00000004 529 #define IG4_CONFIG_MAXSPEED_FAST 0x00000008 530 #define IG4_CONFIG_MAXSPEED_HIGH 0x0000000C 531 532 #define IG4_CONFIG_DATAW_8 0x00000000 533 #define IG4_CONFIG_DATAW_16 0x00000001 534 #define IG4_CONFIG_DATAW_32 0x00000002 535 #define IG4_CONFIG_DATAW_RESERVED11 0x00000003 536 537 /* 538 * COMP_VER - (RO) Component Version Register 22.2.36 539 * Default Value 0x3131352A 540 * 541 * Contains the chip version number. All 32 bits. 542 */ 543 #define IG4_COMP_VER 0x3131352A 544 545 /* 546 * COMP_TYPE - (RO) (linux) Endian and bus width probe 547 * 548 * Read32 from this register and test against IG4_COMP_TYPE 549 * to determine the bus width. e.g. 01404457 = endian-reversed, 550 * and 00000140 or 00004457 means internal 16-bit bus (?). 551 * 552 * This register is not in the intel documentation, I pulled it 553 * from the linux driver i2c-designware-core.c. 554 */ 555 #define IG4_COMP_TYPE 0x44570140 556 557 /* 558 * RESETS - (RW) Resets Register 22.2.37 559 * 560 * Used to reset the I2C host controller by SW. There is no timing 561 * requirement, software can assert and de-assert in back-to-back 562 * transactions. 563 * 564 * 00 I2C host controller is NOT in reset. 565 * 01 (reserved) 566 * 10 (reserved) 567 * 11 I2C host controller is in reset. 568 */ 569 #define IG4_RESETS_ASSERT 0x0003 570 #define IG4_RESETS_DEASSERT 0x0000 571 572 /* 573 * GENERAL - (RW) General Reigster 22.2.38 574 * 575 * IOVOLT 0=1.8V 1=3.3V 576 * 577 * LTR 0=Auto 1=SW 578 * 579 * In Auto mode the BIOS will write to the host controller's 580 * AUTO LTR Value register (offset 0x0814) with the active 581 * state LTR value, and will write to the SW LTR Value register 582 * (offset 0x0810) with the idle state LTR value. 583 * 584 * In SW mode the SW will write to the host controller SW LTR 585 * value (offset 0x0810). It is the SW responsibility to update 586 * the LTR with the appropriate value. 587 */ 588 #define IG4_GENERAL_IOVOLT3_3 0x0008 589 #define IG4_GENERAL_SWMODE 0x0004 590 591 /* 592 * SW_LTR_VALUE - (RW) SW LTR Value Register 22.2.39 593 * AUTO_LTR_VALUE - (RW) SW LTR Value Register 22.2.40 594 * 595 * Default value is 0x00000800 which means the best possible 596 * service/response time. 597 * 598 * It isn't quite clear how the snooping works. There are two scale 599 * bits for both sets but two of the four codes are reserved. The 600 * *SNOOP_VALUE() is specified as a 10-bit latency value. If 0, it 601 * indicates that the device cannot tolerate any delay and needs the 602 * best possible service/response time. 603 * 604 * I think this is for snooping (testing) the I2C bus. The lowest 605 * delay (0) probably runs the controller polling at a high, power hungry 606 * rate. But I dunno. 607 */ 608 #define IG4_SWLTR_NSNOOP_REQ 0x80000000 /* (ro) */ 609 #define IG4_SWLTR_NSNOOP_SCALE_MASK 0x1C000000 /* (ro) */ 610 #define IG4_SWLTR_NSNOOP_SCALE_1US 0x08000000 /* (ro) */ 611 #define IG4_SWLTR_NSNOOP_SCALE_32US 0x0C000000 /* (ro) */ 612 #define IG4_SWLTR_NSNOOP_VALUE_DECODE(v) (((v) >> 16) & 0x3F) 613 #define IG4_SWLTR_NSNOOP_VALUE_ENCODE(v) (((v) & 0x3F) << 16) 614 615 #define IG4_SWLTR_SNOOP_REQ 0x00008000 /* (rw) */ 616 #define IG4_SWLTR_SNOOP_SCALE_MASK 0x00001C00 /* (rw) */ 617 #define IG4_SWLTR_SNOOP_SCALE_1US 0x00000800 /* (rw) */ 618 #define IG4_SWLTR_SNOOP_SCALE_32US 0x00000C00 /* (rw) */ 619 #define IG4_SWLTR_SNOOP_VALUE_DECODE(v) ((v) & 0x3F) 620 #define IG4_SWLTR_SNOOP_VALUE_ENCODE(v) ((v) & 0x3F) 621 622 #endif /* _ICHIIC_IG4_REG_H_ */ 623