1 /* $OpenBSD: if_iwmreg.h,v 1.4 2015/06/15 08:06:11 stsp Exp $ */ 2 /* $FreeBSD$ */ 3 4 /****************************************************************************** 5 * 6 * This file is provided under a dual BSD/GPLv2 license. When using or 7 * redistributing this file, you may do so under either license. 8 * 9 * GPL LICENSE SUMMARY 10 * 11 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 25 * USA 26 * 27 * The full GNU General Public License is included in this distribution 28 * in the file called COPYING. 29 * 30 * Contact Information: 31 * Intel Linux Wireless <ilw@linux.intel.com> 32 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 33 * 34 * BSD LICENSE 35 * 36 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 37 * All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 43 * * Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * * Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in 47 * the documentation and/or other materials provided with the 48 * distribution. 49 * * Neither the name Intel Corporation nor the names of its 50 * contributors may be used to endorse or promote products derived 51 * from this software without specific prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 54 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 56 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 57 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 58 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 59 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 63 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 * 65 *****************************************************************************/ 66 #ifndef __IF_IWM_REG_H__ 67 #define __IF_IWM_REG_H__ 68 69 #define le16_to_cpup(_a_) (le16toh(*(const uint16_t *)(_a_))) 70 #define le32_to_cpup(_a_) (le32toh(*(const uint32_t *)(_a_))) 71 72 /* 73 * BEGIN iwl-csr.h 74 */ 75 76 /* 77 * CSR (control and status registers) 78 * 79 * CSR registers are mapped directly into PCI bus space, and are accessible 80 * whenever platform supplies power to device, even when device is in 81 * low power states due to driver-invoked device resets 82 * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes. 83 * 84 * Use iwl_write32() and iwl_read32() family to access these registers; 85 * these provide simple PCI bus access, without waking up the MAC. 86 * Do not use iwl_write_direct32() family for these registers; 87 * no need to "grab nic access" via IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. 88 * The MAC (uCode processor, etc.) does not need to be powered up for accessing 89 * the CSR registers. 90 * 91 * NOTE: Device does need to be awake in order to read this memory 92 * via IWM_CSR_EEPROM and IWM_CSR_OTP registers 93 */ 94 #define IWM_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */ 95 #define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */ 96 #define IWM_CSR_INT (0x008) /* host interrupt status/ack */ 97 #define IWM_CSR_INT_MASK (0x00c) /* host interrupt enable */ 98 #define IWM_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/ 99 #define IWM_CSR_GPIO_IN (0x018) /* read external chip pins */ 100 #define IWM_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/ 101 #define IWM_CSR_GP_CNTRL (0x024) 102 103 /* 2nd byte of IWM_CSR_INT_COALESCING, not accessible via iwl_write32()! */ 104 #define IWM_CSR_INT_PERIODIC_REG (0x005) 105 106 /* 107 * Hardware revision info 108 * Bit fields: 109 * 31-16: Reserved 110 * 15-4: Type of device: see IWM_CSR_HW_REV_TYPE_xxx definitions 111 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D 112 * 1-0: "Dash" (-) value, as in A-1, etc. 113 */ 114 #define IWM_CSR_HW_REV (0x028) 115 116 /* 117 * EEPROM and OTP (one-time-programmable) memory reads 118 * 119 * NOTE: Device must be awake, initialized via apm_ops.init(), 120 * in order to read. 121 */ 122 #define IWM_CSR_EEPROM_REG (0x02c) 123 #define IWM_CSR_EEPROM_GP (0x030) 124 #define IWM_CSR_OTP_GP_REG (0x034) 125 126 #define IWM_CSR_GIO_REG (0x03C) 127 #define IWM_CSR_GP_UCODE_REG (0x048) 128 #define IWM_CSR_GP_DRIVER_REG (0x050) 129 130 /* 131 * UCODE-DRIVER GP (general purpose) mailbox registers. 132 * SET/CLR registers set/clear bit(s) if "1" is written. 133 */ 134 #define IWM_CSR_UCODE_DRV_GP1 (0x054) 135 #define IWM_CSR_UCODE_DRV_GP1_SET (0x058) 136 #define IWM_CSR_UCODE_DRV_GP1_CLR (0x05c) 137 #define IWM_CSR_UCODE_DRV_GP2 (0x060) 138 139 #define IWM_CSR_MBOX_SET_REG (0x088) 140 #define IWM_CSR_MBOX_SET_REG_OS_ALIVE 0x20 141 142 #define IWM_CSR_LED_REG (0x094) 143 #define IWM_CSR_DRAM_INT_TBL_REG (0x0A0) 144 #define IWM_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */ 145 146 147 /* GIO Chicken Bits (PCI Express bus link power management) */ 148 #define IWM_CSR_GIO_CHICKEN_BITS (0x100) 149 150 /* Analog phase-lock-loop configuration */ 151 #define IWM_CSR_ANA_PLL_CFG (0x20c) 152 153 /* 154 * CSR Hardware Revision Workaround Register. Indicates hardware rev; 155 * "step" determines CCK backoff for txpower calculation. Used for 4965 only. 156 * See also IWM_CSR_HW_REV register. 157 * Bit fields: 158 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step 159 * 1-0: "Dash" (-) value, as in C-1, etc. 160 */ 161 #define IWM_CSR_HW_REV_WA_REG (0x22C) 162 163 #define IWM_CSR_DBG_HPET_MEM_REG (0x240) 164 #define IWM_CSR_DBG_LINK_PWR_MGMT_REG (0x250) 165 166 /* Bits for IWM_CSR_HW_IF_CONFIG_REG */ 167 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003) 168 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C) 169 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0) 170 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) 171 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) 172 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00) 173 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000) 174 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000) 175 176 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0) 177 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2) 178 #define IWM_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6) 179 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10) 180 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12) 181 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14) 182 183 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) 184 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) 185 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */ 186 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */ 187 #define IWM_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */ 188 #define IWM_CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000) 189 #define IWM_CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */ 190 191 #define IWM_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/ 192 #define IWM_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/ 193 194 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma), 195 * acknowledged (reset) by host writing "1" to flagged bits. */ 196 #define IWM_CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ 197 #define IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ 198 #define IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ 199 #define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ 200 #define IWM_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ 201 #define IWM_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ 202 #define IWM_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ 203 #define IWM_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ 204 #define IWM_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */ 205 #define IWM_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ 206 #define IWM_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ 207 208 #define IWM_CSR_INI_SET_MASK (IWM_CSR_INT_BIT_FH_RX | \ 209 IWM_CSR_INT_BIT_HW_ERR | \ 210 IWM_CSR_INT_BIT_FH_TX | \ 211 IWM_CSR_INT_BIT_SW_ERR | \ 212 IWM_CSR_INT_BIT_RF_KILL | \ 213 IWM_CSR_INT_BIT_SW_RX | \ 214 IWM_CSR_INT_BIT_WAKEUP | \ 215 IWM_CSR_INT_BIT_ALIVE | \ 216 IWM_CSR_INT_BIT_RX_PERIODIC) 217 218 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ 219 #define IWM_CSR_FH_INT_BIT_ERR (1 << 31) /* Error */ 220 #define IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ 221 #define IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ 222 #define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ 223 #define IWM_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ 224 #define IWM_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ 225 226 #define IWM_CSR_FH_INT_RX_MASK (IWM_CSR_FH_INT_BIT_HI_PRIOR | \ 227 IWM_CSR_FH_INT_BIT_RX_CHNL1 | \ 228 IWM_CSR_FH_INT_BIT_RX_CHNL0) 229 230 #define IWM_CSR_FH_INT_TX_MASK (IWM_CSR_FH_INT_BIT_TX_CHNL1 | \ 231 IWM_CSR_FH_INT_BIT_TX_CHNL0) 232 233 /* GPIO */ 234 #define IWM_CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) 235 #define IWM_CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) 236 #define IWM_CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200) 237 238 /* RESET */ 239 #define IWM_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) 240 #define IWM_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) 241 #define IWM_CSR_RESET_REG_FLAG_SW_RESET (0x00000080) 242 #define IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) 243 #define IWM_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) 244 #define IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000) 245 246 /* 247 * GP (general purpose) CONTROL REGISTER 248 * Bit fields: 249 * 27: HW_RF_KILL_SW 250 * Indicates state of (platform's) hardware RF-Kill switch 251 * 26-24: POWER_SAVE_TYPE 252 * Indicates current power-saving mode: 253 * 000 -- No power saving 254 * 001 -- MAC power-down 255 * 010 -- PHY (radio) power-down 256 * 011 -- Error 257 * 9-6: SYS_CONFIG 258 * Indicates current system configuration, reflecting pins on chip 259 * as forced high/low by device circuit board. 260 * 4: GOING_TO_SLEEP 261 * Indicates MAC is entering a power-saving sleep power-down. 262 * Not a good time to access device-internal resources. 263 * 3: MAC_ACCESS_REQ 264 * Host sets this to request and maintain MAC wakeup, to allow host 265 * access to device-internal resources. Host must wait for 266 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR 267 * device registers. 268 * 2: INIT_DONE 269 * Host sets this to put device into fully operational D0 power mode. 270 * Host resets this after SW_RESET to put device into low power mode. 271 * 0: MAC_CLOCK_READY 272 * Indicates MAC (ucode processor, etc.) is powered up and can run. 273 * Internal resources are accessible. 274 * NOTE: This does not indicate that the processor is actually running. 275 * NOTE: This does not indicate that device has completed 276 * init or post-power-down restore of internal SRAM memory. 277 * Use IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that 278 * SRAM is restored and uCode is in normal operation mode. 279 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 280 * do not need to save/restore it. 281 * NOTE: After device reset, this bit remains "0" until host sets 282 * INIT_DONE 283 */ 284 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) 285 #define IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) 286 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) 287 #define IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) 288 289 #define IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) 290 291 #define IWM_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) 292 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000) 293 #define IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) 294 295 296 /* HW REV */ 297 #define IWM_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0) 298 #define IWM_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2) 299 300 /** 301 * hw_rev values 302 */ 303 enum { 304 IWM_SILICON_A_STEP = 0, 305 IWM_SILICON_B_STEP, 306 IWM_SILICON_C_STEP, 307 }; 308 309 310 #define IWM_CSR_HW_REV_TYPE_MSK (0x000FFF0) 311 #define IWM_CSR_HW_REV_TYPE_5300 (0x0000020) 312 #define IWM_CSR_HW_REV_TYPE_5350 (0x0000030) 313 #define IWM_CSR_HW_REV_TYPE_5100 (0x0000050) 314 #define IWM_CSR_HW_REV_TYPE_5150 (0x0000040) 315 #define IWM_CSR_HW_REV_TYPE_1000 (0x0000060) 316 #define IWM_CSR_HW_REV_TYPE_6x00 (0x0000070) 317 #define IWM_CSR_HW_REV_TYPE_6x50 (0x0000080) 318 #define IWM_CSR_HW_REV_TYPE_6150 (0x0000084) 319 #define IWM_CSR_HW_REV_TYPE_6x05 (0x00000B0) 320 #define IWM_CSR_HW_REV_TYPE_6x30 IWM_CSR_HW_REV_TYPE_6x05 321 #define IWM_CSR_HW_REV_TYPE_6x35 IWM_CSR_HW_REV_TYPE_6x05 322 #define IWM_CSR_HW_REV_TYPE_2x30 (0x00000C0) 323 #define IWM_CSR_HW_REV_TYPE_2x00 (0x0000100) 324 #define IWM_CSR_HW_REV_TYPE_105 (0x0000110) 325 #define IWM_CSR_HW_REV_TYPE_135 (0x0000120) 326 #define IWM_CSR_HW_REV_TYPE_7265D (0x0000210) 327 #define IWM_CSR_HW_REV_TYPE_NONE (0x00001F0) 328 329 /* EEPROM REG */ 330 #define IWM_CSR_EEPROM_REG_READ_VALID_MSK (0x00000001) 331 #define IWM_CSR_EEPROM_REG_BIT_CMD (0x00000002) 332 #define IWM_CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC) 333 #define IWM_CSR_EEPROM_REG_MSK_DATA (0xFFFF0000) 334 335 /* EEPROM GP */ 336 #define IWM_CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */ 337 #define IWM_CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180) 338 #define IWM_CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000) 339 #define IWM_CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001) 340 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002) 341 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004) 342 343 /* One-time-programmable memory general purpose reg */ 344 #define IWM_CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */ 345 #define IWM_CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */ 346 #define IWM_CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */ 347 #define IWM_CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */ 348 349 /* GP REG */ 350 #define IWM_CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */ 351 #define IWM_CSR_GP_REG_NO_POWER_SAVE (0x00000000) 352 #define IWM_CSR_GP_REG_MAC_POWER_SAVE (0x01000000) 353 #define IWM_CSR_GP_REG_PHY_POWER_SAVE (0x02000000) 354 #define IWM_CSR_GP_REG_POWER_SAVE_ERROR (0x03000000) 355 356 357 /* CSR GIO */ 358 #define IWM_CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002) 359 360 /* 361 * UCODE-DRIVER GP (general purpose) mailbox register 1 362 * Host driver and uCode write and/or read this register to communicate with 363 * each other. 364 * Bit fields: 365 * 4: UCODE_DISABLE 366 * Host sets this to request permanent halt of uCode, same as 367 * sending CARD_STATE command with "halt" bit set. 368 * 3: CT_KILL_EXIT 369 * Host sets this to request exit from CT_KILL state, i.e. host thinks 370 * device temperature is low enough to continue normal operation. 371 * 2: CMD_BLOCKED 372 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL) 373 * to release uCode to clear all Tx and command queues, enter 374 * unassociated mode, and power down. 375 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit. 376 * 1: SW_BIT_RFKILL 377 * Host sets this when issuing CARD_STATE command to request 378 * device sleep. 379 * 0: MAC_SLEEP 380 * uCode sets this when preparing a power-saving power-down. 381 * uCode resets this when power-up is complete and SRAM is sane. 382 * NOTE: device saves internal SRAM data to host when powering down, 383 * and must restore this data after powering back up. 384 * MAC_SLEEP is the best indication that restore is complete. 385 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 386 * do not need to save/restore it. 387 */ 388 #define IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) 389 #define IWM_CSR_UCODE_SW_BIT_RFKILL (0x00000002) 390 #define IWM_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) 391 #define IWM_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) 392 #define IWM_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020) 393 394 /* GP Driver */ 395 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003) 396 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000) 397 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001) 398 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002) 399 #define IWM_CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004) 400 #define IWM_CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008) 401 402 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080) 403 404 /* GIO Chicken Bits (PCI Express bus link power management) */ 405 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) 406 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) 407 408 /* LED */ 409 #define IWM_CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF) 410 #define IWM_CSR_LED_REG_TURN_ON (0x60) 411 #define IWM_CSR_LED_REG_TURN_OFF (0x20) 412 413 /* ANA_PLL */ 414 #define IWM_CSR50_ANA_PLL_CFG_VAL (0x00880300) 415 416 /* HPET MEM debug */ 417 #define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) 418 419 /* DRAM INT TABLE */ 420 #define IWM_CSR_DRAM_INT_TBL_ENABLE (1 << 31) 421 #define IWM_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28) 422 #define IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) 423 424 /* SECURE boot registers */ 425 #define IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100) 426 enum iwm_secure_boot_config_reg { 427 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP = 0x00000001, 428 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ = 0x00000002, 429 }; 430 431 #define IWM_CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100) 432 #define IWM_CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100) 433 enum iwm_secure_boot_status_reg { 434 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS = 0x00000003, 435 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED = 0x00000002, 436 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS = 0x00000004, 437 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL = 0x00000008, 438 IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL = 0x00000010, 439 }; 440 441 #define IWM_FH_UCODE_LOAD_STATUS 0x1af0 442 #define IWM_CSR_UCODE_LOAD_STATUS_ADDR 0x1e70 443 enum iwm_secure_load_status_reg { 444 IWM_LMPM_CPU_UCODE_LOADING_STARTED = 0x00000001, 445 IWM_LMPM_CPU_HDRS_LOADING_COMPLETED = 0x00000003, 446 IWM_LMPM_CPU_UCODE_LOADING_COMPLETED = 0x00000007, 447 IWM_LMPM_CPU_STATUS_NUM_OF_LAST_COMPLETED = 0x000000F8, 448 IWM_LMPM_CPU_STATUS_NUM_OF_LAST_LOADED_BLOCK = 0x0000FF00, 449 }; 450 #define IWM_FH_MEM_TB_MAX_LENGTH 0x20000 451 452 #define IWM_LMPM_SECURE_INSPECTOR_CODE_ADDR 0x1e38 453 #define IWM_LMPM_SECURE_INSPECTOR_DATA_ADDR 0x1e3c 454 #define IWM_LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR 0x1e78 455 #define IWM_LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR 0x1e7c 456 457 #define IWM_LMPM_SECURE_INSPECTOR_CODE_MEM_SPACE 0x400000 458 #define IWM_LMPM_SECURE_INSPECTOR_DATA_MEM_SPACE 0x402000 459 #define IWM_LMPM_SECURE_CPU1_HDR_MEM_SPACE 0x420000 460 #define IWM_LMPM_SECURE_CPU2_HDR_MEM_SPACE 0x420400 461 462 #define IWM_CSR_SECURE_TIME_OUT (100) 463 464 /* extended range in FW SRAM */ 465 #define IWM_FW_MEM_EXTENDED_START 0x40000 466 #define IWM_FW_MEM_EXTENDED_END 0x57FFF 467 468 /* FW chicken bits */ 469 #define IWM_LMPM_CHICK 0xa01ff8 470 #define IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE 0x01 471 472 #define IWM_FH_TCSR_0_REG0 (0x1D00) 473 474 /* 475 * HBUS (Host-side Bus) 476 * 477 * HBUS registers are mapped directly into PCI bus space, but are used 478 * to indirectly access device's internal memory or registers that 479 * may be powered-down. 480 * 481 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers; 482 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ 483 * to make sure the MAC (uCode processor, etc.) is powered up for accessing 484 * internal resources. 485 * 486 * Do not use iwl_write32()/iwl_read32() family to access these registers; 487 * these provide only simple PCI bus access, without waking up the MAC. 488 */ 489 #define IWM_HBUS_BASE (0x400) 490 491 /* 492 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM 493 * structures, error log, event log, verifying uCode load). 494 * First write to address register, then read from or write to data register 495 * to complete the job. Once the address register is set up, accesses to 496 * data registers auto-increment the address by one dword. 497 * Bit usage for address registers (read or write): 498 * 0-31: memory address within device 499 */ 500 #define IWM_HBUS_TARG_MEM_RADDR (IWM_HBUS_BASE+0x00c) 501 #define IWM_HBUS_TARG_MEM_WADDR (IWM_HBUS_BASE+0x010) 502 #define IWM_HBUS_TARG_MEM_WDAT (IWM_HBUS_BASE+0x018) 503 #define IWM_HBUS_TARG_MEM_RDAT (IWM_HBUS_BASE+0x01c) 504 505 /* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */ 506 #define IWM_HBUS_TARG_MBX_C (IWM_HBUS_BASE+0x030) 507 #define IWM_HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) 508 509 /* 510 * Registers for accessing device's internal peripheral registers 511 * (e.g. SCD, BSM, etc.). First write to address register, 512 * then read from or write to data register to complete the job. 513 * Bit usage for address registers (read or write): 514 * 0-15: register address (offset) within device 515 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) 516 */ 517 #define IWM_HBUS_TARG_PRPH_WADDR (IWM_HBUS_BASE+0x044) 518 #define IWM_HBUS_TARG_PRPH_RADDR (IWM_HBUS_BASE+0x048) 519 #define IWM_HBUS_TARG_PRPH_WDAT (IWM_HBUS_BASE+0x04c) 520 #define IWM_HBUS_TARG_PRPH_RDAT (IWM_HBUS_BASE+0x050) 521 522 /* enable the ID buf for read */ 523 #define IWM_WFPM_PS_CTL_CLR 0xa0300c 524 #define IWM_WFMP_MAC_ADDR_0 0xa03080 525 #define IWM_WFMP_MAC_ADDR_1 0xa03084 526 #define IWM_LMPM_PMG_EN 0xa01cec 527 #define IWM_RADIO_REG_SYS_MANUAL_DFT_0 0xad4078 528 #define IWM_RFIC_REG_RD 0xad0470 529 #define IWM_WFPM_CTRL_REG 0xa03030 530 #define IWM_WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK 0x08000000 531 #define IWM_ENABLE_WFPM 0x80000000 532 533 #define IWM_AUX_MISC_REG 0xa200b0 534 #define IWM_HW_STEP_LOCATION_BITS 24 535 536 #define IWM_AUX_MISC_MASTER1_EN 0xa20818 537 #define IWM_AUX_MISC_MASTER1_EN_SBE_MSK 0x1 538 #define IWM_AUX_MISC_MASTER1_SMPHR_STATUS 0xa20800 539 #define IWM_RSA_ENABLE 0xa24b08 540 #define IWM_PREG_AUX_BUS_WPROT_0 0xa04cc0 541 #define IWM_SB_CFG_OVERRIDE_ADDR 0xa26c78 542 #define IWM_SB_CFG_OVERRIDE_ENABLE 0x8000 543 #define IWM_SB_CFG_BASE_OVERRIDE 0xa20000 544 #define IWM_SB_MODIFY_CFG_FLAG 0xa03088 545 #define IWM_SB_CPU_1_STATUS 0xa01e30 546 #define IWM_SB_CPU_2_STATUS 0Xa01e34 547 548 /* Used to enable DBGM */ 549 #define IWM_HBUS_TARG_TEST_REG (IWM_HBUS_BASE+0x05c) 550 551 /* 552 * Per-Tx-queue write pointer (index, really!) 553 * Indicates index to next TFD that driver will fill (1 past latest filled). 554 * Bit usage: 555 * 0-7: queue write index 556 * 11-8: queue selector 557 */ 558 #define IWM_HBUS_TARG_WRPTR (IWM_HBUS_BASE+0x060) 559 560 /********************************************************** 561 * CSR values 562 **********************************************************/ 563 /* 564 * host interrupt timeout value 565 * used with setting interrupt coalescing timer 566 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit 567 * 568 * default interrupt coalescing timer is 64 x 32 = 2048 usecs 569 */ 570 #define IWM_HOST_INT_TIMEOUT_MAX (0xFF) 571 #define IWM_HOST_INT_TIMEOUT_DEF (0x40) 572 #define IWM_HOST_INT_TIMEOUT_MIN (0x0) 573 #define IWM_HOST_INT_OPER_MODE (1 << 31) 574 575 /***************************************************************************** 576 * 7000/3000 series SHR DTS addresses * 577 *****************************************************************************/ 578 579 /* Diode Results Register Structure: */ 580 enum iwm_dtd_diode_reg { 581 IWM_DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */ 582 IWM_DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */ 583 IWM_DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */ 584 IWM_DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */ 585 IWM_DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */ 586 IWM_DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */ 587 /* Those are the masks INSIDE the flags bit-field: */ 588 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0, 589 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */ 590 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7, 591 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */ 592 }; 593 594 /* 595 * END iwl-csr.h 596 */ 597 598 /* 599 * BEGIN iwl-fw.h 600 */ 601 602 /** 603 * enum iwm_ucode_tlv_flag - ucode API flags 604 * @IWM_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously 605 * was a separate TLV but moved here to save space. 606 * @IWM_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID, 607 * treats good CRC threshold as a boolean 608 * @IWM_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). 609 * @IWM_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P. 610 * @IWM_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS 611 * @IWM_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD 612 * @IWM_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan 613 * offload profile config command. 614 * @IWM_UCODE_TLV_FLAGS_RX_ENERGY_API: supports rx signal strength api 615 * @IWM_UCODE_TLV_FLAGS_TIME_EVENT_API_V2: using the new time event API. 616 * @IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six 617 * (rather than two) IPv6 addresses 618 * @IWM_UCODE_TLV_FLAGS_BF_UPDATED: new beacon filtering API 619 * @IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element 620 * from the probe request template. 621 * @IWM_UCODE_TLV_FLAGS_D3_CONTINUITY_API: modified D3 API to allow keeping 622 * connection when going back to D0 623 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version) 624 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version) 625 * @IWM_UCODE_TLV_FLAGS_SCHED_SCAN: this uCode image supports scheduled scan. 626 * @IWM_UCODE_TLV_FLAGS_STA_KEY_CMD: new ADD_STA and ADD_STA_KEY command API 627 * @IWM_UCODE_TLV_FLAGS_DEVICE_PS_CMD: support device wide power command 628 * containing CAM (Continuous Active Mode) indication. 629 * @IWM_UCODE_TLV_FLAGS_P2P_PS: P2P client power save is supported (only on a 630 * single bound interface). 631 * @IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT: General support for uAPSD 632 * @IWM_UCODE_TLV_FLAGS_EBS_SUPPORT: this uCode image supports EBS. 633 * @IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save 634 * @IWM_UCODE_TLV_FLAGS_BCAST_FILTERING: uCode supports broadcast filtering. 635 * @IWM_UCODE_TLV_FLAGS_GO_UAPSD: AP/GO interfaces support uAPSD clients 636 * 637 */ 638 enum iwm_ucode_tlv_flag { 639 IWM_UCODE_TLV_FLAGS_PAN = (1 << 0), 640 IWM_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1), 641 IWM_UCODE_TLV_FLAGS_MFP = (1 << 2), 642 IWM_UCODE_TLV_FLAGS_P2P = (1 << 3), 643 IWM_UCODE_TLV_FLAGS_DW_BC_TABLE = (1 << 4), 644 IWM_UCODE_TLV_FLAGS_NEWBT_COEX = (1 << 5), 645 IWM_UCODE_TLV_FLAGS_PM_CMD_SUPPORT = (1 << 6), 646 IWM_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7), 647 IWM_UCODE_TLV_FLAGS_RX_ENERGY_API = (1 << 8), 648 IWM_UCODE_TLV_FLAGS_TIME_EVENT_API_V2 = (1 << 9), 649 IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10), 650 IWM_UCODE_TLV_FLAGS_BF_UPDATED = (1 << 11), 651 IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12), 652 IWM_UCODE_TLV_FLAGS_D3_CONTINUITY_API = (1 << 14), 653 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15), 654 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16), 655 IWM_UCODE_TLV_FLAGS_SCHED_SCAN = (1 << 17), 656 IWM_UCODE_TLV_FLAGS_STA_KEY_CMD = (1 << 19), 657 IWM_UCODE_TLV_FLAGS_DEVICE_PS_CMD = (1 << 20), 658 IWM_UCODE_TLV_FLAGS_P2P_PS = (1 << 21), 659 IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_DCM = (1 << 22), 660 IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_SCM = (1 << 23), 661 IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT = (1 << 24), 662 IWM_UCODE_TLV_FLAGS_EBS_SUPPORT = (1 << 25), 663 IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD = (1 << 26), 664 IWM_UCODE_TLV_FLAGS_BCAST_FILTERING = (1 << 29), 665 IWM_UCODE_TLV_FLAGS_GO_UAPSD = (1 << 30), 666 IWM_UCODE_TLV_FLAGS_LTE_COEX = (1 << 31), 667 }; 668 669 #define IWM_UCODE_TLV_FLAG_BITS \ 670 "\020\1PAN\2NEWSCAN\3MFP\4P2P\5DW_BC_TABLE\6NEWBT_COEX\7PM_CMD\10SHORT_BL\11RX_ENERG \ 671 Y\12TIME_EVENT_V2\13D3_6_IPV6\14BF_UPDATED\15NO_BASIC_SSID\17D3_CONTINUITY\20NEW_NSOFF \ 672 L_S\21NEW_NSOFFL_L\22SCHED_SCAN\24STA_KEY_CMD\25DEVICE_PS_CMD\26P2P_PS\27P2P_PS_DCM\30 \ 673 P2P_PS_SCM\31UAPSD_SUPPORT\32EBS\33P2P_PS_UAPSD\36BCAST_FILTERING\37GO_UAPSD\40LTE_COEX" 674 675 /** 676 * enum iwm_ucode_tlv_api - ucode api 677 * @IWM_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time 678 * longer than the passive one, which is essential for fragmented scan. 679 * @IWM_UCODE_TLV_API_WIFI_MCC_UPDATE: ucode supports MCC updates with source. 680 * @IWM_UCODE_TLV_API_WIDE_CMD_HDR: ucode supports wide command header 681 * @IWM_UCODE_TLV_API_LQ_SS_PARAMS: Configure STBC/BFER via LQ CMD ss_params 682 * @IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY: scan APIs use 8-level priority 683 * instead of 3. 684 * @IWM_UCODE_TLV_API_TX_POWER_CHAIN: TX power API has larger command size 685 * (command version 3) that supports per-chain limits 686 * 687 * @IWM_NUM_UCODE_TLV_API: number of bits used 688 */ 689 enum iwm_ucode_tlv_api { 690 IWM_UCODE_TLV_API_FRAGMENTED_SCAN = (1 << 8), 691 IWM_UCODE_TLV_API_WIFI_MCC_UPDATE = (1 << 9), 692 IWM_UCODE_TLV_API_WIDE_CMD_HDR = (1 << 14), 693 IWM_UCODE_TLV_API_LQ_SS_PARAMS = (1 << 18), 694 IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY = (1 << 24), 695 IWM_UCODE_TLV_API_TX_POWER_CHAIN = (1 << 27), 696 697 IWM_NUM_UCODE_TLV_API = 32 698 }; 699 700 #define IWM_UCODE_TLV_API_BITS \ 701 "\020\10FRAGMENTED_SCAN\11WIFI_MCC_UPDATE\16WIDE_CMD_HDR\22LQ_SS_PARAMS\30EXT_SCAN_PRIO\33TX_POWER_CHAIN" 702 703 /** 704 * enum iwm_ucode_tlv_capa - ucode capabilities 705 * @IWM_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3 706 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT: supports Location Aware Regulatory 707 * @IWM_UCODE_TLV_CAPA_UMAC_SCAN: supports UMAC scan. 708 * @IWM_UCODE_TLV_CAPA_BEAMFORMER: supports Beamformer 709 * @IWM_UCODE_TLV_CAPA_TOF_SUPPORT: supports Time of Flight (802.11mc FTM) 710 * @IWM_UCODE_TLV_CAPA_TDLS_SUPPORT: support basic TDLS functionality 711 * @IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT: supports insertion of current 712 * tx power value into TPC Report action frame and Link Measurement Report 713 * action frame 714 * @IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT: supports updating current 715 * channel in DS parameter set element in probe requests. 716 * @IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT: supports adding TPC Report IE in 717 * probe requests. 718 * @IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT: supports Quiet Period requests 719 * @IWM_UCODE_TLV_CAPA_DQA_SUPPORT: supports dynamic queue allocation (DQA), 720 * which also implies support for the scheduler configuration command 721 * @IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH: supports TDLS channel switching 722 * @IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG: Consolidated D3-D0 image 723 * @IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT: supports Hot Spot Command 724 * @IWM_UCODE_TLV_CAPA_DC2DC_SUPPORT: supports DC2DC Command 725 * @IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT: supports 2G coex Command 726 * @IWM_UCODE_TLV_CAPA_CSUM_SUPPORT: supports TCP Checksum Offload 727 * @IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS: support radio and beacon statistics 728 * @IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD: support p2p standalone U-APSD 729 * @IWM_UCODE_TLV_CAPA_BT_COEX_PLCR: enabled BT Coex packet level co-running 730 * @IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC: ucode supports LAR updates with different 731 * sources for the MCC. This TLV bit is a future replacement to 732 * IWM_UCODE_TLV_API_WIFI_MCC_UPDATE. When either is set, multi-source LAR 733 * is supported. 734 * @IWM_UCODE_TLV_CAPA_BT_COEX_RRC: supports BT Coex RRC 735 * @IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT: supports gscan 736 * @IWM_UCODE_TLV_CAPA_NAN_SUPPORT: supports NAN 737 * @IWM_UCODE_TLV_CAPA_UMAC_UPLOAD: supports upload mode in umac (1=supported, 738 * 0=no support) 739 * @IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE: extended DTS measurement 740 * @IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS: supports short PM timeouts 741 * @IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT: supports bt-coex Multi-priority LUT 742 * @IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION: firmware will decide on what 743 * antenna the beacon should be transmitted 744 * @IWM_UCODE_TLV_CAPA_BEACON_STORING: firmware will store the latest beacon 745 * from AP and will send it upon d0i3 exit. 746 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2: support LAR API V2 747 * @IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW: firmware responsible for CT-kill 748 * @IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT: supports temperature 749 * thresholds reporting 750 * @IWM_UCODE_TLV_CAPA_CTDP_SUPPORT: supports cTDP command 751 * @IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED: supports usniffer enabled in 752 * regular image. 753 * @IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG: support getting more shared 754 * memory addresses from the firmware. 755 * @IWM_UCODE_TLV_CAPA_LQM_SUPPORT: supports Link Quality Measurement 756 * @IWM_UCODE_TLV_CAPA_LMAC_UPLOAD: supports upload mode in lmac (1=supported, 757 * 0=no support) 758 * 759 * @IWM_NUM_UCODE_TLV_CAPA: number of bits used 760 */ 761 enum iwm_ucode_tlv_capa { 762 IWM_UCODE_TLV_CAPA_D0I3_SUPPORT = 0, 763 IWM_UCODE_TLV_CAPA_LAR_SUPPORT = 1, 764 IWM_UCODE_TLV_CAPA_UMAC_SCAN = 2, 765 IWM_UCODE_TLV_CAPA_BEAMFORMER = 3, 766 IWM_UCODE_TLV_CAPA_TOF_SUPPORT = 5, 767 IWM_UCODE_TLV_CAPA_TDLS_SUPPORT = 6, 768 IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT = 8, 769 IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT = 9, 770 IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT = 10, 771 IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT = 11, 772 IWM_UCODE_TLV_CAPA_DQA_SUPPORT = 12, 773 IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH = 13, 774 IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG = 17, 775 IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT = 18, 776 IWM_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT = 19, 777 IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT = 20, 778 IWM_UCODE_TLV_CAPA_CSUM_SUPPORT = 21, 779 IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS = 22, 780 IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD = 26, 781 IWM_UCODE_TLV_CAPA_BT_COEX_PLCR = 28, 782 IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC = 29, 783 IWM_UCODE_TLV_CAPA_BT_COEX_RRC = 30, 784 IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT = 31, 785 IWM_UCODE_TLV_CAPA_NAN_SUPPORT = 34, 786 IWM_UCODE_TLV_CAPA_UMAC_UPLOAD = 35, 787 IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE = 64, 788 IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS = 65, 789 IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT = 67, 790 IWM_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT = 68, 791 IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION = 71, 792 IWM_UCODE_TLV_CAPA_BEACON_STORING = 72, 793 IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2 = 73, 794 IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW = 74, 795 IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT = 75, 796 IWM_UCODE_TLV_CAPA_CTDP_SUPPORT = 76, 797 IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED = 77, 798 IWM_UCODE_TLV_CAPA_LMAC_UPLOAD = 79, 799 IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG = 80, 800 IWM_UCODE_TLV_CAPA_LQM_SUPPORT = 81, 801 802 IWM_NUM_UCODE_TLV_CAPA = 128 803 }; 804 805 /* The default calibrate table size if not specified by firmware file */ 806 #define IWM_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18 807 #define IWM_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE 19 808 #define IWM_MAX_PHY_CALIBRATE_TBL_SIZE 253 809 810 /* The default max probe length if not specified by the firmware file */ 811 #define IWM_DEFAULT_MAX_PROBE_LENGTH 200 812 813 /* 814 * enumeration of ucode section. 815 * This enumeration is used directly for older firmware (before 16.0). 816 * For new firmware, there can be up to 4 sections (see below) but the 817 * first one packaged into the firmware file is the DATA section and 818 * some debugging code accesses that. 819 */ 820 enum iwm_ucode_sec { 821 IWM_UCODE_SECTION_DATA, 822 IWM_UCODE_SECTION_INST, 823 }; 824 /* 825 * For 16.0 uCode and above, there is no differentiation between sections, 826 * just an offset to the HW address. 827 */ 828 #define IWM_CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC 829 #define IWM_PAGING_SEPARATOR_SECTION 0xAAAABBBB 830 831 /* uCode version contains 4 values: Major/Minor/API/Serial */ 832 #define IWM_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24) 833 #define IWM_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16) 834 #define IWM_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8) 835 #define IWM_UCODE_SERIAL(ver) ((ver) & 0x000000FF) 836 837 /* 838 * Calibration control struct. 839 * Sent as part of the phy configuration command. 840 * @flow_trigger: bitmap for which calibrations to perform according to 841 * flow triggers. 842 * @event_trigger: bitmap for which calibrations to perform according to 843 * event triggers. 844 */ 845 struct iwm_tlv_calib_ctrl { 846 uint32_t flow_trigger; 847 uint32_t event_trigger; 848 } __packed; 849 850 enum iwm_fw_phy_cfg { 851 IWM_FW_PHY_CFG_RADIO_TYPE_POS = 0, 852 IWM_FW_PHY_CFG_RADIO_TYPE = 0x3 << IWM_FW_PHY_CFG_RADIO_TYPE_POS, 853 IWM_FW_PHY_CFG_RADIO_STEP_POS = 2, 854 IWM_FW_PHY_CFG_RADIO_STEP = 0x3 << IWM_FW_PHY_CFG_RADIO_STEP_POS, 855 IWM_FW_PHY_CFG_RADIO_DASH_POS = 4, 856 IWM_FW_PHY_CFG_RADIO_DASH = 0x3 << IWM_FW_PHY_CFG_RADIO_DASH_POS, 857 IWM_FW_PHY_CFG_TX_CHAIN_POS = 16, 858 IWM_FW_PHY_CFG_TX_CHAIN = 0xf << IWM_FW_PHY_CFG_TX_CHAIN_POS, 859 IWM_FW_PHY_CFG_RX_CHAIN_POS = 20, 860 IWM_FW_PHY_CFG_RX_CHAIN = 0xf << IWM_FW_PHY_CFG_RX_CHAIN_POS, 861 }; 862 863 #define IWM_UCODE_MAX_CS 1 864 865 /** 866 * struct iwm_fw_cipher_scheme - a cipher scheme supported by FW. 867 * @cipher: a cipher suite selector 868 * @flags: cipher scheme flags (currently reserved for a future use) 869 * @hdr_len: a size of MPDU security header 870 * @pn_len: a size of PN 871 * @pn_off: an offset of pn from the beginning of the security header 872 * @key_idx_off: an offset of key index byte in the security header 873 * @key_idx_mask: a bit mask of key_idx bits 874 * @key_idx_shift: bit shift needed to get key_idx 875 * @mic_len: mic length in bytes 876 * @hw_cipher: a HW cipher index used in host commands 877 */ 878 struct iwm_fw_cipher_scheme { 879 uint32_t cipher; 880 uint8_t flags; 881 uint8_t hdr_len; 882 uint8_t pn_len; 883 uint8_t pn_off; 884 uint8_t key_idx_off; 885 uint8_t key_idx_mask; 886 uint8_t key_idx_shift; 887 uint8_t mic_len; 888 uint8_t hw_cipher; 889 } __packed; 890 891 /** 892 * struct iwm_fw_cscheme_list - a cipher scheme list 893 * @size: a number of entries 894 * @cs: cipher scheme entries 895 */ 896 struct iwm_fw_cscheme_list { 897 uint8_t size; 898 struct iwm_fw_cipher_scheme cs[]; 899 } __packed; 900 901 /* 902 * END iwl-fw.h 903 */ 904 905 /* 906 * BEGIN iwl-fw-file.h 907 */ 908 909 /* v1/v2 uCode file layout */ 910 struct iwm_ucode_header { 911 uint32_t ver; /* major/minor/API/serial */ 912 union { 913 struct { 914 uint32_t inst_size; /* bytes of runtime code */ 915 uint32_t data_size; /* bytes of runtime data */ 916 uint32_t init_size; /* bytes of init code */ 917 uint32_t init_data_size; /* bytes of init data */ 918 uint32_t boot_size; /* bytes of bootstrap code */ 919 uint8_t data[0]; /* in same order as sizes */ 920 } v1; 921 struct { 922 uint32_t build; /* build number */ 923 uint32_t inst_size; /* bytes of runtime code */ 924 uint32_t data_size; /* bytes of runtime data */ 925 uint32_t init_size; /* bytes of init code */ 926 uint32_t init_data_size; /* bytes of init data */ 927 uint32_t boot_size; /* bytes of bootstrap code */ 928 uint8_t data[0]; /* in same order as sizes */ 929 } v2; 930 } u; 931 }; 932 933 /* 934 * new TLV uCode file layout 935 * 936 * The new TLV file format contains TLVs, that each specify 937 * some piece of data. 938 */ 939 940 enum iwm_ucode_tlv_type { 941 IWM_UCODE_TLV_INVALID = 0, /* unused */ 942 IWM_UCODE_TLV_INST = 1, 943 IWM_UCODE_TLV_DATA = 2, 944 IWM_UCODE_TLV_INIT = 3, 945 IWM_UCODE_TLV_INIT_DATA = 4, 946 IWM_UCODE_TLV_BOOT = 5, 947 IWM_UCODE_TLV_PROBE_MAX_LEN = 6, /* a uint32_t value */ 948 IWM_UCODE_TLV_PAN = 7, 949 IWM_UCODE_TLV_RUNT_EVTLOG_PTR = 8, 950 IWM_UCODE_TLV_RUNT_EVTLOG_SIZE = 9, 951 IWM_UCODE_TLV_RUNT_ERRLOG_PTR = 10, 952 IWM_UCODE_TLV_INIT_EVTLOG_PTR = 11, 953 IWM_UCODE_TLV_INIT_EVTLOG_SIZE = 12, 954 IWM_UCODE_TLV_INIT_ERRLOG_PTR = 13, 955 IWM_UCODE_TLV_ENHANCE_SENS_TBL = 14, 956 IWM_UCODE_TLV_PHY_CALIBRATION_SIZE = 15, 957 IWM_UCODE_TLV_WOWLAN_INST = 16, 958 IWM_UCODE_TLV_WOWLAN_DATA = 17, 959 IWM_UCODE_TLV_FLAGS = 18, 960 IWM_UCODE_TLV_SEC_RT = 19, 961 IWM_UCODE_TLV_SEC_INIT = 20, 962 IWM_UCODE_TLV_SEC_WOWLAN = 21, 963 IWM_UCODE_TLV_DEF_CALIB = 22, 964 IWM_UCODE_TLV_PHY_SKU = 23, 965 IWM_UCODE_TLV_SECURE_SEC_RT = 24, 966 IWM_UCODE_TLV_SECURE_SEC_INIT = 25, 967 IWM_UCODE_TLV_SECURE_SEC_WOWLAN = 26, 968 IWM_UCODE_TLV_NUM_OF_CPU = 27, 969 IWM_UCODE_TLV_CSCHEME = 28, 970 971 /* 972 * Following two are not in our base tag, but allow 973 * handling ucode version 9. 974 */ 975 IWM_UCODE_TLV_API_CHANGES_SET = 29, 976 IWM_UCODE_TLV_ENABLED_CAPABILITIES = 30, 977 978 IWM_UCODE_TLV_N_SCAN_CHANNELS = 31, 979 IWM_UCODE_TLV_PAGING = 32, 980 IWM_UCODE_TLV_SEC_RT_USNIFFER = 34, 981 IWM_UCODE_TLV_SDIO_ADMA_ADDR = 35, 982 IWM_UCODE_TLV_FW_VERSION = 36, 983 IWM_UCODE_TLV_FW_DBG_DEST = 38, 984 IWM_UCODE_TLV_FW_DBG_CONF = 39, 985 IWM_UCODE_TLV_FW_DBG_TRIGGER = 40, 986 IWM_UCODE_TLV_FW_GSCAN_CAPA = 50, 987 IWM_UCODE_TLV_FW_MEM_SEG = 51, 988 }; 989 990 struct iwm_ucode_tlv { 991 uint32_t type; /* see above */ 992 uint32_t length; /* not including type/length fields */ 993 uint8_t data[0]; 994 }; 995 996 struct iwm_ucode_api { 997 uint32_t api_index; 998 uint32_t api_flags; 999 } __packed; 1000 1001 struct iwm_ucode_capa { 1002 uint32_t api_index; 1003 uint32_t api_capa; 1004 } __packed; 1005 1006 #define IWM_TLV_UCODE_MAGIC 0x0a4c5749 1007 1008 struct iwm_tlv_ucode_header { 1009 /* 1010 * The TLV style ucode header is distinguished from 1011 * the v1/v2 style header by first four bytes being 1012 * zero, as such is an invalid combination of 1013 * major/minor/API/serial versions. 1014 */ 1015 uint32_t zero; 1016 uint32_t magic; 1017 uint8_t human_readable[64]; 1018 uint32_t ver; /* major/minor/API/serial */ 1019 uint32_t build; 1020 uint64_t ignore; 1021 /* 1022 * The data contained herein has a TLV layout, 1023 * see above for the TLV header and types. 1024 * Note that each TLV is padded to a length 1025 * that is a multiple of 4 for alignment. 1026 */ 1027 uint8_t data[0]; 1028 }; 1029 1030 /* 1031 * END iwl-fw-file.h 1032 */ 1033 1034 /* 1035 * BEGIN iwl-prph.h 1036 */ 1037 1038 /* 1039 * Registers in this file are internal, not PCI bus memory mapped. 1040 * Driver accesses these via IWM_HBUS_TARG_PRPH_* registers. 1041 */ 1042 #define IWM_PRPH_BASE (0x00000) 1043 #define IWM_PRPH_END (0xFFFFF) 1044 1045 /* APMG (power management) constants */ 1046 #define IWM_APMG_BASE (IWM_PRPH_BASE + 0x3000) 1047 #define IWM_APMG_CLK_CTRL_REG (IWM_APMG_BASE + 0x0000) 1048 #define IWM_APMG_CLK_EN_REG (IWM_APMG_BASE + 0x0004) 1049 #define IWM_APMG_CLK_DIS_REG (IWM_APMG_BASE + 0x0008) 1050 #define IWM_APMG_PS_CTRL_REG (IWM_APMG_BASE + 0x000c) 1051 #define IWM_APMG_PCIDEV_STT_REG (IWM_APMG_BASE + 0x0010) 1052 #define IWM_APMG_RFKILL_REG (IWM_APMG_BASE + 0x0014) 1053 #define IWM_APMG_RTC_INT_STT_REG (IWM_APMG_BASE + 0x001c) 1054 #define IWM_APMG_RTC_INT_MSK_REG (IWM_APMG_BASE + 0x0020) 1055 #define IWM_APMG_DIGITAL_SVR_REG (IWM_APMG_BASE + 0x0058) 1056 #define IWM_APMG_ANALOG_SVR_REG (IWM_APMG_BASE + 0x006C) 1057 1058 #define IWM_APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001) 1059 #define IWM_APMG_CLK_VAL_DMA_CLK_RQT (0x00000200) 1060 #define IWM_APMG_CLK_VAL_BSM_CLK_RQT (0x00000800) 1061 1062 #define IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000) 1063 #define IWM_APMG_PS_CTRL_VAL_RESET_REQ (0x04000000) 1064 #define IWM_APMG_PS_CTRL_MSK_PWR_SRC (0x03000000) 1065 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000) 1066 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000) 1067 #define IWM_APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */ 1068 #define IWM_APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060) 1069 1070 #define IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800) 1071 1072 #define IWM_APMG_RTC_INT_STT_RFKILL (0x10000000) 1073 1074 /* Device system time */ 1075 #define IWM_DEVICE_SYSTEM_TIME_REG 0xA0206C 1076 1077 /* Device NMI register */ 1078 #define IWM_DEVICE_SET_NMI_REG 0x00a01c30 1079 #define IWM_DEVICE_SET_NMI_VAL_HW 0x01 1080 #define IWM_DEVICE_SET_NMI_VAL_DRV 0x80 1081 #define IWM_DEVICE_SET_NMI_8000_REG 0x00a01c24 1082 #define IWM_DEVICE_SET_NMI_8000_VAL 0x1000000 1083 1084 /* 1085 * Device reset for family 8000 1086 * write to bit 24 in order to reset the CPU 1087 */ 1088 #define IWM_RELEASE_CPU_RESET 0x300c 1089 #define IWM_RELEASE_CPU_RESET_BIT 0x1000000 1090 1091 1092 /***************************************************************************** 1093 * 7000/3000 series SHR DTS addresses * 1094 *****************************************************************************/ 1095 1096 #define IWM_SHR_MISC_WFM_DTS_EN (0x00a10024) 1097 #define IWM_DTSC_CFG_MODE (0x00a10604) 1098 #define IWM_DTSC_VREF_AVG (0x00a10648) 1099 #define IWM_DTSC_VREF5_AVG (0x00a1064c) 1100 #define IWM_DTSC_CFG_MODE_PERIODIC (0x2) 1101 #define IWM_DTSC_PTAT_AVG (0x00a10650) 1102 1103 1104 /** 1105 * Tx Scheduler 1106 * 1107 * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs 1108 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in 1109 * host DRAM. It steers each frame's Tx command (which contains the frame 1110 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the 1111 * device. A queue maps to only one (selectable by driver) Tx DMA channel, 1112 * but one DMA channel may take input from several queues. 1113 * 1114 * Tx DMA FIFOs have dedicated purposes. 1115 * 1116 * For 5000 series and up, they are used differently 1117 * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c): 1118 * 1119 * 0 -- EDCA BK (background) frames, lowest priority 1120 * 1 -- EDCA BE (best effort) frames, normal priority 1121 * 2 -- EDCA VI (video) frames, higher priority 1122 * 3 -- EDCA VO (voice) and management frames, highest priority 1123 * 4 -- unused 1124 * 5 -- unused 1125 * 6 -- unused 1126 * 7 -- Commands 1127 * 1128 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6. 1129 * In addition, driver can map the remaining queues to Tx DMA/FIFO 1130 * channels 0-3 to support 11n aggregation via EDCA DMA channels. 1131 * 1132 * The driver sets up each queue to work in one of two modes: 1133 * 1134 * 1) Scheduler-Ack, in which the scheduler automatically supports a 1135 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue 1136 * contains TFDs for a unique combination of Recipient Address (RA) 1137 * and Traffic Identifier (TID), that is, traffic of a given 1138 * Quality-Of-Service (QOS) priority, destined for a single station. 1139 * 1140 * In scheduler-ack mode, the scheduler keeps track of the Tx status of 1141 * each frame within the BA window, including whether it's been transmitted, 1142 * and whether it's been acknowledged by the receiving station. The device 1143 * automatically processes block-acks received from the receiving STA, 1144 * and reschedules un-acked frames to be retransmitted (successful 1145 * Tx completion may end up being out-of-order). 1146 * 1147 * The driver must maintain the queue's Byte Count table in host DRAM 1148 * for this mode. 1149 * This mode does not support fragmentation. 1150 * 1151 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order. 1152 * The device may automatically retry Tx, but will retry only one frame 1153 * at a time, until receiving ACK from receiving station, or reaching 1154 * retry limit and giving up. 1155 * 1156 * The command queue (#4/#9) must use this mode! 1157 * This mode does not require use of the Byte Count table in host DRAM. 1158 * 1159 * Driver controls scheduler operation via 3 means: 1160 * 1) Scheduler registers 1161 * 2) Shared scheduler data base in internal SRAM 1162 * 3) Shared data in host DRAM 1163 * 1164 * Initialization: 1165 * 1166 * When loading, driver should allocate memory for: 1167 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs. 1168 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory 1169 * (1024 bytes for each queue). 1170 * 1171 * After receiving "Alive" response from uCode, driver must initialize 1172 * the scheduler (especially for queue #4/#9, the command queue, otherwise 1173 * the driver can't issue commands!): 1174 */ 1175 #define IWM_SCD_MEM_LOWER_BOUND (0x0000) 1176 1177 /** 1178 * Max Tx window size is the max number of contiguous TFDs that the scheduler 1179 * can keep track of at one time when creating block-ack chains of frames. 1180 * Note that "64" matches the number of ack bits in a block-ack packet. 1181 */ 1182 #define IWM_SCD_WIN_SIZE 64 1183 #define IWM_SCD_FRAME_LIMIT 64 1184 1185 #define IWM_SCD_TXFIFO_POS_TID (0) 1186 #define IWM_SCD_TXFIFO_POS_RA (4) 1187 #define IWM_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF) 1188 1189 /* agn SCD */ 1190 #define IWM_SCD_QUEUE_STTS_REG_POS_TXF (0) 1191 #define IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE (3) 1192 #define IWM_SCD_QUEUE_STTS_REG_POS_WSL (4) 1193 #define IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19) 1194 #define IWM_SCD_QUEUE_STTS_REG_MSK (0x017F0000) 1195 1196 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_POS (8) 1197 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00) 1198 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24) 1199 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000) 1200 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0) 1201 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F) 1202 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) 1203 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) 1204 #define IWM_SCD_GP_CTRL_ENABLE_31_QUEUES (1 << 0) 1205 #define IWM_SCD_GP_CTRL_AUTO_ACTIVE_MODE (1 << 18) 1206 1207 /* Context Data */ 1208 #define IWM_SCD_CONTEXT_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x600) 1209 #define IWM_SCD_CONTEXT_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 1210 1211 /* Tx status */ 1212 #define IWM_SCD_TX_STTS_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 1213 #define IWM_SCD_TX_STTS_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 1214 1215 /* Translation Data */ 1216 #define IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 1217 #define IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x808) 1218 1219 #define IWM_SCD_CONTEXT_QUEUE_OFFSET(x)\ 1220 (IWM_SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8)) 1221 1222 #define IWM_SCD_TX_STTS_QUEUE_OFFSET(x)\ 1223 (IWM_SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16)) 1224 1225 #define IWM_SCD_TRANS_TBL_OFFSET_QUEUE(x) \ 1226 ((IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc) 1227 1228 #define IWM_SCD_BASE (IWM_PRPH_BASE + 0xa02c00) 1229 1230 #define IWM_SCD_SRAM_BASE_ADDR (IWM_SCD_BASE + 0x0) 1231 #define IWM_SCD_DRAM_BASE_ADDR (IWM_SCD_BASE + 0x8) 1232 #define IWM_SCD_AIT (IWM_SCD_BASE + 0x0c) 1233 #define IWM_SCD_TXFACT (IWM_SCD_BASE + 0x10) 1234 #define IWM_SCD_ACTIVE (IWM_SCD_BASE + 0x14) 1235 #define IWM_SCD_QUEUECHAIN_SEL (IWM_SCD_BASE + 0xe8) 1236 #define IWM_SCD_CHAINEXT_EN (IWM_SCD_BASE + 0x244) 1237 #define IWM_SCD_AGGR_SEL (IWM_SCD_BASE + 0x248) 1238 #define IWM_SCD_INTERRUPT_MASK (IWM_SCD_BASE + 0x108) 1239 #define IWM_SCD_GP_CTRL (IWM_SCD_BASE + 0x1a8) 1240 #define IWM_SCD_EN_CTRL (IWM_SCD_BASE + 0x254) 1241 1242 static inline unsigned int IWM_SCD_QUEUE_WRPTR(unsigned int chnl) 1243 { 1244 if (chnl < 20) 1245 return IWM_SCD_BASE + 0x18 + chnl * 4; 1246 return IWM_SCD_BASE + 0x284 + (chnl - 20) * 4; 1247 } 1248 1249 static inline unsigned int IWM_SCD_QUEUE_RDPTR(unsigned int chnl) 1250 { 1251 if (chnl < 20) 1252 return IWM_SCD_BASE + 0x68 + chnl * 4; 1253 return IWM_SCD_BASE + 0x2B4 + (chnl - 20) * 4; 1254 } 1255 1256 static inline unsigned int IWM_SCD_QUEUE_STATUS_BITS(unsigned int chnl) 1257 { 1258 if (chnl < 20) 1259 return IWM_SCD_BASE + 0x10c + chnl * 4; 1260 return IWM_SCD_BASE + 0x384 + (chnl - 20) * 4; 1261 } 1262 1263 /*********************** END TX SCHEDULER *************************************/ 1264 1265 /* Oscillator clock */ 1266 #define IWM_OSC_CLK (0xa04068) 1267 #define IWM_OSC_CLK_FORCE_CONTROL (0x8) 1268 1269 /* 1270 * END iwl-prph.h 1271 */ 1272 1273 /* 1274 * BEGIN iwl-fh.h 1275 */ 1276 1277 /****************************/ 1278 /* Flow Handler Definitions */ 1279 /****************************/ 1280 1281 /** 1282 * This I/O area is directly read/writable by driver (e.g. Linux uses writel()) 1283 * Addresses are offsets from device's PCI hardware base address. 1284 */ 1285 #define IWM_FH_MEM_LOWER_BOUND (0x1000) 1286 #define IWM_FH_MEM_UPPER_BOUND (0x2000) 1287 1288 /** 1289 * Keep-Warm (KW) buffer base address. 1290 * 1291 * Driver must allocate a 4KByte buffer that is for keeping the 1292 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency 1293 * DRAM access when doing Txing or Rxing. The dummy accesses prevent host 1294 * from going into a power-savings mode that would cause higher DRAM latency, 1295 * and possible data over/under-runs, before all Tx/Rx is complete. 1296 * 1297 * Driver loads IWM_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4) 1298 * of the buffer, which must be 4K aligned. Once this is set up, the device 1299 * automatically invokes keep-warm accesses when normal accesses might not 1300 * be sufficient to maintain fast DRAM response. 1301 * 1302 * Bit fields: 1303 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned 1304 */ 1305 #define IWM_FH_KW_MEM_ADDR_REG (IWM_FH_MEM_LOWER_BOUND + 0x97C) 1306 1307 1308 /** 1309 * TFD Circular Buffers Base (CBBC) addresses 1310 * 1311 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident 1312 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs) 1313 * (see struct iwm_tfd_frame). These 16 pointer registers are offset by 0x04 1314 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte 1315 * aligned (address bits 0-7 must be 0). 1316 * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers 1317 * for them are in different places. 1318 * 1319 * Bit fields in each pointer register: 1320 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned 1321 */ 1322 #define IWM_FH_MEM_CBBC_0_15_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1323 #define IWM_FH_MEM_CBBC_0_15_UPPER_BOUN (IWM_FH_MEM_LOWER_BOUND + 0xA10) 1324 #define IWM_FH_MEM_CBBC_16_19_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBF0) 1325 #define IWM_FH_MEM_CBBC_16_19_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1326 #define IWM_FH_MEM_CBBC_20_31_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB20) 1327 #define IWM_FH_MEM_CBBC_20_31_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB80) 1328 1329 /* Find TFD CB base pointer for given queue */ 1330 static inline unsigned int IWM_FH_MEM_CBBC_QUEUE(unsigned int chnl) 1331 { 1332 if (chnl < 16) 1333 return IWM_FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl; 1334 if (chnl < 20) 1335 return IWM_FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16); 1336 return IWM_FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20); 1337 } 1338 1339 1340 /** 1341 * Rx SRAM Control and Status Registers (RSCSR) 1342 * 1343 * These registers provide handshake between driver and device for the Rx queue 1344 * (this queue handles *all* command responses, notifications, Rx data, etc. 1345 * sent from uCode to host driver). Unlike Tx, there is only one Rx 1346 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can 1347 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer 1348 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1 1349 * mapping between RBDs and RBs. 1350 * 1351 * Driver must allocate host DRAM memory for the following, and set the 1352 * physical address of each into device registers: 1353 * 1354 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256 1355 * entries (although any power of 2, up to 4096, is selectable by driver). 1356 * Each entry (1 dword) points to a receive buffer (RB) of consistent size 1357 * (typically 4K, although 8K or 16K are also selectable by driver). 1358 * Driver sets up RB size and number of RBDs in the CB via Rx config 1359 * register IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG. 1360 * 1361 * Bit fields within one RBD: 1362 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned 1363 * 1364 * Driver sets physical address [35:8] of base of RBD circular buffer 1365 * into IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0]. 1366 * 1367 * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers 1368 * (RBs) have been filled, via a "write pointer", actually the index of 1369 * the RB's corresponding RBD within the circular buffer. Driver sets 1370 * physical address [35:4] into IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0]. 1371 * 1372 * Bit fields in lower dword of Rx status buffer (upper dword not used 1373 * by driver: 1374 * 31-12: Not used by driver 1375 * 11- 0: Index of last filled Rx buffer descriptor 1376 * (device writes, driver reads this value) 1377 * 1378 * As the driver prepares Receive Buffers (RBs) for device to fill, driver must 1379 * enter pointers to these RBs into contiguous RBD circular buffer entries, 1380 * and update the device's "write" index register, 1381 * IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG. 1382 * 1383 * This "write" index corresponds to the *next* RBD that the driver will make 1384 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within 1385 * the circular buffer. This value should initially be 0 (before preparing any 1386 * RBs), should be 8 after preparing the first 8 RBs (for example), and must 1387 * wrap back to 0 at the end of the circular buffer (but don't wrap before 1388 * "read" index has advanced past 1! See below). 1389 * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8. 1390 * 1391 * As the device fills RBs (referenced from contiguous RBDs within the circular 1392 * buffer), it updates the Rx status buffer in host DRAM, 2) described above, 1393 * to tell the driver the index of the latest filled RBD. The driver must 1394 * read this "read" index from DRAM after receiving an Rx interrupt from device 1395 * 1396 * The driver must also internally keep track of a third index, which is the 1397 * next RBD to process. When receiving an Rx interrupt, driver should process 1398 * all filled but unprocessed RBs up to, but not including, the RB 1399 * corresponding to the "read" index. For example, if "read" index becomes "1", 1400 * driver may process the RB pointed to by RBD 0. Depending on volume of 1401 * traffic, there may be many RBs to process. 1402 * 1403 * If read index == write index, device thinks there is no room to put new data. 1404 * Due to this, the maximum number of filled RBs is 255, instead of 256. To 1405 * be safe, make sure that there is a gap of at least 2 RBDs between "write" 1406 * and "read" indexes; that is, make sure that there are no more than 254 1407 * buffers waiting to be filled. 1408 */ 1409 #define IWM_FH_MEM_RSCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBC0) 1410 #define IWM_FH_MEM_RSCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1411 #define IWM_FH_MEM_RSCSR_CHNL0 (IWM_FH_MEM_RSCSR_LOWER_BOUND) 1412 1413 /** 1414 * Physical base address of 8-byte Rx Status buffer. 1415 * Bit fields: 1416 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned. 1417 */ 1418 #define IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0) 1419 1420 /** 1421 * Physical base address of Rx Buffer Descriptor Circular Buffer. 1422 * Bit fields: 1423 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned. 1424 */ 1425 #define IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x004) 1426 1427 /** 1428 * Rx write pointer (index, really!). 1429 * Bit fields: 1430 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1. 1431 * NOTE: For 256-entry circular buffer, use only bits [7:0]. 1432 */ 1433 #define IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x008) 1434 #define IWM_FH_RSCSR_CHNL0_WPTR (IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG) 1435 1436 #define IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x00c) 1437 #define IWM_FH_RSCSR_CHNL0_RDPTR IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG 1438 1439 /** 1440 * Rx Config/Status Registers (RCSR) 1441 * Rx Config Reg for channel 0 (only channel used) 1442 * 1443 * Driver must initialize IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for 1444 * normal operation (see bit fields). 1445 * 1446 * Clearing IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA. 1447 * Driver should poll IWM_FH_MEM_RSSR_RX_STATUS_REG for 1448 * IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing. 1449 * 1450 * Bit fields: 1451 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1452 * '10' operate normally 1453 * 29-24: reserved 1454 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal), 1455 * min "5" for 32 RBDs, max "12" for 4096 RBDs. 1456 * 19-18: reserved 1457 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K, 1458 * '10' 12K, '11' 16K. 1459 * 15-14: reserved 1460 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation) 1461 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec) 1462 * typical value 0x10 (about 1/2 msec) 1463 * 3- 0: reserved 1464 */ 1465 #define IWM_FH_MEM_RCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1466 #define IWM_FH_MEM_RCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xCC0) 1467 #define IWM_FH_MEM_RCSR_CHNL0 (IWM_FH_MEM_RCSR_LOWER_BOUND) 1468 1469 #define IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG (IWM_FH_MEM_RCSR_CHNL0) 1470 #define IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR (IWM_FH_MEM_RCSR_CHNL0 + 0x8) 1471 #define IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (IWM_FH_MEM_RCSR_CHNL0 + 0x10) 1472 1473 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */ 1474 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */ 1475 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */ 1476 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */ 1477 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */ 1478 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/ 1479 1480 #define IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20) 1481 #define IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4) 1482 #define IWM_RX_RB_TIMEOUT (0x11) 1483 1484 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000) 1485 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000) 1486 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) 1487 1488 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) 1489 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000) 1490 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000) 1491 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000) 1492 1493 #define IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004) 1494 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) 1495 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) 1496 1497 /** 1498 * Rx Shared Status Registers (RSSR) 1499 * 1500 * After stopping Rx DMA channel (writing 0 to 1501 * IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll 1502 * IWM_FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle. 1503 * 1504 * Bit fields: 1505 * 24: 1 = Channel 0 is idle 1506 * 1507 * IWM_FH_MEM_RSSR_SHARED_CTRL_REG and IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV 1508 * contain default values that should not be altered by the driver. 1509 */ 1510 #define IWM_FH_MEM_RSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC40) 1511 #define IWM_FH_MEM_RSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1512 1513 #define IWM_FH_MEM_RSSR_SHARED_CTRL_REG (IWM_FH_MEM_RSSR_LOWER_BOUND) 1514 #define IWM_FH_MEM_RSSR_RX_STATUS_REG (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x004) 1515 #define IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\ 1516 (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x008) 1517 1518 #define IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000) 1519 1520 #define IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28 1521 1522 /* TFDB Area - TFDs buffer table */ 1523 #define IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF) 1524 #define IWM_FH_TFDIB_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x900) 1525 #define IWM_FH_TFDIB_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x958) 1526 #define IWM_FH_TFDIB_CTRL0_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl)) 1527 #define IWM_FH_TFDIB_CTRL1_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4) 1528 1529 /** 1530 * Transmit DMA Channel Control/Status Registers (TCSR) 1531 * 1532 * Device has one configuration register for each of 8 Tx DMA/FIFO channels 1533 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM, 1534 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes. 1535 * 1536 * To use a Tx DMA channel, driver must initialize its 1537 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with: 1538 * 1539 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 1540 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL 1541 * 1542 * All other bits should be 0. 1543 * 1544 * Bit fields: 1545 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1546 * '10' operate normally 1547 * 29- 4: Reserved, set to "0" 1548 * 3: Enable internal DMA requests (1, normal operation), disable (0) 1549 * 2- 0: Reserved, set to "0" 1550 */ 1551 #define IWM_FH_TCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1552 #define IWM_FH_TCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xE60) 1553 1554 /* Find Control/Status reg for given Tx DMA/FIFO channel */ 1555 #define IWM_FH_TCSR_CHNL_NUM (8) 1556 1557 /* TCSR: tx_config register values */ 1558 #define IWM_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ 1559 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl)) 1560 #define IWM_FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \ 1561 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4) 1562 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \ 1563 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8) 1564 1565 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) 1566 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001) 1567 1568 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000) 1569 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008) 1570 1571 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000) 1572 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000) 1573 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) 1574 1575 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) 1576 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000) 1577 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000) 1578 1579 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) 1580 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000) 1581 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) 1582 1583 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000) 1584 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000) 1585 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003) 1586 1587 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20) 1588 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12) 1589 1590 /** 1591 * Tx Shared Status Registers (TSSR) 1592 * 1593 * After stopping Tx DMA channel (writing 0 to 1594 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll 1595 * IWM_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle 1596 * (channel's buffers empty | no pending requests). 1597 * 1598 * Bit fields: 1599 * 31-24: 1 = Channel buffers empty (channel 7:0) 1600 * 23-16: 1 = No pending requests (channel 7:0) 1601 */ 1602 #define IWM_FH_TSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEA0) 1603 #define IWM_FH_TSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEC0) 1604 1605 #define IWM_FH_TSSR_TX_STATUS_REG (IWM_FH_TSSR_LOWER_BOUND + 0x010) 1606 1607 /** 1608 * Bit fields for TSSR(Tx Shared Status & Control) error status register: 1609 * 31: Indicates an address error when accessed to internal memory 1610 * uCode/driver must write "1" in order to clear this flag 1611 * 30: Indicates that Host did not send the expected number of dwords to FH 1612 * uCode/driver must write "1" in order to clear this flag 1613 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA 1614 * command was received from the scheduler while the TRB was already full 1615 * with previous command 1616 * uCode/driver must write "1" in order to clear this flag 1617 * 7-0: Each status bit indicates a channel's TxCredit error. When an error 1618 * bit is set, it indicates that the FH has received a full indication 1619 * from the RTC TxFIFO and the current value of the TxCredit counter was 1620 * not equal to zero. This mean that the credit mechanism was not 1621 * synchronized to the TxFIFO status 1622 * uCode/driver must write "1" in order to clear this flag 1623 */ 1624 #define IWM_FH_TSSR_TX_ERROR_REG (IWM_FH_TSSR_LOWER_BOUND + 0x018) 1625 #define IWM_FH_TSSR_TX_MSG_CONFIG_REG (IWM_FH_TSSR_LOWER_BOUND + 0x008) 1626 1627 #define IWM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16) 1628 1629 /* Tx service channels */ 1630 #define IWM_FH_SRVC_CHNL (9) 1631 #define IWM_FH_SRVC_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9C8) 1632 #define IWM_FH_SRVC_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1633 #define IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \ 1634 (IWM_FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4) 1635 1636 #define IWM_FH_TX_CHICKEN_BITS_REG (IWM_FH_MEM_LOWER_BOUND + 0xE98) 1637 #define IWM_FH_TX_TRB_REG(_chan) (IWM_FH_MEM_LOWER_BOUND + 0x958 + \ 1638 (_chan) * 4) 1639 1640 /* Instruct FH to increment the retry count of a packet when 1641 * it is brought from the memory to TX-FIFO 1642 */ 1643 #define IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002) 1644 1645 #define IWM_RX_QUEUE_SIZE 256 1646 #define IWM_RX_QUEUE_MASK 255 1647 #define IWM_RX_QUEUE_SIZE_LOG 8 1648 1649 /* 1650 * RX related structures and functions 1651 */ 1652 #define IWM_RX_FREE_BUFFERS 64 1653 #define IWM_RX_LOW_WATERMARK 8 1654 1655 /** 1656 * struct iwm_rb_status - reseve buffer status 1657 * host memory mapped FH registers 1658 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed 1659 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed 1660 * @finished_rb_num [0:11] - Indicates the index of the current RB 1661 * in which the last frame was written to 1662 * @finished_fr_num [0:11] - Indicates the index of the RX Frame 1663 * which was transferred 1664 */ 1665 struct iwm_rb_status { 1666 uint16_t closed_rb_num; 1667 uint16_t closed_fr_num; 1668 uint16_t finished_rb_num; 1669 uint16_t finished_fr_nam; 1670 uint32_t unused; 1671 } __packed; 1672 1673 1674 #define IWM_TFD_QUEUE_SIZE_MAX (256) 1675 #define IWM_TFD_QUEUE_SIZE_BC_DUP (64) 1676 #define IWM_TFD_QUEUE_BC_SIZE (IWM_TFD_QUEUE_SIZE_MAX + \ 1677 IWM_TFD_QUEUE_SIZE_BC_DUP) 1678 #define IWM_TX_DMA_MASK DMA_BIT_MASK(36) 1679 #define IWM_NUM_OF_TBS 20 1680 1681 static inline uint8_t iwm_get_dma_hi_addr(bus_addr_t addr) 1682 { 1683 return (sizeof(addr) > sizeof(uint32_t) ? (addr >> 16) >> 16 : 0) & 0xF; 1684 } 1685 /** 1686 * struct iwm_tfd_tb transmit buffer descriptor within transmit frame descriptor 1687 * 1688 * This structure contains dma address and length of transmission address 1689 * 1690 * @lo: low [31:0] portion of the dma address of TX buffer 1691 * every even is unaligned on 16 bit boundary 1692 * @hi_n_len 0-3 [35:32] portion of dma 1693 * 4-15 length of the tx buffer 1694 */ 1695 struct iwm_tfd_tb { 1696 uint32_t lo; 1697 uint16_t hi_n_len; 1698 } __packed; 1699 1700 /** 1701 * struct iwm_tfd 1702 * 1703 * Transmit Frame Descriptor (TFD) 1704 * 1705 * @ __reserved1[3] reserved 1706 * @ num_tbs 0-4 number of active tbs 1707 * 5 reserved 1708 * 6-7 padding (not used) 1709 * @ tbs[20] transmit frame buffer descriptors 1710 * @ __pad padding 1711 * 1712 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM. 1713 * Both driver and device share these circular buffers, each of which must be 1714 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes 1715 * 1716 * Driver must indicate the physical address of the base of each 1717 * circular buffer via the IWM_FH_MEM_CBBC_QUEUE registers. 1718 * 1719 * Each TFD contains pointer/size information for up to 20 data buffers 1720 * in host DRAM. These buffers collectively contain the (one) frame described 1721 * by the TFD. Each buffer must be a single contiguous block of memory within 1722 * itself, but buffers may be scattered in host DRAM. Each buffer has max size 1723 * of (4K - 4). The concatenates all of a TFD's buffers into a single 1724 * Tx frame, up to 8 KBytes in size. 1725 * 1726 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx. 1727 */ 1728 struct iwm_tfd { 1729 uint8_t __reserved1[3]; 1730 uint8_t num_tbs; 1731 struct iwm_tfd_tb tbs[IWM_NUM_OF_TBS]; 1732 uint32_t __pad; 1733 } __packed; 1734 1735 /* Keep Warm Size */ 1736 #define IWM_KW_SIZE 0x1000 /* 4k */ 1737 1738 /* Fixed (non-configurable) rx data from phy */ 1739 1740 /** 1741 * struct iwm_agn_schedq_bc_tbl scheduler byte count table 1742 * base physical address provided by IWM_SCD_DRAM_BASE_ADDR 1743 * @tfd_offset 0-12 - tx command byte count 1744 * 12-16 - station index 1745 */ 1746 struct iwm_agn_scd_bc_tbl { 1747 uint16_t tfd_offset[IWM_TFD_QUEUE_BC_SIZE]; 1748 } __packed; 1749 1750 /* 1751 * END iwl-fh.h 1752 */ 1753 1754 /* 1755 * BEGIN mvm/fw-api.h 1756 */ 1757 1758 /* Maximum number of Tx queues. */ 1759 #define IWM_MVM_MAX_QUEUES 31 1760 1761 /* Tx queue numbers */ 1762 enum { 1763 IWM_MVM_OFFCHANNEL_QUEUE = 8, 1764 IWM_MVM_CMD_QUEUE = 9, 1765 IWM_MVM_AUX_QUEUE = 15, 1766 }; 1767 1768 enum iwm_mvm_tx_fifo { 1769 IWM_MVM_TX_FIFO_BK = 0, 1770 IWM_MVM_TX_FIFO_BE, 1771 IWM_MVM_TX_FIFO_VI, 1772 IWM_MVM_TX_FIFO_VO, 1773 IWM_MVM_TX_FIFO_MCAST = 5, 1774 IWM_MVM_TX_FIFO_CMD = 7, 1775 }; 1776 1777 #define IWM_MVM_STATION_COUNT 16 1778 1779 /* commands */ 1780 enum { 1781 IWM_MVM_ALIVE = 0x1, 1782 IWM_REPLY_ERROR = 0x2, 1783 1784 IWM_INIT_COMPLETE_NOTIF = 0x4, 1785 1786 /* PHY context commands */ 1787 IWM_PHY_CONTEXT_CMD = 0x8, 1788 IWM_DBG_CFG = 0x9, 1789 1790 /* UMAC scan commands */ 1791 IWM_SCAN_ITERATION_COMPLETE_UMAC = 0xb5, 1792 IWM_SCAN_CFG_CMD = 0xc, 1793 IWM_SCAN_REQ_UMAC = 0xd, 1794 IWM_SCAN_ABORT_UMAC = 0xe, 1795 IWM_SCAN_COMPLETE_UMAC = 0xf, 1796 1797 /* station table */ 1798 IWM_ADD_STA_KEY = 0x17, 1799 IWM_ADD_STA = 0x18, 1800 IWM_REMOVE_STA = 0x19, 1801 1802 /* TX */ 1803 IWM_TX_CMD = 0x1c, 1804 IWM_TXPATH_FLUSH = 0x1e, 1805 IWM_MGMT_MCAST_KEY = 0x1f, 1806 1807 /* scheduler config */ 1808 IWM_SCD_QUEUE_CFG = 0x1d, 1809 1810 /* global key */ 1811 IWM_WEP_KEY = 0x20, 1812 1813 /* MAC and Binding commands */ 1814 IWM_MAC_CONTEXT_CMD = 0x28, 1815 IWM_TIME_EVENT_CMD = 0x29, /* both CMD and response */ 1816 IWM_TIME_EVENT_NOTIFICATION = 0x2a, 1817 IWM_BINDING_CONTEXT_CMD = 0x2b, 1818 IWM_TIME_QUOTA_CMD = 0x2c, 1819 IWM_NON_QOS_TX_COUNTER_CMD = 0x2d, 1820 1821 IWM_LQ_CMD = 0x4e, 1822 1823 /* paging block to FW cpu2 */ 1824 IWM_FW_PAGING_BLOCK_CMD = 0x4f, 1825 1826 /* Scan offload */ 1827 IWM_SCAN_OFFLOAD_REQUEST_CMD = 0x51, 1828 IWM_SCAN_OFFLOAD_ABORT_CMD = 0x52, 1829 IWM_HOT_SPOT_CMD = 0x53, 1830 IWM_SCAN_OFFLOAD_COMPLETE = 0x6d, 1831 IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD = 0x6e, 1832 IWM_SCAN_OFFLOAD_CONFIG_CMD = 0x6f, 1833 IWM_MATCH_FOUND_NOTIFICATION = 0xd9, 1834 IWM_SCAN_ITERATION_COMPLETE = 0xe7, 1835 1836 /* Phy */ 1837 IWM_PHY_CONFIGURATION_CMD = 0x6a, 1838 IWM_CALIB_RES_NOTIF_PHY_DB = 0x6b, 1839 /* IWM_PHY_DB_CMD = 0x6c, */ 1840 1841 /* Power - legacy power table command */ 1842 IWM_POWER_TABLE_CMD = 0x77, 1843 IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78, 1844 1845 /* Thermal Throttling*/ 1846 IWM_REPLY_THERMAL_MNG_BACKOFF = 0x7e, 1847 1848 /* Scanning */ 1849 IWM_SCAN_ABORT_CMD = 0x81, 1850 IWM_SCAN_START_NOTIFICATION = 0x82, 1851 IWM_SCAN_RESULTS_NOTIFICATION = 0x83, 1852 1853 /* NVM */ 1854 IWM_NVM_ACCESS_CMD = 0x88, 1855 1856 IWM_SET_CALIB_DEFAULT_CMD = 0x8e, 1857 1858 IWM_BEACON_NOTIFICATION = 0x90, 1859 IWM_BEACON_TEMPLATE_CMD = 0x91, 1860 IWM_TX_ANT_CONFIGURATION_CMD = 0x98, 1861 IWM_BT_CONFIG = 0x9b, 1862 IWM_STATISTICS_NOTIFICATION = 0x9d, 1863 IWM_REDUCE_TX_POWER_CMD = 0x9f, 1864 1865 /* RF-KILL commands and notifications */ 1866 IWM_CARD_STATE_CMD = 0xa0, 1867 IWM_CARD_STATE_NOTIFICATION = 0xa1, 1868 1869 IWM_MISSED_BEACONS_NOTIFICATION = 0xa2, 1870 1871 IWM_MFUART_LOAD_NOTIFICATION = 0xb1, 1872 1873 /* Power - new power table command */ 1874 IWM_MAC_PM_POWER_TABLE = 0xa9, 1875 1876 IWM_REPLY_RX_PHY_CMD = 0xc0, 1877 IWM_REPLY_RX_MPDU_CMD = 0xc1, 1878 IWM_BA_NOTIF = 0xc5, 1879 1880 /* Location Aware Regulatory */ 1881 IWM_MCC_UPDATE_CMD = 0xc8, 1882 IWM_MCC_CHUB_UPDATE_CMD = 0xc9, 1883 1884 /* BT Coex */ 1885 IWM_BT_COEX_PRIO_TABLE = 0xcc, 1886 IWM_BT_COEX_PROT_ENV = 0xcd, 1887 IWM_BT_PROFILE_NOTIFICATION = 0xce, 1888 IWM_BT_COEX_CI = 0x5d, 1889 1890 IWM_REPLY_SF_CFG_CMD = 0xd1, 1891 IWM_REPLY_BEACON_FILTERING_CMD = 0xd2, 1892 1893 /* DTS measurements */ 1894 IWM_CMD_DTS_MEASUREMENT_TRIGGER = 0xdc, 1895 IWM_DTS_MEASUREMENT_NOTIFICATION = 0xdd, 1896 1897 IWM_REPLY_DEBUG_CMD = 0xf0, 1898 IWM_DEBUG_LOG_MSG = 0xf7, 1899 1900 IWM_MCAST_FILTER_CMD = 0xd0, 1901 1902 /* D3 commands/notifications */ 1903 IWM_D3_CONFIG_CMD = 0xd3, 1904 IWM_PROT_OFFLOAD_CONFIG_CMD = 0xd4, 1905 IWM_OFFLOADS_QUERY_CMD = 0xd5, 1906 IWM_REMOTE_WAKE_CONFIG_CMD = 0xd6, 1907 1908 /* for WoWLAN in particular */ 1909 IWM_WOWLAN_PATTERNS = 0xe0, 1910 IWM_WOWLAN_CONFIGURATION = 0xe1, 1911 IWM_WOWLAN_TSC_RSC_PARAM = 0xe2, 1912 IWM_WOWLAN_TKIP_PARAM = 0xe3, 1913 IWM_WOWLAN_KEK_KCK_MATERIAL = 0xe4, 1914 IWM_WOWLAN_GET_STATUSES = 0xe5, 1915 IWM_WOWLAN_TX_POWER_PER_DB = 0xe6, 1916 1917 /* and for NetDetect */ 1918 IWM_NET_DETECT_CONFIG_CMD = 0x54, 1919 IWM_NET_DETECT_PROFILES_QUERY_CMD = 0x56, 1920 IWM_NET_DETECT_PROFILES_CMD = 0x57, 1921 IWM_NET_DETECT_HOTSPOTS_CMD = 0x58, 1922 IWM_NET_DETECT_HOTSPOTS_QUERY_CMD = 0x59, 1923 1924 IWM_REPLY_MAX = 0xff, 1925 }; 1926 1927 enum iwm_phy_ops_subcmd_ids { 1928 IWM_CMD_DTS_MEASUREMENT_TRIGGER_WIDE = 0x0, 1929 IWM_CTDP_CONFIG_CMD = 0x03, 1930 IWM_TEMP_REPORTING_THRESHOLDS_CMD = 0x04, 1931 IWM_CT_KILL_NOTIFICATION = 0xFE, 1932 IWM_DTS_MEASUREMENT_NOTIF_WIDE = 0xFF, 1933 }; 1934 1935 /* command groups */ 1936 enum { 1937 IWM_LEGACY_GROUP = 0x0, 1938 IWM_LONG_GROUP = 0x1, 1939 IWM_SYSTEM_GROUP = 0x2, 1940 IWM_MAC_CONF_GROUP = 0x3, 1941 IWM_PHY_OPS_GROUP = 0x4, 1942 IWM_DATA_PATH_GROUP = 0x5, 1943 IWM_PROT_OFFLOAD_GROUP = 0xb, 1944 }; 1945 1946 /** 1947 * struct iwm_cmd_response - generic response struct for most commands 1948 * @status: status of the command asked, changes for each one 1949 */ 1950 struct iwm_cmd_response { 1951 uint32_t status; 1952 }; 1953 1954 /* 1955 * struct iwm_tx_ant_cfg_cmd 1956 * @valid: valid antenna configuration 1957 */ 1958 struct iwm_tx_ant_cfg_cmd { 1959 uint32_t valid; 1960 } __packed; 1961 1962 /** 1963 * struct iwm_reduce_tx_power_cmd - TX power reduction command 1964 * IWM_REDUCE_TX_POWER_CMD = 0x9f 1965 * @flags: (reserved for future implementation) 1966 * @mac_context_id: id of the mac ctx for which we are reducing TX power. 1967 * @pwr_restriction: TX power restriction in dBms. 1968 */ 1969 struct iwm_reduce_tx_power_cmd { 1970 uint8_t flags; 1971 uint8_t mac_context_id; 1972 uint16_t pwr_restriction; 1973 } __packed; /* IWM_TX_REDUCED_POWER_API_S_VER_1 */ 1974 1975 /* 1976 * Calibration control struct. 1977 * Sent as part of the phy configuration command. 1978 * @flow_trigger: bitmap for which calibrations to perform according to 1979 * flow triggers. 1980 * @event_trigger: bitmap for which calibrations to perform according to 1981 * event triggers. 1982 */ 1983 struct iwm_calib_ctrl { 1984 uint32_t flow_trigger; 1985 uint32_t event_trigger; 1986 } __packed; 1987 1988 /* This enum defines the bitmap of various calibrations to enable in both 1989 * init ucode and runtime ucode through IWM_CALIBRATION_CFG_CMD. 1990 */ 1991 enum iwm_calib_cfg { 1992 IWM_CALIB_CFG_XTAL_IDX = (1 << 0), 1993 IWM_CALIB_CFG_TEMPERATURE_IDX = (1 << 1), 1994 IWM_CALIB_CFG_VOLTAGE_READ_IDX = (1 << 2), 1995 IWM_CALIB_CFG_PAPD_IDX = (1 << 3), 1996 IWM_CALIB_CFG_TX_PWR_IDX = (1 << 4), 1997 IWM_CALIB_CFG_DC_IDX = (1 << 5), 1998 IWM_CALIB_CFG_BB_FILTER_IDX = (1 << 6), 1999 IWM_CALIB_CFG_LO_LEAKAGE_IDX = (1 << 7), 2000 IWM_CALIB_CFG_TX_IQ_IDX = (1 << 8), 2001 IWM_CALIB_CFG_TX_IQ_SKEW_IDX = (1 << 9), 2002 IWM_CALIB_CFG_RX_IQ_IDX = (1 << 10), 2003 IWM_CALIB_CFG_RX_IQ_SKEW_IDX = (1 << 11), 2004 IWM_CALIB_CFG_SENSITIVITY_IDX = (1 << 12), 2005 IWM_CALIB_CFG_CHAIN_NOISE_IDX = (1 << 13), 2006 IWM_CALIB_CFG_DISCONNECTED_ANT_IDX = (1 << 14), 2007 IWM_CALIB_CFG_ANT_COUPLING_IDX = (1 << 15), 2008 IWM_CALIB_CFG_DAC_IDX = (1 << 16), 2009 IWM_CALIB_CFG_ABS_IDX = (1 << 17), 2010 IWM_CALIB_CFG_AGC_IDX = (1 << 18), 2011 }; 2012 2013 /* 2014 * Phy configuration command. 2015 */ 2016 struct iwm_phy_cfg_cmd { 2017 uint32_t phy_cfg; 2018 struct iwm_calib_ctrl calib_control; 2019 } __packed; 2020 2021 #define IWM_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1)) 2022 #define IWM_PHY_CFG_RADIO_STEP ((1 << 2) | (1 << 3)) 2023 #define IWM_PHY_CFG_RADIO_DASH ((1 << 4) | (1 << 5)) 2024 #define IWM_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7)) 2025 #define IWM_PHY_CFG_TX_CHAIN_A (1 << 8) 2026 #define IWM_PHY_CFG_TX_CHAIN_B (1 << 9) 2027 #define IWM_PHY_CFG_TX_CHAIN_C (1 << 10) 2028 #define IWM_PHY_CFG_RX_CHAIN_A (1 << 12) 2029 #define IWM_PHY_CFG_RX_CHAIN_B (1 << 13) 2030 #define IWM_PHY_CFG_RX_CHAIN_C (1 << 14) 2031 2032 2033 /* Target of the IWM_NVM_ACCESS_CMD */ 2034 enum { 2035 IWM_NVM_ACCESS_TARGET_CACHE = 0, 2036 IWM_NVM_ACCESS_TARGET_OTP = 1, 2037 IWM_NVM_ACCESS_TARGET_EEPROM = 2, 2038 }; 2039 2040 /* Section types for IWM_NVM_ACCESS_CMD */ 2041 enum { 2042 IWM_NVM_SECTION_TYPE_SW = 1, 2043 IWM_NVM_SECTION_TYPE_REGULATORY = 3, 2044 IWM_NVM_SECTION_TYPE_CALIBRATION = 4, 2045 IWM_NVM_SECTION_TYPE_PRODUCTION = 5, 2046 IWM_NVM_SECTION_TYPE_MAC_OVERRIDE = 11, 2047 IWM_NVM_SECTION_TYPE_PHY_SKU = 12, 2048 IWM_NVM_MAX_NUM_SECTIONS = 13, 2049 }; 2050 2051 /** 2052 * struct iwm_nvm_access_cmd_ver2 - Request the device to send an NVM section 2053 * @op_code: 0 - read, 1 - write 2054 * @target: IWM_NVM_ACCESS_TARGET_* 2055 * @type: IWM_NVM_SECTION_TYPE_* 2056 * @offset: offset in bytes into the section 2057 * @length: in bytes, to read/write 2058 * @data: if write operation, the data to write. On read its empty 2059 */ 2060 struct iwm_nvm_access_cmd { 2061 uint8_t op_code; 2062 uint8_t target; 2063 uint16_t type; 2064 uint16_t offset; 2065 uint16_t length; 2066 uint8_t data[]; 2067 } __packed; /* IWM_NVM_ACCESS_CMD_API_S_VER_2 */ 2068 2069 #define IWM_NUM_OF_FW_PAGING_BLOCKS 33 /* 32 for data and 1 block for CSS */ 2070 2071 /* 2072 * struct iwm_fw_paging_cmd - paging layout 2073 * 2074 * (IWM_FW_PAGING_BLOCK_CMD = 0x4f) 2075 * 2076 * Send to FW the paging layout in the driver. 2077 * 2078 * @flags: various flags for the command 2079 * @block_size: the block size in powers of 2 2080 * @block_num: number of blocks specified in the command. 2081 * @device_phy_addr: virtual addresses from device side 2082 */ 2083 struct iwm_fw_paging_cmd { 2084 uint32_t flags; 2085 uint32_t block_size; 2086 uint32_t block_num; 2087 uint32_t device_phy_addr[IWM_NUM_OF_FW_PAGING_BLOCKS]; 2088 } __packed; /* IWM_FW_PAGING_BLOCK_CMD_API_S_VER_1 */ 2089 2090 /* 2091 * Fw items ID's 2092 * 2093 * @IWM_FW_ITEM_ID_PAGING: Address of the pages that the FW will upload 2094 * download 2095 */ 2096 enum iwm_fw_item_id { 2097 IWM_FW_ITEM_ID_PAGING = 3, 2098 }; 2099 2100 /* 2101 * struct iwm_fw_get_item_cmd - get an item from the fw 2102 */ 2103 struct iwm_fw_get_item_cmd { 2104 uint32_t item_id; 2105 } __packed; /* IWM_FW_GET_ITEM_CMD_API_S_VER_1 */ 2106 2107 /** 2108 * struct iwm_nvm_access_resp_ver2 - response to IWM_NVM_ACCESS_CMD 2109 * @offset: offset in bytes into the section 2110 * @length: in bytes, either how much was written or read 2111 * @type: IWM_NVM_SECTION_TYPE_* 2112 * @status: 0 for success, fail otherwise 2113 * @data: if read operation, the data returned. Empty on write. 2114 */ 2115 struct iwm_nvm_access_resp { 2116 uint16_t offset; 2117 uint16_t length; 2118 uint16_t type; 2119 uint16_t status; 2120 uint8_t data[]; 2121 } __packed; /* IWM_NVM_ACCESS_CMD_RESP_API_S_VER_2 */ 2122 2123 /* IWM_MVM_ALIVE 0x1 */ 2124 2125 /* alive response is_valid values */ 2126 #define IWM_ALIVE_RESP_UCODE_OK (1 << 0) 2127 #define IWM_ALIVE_RESP_RFKILL (1 << 1) 2128 2129 /* alive response ver_type values */ 2130 enum { 2131 IWM_FW_TYPE_HW = 0, 2132 IWM_FW_TYPE_PROT = 1, 2133 IWM_FW_TYPE_AP = 2, 2134 IWM_FW_TYPE_WOWLAN = 3, 2135 IWM_FW_TYPE_TIMING = 4, 2136 IWM_FW_TYPE_WIPAN = 5 2137 }; 2138 2139 /* alive response ver_subtype values */ 2140 enum { 2141 IWM_FW_SUBTYPE_FULL_FEATURE = 0, 2142 IWM_FW_SUBTYPE_BOOTSRAP = 1, /* Not valid */ 2143 IWM_FW_SUBTYPE_REDUCED = 2, 2144 IWM_FW_SUBTYPE_ALIVE_ONLY = 3, 2145 IWM_FW_SUBTYPE_WOWLAN = 4, 2146 IWM_FW_SUBTYPE_AP_SUBTYPE = 5, 2147 IWM_FW_SUBTYPE_WIPAN = 6, 2148 IWM_FW_SUBTYPE_INITIALIZE = 9 2149 }; 2150 2151 #define IWM_ALIVE_STATUS_ERR 0xDEAD 2152 #define IWM_ALIVE_STATUS_OK 0xCAFE 2153 2154 #define IWM_ALIVE_FLG_RFKILL (1 << 0) 2155 2156 struct iwm_mvm_alive_resp_ver1 { 2157 uint16_t status; 2158 uint16_t flags; 2159 uint8_t ucode_minor; 2160 uint8_t ucode_major; 2161 uint16_t id; 2162 uint8_t api_minor; 2163 uint8_t api_major; 2164 uint8_t ver_subtype; 2165 uint8_t ver_type; 2166 uint8_t mac; 2167 uint8_t opt; 2168 uint16_t reserved2; 2169 uint32_t timestamp; 2170 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2171 uint32_t log_event_table_ptr; /* SRAM address for event log */ 2172 uint32_t cpu_register_ptr; 2173 uint32_t dbgm_config_ptr; 2174 uint32_t alive_counter_ptr; 2175 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2176 } __packed; /* IWM_ALIVE_RES_API_S_VER_1 */ 2177 2178 struct iwm_mvm_alive_resp_ver2 { 2179 uint16_t status; 2180 uint16_t flags; 2181 uint8_t ucode_minor; 2182 uint8_t ucode_major; 2183 uint16_t id; 2184 uint8_t api_minor; 2185 uint8_t api_major; 2186 uint8_t ver_subtype; 2187 uint8_t ver_type; 2188 uint8_t mac; 2189 uint8_t opt; 2190 uint16_t reserved2; 2191 uint32_t timestamp; 2192 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2193 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 2194 uint32_t cpu_register_ptr; 2195 uint32_t dbgm_config_ptr; 2196 uint32_t alive_counter_ptr; 2197 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2198 uint32_t st_fwrd_addr; /* pointer to Store and forward */ 2199 uint32_t st_fwrd_size; 2200 uint8_t umac_minor; /* UMAC version: minor */ 2201 uint8_t umac_major; /* UMAC version: major */ 2202 uint16_t umac_id; /* UMAC version: id */ 2203 uint32_t error_info_addr; /* SRAM address for UMAC error log */ 2204 uint32_t dbg_print_buff_addr; 2205 } __packed; /* ALIVE_RES_API_S_VER_2 */ 2206 2207 struct iwm_mvm_alive_resp { 2208 uint16_t status; 2209 uint16_t flags; 2210 uint32_t ucode_minor; 2211 uint32_t ucode_major; 2212 uint8_t ver_subtype; 2213 uint8_t ver_type; 2214 uint8_t mac; 2215 uint8_t opt; 2216 uint32_t timestamp; 2217 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2218 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 2219 uint32_t cpu_register_ptr; 2220 uint32_t dbgm_config_ptr; 2221 uint32_t alive_counter_ptr; 2222 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2223 uint32_t st_fwrd_addr; /* pointer to Store and forward */ 2224 uint32_t st_fwrd_size; 2225 uint32_t umac_minor; /* UMAC version: minor */ 2226 uint32_t umac_major; /* UMAC version: major */ 2227 uint32_t error_info_addr; /* SRAM address for UMAC error log */ 2228 uint32_t dbg_print_buff_addr; 2229 } __packed; /* ALIVE_RES_API_S_VER_3 */ 2230 2231 /* Error response/notification */ 2232 enum { 2233 IWM_FW_ERR_UNKNOWN_CMD = 0x0, 2234 IWM_FW_ERR_INVALID_CMD_PARAM = 0x1, 2235 IWM_FW_ERR_SERVICE = 0x2, 2236 IWM_FW_ERR_ARC_MEMORY = 0x3, 2237 IWM_FW_ERR_ARC_CODE = 0x4, 2238 IWM_FW_ERR_WATCH_DOG = 0x5, 2239 IWM_FW_ERR_WEP_GRP_KEY_INDX = 0x10, 2240 IWM_FW_ERR_WEP_KEY_SIZE = 0x11, 2241 IWM_FW_ERR_OBSOLETE_FUNC = 0x12, 2242 IWM_FW_ERR_UNEXPECTED = 0xFE, 2243 IWM_FW_ERR_FATAL = 0xFF 2244 }; 2245 2246 /** 2247 * struct iwm_error_resp - FW error indication 2248 * ( IWM_REPLY_ERROR = 0x2 ) 2249 * @error_type: one of IWM_FW_ERR_* 2250 * @cmd_id: the command ID for which the error occurred 2251 * @bad_cmd_seq_num: sequence number of the erroneous command 2252 * @error_service: which service created the error, applicable only if 2253 * error_type = 2, otherwise 0 2254 * @timestamp: TSF in usecs. 2255 */ 2256 struct iwm_error_resp { 2257 uint32_t error_type; 2258 uint8_t cmd_id; 2259 uint8_t reserved1; 2260 uint16_t bad_cmd_seq_num; 2261 uint32_t error_service; 2262 uint64_t timestamp; 2263 } __packed; 2264 2265 2266 /* Common PHY, MAC and Bindings definitions */ 2267 2268 #define IWM_MAX_MACS_IN_BINDING (3) 2269 #define IWM_MAX_BINDINGS (4) 2270 #define IWM_AUX_BINDING_INDEX (3) 2271 #define IWM_MAX_PHYS (4) 2272 2273 /* Used to extract ID and color from the context dword */ 2274 #define IWM_FW_CTXT_ID_POS (0) 2275 #define IWM_FW_CTXT_ID_MSK (0xff << IWM_FW_CTXT_ID_POS) 2276 #define IWM_FW_CTXT_COLOR_POS (8) 2277 #define IWM_FW_CTXT_COLOR_MSK (0xff << IWM_FW_CTXT_COLOR_POS) 2278 #define IWM_FW_CTXT_INVALID (0xffffffff) 2279 2280 #define IWM_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWM_FW_CTXT_ID_POS) |\ 2281 (_color << IWM_FW_CTXT_COLOR_POS)) 2282 2283 /* Possible actions on PHYs, MACs and Bindings */ 2284 enum { 2285 IWM_FW_CTXT_ACTION_STUB = 0, 2286 IWM_FW_CTXT_ACTION_ADD, 2287 IWM_FW_CTXT_ACTION_MODIFY, 2288 IWM_FW_CTXT_ACTION_REMOVE, 2289 IWM_FW_CTXT_ACTION_NUM 2290 }; /* COMMON_CONTEXT_ACTION_API_E_VER_1 */ 2291 2292 /* Time Events */ 2293 2294 /* Time Event types, according to MAC type */ 2295 enum iwm_time_event_type { 2296 /* BSS Station Events */ 2297 IWM_TE_BSS_STA_AGGRESSIVE_ASSOC, 2298 IWM_TE_BSS_STA_ASSOC, 2299 IWM_TE_BSS_EAP_DHCP_PROT, 2300 IWM_TE_BSS_QUIET_PERIOD, 2301 2302 /* P2P Device Events */ 2303 IWM_TE_P2P_DEVICE_DISCOVERABLE, 2304 IWM_TE_P2P_DEVICE_LISTEN, 2305 IWM_TE_P2P_DEVICE_ACTION_SCAN, 2306 IWM_TE_P2P_DEVICE_FULL_SCAN, 2307 2308 /* P2P Client Events */ 2309 IWM_TE_P2P_CLIENT_AGGRESSIVE_ASSOC, 2310 IWM_TE_P2P_CLIENT_ASSOC, 2311 IWM_TE_P2P_CLIENT_QUIET_PERIOD, 2312 2313 /* P2P GO Events */ 2314 IWM_TE_P2P_GO_ASSOC_PROT, 2315 IWM_TE_P2P_GO_REPETITIVE_NOA, 2316 IWM_TE_P2P_GO_CT_WINDOW, 2317 2318 /* WiDi Sync Events */ 2319 IWM_TE_WIDI_TX_SYNC, 2320 2321 IWM_TE_MAX 2322 }; /* IWM_MAC_EVENT_TYPE_API_E_VER_1 */ 2323 2324 2325 2326 /* Time event - defines for command API v1 */ 2327 2328 /* 2329 * @IWM_TE_V1_FRAG_NONE: fragmentation of the time event is NOT allowed. 2330 * @IWM_TE_V1_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2331 * the first fragment is scheduled. 2332 * @IWM_TE_V1_FRAG_DUAL: fragmentation of the time event is allowed, but only 2333 * the first 2 fragments are scheduled. 2334 * @IWM_TE_V1_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2335 * number of fragments are valid. 2336 * 2337 * Other than the constant defined above, specifying a fragmentation value 'x' 2338 * means that the event can be fragmented but only the first 'x' will be 2339 * scheduled. 2340 */ 2341 enum { 2342 IWM_TE_V1_FRAG_NONE = 0, 2343 IWM_TE_V1_FRAG_SINGLE = 1, 2344 IWM_TE_V1_FRAG_DUAL = 2, 2345 IWM_TE_V1_FRAG_ENDLESS = 0xffffffff 2346 }; 2347 2348 /* If a Time Event can be fragmented, this is the max number of fragments */ 2349 #define IWM_TE_V1_FRAG_MAX_MSK 0x0fffffff 2350 /* Repeat the time event endlessly (until removed) */ 2351 #define IWM_TE_V1_REPEAT_ENDLESS 0xffffffff 2352 /* If a Time Event has bounded repetitions, this is the maximal value */ 2353 #define IWM_TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff 2354 2355 /* Time Event dependencies: none, on another TE, or in a specific time */ 2356 enum { 2357 IWM_TE_V1_INDEPENDENT = 0, 2358 IWM_TE_V1_DEP_OTHER = (1 << 0), 2359 IWM_TE_V1_DEP_TSF = (1 << 1), 2360 IWM_TE_V1_EVENT_SOCIOPATHIC = (1 << 2), 2361 }; /* IWM_MAC_EVENT_DEPENDENCY_POLICY_API_E_VER_2 */ 2362 2363 /* 2364 * @IWM_TE_V1_NOTIF_NONE: no notifications 2365 * @IWM_TE_V1_NOTIF_HOST_EVENT_START: request/receive notification on event start 2366 * @IWM_TE_V1_NOTIF_HOST_EVENT_END:request/receive notification on event end 2367 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_START: internal FW use 2368 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_END: internal FW use. 2369 * @IWM_TE_V1_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2370 * @IWM_TE_V1_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2371 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_START: internal FW use. 2372 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_END: internal FW use. 2373 * 2374 * Supported Time event notifications configuration. 2375 * A notification (both event and fragment) includes a status indicating weather 2376 * the FW was able to schedule the event or not. For fragment start/end 2377 * notification the status is always success. There is no start/end fragment 2378 * notification for monolithic events. 2379 */ 2380 enum { 2381 IWM_TE_V1_NOTIF_NONE = 0, 2382 IWM_TE_V1_NOTIF_HOST_EVENT_START = (1 << 0), 2383 IWM_TE_V1_NOTIF_HOST_EVENT_END = (1 << 1), 2384 IWM_TE_V1_NOTIF_INTERNAL_EVENT_START = (1 << 2), 2385 IWM_TE_V1_NOTIF_INTERNAL_EVENT_END = (1 << 3), 2386 IWM_TE_V1_NOTIF_HOST_FRAG_START = (1 << 4), 2387 IWM_TE_V1_NOTIF_HOST_FRAG_END = (1 << 5), 2388 IWM_TE_V1_NOTIF_INTERNAL_FRAG_START = (1 << 6), 2389 IWM_TE_V1_NOTIF_INTERNAL_FRAG_END = (1 << 7), 2390 IWM_T2_V2_START_IMMEDIATELY = (1 << 11), 2391 }; /* IWM_MAC_EVENT_ACTION_API_E_VER_2 */ 2392 2393 2394 /** 2395 * struct iwm_time_event_cmd_api_v1 - configuring Time Events 2396 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_1 (see also 2397 * with version 2. determined by IWM_UCODE_TLV_FLAGS) 2398 * ( IWM_TIME_EVENT_CMD = 0x29 ) 2399 * @id_and_color: ID and color of the relevant MAC 2400 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2401 * @id: this field has two meanings, depending on the action: 2402 * If the action is ADD, then it means the type of event to add. 2403 * For all other actions it is the unique event ID assigned when the 2404 * event was added by the FW. 2405 * @apply_time: When to start the Time Event (in GP2) 2406 * @max_delay: maximum delay to event's start (apply time), in TU 2407 * @depends_on: the unique ID of the event we depend on (if any) 2408 * @interval: interval between repetitions, in TU 2409 * @interval_reciprocal: 2^32 / interval 2410 * @duration: duration of event in TU 2411 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS 2412 * @dep_policy: one of IWM_TE_V1_INDEPENDENT, IWM_TE_V1_DEP_OTHER, IWM_TE_V1_DEP_TSF 2413 * and IWM_TE_V1_EVENT_SOCIOPATHIC 2414 * @is_present: 0 or 1, are we present or absent during the Time Event 2415 * @max_frags: maximal number of fragments the Time Event can be divided to 2416 * @notify: notifications using IWM_TE_V1_NOTIF_* (whom to notify when) 2417 */ 2418 struct iwm_time_event_cmd_v1 { 2419 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2420 uint32_t id_and_color; 2421 uint32_t action; 2422 uint32_t id; 2423 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_1 */ 2424 uint32_t apply_time; 2425 uint32_t max_delay; 2426 uint32_t dep_policy; 2427 uint32_t depends_on; 2428 uint32_t is_present; 2429 uint32_t max_frags; 2430 uint32_t interval; 2431 uint32_t interval_reciprocal; 2432 uint32_t duration; 2433 uint32_t repeat; 2434 uint32_t notify; 2435 } __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_1 */ 2436 2437 2438 /* Time event - defines for command API v2 */ 2439 2440 /* 2441 * @IWM_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed. 2442 * @IWM_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2443 * the first fragment is scheduled. 2444 * @IWM_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only 2445 * the first 2 fragments are scheduled. 2446 * @IWM_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2447 * number of fragments are valid. 2448 * 2449 * Other than the constant defined above, specifying a fragmentation value 'x' 2450 * means that the event can be fragmented but only the first 'x' will be 2451 * scheduled. 2452 */ 2453 enum { 2454 IWM_TE_V2_FRAG_NONE = 0, 2455 IWM_TE_V2_FRAG_SINGLE = 1, 2456 IWM_TE_V2_FRAG_DUAL = 2, 2457 IWM_TE_V2_FRAG_MAX = 0xfe, 2458 IWM_TE_V2_FRAG_ENDLESS = 0xff 2459 }; 2460 2461 /* Repeat the time event endlessly (until removed) */ 2462 #define IWM_TE_V2_REPEAT_ENDLESS 0xff 2463 /* If a Time Event has bounded repetitions, this is the maximal value */ 2464 #define IWM_TE_V2_REPEAT_MAX 0xfe 2465 2466 #define IWM_TE_V2_PLACEMENT_POS 12 2467 #define IWM_TE_V2_ABSENCE_POS 15 2468 2469 /* Time event policy values (for time event cmd api v2) 2470 * A notification (both event and fragment) includes a status indicating weather 2471 * the FW was able to schedule the event or not. For fragment start/end 2472 * notification the status is always success. There is no start/end fragment 2473 * notification for monolithic events. 2474 * 2475 * @IWM_TE_V2_DEFAULT_POLICY: independent, social, present, unoticable 2476 * @IWM_TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start 2477 * @IWM_TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end 2478 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use 2479 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use. 2480 * @IWM_TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2481 * @IWM_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2482 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use. 2483 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use. 2484 * @IWM_TE_V2_DEP_OTHER: depends on another time event 2485 * @IWM_TE_V2_DEP_TSF: depends on a specific time 2486 * @IWM_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of tha same MAC 2487 * @IWM_TE_V2_ABSENCE: are we present or absent during the Time Event. 2488 */ 2489 enum { 2490 IWM_TE_V2_DEFAULT_POLICY = 0x0, 2491 2492 /* notifications (event start/stop, fragment start/stop) */ 2493 IWM_TE_V2_NOTIF_HOST_EVENT_START = (1 << 0), 2494 IWM_TE_V2_NOTIF_HOST_EVENT_END = (1 << 1), 2495 IWM_TE_V2_NOTIF_INTERNAL_EVENT_START = (1 << 2), 2496 IWM_TE_V2_NOTIF_INTERNAL_EVENT_END = (1 << 3), 2497 2498 IWM_TE_V2_NOTIF_HOST_FRAG_START = (1 << 4), 2499 IWM_TE_V2_NOTIF_HOST_FRAG_END = (1 << 5), 2500 IWM_TE_V2_NOTIF_INTERNAL_FRAG_START = (1 << 6), 2501 IWM_TE_V2_NOTIF_INTERNAL_FRAG_END = (1 << 7), 2502 2503 IWM_TE_V2_NOTIF_MSK = 0xff, 2504 2505 /* placement characteristics */ 2506 IWM_TE_V2_DEP_OTHER = (1 << IWM_TE_V2_PLACEMENT_POS), 2507 IWM_TE_V2_DEP_TSF = (1 << (IWM_TE_V2_PLACEMENT_POS + 1)), 2508 IWM_TE_V2_EVENT_SOCIOPATHIC = (1 << (IWM_TE_V2_PLACEMENT_POS + 2)), 2509 2510 /* are we present or absent during the Time Event. */ 2511 IWM_TE_V2_ABSENCE = (1 << IWM_TE_V2_ABSENCE_POS), 2512 }; 2513 2514 /** 2515 * struct iwm_time_event_cmd_api_v2 - configuring Time Events 2516 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also 2517 * with version 1. determined by IWM_UCODE_TLV_FLAGS) 2518 * ( IWM_TIME_EVENT_CMD = 0x29 ) 2519 * @id_and_color: ID and color of the relevant MAC 2520 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2521 * @id: this field has two meanings, depending on the action: 2522 * If the action is ADD, then it means the type of event to add. 2523 * For all other actions it is the unique event ID assigned when the 2524 * event was added by the FW. 2525 * @apply_time: When to start the Time Event (in GP2) 2526 * @max_delay: maximum delay to event's start (apply time), in TU 2527 * @depends_on: the unique ID of the event we depend on (if any) 2528 * @interval: interval between repetitions, in TU 2529 * @duration: duration of event in TU 2530 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS 2531 * @max_frags: maximal number of fragments the Time Event can be divided to 2532 * @policy: defines whether uCode shall notify the host or other uCode modules 2533 * on event and/or fragment start and/or end 2534 * using one of IWM_TE_INDEPENDENT, IWM_TE_DEP_OTHER, IWM_TE_DEP_TSF 2535 * IWM_TE_EVENT_SOCIOPATHIC 2536 * using IWM_TE_ABSENCE and using IWM_TE_NOTIF_* 2537 */ 2538 struct iwm_time_event_cmd_v2 { 2539 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2540 uint32_t id_and_color; 2541 uint32_t action; 2542 uint32_t id; 2543 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 */ 2544 uint32_t apply_time; 2545 uint32_t max_delay; 2546 uint32_t depends_on; 2547 uint32_t interval; 2548 uint32_t duration; 2549 uint8_t repeat; 2550 uint8_t max_frags; 2551 uint16_t policy; 2552 } __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_2 */ 2553 2554 /** 2555 * struct iwm_time_event_resp - response structure to iwm_time_event_cmd 2556 * @status: bit 0 indicates success, all others specify errors 2557 * @id: the Time Event type 2558 * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE 2559 * @id_and_color: ID and color of the relevant MAC 2560 */ 2561 struct iwm_time_event_resp { 2562 uint32_t status; 2563 uint32_t id; 2564 uint32_t unique_id; 2565 uint32_t id_and_color; 2566 } __packed; /* IWM_MAC_TIME_EVENT_RSP_API_S_VER_1 */ 2567 2568 /** 2569 * struct iwm_time_event_notif - notifications of time event start/stop 2570 * ( IWM_TIME_EVENT_NOTIFICATION = 0x2a ) 2571 * @timestamp: action timestamp in GP2 2572 * @session_id: session's unique id 2573 * @unique_id: unique id of the Time Event itself 2574 * @id_and_color: ID and color of the relevant MAC 2575 * @action: one of IWM_TE_NOTIF_START or IWM_TE_NOTIF_END 2576 * @status: true if scheduled, false otherwise (not executed) 2577 */ 2578 struct iwm_time_event_notif { 2579 uint32_t timestamp; 2580 uint32_t session_id; 2581 uint32_t unique_id; 2582 uint32_t id_and_color; 2583 uint32_t action; 2584 uint32_t status; 2585 } __packed; /* IWM_MAC_TIME_EVENT_NTFY_API_S_VER_1 */ 2586 2587 2588 /* Bindings and Time Quota */ 2589 2590 /** 2591 * struct iwm_binding_cmd - configuring bindings 2592 * ( IWM_BINDING_CONTEXT_CMD = 0x2b ) 2593 * @id_and_color: ID and color of the relevant Binding 2594 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2595 * @macs: array of MAC id and colors which belong to the binding 2596 * @phy: PHY id and color which belongs to the binding 2597 */ 2598 struct iwm_binding_cmd { 2599 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2600 uint32_t id_and_color; 2601 uint32_t action; 2602 /* IWM_BINDING_DATA_API_S_VER_1 */ 2603 uint32_t macs[IWM_MAX_MACS_IN_BINDING]; 2604 uint32_t phy; 2605 } __packed; /* IWM_BINDING_CMD_API_S_VER_1 */ 2606 2607 /* The maximal number of fragments in the FW's schedule session */ 2608 #define IWM_MVM_MAX_QUOTA 128 2609 2610 /** 2611 * struct iwm_time_quota_data - configuration of time quota per binding 2612 * @id_and_color: ID and color of the relevant Binding 2613 * @quota: absolute time quota in TU. The scheduler will try to divide the 2614 * remainig quota (after Time Events) according to this quota. 2615 * @max_duration: max uninterrupted context duration in TU 2616 */ 2617 struct iwm_time_quota_data { 2618 uint32_t id_and_color; 2619 uint32_t quota; 2620 uint32_t max_duration; 2621 } __packed; /* IWM_TIME_QUOTA_DATA_API_S_VER_1 */ 2622 2623 /** 2624 * struct iwm_time_quota_cmd - configuration of time quota between bindings 2625 * ( IWM_TIME_QUOTA_CMD = 0x2c ) 2626 * @quotas: allocations per binding 2627 */ 2628 struct iwm_time_quota_cmd { 2629 struct iwm_time_quota_data quotas[IWM_MAX_BINDINGS]; 2630 } __packed; /* IWM_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */ 2631 2632 2633 /* PHY context */ 2634 2635 /* Supported bands */ 2636 #define IWM_PHY_BAND_5 (0) 2637 #define IWM_PHY_BAND_24 (1) 2638 2639 /* Supported channel width, vary if there is VHT support */ 2640 #define IWM_PHY_VHT_CHANNEL_MODE20 (0x0) 2641 #define IWM_PHY_VHT_CHANNEL_MODE40 (0x1) 2642 #define IWM_PHY_VHT_CHANNEL_MODE80 (0x2) 2643 #define IWM_PHY_VHT_CHANNEL_MODE160 (0x3) 2644 2645 /* 2646 * Control channel position: 2647 * For legacy set bit means upper channel, otherwise lower. 2648 * For VHT - bit-2 marks if the control is lower/upper relative to center-freq 2649 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0. 2650 * center_freq 2651 * | 2652 * 40Mhz |_______|_______| 2653 * 80Mhz |_______|_______|_______|_______| 2654 * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______| 2655 * code 011 010 001 000 | 100 101 110 111 2656 */ 2657 #define IWM_PHY_VHT_CTRL_POS_1_BELOW (0x0) 2658 #define IWM_PHY_VHT_CTRL_POS_2_BELOW (0x1) 2659 #define IWM_PHY_VHT_CTRL_POS_3_BELOW (0x2) 2660 #define IWM_PHY_VHT_CTRL_POS_4_BELOW (0x3) 2661 #define IWM_PHY_VHT_CTRL_POS_1_ABOVE (0x4) 2662 #define IWM_PHY_VHT_CTRL_POS_2_ABOVE (0x5) 2663 #define IWM_PHY_VHT_CTRL_POS_3_ABOVE (0x6) 2664 #define IWM_PHY_VHT_CTRL_POS_4_ABOVE (0x7) 2665 2666 /* 2667 * @band: IWM_PHY_BAND_* 2668 * @channel: channel number 2669 * @width: PHY_[VHT|LEGACY]_CHANNEL_* 2670 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_* 2671 */ 2672 struct iwm_fw_channel_info { 2673 uint8_t band; 2674 uint8_t channel; 2675 uint8_t width; 2676 uint8_t ctrl_pos; 2677 } __packed; 2678 2679 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS (0) 2680 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_MSK \ 2681 (0x1 << IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS) 2682 #define IWM_PHY_RX_CHAIN_VALID_POS (1) 2683 #define IWM_PHY_RX_CHAIN_VALID_MSK \ 2684 (0x7 << IWM_PHY_RX_CHAIN_VALID_POS) 2685 #define IWM_PHY_RX_CHAIN_FORCE_SEL_POS (4) 2686 #define IWM_PHY_RX_CHAIN_FORCE_SEL_MSK \ 2687 (0x7 << IWM_PHY_RX_CHAIN_FORCE_SEL_POS) 2688 #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7) 2689 #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \ 2690 (0x7 << IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS) 2691 #define IWM_PHY_RX_CHAIN_CNT_POS (10) 2692 #define IWM_PHY_RX_CHAIN_CNT_MSK \ 2693 (0x3 << IWM_PHY_RX_CHAIN_CNT_POS) 2694 #define IWM_PHY_RX_CHAIN_MIMO_CNT_POS (12) 2695 #define IWM_PHY_RX_CHAIN_MIMO_CNT_MSK \ 2696 (0x3 << IWM_PHY_RX_CHAIN_MIMO_CNT_POS) 2697 #define IWM_PHY_RX_CHAIN_MIMO_FORCE_POS (14) 2698 #define IWM_PHY_RX_CHAIN_MIMO_FORCE_MSK \ 2699 (0x1 << IWM_PHY_RX_CHAIN_MIMO_FORCE_POS) 2700 2701 /* TODO: fix the value, make it depend on firmware at runtime? */ 2702 #define IWM_NUM_PHY_CTX 3 2703 2704 /* TODO: complete missing documentation */ 2705 /** 2706 * struct iwm_phy_context_cmd - config of the PHY context 2707 * ( IWM_PHY_CONTEXT_CMD = 0x8 ) 2708 * @id_and_color: ID and color of the relevant Binding 2709 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2710 * @apply_time: 0 means immediate apply and context switch. 2711 * other value means apply new params after X usecs 2712 * @tx_param_color: ??? 2713 * @channel_info: 2714 * @txchain_info: ??? 2715 * @rxchain_info: ??? 2716 * @acquisition_data: ??? 2717 * @dsp_cfg_flags: set to 0 2718 */ 2719 struct iwm_phy_context_cmd { 2720 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2721 uint32_t id_and_color; 2722 uint32_t action; 2723 /* IWM_PHY_CONTEXT_DATA_API_S_VER_1 */ 2724 uint32_t apply_time; 2725 uint32_t tx_param_color; 2726 struct iwm_fw_channel_info ci; 2727 uint32_t txchain_info; 2728 uint32_t rxchain_info; 2729 uint32_t acquisition_data; 2730 uint32_t dsp_cfg_flags; 2731 } __packed; /* IWM_PHY_CONTEXT_CMD_API_VER_1 */ 2732 2733 #define IWM_RX_INFO_PHY_CNT 8 2734 #define IWM_RX_INFO_ENERGY_ANT_ABC_IDX 1 2735 #define IWM_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff 2736 #define IWM_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00 2737 #define IWM_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000 2738 #define IWM_RX_INFO_ENERGY_ANT_A_POS 0 2739 #define IWM_RX_INFO_ENERGY_ANT_B_POS 8 2740 #define IWM_RX_INFO_ENERGY_ANT_C_POS 16 2741 2742 #define IWM_RX_INFO_AGC_IDX 1 2743 #define IWM_RX_INFO_RSSI_AB_IDX 2 2744 #define IWM_OFDM_AGC_A_MSK 0x0000007f 2745 #define IWM_OFDM_AGC_A_POS 0 2746 #define IWM_OFDM_AGC_B_MSK 0x00003f80 2747 #define IWM_OFDM_AGC_B_POS 7 2748 #define IWM_OFDM_AGC_CODE_MSK 0x3fe00000 2749 #define IWM_OFDM_AGC_CODE_POS 20 2750 #define IWM_OFDM_RSSI_INBAND_A_MSK 0x00ff 2751 #define IWM_OFDM_RSSI_A_POS 0 2752 #define IWM_OFDM_RSSI_ALLBAND_A_MSK 0xff00 2753 #define IWM_OFDM_RSSI_ALLBAND_A_POS 8 2754 #define IWM_OFDM_RSSI_INBAND_B_MSK 0xff0000 2755 #define IWM_OFDM_RSSI_B_POS 16 2756 #define IWM_OFDM_RSSI_ALLBAND_B_MSK 0xff000000 2757 #define IWM_OFDM_RSSI_ALLBAND_B_POS 24 2758 2759 /** 2760 * struct iwm_rx_phy_info - phy info 2761 * (IWM_REPLY_RX_PHY_CMD = 0xc0) 2762 * @non_cfg_phy_cnt: non configurable DSP phy data byte count 2763 * @cfg_phy_cnt: configurable DSP phy data byte count 2764 * @stat_id: configurable DSP phy data set ID 2765 * @reserved1: 2766 * @system_timestamp: GP2 at on air rise 2767 * @timestamp: TSF at on air rise 2768 * @beacon_time_stamp: beacon at on-air rise 2769 * @phy_flags: general phy flags: band, modulation, ... 2770 * @channel: channel number 2771 * @non_cfg_phy_buf: for various implementations of non_cfg_phy 2772 * @rate_n_flags: IWM_RATE_MCS_* 2773 * @byte_count: frame's byte-count 2774 * @frame_time: frame's time on the air, based on byte count and frame rate 2775 * calculation 2776 * @mac_active_msk: what MACs were active when the frame was received 2777 * 2778 * Before each Rx, the device sends this data. It contains PHY information 2779 * about the reception of the packet. 2780 */ 2781 struct iwm_rx_phy_info { 2782 uint8_t non_cfg_phy_cnt; 2783 uint8_t cfg_phy_cnt; 2784 uint8_t stat_id; 2785 uint8_t reserved1; 2786 uint32_t system_timestamp; 2787 uint64_t timestamp; 2788 uint32_t beacon_time_stamp; 2789 uint16_t phy_flags; 2790 #define IWM_PHY_INFO_FLAG_SHPREAMBLE (1 << 2) 2791 uint16_t channel; 2792 uint32_t non_cfg_phy[IWM_RX_INFO_PHY_CNT]; 2793 uint8_t rate; 2794 uint8_t rflags; 2795 uint16_t xrflags; 2796 uint32_t byte_count; 2797 uint16_t mac_active_msk; 2798 uint16_t frame_time; 2799 } __packed; 2800 2801 struct iwm_rx_mpdu_res_start { 2802 uint16_t byte_count; 2803 uint16_t reserved; 2804 } __packed; 2805 2806 /** 2807 * enum iwm_rx_phy_flags - to parse %iwm_rx_phy_info phy_flags 2808 * @IWM_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band 2809 * @IWM_RX_RES_PHY_FLAGS_MOD_CCK: 2810 * @IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short 2811 * @IWM_RX_RES_PHY_FLAGS_NARROW_BAND: 2812 * @IWM_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received 2813 * @IWM_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU 2814 * @IWM_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame 2815 * @IWM_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble 2816 * @IWM_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame 2817 */ 2818 enum iwm_rx_phy_flags { 2819 IWM_RX_RES_PHY_FLAGS_BAND_24 = (1 << 0), 2820 IWM_RX_RES_PHY_FLAGS_MOD_CCK = (1 << 1), 2821 IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE = (1 << 2), 2822 IWM_RX_RES_PHY_FLAGS_NARROW_BAND = (1 << 3), 2823 IWM_RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4), 2824 IWM_RX_RES_PHY_FLAGS_ANTENNA_POS = 4, 2825 IWM_RX_RES_PHY_FLAGS_AGG = (1 << 7), 2826 IWM_RX_RES_PHY_FLAGS_OFDM_HT = (1 << 8), 2827 IWM_RX_RES_PHY_FLAGS_OFDM_GF = (1 << 9), 2828 IWM_RX_RES_PHY_FLAGS_OFDM_VHT = (1 << 10), 2829 }; 2830 2831 /** 2832 * enum iwm_mvm_rx_status - written by fw for each Rx packet 2833 * @IWM_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine 2834 * @IWM_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow 2835 * @IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND: 2836 * @IWM_RX_MPDU_RES_STATUS_KEY_VALID: 2837 * @IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK: 2838 * @IWM_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed 2839 * @IWM_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked 2840 * in the driver. 2841 * @IWM_RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine 2842 * @IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or 2843 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if 2844 * %IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set. 2845 * @IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted 2846 * @IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP 2847 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM 2848 * @IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP 2849 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC 2850 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted 2851 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm 2852 * @IWM_RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted 2853 * @IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP: 2854 * @IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP: 2855 * @IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT: 2856 * @IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame 2857 * @IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK: 2858 * @IWM_RX_MPDU_RES_STATUS_STA_ID_MSK: 2859 * @IWM_RX_MPDU_RES_STATUS_RRF_KILL: 2860 * @IWM_RX_MPDU_RES_STATUS_FILTERING_MSK: 2861 * @IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK: 2862 */ 2863 enum iwm_mvm_rx_status { 2864 IWM_RX_MPDU_RES_STATUS_CRC_OK = (1 << 0), 2865 IWM_RX_MPDU_RES_STATUS_OVERRUN_OK = (1 << 1), 2866 IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND = (1 << 2), 2867 IWM_RX_MPDU_RES_STATUS_KEY_VALID = (1 << 3), 2868 IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK = (1 << 4), 2869 IWM_RX_MPDU_RES_STATUS_ICV_OK = (1 << 5), 2870 IWM_RX_MPDU_RES_STATUS_MIC_OK = (1 << 6), 2871 IWM_RX_MPDU_RES_STATUS_TTAK_OK = (1 << 7), 2872 IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = (1 << 7), 2873 IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8), 2874 IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8), 2875 IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8), 2876 IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8), 2877 IWM_RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8), 2878 IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8), 2879 IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8), 2880 IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8), 2881 IWM_RX_MPDU_RES_STATUS_DEC_DONE = (1 << 11), 2882 IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP = (1 << 12), 2883 IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = (1 << 13), 2884 IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = (1 << 14), 2885 IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = (1 << 15), 2886 IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK = (0x3F0000), 2887 IWM_RX_MPDU_RES_STATUS_STA_ID_MSK = (0x1f000000), 2888 IWM_RX_MPDU_RES_STATUS_RRF_KILL = (1 << 29), 2889 IWM_RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000), 2890 IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000), 2891 }; 2892 2893 /** 2894 * struct iwm_radio_version_notif - information on the radio version 2895 * ( IWM_RADIO_VERSION_NOTIFICATION = 0x68 ) 2896 * @radio_flavor: 2897 * @radio_step: 2898 * @radio_dash: 2899 */ 2900 struct iwm_radio_version_notif { 2901 uint32_t radio_flavor; 2902 uint32_t radio_step; 2903 uint32_t radio_dash; 2904 } __packed; /* IWM_RADIO_VERSION_NOTOFICATION_S_VER_1 */ 2905 2906 enum iwm_card_state_flags { 2907 IWM_CARD_ENABLED = 0x00, 2908 IWM_HW_CARD_DISABLED = 0x01, 2909 IWM_SW_CARD_DISABLED = 0x02, 2910 IWM_CT_KILL_CARD_DISABLED = 0x04, 2911 IWM_HALT_CARD_DISABLED = 0x08, 2912 IWM_CARD_DISABLED_MSK = 0x0f, 2913 IWM_CARD_IS_RX_ON = 0x10, 2914 }; 2915 2916 /** 2917 * struct iwm_radio_version_notif - information on the radio version 2918 * (IWM_CARD_STATE_NOTIFICATION = 0xa1 ) 2919 * @flags: %iwm_card_state_flags 2920 */ 2921 struct iwm_card_state_notif { 2922 uint32_t flags; 2923 } __packed; /* CARD_STATE_NTFY_API_S_VER_1 */ 2924 2925 /** 2926 * struct iwm_missed_beacons_notif - information on missed beacons 2927 * ( IWM_MISSED_BEACONS_NOTIFICATION = 0xa2 ) 2928 * @mac_id: interface ID 2929 * @consec_missed_beacons_since_last_rx: number of consecutive missed 2930 * beacons since last RX. 2931 * @consec_missed_beacons: number of consecutive missed beacons 2932 * @num_expected_beacons: 2933 * @num_recvd_beacons: 2934 */ 2935 struct iwm_missed_beacons_notif { 2936 uint32_t mac_id; 2937 uint32_t consec_missed_beacons_since_last_rx; 2938 uint32_t consec_missed_beacons; 2939 uint32_t num_expected_beacons; 2940 uint32_t num_recvd_beacons; 2941 } __packed; /* IWM_MISSED_BEACON_NTFY_API_S_VER_3 */ 2942 2943 /** 2944 * struct iwm_mfuart_load_notif - mfuart image version & status 2945 * ( IWM_MFUART_LOAD_NOTIFICATION = 0xb1 ) 2946 * @installed_ver: installed image version 2947 * @external_ver: external image version 2948 * @status: MFUART loading status 2949 * @duration: MFUART loading time 2950 */ 2951 struct iwm_mfuart_load_notif { 2952 uint32_t installed_ver; 2953 uint32_t external_ver; 2954 uint32_t status; 2955 uint32_t duration; 2956 } __packed; /*MFU_LOADER_NTFY_API_S_VER_1*/ 2957 2958 /** 2959 * struct iwm_set_calib_default_cmd - set default value for calibration. 2960 * ( IWM_SET_CALIB_DEFAULT_CMD = 0x8e ) 2961 * @calib_index: the calibration to set value for 2962 * @length: of data 2963 * @data: the value to set for the calibration result 2964 */ 2965 struct iwm_set_calib_default_cmd { 2966 uint16_t calib_index; 2967 uint16_t length; 2968 uint8_t data[0]; 2969 } __packed; /* IWM_PHY_CALIB_OVERRIDE_VALUES_S */ 2970 2971 #define IWM_MAX_PORT_ID_NUM 2 2972 #define IWM_MAX_MCAST_FILTERING_ADDRESSES 256 2973 2974 /** 2975 * struct iwm_mcast_filter_cmd - configure multicast filter. 2976 * @filter_own: Set 1 to filter out multicast packets sent by station itself 2977 * @port_id: Multicast MAC addresses array specifier. This is a strange way 2978 * to identify network interface adopted in host-device IF. 2979 * It is used by FW as index in array of addresses. This array has 2980 * IWM_MAX_PORT_ID_NUM members. 2981 * @count: Number of MAC addresses in the array 2982 * @pass_all: Set 1 to pass all multicast packets. 2983 * @bssid: current association BSSID. 2984 * @addr_list: Place holder for array of MAC addresses. 2985 * IMPORTANT: add padding if necessary to ensure DWORD alignment. 2986 */ 2987 struct iwm_mcast_filter_cmd { 2988 uint8_t filter_own; 2989 uint8_t port_id; 2990 uint8_t count; 2991 uint8_t pass_all; 2992 uint8_t bssid[6]; 2993 uint8_t reserved[2]; 2994 uint8_t addr_list[0]; 2995 } __packed; /* IWM_MCAST_FILTERING_CMD_API_S_VER_1 */ 2996 2997 struct iwm_mvm_statistics_dbg { 2998 uint32_t burst_check; 2999 uint32_t burst_count; 3000 uint32_t wait_for_silence_timeout_cnt; 3001 uint32_t reserved[3]; 3002 } __packed; /* IWM_STATISTICS_DEBUG_API_S_VER_2 */ 3003 3004 struct iwm_mvm_statistics_div { 3005 uint32_t tx_on_a; 3006 uint32_t tx_on_b; 3007 uint32_t exec_time; 3008 uint32_t probe_time; 3009 uint32_t rssi_ant; 3010 uint32_t reserved2; 3011 } __packed; /* IWM_STATISTICS_SLOW_DIV_API_S_VER_2 */ 3012 3013 struct iwm_mvm_statistics_general_common { 3014 uint32_t temperature; /* radio temperature */ 3015 uint32_t temperature_m; /* radio voltage */ 3016 struct iwm_mvm_statistics_dbg dbg; 3017 uint32_t sleep_time; 3018 uint32_t slots_out; 3019 uint32_t slots_idle; 3020 uint32_t ttl_timestamp; 3021 struct iwm_mvm_statistics_div div; 3022 uint32_t rx_enable_counter; 3023 /* 3024 * num_of_sos_states: 3025 * count the number of times we have to re-tune 3026 * in order to get out of bad PHY status 3027 */ 3028 uint32_t num_of_sos_states; 3029 } __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */ 3030 3031 struct iwm_mvm_statistics_rx_non_phy { 3032 uint32_t bogus_cts; /* CTS received when not expecting CTS */ 3033 uint32_t bogus_ack; /* ACK received when not expecting ACK */ 3034 uint32_t non_bssid_frames; /* number of frames with BSSID that 3035 * doesn't belong to the STA BSSID */ 3036 uint32_t filtered_frames; /* count frames that were dumped in the 3037 * filtering process */ 3038 uint32_t non_channel_beacons; /* beacons with our bss id but not on 3039 * our serving channel */ 3040 uint32_t channel_beacons; /* beacons with our bss id and in our 3041 * serving channel */ 3042 uint32_t num_missed_bcon; /* number of missed beacons */ 3043 uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the 3044 * ADC was in saturation */ 3045 uint32_t ina_detection_search_time;/* total time (in 0.8us) searched 3046 * for INA */ 3047 uint32_t beacon_silence_rssi[3];/* RSSI silence after beacon frame */ 3048 uint32_t interference_data_flag; /* flag for interference data 3049 * availability. 1 when data is 3050 * available. */ 3051 uint32_t channel_load; /* counts RX Enable time in uSec */ 3052 uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM 3053 * and CCK) counter */ 3054 uint32_t beacon_rssi_a; 3055 uint32_t beacon_rssi_b; 3056 uint32_t beacon_rssi_c; 3057 uint32_t beacon_energy_a; 3058 uint32_t beacon_energy_b; 3059 uint32_t beacon_energy_c; 3060 uint32_t num_bt_kills; 3061 uint32_t mac_id; 3062 uint32_t directed_data_mpdu; 3063 } __packed; /* IWM_STATISTICS_RX_NON_PHY_API_S_VER_3 */ 3064 3065 struct iwm_mvm_statistics_rx_phy { 3066 uint32_t ina_cnt; 3067 uint32_t fina_cnt; 3068 uint32_t plcp_err; 3069 uint32_t crc32_err; 3070 uint32_t overrun_err; 3071 uint32_t early_overrun_err; 3072 uint32_t crc32_good; 3073 uint32_t false_alarm_cnt; 3074 uint32_t fina_sync_err_cnt; 3075 uint32_t sfd_timeout; 3076 uint32_t fina_timeout; 3077 uint32_t unresponded_rts; 3078 uint32_t rxe_frame_limit_overrun; 3079 uint32_t sent_ack_cnt; 3080 uint32_t sent_cts_cnt; 3081 uint32_t sent_ba_rsp_cnt; 3082 uint32_t dsp_self_kill; 3083 uint32_t mh_format_err; 3084 uint32_t re_acq_main_rssi_sum; 3085 uint32_t reserved; 3086 } __packed; /* IWM_STATISTICS_RX_PHY_API_S_VER_2 */ 3087 3088 struct iwm_mvm_statistics_rx_ht_phy { 3089 uint32_t plcp_err; 3090 uint32_t overrun_err; 3091 uint32_t early_overrun_err; 3092 uint32_t crc32_good; 3093 uint32_t crc32_err; 3094 uint32_t mh_format_err; 3095 uint32_t agg_crc32_good; 3096 uint32_t agg_mpdu_cnt; 3097 uint32_t agg_cnt; 3098 uint32_t unsupport_mcs; 3099 } __packed; /* IWM_STATISTICS_HT_RX_PHY_API_S_VER_1 */ 3100 3101 #define IWM_MAX_CHAINS 3 3102 3103 struct iwm_mvm_statistics_tx_non_phy_agg { 3104 uint32_t ba_timeout; 3105 uint32_t ba_reschedule_frames; 3106 uint32_t scd_query_agg_frame_cnt; 3107 uint32_t scd_query_no_agg; 3108 uint32_t scd_query_agg; 3109 uint32_t scd_query_mismatch; 3110 uint32_t frame_not_ready; 3111 uint32_t underrun; 3112 uint32_t bt_prio_kill; 3113 uint32_t rx_ba_rsp_cnt; 3114 int8_t txpower[IWM_MAX_CHAINS]; 3115 int8_t reserved; 3116 uint32_t reserved2; 3117 } __packed; /* IWM_STATISTICS_TX_NON_PHY_AGG_API_S_VER_1 */ 3118 3119 struct iwm_mvm_statistics_tx_channel_width { 3120 uint32_t ext_cca_narrow_ch20[1]; 3121 uint32_t ext_cca_narrow_ch40[2]; 3122 uint32_t ext_cca_narrow_ch80[3]; 3123 uint32_t ext_cca_narrow_ch160[4]; 3124 uint32_t last_tx_ch_width_indx; 3125 uint32_t rx_detected_per_ch_width[4]; 3126 uint32_t success_per_ch_width[4]; 3127 uint32_t fail_per_ch_width[4]; 3128 }; /* IWM_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */ 3129 3130 struct iwm_mvm_statistics_tx { 3131 uint32_t preamble_cnt; 3132 uint32_t rx_detected_cnt; 3133 uint32_t bt_prio_defer_cnt; 3134 uint32_t bt_prio_kill_cnt; 3135 uint32_t few_bytes_cnt; 3136 uint32_t cts_timeout; 3137 uint32_t ack_timeout; 3138 uint32_t expected_ack_cnt; 3139 uint32_t actual_ack_cnt; 3140 uint32_t dump_msdu_cnt; 3141 uint32_t burst_abort_next_frame_mismatch_cnt; 3142 uint32_t burst_abort_missing_next_frame_cnt; 3143 uint32_t cts_timeout_collision; 3144 uint32_t ack_or_ba_timeout_collision; 3145 struct iwm_mvm_statistics_tx_non_phy_agg agg; 3146 struct iwm_mvm_statistics_tx_channel_width channel_width; 3147 } __packed; /* IWM_STATISTICS_TX_API_S_VER_4 */ 3148 3149 3150 struct iwm_mvm_statistics_bt_activity { 3151 uint32_t hi_priority_tx_req_cnt; 3152 uint32_t hi_priority_tx_denied_cnt; 3153 uint32_t lo_priority_tx_req_cnt; 3154 uint32_t lo_priority_tx_denied_cnt; 3155 uint32_t hi_priority_rx_req_cnt; 3156 uint32_t hi_priority_rx_denied_cnt; 3157 uint32_t lo_priority_rx_req_cnt; 3158 uint32_t lo_priority_rx_denied_cnt; 3159 } __packed; /* IWM_STATISTICS_BT_ACTIVITY_API_S_VER_1 */ 3160 3161 struct iwm_mvm_statistics_general { 3162 struct iwm_mvm_statistics_general_common common; 3163 uint32_t beacon_filtered; 3164 uint32_t missed_beacons; 3165 int8_t beacon_filter_average_energy; 3166 int8_t beacon_filter_reason; 3167 int8_t beacon_filter_current_energy; 3168 int8_t beacon_filter_reserved; 3169 uint32_t beacon_filter_delta_time; 3170 struct iwm_mvm_statistics_bt_activity bt_activity; 3171 } __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */ 3172 3173 struct iwm_mvm_statistics_rx { 3174 struct iwm_mvm_statistics_rx_phy ofdm; 3175 struct iwm_mvm_statistics_rx_phy cck; 3176 struct iwm_mvm_statistics_rx_non_phy general; 3177 struct iwm_mvm_statistics_rx_ht_phy ofdm_ht; 3178 } __packed; /* IWM_STATISTICS_RX_API_S_VER_3 */ 3179 3180 /* 3181 * IWM_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command) 3182 * 3183 * By default, uCode issues this notification after receiving a beacon 3184 * while associated. To disable this behavior, set DISABLE_NOTIF flag in the 3185 * IWM_REPLY_STATISTICS_CMD 0x9c, above. 3186 * 3187 * Statistics counters continue to increment beacon after beacon, but are 3188 * cleared when changing channels or when driver issues IWM_REPLY_STATISTICS_CMD 3189 * 0x9c with CLEAR_STATS bit set (see above). 3190 * 3191 * uCode also issues this notification during scans. uCode clears statistics 3192 * appropriately so that each notification contains statistics for only the 3193 * one channel that has just been scanned. 3194 */ 3195 3196 struct iwm_notif_statistics { /* IWM_STATISTICS_NTFY_API_S_VER_8 */ 3197 uint32_t flag; 3198 struct iwm_mvm_statistics_rx rx; 3199 struct iwm_mvm_statistics_tx tx; 3200 struct iwm_mvm_statistics_general general; 3201 } __packed; 3202 3203 /*********************************** 3204 * Smart Fifo API 3205 ***********************************/ 3206 /* Smart Fifo state */ 3207 enum iwm_sf_state { 3208 IWM_SF_LONG_DELAY_ON = 0, /* should never be called by driver */ 3209 IWM_SF_FULL_ON, 3210 IWM_SF_UNINIT, 3211 IWM_SF_INIT_OFF, 3212 IWM_SF_HW_NUM_STATES 3213 }; 3214 3215 /* Smart Fifo possible scenario */ 3216 enum iwm_sf_scenario { 3217 IWM_SF_SCENARIO_SINGLE_UNICAST, 3218 IWM_SF_SCENARIO_AGG_UNICAST, 3219 IWM_SF_SCENARIO_MULTICAST, 3220 IWM_SF_SCENARIO_BA_RESP, 3221 IWM_SF_SCENARIO_TX_RESP, 3222 IWM_SF_NUM_SCENARIO 3223 }; 3224 3225 #define IWM_SF_TRANSIENT_STATES_NUMBER 2 /* IWM_SF_LONG_DELAY_ON and IWM_SF_FULL_ON */ 3226 #define IWM_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */ 3227 3228 /* smart FIFO default values */ 3229 #define IWM_SF_W_MARK_SISO 4096 3230 #define IWM_SF_W_MARK_MIMO2 8192 3231 #define IWM_SF_W_MARK_MIMO3 6144 3232 #define IWM_SF_W_MARK_LEGACY 4096 3233 #define IWM_SF_W_MARK_SCAN 4096 3234 3235 /* SF Scenarios timers for default configuration (aligned to 32 uSec) */ 3236 #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3237 #define IWM_SF_SINGLE_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3238 #define IWM_SF_AGG_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3239 #define IWM_SF_AGG_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3240 #define IWM_SF_MCAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3241 #define IWM_SF_MCAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3242 #define IWM_SF_BA_IDLE_TIMER_DEF 160 /* 150 uSec */ 3243 #define IWM_SF_BA_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3244 #define IWM_SF_TX_RE_IDLE_TIMER_DEF 160 /* 150 uSec */ 3245 #define IWM_SF_TX_RE_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3246 3247 /* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */ 3248 #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3249 #define IWM_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3250 #define IWM_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3251 #define IWM_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3252 #define IWM_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */ 3253 #define IWM_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */ 3254 #define IWM_SF_BA_IDLE_TIMER 320 /* 300 uSec */ 3255 #define IWM_SF_BA_AGING_TIMER 2016 /* 2 mSec */ 3256 #define IWM_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */ 3257 #define IWM_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */ 3258 3259 #define IWM_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */ 3260 3261 #define IWM_SF_CFG_DUMMY_NOTIF_OFF (1 << 16) 3262 3263 /** 3264 * Smart Fifo configuration command. 3265 * @state: smart fifo state, types listed in iwm_sf_state. 3266 * @watermark: Minimum allowed available free space in RXF for transient state. 3267 * @long_delay_timeouts: aging and idle timer values for each scenario 3268 * in long delay state. 3269 * @full_on_timeouts: timer values for each scenario in full on state. 3270 */ 3271 struct iwm_sf_cfg_cmd { 3272 uint32_t state; 3273 uint32_t watermark[IWM_SF_TRANSIENT_STATES_NUMBER]; 3274 uint32_t long_delay_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 3275 uint32_t full_on_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 3276 } __packed; /* IWM_SF_CFG_API_S_VER_2 */ 3277 3278 /* 3279 * END mvm/fw-api.h 3280 */ 3281 3282 /* 3283 * BEGIN mvm/fw-api-mac.h 3284 */ 3285 3286 /* 3287 * The first MAC indices (starting from 0) 3288 * are available to the driver, AUX follows 3289 */ 3290 #define IWM_MAC_INDEX_AUX 4 3291 #define IWM_MAC_INDEX_MIN_DRIVER 0 3292 #define IWM_NUM_MAC_INDEX_DRIVER IWM_MAC_INDEX_AUX 3293 3294 enum iwm_ac { 3295 IWM_AC_BK, 3296 IWM_AC_BE, 3297 IWM_AC_VI, 3298 IWM_AC_VO, 3299 IWM_AC_NUM, 3300 }; 3301 3302 /** 3303 * enum iwm_mac_protection_flags - MAC context flags 3304 * @IWM_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames, 3305 * this will require CCK RTS/CTS2self. 3306 * RTS/CTS will protect full burst time. 3307 * @IWM_MAC_PROT_FLG_HT_PROT: enable HT protection 3308 * @IWM_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions 3309 * @IWM_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self 3310 */ 3311 enum iwm_mac_protection_flags { 3312 IWM_MAC_PROT_FLG_TGG_PROTECT = (1 << 3), 3313 IWM_MAC_PROT_FLG_HT_PROT = (1 << 23), 3314 IWM_MAC_PROT_FLG_FAT_PROT = (1 << 24), 3315 IWM_MAC_PROT_FLG_SELF_CTS_EN = (1 << 30), 3316 }; 3317 3318 #define IWM_MAC_FLG_SHORT_SLOT (1 << 4) 3319 #define IWM_MAC_FLG_SHORT_PREAMBLE (1 << 5) 3320 3321 /** 3322 * enum iwm_mac_types - Supported MAC types 3323 * @IWM_FW_MAC_TYPE_FIRST: lowest supported MAC type 3324 * @IWM_FW_MAC_TYPE_AUX: Auxiliary MAC (internal) 3325 * @IWM_FW_MAC_TYPE_LISTENER: monitor MAC type (?) 3326 * @IWM_FW_MAC_TYPE_PIBSS: Pseudo-IBSS 3327 * @IWM_FW_MAC_TYPE_IBSS: IBSS 3328 * @IWM_FW_MAC_TYPE_BSS_STA: BSS (managed) station 3329 * @IWM_FW_MAC_TYPE_P2P_DEVICE: P2P Device 3330 * @IWM_FW_MAC_TYPE_P2P_STA: P2P client 3331 * @IWM_FW_MAC_TYPE_GO: P2P GO 3332 * @IWM_FW_MAC_TYPE_TEST: ? 3333 * @IWM_FW_MAC_TYPE_MAX: highest support MAC type 3334 */ 3335 enum iwm_mac_types { 3336 IWM_FW_MAC_TYPE_FIRST = 1, 3337 IWM_FW_MAC_TYPE_AUX = IWM_FW_MAC_TYPE_FIRST, 3338 IWM_FW_MAC_TYPE_LISTENER, 3339 IWM_FW_MAC_TYPE_PIBSS, 3340 IWM_FW_MAC_TYPE_IBSS, 3341 IWM_FW_MAC_TYPE_BSS_STA, 3342 IWM_FW_MAC_TYPE_P2P_DEVICE, 3343 IWM_FW_MAC_TYPE_P2P_STA, 3344 IWM_FW_MAC_TYPE_GO, 3345 IWM_FW_MAC_TYPE_TEST, 3346 IWM_FW_MAC_TYPE_MAX = IWM_FW_MAC_TYPE_TEST 3347 }; /* IWM_MAC_CONTEXT_TYPE_API_E_VER_1 */ 3348 3349 /** 3350 * enum iwm_tsf_id - TSF hw timer ID 3351 * @IWM_TSF_ID_A: use TSF A 3352 * @IWM_TSF_ID_B: use TSF B 3353 * @IWM_TSF_ID_C: use TSF C 3354 * @IWM_TSF_ID_D: use TSF D 3355 * @IWM_NUM_TSF_IDS: number of TSF timers available 3356 */ 3357 enum iwm_tsf_id { 3358 IWM_TSF_ID_A = 0, 3359 IWM_TSF_ID_B = 1, 3360 IWM_TSF_ID_C = 2, 3361 IWM_TSF_ID_D = 3, 3362 IWM_NUM_TSF_IDS = 4, 3363 }; /* IWM_TSF_ID_API_E_VER_1 */ 3364 3365 /** 3366 * struct iwm_mac_data_ap - configuration data for AP MAC context 3367 * @beacon_time: beacon transmit time in system time 3368 * @beacon_tsf: beacon transmit time in TSF 3369 * @bi: beacon interval in TU 3370 * @bi_reciprocal: 2^32 / bi 3371 * @dtim_interval: dtim transmit time in TU 3372 * @dtim_reciprocal: 2^32 / dtim_interval 3373 * @mcast_qid: queue ID for multicast traffic 3374 * @beacon_template: beacon template ID 3375 */ 3376 struct iwm_mac_data_ap { 3377 uint32_t beacon_time; 3378 uint64_t beacon_tsf; 3379 uint32_t bi; 3380 uint32_t bi_reciprocal; 3381 uint32_t dtim_interval; 3382 uint32_t dtim_reciprocal; 3383 uint32_t mcast_qid; 3384 uint32_t beacon_template; 3385 } __packed; /* AP_MAC_DATA_API_S_VER_1 */ 3386 3387 /** 3388 * struct iwm_mac_data_ibss - configuration data for IBSS MAC context 3389 * @beacon_time: beacon transmit time in system time 3390 * @beacon_tsf: beacon transmit time in TSF 3391 * @bi: beacon interval in TU 3392 * @bi_reciprocal: 2^32 / bi 3393 * @beacon_template: beacon template ID 3394 */ 3395 struct iwm_mac_data_ibss { 3396 uint32_t beacon_time; 3397 uint64_t beacon_tsf; 3398 uint32_t bi; 3399 uint32_t bi_reciprocal; 3400 uint32_t beacon_template; 3401 } __packed; /* IBSS_MAC_DATA_API_S_VER_1 */ 3402 3403 /** 3404 * struct iwm_mac_data_sta - configuration data for station MAC context 3405 * @is_assoc: 1 for associated state, 0 otherwise 3406 * @dtim_time: DTIM arrival time in system time 3407 * @dtim_tsf: DTIM arrival time in TSF 3408 * @bi: beacon interval in TU, applicable only when associated 3409 * @bi_reciprocal: 2^32 / bi , applicable only when associated 3410 * @dtim_interval: DTIM interval in TU, applicable only when associated 3411 * @dtim_reciprocal: 2^32 / dtim_interval , applicable only when associated 3412 * @listen_interval: in beacon intervals, applicable only when associated 3413 * @assoc_id: unique ID assigned by the AP during association 3414 */ 3415 struct iwm_mac_data_sta { 3416 uint32_t is_assoc; 3417 uint32_t dtim_time; 3418 uint64_t dtim_tsf; 3419 uint32_t bi; 3420 uint32_t bi_reciprocal; 3421 uint32_t dtim_interval; 3422 uint32_t dtim_reciprocal; 3423 uint32_t listen_interval; 3424 uint32_t assoc_id; 3425 uint32_t assoc_beacon_arrive_time; 3426 } __packed; /* IWM_STA_MAC_DATA_API_S_VER_1 */ 3427 3428 /** 3429 * struct iwm_mac_data_go - configuration data for P2P GO MAC context 3430 * @ap: iwm_mac_data_ap struct with most config data 3431 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3432 * 0 indicates that there is no CT window. 3433 * @opp_ps_enabled: indicate that opportunistic PS allowed 3434 */ 3435 struct iwm_mac_data_go { 3436 struct iwm_mac_data_ap ap; 3437 uint32_t ctwin; 3438 uint32_t opp_ps_enabled; 3439 } __packed; /* GO_MAC_DATA_API_S_VER_1 */ 3440 3441 /** 3442 * struct iwm_mac_data_p2p_sta - configuration data for P2P client MAC context 3443 * @sta: iwm_mac_data_sta struct with most config data 3444 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3445 * 0 indicates that there is no CT window. 3446 */ 3447 struct iwm_mac_data_p2p_sta { 3448 struct iwm_mac_data_sta sta; 3449 uint32_t ctwin; 3450 } __packed; /* P2P_STA_MAC_DATA_API_S_VER_1 */ 3451 3452 /** 3453 * struct iwm_mac_data_pibss - Pseudo IBSS config data 3454 * @stats_interval: interval in TU between statistics notifications to host. 3455 */ 3456 struct iwm_mac_data_pibss { 3457 uint32_t stats_interval; 3458 } __packed; /* PIBSS_MAC_DATA_API_S_VER_1 */ 3459 3460 /* 3461 * struct iwm_mac_data_p2p_dev - configuration data for the P2P Device MAC 3462 * context. 3463 * @is_disc_extended: if set to true, P2P Device discoverability is enabled on 3464 * other channels as well. This should be to true only in case that the 3465 * device is discoverable and there is an active GO. Note that setting this 3466 * field when not needed, will increase the number of interrupts and have 3467 * effect on the platform power, as this setting opens the Rx filters on 3468 * all macs. 3469 */ 3470 struct iwm_mac_data_p2p_dev { 3471 uint32_t is_disc_extended; 3472 } __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */ 3473 3474 /** 3475 * enum iwm_mac_filter_flags - MAC context filter flags 3476 * @IWM_MAC_FILTER_IN_PROMISC: accept all data frames 3477 * @IWM_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all mangement and 3478 * control frames to the host 3479 * @IWM_MAC_FILTER_ACCEPT_GRP: accept multicast frames 3480 * @IWM_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames 3481 * @IWM_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames 3482 * @IWM_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host 3483 * (in station mode when associated) 3484 * @IWM_MAC_FILTER_OUT_BCAST: filter out all broadcast frames 3485 * @IWM_MAC_FILTER_IN_CRC32: extract FCS and append it to frames 3486 * @IWM_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host 3487 */ 3488 enum iwm_mac_filter_flags { 3489 IWM_MAC_FILTER_IN_PROMISC = (1 << 0), 3490 IWM_MAC_FILTER_IN_CONTROL_AND_MGMT = (1 << 1), 3491 IWM_MAC_FILTER_ACCEPT_GRP = (1 << 2), 3492 IWM_MAC_FILTER_DIS_DECRYPT = (1 << 3), 3493 IWM_MAC_FILTER_DIS_GRP_DECRYPT = (1 << 4), 3494 IWM_MAC_FILTER_IN_BEACON = (1 << 6), 3495 IWM_MAC_FILTER_OUT_BCAST = (1 << 8), 3496 IWM_MAC_FILTER_IN_CRC32 = (1 << 11), 3497 IWM_MAC_FILTER_IN_PROBE_REQUEST = (1 << 12), 3498 }; 3499 3500 /** 3501 * enum iwm_mac_qos_flags - QoS flags 3502 * @IWM_MAC_QOS_FLG_UPDATE_EDCA: ? 3503 * @IWM_MAC_QOS_FLG_TGN: HT is enabled 3504 * @IWM_MAC_QOS_FLG_TXOP_TYPE: ? 3505 * 3506 */ 3507 enum iwm_mac_qos_flags { 3508 IWM_MAC_QOS_FLG_UPDATE_EDCA = (1 << 0), 3509 IWM_MAC_QOS_FLG_TGN = (1 << 1), 3510 IWM_MAC_QOS_FLG_TXOP_TYPE = (1 << 4), 3511 }; 3512 3513 /** 3514 * struct iwm_ac_qos - QOS timing params for IWM_MAC_CONTEXT_CMD 3515 * @cw_min: Contention window, start value in numbers of slots. 3516 * Should be a power-of-2, minus 1. Device's default is 0x0f. 3517 * @cw_max: Contention window, max value in numbers of slots. 3518 * Should be a power-of-2, minus 1. Device's default is 0x3f. 3519 * @aifsn: Number of slots in Arbitration Interframe Space (before 3520 * performing random backoff timing prior to Tx). Device default 1. 3521 * @fifos_mask: FIFOs used by this MAC for this AC 3522 * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0. 3523 * 3524 * One instance of this config struct for each of 4 EDCA access categories 3525 * in struct iwm_qosparam_cmd. 3526 * 3527 * Device will automatically increase contention window by (2*CW) + 1 for each 3528 * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW 3529 * value, to cap the CW value. 3530 */ 3531 struct iwm_ac_qos { 3532 uint16_t cw_min; 3533 uint16_t cw_max; 3534 uint8_t aifsn; 3535 uint8_t fifos_mask; 3536 uint16_t edca_txop; 3537 } __packed; /* IWM_AC_QOS_API_S_VER_2 */ 3538 3539 /** 3540 * struct iwm_mac_ctx_cmd - command structure to configure MAC contexts 3541 * ( IWM_MAC_CONTEXT_CMD = 0x28 ) 3542 * @id_and_color: ID and color of the MAC 3543 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 3544 * @mac_type: one of IWM_FW_MAC_TYPE_* 3545 * @tsd_id: TSF HW timer, one of IWM_TSF_ID_* 3546 * @node_addr: MAC address 3547 * @bssid_addr: BSSID 3548 * @cck_rates: basic rates available for CCK 3549 * @ofdm_rates: basic rates available for OFDM 3550 * @protection_flags: combination of IWM_MAC_PROT_FLG_FLAG_* 3551 * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise 3552 * @short_slot: 0x10 for enabling short slots, 0 otherwise 3553 * @filter_flags: combination of IWM_MAC_FILTER_* 3554 * @qos_flags: from IWM_MAC_QOS_FLG_* 3555 * @ac: one iwm_mac_qos configuration for each AC 3556 * @mac_specific: one of struct iwm_mac_data_*, according to mac_type 3557 */ 3558 struct iwm_mac_ctx_cmd { 3559 /* COMMON_INDEX_HDR_API_S_VER_1 */ 3560 uint32_t id_and_color; 3561 uint32_t action; 3562 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S_VER_1 */ 3563 uint32_t mac_type; 3564 uint32_t tsf_id; 3565 uint8_t node_addr[6]; 3566 uint16_t reserved_for_node_addr; 3567 uint8_t bssid_addr[6]; 3568 uint16_t reserved_for_bssid_addr; 3569 uint32_t cck_rates; 3570 uint32_t ofdm_rates; 3571 uint32_t protection_flags; 3572 uint32_t cck_short_preamble; 3573 uint32_t short_slot; 3574 uint32_t filter_flags; 3575 /* IWM_MAC_QOS_PARAM_API_S_VER_1 */ 3576 uint32_t qos_flags; 3577 struct iwm_ac_qos ac[IWM_AC_NUM+1]; 3578 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S */ 3579 union { 3580 struct iwm_mac_data_ap ap; 3581 struct iwm_mac_data_go go; 3582 struct iwm_mac_data_sta sta; 3583 struct iwm_mac_data_p2p_sta p2p_sta; 3584 struct iwm_mac_data_p2p_dev p2p_dev; 3585 struct iwm_mac_data_pibss pibss; 3586 struct iwm_mac_data_ibss ibss; 3587 }; 3588 } __packed; /* IWM_MAC_CONTEXT_CMD_API_S_VER_1 */ 3589 3590 static inline uint32_t iwm_mvm_reciprocal(uint32_t v) 3591 { 3592 if (!v) 3593 return 0; 3594 return 0xFFFFFFFF / v; 3595 } 3596 3597 #define IWM_NONQOS_SEQ_GET 0x1 3598 #define IWM_NONQOS_SEQ_SET 0x2 3599 struct iwm_nonqos_seq_query_cmd { 3600 uint32_t get_set_flag; 3601 uint32_t mac_id_n_color; 3602 uint16_t value; 3603 uint16_t reserved; 3604 } __packed; /* IWM_NON_QOS_TX_COUNTER_GET_SET_API_S_VER_1 */ 3605 3606 /* 3607 * END mvm/fw-api-mac.h 3608 */ 3609 3610 /* 3611 * BEGIN mvm/fw-api-power.h 3612 */ 3613 3614 /* Power Management Commands, Responses, Notifications */ 3615 3616 /* Radio LP RX Energy Threshold measured in dBm */ 3617 #define IWM_POWER_LPRX_RSSI_THRESHOLD 75 3618 #define IWM_POWER_LPRX_RSSI_THRESHOLD_MAX 94 3619 #define IWM_POWER_LPRX_RSSI_THRESHOLD_MIN 30 3620 3621 /** 3622 * enum iwm_scan_flags - masks for power table command flags 3623 * @IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 3624 * receiver and transmitter. '0' - does not allow. 3625 * @IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management, 3626 * '1' Driver enables PM (use rest of parameters) 3627 * @IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM, 3628 * '1' PM could sleep over DTIM till listen Interval. 3629 * @IWM_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all 3630 * access categories are both delivery and trigger enabled. 3631 * @IWM_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and 3632 * PBW Snoozing enabled 3633 * @IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask 3634 * @IWM_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable. 3635 * @IWM_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving 3636 * detection enablement 3637 */ 3638 enum iwm_power_flags { 3639 IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0), 3640 IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK = (1 << 1), 3641 IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK = (1 << 2), 3642 IWM_POWER_FLAGS_SNOOZE_ENA_MSK = (1 << 5), 3643 IWM_POWER_FLAGS_BT_SCO_ENA = (1 << 8), 3644 IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK = (1 << 9), 3645 IWM_POWER_FLAGS_LPRX_ENA_MSK = (1 << 11), 3646 IWM_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK = (1 << 12), 3647 }; 3648 3649 #define IWM_POWER_VEC_SIZE 5 3650 3651 /** 3652 * struct iwm_powertable_cmd - legacy power command. Beside old API support this 3653 * is used also with a new power API for device wide power settings. 3654 * IWM_POWER_TABLE_CMD = 0x77 (command, has simple generic response) 3655 * 3656 * @flags: Power table command flags from IWM_POWER_FLAGS_* 3657 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 3658 * Minimum allowed:- 3 * DTIM. Keep alive period must be 3659 * set regardless of power scheme or current power state. 3660 * FW use this value also when PM is disabled. 3661 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 3662 * PSM transition - legacy PM 3663 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 3664 * PSM transition - legacy PM 3665 * @sleep_interval: not in use 3666 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 3667 * is set. For example, if it is required to skip over 3668 * one DTIM, this value need to be set to 2 (DTIM periods). 3669 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 3670 * Default: 80dbm 3671 */ 3672 struct iwm_powertable_cmd { 3673 /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 3674 uint16_t flags; 3675 uint8_t keep_alive_seconds; 3676 uint8_t debug_flags; 3677 uint32_t rx_data_timeout; 3678 uint32_t tx_data_timeout; 3679 uint32_t sleep_interval[IWM_POWER_VEC_SIZE]; 3680 uint32_t skip_dtim_periods; 3681 uint32_t lprx_rssi_threshold; 3682 } __packed; 3683 3684 /** 3685 * enum iwm_device_power_flags - masks for device power command flags 3686 * @DEVIC_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 3687 * receiver and transmitter. '0' - does not allow. This flag should be 3688 * always set to '1' unless one need to disable actual power down for debug 3689 * purposes. 3690 * @IWM_DEVICE_POWER_FLAGS_CAM_MSK: '1' CAM (Continuous Active Mode) is set, meaning 3691 * that power management is disabled. '0' Power management is enabled, one 3692 * of power schemes is applied. 3693 */ 3694 enum iwm_device_power_flags { 3695 IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0), 3696 IWM_DEVICE_POWER_FLAGS_CAM_MSK = (1 << 13), 3697 }; 3698 3699 /** 3700 * struct iwm_device_power_cmd - device wide power command. 3701 * IWM_DEVICE_POWER_CMD = 0x77 (command, has simple generic response) 3702 * 3703 * @flags: Power table command flags from IWM_DEVICE_POWER_FLAGS_* 3704 */ 3705 struct iwm_device_power_cmd { 3706 /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 3707 uint16_t flags; 3708 uint16_t reserved; 3709 } __packed; 3710 3711 /** 3712 * struct iwm_mac_power_cmd - New power command containing uAPSD support 3713 * IWM_MAC_PM_POWER_TABLE = 0xA9 (command, has simple generic response) 3714 * @id_and_color: MAC contex identifier 3715 * @flags: Power table command flags from POWER_FLAGS_* 3716 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 3717 * Minimum allowed:- 3 * DTIM. Keep alive period must be 3718 * set regardless of power scheme or current power state. 3719 * FW use this value also when PM is disabled. 3720 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 3721 * PSM transition - legacy PM 3722 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 3723 * PSM transition - legacy PM 3724 * @sleep_interval: not in use 3725 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 3726 * is set. For example, if it is required to skip over 3727 * one DTIM, this value need to be set to 2 (DTIM periods). 3728 * @rx_data_timeout_uapsd: Minimum time (usec) from last Rx packet for AM to 3729 * PSM transition - uAPSD 3730 * @tx_data_timeout_uapsd: Minimum time (usec) from last Tx packet for AM to 3731 * PSM transition - uAPSD 3732 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 3733 * Default: 80dbm 3734 * @num_skip_dtim: Number of DTIMs to skip if Skip over DTIM flag is set 3735 * @snooze_interval: Maximum time between attempts to retrieve buffered data 3736 * from the AP [msec] 3737 * @snooze_window: A window of time in which PBW snoozing insures that all 3738 * packets received. It is also the minimum time from last 3739 * received unicast RX packet, before client stops snoozing 3740 * for data. [msec] 3741 * @snooze_step: TBD 3742 * @qndp_tid: TID client shall use for uAPSD QNDP triggers 3743 * @uapsd_ac_flags: Set trigger-enabled and delivery-enabled indication for 3744 * each corresponding AC. 3745 * Use IEEE80211_WMM_IE_STA_QOSINFO_AC* for correct values. 3746 * @uapsd_max_sp: Use IEEE80211_WMM_IE_STA_QOSINFO_SP_* for correct 3747 * values. 3748 * @heavy_tx_thld_packets: TX threshold measured in number of packets 3749 * @heavy_rx_thld_packets: RX threshold measured in number of packets 3750 * @heavy_tx_thld_percentage: TX threshold measured in load's percentage 3751 * @heavy_rx_thld_percentage: RX threshold measured in load's percentage 3752 * @limited_ps_threshold: 3753 */ 3754 struct iwm_mac_power_cmd { 3755 /* CONTEXT_DESC_API_T_VER_1 */ 3756 uint32_t id_and_color; 3757 3758 /* CLIENT_PM_POWER_TABLE_S_VER_1 */ 3759 uint16_t flags; 3760 uint16_t keep_alive_seconds; 3761 uint32_t rx_data_timeout; 3762 uint32_t tx_data_timeout; 3763 uint32_t rx_data_timeout_uapsd; 3764 uint32_t tx_data_timeout_uapsd; 3765 uint8_t lprx_rssi_threshold; 3766 uint8_t skip_dtim_periods; 3767 uint16_t snooze_interval; 3768 uint16_t snooze_window; 3769 uint8_t snooze_step; 3770 uint8_t qndp_tid; 3771 uint8_t uapsd_ac_flags; 3772 uint8_t uapsd_max_sp; 3773 uint8_t heavy_tx_thld_packets; 3774 uint8_t heavy_rx_thld_packets; 3775 uint8_t heavy_tx_thld_percentage; 3776 uint8_t heavy_rx_thld_percentage; 3777 uint8_t limited_ps_threshold; 3778 uint8_t reserved; 3779 } __packed; 3780 3781 /* 3782 * struct iwm_uapsd_misbehaving_ap_notif - FW sends this notification when 3783 * associated AP is identified as improperly implementing uAPSD protocol. 3784 * IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78 3785 * @sta_id: index of station in uCode's station table - associated AP ID in 3786 * this context. 3787 */ 3788 struct iwm_uapsd_misbehaving_ap_notif { 3789 uint32_t sta_id; 3790 uint8_t mac_id; 3791 uint8_t reserved[3]; 3792 } __packed; 3793 3794 /** 3795 * struct iwm_beacon_filter_cmd 3796 * IWM_REPLY_BEACON_FILTERING_CMD = 0xd2 (command) 3797 * @id_and_color: MAC contex identifier 3798 * @bf_energy_delta: Used for RSSI filtering, if in 'normal' state. Send beacon 3799 * to driver if delta in Energy values calculated for this and last 3800 * passed beacon is greater than this threshold. Zero value means that 3801 * the Energy change is ignored for beacon filtering, and beacon will 3802 * not be forced to be sent to driver regardless of this delta. Typical 3803 * energy delta 5dB. 3804 * @bf_roaming_energy_delta: Used for RSSI filtering, if in 'roaming' state. 3805 * Send beacon to driver if delta in Energy values calculated for this 3806 * and last passed beacon is greater than this threshold. Zero value 3807 * means that the Energy change is ignored for beacon filtering while in 3808 * Roaming state, typical energy delta 1dB. 3809 * @bf_roaming_state: Used for RSSI filtering. If absolute Energy values 3810 * calculated for current beacon is less than the threshold, use 3811 * Roaming Energy Delta Threshold, otherwise use normal Energy Delta 3812 * Threshold. Typical energy threshold is -72dBm. 3813 * @bf_temp_threshold: This threshold determines the type of temperature 3814 * filtering (Slow or Fast) that is selected (Units are in Celsuis): 3815 * If the current temperature is above this threshold - Fast filter 3816 * will be used, If the current temperature is below this threshold - 3817 * Slow filter will be used. 3818 * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values 3819 * calculated for this and the last passed beacon is greater than this 3820 * threshold. Zero value means that the temperature change is ignored for 3821 * beacon filtering; beacons will not be forced to be sent to driver 3822 * regardless of whether its temperature has been changed. 3823 * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values 3824 * calculated for this and the last passed beacon is greater than this 3825 * threshold. Zero value means that the temperature change is ignored for 3826 * beacon filtering; beacons will not be forced to be sent to driver 3827 * regardless of whether its temperature has been changed. 3828 * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled. 3829 * @bf_filter_escape_timer: Send beacons to to driver if no beacons were passed 3830 * for a specific period of time. Units: Beacons. 3831 * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed 3832 * for a longer period of time then this escape-timeout. Units: Beacons. 3833 * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled. 3834 */ 3835 struct iwm_beacon_filter_cmd { 3836 uint32_t bf_energy_delta; 3837 uint32_t bf_roaming_energy_delta; 3838 uint32_t bf_roaming_state; 3839 uint32_t bf_temp_threshold; 3840 uint32_t bf_temp_fast_filter; 3841 uint32_t bf_temp_slow_filter; 3842 uint32_t bf_enable_beacon_filter; 3843 uint32_t bf_debug_flag; 3844 uint32_t bf_escape_timer; 3845 uint32_t ba_escape_timer; 3846 uint32_t ba_enable_beacon_abort; 3847 } __packed; 3848 3849 /* Beacon filtering and beacon abort */ 3850 #define IWM_BF_ENERGY_DELTA_DEFAULT 5 3851 #define IWM_BF_ENERGY_DELTA_MAX 255 3852 #define IWM_BF_ENERGY_DELTA_MIN 0 3853 3854 #define IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT 1 3855 #define IWM_BF_ROAMING_ENERGY_DELTA_MAX 255 3856 #define IWM_BF_ROAMING_ENERGY_DELTA_MIN 0 3857 3858 #define IWM_BF_ROAMING_STATE_DEFAULT 72 3859 #define IWM_BF_ROAMING_STATE_MAX 255 3860 #define IWM_BF_ROAMING_STATE_MIN 0 3861 3862 #define IWM_BF_TEMP_THRESHOLD_DEFAULT 112 3863 #define IWM_BF_TEMP_THRESHOLD_MAX 255 3864 #define IWM_BF_TEMP_THRESHOLD_MIN 0 3865 3866 #define IWM_BF_TEMP_FAST_FILTER_DEFAULT 1 3867 #define IWM_BF_TEMP_FAST_FILTER_MAX 255 3868 #define IWM_BF_TEMP_FAST_FILTER_MIN 0 3869 3870 #define IWM_BF_TEMP_SLOW_FILTER_DEFAULT 5 3871 #define IWM_BF_TEMP_SLOW_FILTER_MAX 255 3872 #define IWM_BF_TEMP_SLOW_FILTER_MIN 0 3873 3874 #define IWM_BF_ENABLE_BEACON_FILTER_DEFAULT 1 3875 3876 #define IWM_BF_DEBUG_FLAG_DEFAULT 0 3877 3878 #define IWM_BF_ESCAPE_TIMER_DEFAULT 50 3879 #define IWM_BF_ESCAPE_TIMER_MAX 1024 3880 #define IWM_BF_ESCAPE_TIMER_MIN 0 3881 3882 #define IWM_BA_ESCAPE_TIMER_DEFAULT 6 3883 #define IWM_BA_ESCAPE_TIMER_D3 9 3884 #define IWM_BA_ESCAPE_TIMER_MAX 1024 3885 #define IWM_BA_ESCAPE_TIMER_MIN 0 3886 3887 #define IWM_BA_ENABLE_BEACON_ABORT_DEFAULT 1 3888 3889 #define IWM_BF_CMD_CONFIG_DEFAULTS \ 3890 .bf_energy_delta = htole32(IWM_BF_ENERGY_DELTA_DEFAULT), \ 3891 .bf_roaming_energy_delta = \ 3892 htole32(IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT), \ 3893 .bf_roaming_state = htole32(IWM_BF_ROAMING_STATE_DEFAULT), \ 3894 .bf_temp_threshold = htole32(IWM_BF_TEMP_THRESHOLD_DEFAULT), \ 3895 .bf_temp_fast_filter = htole32(IWM_BF_TEMP_FAST_FILTER_DEFAULT), \ 3896 .bf_temp_slow_filter = htole32(IWM_BF_TEMP_SLOW_FILTER_DEFAULT), \ 3897 .bf_debug_flag = htole32(IWM_BF_DEBUG_FLAG_DEFAULT), \ 3898 .bf_escape_timer = htole32(IWM_BF_ESCAPE_TIMER_DEFAULT), \ 3899 .ba_escape_timer = htole32(IWM_BA_ESCAPE_TIMER_DEFAULT) 3900 3901 /* 3902 * END mvm/fw-api-power.h 3903 */ 3904 3905 /* 3906 * BEGIN mvm/fw-api-rs.h 3907 */ 3908 3909 /* 3910 * These serve as indexes into 3911 * struct iwm_rate_info fw_rate_idx_to_plcp[IWM_RATE_COUNT]; 3912 * TODO: avoid overlap between legacy and HT rates 3913 */ 3914 enum { 3915 IWM_RATE_1M_INDEX = 0, 3916 IWM_FIRST_CCK_RATE = IWM_RATE_1M_INDEX, 3917 IWM_RATE_2M_INDEX, 3918 IWM_RATE_5M_INDEX, 3919 IWM_RATE_11M_INDEX, 3920 IWM_LAST_CCK_RATE = IWM_RATE_11M_INDEX, 3921 IWM_RATE_6M_INDEX, 3922 IWM_FIRST_OFDM_RATE = IWM_RATE_6M_INDEX, 3923 IWM_RATE_MCS_0_INDEX = IWM_RATE_6M_INDEX, 3924 IWM_FIRST_HT_RATE = IWM_RATE_MCS_0_INDEX, 3925 IWM_FIRST_VHT_RATE = IWM_RATE_MCS_0_INDEX, 3926 IWM_RATE_9M_INDEX, 3927 IWM_RATE_12M_INDEX, 3928 IWM_RATE_MCS_1_INDEX = IWM_RATE_12M_INDEX, 3929 IWM_RATE_18M_INDEX, 3930 IWM_RATE_MCS_2_INDEX = IWM_RATE_18M_INDEX, 3931 IWM_RATE_24M_INDEX, 3932 IWM_RATE_MCS_3_INDEX = IWM_RATE_24M_INDEX, 3933 IWM_RATE_36M_INDEX, 3934 IWM_RATE_MCS_4_INDEX = IWM_RATE_36M_INDEX, 3935 IWM_RATE_48M_INDEX, 3936 IWM_RATE_MCS_5_INDEX = IWM_RATE_48M_INDEX, 3937 IWM_RATE_54M_INDEX, 3938 IWM_RATE_MCS_6_INDEX = IWM_RATE_54M_INDEX, 3939 IWM_LAST_NON_HT_RATE = IWM_RATE_54M_INDEX, 3940 IWM_RATE_60M_INDEX, 3941 IWM_RATE_MCS_7_INDEX = IWM_RATE_60M_INDEX, 3942 IWM_LAST_HT_RATE = IWM_RATE_MCS_7_INDEX, 3943 IWM_RATE_MCS_8_INDEX, 3944 IWM_RATE_MCS_9_INDEX, 3945 IWM_LAST_VHT_RATE = IWM_RATE_MCS_9_INDEX, 3946 IWM_RATE_COUNT_LEGACY = IWM_LAST_NON_HT_RATE + 1, 3947 IWM_RATE_COUNT = IWM_LAST_VHT_RATE + 1, 3948 }; 3949 3950 #define IWM_RATE_BIT_MSK(r) (1 << (IWM_RATE_##r##M_INDEX)) 3951 3952 /* fw API values for legacy bit rates, both OFDM and CCK */ 3953 enum { 3954 IWM_RATE_6M_PLCP = 13, 3955 IWM_RATE_9M_PLCP = 15, 3956 IWM_RATE_12M_PLCP = 5, 3957 IWM_RATE_18M_PLCP = 7, 3958 IWM_RATE_24M_PLCP = 9, 3959 IWM_RATE_36M_PLCP = 11, 3960 IWM_RATE_48M_PLCP = 1, 3961 IWM_RATE_54M_PLCP = 3, 3962 IWM_RATE_1M_PLCP = 10, 3963 IWM_RATE_2M_PLCP = 20, 3964 IWM_RATE_5M_PLCP = 55, 3965 IWM_RATE_11M_PLCP = 110, 3966 IWM_RATE_INVM_PLCP = -1, 3967 }; 3968 3969 /* 3970 * rate_n_flags bit fields 3971 * 3972 * The 32-bit value has different layouts in the low 8 bites depending on the 3973 * format. There are three formats, HT, VHT and legacy (11abg, with subformats 3974 * for CCK and OFDM). 3975 * 3976 * High-throughput (HT) rate format 3977 * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM) 3978 * Very High-throughput (VHT) rate format 3979 * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM) 3980 * Legacy OFDM rate format for bits 7:0 3981 * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM) 3982 * Legacy CCK rate format for bits 7:0: 3983 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK) 3984 */ 3985 3986 /* Bit 8: (1) HT format, (0) legacy or VHT format */ 3987 #define IWM_RATE_MCS_HT_POS 8 3988 #define IWM_RATE_MCS_HT_MSK (1 << IWM_RATE_MCS_HT_POS) 3989 3990 /* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */ 3991 #define IWM_RATE_MCS_CCK_POS 9 3992 #define IWM_RATE_MCS_CCK_MSK (1 << IWM_RATE_MCS_CCK_POS) 3993 3994 /* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */ 3995 #define IWM_RATE_MCS_VHT_POS 26 3996 #define IWM_RATE_MCS_VHT_MSK (1 << IWM_RATE_MCS_VHT_POS) 3997 3998 3999 /* 4000 * High-throughput (HT) rate format for bits 7:0 4001 * 4002 * 2-0: MCS rate base 4003 * 0) 6 Mbps 4004 * 1) 12 Mbps 4005 * 2) 18 Mbps 4006 * 3) 24 Mbps 4007 * 4) 36 Mbps 4008 * 5) 48 Mbps 4009 * 6) 54 Mbps 4010 * 7) 60 Mbps 4011 * 4-3: 0) Single stream (SISO) 4012 * 1) Dual stream (MIMO) 4013 * 2) Triple stream (MIMO) 4014 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data 4015 * (bits 7-6 are zero) 4016 * 4017 * Together the low 5 bits work out to the MCS index because we don't 4018 * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two 4019 * streams and 16-23 have three streams. We could also support MCS 32 4020 * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.) 4021 */ 4022 #define IWM_RATE_HT_MCS_RATE_CODE_MSK 0x7 4023 #define IWM_RATE_HT_MCS_NSS_POS 3 4024 #define IWM_RATE_HT_MCS_NSS_MSK (3 << IWM_RATE_HT_MCS_NSS_POS) 4025 4026 /* Bit 10: (1) Use Green Field preamble */ 4027 #define IWM_RATE_HT_MCS_GF_POS 10 4028 #define IWM_RATE_HT_MCS_GF_MSK (1 << IWM_RATE_HT_MCS_GF_POS) 4029 4030 #define IWM_RATE_HT_MCS_INDEX_MSK 0x3f 4031 4032 /* 4033 * Very High-throughput (VHT) rate format for bits 7:0 4034 * 4035 * 3-0: VHT MCS (0-9) 4036 * 5-4: number of streams - 1: 4037 * 0) Single stream (SISO) 4038 * 1) Dual stream (MIMO) 4039 * 2) Triple stream (MIMO) 4040 */ 4041 4042 /* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */ 4043 #define IWM_RATE_VHT_MCS_RATE_CODE_MSK 0xf 4044 #define IWM_RATE_VHT_MCS_NSS_POS 4 4045 #define IWM_RATE_VHT_MCS_NSS_MSK (3 << IWM_RATE_VHT_MCS_NSS_POS) 4046 4047 /* 4048 * Legacy OFDM rate format for bits 7:0 4049 * 4050 * 3-0: 0xD) 6 Mbps 4051 * 0xF) 9 Mbps 4052 * 0x5) 12 Mbps 4053 * 0x7) 18 Mbps 4054 * 0x9) 24 Mbps 4055 * 0xB) 36 Mbps 4056 * 0x1) 48 Mbps 4057 * 0x3) 54 Mbps 4058 * (bits 7-4 are 0) 4059 * 4060 * Legacy CCK rate format for bits 7:0: 4061 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK): 4062 * 4063 * 6-0: 10) 1 Mbps 4064 * 20) 2 Mbps 4065 * 55) 5.5 Mbps 4066 * 110) 11 Mbps 4067 * (bit 7 is 0) 4068 */ 4069 #define IWM_RATE_LEGACY_RATE_MSK 0xff 4070 4071 4072 /* 4073 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz 4074 * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT 4075 */ 4076 #define IWM_RATE_MCS_CHAN_WIDTH_POS 11 4077 #define IWM_RATE_MCS_CHAN_WIDTH_MSK (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4078 #define IWM_RATE_MCS_CHAN_WIDTH_20 (0 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4079 #define IWM_RATE_MCS_CHAN_WIDTH_40 (1 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4080 #define IWM_RATE_MCS_CHAN_WIDTH_80 (2 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4081 #define IWM_RATE_MCS_CHAN_WIDTH_160 (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4082 4083 /* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */ 4084 #define IWM_RATE_MCS_SGI_POS 13 4085 #define IWM_RATE_MCS_SGI_MSK (1 << IWM_RATE_MCS_SGI_POS) 4086 4087 /* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */ 4088 #define IWM_RATE_MCS_ANT_POS 14 4089 #define IWM_RATE_MCS_ANT_A_MSK (1 << IWM_RATE_MCS_ANT_POS) 4090 #define IWM_RATE_MCS_ANT_B_MSK (2 << IWM_RATE_MCS_ANT_POS) 4091 #define IWM_RATE_MCS_ANT_C_MSK (4 << IWM_RATE_MCS_ANT_POS) 4092 #define IWM_RATE_MCS_ANT_AB_MSK (IWM_RATE_MCS_ANT_A_MSK | \ 4093 IWM_RATE_MCS_ANT_B_MSK) 4094 #define IWM_RATE_MCS_ANT_ABC_MSK (IWM_RATE_MCS_ANT_AB_MSK | \ 4095 IWM_RATE_MCS_ANT_C_MSK) 4096 #define IWM_RATE_MCS_ANT_MSK IWM_RATE_MCS_ANT_ABC_MSK 4097 #define IWM_RATE_MCS_ANT_NUM 3 4098 4099 /* Bit 17-18: (0) SS, (1) SS*2 */ 4100 #define IWM_RATE_MCS_STBC_POS 17 4101 #define IWM_RATE_MCS_STBC_MSK (1 << IWM_RATE_MCS_STBC_POS) 4102 4103 /* Bit 19: (0) Beamforming is off, (1) Beamforming is on */ 4104 #define IWM_RATE_MCS_BF_POS 19 4105 #define IWM_RATE_MCS_BF_MSK (1 << IWM_RATE_MCS_BF_POS) 4106 4107 /* Bit 20: (0) ZLF is off, (1) ZLF is on */ 4108 #define IWM_RATE_MCS_ZLF_POS 20 4109 #define IWM_RATE_MCS_ZLF_MSK (1 << IWM_RATE_MCS_ZLF_POS) 4110 4111 /* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */ 4112 #define IWM_RATE_MCS_DUP_POS 24 4113 #define IWM_RATE_MCS_DUP_MSK (3 << IWM_RATE_MCS_DUP_POS) 4114 4115 /* Bit 27: (1) LDPC enabled, (0) LDPC disabled */ 4116 #define IWM_RATE_MCS_LDPC_POS 27 4117 #define IWM_RATE_MCS_LDPC_MSK (1 << IWM_RATE_MCS_LDPC_POS) 4118 4119 4120 /* Link Quality definitions */ 4121 4122 /* # entries in rate scale table to support Tx retries */ 4123 #define IWM_LQ_MAX_RETRY_NUM 16 4124 4125 /* Link quality command flags bit fields */ 4126 4127 /* Bit 0: (0) Don't use RTS (1) Use RTS */ 4128 #define IWM_LQ_FLAG_USE_RTS_POS 0 4129 #define IWM_LQ_FLAG_USE_RTS_MSK (1 << IWM_LQ_FLAG_USE_RTS_POS) 4130 4131 /* Bit 1-3: LQ command color. Used to match responses to LQ commands */ 4132 #define IWM_LQ_FLAG_COLOR_POS 1 4133 #define IWM_LQ_FLAG_COLOR_MSK (7 << IWM_LQ_FLAG_COLOR_POS) 4134 4135 /* Bit 4-5: Tx RTS BW Signalling 4136 * (0) No RTS BW signalling 4137 * (1) Static BW signalling 4138 * (2) Dynamic BW signalling 4139 */ 4140 #define IWM_LQ_FLAG_RTS_BW_SIG_POS 4 4141 #define IWM_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4142 #define IWM_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4143 #define IWM_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4144 4145 /* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection 4146 * Dyanmic BW selection allows Tx with narrower BW then requested in rates 4147 */ 4148 #define IWM_LQ_FLAG_DYNAMIC_BW_POS 6 4149 #define IWM_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWM_LQ_FLAG_DYNAMIC_BW_POS) 4150 4151 /** 4152 * struct iwm_lq_cmd - link quality command 4153 * @sta_id: station to update 4154 * @control: not used 4155 * @flags: combination of IWM_LQ_FLAG_* 4156 * @mimo_delim: the first SISO index in rs_table, which separates MIMO 4157 * and SISO rates 4158 * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD). 4159 * Should be ANT_[ABC] 4160 * @dual_stream_ant_msk: best antennas for MIMO, combination of ANT_[ABC] 4161 * @initial_rate_index: first index from rs_table per AC category 4162 * @agg_time_limit: aggregation max time threshold in usec/100, meaning 4163 * value of 100 is one usec. Range is 100 to 8000 4164 * @agg_disable_start_th: try-count threshold for starting aggregation. 4165 * If a frame has higher try-count, it should not be selected for 4166 * starting an aggregation sequence. 4167 * @agg_frame_cnt_limit: max frame count in an aggregation. 4168 * 0: no limit 4169 * 1: no aggregation (one frame per aggregation) 4170 * 2 - 0x3f: maximal number of frames (up to 3f == 63) 4171 * @rs_table: array of rates for each TX try, each is rate_n_flags, 4172 * meaning it is a combination of IWM_RATE_MCS_* and IWM_RATE_*_PLCP 4173 * @bf_params: beam forming params, currently not used 4174 */ 4175 struct iwm_lq_cmd { 4176 uint8_t sta_id; 4177 uint8_t reserved1; 4178 uint16_t control; 4179 /* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */ 4180 uint8_t flags; 4181 uint8_t mimo_delim; 4182 uint8_t single_stream_ant_msk; 4183 uint8_t dual_stream_ant_msk; 4184 uint8_t initial_rate_index[IWM_AC_NUM]; 4185 /* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */ 4186 uint16_t agg_time_limit; 4187 uint8_t agg_disable_start_th; 4188 uint8_t agg_frame_cnt_limit; 4189 uint32_t reserved2; 4190 uint32_t rs_table[IWM_LQ_MAX_RETRY_NUM]; 4191 uint32_t bf_params; 4192 }; /* LINK_QUALITY_CMD_API_S_VER_1 */ 4193 4194 /* 4195 * END mvm/fw-api-rs.h 4196 */ 4197 4198 /* 4199 * BEGIN mvm/fw-api-tx.h 4200 */ 4201 4202 /** 4203 * enum iwm_tx_flags - bitmasks for tx_flags in TX command 4204 * @IWM_TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame 4205 * @IWM_TX_CMD_FLG_ACK: expect ACK from receiving station 4206 * @IWM_TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command. 4207 * Otherwise, use rate_n_flags from the TX command 4208 * @IWM_TX_CMD_FLG_BA: this frame is a block ack 4209 * @IWM_TX_CMD_FLG_BAR: this frame is a BA request, immediate BAR is expected 4210 * Must set IWM_TX_CMD_FLG_ACK with this flag. 4211 * @IWM_TX_CMD_FLG_TXOP_PROT: protect frame with full TXOP protection 4212 * @IWM_TX_CMD_FLG_VHT_NDPA: mark frame is NDPA for VHT beamformer sequence 4213 * @IWM_TX_CMD_FLG_HT_NDPA: mark frame is NDPA for HT beamformer sequence 4214 * @IWM_TX_CMD_FLG_CSI_FDBK2HOST: mark to send feedback to host (only if good CRC) 4215 * @IWM_TX_CMD_FLG_BT_DIS: disable BT priority for this frame 4216 * @IWM_TX_CMD_FLG_SEQ_CTL: set if FW should override the sequence control. 4217 * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command 4218 * @IWM_TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU 4219 * @IWM_TX_CMD_FLG_NEXT_FRAME: this frame includes information of the next frame 4220 * @IWM_TX_CMD_FLG_TSF: FW should calculate and insert TSF in the frame 4221 * Should be set for beacons and probe responses 4222 * @IWM_TX_CMD_FLG_CALIB: activate PA TX power calibrations 4223 * @IWM_TX_CMD_FLG_KEEP_SEQ_CTL: if seq_ctl is set, don't increase inner seq count 4224 * @IWM_TX_CMD_FLG_AGG_START: allow this frame to start aggregation 4225 * @IWM_TX_CMD_FLG_MH_PAD: driver inserted 2 byte padding after MAC header. 4226 * Should be set for 26/30 length MAC headers 4227 * @IWM_TX_CMD_FLG_RESP_TO_DRV: zero this if the response should go only to FW 4228 * @IWM_TX_CMD_FLG_CCMP_AGG: this frame uses CCMP for aggregation acceleration 4229 * @IWM_TX_CMD_FLG_TKIP_MIC_DONE: FW already performed TKIP MIC calculation 4230 * @IWM_TX_CMD_FLG_DUR: disable duration overwriting used in PS-Poll Assoc-id 4231 * @IWM_TX_CMD_FLG_FW_DROP: FW should mark frame to be dropped 4232 * @IWM_TX_CMD_FLG_EXEC_PAPD: execute PAPD 4233 * @IWM_TX_CMD_FLG_PAPD_TYPE: 0 for reference power, 1 for nominal power 4234 * @IWM_TX_CMD_FLG_HCCA_CHUNK: mark start of TSPEC chunk 4235 */ 4236 enum iwm_tx_flags { 4237 IWM_TX_CMD_FLG_PROT_REQUIRE = (1 << 0), 4238 IWM_TX_CMD_FLG_ACK = (1 << 3), 4239 IWM_TX_CMD_FLG_STA_RATE = (1 << 4), 4240 IWM_TX_CMD_FLG_BA = (1 << 5), 4241 IWM_TX_CMD_FLG_BAR = (1 << 6), 4242 IWM_TX_CMD_FLG_TXOP_PROT = (1 << 7), 4243 IWM_TX_CMD_FLG_VHT_NDPA = (1 << 8), 4244 IWM_TX_CMD_FLG_HT_NDPA = (1 << 9), 4245 IWM_TX_CMD_FLG_CSI_FDBK2HOST = (1 << 10), 4246 IWM_TX_CMD_FLG_BT_DIS = (1 << 12), 4247 IWM_TX_CMD_FLG_SEQ_CTL = (1 << 13), 4248 IWM_TX_CMD_FLG_MORE_FRAG = (1 << 14), 4249 IWM_TX_CMD_FLG_NEXT_FRAME = (1 << 15), 4250 IWM_TX_CMD_FLG_TSF = (1 << 16), 4251 IWM_TX_CMD_FLG_CALIB = (1 << 17), 4252 IWM_TX_CMD_FLG_KEEP_SEQ_CTL = (1 << 18), 4253 IWM_TX_CMD_FLG_AGG_START = (1 << 19), 4254 IWM_TX_CMD_FLG_MH_PAD = (1 << 20), 4255 IWM_TX_CMD_FLG_RESP_TO_DRV = (1 << 21), 4256 IWM_TX_CMD_FLG_CCMP_AGG = (1 << 22), 4257 IWM_TX_CMD_FLG_TKIP_MIC_DONE = (1 << 23), 4258 IWM_TX_CMD_FLG_DUR = (1 << 25), 4259 IWM_TX_CMD_FLG_FW_DROP = (1 << 26), 4260 IWM_TX_CMD_FLG_EXEC_PAPD = (1 << 27), 4261 IWM_TX_CMD_FLG_PAPD_TYPE = (1 << 28), 4262 IWM_TX_CMD_FLG_HCCA_CHUNK = (1 << 31) 4263 }; /* IWM_TX_FLAGS_BITS_API_S_VER_1 */ 4264 4265 /** 4266 * enum iwm_tx_pm_timeouts - pm timeout values in TX command 4267 * @IWM_PM_FRAME_NONE: no need to suspend sleep mode 4268 * @IWM_PM_FRAME_MGMT: fw suspend sleep mode for 100TU 4269 * @IWM_PM_FRAME_ASSOC: fw suspend sleep mode for 10sec 4270 */ 4271 enum iwm_tx_pm_timeouts { 4272 IWM_PM_FRAME_NONE = 0, 4273 IWM_PM_FRAME_MGMT = 2, 4274 IWM_PM_FRAME_ASSOC = 3, 4275 }; 4276 4277 /* 4278 * TX command security control 4279 */ 4280 #define IWM_TX_CMD_SEC_WEP 0x01 4281 #define IWM_TX_CMD_SEC_CCM 0x02 4282 #define IWM_TX_CMD_SEC_TKIP 0x03 4283 #define IWM_TX_CMD_SEC_EXT 0x04 4284 #define IWM_TX_CMD_SEC_MSK 0x07 4285 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_POS 6 4286 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0 4287 #define IWM_TX_CMD_SEC_KEY128 0x08 4288 4289 /* TODO: how does these values are OK with only 16 bit variable??? */ 4290 /* 4291 * TX command next frame info 4292 * 4293 * bits 0:2 - security control (IWM_TX_CMD_SEC_*) 4294 * bit 3 - immediate ACK required 4295 * bit 4 - rate is taken from STA table 4296 * bit 5 - frame belongs to BA stream 4297 * bit 6 - immediate BA response expected 4298 * bit 7 - unused 4299 * bits 8:15 - Station ID 4300 * bits 16:31 - rate 4301 */ 4302 #define IWM_TX_CMD_NEXT_FRAME_ACK_MSK (0x8) 4303 #define IWM_TX_CMD_NEXT_FRAME_STA_RATE_MSK (0x10) 4304 #define IWM_TX_CMD_NEXT_FRAME_BA_MSK (0x20) 4305 #define IWM_TX_CMD_NEXT_FRAME_IMM_BA_RSP_MSK (0x40) 4306 #define IWM_TX_CMD_NEXT_FRAME_FLAGS_MSK (0xf8) 4307 #define IWM_TX_CMD_NEXT_FRAME_STA_ID_MSK (0xff00) 4308 #define IWM_TX_CMD_NEXT_FRAME_STA_ID_POS (8) 4309 #define IWM_TX_CMD_NEXT_FRAME_RATE_MSK (0xffff0000) 4310 #define IWM_TX_CMD_NEXT_FRAME_RATE_POS (16) 4311 4312 /* 4313 * TX command Frame life time in us - to be written in pm_frame_timeout 4314 */ 4315 #define IWM_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF 4316 #define IWM_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/ 4317 #define IWM_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */ 4318 #define IWM_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0 4319 4320 /* 4321 * TID for non QoS frames - to be written in tid_tspec 4322 */ 4323 #define IWM_TID_NON_QOS IWM_MAX_TID_COUNT 4324 4325 /* 4326 * Limits on the retransmissions - to be written in {data,rts}_retry_limit 4327 */ 4328 #define IWM_DEFAULT_TX_RETRY 15 4329 #define IWM_MGMT_DFAULT_RETRY_LIMIT 3 4330 #define IWM_RTS_DFAULT_RETRY_LIMIT 60 4331 #define IWM_BAR_DFAULT_RETRY_LIMIT 60 4332 #define IWM_LOW_RETRY_LIMIT 7 4333 4334 /* TODO: complete documentation for try_cnt and btkill_cnt */ 4335 /** 4336 * struct iwm_tx_cmd - TX command struct to FW 4337 * ( IWM_TX_CMD = 0x1c ) 4338 * @len: in bytes of the payload, see below for details 4339 * @next_frame_len: same as len, but for next frame (0 if not applicable) 4340 * Used for fragmentation and bursting, but not in 11n aggregation. 4341 * @tx_flags: combination of IWM_TX_CMD_FLG_* 4342 * @rate_n_flags: rate for *all* Tx attempts, if IWM_TX_CMD_FLG_STA_RATE_MSK is 4343 * cleared. Combination of IWM_RATE_MCS_* 4344 * @sta_id: index of destination station in FW station table 4345 * @sec_ctl: security control, IWM_TX_CMD_SEC_* 4346 * @initial_rate_index: index into the rate table for initial TX attempt. 4347 * Applied if IWM_TX_CMD_FLG_STA_RATE_MSK is set, normally 0 for data frames. 4348 * @key: security key 4349 * @next_frame_flags: IWM_TX_CMD_SEC_* and IWM_TX_CMD_NEXT_FRAME_* 4350 * @life_time: frame life time (usecs??) 4351 * @dram_lsb_ptr: Physical address of scratch area in the command (try_cnt + 4352 * btkill_cnd + reserved), first 32 bits. "0" disables usage. 4353 * @dram_msb_ptr: upper bits of the scratch physical address 4354 * @rts_retry_limit: max attempts for RTS 4355 * @data_retry_limit: max attempts to send the data packet 4356 * @tid_spec: TID/tspec 4357 * @pm_frame_timeout: PM TX frame timeout 4358 * @driver_txop: duration od EDCA TXOP, in 32-usec units. Set this if not 4359 * specified by HCCA protocol 4360 * 4361 * The byte count (both len and next_frame_len) includes MAC header 4362 * (24/26/30/32 bytes) 4363 * + 2 bytes pad if 26/30 header size 4364 * + 8 byte IV for CCM or TKIP (not used for WEP) 4365 * + Data payload 4366 * + 8-byte MIC (not used for CCM/WEP) 4367 * It does not include post-MAC padding, i.e., 4368 * MIC (CCM) 8 bytes, ICV (WEP/TKIP/CKIP) 4 bytes, CRC 4 bytes. 4369 * Range of len: 14-2342 bytes. 4370 * 4371 * After the struct fields the MAC header is placed, plus any padding, 4372 * and then the actial payload. 4373 */ 4374 struct iwm_tx_cmd { 4375 uint16_t len; 4376 uint16_t next_frame_len; 4377 uint32_t tx_flags; 4378 struct { 4379 uint8_t try_cnt; 4380 uint8_t btkill_cnt; 4381 uint16_t reserved; 4382 } scratch; /* DRAM_SCRATCH_API_U_VER_1 */ 4383 uint32_t rate_n_flags; 4384 uint8_t sta_id; 4385 uint8_t sec_ctl; 4386 uint8_t initial_rate_index; 4387 uint8_t reserved2; 4388 uint8_t key[16]; 4389 uint16_t next_frame_flags; 4390 uint16_t reserved3; 4391 uint32_t life_time; 4392 uint32_t dram_lsb_ptr; 4393 uint8_t dram_msb_ptr; 4394 uint8_t rts_retry_limit; 4395 uint8_t data_retry_limit; 4396 uint8_t tid_tspec; 4397 uint16_t pm_frame_timeout; 4398 uint16_t driver_txop; 4399 uint8_t payload[0]; 4400 struct ieee80211_frame hdr[0]; 4401 } __packed; /* IWM_TX_CMD_API_S_VER_3 */ 4402 4403 /* 4404 * TX response related data 4405 */ 4406 4407 /* 4408 * enum iwm_tx_status - status that is returned by the fw after attempts to Tx 4409 * @IWM_TX_STATUS_SUCCESS: 4410 * @IWM_TX_STATUS_DIRECT_DONE: 4411 * @IWM_TX_STATUS_POSTPONE_DELAY: 4412 * @IWM_TX_STATUS_POSTPONE_FEW_BYTES: 4413 * @IWM_TX_STATUS_POSTPONE_BT_PRIO: 4414 * @IWM_TX_STATUS_POSTPONE_QUIET_PERIOD: 4415 * @IWM_TX_STATUS_POSTPONE_CALC_TTAK: 4416 * @IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY: 4417 * @IWM_TX_STATUS_FAIL_SHORT_LIMIT: 4418 * @IWM_TX_STATUS_FAIL_LONG_LIMIT: 4419 * @IWM_TX_STATUS_FAIL_UNDERRUN: 4420 * @IWM_TX_STATUS_FAIL_DRAIN_FLOW: 4421 * @IWM_TX_STATUS_FAIL_RFKILL_FLUSH: 4422 * @IWM_TX_STATUS_FAIL_LIFE_EXPIRE: 4423 * @IWM_TX_STATUS_FAIL_DEST_PS: 4424 * @IWM_TX_STATUS_FAIL_HOST_ABORTED: 4425 * @IWM_TX_STATUS_FAIL_BT_RETRY: 4426 * @IWM_TX_STATUS_FAIL_STA_INVALID: 4427 * @IWM_TX_TATUS_FAIL_FRAG_DROPPED: 4428 * @IWM_TX_STATUS_FAIL_TID_DISABLE: 4429 * @IWM_TX_STATUS_FAIL_FIFO_FLUSHED: 4430 * @IWM_TX_STATUS_FAIL_SMALL_CF_POLL: 4431 * @IWM_TX_STATUS_FAIL_FW_DROP: 4432 * @IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH: mismatch between color of Tx cmd and 4433 * STA table 4434 * @IWM_TX_FRAME_STATUS_INTERNAL_ABORT: 4435 * @IWM_TX_MODE_MSK: 4436 * @IWM_TX_MODE_NO_BURST: 4437 * @IWM_TX_MODE_IN_BURST_SEQ: 4438 * @IWM_TX_MODE_FIRST_IN_BURST: 4439 * @IWM_TX_QUEUE_NUM_MSK: 4440 * 4441 * Valid only if frame_count =1 4442 * TODO: complete documentation 4443 */ 4444 enum iwm_tx_status { 4445 IWM_TX_STATUS_MSK = 0x000000ff, 4446 IWM_TX_STATUS_SUCCESS = 0x01, 4447 IWM_TX_STATUS_DIRECT_DONE = 0x02, 4448 /* postpone TX */ 4449 IWM_TX_STATUS_POSTPONE_DELAY = 0x40, 4450 IWM_TX_STATUS_POSTPONE_FEW_BYTES = 0x41, 4451 IWM_TX_STATUS_POSTPONE_BT_PRIO = 0x42, 4452 IWM_TX_STATUS_POSTPONE_QUIET_PERIOD = 0x43, 4453 IWM_TX_STATUS_POSTPONE_CALC_TTAK = 0x44, 4454 /* abort TX */ 4455 IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY = 0x81, 4456 IWM_TX_STATUS_FAIL_SHORT_LIMIT = 0x82, 4457 IWM_TX_STATUS_FAIL_LONG_LIMIT = 0x83, 4458 IWM_TX_STATUS_FAIL_UNDERRUN = 0x84, 4459 IWM_TX_STATUS_FAIL_DRAIN_FLOW = 0x85, 4460 IWM_TX_STATUS_FAIL_RFKILL_FLUSH = 0x86, 4461 IWM_TX_STATUS_FAIL_LIFE_EXPIRE = 0x87, 4462 IWM_TX_STATUS_FAIL_DEST_PS = 0x88, 4463 IWM_TX_STATUS_FAIL_HOST_ABORTED = 0x89, 4464 IWM_TX_STATUS_FAIL_BT_RETRY = 0x8a, 4465 IWM_TX_STATUS_FAIL_STA_INVALID = 0x8b, 4466 IWM_TX_STATUS_FAIL_FRAG_DROPPED = 0x8c, 4467 IWM_TX_STATUS_FAIL_TID_DISABLE = 0x8d, 4468 IWM_TX_STATUS_FAIL_FIFO_FLUSHED = 0x8e, 4469 IWM_TX_STATUS_FAIL_SMALL_CF_POLL = 0x8f, 4470 IWM_TX_STATUS_FAIL_FW_DROP = 0x90, 4471 IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH = 0x91, 4472 IWM_TX_STATUS_INTERNAL_ABORT = 0x92, 4473 IWM_TX_MODE_MSK = 0x00000f00, 4474 IWM_TX_MODE_NO_BURST = 0x00000000, 4475 IWM_TX_MODE_IN_BURST_SEQ = 0x00000100, 4476 IWM_TX_MODE_FIRST_IN_BURST = 0x00000200, 4477 IWM_TX_QUEUE_NUM_MSK = 0x0001f000, 4478 IWM_TX_NARROW_BW_MSK = 0x00060000, 4479 IWM_TX_NARROW_BW_1DIV2 = 0x00020000, 4480 IWM_TX_NARROW_BW_1DIV4 = 0x00040000, 4481 IWM_TX_NARROW_BW_1DIV8 = 0x00060000, 4482 }; 4483 4484 /* 4485 * enum iwm_tx_agg_status - TX aggregation status 4486 * @IWM_AGG_TX_STATE_STATUS_MSK: 4487 * @IWM_AGG_TX_STATE_TRANSMITTED: 4488 * @IWM_AGG_TX_STATE_UNDERRUN: 4489 * @IWM_AGG_TX_STATE_BT_PRIO: 4490 * @IWM_AGG_TX_STATE_FEW_BYTES: 4491 * @IWM_AGG_TX_STATE_ABORT: 4492 * @IWM_AGG_TX_STATE_LAST_SENT_TTL: 4493 * @IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT: 4494 * @IWM_AGG_TX_STATE_LAST_SENT_BT_KILL: 4495 * @IWM_AGG_TX_STATE_SCD_QUERY: 4496 * @IWM_AGG_TX_STATE_TEST_BAD_CRC32: 4497 * @IWM_AGG_TX_STATE_RESPONSE: 4498 * @IWM_AGG_TX_STATE_DUMP_TX: 4499 * @IWM_AGG_TX_STATE_DELAY_TX: 4500 * @IWM_AGG_TX_STATE_TRY_CNT_MSK: Retry count for 1st frame in aggregation (retries 4501 * occur if tx failed for this frame when it was a member of a previous 4502 * aggregation block). If rate scaling is used, retry count indicates the 4503 * rate table entry used for all frames in the new agg. 4504 *@ IWM_AGG_TX_STATE_SEQ_NUM_MSK: Command ID and sequence number of Tx command for 4505 * this frame 4506 * 4507 * TODO: complete documentation 4508 */ 4509 enum iwm_tx_agg_status { 4510 IWM_AGG_TX_STATE_STATUS_MSK = 0x00fff, 4511 IWM_AGG_TX_STATE_TRANSMITTED = 0x000, 4512 IWM_AGG_TX_STATE_UNDERRUN = 0x001, 4513 IWM_AGG_TX_STATE_BT_PRIO = 0x002, 4514 IWM_AGG_TX_STATE_FEW_BYTES = 0x004, 4515 IWM_AGG_TX_STATE_ABORT = 0x008, 4516 IWM_AGG_TX_STATE_LAST_SENT_TTL = 0x010, 4517 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT = 0x020, 4518 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL = 0x040, 4519 IWM_AGG_TX_STATE_SCD_QUERY = 0x080, 4520 IWM_AGG_TX_STATE_TEST_BAD_CRC32 = 0x0100, 4521 IWM_AGG_TX_STATE_RESPONSE = 0x1ff, 4522 IWM_AGG_TX_STATE_DUMP_TX = 0x200, 4523 IWM_AGG_TX_STATE_DELAY_TX = 0x400, 4524 IWM_AGG_TX_STATE_TRY_CNT_POS = 12, 4525 IWM_AGG_TX_STATE_TRY_CNT_MSK = 0xf << IWM_AGG_TX_STATE_TRY_CNT_POS, 4526 }; 4527 4528 #define IWM_AGG_TX_STATE_LAST_SENT_MSK (IWM_AGG_TX_STATE_LAST_SENT_TTL| \ 4529 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT| \ 4530 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL) 4531 4532 /* 4533 * The mask below describes a status where we are absolutely sure that the MPDU 4534 * wasn't sent. For BA/Underrun we cannot be that sure. All we know that we've 4535 * written the bytes to the TXE, but we know nothing about what the DSP did. 4536 */ 4537 #define IWM_AGG_TX_STAT_FRAME_NOT_SENT (IWM_AGG_TX_STATE_FEW_BYTES | \ 4538 IWM_AGG_TX_STATE_ABORT | \ 4539 IWM_AGG_TX_STATE_SCD_QUERY) 4540 4541 /* 4542 * IWM_REPLY_TX = 0x1c (response) 4543 * 4544 * This response may be in one of two slightly different formats, indicated 4545 * by the frame_count field: 4546 * 4547 * 1) No aggregation (frame_count == 1). This reports Tx results for a single 4548 * frame. Multiple attempts, at various bit rates, may have been made for 4549 * this frame. 4550 * 4551 * 2) Aggregation (frame_count > 1). This reports Tx results for two or more 4552 * frames that used block-acknowledge. All frames were transmitted at 4553 * same rate. Rate scaling may have been used if first frame in this new 4554 * agg block failed in previous agg block(s). 4555 * 4556 * Note that, for aggregation, ACK (block-ack) status is not delivered 4557 * here; block-ack has not been received by the time the device records 4558 * this status. 4559 * This status relates to reasons the tx might have been blocked or aborted 4560 * within the device, rather than whether it was received successfully by 4561 * the destination station. 4562 */ 4563 4564 /** 4565 * struct iwm_agg_tx_status - per packet TX aggregation status 4566 * @status: enum iwm_tx_agg_status 4567 * @sequence: Sequence # for this frame's Tx cmd (not SSN!) 4568 */ 4569 struct iwm_agg_tx_status { 4570 uint16_t status; 4571 uint16_t sequence; 4572 } __packed; 4573 4574 /* 4575 * definitions for initial rate index field 4576 * bits [3:0] initial rate index 4577 * bits [6:4] rate table color, used for the initial rate 4578 * bit-7 invalid rate indication 4579 */ 4580 #define IWM_TX_RES_INIT_RATE_INDEX_MSK 0x0f 4581 #define IWM_TX_RES_RATE_TABLE_COLOR_MSK 0x70 4582 #define IWM_TX_RES_INV_RATE_INDEX_MSK 0x80 4583 4584 #define IWM_MVM_TX_RES_GET_TID(_ra_tid) ((_ra_tid) & 0x0f) 4585 #define IWM_MVM_TX_RES_GET_RA(_ra_tid) ((_ra_tid) >> 4) 4586 4587 /** 4588 * struct iwm_mvm_tx_resp - notifies that fw is TXing a packet 4589 * ( IWM_REPLY_TX = 0x1c ) 4590 * @frame_count: 1 no aggregation, >1 aggregation 4591 * @bt_kill_count: num of times blocked by bluetooth (unused for agg) 4592 * @failure_rts: num of failures due to unsuccessful RTS 4593 * @failure_frame: num failures due to no ACK (unused for agg) 4594 * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the 4595 * Tx of all the batch. IWM_RATE_MCS_* 4596 * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK. 4597 * for agg: RTS + CTS + aggregation tx time + block-ack time. 4598 * in usec. 4599 * @pa_status: tx power info 4600 * @pa_integ_res_a: tx power info 4601 * @pa_integ_res_b: tx power info 4602 * @pa_integ_res_c: tx power info 4603 * @measurement_req_id: tx power info 4604 * @tfd_info: TFD information set by the FH 4605 * @seq_ctl: sequence control from the Tx cmd 4606 * @byte_cnt: byte count from the Tx cmd 4607 * @tlc_info: TLC rate info 4608 * @ra_tid: bits [3:0] = ra, bits [7:4] = tid 4609 * @frame_ctrl: frame control 4610 * @status: for non-agg: frame status IWM_TX_STATUS_* 4611 * for agg: status of 1st frame, IWM_AGG_TX_STATE_*; other frame status fields 4612 * follow this one, up to frame_count. 4613 * 4614 * After the array of statuses comes the SSN of the SCD. Look at 4615 * %iwm_mvm_get_scd_ssn for more details. 4616 */ 4617 struct iwm_mvm_tx_resp { 4618 uint8_t frame_count; 4619 uint8_t bt_kill_count; 4620 uint8_t failure_rts; 4621 uint8_t failure_frame; 4622 uint32_t initial_rate; 4623 uint16_t wireless_media_time; 4624 4625 uint8_t pa_status; 4626 uint8_t pa_integ_res_a[3]; 4627 uint8_t pa_integ_res_b[3]; 4628 uint8_t pa_integ_res_c[3]; 4629 uint16_t measurement_req_id; 4630 uint16_t reserved; 4631 4632 uint32_t tfd_info; 4633 uint16_t seq_ctl; 4634 uint16_t byte_cnt; 4635 uint8_t tlc_info; 4636 uint8_t ra_tid; 4637 uint16_t frame_ctrl; 4638 4639 struct iwm_agg_tx_status status; 4640 } __packed; /* IWM_TX_RSP_API_S_VER_3 */ 4641 4642 /** 4643 * struct iwm_mvm_ba_notif - notifies about reception of BA 4644 * ( IWM_BA_NOTIF = 0xc5 ) 4645 * @sta_addr_lo32: lower 32 bits of the MAC address 4646 * @sta_addr_hi16: upper 16 bits of the MAC address 4647 * @sta_id: Index of recipient (BA-sending) station in fw's station table 4648 * @tid: tid of the session 4649 * @seq_ctl: 4650 * @bitmap: the bitmap of the BA notification as seen in the air 4651 * @scd_flow: the tx queue this BA relates to 4652 * @scd_ssn: the index of the last contiguously sent packet 4653 * @txed: number of Txed frames in this batch 4654 * @txed_2_done: number of Acked frames in this batch 4655 */ 4656 struct iwm_mvm_ba_notif { 4657 uint32_t sta_addr_lo32; 4658 uint16_t sta_addr_hi16; 4659 uint16_t reserved; 4660 4661 uint8_t sta_id; 4662 uint8_t tid; 4663 uint16_t seq_ctl; 4664 uint64_t bitmap; 4665 uint16_t scd_flow; 4666 uint16_t scd_ssn; 4667 uint8_t txed; 4668 uint8_t txed_2_done; 4669 uint16_t reserved1; 4670 } __packed; 4671 4672 /* 4673 * struct iwm_mac_beacon_cmd - beacon template command 4674 * @tx: the tx commands associated with the beacon frame 4675 * @template_id: currently equal to the mac context id of the coresponding 4676 * mac. 4677 * @tim_idx: the offset of the tim IE in the beacon 4678 * @tim_size: the length of the tim IE 4679 * @frame: the template of the beacon frame 4680 */ 4681 struct iwm_mac_beacon_cmd { 4682 struct iwm_tx_cmd tx; 4683 uint32_t template_id; 4684 uint32_t tim_idx; 4685 uint32_t tim_size; 4686 struct ieee80211_frame frame[0]; 4687 } __packed; 4688 4689 struct iwm_beacon_notif { 4690 struct iwm_mvm_tx_resp beacon_notify_hdr; 4691 uint64_t tsf; 4692 uint32_t ibss_mgr_status; 4693 } __packed; 4694 4695 /** 4696 * enum iwm_dump_control - dump (flush) control flags 4697 * @IWM_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the FIFO is empty 4698 * and the TFD queues are empty. 4699 */ 4700 enum iwm_dump_control { 4701 IWM_DUMP_TX_FIFO_FLUSH = (1 << 1), 4702 }; 4703 4704 /** 4705 * struct iwm_tx_path_flush_cmd -- queue/FIFO flush command 4706 * @queues_ctl: bitmap of queues to flush 4707 * @flush_ctl: control flags 4708 * @reserved: reserved 4709 */ 4710 struct iwm_tx_path_flush_cmd { 4711 uint32_t queues_ctl; 4712 uint16_t flush_ctl; 4713 uint16_t reserved; 4714 } __packed; /* IWM_TX_PATH_FLUSH_CMD_API_S_VER_1 */ 4715 4716 /** 4717 * iwm_mvm_get_scd_ssn - returns the SSN of the SCD 4718 * @tx_resp: the Tx response from the fw (agg or non-agg) 4719 * 4720 * When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since 4721 * it can't know that everything will go well until the end of the AMPDU, it 4722 * can't know in advance the number of MPDUs that will be sent in the current 4723 * batch. This is why it writes the agg Tx response while it fetches the MPDUs. 4724 * Hence, it can't know in advance what the SSN of the SCD will be at the end 4725 * of the batch. This is why the SSN of the SCD is written at the end of the 4726 * whole struct at a variable offset. This function knows how to cope with the 4727 * variable offset and returns the SSN of the SCD. 4728 */ 4729 static inline uint32_t iwm_mvm_get_scd_ssn(struct iwm_mvm_tx_resp *tx_resp) 4730 { 4731 return le32_to_cpup((uint32_t *)&tx_resp->status + 4732 tx_resp->frame_count) & 0xfff; 4733 } 4734 4735 /* 4736 * END mvm/fw-api-tx.h 4737 */ 4738 4739 /* 4740 * BEGIN mvm/fw-api-scan.h 4741 */ 4742 4743 /** 4744 * struct iwm_scd_txq_cfg_cmd - New txq hw scheduler config command 4745 * @token: 4746 * @sta_id: station id 4747 * @tid: 4748 * @scd_queue: scheduler queue to confiug 4749 * @enable: 1 queue enable, 0 queue disable 4750 * @aggregate: 1 aggregated queue, 0 otherwise 4751 * @tx_fifo: %enum iwm_mvm_tx_fifo 4752 * @window: BA window size 4753 * @ssn: SSN for the BA agreement 4754 */ 4755 struct iwm_scd_txq_cfg_cmd { 4756 uint8_t token; 4757 uint8_t sta_id; 4758 uint8_t tid; 4759 uint8_t scd_queue; 4760 uint8_t enable; 4761 uint8_t aggregate; 4762 uint8_t tx_fifo; 4763 uint8_t window; 4764 uint16_t ssn; 4765 uint16_t reserved; 4766 } __packed; /* SCD_QUEUE_CFG_CMD_API_S_VER_1 */ 4767 4768 /** 4769 * struct iwm_scd_txq_cfg_rsp 4770 * @token: taken from the command 4771 * @sta_id: station id from the command 4772 * @tid: tid from the command 4773 * @scd_queue: scd_queue from the command 4774 */ 4775 struct iwm_scd_txq_cfg_rsp { 4776 uint8_t token; 4777 uint8_t sta_id; 4778 uint8_t tid; 4779 uint8_t scd_queue; 4780 } __packed; /* SCD_QUEUE_CFG_RSP_API_S_VER_1 */ 4781 4782 4783 /* Scan Commands, Responses, Notifications */ 4784 4785 /* Masks for iwm_scan_channel.type flags */ 4786 #define IWM_SCAN_CHANNEL_TYPE_ACTIVE (1 << 0) 4787 #define IWM_SCAN_CHANNEL_NSSIDS(x) (((1 << (x)) - 1) << 1) 4788 4789 /* Max number of IEs for direct SSID scans in a command */ 4790 #define IWM_PROBE_OPTION_MAX 20 4791 4792 /** 4793 * struct iwm_ssid_ie - directed scan network information element 4794 * 4795 * Up to 20 of these may appear in IWM_REPLY_SCAN_CMD, 4796 * selected by "type" bit field in struct iwm_scan_channel; 4797 * each channel may select different ssids from among the 20 entries. 4798 * SSID IEs get transmitted in reverse order of entry. 4799 */ 4800 struct iwm_ssid_ie { 4801 uint8_t id; 4802 uint8_t len; 4803 uint8_t ssid[IEEE80211_NWID_LEN]; 4804 } __packed; /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */ 4805 4806 /* scan offload */ 4807 #define IWM_SCAN_MAX_BLACKLIST_LEN 64 4808 #define IWM_SCAN_SHORT_BLACKLIST_LEN 16 4809 #define IWM_SCAN_MAX_PROFILES 11 4810 #define IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE 512 4811 4812 /* Default watchdog (in MS) for scheduled scan iteration */ 4813 #define IWM_SCHED_SCAN_WATCHDOG cpu_to_le16(15000) 4814 4815 #define IWM_GOOD_CRC_TH_DEFAULT cpu_to_le16(1) 4816 #define IWM_CAN_ABORT_STATUS 1 4817 4818 #define IWM_FULL_SCAN_MULTIPLIER 5 4819 #define IWM_FAST_SCHED_SCAN_ITERATIONS 3 4820 #define IWM_MAX_SCHED_SCAN_PLANS 2 4821 4822 /** 4823 * iwm_scan_schedule_lmac - schedule of scan offload 4824 * @delay: delay between iterations, in seconds. 4825 * @iterations: num of scan iterations 4826 * @full_scan_mul: number of partial scans before each full scan 4827 */ 4828 struct iwm_scan_schedule_lmac { 4829 uint16_t delay; 4830 uint8_t iterations; 4831 uint8_t full_scan_mul; 4832 } __packed; /* SCAN_SCHEDULE_API_S */ 4833 4834 /** 4835 * iwm_scan_req_tx_cmd - SCAN_REQ_TX_CMD_API_S 4836 * @tx_flags: combination of TX_CMD_FLG_* 4837 * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is 4838 * cleared. Combination of RATE_MCS_* 4839 * @sta_id: index of destination station in FW station table 4840 * @reserved: for alignment and future use 4841 */ 4842 struct iwm_scan_req_tx_cmd { 4843 uint32_t tx_flags; 4844 uint32_t rate_n_flags; 4845 uint8_t sta_id; 4846 uint8_t reserved[3]; 4847 } __packed; 4848 4849 enum iwm_scan_channel_flags_lmac { 4850 IWM_UNIFIED_SCAN_CHANNEL_FULL = (1 << 27), 4851 IWM_UNIFIED_SCAN_CHANNEL_PARTIAL = (1 << 28), 4852 }; 4853 4854 /** 4855 * iwm_scan_channel_cfg_lmac - SCAN_CHANNEL_CFG_S_VER2 4856 * @flags: bits 1-20: directed scan to i'th ssid 4857 * other bits &enum iwm_scan_channel_flags_lmac 4858 * @channel_number: channel number 1-13 etc 4859 * @iter_count: scan iteration on this channel 4860 * @iter_interval: interval in seconds between iterations on one channel 4861 */ 4862 struct iwm_scan_channel_cfg_lmac { 4863 uint32_t flags; 4864 uint16_t channel_num; 4865 uint16_t iter_count; 4866 uint32_t iter_interval; 4867 } __packed; 4868 4869 /* 4870 * iwm_scan_probe_segment - PROBE_SEGMENT_API_S_VER_1 4871 * @offset: offset in the data block 4872 * @len: length of the segment 4873 */ 4874 struct iwm_scan_probe_segment { 4875 uint16_t offset; 4876 uint16_t len; 4877 } __packed; 4878 4879 /* iwm_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_2 4880 * @mac_header: first (and common) part of the probe 4881 * @band_data: band specific data 4882 * @common_data: last (and common) part of the probe 4883 * @buf: raw data block 4884 */ 4885 struct iwm_scan_probe_req { 4886 struct iwm_scan_probe_segment mac_header; 4887 struct iwm_scan_probe_segment band_data[2]; 4888 struct iwm_scan_probe_segment common_data; 4889 uint8_t buf[IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE]; 4890 } __packed; 4891 4892 enum iwm_scan_channel_flags { 4893 IWM_SCAN_CHANNEL_FLAG_EBS = (1 << 0), 4894 IWM_SCAN_CHANNEL_FLAG_EBS_ACCURATE = (1 << 1), 4895 IWM_SCAN_CHANNEL_FLAG_CACHE_ADD = (1 << 2), 4896 }; 4897 4898 /* iwm_scan_channel_opt - CHANNEL_OPTIMIZATION_API_S 4899 * @flags: enum iwm_scan_channel_flags 4900 * @non_ebs_ratio: defines the ratio of number of scan iterations where EBS is 4901 * involved. 4902 * 1 - EBS is disabled. 4903 * 2 - every second scan will be full scan(and so on). 4904 */ 4905 struct iwm_scan_channel_opt { 4906 uint16_t flags; 4907 uint16_t non_ebs_ratio; 4908 } __packed; 4909 4910 /** 4911 * iwm_mvm_lmac_scan_flags 4912 * @IWM_MVM_LMAC_SCAN_FLAG_PASS_ALL: pass all beacons and probe responses 4913 * without filtering. 4914 * @IWM_MVM_LMAC_SCAN_FLAG_PASSIVE: force passive scan on all channels 4915 * @IWM_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION: single channel scan 4916 * @IWM_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE: send iteration complete notification 4917 * @IWM_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS multiple SSID matching 4918 * @IWM_MVM_LMAC_SCAN_FLAG_FRAGMENTED: all passive scans will be fragmented 4919 * @IWM_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED: insert WFA vendor-specific TPC report 4920 * and DS parameter set IEs into probe requests. 4921 * @IWM_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL: use extended dwell time on channels 4922 * 1, 6 and 11. 4923 * @IWM_MVM_LMAC_SCAN_FLAG_MATCH: Send match found notification on matches 4924 */ 4925 enum iwm_mvm_lmac_scan_flags { 4926 IWM_MVM_LMAC_SCAN_FLAG_PASS_ALL = (1 << 0), 4927 IWM_MVM_LMAC_SCAN_FLAG_PASSIVE = (1 << 1), 4928 IWM_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION = (1 << 2), 4929 IWM_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE = (1 << 3), 4930 IWM_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS = (1 << 4), 4931 IWM_MVM_LMAC_SCAN_FLAG_FRAGMENTED = (1 << 5), 4932 IWM_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED = (1 << 6), 4933 IWM_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL = (1 << 7), 4934 IWM_MVM_LMAC_SCAN_FLAG_MATCH = (1 << 9), 4935 }; 4936 4937 enum iwm_scan_priority { 4938 IWM_SCAN_PRIORITY_LOW, 4939 IWM_SCAN_PRIORITY_MEDIUM, 4940 IWM_SCAN_PRIORITY_HIGH, 4941 }; 4942 4943 /** 4944 * iwm_scan_req_lmac - SCAN_REQUEST_CMD_API_S_VER_1 4945 * @reserved1: for alignment and future use 4946 * @channel_num: num of channels to scan 4947 * @active-dwell: dwell time for active channels 4948 * @passive-dwell: dwell time for passive channels 4949 * @fragmented-dwell: dwell time for fragmented passive scan 4950 * @extended_dwell: dwell time for channels 1, 6 and 11 (in certain cases) 4951 * @reserved2: for alignment and future use 4952 * @rx_chain_selct: PHY_RX_CHAIN_* flags 4953 * @scan_flags: &enum iwm_mvm_lmac_scan_flags 4954 * @max_out_time: max time (in TU) to be out of associated channel 4955 * @suspend_time: pause scan this long (TUs) when returning to service channel 4956 * @flags: RXON flags 4957 * @filter_flags: RXON filter 4958 * @tx_cmd: tx command for active scan; for 2GHz and for 5GHz 4959 * @direct_scan: list of SSIDs for directed active scan 4960 * @scan_prio: enum iwm_scan_priority 4961 * @iter_num: number of scan iterations 4962 * @delay: delay in seconds before first iteration 4963 * @schedule: two scheduling plans. The first one is finite, the second one can 4964 * be infinite. 4965 * @channel_opt: channel optimization options, for full and partial scan 4966 * @data: channel configuration and probe request packet. 4967 */ 4968 struct iwm_scan_req_lmac { 4969 /* SCAN_REQUEST_FIXED_PART_API_S_VER_7 */ 4970 uint32_t reserved1; 4971 uint8_t n_channels; 4972 uint8_t active_dwell; 4973 uint8_t passive_dwell; 4974 uint8_t fragmented_dwell; 4975 uint8_t extended_dwell; 4976 uint8_t reserved2; 4977 uint16_t rx_chain_select; 4978 uint32_t scan_flags; 4979 uint32_t max_out_time; 4980 uint32_t suspend_time; 4981 /* RX_ON_FLAGS_API_S_VER_1 */ 4982 uint32_t flags; 4983 uint32_t filter_flags; 4984 struct iwm_scan_req_tx_cmd tx_cmd[2]; 4985 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 4986 uint32_t scan_prio; 4987 /* SCAN_REQ_PERIODIC_PARAMS_API_S */ 4988 uint32_t iter_num; 4989 uint32_t delay; 4990 struct iwm_scan_schedule_lmac schedule[IWM_MAX_SCHED_SCAN_PLANS]; 4991 struct iwm_scan_channel_opt channel_opt[2]; 4992 uint8_t data[]; 4993 } __packed; 4994 4995 /** 4996 * iwm_scan_offload_complete - PERIODIC_SCAN_COMPLETE_NTF_API_S_VER_2 4997 * @last_schedule_line: last schedule line executed (fast or regular) 4998 * @last_schedule_iteration: last scan iteration executed before scan abort 4999 * @status: enum iwm_scan_offload_complete_status 5000 * @ebs_status: EBS success status &enum iwm_scan_ebs_status 5001 * @time_after_last_iter; time in seconds elapsed after last iteration 5002 */ 5003 struct iwm_periodic_scan_complete { 5004 uint8_t last_schedule_line; 5005 uint8_t last_schedule_iteration; 5006 uint8_t status; 5007 uint8_t ebs_status; 5008 uint32_t time_after_last_iter; 5009 uint32_t reserved; 5010 } __packed; 5011 5012 /* How many statistics are gathered for each channel */ 5013 #define IWM_SCAN_RESULTS_STATISTICS 1 5014 5015 /** 5016 * enum iwm_scan_complete_status - status codes for scan complete notifications 5017 * @IWM_SCAN_COMP_STATUS_OK: scan completed successfully 5018 * @IWM_SCAN_COMP_STATUS_ABORT: scan was aborted by user 5019 * @IWM_SCAN_COMP_STATUS_ERR_SLEEP: sending null sleep packet failed 5020 * @IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT: timeout before channel is ready 5021 * @IWM_SCAN_COMP_STATUS_ERR_PROBE: sending probe request failed 5022 * @IWM_SCAN_COMP_STATUS_ERR_WAKEUP: sending null wakeup packet failed 5023 * @IWM_SCAN_COMP_STATUS_ERR_ANTENNAS: invalid antennas chosen at scan command 5024 * @IWM_SCAN_COMP_STATUS_ERR_INTERNAL: internal error caused scan abort 5025 * @IWM_SCAN_COMP_STATUS_ERR_COEX: medium was lost ot WiMax 5026 * @IWM_SCAN_COMP_STATUS_P2P_ACTION_OK: P2P public action frame TX was successful 5027 * (not an error!) 5028 * @IWM_SCAN_COMP_STATUS_ITERATION_END: indicates end of one repeatition the driver 5029 * asked for 5030 * @IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE: scan could not allocate time events 5031 */ 5032 enum iwm_scan_complete_status { 5033 IWM_SCAN_COMP_STATUS_OK = 0x1, 5034 IWM_SCAN_COMP_STATUS_ABORT = 0x2, 5035 IWM_SCAN_COMP_STATUS_ERR_SLEEP = 0x3, 5036 IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT = 0x4, 5037 IWM_SCAN_COMP_STATUS_ERR_PROBE = 0x5, 5038 IWM_SCAN_COMP_STATUS_ERR_WAKEUP = 0x6, 5039 IWM_SCAN_COMP_STATUS_ERR_ANTENNAS = 0x7, 5040 IWM_SCAN_COMP_STATUS_ERR_INTERNAL = 0x8, 5041 IWM_SCAN_COMP_STATUS_ERR_COEX = 0x9, 5042 IWM_SCAN_COMP_STATUS_P2P_ACTION_OK = 0xA, 5043 IWM_SCAN_COMP_STATUS_ITERATION_END = 0x0B, 5044 IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE = 0x0C, 5045 }; 5046 5047 /** 5048 * struct iwm_scan_results_notif - scan results for one channel 5049 * ( IWM_SCAN_RESULTS_NOTIFICATION = 0x83 ) 5050 * @channel: which channel the results are from 5051 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz 5052 * @probe_status: IWM_SCAN_PROBE_STATUS_*, indicates success of probe request 5053 * @num_probe_not_sent: # of request that weren't sent due to not enough time 5054 * @duration: duration spent in channel, in usecs 5055 * @statistics: statistics gathered for this channel 5056 */ 5057 struct iwm_scan_results_notif { 5058 uint8_t channel; 5059 uint8_t band; 5060 uint8_t probe_status; 5061 uint8_t num_probe_not_sent; 5062 uint32_t duration; 5063 uint32_t statistics[IWM_SCAN_RESULTS_STATISTICS]; 5064 } __packed; /* IWM_SCAN_RESULT_NTF_API_S_VER_2 */ 5065 5066 enum iwm_scan_framework_client { 5067 IWM_SCAN_CLIENT_SCHED_SCAN = (1 << 0), 5068 IWM_SCAN_CLIENT_NETDETECT = (1 << 1), 5069 IWM_SCAN_CLIENT_ASSET_TRACKING = (1 << 2), 5070 }; 5071 5072 /** 5073 * iwm_scan_offload_blacklist - IWM_SCAN_OFFLOAD_BLACKLIST_S 5074 * @ssid: MAC address to filter out 5075 * @reported_rssi: AP rssi reported to the host 5076 * @client_bitmap: clients ignore this entry - enum scan_framework_client 5077 */ 5078 struct iwm_scan_offload_blacklist { 5079 uint8_t ssid[IEEE80211_ADDR_LEN]; 5080 uint8_t reported_rssi; 5081 uint8_t client_bitmap; 5082 } __packed; 5083 5084 enum iwm_scan_offload_network_type { 5085 IWM_NETWORK_TYPE_BSS = 1, 5086 IWM_NETWORK_TYPE_IBSS = 2, 5087 IWM_NETWORK_TYPE_ANY = 3, 5088 }; 5089 5090 enum iwm_scan_offload_band_selection { 5091 IWM_SCAN_OFFLOAD_SELECT_2_4 = 0x4, 5092 IWM_SCAN_OFFLOAD_SELECT_5_2 = 0x8, 5093 IWM_SCAN_OFFLOAD_SELECT_ANY = 0xc, 5094 }; 5095 5096 /** 5097 * iwm_scan_offload_profile - IWM_SCAN_OFFLOAD_PROFILE_S 5098 * @ssid_index: index to ssid list in fixed part 5099 * @unicast_cipher: encryption olgorithm to match - bitmap 5100 * @aut_alg: authentication olgorithm to match - bitmap 5101 * @network_type: enum iwm_scan_offload_network_type 5102 * @band_selection: enum iwm_scan_offload_band_selection 5103 * @client_bitmap: clients waiting for match - enum scan_framework_client 5104 */ 5105 struct iwm_scan_offload_profile { 5106 uint8_t ssid_index; 5107 uint8_t unicast_cipher; 5108 uint8_t auth_alg; 5109 uint8_t network_type; 5110 uint8_t band_selection; 5111 uint8_t client_bitmap; 5112 uint8_t reserved[2]; 5113 } __packed; 5114 5115 /** 5116 * iwm_scan_offload_profile_cfg - IWM_SCAN_OFFLOAD_PROFILES_CFG_API_S_VER_1 5117 * @blaclist: AP list to filter off from scan results 5118 * @profiles: profiles to search for match 5119 * @blacklist_len: length of blacklist 5120 * @num_profiles: num of profiles in the list 5121 * @match_notify: clients waiting for match found notification 5122 * @pass_match: clients waiting for the results 5123 * @active_clients: active clients bitmap - enum scan_framework_client 5124 * @any_beacon_notify: clients waiting for match notification without match 5125 */ 5126 struct iwm_scan_offload_profile_cfg { 5127 struct iwm_scan_offload_profile profiles[IWM_SCAN_MAX_PROFILES]; 5128 uint8_t blacklist_len; 5129 uint8_t num_profiles; 5130 uint8_t match_notify; 5131 uint8_t pass_match; 5132 uint8_t active_clients; 5133 uint8_t any_beacon_notify; 5134 uint8_t reserved[2]; 5135 } __packed; 5136 5137 enum iwm_scan_offload_complete_status { 5138 IWM_SCAN_OFFLOAD_COMPLETED = 1, 5139 IWM_SCAN_OFFLOAD_ABORTED = 2, 5140 }; 5141 5142 /** 5143 * struct iwm_lmac_scan_complete_notif - notifies end of scanning (all channels) 5144 * SCAN_COMPLETE_NTF_API_S_VER_3 5145 * @scanned_channels: number of channels scanned (and number of valid results) 5146 * @status: one of SCAN_COMP_STATUS_* 5147 * @bt_status: BT on/off status 5148 * @last_channel: last channel that was scanned 5149 * @tsf_low: TSF timer (lower half) in usecs 5150 * @tsf_high: TSF timer (higher half) in usecs 5151 * @results: an array of scan results, only "scanned_channels" of them are valid 5152 */ 5153 struct iwm_lmac_scan_complete_notif { 5154 uint8_t scanned_channels; 5155 uint8_t status; 5156 uint8_t bt_status; 5157 uint8_t last_channel; 5158 uint32_t tsf_low; 5159 uint32_t tsf_high; 5160 struct iwm_scan_results_notif results[]; 5161 } __packed; 5162 5163 5164 /* 5165 * END mvm/fw-api-scan.h 5166 */ 5167 5168 /* 5169 * BEGIN mvm/fw-api-sta.h 5170 */ 5171 5172 /* UMAC Scan API */ 5173 5174 /* The maximum of either of these cannot exceed 8, because we use an 5175 * 8-bit mask (see IWM_MVM_SCAN_MASK). 5176 */ 5177 #define IWM_MVM_MAX_UMAC_SCANS 8 5178 #define IWM_MVM_MAX_LMAC_SCANS 1 5179 5180 enum iwm_scan_config_flags { 5181 IWM_SCAN_CONFIG_FLAG_ACTIVATE = (1 << 0), 5182 IWM_SCAN_CONFIG_FLAG_DEACTIVATE = (1 << 1), 5183 IWM_SCAN_CONFIG_FLAG_FORBID_CHUB_REQS = (1 << 2), 5184 IWM_SCAN_CONFIG_FLAG_ALLOW_CHUB_REQS = (1 << 3), 5185 IWM_SCAN_CONFIG_FLAG_SET_TX_CHAINS = (1 << 8), 5186 IWM_SCAN_CONFIG_FLAG_SET_RX_CHAINS = (1 << 9), 5187 IWM_SCAN_CONFIG_FLAG_SET_AUX_STA_ID = (1 << 10), 5188 IWM_SCAN_CONFIG_FLAG_SET_ALL_TIMES = (1 << 11), 5189 IWM_SCAN_CONFIG_FLAG_SET_EFFECTIVE_TIMES = (1 << 12), 5190 IWM_SCAN_CONFIG_FLAG_SET_CHANNEL_FLAGS = (1 << 13), 5191 IWM_SCAN_CONFIG_FLAG_SET_LEGACY_RATES = (1 << 14), 5192 IWM_SCAN_CONFIG_FLAG_SET_MAC_ADDR = (1 << 15), 5193 IWM_SCAN_CONFIG_FLAG_SET_FRAGMENTED = (1 << 16), 5194 IWM_SCAN_CONFIG_FLAG_CLEAR_FRAGMENTED = (1 << 17), 5195 IWM_SCAN_CONFIG_FLAG_SET_CAM_MODE = (1 << 18), 5196 IWM_SCAN_CONFIG_FLAG_CLEAR_CAM_MODE = (1 << 19), 5197 IWM_SCAN_CONFIG_FLAG_SET_PROMISC_MODE = (1 << 20), 5198 IWM_SCAN_CONFIG_FLAG_CLEAR_PROMISC_MODE = (1 << 21), 5199 5200 /* Bits 26-31 are for num of channels in channel_array */ 5201 #define IWM_SCAN_CONFIG_N_CHANNELS(n) ((n) << 26) 5202 }; 5203 5204 enum iwm_scan_config_rates { 5205 /* OFDM basic rates */ 5206 IWM_SCAN_CONFIG_RATE_6M = (1 << 0), 5207 IWM_SCAN_CONFIG_RATE_9M = (1 << 1), 5208 IWM_SCAN_CONFIG_RATE_12M = (1 << 2), 5209 IWM_SCAN_CONFIG_RATE_18M = (1 << 3), 5210 IWM_SCAN_CONFIG_RATE_24M = (1 << 4), 5211 IWM_SCAN_CONFIG_RATE_36M = (1 << 5), 5212 IWM_SCAN_CONFIG_RATE_48M = (1 << 6), 5213 IWM_SCAN_CONFIG_RATE_54M = (1 << 7), 5214 /* CCK basic rates */ 5215 IWM_SCAN_CONFIG_RATE_1M = (1 << 8), 5216 IWM_SCAN_CONFIG_RATE_2M = (1 << 9), 5217 IWM_SCAN_CONFIG_RATE_5M = (1 << 10), 5218 IWM_SCAN_CONFIG_RATE_11M = (1 << 11), 5219 5220 /* Bits 16-27 are for supported rates */ 5221 #define IWM_SCAN_CONFIG_SUPPORTED_RATE(rate) ((rate) << 16) 5222 }; 5223 5224 enum iwm_channel_flags { 5225 IWM_CHANNEL_FLAG_EBS = (1 << 0), 5226 IWM_CHANNEL_FLAG_ACCURATE_EBS = (1 << 1), 5227 IWM_CHANNEL_FLAG_EBS_ADD = (1 << 2), 5228 IWM_CHANNEL_FLAG_PRE_SCAN_PASSIVE2ACTIVE = (1 << 3), 5229 }; 5230 5231 /** 5232 * struct iwm_scan_config 5233 * @flags: enum scan_config_flags 5234 * @tx_chains: valid_tx antenna - ANT_* definitions 5235 * @rx_chains: valid_rx antenna - ANT_* definitions 5236 * @legacy_rates: default legacy rates - enum scan_config_rates 5237 * @out_of_channel_time: default max out of serving channel time 5238 * @suspend_time: default max suspend time 5239 * @dwell_active: default dwell time for active scan 5240 * @dwell_passive: default dwell time for passive scan 5241 * @dwell_fragmented: default dwell time for fragmented scan 5242 * @dwell_extended: default dwell time for channels 1, 6 and 11 5243 * @mac_addr: default mac address to be used in probes 5244 * @bcast_sta_id: the index of the station in the fw 5245 * @channel_flags: default channel flags - enum iwm_channel_flags 5246 * scan_config_channel_flag 5247 * @channel_array: default supported channels 5248 */ 5249 struct iwm_scan_config { 5250 uint32_t flags; 5251 uint32_t tx_chains; 5252 uint32_t rx_chains; 5253 uint32_t legacy_rates; 5254 uint32_t out_of_channel_time; 5255 uint32_t suspend_time; 5256 uint8_t dwell_active; 5257 uint8_t dwell_passive; 5258 uint8_t dwell_fragmented; 5259 uint8_t dwell_extended; 5260 uint8_t mac_addr[IEEE80211_ADDR_LEN]; 5261 uint8_t bcast_sta_id; 5262 uint8_t channel_flags; 5263 uint8_t channel_array[]; 5264 } __packed; /* SCAN_CONFIG_DB_CMD_API_S */ 5265 5266 /** 5267 * iwm_umac_scan_flags 5268 *@IWM_UMAC_SCAN_FLAG_PREEMPTIVE: scan process triggered by this scan request 5269 * can be preempted by other scan requests with higher priority. 5270 * The low priority scan will be resumed when the higher proirity scan is 5271 * completed. 5272 *@IWM_UMAC_SCAN_FLAG_START_NOTIF: notification will be sent to the driver 5273 * when scan starts. 5274 */ 5275 enum iwm_umac_scan_flags { 5276 IWM_UMAC_SCAN_FLAG_PREEMPTIVE = (1 << 0), 5277 IWM_UMAC_SCAN_FLAG_START_NOTIF = (1 << 1), 5278 }; 5279 5280 enum iwm_umac_scan_uid_offsets { 5281 IWM_UMAC_SCAN_UID_TYPE_OFFSET = 0, 5282 IWM_UMAC_SCAN_UID_SEQ_OFFSET = 8, 5283 }; 5284 5285 enum iwm_umac_scan_general_flags { 5286 IWM_UMAC_SCAN_GEN_FLAGS_PERIODIC = (1 << 0), 5287 IWM_UMAC_SCAN_GEN_FLAGS_OVER_BT = (1 << 1), 5288 IWM_UMAC_SCAN_GEN_FLAGS_PASS_ALL = (1 << 2), 5289 IWM_UMAC_SCAN_GEN_FLAGS_PASSIVE = (1 << 3), 5290 IWM_UMAC_SCAN_GEN_FLAGS_PRE_CONNECT = (1 << 4), 5291 IWM_UMAC_SCAN_GEN_FLAGS_ITER_COMPLETE = (1 << 5), 5292 IWM_UMAC_SCAN_GEN_FLAGS_MULTIPLE_SSID = (1 << 6), 5293 IWM_UMAC_SCAN_GEN_FLAGS_FRAGMENTED = (1 << 7), 5294 IWM_UMAC_SCAN_GEN_FLAGS_RRM_ENABLED = (1 << 8), 5295 IWM_UMAC_SCAN_GEN_FLAGS_MATCH = (1 << 9), 5296 IWM_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL = (1 << 10), 5297 }; 5298 5299 /** 5300 * struct iwm_scan_channel_cfg_umac 5301 * @flags: bitmap - 0-19: directed scan to i'th ssid. 5302 * @channel_num: channel number 1-13 etc. 5303 * @iter_count: repetition count for the channel. 5304 * @iter_interval: interval between two scan iterations on one channel. 5305 */ 5306 struct iwm_scan_channel_cfg_umac { 5307 uint32_t flags; 5308 #define IWM_SCAN_CHANNEL_UMAC_NSSIDS(x) ((1 << (x)) - 1) 5309 5310 uint8_t channel_num; 5311 uint8_t iter_count; 5312 uint16_t iter_interval; 5313 } __packed; /* SCAN_CHANNEL_CFG_S_VER2 */ 5314 5315 /** 5316 * struct iwm_scan_umac_schedule 5317 * @interval: interval in seconds between scan iterations 5318 * @iter_count: num of scan iterations for schedule plan, 0xff for infinite loop 5319 * @reserved: for alignment and future use 5320 */ 5321 struct iwm_scan_umac_schedule { 5322 uint16_t interval; 5323 uint8_t iter_count; 5324 uint8_t reserved; 5325 } __packed; /* SCAN_SCHED_PARAM_API_S_VER_1 */ 5326 5327 /** 5328 * struct iwm_scan_req_umac_tail - the rest of the UMAC scan request command 5329 * parameters following channels configuration array. 5330 * @schedule: two scheduling plans. 5331 * @delay: delay in TUs before starting the first scan iteration 5332 * @reserved: for future use and alignment 5333 * @preq: probe request with IEs blocks 5334 * @direct_scan: list of SSIDs for directed active scan 5335 */ 5336 struct iwm_scan_req_umac_tail { 5337 /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */ 5338 struct iwm_scan_umac_schedule schedule[IWM_MAX_SCHED_SCAN_PLANS]; 5339 uint16_t delay; 5340 uint16_t reserved; 5341 /* SCAN_PROBE_PARAMS_API_S_VER_1 */ 5342 struct iwm_scan_probe_req preq; 5343 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 5344 } __packed; 5345 5346 /** 5347 * struct iwm_scan_req_umac 5348 * @flags: &enum iwm_umac_scan_flags 5349 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5350 * @ooc_priority: out of channel priority - &enum iwm_scan_priority 5351 * @general_flags: &enum iwm_umac_scan_general_flags 5352 * @extended_dwell: dwell time for channels 1, 6 and 11 5353 * @active_dwell: dwell time for active scan 5354 * @passive_dwell: dwell time for passive scan 5355 * @fragmented_dwell: dwell time for fragmented passive scan 5356 * @max_out_time: max out of serving channel time 5357 * @suspend_time: max suspend time 5358 * @scan_priority: scan internal prioritization &enum iwm_scan_priority 5359 * @channel_flags: &enum iwm_scan_channel_flags 5360 * @n_channels: num of channels in scan request 5361 * @reserved: for future use and alignment 5362 * @data: &struct iwm_scan_channel_cfg_umac and 5363 * &struct iwm_scan_req_umac_tail 5364 */ 5365 struct iwm_scan_req_umac { 5366 uint32_t flags; 5367 uint32_t uid; 5368 uint32_t ooc_priority; 5369 /* SCAN_GENERAL_PARAMS_API_S_VER_1 */ 5370 uint32_t general_flags; 5371 uint8_t extended_dwell; 5372 uint8_t active_dwell; 5373 uint8_t passive_dwell; 5374 uint8_t fragmented_dwell; 5375 uint32_t max_out_time; 5376 uint32_t suspend_time; 5377 uint32_t scan_priority; 5378 /* SCAN_CHANNEL_PARAMS_API_S_VER_1 */ 5379 uint8_t channel_flags; 5380 uint8_t n_channels; 5381 uint16_t reserved; 5382 uint8_t data[]; 5383 } __packed; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_1 */ 5384 5385 /** 5386 * struct iwm_umac_scan_abort 5387 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5388 * @flags: reserved 5389 */ 5390 struct iwm_umac_scan_abort { 5391 uint32_t uid; 5392 uint32_t flags; 5393 } __packed; /* SCAN_ABORT_CMD_UMAC_API_S_VER_1 */ 5394 5395 /** 5396 * struct iwm_umac_scan_complete 5397 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5398 * @last_schedule: last scheduling line 5399 * @last_iter: last scan iteration number 5400 * @scan status: &enum iwm_scan_offload_complete_status 5401 * @ebs_status: &enum iwm_scan_ebs_status 5402 * @time_from_last_iter: time elapsed from last iteration 5403 * @reserved: for future use 5404 */ 5405 struct iwm_umac_scan_complete { 5406 uint32_t uid; 5407 uint8_t last_schedule; 5408 uint8_t last_iter; 5409 uint8_t status; 5410 uint8_t ebs_status; 5411 uint32_t time_from_last_iter; 5412 uint32_t reserved; 5413 } __packed; /* SCAN_COMPLETE_NTF_UMAC_API_S_VER_1 */ 5414 5415 #define IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN 5 5416 /** 5417 * struct iwm_scan_offload_profile_match - match information 5418 * @bssid: matched bssid 5419 * @channel: channel where the match occurred 5420 * @energy: 5421 * @matching_feature: 5422 * @matching_channels: bitmap of channels that matched, referencing 5423 * the channels passed in tue scan offload request 5424 */ 5425 struct iwm_scan_offload_profile_match { 5426 uint8_t bssid[IEEE80211_ADDR_LEN]; 5427 uint16_t reserved; 5428 uint8_t channel; 5429 uint8_t energy; 5430 uint8_t matching_feature; 5431 uint8_t matching_channels[IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN]; 5432 } __packed; /* SCAN_OFFLOAD_PROFILE_MATCH_RESULTS_S_VER_1 */ 5433 5434 /** 5435 * struct iwm_scan_offload_profiles_query - match results query response 5436 * @matched_profiles: bitmap of matched profiles, referencing the 5437 * matches passed in the scan offload request 5438 * @last_scan_age: age of the last offloaded scan 5439 * @n_scans_done: number of offloaded scans done 5440 * @gp2_d0u: GP2 when D0U occurred 5441 * @gp2_invoked: GP2 when scan offload was invoked 5442 * @resume_while_scanning: not used 5443 * @self_recovery: obsolete 5444 * @reserved: reserved 5445 * @matches: array of match information, one for each match 5446 */ 5447 struct iwm_scan_offload_profiles_query { 5448 uint32_t matched_profiles; 5449 uint32_t last_scan_age; 5450 uint32_t n_scans_done; 5451 uint32_t gp2_d0u; 5452 uint32_t gp2_invoked; 5453 uint8_t resume_while_scanning; 5454 uint8_t self_recovery; 5455 uint16_t reserved; 5456 struct iwm_scan_offload_profile_match matches[IWM_SCAN_MAX_PROFILES]; 5457 } __packed; /* SCAN_OFFLOAD_PROFILES_QUERY_RSP_S_VER_2 */ 5458 5459 /** 5460 * struct iwm_umac_scan_iter_complete_notif - notifies end of scanning iteration 5461 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5462 * @scanned_channels: number of channels scanned and number of valid elements in 5463 * results array 5464 * @status: one of SCAN_COMP_STATUS_* 5465 * @bt_status: BT on/off status 5466 * @last_channel: last channel that was scanned 5467 * @tsf_low: TSF timer (lower half) in usecs 5468 * @tsf_high: TSF timer (higher half) in usecs 5469 * @results: array of scan results, only "scanned_channels" of them are valid 5470 */ 5471 struct iwm_umac_scan_iter_complete_notif { 5472 uint32_t uid; 5473 uint8_t scanned_channels; 5474 uint8_t status; 5475 uint8_t bt_status; 5476 uint8_t last_channel; 5477 uint32_t tsf_low; 5478 uint32_t tsf_high; 5479 struct iwm_scan_results_notif results[]; 5480 } __packed; /* SCAN_ITER_COMPLETE_NTF_UMAC_API_S_VER_1 */ 5481 5482 /* Please keep this enum *SORTED* by hex value. 5483 * Needed for binary search, otherwise a warning will be triggered. 5484 */ 5485 enum iwm_scan_subcmd_ids { 5486 IWM_GSCAN_START_CMD = 0x0, 5487 IWM_GSCAN_STOP_CMD = 0x1, 5488 IWM_GSCAN_SET_HOTLIST_CMD = 0x2, 5489 IWM_GSCAN_RESET_HOTLIST_CMD = 0x3, 5490 IWM_GSCAN_SET_SIGNIFICANT_CHANGE_CMD = 0x4, 5491 IWM_GSCAN_RESET_SIGNIFICANT_CHANGE_CMD = 0x5, 5492 IWM_GSCAN_SIGNIFICANT_CHANGE_EVENT = 0xFD, 5493 IWM_GSCAN_HOTLIST_CHANGE_EVENT = 0xFE, 5494 IWM_GSCAN_RESULTS_AVAILABLE_EVENT = 0xFF, 5495 }; 5496 5497 /* STA API */ 5498 5499 /** 5500 * enum iwm_sta_flags - flags for the ADD_STA host command 5501 * @IWM_STA_FLG_REDUCED_TX_PWR_CTRL: 5502 * @IWM_STA_FLG_REDUCED_TX_PWR_DATA: 5503 * @IWM_STA_FLG_DISABLE_TX: set if TX should be disabled 5504 * @IWM_STA_FLG_PS: set if STA is in Power Save 5505 * @IWM_STA_FLG_INVALID: set if STA is invalid 5506 * @IWM_STA_FLG_DLP_EN: Direct Link Protocol is enabled 5507 * @IWM_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs 5508 * @IWM_STA_FLG_DRAIN_FLOW: drain flow 5509 * @IWM_STA_FLG_PAN: STA is for PAN interface 5510 * @IWM_STA_FLG_CLASS_AUTH: 5511 * @IWM_STA_FLG_CLASS_ASSOC: 5512 * @IWM_STA_FLG_CLASS_MIMO_PROT: 5513 * @IWM_STA_FLG_MAX_AGG_SIZE_MSK: maximal size for A-MPDU 5514 * @IWM_STA_FLG_AGG_MPDU_DENS_MSK: maximal MPDU density for Tx aggregation 5515 * @IWM_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is 5516 * initialised by driver and can be updated by fw upon reception of 5517 * action frames that can change the channel width. When cleared the fw 5518 * will send all the frames in 20MHz even when FAT channel is requested. 5519 * @IWM_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the 5520 * driver and can be updated by fw upon reception of action frames. 5521 * @IWM_STA_FLG_MFP_EN: Management Frame Protection 5522 */ 5523 enum iwm_sta_flags { 5524 IWM_STA_FLG_REDUCED_TX_PWR_CTRL = (1 << 3), 5525 IWM_STA_FLG_REDUCED_TX_PWR_DATA = (1 << 6), 5526 5527 IWM_STA_FLG_DISABLE_TX = (1 << 4), 5528 5529 IWM_STA_FLG_PS = (1 << 8), 5530 IWM_STA_FLG_DRAIN_FLOW = (1 << 12), 5531 IWM_STA_FLG_PAN = (1 << 13), 5532 IWM_STA_FLG_CLASS_AUTH = (1 << 14), 5533 IWM_STA_FLG_CLASS_ASSOC = (1 << 15), 5534 IWM_STA_FLG_RTS_MIMO_PROT = (1 << 17), 5535 5536 IWM_STA_FLG_MAX_AGG_SIZE_SHIFT = 19, 5537 IWM_STA_FLG_MAX_AGG_SIZE_8K = (0 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5538 IWM_STA_FLG_MAX_AGG_SIZE_16K = (1 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5539 IWM_STA_FLG_MAX_AGG_SIZE_32K = (2 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5540 IWM_STA_FLG_MAX_AGG_SIZE_64K = (3 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5541 IWM_STA_FLG_MAX_AGG_SIZE_128K = (4 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5542 IWM_STA_FLG_MAX_AGG_SIZE_256K = (5 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5543 IWM_STA_FLG_MAX_AGG_SIZE_512K = (6 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5544 IWM_STA_FLG_MAX_AGG_SIZE_1024K = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5545 IWM_STA_FLG_MAX_AGG_SIZE_MSK = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5546 5547 IWM_STA_FLG_AGG_MPDU_DENS_SHIFT = 23, 5548 IWM_STA_FLG_AGG_MPDU_DENS_2US = (4 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5549 IWM_STA_FLG_AGG_MPDU_DENS_4US = (5 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5550 IWM_STA_FLG_AGG_MPDU_DENS_8US = (6 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5551 IWM_STA_FLG_AGG_MPDU_DENS_16US = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5552 IWM_STA_FLG_AGG_MPDU_DENS_MSK = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5553 5554 IWM_STA_FLG_FAT_EN_20MHZ = (0 << 26), 5555 IWM_STA_FLG_FAT_EN_40MHZ = (1 << 26), 5556 IWM_STA_FLG_FAT_EN_80MHZ = (2 << 26), 5557 IWM_STA_FLG_FAT_EN_160MHZ = (3 << 26), 5558 IWM_STA_FLG_FAT_EN_MSK = (3 << 26), 5559 5560 IWM_STA_FLG_MIMO_EN_SISO = (0 << 28), 5561 IWM_STA_FLG_MIMO_EN_MIMO2 = (1 << 28), 5562 IWM_STA_FLG_MIMO_EN_MIMO3 = (2 << 28), 5563 IWM_STA_FLG_MIMO_EN_MSK = (3 << 28), 5564 }; 5565 5566 /** 5567 * enum iwm_sta_key_flag - key flags for the ADD_STA host command 5568 * @IWM_STA_KEY_FLG_NO_ENC: no encryption 5569 * @IWM_STA_KEY_FLG_WEP: WEP encryption algorithm 5570 * @IWM_STA_KEY_FLG_CCM: CCMP encryption algorithm 5571 * @IWM_STA_KEY_FLG_TKIP: TKIP encryption algorithm 5572 * @IWM_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support) 5573 * @IWM_STA_KEY_FLG_CMAC: CMAC encryption algorithm 5574 * @IWM_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm 5575 * @IWM_STA_KEY_FLG_EN_MSK: mask for encryption algorithmi value 5576 * @IWM_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from 5577 * station info array (1 - n 1X mode) 5578 * @IWM_STA_KEY_FLG_KEYID_MSK: the index of the key 5579 * @IWM_STA_KEY_NOT_VALID: key is invalid 5580 * @IWM_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key 5581 * @IWM_STA_KEY_MULTICAST: set for multical key 5582 * @IWM_STA_KEY_MFP: key is used for Management Frame Protection 5583 */ 5584 enum iwm_sta_key_flag { 5585 IWM_STA_KEY_FLG_NO_ENC = (0 << 0), 5586 IWM_STA_KEY_FLG_WEP = (1 << 0), 5587 IWM_STA_KEY_FLG_CCM = (2 << 0), 5588 IWM_STA_KEY_FLG_TKIP = (3 << 0), 5589 IWM_STA_KEY_FLG_EXT = (4 << 0), 5590 IWM_STA_KEY_FLG_CMAC = (6 << 0), 5591 IWM_STA_KEY_FLG_ENC_UNKNOWN = (7 << 0), 5592 IWM_STA_KEY_FLG_EN_MSK = (7 << 0), 5593 5594 IWM_STA_KEY_FLG_WEP_KEY_MAP = (1 << 3), 5595 IWM_STA_KEY_FLG_KEYID_POS = 8, 5596 IWM_STA_KEY_FLG_KEYID_MSK = (3 << IWM_STA_KEY_FLG_KEYID_POS), 5597 IWM_STA_KEY_NOT_VALID = (1 << 11), 5598 IWM_STA_KEY_FLG_WEP_13BYTES = (1 << 12), 5599 IWM_STA_KEY_MULTICAST = (1 << 14), 5600 IWM_STA_KEY_MFP = (1 << 15), 5601 }; 5602 5603 /** 5604 * enum iwm_sta_modify_flag - indicate to the fw what flag are being changed 5605 * @IWM_STA_MODIFY_QUEUE_REMOVAL: this command removes a queue 5606 * @IWM_STA_MODIFY_TID_DISABLE_TX: this command modifies %tid_disable_tx 5607 * @IWM_STA_MODIFY_TX_RATE: unused 5608 * @IWM_STA_MODIFY_ADD_BA_TID: this command modifies %add_immediate_ba_tid 5609 * @IWM_STA_MODIFY_REMOVE_BA_TID: this command modifies %remove_immediate_ba_tid 5610 * @IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies %sleep_tx_count 5611 * @IWM_STA_MODIFY_PROT_TH: 5612 * @IWM_STA_MODIFY_QUEUES: modify the queues used by this station 5613 */ 5614 enum iwm_sta_modify_flag { 5615 IWM_STA_MODIFY_QUEUE_REMOVAL = (1 << 0), 5616 IWM_STA_MODIFY_TID_DISABLE_TX = (1 << 1), 5617 IWM_STA_MODIFY_TX_RATE = (1 << 2), 5618 IWM_STA_MODIFY_ADD_BA_TID = (1 << 3), 5619 IWM_STA_MODIFY_REMOVE_BA_TID = (1 << 4), 5620 IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT = (1 << 5), 5621 IWM_STA_MODIFY_PROT_TH = (1 << 6), 5622 IWM_STA_MODIFY_QUEUES = (1 << 7), 5623 }; 5624 5625 #define IWM_STA_MODE_MODIFY 1 5626 5627 /** 5628 * enum iwm_sta_sleep_flag - type of sleep of the station 5629 * @IWM_STA_SLEEP_STATE_AWAKE: 5630 * @IWM_STA_SLEEP_STATE_PS_POLL: 5631 * @IWM_STA_SLEEP_STATE_UAPSD: 5632 * @IWM_STA_SLEEP_STATE_MOREDATA: set more-data bit on 5633 * (last) released frame 5634 */ 5635 enum iwm_sta_sleep_flag { 5636 IWM_STA_SLEEP_STATE_AWAKE = 0, 5637 IWM_STA_SLEEP_STATE_PS_POLL = (1 << 0), 5638 IWM_STA_SLEEP_STATE_UAPSD = (1 << 1), 5639 IWM_STA_SLEEP_STATE_MOREDATA = (1 << 2), 5640 }; 5641 5642 /* STA ID and color bits definitions */ 5643 #define IWM_STA_ID_SEED (0x0f) 5644 #define IWM_STA_ID_POS (0) 5645 #define IWM_STA_ID_MSK (IWM_STA_ID_SEED << IWM_STA_ID_POS) 5646 5647 #define IWM_STA_COLOR_SEED (0x7) 5648 #define IWM_STA_COLOR_POS (4) 5649 #define IWM_STA_COLOR_MSK (IWM_STA_COLOR_SEED << IWM_STA_COLOR_POS) 5650 5651 #define IWM_STA_ID_N_COLOR_GET_COLOR(id_n_color) \ 5652 (((id_n_color) & IWM_STA_COLOR_MSK) >> IWM_STA_COLOR_POS) 5653 #define IWM_STA_ID_N_COLOR_GET_ID(id_n_color) \ 5654 (((id_n_color) & IWM_STA_ID_MSK) >> IWM_STA_ID_POS) 5655 5656 #define IWM_STA_KEY_MAX_NUM (16) 5657 #define IWM_STA_KEY_IDX_INVALID (0xff) 5658 #define IWM_STA_KEY_MAX_DATA_KEY_NUM (4) 5659 #define IWM_MAX_GLOBAL_KEYS (4) 5660 #define IWM_STA_KEY_LEN_WEP40 (5) 5661 #define IWM_STA_KEY_LEN_WEP104 (13) 5662 5663 /** 5664 * struct iwm_mvm_keyinfo - key information 5665 * @key_flags: type %iwm_sta_key_flag 5666 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 5667 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 5668 * @key_offset: key offset in the fw's key table 5669 * @key: 16-byte unicast decryption key 5670 * @tx_secur_seq_cnt: initial RSC / PN needed for replay check 5671 * @hw_tkip_mic_rx_key: byte: MIC Rx Key - used for TKIP only 5672 * @hw_tkip_mic_tx_key: byte: MIC Tx Key - used for TKIP only 5673 */ 5674 struct iwm_mvm_keyinfo { 5675 uint16_t key_flags; 5676 uint8_t tkip_rx_tsc_byte2; 5677 uint8_t reserved1; 5678 uint16_t tkip_rx_ttak[5]; 5679 uint8_t key_offset; 5680 uint8_t reserved2; 5681 uint8_t key[16]; 5682 uint64_t tx_secur_seq_cnt; 5683 uint64_t hw_tkip_mic_rx_key; 5684 uint64_t hw_tkip_mic_tx_key; 5685 } __packed; 5686 5687 #define IWM_ADD_STA_STATUS_MASK 0xFF 5688 #define IWM_ADD_STA_BAID_VALID_MASK 0x8000 5689 #define IWM_ADD_STA_BAID_MASK 0x7F00 5690 #define IWM_ADD_STA_BAID_SHIFT 8 5691 5692 /** 5693 * struct iwm_mvm_add_sta_cmd_v7 - Add/modify a station in the fw's sta table. 5694 * ( REPLY_ADD_STA = 0x18 ) 5695 * @add_modify: 1: modify existing, 0: add new station 5696 * @awake_acs: 5697 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable 5698 * AMPDU for tid x. Set %IWM_STA_MODIFY_TID_DISABLE_TX to change this field. 5699 * @mac_id_n_color: the Mac context this station belongs to 5700 * @addr[IEEE80211_ADDR_LEN]: station's MAC address 5701 * @sta_id: index of station in uCode's station table 5702 * @modify_mask: IWM_STA_MODIFY_*, selects which parameters to modify vs. leave 5703 * alone. 1 - modify, 0 - don't change. 5704 * @station_flags: look at %iwm_sta_flags 5705 * @station_flags_msk: what of %station_flags have changed 5706 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx) 5707 * Set %IWM_STA_MODIFY_ADD_BA_TID to use this field, and also set 5708 * add_immediate_ba_ssn. 5709 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx) 5710 * Set %IWM_STA_MODIFY_REMOVE_BA_TID to use this field 5711 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with 5712 * add_immediate_ba_tid. 5713 * @sleep_tx_count: number of packets to transmit to station even though it is 5714 * asleep. Used to synchronise PS-poll and u-APSD responses while ucode 5715 * keeps track of STA sleep state. 5716 * @sleep_state_flags: Look at %iwm_sta_sleep_flag. 5717 * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP 5718 * mac-addr. 5719 * @beamform_flags: beam forming controls 5720 * @tfd_queue_msk: tfd queues used by this station 5721 * 5722 * The device contains an internal table of per-station information, with info 5723 * on security keys, aggregation parameters, and Tx rates for initial Tx 5724 * attempt and any retries (set by IWM_REPLY_TX_LINK_QUALITY_CMD). 5725 * 5726 * ADD_STA sets up the table entry for one station, either creating a new 5727 * entry, or modifying a pre-existing one. 5728 */ 5729 struct iwm_mvm_add_sta_cmd_v7 { 5730 uint8_t add_modify; 5731 uint8_t awake_acs; 5732 uint16_t tid_disable_tx; 5733 uint32_t mac_id_n_color; 5734 uint8_t addr[IEEE80211_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */ 5735 uint16_t reserved2; 5736 uint8_t sta_id; 5737 uint8_t modify_mask; 5738 uint16_t reserved3; 5739 uint32_t station_flags; 5740 uint32_t station_flags_msk; 5741 uint8_t add_immediate_ba_tid; 5742 uint8_t remove_immediate_ba_tid; 5743 uint16_t add_immediate_ba_ssn; 5744 uint16_t sleep_tx_count; 5745 uint16_t sleep_state_flags; 5746 uint16_t assoc_id; 5747 uint16_t beamform_flags; 5748 uint32_t tfd_queue_msk; 5749 } __packed; /* ADD_STA_CMD_API_S_VER_7 */ 5750 5751 /** 5752 * struct iwm_mvm_add_sta_key_cmd - add/modify sta key 5753 * ( IWM_REPLY_ADD_STA_KEY = 0x17 ) 5754 * @sta_id: index of station in uCode's station table 5755 * @key_offset: key offset in key storage 5756 * @key_flags: type %iwm_sta_key_flag 5757 * @key: key material data 5758 * @key2: key material data 5759 * @rx_secur_seq_cnt: RX security sequence counter for the key 5760 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 5761 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 5762 */ 5763 struct iwm_mvm_add_sta_key_cmd { 5764 uint8_t sta_id; 5765 uint8_t key_offset; 5766 uint16_t key_flags; 5767 uint8_t key[16]; 5768 uint8_t key2[16]; 5769 uint8_t rx_secur_seq_cnt[16]; 5770 uint8_t tkip_rx_tsc_byte2; 5771 uint8_t reserved; 5772 uint16_t tkip_rx_ttak[5]; 5773 } __packed; /* IWM_ADD_MODIFY_STA_KEY_API_S_VER_1 */ 5774 5775 /** 5776 * enum iwm_mvm_add_sta_rsp_status - status in the response to ADD_STA command 5777 * @IWM_ADD_STA_SUCCESS: operation was executed successfully 5778 * @IWM_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table 5779 * @IWM_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session 5780 * @IWM_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station 5781 * that doesn't exist. 5782 */ 5783 enum iwm_mvm_add_sta_rsp_status { 5784 IWM_ADD_STA_SUCCESS = 0x1, 5785 IWM_ADD_STA_STATIONS_OVERLOAD = 0x2, 5786 IWM_ADD_STA_IMMEDIATE_BA_FAILURE = 0x4, 5787 IWM_ADD_STA_MODIFY_NON_EXISTING_STA = 0x8, 5788 }; 5789 5790 /** 5791 * struct iwm_mvm_rm_sta_cmd - Add / modify a station in the fw's station table 5792 * ( IWM_REMOVE_STA = 0x19 ) 5793 * @sta_id: the station id of the station to be removed 5794 */ 5795 struct iwm_mvm_rm_sta_cmd { 5796 uint8_t sta_id; 5797 uint8_t reserved[3]; 5798 } __packed; /* IWM_REMOVE_STA_CMD_API_S_VER_2 */ 5799 5800 /** 5801 * struct iwm_mvm_mgmt_mcast_key_cmd 5802 * ( IWM_MGMT_MCAST_KEY = 0x1f ) 5803 * @ctrl_flags: %iwm_sta_key_flag 5804 * @IGTK: 5805 * @K1: IGTK master key 5806 * @K2: IGTK sub key 5807 * @sta_id: station ID that support IGTK 5808 * @key_id: 5809 * @receive_seq_cnt: initial RSC/PN needed for replay check 5810 */ 5811 struct iwm_mvm_mgmt_mcast_key_cmd { 5812 uint32_t ctrl_flags; 5813 uint8_t IGTK[16]; 5814 uint8_t K1[16]; 5815 uint8_t K2[16]; 5816 uint32_t key_id; 5817 uint32_t sta_id; 5818 uint64_t receive_seq_cnt; 5819 } __packed; /* SEC_MGMT_MULTICAST_KEY_CMD_API_S_VER_1 */ 5820 5821 struct iwm_mvm_wep_key { 5822 uint8_t key_index; 5823 uint8_t key_offset; 5824 uint16_t reserved1; 5825 uint8_t key_size; 5826 uint8_t reserved2[3]; 5827 uint8_t key[16]; 5828 } __packed; 5829 5830 struct iwm_mvm_wep_key_cmd { 5831 uint32_t mac_id_n_color; 5832 uint8_t num_keys; 5833 uint8_t decryption_type; 5834 uint8_t flags; 5835 uint8_t reserved; 5836 struct iwm_mvm_wep_key wep_key[0]; 5837 } __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */ 5838 5839 /* 5840 * END mvm/fw-api-sta.h 5841 */ 5842 5843 /* 5844 * BT coex 5845 */ 5846 5847 enum iwm_bt_coex_mode { 5848 IWM_BT_COEX_DISABLE = 0x0, 5849 IWM_BT_COEX_NW = 0x1, 5850 IWM_BT_COEX_BT = 0x2, 5851 IWM_BT_COEX_WIFI = 0x3, 5852 }; /* BT_COEX_MODES_E */ 5853 5854 enum iwm_bt_coex_enabled_modules { 5855 IWM_BT_COEX_MPLUT_ENABLED = (1 << 0), 5856 IWM_BT_COEX_MPLUT_BOOST_ENABLED = (1 << 1), 5857 IWM_BT_COEX_SYNC2SCO_ENABLED = (1 << 2), 5858 IWM_BT_COEX_CORUN_ENABLED = (1 << 3), 5859 IWM_BT_COEX_HIGH_BAND_RET = (1 << 4), 5860 }; /* BT_COEX_MODULES_ENABLE_E_VER_1 */ 5861 5862 /** 5863 * struct iwm_bt_coex_cmd - bt coex configuration command 5864 * @mode: enum %iwm_bt_coex_mode 5865 * @enabled_modules: enum %iwm_bt_coex_enabled_modules 5866 * 5867 * The structure is used for the BT_COEX command. 5868 */ 5869 struct iwm_bt_coex_cmd { 5870 uint32_t mode; 5871 uint32_t enabled_modules; 5872 } __packed; /* BT_COEX_CMD_API_S_VER_6 */ 5873 5874 5875 /* 5876 * Location Aware Regulatory (LAR) API - MCC updates 5877 */ 5878 5879 /** 5880 * struct iwm_mcc_update_cmd_v1 - Request the device to update geographic 5881 * regulatory profile according to the given MCC (Mobile Country Code). 5882 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5883 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5884 * MCC in the cmd response will be the relevant MCC in the NVM. 5885 * @mcc: given mobile country code 5886 * @source_id: the source from where we got the MCC, see iwm_mcc_source 5887 * @reserved: reserved for alignment 5888 */ 5889 struct iwm_mcc_update_cmd_v1 { 5890 uint16_t mcc; 5891 uint8_t source_id; 5892 uint8_t reserved; 5893 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_1 */ 5894 5895 /** 5896 * struct iwm_mcc_update_cmd - Request the device to update geographic 5897 * regulatory profile according to the given MCC (Mobile Country Code). 5898 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5899 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5900 * MCC in the cmd response will be the relevant MCC in the NVM. 5901 * @mcc: given mobile country code 5902 * @source_id: the source from where we got the MCC, see iwm_mcc_source 5903 * @reserved: reserved for alignment 5904 * @key: integrity key for MCC API OEM testing 5905 * @reserved2: reserved 5906 */ 5907 struct iwm_mcc_update_cmd { 5908 uint16_t mcc; 5909 uint8_t source_id; 5910 uint8_t reserved; 5911 uint32_t key; 5912 uint32_t reserved2[5]; 5913 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_2 */ 5914 5915 /** 5916 * iwm_mcc_update_resp_v1 - response to MCC_UPDATE_CMD. 5917 * Contains the new channel control profile map, if changed, and the new MCC 5918 * (mobile country code). 5919 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 5920 * @status: see &enum iwm_mcc_update_status 5921 * @mcc: the new applied MCC 5922 * @cap: capabilities for all channels which matches the MCC 5923 * @source_id: the MCC source, see iwm_mcc_source 5924 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 5925 * channels, depending on platform) 5926 * @channels: channel control data map, DWORD for each channel. Only the first 5927 * 16bits are used. 5928 */ 5929 struct iwm_mcc_update_resp_v1 { 5930 uint32_t status; 5931 uint16_t mcc; 5932 uint8_t cap; 5933 uint8_t source_id; 5934 uint32_t n_channels; 5935 uint32_t channels[0]; 5936 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_1 */ 5937 5938 /** 5939 * iwm_mcc_update_resp - response to MCC_UPDATE_CMD. 5940 * Contains the new channel control profile map, if changed, and the new MCC 5941 * (mobile country code). 5942 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 5943 * @status: see &enum iwm_mcc_update_status 5944 * @mcc: the new applied MCC 5945 * @cap: capabilities for all channels which matches the MCC 5946 * @source_id: the MCC source, see iwm_mcc_source 5947 * @time: time elapsed from the MCC test start (in 30 seconds TU) 5948 * @reserved: reserved. 5949 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 5950 * channels, depending on platform) 5951 * @channels: channel control data map, DWORD for each channel. Only the first 5952 * 16bits are used. 5953 */ 5954 struct iwm_mcc_update_resp { 5955 uint32_t status; 5956 uint16_t mcc; 5957 uint8_t cap; 5958 uint8_t source_id; 5959 uint16_t time; 5960 uint16_t reserved; 5961 uint32_t n_channels; 5962 uint32_t channels[0]; 5963 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_2 */ 5964 5965 /** 5966 * struct iwm_mcc_chub_notif - chub notifies of mcc change 5967 * (MCC_CHUB_UPDATE_CMD = 0xc9) 5968 * The Chub (Communication Hub, CommsHUB) is a HW component that connects to 5969 * the cellular and connectivity cores that gets updates of the mcc, and 5970 * notifies the ucode directly of any mcc change. 5971 * The ucode requests the driver to request the device to update geographic 5972 * regulatory profile according to the given MCC (Mobile Country Code). 5973 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5974 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5975 * MCC in the cmd response will be the relevant MCC in the NVM. 5976 * @mcc: given mobile country code 5977 * @source_id: identity of the change originator, see iwm_mcc_source 5978 * @reserved1: reserved for alignment 5979 */ 5980 struct iwm_mcc_chub_notif { 5981 uint16_t mcc; 5982 uint8_t source_id; 5983 uint8_t reserved1; 5984 } __packed; /* LAR_MCC_NOTIFY_S */ 5985 5986 enum iwm_mcc_update_status { 5987 IWM_MCC_RESP_NEW_CHAN_PROFILE, 5988 IWM_MCC_RESP_SAME_CHAN_PROFILE, 5989 IWM_MCC_RESP_INVALID, 5990 IWM_MCC_RESP_NVM_DISABLED, 5991 IWM_MCC_RESP_ILLEGAL, 5992 IWM_MCC_RESP_LOW_PRIORITY, 5993 IWM_MCC_RESP_TEST_MODE_ACTIVE, 5994 IWM_MCC_RESP_TEST_MODE_NOT_ACTIVE, 5995 IWM_MCC_RESP_TEST_MODE_DENIAL_OF_SERVICE, 5996 }; 5997 5998 enum iwm_mcc_source { 5999 IWM_MCC_SOURCE_OLD_FW = 0, 6000 IWM_MCC_SOURCE_ME = 1, 6001 IWM_MCC_SOURCE_BIOS = 2, 6002 IWM_MCC_SOURCE_3G_LTE_HOST = 3, 6003 IWM_MCC_SOURCE_3G_LTE_DEVICE = 4, 6004 IWM_MCC_SOURCE_WIFI = 5, 6005 IWM_MCC_SOURCE_RESERVED = 6, 6006 IWM_MCC_SOURCE_DEFAULT = 7, 6007 IWM_MCC_SOURCE_UNINITIALIZED = 8, 6008 IWM_MCC_SOURCE_MCC_API = 9, 6009 IWM_MCC_SOURCE_GET_CURRENT = 0x10, 6010 IWM_MCC_SOURCE_GETTING_MCC_TEST_MODE = 0x11, 6011 }; 6012 6013 /** 6014 * struct iwm_dts_measurement_notif_v1 - measurements notification 6015 * 6016 * @temp: the measured temperature 6017 * @voltage: the measured voltage 6018 */ 6019 struct iwm_dts_measurement_notif_v1 { 6020 int32_t temp; 6021 int32_t voltage; 6022 } __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_NTFY_S_VER_1*/ 6023 6024 /** 6025 * struct iwm_dts_measurement_notif_v2 - measurements notification 6026 * 6027 * @temp: the measured temperature 6028 * @voltage: the measured voltage 6029 * @threshold_idx: the trip index that was crossed 6030 */ 6031 struct iwm_dts_measurement_notif_v2 { 6032 int32_t temp; 6033 int32_t voltage; 6034 int32_t threshold_idx; 6035 } __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_NTFY_S_VER_2 */ 6036 6037 /* 6038 * Some cherry-picked definitions 6039 */ 6040 6041 #define IWM_FRAME_LIMIT 64 6042 6043 /* 6044 * From Linux commit ab02165ccec4c78162501acedeef1a768acdb811: 6045 * As the firmware is slowly running out of command IDs and grouping of 6046 * commands is desirable anyway, the firmware is extending the command 6047 * header from 4 bytes to 8 bytes to introduce a group (in place of the 6048 * former flags field, since that's always 0 on commands and thus can 6049 * be easily used to distinguish between the two). 6050 * 6051 * These functions retrieve specific information from the id field in 6052 * the iwm_host_cmd struct which contains the command id, the group id, 6053 * and the version of the command. 6054 */ 6055 static inline uint8_t 6056 iwm_cmd_opcode(uint32_t cmdid) 6057 { 6058 return cmdid & 0xff; 6059 } 6060 6061 static inline uint8_t 6062 iwm_cmd_groupid(uint32_t cmdid) 6063 { 6064 return ((cmdid & 0Xff00) >> 8); 6065 } 6066 6067 static inline uint8_t 6068 iwm_cmd_version(uint32_t cmdid) 6069 { 6070 return ((cmdid & 0xff0000) >> 16); 6071 } 6072 6073 static inline uint32_t 6074 iwm_cmd_id(uint8_t opcode, uint8_t groupid, uint8_t version) 6075 { 6076 return opcode + (groupid << 8) + (version << 16); 6077 } 6078 6079 /* make uint16_t wide id out of uint8_t group and opcode */ 6080 #define IWM_WIDE_ID(grp, opcode) ((grp << 8) | opcode) 6081 6082 /* due to the conversion, this group is special */ 6083 #define IWM_ALWAYS_LONG_GROUP 1 6084 6085 struct iwm_cmd_header { 6086 uint8_t code; 6087 uint8_t flags; 6088 uint8_t idx; 6089 uint8_t qid; 6090 } __packed; 6091 6092 struct iwm_cmd_header_wide { 6093 uint8_t opcode; 6094 uint8_t group_id; 6095 uint8_t idx; 6096 uint8_t qid; 6097 uint16_t length; 6098 uint8_t reserved; 6099 uint8_t version; 6100 } __packed; 6101 6102 enum iwm_power_scheme { 6103 IWM_POWER_SCHEME_CAM = 1, 6104 IWM_POWER_SCHEME_BPS, 6105 IWM_POWER_SCHEME_LP 6106 }; 6107 6108 #define IWM_DEF_CMD_PAYLOAD_SIZE 320 6109 #define IWM_MAX_CMD_PAYLOAD_SIZE ((4096 - 4) - sizeof(struct iwm_cmd_header)) 6110 #define IWM_CMD_FAILED_MSK 0x40 6111 6112 /** 6113 * struct iwm_device_cmd 6114 * 6115 * For allocation of the command and tx queues, this establishes the overall 6116 * size of the largest command we send to uCode, except for commands that 6117 * aren't fully copied and use other TFD space. 6118 */ 6119 struct iwm_device_cmd { 6120 union { 6121 struct { 6122 struct iwm_cmd_header hdr; 6123 uint8_t data[IWM_DEF_CMD_PAYLOAD_SIZE]; 6124 }; 6125 struct { 6126 struct iwm_cmd_header_wide hdr_wide; 6127 uint8_t data_wide[IWM_DEF_CMD_PAYLOAD_SIZE - 6128 sizeof(struct iwm_cmd_header_wide) + 6129 sizeof(struct iwm_cmd_header)]; 6130 }; 6131 }; 6132 } __packed; 6133 6134 struct iwm_rx_packet { 6135 /* 6136 * The first 4 bytes of the RX frame header contain both the RX frame 6137 * size and some flags. 6138 * Bit fields: 6139 * 31: flag flush RB request 6140 * 30: flag ignore TC (terminal counter) request 6141 * 29: flag fast IRQ request 6142 * 28-14: Reserved 6143 * 13-00: RX frame size 6144 */ 6145 uint32_t len_n_flags; 6146 struct iwm_cmd_header hdr; 6147 uint8_t data[]; 6148 } __packed; 6149 6150 #define IWM_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff 6151 6152 static inline uint32_t 6153 iwm_rx_packet_len(const struct iwm_rx_packet *pkt) 6154 { 6155 6156 return le32toh(pkt->len_n_flags) & IWM_FH_RSCSR_FRAME_SIZE_MSK; 6157 } 6158 6159 static inline uint32_t 6160 iwm_rx_packet_payload_len(const struct iwm_rx_packet *pkt) 6161 { 6162 6163 return iwm_rx_packet_len(pkt) - sizeof(pkt->hdr); 6164 } 6165 6166 6167 #define IWM_MIN_DBM -100 6168 #define IWM_MAX_DBM -33 /* realistic guess */ 6169 6170 #define IWM_READ(sc, reg) \ 6171 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 6172 6173 #define IWM_WRITE(sc, reg, val) \ 6174 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6175 6176 #define IWM_WRITE_1(sc, reg, val) \ 6177 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6178 6179 #define IWM_SETBITS(sc, reg, mask) \ 6180 IWM_WRITE(sc, reg, IWM_READ(sc, reg) | (mask)) 6181 6182 #define IWM_CLRBITS(sc, reg, mask) \ 6183 IWM_WRITE(sc, reg, IWM_READ(sc, reg) & ~(mask)) 6184 6185 #define IWM_BARRIER_WRITE(sc) \ 6186 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6187 BUS_SPACE_BARRIER_WRITE) 6188 6189 #define IWM_BARRIER_READ_WRITE(sc) \ 6190 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6191 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 6192 6193 #endif /* __IF_IWM_REG_H__ */ 6194