1 /* $FreeBSD$ */ 2 /* $OpenBSD: if_iwnreg.h,v 1.40 2010/05/05 19:41:57 damien Exp $ */ 3 4 /*- 5 * Copyright (c) 2007, 2008 6 * Damien Bergamini <damien.bergamini@free.fr> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 #ifndef __IF_IWNREG_H__ 21 #define __IF_IWNREG_H__ 22 23 #define IWN_CT_KILL_THRESHOLD 114 /* in Celsius */ 24 #define IWN_CT_KILL_EXIT_THRESHOLD 95 /* in Celsius */ 25 26 #define IWN_TX_RING_COUNT 256 27 #define IWN_TX_RING_LOMARK 192 28 #define IWN_TX_RING_HIMARK 224 29 #define IWN_RX_RING_COUNT_LOG 6 30 #define IWN_RX_RING_COUNT (1 << IWN_RX_RING_COUNT_LOG) 31 32 #define IWN4965_NTXQUEUES 16 33 #define IWN5000_NTXQUEUES 20 34 35 #define IWN4965_FIRSTAGGQUEUE 7 36 #define IWN5000_FIRSTAGGQUEUE 10 37 38 #define IWN4965_NDMACHNLS 7 39 #define IWN5000_NDMACHNLS 8 40 41 #define IWN_SRVC_DMACHNL 9 42 43 #define IWN_ICT_SIZE 4096 44 #define IWN_ICT_COUNT (IWN_ICT_SIZE / sizeof (uint32_t)) 45 46 /* For cards with PAN command, default is IWN_CMD_QUEUE_NUM */ 47 #define IWN_CMD_QUEUE_NUM 4 48 #define IWN_PAN_CMD_QUEUE 9 49 50 /* Maximum number of DMA segments for TX. */ 51 #define IWN_MAX_SCATTER 20 52 53 /* RX buffers must be large enough to hold a full 4K A-MPDU. */ 54 #define IWN_RBUF_SIZE (4 * 1024) 55 56 #if defined(__LP64__) 57 /* HW supports 36-bit DMA addresses. */ 58 #define IWN_LOADDR(paddr) ((uint32_t)(paddr)) 59 #define IWN_HIADDR(paddr) (((paddr) >> 32) & 0xf) 60 #else 61 #define IWN_LOADDR(paddr) (paddr) 62 #define IWN_HIADDR(paddr) (0) 63 #endif 64 65 /* 66 * Control and status registers. 67 */ 68 #define IWN_HW_IF_CONFIG 0x000 69 #define IWN_INT_COALESCING 0x004 70 #define IWN_INT_PERIODIC 0x005 /* use IWN_WRITE_1 */ 71 #define IWN_INT 0x008 72 #define IWN_INT_MASK 0x00c 73 #define IWN_FH_INT 0x010 74 #define IWN_GPIO_IN 0x018 /* read external chip pins */ 75 #define IWN_RESET 0x020 76 #define IWN_GP_CNTRL 0x024 77 #define IWN_HW_REV 0x028 78 #define IWN_EEPROM 0x02c 79 #define IWN_EEPROM_GP 0x030 80 #define IWN_OTP_GP 0x034 81 #define IWN_GIO 0x03c 82 #define IWN_GP_UCODE 0x048 83 #define IWN_GP_DRIVER 0x050 84 #define IWN_UCODE_GP1 0x054 85 #define IWN_UCODE_GP1_SET 0x058 86 #define IWN_UCODE_GP1_CLR 0x05c 87 #define IWN_UCODE_GP2 0x060 88 #define IWN_LED 0x094 89 #define IWN_DRAM_INT_TBL 0x0a0 90 #define IWN_SHADOW_REG_CTRL 0x0a8 91 #define IWN_GIO_CHICKEN 0x100 92 #define IWN_ANA_PLL 0x20c 93 #define IWN_HW_REV_WA 0x22c 94 #define IWN_DBG_HPET_MEM 0x240 95 #define IWN_DBG_LINK_PWR_MGMT 0x250 96 /* Need nic_lock for use above */ 97 #define IWN_MEM_RADDR 0x40c 98 #define IWN_MEM_WADDR 0x410 99 #define IWN_MEM_WDATA 0x418 100 #define IWN_MEM_RDATA 0x41c 101 #define IWN_TARG_MBX_C 0x430 102 #define IWN_PRPH_WADDR 0x444 103 #define IWN_PRPH_RADDR 0x448 104 #define IWN_PRPH_WDATA 0x44c 105 #define IWN_PRPH_RDATA 0x450 106 #define IWN_HBUS_TARG_WRPTR 0x460 107 108 /* 109 * Flow-Handler registers. 110 */ 111 #define IWN_FH_TFBD_CTRL0(qid) (0x1900 + (qid) * 8) 112 #define IWN_FH_TFBD_CTRL1(qid) (0x1904 + (qid) * 8) 113 #define IWN_FH_KW_ADDR 0x197c 114 #define IWN_FH_SRAM_ADDR(qid) (0x19a4 + (qid) * 4) 115 #define IWN_FH_CBBC_QUEUE(qid) (0x19d0 + (qid) * 4) 116 #define IWN_FH_STATUS_WPTR 0x1bc0 117 #define IWN_FH_RX_BASE 0x1bc4 118 #define IWN_FH_RX_WPTR 0x1bc8 119 #define IWN_FH_RX_CONFIG 0x1c00 120 #define IWN_FH_RX_STATUS 0x1c44 121 #define IWN_FH_TX_CONFIG(qid) (0x1d00 + (qid) * 32) 122 #define IWN_FH_TXBUF_STATUS(qid) (0x1d08 + (qid) * 32) 123 #define IWN_FH_TX_CHICKEN 0x1e98 124 #define IWN_FH_TX_STATUS 0x1eb0 125 126 /* 127 * TX scheduler registers. 128 */ 129 #define IWN_SCHED_BASE 0xa02c00 130 #define IWN_SCHED_SRAM_ADDR (IWN_SCHED_BASE + 0x000) 131 #define IWN5000_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x008) 132 #define IWN4965_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x010) 133 #define IWN5000_SCHED_TXFACT (IWN_SCHED_BASE + 0x010) 134 #define IWN4965_SCHED_TXFACT (IWN_SCHED_BASE + 0x01c) 135 #define IWN4965_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x064 + (qid) * 4) 136 #define IWN5000_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x068 + (qid) * 4) 137 #define IWN4965_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0d0) 138 #define IWN4965_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x0e4) 139 #define IWN5000_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0e8) 140 #define IWN4965_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x104 + (qid) * 4) 141 #define IWN5000_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x108) 142 #define IWN5000_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x10c + (qid) * 4) 143 #define IWN5000_SCHED_AGGR_SEL (IWN_SCHED_BASE + 0x248) 144 145 /* 146 * Offsets in TX scheduler's SRAM. 147 */ 148 #define IWN4965_SCHED_CTX_OFF 0x380 149 #define IWN4965_SCHED_CTX_LEN 416 150 #define IWN4965_SCHED_QUEUE_OFFSET(qid) (0x380 + (qid) * 8) 151 #define IWN4965_SCHED_TRANS_TBL(qid) (0x500 + (qid) * 2) 152 #define IWN5000_SCHED_CTX_OFF 0x600 153 #define IWN5000_SCHED_CTX_LEN 520 154 #define IWN5000_SCHED_QUEUE_OFFSET(qid) (0x600 + (qid) * 8) 155 #define IWN5000_SCHED_TRANS_TBL(qid) (0x7e0 + (qid) * 2) 156 157 /* 158 * NIC internal memory offsets. 159 */ 160 #define IWN_APMG_CLK_CTRL 0x3000 161 #define IWN_APMG_CLK_EN 0x3004 162 #define IWN_APMG_CLK_DIS 0x3008 163 #define IWN_APMG_PS 0x300c 164 #define IWN_APMG_DIGITAL_SVR 0x3058 165 #define IWN_APMG_ANALOG_SVR 0x306c 166 #define IWN_APMG_PCI_STT 0x3010 167 #define IWN_BSM_WR_CTRL 0x3400 168 #define IWN_BSM_WR_MEM_SRC 0x3404 169 #define IWN_BSM_WR_MEM_DST 0x3408 170 #define IWN_BSM_WR_DWCOUNT 0x340c 171 #define IWN_BSM_DRAM_TEXT_ADDR 0x3490 172 #define IWN_BSM_DRAM_TEXT_SIZE 0x3494 173 #define IWN_BSM_DRAM_DATA_ADDR 0x3498 174 #define IWN_BSM_DRAM_DATA_SIZE 0x349c 175 #define IWN_BSM_SRAM_BASE 0x3800 176 177 /* Possible flags for register IWN_HW_IF_CONFIG. */ 178 #define IWN_HW_IF_CONFIG_4965_R (1 << 4) 179 #define IWN_HW_IF_CONFIG_MAC_SI (1 << 8) 180 #define IWN_HW_IF_CONFIG_RADIO_SI (1 << 9) 181 #define IWN_HW_IF_CONFIG_EEPROM_LOCKED (1 << 21) 182 #define IWN_HW_IF_CONFIG_NIC_READY (1 << 22) 183 #define IWN_HW_IF_CONFIG_HAP_WAKE_L1A (1 << 23) 184 #define IWN_HW_IF_CONFIG_PREPARE_DONE (1 << 25) 185 #define IWN_HW_IF_CONFIG_PREPARE (1 << 27) 186 187 /* Possible values for register IWN_INT_PERIODIC. */ 188 #define IWN_INT_PERIODIC_DIS 0x00 189 #define IWN_INT_PERIODIC_ENA 0xff 190 191 /* Possible flags for registers IWN_PRPH_RADDR/IWN_PRPH_WADDR. */ 192 #define IWN_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) 193 194 /* Possible values for IWN_BSM_WR_MEM_DST. */ 195 #define IWN_FW_TEXT_BASE 0x00000000 196 #define IWN_FW_DATA_BASE 0x00800000 197 198 /* Possible flags for register IWN_RESET. */ 199 #define IWN_RESET_NEVO (1 << 0) 200 #define IWN_RESET_SW (1 << 7) 201 #define IWN_RESET_MASTER_DISABLED (1 << 8) 202 #define IWN_RESET_STOP_MASTER (1 << 9) 203 #define IWN_RESET_LINK_PWR_MGMT_DIS (1U << 31) 204 205 /* Possible flags for register IWN_GP_CNTRL. */ 206 #define IWN_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) 207 #define IWN_GP_CNTRL_MAC_CLOCK_READY (1 << 0) 208 #define IWN_GP_CNTRL_INIT_DONE (1 << 2) 209 #define IWN_GP_CNTRL_MAC_ACCESS_REQ (1 << 3) 210 #define IWN_GP_CNTRL_SLEEP (1 << 4) 211 #define IWN_GP_CNTRL_RFKILL (1 << 27) 212 213 /* Possible flags for register IWN_GIO_CHICKEN. */ 214 #define IWN_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) 215 #define IWN_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29) 216 217 /* Possible flags for register IWN_GIO. */ 218 #define IWN_GIO_L0S_ENA (1 << 1) 219 220 /* Possible flags for register IWN_GP_DRIVER. */ 221 #define IWN_GP_DRIVER_RADIO_3X3_HYB (0 << 0) 222 #define IWN_GP_DRIVER_RADIO_2X2_HYB (1 << 0) 223 #define IWN_GP_DRIVER_RADIO_2X2_IPA (2 << 0) 224 #define IWN_GP_DRIVER_CALIB_VER6 (1 << 2) 225 #define IWN_GP_DRIVER_6050_1X2 (1 << 3) 226 #define IWN_GP_DRIVER_REG_BIT_RADIO_IQ_INVERT (1 << 7) 227 #define IWN_GP_DRIVER_NONE 0 228 229 /* Possible flags for register IWN_UCODE_GP1_CLR. */ 230 #define IWN_UCODE_GP1_RFKILL (1 << 1) 231 #define IWN_UCODE_GP1_CMD_BLOCKED (1 << 2) 232 #define IWN_UCODE_GP1_CTEMP_STOP_RF (1 << 3) 233 #define IWN_UCODE_GP1_CFG_COMPLETE (1 << 5) 234 235 /* Possible flags/values for register IWN_LED. */ 236 #define IWN_LED_BSM_CTRL (1 << 5) 237 #define IWN_LED_OFF 0x00000038 238 #define IWN_LED_ON 0x00000078 239 240 #define IWN_MAX_BLINK_TBL 10 241 #define IWN_LED_STATIC_ON 0 242 #define IWN_LED_STATIC_OFF 1 243 #define IWN_LED_SLOW_BLINK 2 244 #define IWN_LED_INT_BLINK 3 245 #define IWN_LED_UNIT 0x1388 /* 5 ms */ 246 247 static const struct { 248 uint16_t tpt; /* Mb/s */ 249 uint8_t on_time; 250 uint8_t off_time; 251 } blink_tbl[] = 252 { 253 {300, 5, 5}, 254 {200, 8, 8}, 255 {100, 11, 11}, 256 {70, 13, 13}, 257 {50, 15, 15}, 258 {20, 17, 17}, 259 {10, 19, 19}, 260 {5, 22, 22}, 261 {1, 26, 26}, 262 {0, 33, 33}, 263 /* SOLID_ON */ 264 }; 265 266 /* Possible flags for register IWN_DRAM_INT_TBL. */ 267 #define IWN_DRAM_INT_TBL_WRAP_CHECK (1 << 27) 268 #define IWN_DRAM_INT_TBL_ENABLE (1U << 31) 269 270 /* Possible values for register IWN_ANA_PLL. */ 271 #define IWN_ANA_PLL_INIT 0x00880300 272 273 /* Possible flags for register IWN_FH_RX_STATUS. */ 274 #define IWN_FH_RX_STATUS_IDLE (1 << 24) 275 276 /* Possible flags for register IWN_BSM_WR_CTRL. */ 277 #define IWN_BSM_WR_CTRL_START_EN (1 << 30) 278 #define IWN_BSM_WR_CTRL_START (1U << 31) 279 280 /* Possible flags for register IWN_INT. */ 281 #define IWN_INT_ALIVE (1 << 0) 282 #define IWN_INT_WAKEUP (1 << 1) 283 #define IWN_INT_SW_RX (1 << 3) 284 #define IWN_INT_CT_REACHED (1 << 6) 285 #define IWN_INT_RF_TOGGLED (1 << 7) 286 #define IWN_INT_SW_ERR (1 << 25) 287 #define IWN_INT_SCHED (1 << 26) 288 #define IWN_INT_FH_TX (1 << 27) 289 #define IWN_INT_RX_PERIODIC (1 << 28) 290 #define IWN_INT_HW_ERR (1 << 29) 291 #define IWN_INT_FH_RX (1U << 31) 292 293 /* Shortcut. */ 294 #define IWN_INT_MASK_DEF \ 295 (IWN_INT_SW_ERR | IWN_INT_HW_ERR | IWN_INT_FH_TX | \ 296 IWN_INT_FH_RX | IWN_INT_ALIVE | IWN_INT_WAKEUP | \ 297 IWN_INT_SW_RX | IWN_INT_CT_REACHED | IWN_INT_RF_TOGGLED) 298 299 /* Possible flags for register IWN_FH_INT. */ 300 #define IWN_FH_INT_TX_CHNL(x) (1 << (x)) 301 #define IWN_FH_INT_RX_CHNL(x) (1 << ((x) + 16)) 302 #define IWN_FH_INT_HI_PRIOR (1 << 30) 303 /* Shortcuts for the above. */ 304 #define IWN_FH_INT_TX \ 305 (IWN_FH_INT_TX_CHNL(0) | IWN_FH_INT_TX_CHNL(1)) 306 #define IWN_FH_INT_RX \ 307 (IWN_FH_INT_RX_CHNL(0) | IWN_FH_INT_RX_CHNL(1) | IWN_FH_INT_HI_PRIOR) 308 309 /* Possible flags/values for register IWN_FH_TX_CONFIG. */ 310 #define IWN_FH_TX_CONFIG_DMA_PAUSE 0 311 #define IWN_FH_TX_CONFIG_DMA_ENA (1U << 31) 312 #define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD (1 << 20) 313 314 /* Possible flags/values for register IWN_FH_TXBUF_STATUS. */ 315 #define IWN_FH_TXBUF_STATUS_TBNUM(x) ((x) << 20) 316 #define IWN_FH_TXBUF_STATUS_TBIDX(x) ((x) << 12) 317 #define IWN_FH_TXBUF_STATUS_TFBD_VALID 3 318 319 /* Possible flags for register IWN_FH_TX_CHICKEN. */ 320 #define IWN_FH_TX_CHICKEN_SCHED_RETRY (1 << 1) 321 322 /* Possible flags for register IWN_FH_TX_STATUS. */ 323 #define IWN_FH_TX_STATUS_IDLE(chnl) (1 << ((chnl) + 16)) 324 325 /* Possible flags for register IWN_FH_RX_CONFIG. */ 326 #define IWN_FH_RX_CONFIG_ENA (1U << 31) 327 #define IWN_FH_RX_CONFIG_NRBD(x) ((x) << 20) 328 #define IWN_FH_RX_CONFIG_RB_SIZE_8K (1 << 16) 329 #define IWN_FH_RX_CONFIG_SINGLE_FRAME (1 << 15) 330 #define IWN_FH_RX_CONFIG_IRQ_DST_HOST (1 << 12) 331 #define IWN_FH_RX_CONFIG_RB_TIMEOUT(x) ((x) << 4) 332 #define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY (1 << 2) 333 334 /* Possible flags for register IWN_FH_TX_CONFIG. */ 335 #define IWN_FH_TX_CONFIG_DMA_ENA (1U << 31) 336 #define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA (1 << 3) 337 338 /* Possible flags for register IWN_EEPROM. */ 339 #define IWN_EEPROM_READ_VALID (1 << 0) 340 #define IWN_EEPROM_CMD (1 << 1) 341 342 /* Possible flags for register IWN_EEPROM_GP. */ 343 #define IWN_EEPROM_GP_IF_OWNER 0x00000180 344 345 /* Possible flags for register IWN_OTP_GP. */ 346 #define IWN_OTP_GP_DEV_SEL_OTP (1 << 16) 347 #define IWN_OTP_GP_RELATIVE_ACCESS (1 << 17) 348 #define IWN_OTP_GP_ECC_CORR_STTS (1 << 20) 349 #define IWN_OTP_GP_ECC_UNCORR_STTS (1 << 21) 350 351 /* Possible flags for register IWN_SCHED_QUEUE_STATUS. */ 352 #define IWN4965_TXQ_STATUS_ACTIVE 0x0007fc01 353 #define IWN4965_TXQ_STATUS_INACTIVE 0x0007fc00 354 #define IWN4965_TXQ_STATUS_AGGR_ENA (1 << 5 | 1 << 8) 355 #define IWN4965_TXQ_STATUS_CHGACT (1 << 10) 356 #define IWN5000_TXQ_STATUS_ACTIVE 0x00ff0018 357 #define IWN5000_TXQ_STATUS_INACTIVE 0x00ff0010 358 #define IWN5000_TXQ_STATUS_CHGACT (1 << 19) 359 360 /* Possible flags for registers IWN_APMG_CLK_*. */ 361 #define IWN_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9) 362 #define IWN_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11) 363 364 /* Possible flags for register IWN_APMG_PS. */ 365 #define IWN_APMG_PS_EARLY_PWROFF_DIS (1 << 22) 366 #define IWN_APMG_PS_PWR_SRC(x) ((x) << 24) 367 #define IWN_APMG_PS_PWR_SRC_VMAIN 0 368 #define IWN_APMG_PS_PWR_SRC_VAUX 2 369 #define IWN_APMG_PS_PWR_SRC_MASK IWN_APMG_PS_PWR_SRC(3) 370 #define IWN_APMG_PS_RESET_REQ (1 << 26) 371 372 /* Possible flags for register IWN_APMG_DIGITAL_SVR. */ 373 #define IWN_APMG_DIGITAL_SVR_VOLTAGE(x) (((x) & 0xf) << 5) 374 #define IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK \ 375 IWN_APMG_DIGITAL_SVR_VOLTAGE(0xf) 376 #define IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32 \ 377 IWN_APMG_DIGITAL_SVR_VOLTAGE(3) 378 379 /* Possible flags for IWN_APMG_PCI_STT. */ 380 #define IWN_APMG_PCI_STT_L1A_DIS (1 << 11) 381 382 /* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */ 383 #define IWN_FW_UPDATED (1U << 31) 384 385 #define IWN_SCHED_WINSZ 64 386 #define IWN_SCHED_LIMIT 64 387 #define IWN4965_SCHED_COUNT 512 388 #define IWN5000_SCHED_COUNT (IWN_TX_RING_COUNT + IWN_SCHED_WINSZ) 389 #define IWN4965_SCHEDSZ (IWN4965_NTXQUEUES * IWN4965_SCHED_COUNT * 2) 390 #define IWN5000_SCHEDSZ (IWN5000_NTXQUEUES * IWN5000_SCHED_COUNT * 2) 391 392 struct iwn_tx_desc { 393 uint8_t reserved1[3]; 394 uint8_t nsegs; 395 struct { 396 uint32_t addr; 397 uint16_t len; 398 } __packed segs[IWN_MAX_SCATTER]; 399 /* Pad to 128 bytes. */ 400 uint32_t reserved2; 401 } __packed; 402 403 struct iwn_rx_status { 404 uint16_t closed_count; 405 uint16_t closed_rx_count; 406 uint16_t finished_count; 407 uint16_t finished_rx_count; 408 uint32_t reserved[2]; 409 } __packed; 410 411 struct iwn_rx_desc { 412 /* 413 * The first 4 bytes of the RX frame header contain both the RX frame 414 * size and some flags. 415 * Bit fields: 416 * 31: flag flush RB request 417 * 30: flag ignore TC (terminal counter) request 418 * 29: flag fast IRQ request 419 * 28-14: Reserved 420 * 13-00: RX frame size 421 */ 422 uint32_t len; 423 uint8_t type; 424 #define IWN_UC_READY 1 425 #define IWN_ADD_NODE_DONE 24 426 #define IWN_TX_DONE 28 427 #define IWN_REPLY_LED_CMD 72 428 #define IWN5000_CALIBRATION_RESULT 102 429 #define IWN5000_CALIBRATION_DONE 103 430 #define IWN_START_SCAN 130 431 #define IWN_NOTIF_SCAN_RESULT 131 432 #define IWN_STOP_SCAN 132 433 #define IWN_RX_STATISTICS 156 434 #define IWN_BEACON_STATISTICS 157 435 #define IWN_STATE_CHANGED 161 436 #define IWN_BEACON_MISSED 162 437 #define IWN_RX_PHY 192 438 #define IWN_MPDU_RX_DONE 193 439 #define IWN_RX_DONE 195 440 #define IWN_RX_COMPRESSED_BA 197 441 442 uint8_t flags; /* 0:5 reserved, 6 abort, 7 internal */ 443 uint8_t idx; /* position within TX queue */ 444 uint8_t qid; 445 /* 0:4 TX queue id - 5:6 reserved - 7 unsolicited RX 446 * or uCode-originated notification 447 */ 448 } __packed; 449 450 #define IWN_RX_DESC_QID_MSK 0x1F 451 #define IWN_UNSOLICITED_RX_NOTIF 0x80 452 453 /* CARD_STATE_NOTIFICATION */ 454 #define IWN_STATE_CHANGE_HW_CARD_DISABLED 0x01 455 #define IWN_STATE_CHANGE_SW_CARD_DISABLED 0x02 456 #define IWN_STATE_CHANGE_CT_CARD_DISABLED 0x04 457 #define IWN_STATE_CHANGE_RXON_CARD_DISABLED 0x10 458 459 /* Possible RX status flags. */ 460 #define IWN_RX_NO_CRC_ERR (1 << 0) 461 #define IWN_RX_NO_OVFL_ERR (1 << 1) 462 /* Shortcut for the above. */ 463 #define IWN_RX_NOERROR (IWN_RX_NO_CRC_ERR | IWN_RX_NO_OVFL_ERR) 464 #define IWN_RX_MPDU_MIC_OK (1 << 6) 465 #define IWN_RX_CIPHER_MASK (7 << 8) 466 #define IWN_RX_CIPHER_CCMP (2 << 8) 467 #define IWN_RX_MPDU_DEC (1 << 11) 468 #define IWN_RX_DECRYPT_MASK (3 << 11) 469 #define IWN_RX_DECRYPT_OK (3 << 11) 470 471 struct iwn_tx_cmd { 472 uint8_t code; 473 #define IWN_CMD_RXON 16 474 #define IWN_CMD_RXON_ASSOC 17 475 #define IWN_CMD_EDCA_PARAMS 19 476 #define IWN_CMD_TIMING 20 477 #define IWN_CMD_ADD_NODE 24 478 #define IWN_CMD_TX_DATA 28 479 #define IWN_CMD_LINK_QUALITY 78 480 #define IWN_CMD_SET_LED 72 481 #define IWN5000_CMD_WIMAX_COEX 90 482 #define IWN_TEMP_NOTIFICATION 98 483 #define IWN5000_CMD_CALIB_CONFIG 101 484 #define IWN5000_CMD_CALIB_RESULT 102 485 #define IWN5000_CMD_CALIB_COMPLETE 103 486 #define IWN_CMD_SET_POWER_MODE 119 487 #define IWN_CMD_SCAN 128 488 #define IWN_CMD_SCAN_RESULTS 131 489 #define IWN_CMD_TXPOWER_DBM 149 490 #define IWN_CMD_TXPOWER 151 491 #define IWN5000_CMD_TX_ANT_CONFIG 152 492 #define IWN_CMD_TXPOWER_DBM_V1 152 493 #define IWN_CMD_BT_COEX 155 494 #define IWN_CMD_GET_STATISTICS 156 495 #define IWN_CMD_SET_CRITICAL_TEMP 164 496 #define IWN_CMD_SET_SENSITIVITY 168 497 #define IWN_CMD_PHY_CALIB 176 498 #define IWN_CMD_BT_COEX_PRIOTABLE 204 499 #define IWN_CMD_BT_COEX_PROT 205 500 #define IWN_CMD_BT_COEX_NOTIF 206 501 /* PAN commands */ 502 #define IWN_CMD_WIPAN_PARAMS 0xb2 503 #define IWN_CMD_WIPAN_RXON 0xb3 504 #define IWN_CMD_WIPAN_RXON_TIMING 0xb4 505 #define IWN_CMD_WIPAN_RXON_ASSOC 0xb6 506 #define IWN_CMD_WIPAN_QOS_PARAM 0xb7 507 #define IWN_CMD_WIPAN_WEPKEY 0xb8 508 #define IWN_CMD_WIPAN_P2P_CHANNEL_SWITCH 0xb9 509 #define IWN_CMD_WIPAN_NOA_NOTIFICATION 0xbc 510 #define IWN_CMD_WIPAN_DEACTIVATION_COMPLETE 0xbd 511 512 uint8_t flags; 513 uint8_t idx; 514 uint8_t qid; 515 uint8_t data[136]; 516 } __packed; 517 518 /* 519 * Structure for IWN_CMD_GET_STATISTICS = (0x9c) 156 520 * all devices identical. 521 * 522 * This command triggers an immediate response containing uCode statistics. 523 * The response is in the same format as IWN_BEACON_STATISTICS (0x9d) 157. 524 * 525 * If the CLEAR_STATS configuration flag is set, uCode will clear its 526 * internal copy of the statistics (counters) after issuing the response. 527 * This flag does not affect IWN_BEACON_STATISTICS after beacons (see below). 528 * 529 * If the DISABLE_NOTIF configuration flag is set, uCode will not issue 530 * IWN_BEACON_STATISTICS after received beacons. This flag 531 * does not affect the response to the IWN_CMD_GET_STATISTICS 0x9c itself. 532 */ 533 struct iwn_statistics_cmd { 534 uint32_t configuration_flags; 535 #define IWN_STATS_CONF_CLEAR_STATS htole32(0x1) 536 #define IWN_STATS_CONF_DISABLE_NOTIF htole32(0x2) 537 } __packed; 538 539 /* Antenna flags, used in various commands. */ 540 #define IWN_ANT_A (1 << 0) 541 #define IWN_ANT_B (1 << 1) 542 #define IWN_ANT_C (1 << 2) 543 /* Shortcuts. */ 544 #define IWN_ANT_AB (IWN_ANT_A | IWN_ANT_B) 545 #define IWN_ANT_BC (IWN_ANT_B | IWN_ANT_C) 546 #define IWN_ANT_AC (IWN_ANT_A | IWN_ANT_C) 547 #define IWN_ANT_ABC (IWN_ANT_A | IWN_ANT_B | IWN_ANT_C) 548 549 /* Structure for command IWN_CMD_RXON. */ 550 struct iwn_rxon { 551 uint8_t myaddr[IEEE80211_ADDR_LEN]; 552 uint16_t reserved1; 553 uint8_t bssid[IEEE80211_ADDR_LEN]; 554 uint16_t reserved2; 555 uint8_t wlap[IEEE80211_ADDR_LEN]; 556 uint16_t reserved3; 557 uint8_t mode; 558 #define IWN_MODE_HOSTAP 1 559 #define IWN_MODE_STA 3 560 #define IWN_MODE_IBSS 4 561 #define IWN_MODE_MONITOR 6 562 #define IWN_MODE_2STA 8 563 #define IWN_MODE_P2P 9 564 565 uint8_t air; 566 uint16_t rxchain; 567 #define IWN_RXCHAIN_DRIVER_FORCE (1 << 0) 568 #define IWN_RXCHAIN_VALID(x) (((x) & IWN_ANT_ABC) << 1) 569 #define IWN_RXCHAIN_FORCE_SEL(x) (((x) & IWN_ANT_ABC) << 4) 570 #define IWN_RXCHAIN_FORCE_MIMO_SEL(x) (((x) & IWN_ANT_ABC) << 7) 571 #define IWN_RXCHAIN_IDLE_COUNT(x) ((x) << 10) 572 #define IWN_RXCHAIN_MIMO_COUNT(x) ((x) << 12) 573 #define IWN_RXCHAIN_MIMO_FORCE (1 << 14) 574 575 uint8_t ofdm_mask; 576 uint8_t cck_mask; 577 uint16_t associd; 578 uint32_t flags; 579 #define IWN_RXON_24GHZ (1 << 0) 580 #define IWN_RXON_CCK (1 << 1) 581 #define IWN_RXON_AUTO (1 << 2) 582 #define IWN_RXON_SHSLOT (1 << 4) 583 #define IWN_RXON_SHPREAMBLE (1 << 5) 584 #define IWN_RXON_NODIVERSITY (1 << 7) 585 #define IWN_RXON_ANTENNA_A (1 << 8) 586 #define IWN_RXON_ANTENNA_B (1 << 9) 587 #define IWN_RXON_TSF (1 << 15) 588 #define IWN_RXON_HT_HT40MINUS (1 << 22) 589 590 #define IWN_RXON_HT_PROTMODE(x) (x << 23) 591 592 /* 0=legacy, 1=pure40, 2=mixed */ 593 #define IWN_RXON_HT_MODEPURE40 (1 << 25) 594 #define IWN_RXON_HT_MODEMIXED (2 << 25) 595 596 #define IWN_RXON_CTS_TO_SELF (1 << 30) 597 598 uint32_t filter; 599 #define IWN_FILTER_PROMISC (1 << 0) 600 #define IWN_FILTER_CTL (1 << 1) 601 #define IWN_FILTER_MULTICAST (1 << 2) 602 #define IWN_FILTER_NODECRYPT (1 << 3) 603 #define IWN_FILTER_BSS (1 << 5) 604 #define IWN_FILTER_BEACON (1 << 6) 605 606 uint8_t chan; 607 uint8_t reserved4; 608 uint8_t ht_single_mask; 609 uint8_t ht_dual_mask; 610 /* The following fields are for >=5000 Series only. */ 611 uint8_t ht_triple_mask; 612 uint8_t reserved5; 613 uint16_t acquisition; 614 uint16_t reserved6; 615 } __packed; 616 617 #define IWN4965_RXONSZ (sizeof (struct iwn_rxon) - 6) 618 #define IWN5000_RXONSZ (sizeof (struct iwn_rxon)) 619 620 /* Structure for command IWN_CMD_ASSOCIATE. */ 621 struct iwn_assoc { 622 uint32_t flags; 623 uint32_t filter; 624 uint8_t ofdm_mask; 625 uint8_t cck_mask; 626 uint16_t reserved; 627 } __packed; 628 629 /* Structure for command IWN_CMD_EDCA_PARAMS. */ 630 struct iwn_edca_params { 631 uint32_t flags; 632 #define IWN_EDCA_UPDATE (1 << 0) 633 #define IWN_EDCA_TXOP (1 << 4) 634 635 struct { 636 uint16_t cwmin; 637 uint16_t cwmax; 638 uint8_t aifsn; 639 uint8_t reserved; 640 uint16_t txoplimit; 641 } __packed ac[WME_NUM_AC]; 642 } __packed; 643 644 /* Structure for command IWN_CMD_TIMING. */ 645 struct iwn_cmd_timing { 646 uint64_t tstamp; 647 uint16_t bintval; 648 uint16_t atim; 649 uint32_t binitval; 650 uint16_t lintval; 651 uint8_t dtim_period; 652 uint8_t delta_cp_bss_tbtts; 653 } __packed; 654 655 /* Structure for command IWN_CMD_ADD_NODE. */ 656 struct iwn_node_info { 657 uint8_t control; 658 #define IWN_NODE_UPDATE (1 << 0) 659 660 uint8_t reserved1[3]; 661 662 uint8_t macaddr[IEEE80211_ADDR_LEN]; 663 uint16_t reserved2; 664 uint8_t id; 665 #define IWN_ID_BSS 0 666 #define IWN_STA_ID 1 667 668 #define IWN_PAN_ID_BCAST 14 669 #define IWN5000_ID_BROADCAST 15 670 #define IWN4965_ID_BROADCAST 31 671 672 uint8_t flags; 673 #define IWN_FLAG_SET_KEY (1 << 0) 674 #define IWN_FLAG_SET_DISABLE_TID (1 << 1) 675 #define IWN_FLAG_SET_TXRATE (1 << 2) 676 #define IWN_FLAG_SET_ADDBA (1 << 3) 677 #define IWN_FLAG_SET_DELBA (1 << 4) 678 679 uint16_t reserved3; 680 uint16_t kflags; 681 #define IWN_KFLAG_CCMP (1 << 1) 682 #define IWN_KFLAG_MAP (1 << 3) 683 #define IWN_KFLAG_KID(kid) ((kid) << 8) 684 #define IWN_KFLAG_INVALID (1 << 11) 685 #define IWN_KFLAG_GROUP (1 << 14) 686 687 uint8_t tsc2; /* TKIP TSC2 */ 688 uint8_t reserved4; 689 uint16_t ttak[5]; 690 uint8_t kid; 691 uint8_t reserved5; 692 uint8_t key[16]; 693 /* The following 3 fields are for 5000 Series only. */ 694 uint64_t tsc; 695 uint8_t rxmic[8]; 696 uint8_t txmic[8]; 697 698 uint32_t htflags; 699 #define IWN_SMPS_MIMO_PROT (1 << 17) 700 #define IWN_AMDPU_SIZE_FACTOR(x) ((x) << 19) 701 #define IWN_NODE_HT40 (1 << 21) 702 #define IWN_SMPS_MIMO_DIS (1 << 22) 703 #define IWN_AMDPU_DENSITY(x) ((x) << 23) 704 705 uint32_t mask; 706 uint16_t disable_tid; 707 uint16_t reserved6; 708 uint8_t addba_tid; 709 uint8_t delba_tid; 710 uint16_t addba_ssn; 711 uint32_t reserved7; 712 } __packed; 713 714 struct iwn4965_node_info { 715 uint8_t control; 716 uint8_t reserved1[3]; 717 uint8_t macaddr[IEEE80211_ADDR_LEN]; 718 uint16_t reserved2; 719 uint8_t id; 720 uint8_t flags; 721 uint16_t reserved3; 722 uint16_t kflags; 723 uint8_t tsc2; /* TKIP TSC2 */ 724 uint8_t reserved4; 725 uint16_t ttak[5]; 726 uint8_t kid; 727 uint8_t reserved5; 728 uint8_t key[16]; 729 uint32_t htflags; 730 uint32_t mask; 731 uint16_t disable_tid; 732 uint16_t reserved6; 733 uint8_t addba_tid; 734 uint8_t delba_tid; 735 uint16_t addba_ssn; 736 uint32_t reserved7; 737 } __packed; 738 739 #define IWN_RFLAG_RATE 0xff 740 #define IWN_RFLAG_RATE_MCS 0x1f 741 #define IWN_RFLAG_HT40_DUP 0x20 742 743 #define IWN_RFLAG_MCS (1 << 8) 744 #define IWN_RFLAG_CCK (1 << 9) 745 #define IWN_RFLAG_GREENFIELD (1 << 10) 746 #define IWN_RFLAG_HT40 (1 << 11) 747 #define IWN_RFLAG_DUPLICATE (1 << 12) 748 #define IWN_RFLAG_SGI (1 << 13) 749 #define IWN_RFLAG_ANT(x) ((x) << 14) 750 751 /* Structure for command IWN_CMD_TX_DATA. */ 752 struct iwn_cmd_data { 753 uint16_t len; 754 uint16_t lnext; 755 uint32_t flags; 756 #define IWN_TX_NEED_PROTECTION (1 << 0) /* 5000 only */ 757 #define IWN_TX_NEED_RTS (1 << 1) 758 #define IWN_TX_NEED_CTS (1 << 2) 759 #define IWN_TX_NEED_ACK (1 << 3) 760 #define IWN_TX_LINKQ (1 << 4) 761 #define IWN_TX_IMM_BA (1 << 6) 762 #define IWN_TX_FULL_TXOP (1 << 7) 763 #define IWN_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 764 #define IWN_TX_AUTO_SEQ (1 << 13) 765 #define IWN_TX_MORE_FRAG (1 << 14) 766 #define IWN_TX_INSERT_TSTAMP (1 << 16) 767 #define IWN_TX_NEED_PADDING (1 << 20) 768 769 uint32_t scratch; 770 uint32_t rate; 771 772 uint8_t id; 773 uint8_t security; 774 #define IWN_CIPHER_WEP40 1 775 #define IWN_CIPHER_CCMP 2 776 #define IWN_CIPHER_TKIP 3 777 #define IWN_CIPHER_WEP104 9 778 779 uint8_t linkq; 780 uint8_t reserved2; 781 uint8_t key[16]; 782 uint16_t fnext; 783 uint16_t reserved3; 784 uint32_t lifetime; 785 #define IWN_LIFETIME_INFINITE 0xffffffff 786 787 uint32_t loaddr; 788 uint8_t hiaddr; 789 uint8_t rts_ntries; 790 uint8_t data_ntries; 791 uint8_t tid; 792 uint16_t timeout; 793 uint16_t txop; 794 } __packed; 795 796 /* Structure for command IWN_CMD_LINK_QUALITY. */ 797 #define IWN_MAX_TX_RETRIES 16 798 struct iwn_cmd_link_quality { 799 uint8_t id; 800 uint8_t reserved1; 801 uint16_t ctl; 802 uint8_t flags; 803 uint8_t mimo; 804 uint8_t antmsk_1stream; 805 uint8_t antmsk_2stream; 806 uint8_t ridx[WME_NUM_AC]; 807 uint16_t ampdu_limit; 808 uint8_t ampdu_threshold; 809 uint8_t ampdu_max; 810 uint32_t reserved2; 811 uint32_t retry[IWN_MAX_TX_RETRIES]; 812 uint32_t reserved3; 813 } __packed; 814 815 /* Structure for command IWN_CMD_SET_LED. */ 816 struct iwn_cmd_led { 817 uint32_t unit; /* multiplier (in usecs) */ 818 uint8_t which; 819 #define IWN_LED_ACTIVITY 1 820 #define IWN_LED_LINK 2 821 822 uint8_t off; 823 uint8_t on; 824 uint8_t reserved; 825 } __packed; 826 827 /* Structure for command IWN5000_CMD_WIMAX_COEX. */ 828 struct iwn5000_wimax_coex { 829 uint32_t flags; 830 #define IWN_WIMAX_COEX_STA_TABLE_VALID (1 << 0) 831 #define IWN_WIMAX_COEX_UNASSOC_WA_UNMASK (1 << 2) 832 #define IWN_WIMAX_COEX_ASSOC_WA_UNMASK (1 << 3) 833 #define IWN_WIMAX_COEX_ENABLE (1 << 7) 834 835 struct iwn5000_wimax_event { 836 uint8_t request; 837 uint8_t window; 838 uint8_t reserved; 839 uint8_t flags; 840 } __packed events[16]; 841 } __packed; 842 843 /* Structures for command IWN5000_CMD_CALIB_CONFIG. */ 844 struct iwn5000_calib_elem { 845 uint32_t enable; 846 uint32_t start; 847 #define IWN5000_CALIB_DC (1 << 1) 848 849 uint32_t send; 850 uint32_t apply; 851 uint32_t reserved; 852 } __packed; 853 854 struct iwn5000_calib_status { 855 struct iwn5000_calib_elem once; 856 struct iwn5000_calib_elem perd; 857 uint32_t flags; 858 } __packed; 859 860 struct iwn5000_calib_config { 861 struct iwn5000_calib_status ucode; 862 struct iwn5000_calib_status driver; 863 uint32_t reserved; 864 } __packed; 865 866 /* Structure for command IWN_CMD_SET_POWER_MODE. */ 867 struct iwn_pmgt_cmd { 868 uint16_t flags; 869 #define IWN_PS_ALLOW_SLEEP (1 << 0) 870 #define IWN_PS_NOTIFY (1 << 1) 871 #define IWN_PS_SLEEP_OVER_DTIM (1 << 2) 872 #define IWN_PS_PCI_PMGT (1 << 3) 873 #define IWN_PS_FAST_PD (1 << 4) 874 #define IWN_PS_BEACON_FILTERING (1 << 5) 875 #define IWN_PS_SHADOW_REG (1 << 6) 876 #define IWN_PS_CT_KILL (1 << 7) 877 #define IWN_PS_BT_SCD (1 << 8) 878 #define IWN_PS_ADVANCED_PM (1 << 9) 879 880 uint8_t keepalive; 881 uint8_t debug; 882 uint32_t rxtimeout; 883 uint32_t txtimeout; 884 uint32_t intval[5]; 885 uint32_t beacons; 886 } __packed; 887 888 /* Structures for command IWN_CMD_SCAN. */ 889 struct iwn_scan_essid { 890 uint8_t id; 891 uint8_t len; 892 uint8_t data[IEEE80211_NWID_LEN]; 893 } __packed; 894 895 struct iwn_scan_hdr { 896 uint16_t len; 897 uint8_t scan_flags; 898 uint8_t nchan; 899 uint16_t quiet_time; 900 uint16_t quiet_threshold; 901 uint16_t crc_threshold; 902 uint16_t rxchain; 903 uint32_t max_svc; /* background scans */ 904 uint32_t pause_svc; /* background scans */ 905 uint32_t flags; 906 uint32_t filter; 907 908 /* Followed by a struct iwn_cmd_data. */ 909 /* Followed by an array of 20 structs iwn_scan_essid. */ 910 /* Followed by probe request body. */ 911 /* Followed by an array of ``nchan'' structs iwn_scan_chan. */ 912 } __packed; 913 914 struct iwn_scan_chan { 915 uint32_t flags; 916 #define IWN_CHAN_PASSIVE (0 << 0) 917 #define IWN_CHAN_ACTIVE (1 << 0) 918 #define IWN_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) 919 920 uint16_t chan; 921 uint8_t rf_gain; 922 uint8_t dsp_gain; 923 uint16_t active; /* msecs */ 924 uint16_t passive; /* msecs */ 925 } __packed; 926 927 #define IWN_SCAN_CRC_TH_DISABLED 0 928 #define IWN_SCAN_CRC_TH_DEFAULT htole16(1) 929 #define IWN_SCAN_CRC_TH_NEVER htole16(0xffff) 930 931 /* Maximum size of a scan command. */ 932 #define IWN_SCAN_MAXSZ (MCLBYTES - 4) 933 934 /* 935 * For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after 936 * sending probe req. This should be set long enough to hear probe responses 937 * from more than one AP. 938 */ 939 #define IWN_ACTIVE_DWELL_TIME_2GHZ (30) /* all times in msec */ 940 #define IWN_ACTIVE_DWELL_TIME_5GHZ (20) 941 #define IWN_ACTIVE_DWELL_FACTOR_2GHZ (3) 942 #define IWN_ACTIVE_DWELL_FACTOR_5GHZ (2) 943 944 /* 945 * For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel. 946 * Must be set longer than active dwell time. 947 * For the most reliable scan, set > AP beacon interval (typically 100msec). 948 */ 949 #define IWN_PASSIVE_DWELL_TIME_2GHZ (20) /* all times in msec */ 950 #define IWN_PASSIVE_DWELL_TIME_5GHZ (10) 951 #define IWN_PASSIVE_DWELL_BASE (100) 952 #define IWN_CHANNEL_TUNE_TIME (5) 953 954 #define IWN_SCAN_CHAN_TIMEOUT 2 955 #define IWN_MAX_SCAN_CHANNEL 50 956 957 /* 958 * If active scanning is requested but a certain channel is 959 * marked passive, we can do active scanning if we detect 960 * transmissions. 961 * 962 * There is an issue with some firmware versions that triggers 963 * a sysassert on a "good CRC threshold" of zero (== disabled), 964 * on a radar channel even though this means that we should NOT 965 * send probes. 966 * 967 * The "good CRC threshold" is the number of frames that we 968 * need to receive during our dwell time on a channel before 969 * sending out probes -- setting this to a huge value will 970 * mean we never reach it, but at the same time work around 971 * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER 972 * here instead of IWL_GOOD_CRC_TH_DISABLED. 973 * 974 * This was fixed in later versions along with some other 975 * scan changes, and the threshold behaves as a flag in those 976 * versions. 977 */ 978 #define IWN_GOOD_CRC_TH_DISABLED 0 979 #define IWN_GOOD_CRC_TH_DEFAULT htole16(1) 980 #define IWN_GOOD_CRC_TH_NEVER htole16(0xffff) 981 982 /* Structure for command IWN_CMD_TXPOWER (4965AGN only.) */ 983 #define IWN_RIDX_MAX 32 984 struct iwn4965_cmd_txpower { 985 uint8_t band; 986 uint8_t reserved1; 987 uint8_t chan; 988 uint8_t reserved2; 989 struct { 990 uint8_t rf_gain[2]; 991 uint8_t dsp_gain[2]; 992 } __packed power[IWN_RIDX_MAX + 1]; 993 } __packed; 994 995 /* Structure for command IWN_CMD_TXPOWER_DBM (5000 Series only.) */ 996 struct iwn5000_cmd_txpower { 997 int8_t global_limit; /* in half-dBm */ 998 #define IWN5000_TXPOWER_AUTO 0x7f 999 #define IWN5000_TXPOWER_MAX_DBM 16 1000 1001 uint8_t flags; 1002 #define IWN5000_TXPOWER_NO_CLOSED (1 << 6) 1003 1004 int8_t srv_limit; /* in half-dBm */ 1005 uint8_t reserved; 1006 } __packed; 1007 1008 /* Structures for command IWN_CMD_BLUETOOTH. */ 1009 struct iwn_bluetooth { 1010 uint8_t flags; 1011 #define IWN_BT_COEX_CHAN_ANN (1 << 0) 1012 #define IWN_BT_COEX_BT_PRIO (1 << 1) 1013 #define IWN_BT_COEX_2_WIRE (1 << 2) 1014 1015 uint8_t lead_time; 1016 #define IWN_BT_LEAD_TIME_DEF 30 1017 1018 uint8_t max_kill; 1019 #define IWN_BT_MAX_KILL_DEF 5 1020 1021 uint8_t reserved; 1022 uint32_t kill_ack; 1023 uint32_t kill_cts; 1024 } __packed; 1025 1026 struct iwn6000_btcoex_config { 1027 uint8_t flags; 1028 #define IWN_BT_FLAG_COEX6000_CHAN_INHIBITION 1 1029 #define IWN_BT_FLAG_COEX6000_MODE_MASK ((1 << 3) | (1 << 4) | (1 << 5 )) 1030 #define IWN_BT_FLAG_COEX6000_MODE_SHIFT 3 1031 #define IWN_BT_FLAG_COEX6000_MODE_DISABLED 0 1032 #define IWN_BT_FLAG_COEX6000_MODE_LEGACY_2W 1 1033 #define IWN_BT_FLAG_COEX6000_MODE_3W 2 1034 #define IWN_BT_FLAG_COEX6000_MODE_4W 3 1035 1036 #define IWN_BT_FLAG_UCODE_DEFAULT (1 << 6) 1037 #define IWN_BT_FLAG_SYNC_2_BT_DISABLE (1 << 7) 1038 uint8_t lead_time; 1039 uint8_t max_kill; 1040 uint8_t bt3_t7_timer; 1041 uint32_t kill_ack; 1042 uint32_t kill_cts; 1043 uint8_t sample_time; 1044 uint8_t bt3_t2_timer; 1045 uint16_t bt4_reaction; 1046 uint32_t lookup_table[12]; 1047 uint16_t bt4_decision; 1048 uint16_t valid; 1049 uint8_t prio_boost; 1050 uint8_t tx_prio_boost; 1051 uint16_t rx_prio_boost; 1052 } __packed; 1053 1054 /* Structure for enhanced command IWN_CMD_BLUETOOTH for 2000 Series. */ 1055 struct iwn2000_btcoex_config { 1056 uint8_t flags; /* Cf Flags in iwn6000_btcoex_config */ 1057 uint8_t lead_time; 1058 uint8_t max_kill; 1059 uint8_t bt3_t7_timer; 1060 uint32_t kill_ack; 1061 uint32_t kill_cts; 1062 uint8_t sample_time; 1063 uint8_t bt3_t2_timer; 1064 uint16_t bt4_reaction; 1065 uint32_t lookup_table[12]; 1066 uint16_t bt4_decision; 1067 uint16_t valid; 1068 1069 uint32_t prio_boost; /* size change prior to iwn6000_btcoex_config */ 1070 uint8_t reserved; /* added prior to iwn6000_btcoex_config */ 1071 1072 uint8_t tx_prio_boost; 1073 uint16_t rx_prio_boost; 1074 } __packed; 1075 1076 struct iwn_btcoex_priotable { 1077 uint8_t calib_init1; 1078 uint8_t calib_init2; 1079 uint8_t calib_periodic_low1; 1080 uint8_t calib_periodic_low2; 1081 uint8_t calib_periodic_high1; 1082 uint8_t calib_periodic_high2; 1083 uint8_t dtim; 1084 uint8_t scan52; 1085 uint8_t scan24; 1086 uint8_t reserved[7]; 1087 } __packed; 1088 1089 struct iwn_btcoex_prot { 1090 uint8_t open; 1091 uint8_t type; 1092 uint8_t reserved[2]; 1093 } __packed; 1094 1095 /* Structure for command IWN_CMD_SET_CRITICAL_TEMP. */ 1096 struct iwn_critical_temp { 1097 uint32_t reserved; 1098 uint32_t tempM; 1099 uint32_t tempR; 1100 /* degK <-> degC conversion macros. */ 1101 #define IWN_CTOK(c) ((c) + 273) 1102 #define IWN_KTOC(k) ((k) - 273) 1103 #define IWN_CTOMUK(c) (((c) * 1000000) + 273150000) 1104 } __packed; 1105 1106 /* Structures for command IWN_CMD_SET_SENSITIVITY. */ 1107 struct iwn_sensitivity_cmd { 1108 uint16_t which; 1109 #define IWN_SENSITIVITY_DEFAULTTBL 0 1110 #define IWN_SENSITIVITY_WORKTBL 1 1111 1112 uint16_t energy_cck; 1113 uint16_t energy_ofdm; 1114 uint16_t corr_ofdm_x1; 1115 uint16_t corr_ofdm_mrc_x1; 1116 uint16_t corr_cck_mrc_x4; 1117 uint16_t corr_ofdm_x4; 1118 uint16_t corr_ofdm_mrc_x4; 1119 uint16_t corr_barker; 1120 uint16_t corr_barker_mrc; 1121 uint16_t corr_cck_x4; 1122 uint16_t energy_ofdm_th; 1123 } __packed; 1124 1125 struct iwn_enhanced_sensitivity_cmd { 1126 uint16_t which; 1127 uint16_t energy_cck; 1128 uint16_t energy_ofdm; 1129 uint16_t corr_ofdm_x1; 1130 uint16_t corr_ofdm_mrc_x1; 1131 uint16_t corr_cck_mrc_x4; 1132 uint16_t corr_ofdm_x4; 1133 uint16_t corr_ofdm_mrc_x4; 1134 uint16_t corr_barker; 1135 uint16_t corr_barker_mrc; 1136 uint16_t corr_cck_x4; 1137 uint16_t energy_ofdm_th; 1138 /* "Enhanced" part. */ 1139 uint16_t ina_det_ofdm; 1140 uint16_t ina_det_cck; 1141 uint16_t corr_11_9_en; 1142 uint16_t ofdm_det_slope_mrc; 1143 uint16_t ofdm_det_icept_mrc; 1144 uint16_t ofdm_det_slope; 1145 uint16_t ofdm_det_icept; 1146 uint16_t cck_det_slope_mrc; 1147 uint16_t cck_det_icept_mrc; 1148 uint16_t cck_det_slope; 1149 uint16_t cck_det_icept; 1150 uint16_t reserved; 1151 } __packed; 1152 1153 /* 1154 * Define maximal number of calib result send to runtime firmware 1155 * PS: TEMP_OFFSET count for 2 (std and v2) 1156 */ 1157 #define IWN5000_PHY_CALIB_MAX_RESULT 8 1158 1159 /* Structures for command IWN_CMD_PHY_CALIB. */ 1160 struct iwn_phy_calib { 1161 uint8_t code; 1162 #define IWN4965_PHY_CALIB_DIFF_GAIN 7 1163 #define IWN5000_PHY_CALIB_DC 8 1164 #define IWN5000_PHY_CALIB_LO 9 1165 #define IWN5000_PHY_CALIB_TX_IQ 11 1166 #define IWN5000_PHY_CALIB_CRYSTAL 15 1167 #define IWN5000_PHY_CALIB_BASE_BAND 16 1168 #define IWN5000_PHY_CALIB_TX_IQ_PERIODIC 17 1169 #define IWN5000_PHY_CALIB_TEMP_OFFSET 18 1170 1171 #define IWN5000_PHY_CALIB_RESET_NOISE_GAIN 18 1172 #define IWN5000_PHY_CALIB_NOISE_GAIN 19 1173 1174 uint8_t group; 1175 uint8_t ngroups; 1176 uint8_t isvalid; 1177 } __packed; 1178 1179 struct iwn5000_phy_calib_crystal { 1180 uint8_t code; 1181 uint8_t group; 1182 uint8_t ngroups; 1183 uint8_t isvalid; 1184 1185 uint8_t cap_pin[2]; 1186 uint8_t reserved[2]; 1187 } __packed; 1188 1189 struct iwn5000_phy_calib_temp_offset { 1190 uint8_t code; 1191 uint8_t group; 1192 uint8_t ngroups; 1193 uint8_t isvalid; 1194 int16_t offset; 1195 #define IWN_DEFAULT_TEMP_OFFSET 2700 1196 1197 uint16_t reserved; 1198 } __packed; 1199 1200 struct iwn5000_phy_calib_temp_offsetv2 { 1201 uint8_t code; 1202 uint8_t group; 1203 uint8_t ngroups; 1204 uint8_t isvalid; 1205 int16_t offset_high; 1206 int16_t offset_low; 1207 int16_t burnt_voltage_ref; 1208 int16_t reserved; 1209 } __packed; 1210 1211 struct iwn_phy_calib_gain { 1212 uint8_t code; 1213 uint8_t group; 1214 uint8_t ngroups; 1215 uint8_t isvalid; 1216 1217 int8_t gain[3]; 1218 uint8_t reserved; 1219 } __packed; 1220 1221 /* Structure for command IWN_CMD_SPECTRUM_MEASUREMENT. */ 1222 struct iwn_spectrum_cmd { 1223 uint16_t len; 1224 uint8_t token; 1225 uint8_t id; 1226 uint8_t origin; 1227 uint8_t periodic; 1228 uint16_t timeout; 1229 uint32_t start; 1230 uint32_t reserved1; 1231 uint32_t flags; 1232 uint32_t filter; 1233 uint16_t nchan; 1234 uint16_t reserved2; 1235 struct { 1236 uint32_t duration; 1237 uint8_t chan; 1238 uint8_t type; 1239 #define IWN_MEASUREMENT_BASIC (1 << 0) 1240 #define IWN_MEASUREMENT_CCA (1 << 1) 1241 #define IWN_MEASUREMENT_RPI_HISTOGRAM (1 << 2) 1242 #define IWN_MEASUREMENT_NOISE_HISTOGRAM (1 << 3) 1243 #define IWN_MEASUREMENT_FRAME (1 << 4) 1244 #define IWN_MEASUREMENT_IDLE (1 << 7) 1245 1246 uint16_t reserved; 1247 } __packed chan[10]; 1248 } __packed; 1249 1250 /* Structure for IWN_UC_READY notification. */ 1251 #define IWN_NATTEN_GROUPS 5 1252 struct iwn_ucode_info { 1253 uint8_t minor; 1254 uint8_t major; 1255 uint16_t reserved1; 1256 uint8_t revision[8]; 1257 uint8_t type; 1258 uint8_t subtype; 1259 #define IWN_UCODE_RUNTIME 0 1260 #define IWN_UCODE_INIT 9 1261 1262 uint16_t reserved2; 1263 uint32_t logptr; 1264 uint32_t errptr; 1265 uint32_t tstamp; 1266 uint32_t valid; 1267 1268 /* The following fields are for UCODE_INIT only. */ 1269 int32_t volt; 1270 struct { 1271 int32_t chan20MHz; 1272 int32_t chan40MHz; 1273 } __packed temp[4]; 1274 int32_t atten[IWN_NATTEN_GROUPS][2]; 1275 } __packed; 1276 1277 /* Structures for IWN_TX_DONE notification. */ 1278 1279 /* 1280 * TX command response is sent after *agn* transmission attempts. 1281 * 1282 * both postpone and abort status are expected behavior from uCode. there is 1283 * no special operation required from driver; except for RFKILL_FLUSH, 1284 * which required tx flush host command to flush all the tx frames in queues 1285 */ 1286 #define IWN_TX_STATUS_MSK 0x000000ff 1287 #define IWN_TX_STATUS_DELAY_MSK 0x00000040 1288 #define IWN_TX_STATUS_ABORT_MSK 0x00000080 1289 #define IWN_TX_PACKET_MODE_MSK 0x0000ff00 1290 #define IWN_TX_FIFO_NUMBER_MSK 0x00070000 1291 #define IWN_TX_RESERVED 0x00780000 1292 #define IWN_TX_POWER_PA_DETECT_MSK 0x7f800000 1293 #define IWN_TX_ABORT_REQUIRED_MSK 0x80000000 1294 1295 /* Success status */ 1296 #define IWN_TX_STATUS_SUCCESS 0x01 1297 #define IWN_TX_STATUS_DIRECT_DONE 0x02 1298 1299 /* postpone TX */ 1300 #define IWN_TX_STATUS_POSTPONE_DELAY 0x40 1301 #define IWN_TX_STATUS_POSTPONE_FEW_BYTES 0x41 1302 #define IWN_TX_STATUS_POSTPONE_BT_PRIO 0x42 1303 #define IWN_TX_STATUS_POSTPONE_QUIET_PERIOD 0x43 1304 #define IWN_TX_STATUS_POSTPONE_CALC_TTAK 0x44 1305 1306 /* Failures */ 1307 #define IWN_TX_FAIL 0x80 /* all failures have 0x80 set */ 1308 #define IWN_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY 0x81 1309 #define IWN_TX_FAIL_SHORT_LIMIT 0x82 /* too many RTS retries */ 1310 #define IWN_TX_FAIL_LONG_LIMIT 0x83 /* too many retries */ 1311 #define IWN_TX_FAIL_FIFO_UNDERRRUN 0x84 /* tx fifo not kept running */ 1312 #define IWN_TX_STATUS_FAIL_DRAIN_FLOW 0x85 1313 #define IWN_TX_STATUS_FAIL_RFKILL_FLUSH 0x86 1314 #define IWN_TX_STATUS_FAIL_LIFE_EXPIRE 0x87 1315 #define IWN_TX_FAIL_DEST_IN_PS 0x88 /* sta found in power save */ 1316 #define IWN_TX_STATUS_FAIL_HOST_ABORTED 0x89 1317 #define IWN_TX_STATUS_FAIL_BT_RETRY 0x8a 1318 #define IWN_TX_FAIL_STA_INVALID 0x8b /* XXX STA invalid (???) */ 1319 #define IWN_TX_STATUS_FAIL_FRAG_DROPPED 0x8c 1320 #define IWN_TX_STATUS_FAIL_TID_DISABLE 0x8d 1321 #define IWN_TX_STATUS_FAIL_FIFO_FLUSHED 0x8e 1322 #define IWN_TX_STATUS_FAIL_INSUFFICIENT_CF_POLL 0x8f 1323 #define IWN_TX_FAIL_TX_LOCKED 0x90 /* waiting to see traffic */ 1324 #define IWN_TX_STATUS_FAIL_NO_BEACON_ON_RADAR 0x91 1325 1326 /* 1327 * TX command response for A-MPDU packet responses. 1328 * 1329 * The status response is different to the non A-MPDU responses. 1330 * In addition, the sequence number is treated as the sequence 1331 * number of the TX command, NOT the 802.11 sequence number! 1332 */ 1333 #define IWN_AGG_TX_STATE_TRANSMITTED 0x00 1334 #define IWN_AGG_TX_STATE_UNDERRUN_MSK 0x01 1335 #define IWN_AGG_TX_STATE_FEW_BYTES_MSK 0x04 1336 #define IWN_AGG_TX_STATE_ABORT_MSK 0x08 1337 1338 #define IWN_AGG_TX_STATE_LAST_SENT_TTL_MSK 0x10 1339 #define IWN_AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK 0x20 1340 1341 #define IWN_AGG_TX_STATE_SCD_QUERY_MSK 0x80 1342 1343 #define IWN_AGG_TX_STATE_TEST_BAD_CRC32_MSK 0x100 1344 1345 #define IWN_AGG_TX_STATE_RESPONSE_MSK 0x1ff 1346 #define IWN_AGG_TX_STATE_DUMP_TX_MSK 0x200 1347 #define IWN_AGG_TX_STATE_DELAY_TX_MSK 0x400 1348 1349 #define IWN_AGG_TX_STATUS_MSK 0x00000fff 1350 #define IWN_AGG_TX_TRY_MSK 0x0000f000 1351 1352 #define IWN_AGG_TX_STATE_LAST_SENT_MSK \ 1353 (IWN_AGG_TX_STATE_LAST_SENT_TTL_MSK | \ 1354 IWN_AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK) 1355 1356 /* # tx attempts for first frame in aggregation */ 1357 #define IWN_AGG_TX_STATE_TRY_CNT_POS 12 1358 #define IWN_AGG_TX_STATE_TRY_CNT_MSK 0xf000 1359 1360 /* Command ID and sequence number of Tx command for this frame */ 1361 #define IWN_AGG_TX_STATE_SEQ_NUM_POS 16 1362 #define IWN_AGG_TX_STATE_SEQ_NUM_MSK 0xffff0000 1363 1364 struct iwn4965_tx_stat { 1365 uint8_t nframes; 1366 uint8_t btkillcnt; 1367 uint8_t rtsfailcnt; 1368 uint8_t ackfailcnt; 1369 uint32_t rate; 1370 uint16_t duration; 1371 uint16_t reserved; 1372 uint32_t power[2]; 1373 uint32_t status; 1374 } __packed; 1375 1376 struct iwn5000_tx_stat { 1377 uint8_t nframes; /* 1 no aggregation, >1 aggregation */ 1378 uint8_t btkillcnt; 1379 uint8_t rtsfailcnt; 1380 uint8_t ackfailcnt; 1381 uint32_t rate; 1382 uint16_t duration; 1383 uint16_t reserved; 1384 uint32_t power[2]; 1385 uint32_t info; 1386 uint16_t seq; 1387 uint16_t len; 1388 uint8_t tlc; 1389 uint8_t ratid; /* tid (0:3), sta_id (4:7) */ 1390 uint8_t fc[2]; 1391 uint16_t status; 1392 uint16_t sequence; 1393 } __packed; 1394 1395 /* Structure for IWN_BEACON_MISSED notification. */ 1396 struct iwn_beacon_missed { 1397 uint32_t consecutive; 1398 uint32_t total; 1399 uint32_t expected; 1400 uint32_t received; 1401 } __packed; 1402 1403 /* Structure for IWN_MPDU_RX_DONE notification. */ 1404 struct iwn_rx_mpdu { 1405 uint16_t len; 1406 uint16_t reserved; 1407 } __packed; 1408 1409 /* Structures for IWN_RX_DONE and IWN_MPDU_RX_DONE notifications. */ 1410 struct iwn4965_rx_phystat { 1411 uint16_t antenna; 1412 uint16_t agc; 1413 uint8_t rssi[6]; 1414 } __packed; 1415 1416 struct iwn5000_rx_phystat { 1417 uint32_t reserved1; 1418 uint32_t agc; 1419 uint16_t rssi[3]; 1420 } __packed; 1421 1422 struct iwn_rx_stat { 1423 uint8_t phy_len; 1424 uint8_t cfg_phy_len; 1425 #define IWN_STAT_MAXLEN 20 1426 1427 uint8_t id; 1428 uint8_t reserved1; 1429 uint64_t tstamp; 1430 uint32_t beacon; 1431 uint16_t flags; 1432 #define IWN_STAT_FLAG_SHPREAMBLE (1 << 2) 1433 1434 uint16_t chan; 1435 uint8_t phybuf[32]; 1436 uint32_t rate; 1437 /* 1438 * rate bit fields 1439 * 1440 * High-throughput (HT) rate format for bits 7:0 (bit 8 must be "1"): 1441 * 2-0: 0) 6 Mbps 1442 * 1) 12 Mbps 1443 * 2) 18 Mbps 1444 * 3) 24 Mbps 1445 * 4) 36 Mbps 1446 * 5) 48 Mbps 1447 * 6) 54 Mbps 1448 * 7) 60 Mbps 1449 * 1450 * 4-3: 0) Single stream (SISO) 1451 * 1) Dual stream (MIMO) 1452 * 2) Triple stream (MIMO) 1453 * 1454 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data 1455 * 1456 * Legacy OFDM rate format for bits 7:0 (bit 8 must be "0", bit 9 "0"): 1457 * 3-0: 0xD) 6 Mbps 1458 * 0xF) 9 Mbps 1459 * 0x5) 12 Mbps 1460 * 0x7) 18 Mbps 1461 * 0x9) 24 Mbps 1462 * 0xB) 36 Mbps 1463 * 0x1) 48 Mbps 1464 * 0x3) 54 Mbps 1465 * 1466 * Legacy CCK rate format for bits 7:0 (bit 8 must be "0", bit 9 "1"): 1467 * 6-0: 10) 1 Mbps 1468 * 20) 2 Mbps 1469 * 55) 5.5 Mbps 1470 * 110) 11 Mbps 1471 * 1472 */ 1473 uint16_t len; 1474 uint16_t reserve3; 1475 } __packed; 1476 1477 #define IWN_RSSI_TO_DBM 44 1478 1479 /* Structure for IWN_RX_COMPRESSED_BA notification. */ 1480 struct iwn_compressed_ba { 1481 uint8_t macaddr[IEEE80211_ADDR_LEN]; 1482 uint16_t reserved; 1483 uint8_t id; 1484 uint8_t tid; 1485 uint16_t seq; 1486 uint64_t bitmap; 1487 uint16_t qid; 1488 uint16_t ssn; 1489 /* extra fields starting with iwn5000 */ 1490 #if 0 1491 uint8_t txed; /* number of frames sent */ 1492 uint8_t txed_2_done; /* number of frames acked */ 1493 uint16_t reserved1; 1494 #endif 1495 } __packed; 1496 1497 /* Structure for IWN_START_SCAN notification. */ 1498 struct iwn_start_scan { 1499 uint64_t tstamp; 1500 uint32_t tbeacon; 1501 uint8_t chan; 1502 uint8_t band; 1503 uint16_t reserved; 1504 uint32_t status; 1505 } __packed; 1506 1507 /* Structure for IWN_STOP_SCAN notification. */ 1508 struct iwn_stop_scan { 1509 uint8_t nchan; 1510 uint8_t status; 1511 uint8_t reserved; 1512 uint8_t chan; 1513 uint64_t tsf; 1514 } __packed; 1515 1516 /* Structure for IWN_SPECTRUM_MEASUREMENT notification. */ 1517 struct iwn_spectrum_notif { 1518 uint8_t id; 1519 uint8_t token; 1520 uint8_t idx; 1521 uint8_t state; 1522 #define IWN_MEASUREMENT_START 0 1523 #define IWN_MEASUREMENT_STOP 1 1524 1525 uint32_t start; 1526 uint8_t band; 1527 uint8_t chan; 1528 uint8_t type; 1529 uint8_t reserved1; 1530 uint32_t cca_ofdm; 1531 uint32_t cca_cck; 1532 uint32_t cca_time; 1533 uint8_t basic; 1534 uint8_t reserved2[3]; 1535 uint32_t ofdm[8]; 1536 uint32_t cck[8]; 1537 uint32_t stop; 1538 uint32_t status; 1539 #define IWN_MEASUREMENT_OK 0 1540 #define IWN_MEASUREMENT_CONCURRENT 1 1541 #define IWN_MEASUREMENT_CSA_CONFLICT 2 1542 #define IWN_MEASUREMENT_TGH_CONFLICT 3 1543 #define IWN_MEASUREMENT_STOPPED 6 1544 #define IWN_MEASUREMENT_TIMEOUT 7 1545 #define IWN_MEASUREMENT_FAILED 8 1546 } __packed; 1547 1548 /* Structures for IWN_{RX,BEACON}_STATISTICS notification. */ 1549 struct iwn_rx_phy_stats { 1550 uint32_t ina; 1551 uint32_t fina; 1552 uint32_t bad_plcp; 1553 uint32_t bad_crc32; 1554 uint32_t overrun; 1555 uint32_t eoverrun; 1556 uint32_t good_crc32; 1557 uint32_t fa; 1558 uint32_t bad_fina_sync; 1559 uint32_t sfd_timeout; 1560 uint32_t fina_timeout; 1561 uint32_t no_rts_ack; 1562 uint32_t rxe_limit; 1563 uint32_t ack; 1564 uint32_t cts; 1565 uint32_t ba_resp; 1566 uint32_t dsp_kill; 1567 uint32_t bad_mh; 1568 uint32_t rssi_sum; 1569 uint32_t reserved; 1570 } __packed; 1571 1572 struct iwn_rx_general_stats { 1573 uint32_t bad_cts; 1574 uint32_t bad_ack; 1575 uint32_t not_bss; 1576 uint32_t filtered; 1577 uint32_t bad_chan; 1578 uint32_t beacons; 1579 uint32_t missed_beacons; 1580 uint32_t adc_saturated; /* time in 0.8us */ 1581 uint32_t ina_searched; /* time in 0.8us */ 1582 uint32_t noise[3]; 1583 uint32_t flags; 1584 uint32_t load; 1585 uint32_t fa; 1586 uint32_t rssi[3]; 1587 uint32_t energy[3]; 1588 } __packed; 1589 1590 struct iwn_rx_ht_phy_stats { 1591 uint32_t bad_plcp; 1592 uint32_t overrun; 1593 uint32_t eoverrun; 1594 uint32_t good_crc32; 1595 uint32_t bad_crc32; 1596 uint32_t bad_mh; 1597 uint32_t good_ampdu_crc32; 1598 uint32_t ampdu; 1599 uint32_t fragment; 1600 uint32_t unsupport_mcs; 1601 } __packed; 1602 1603 struct iwn_rx_stats { 1604 struct iwn_rx_phy_stats ofdm; 1605 struct iwn_rx_phy_stats cck; 1606 struct iwn_rx_general_stats general; 1607 struct iwn_rx_ht_phy_stats ht; 1608 } __packed; 1609 1610 struct iwn_rx_general_stats_bt { 1611 struct iwn_rx_general_stats common; 1612 /* additional stats for bt */ 1613 uint32_t num_bt_kills; 1614 uint32_t reserved[2]; 1615 } __packed; 1616 1617 struct iwn_rx_stats_bt { 1618 struct iwn_rx_phy_stats ofdm; 1619 struct iwn_rx_phy_stats cck; 1620 struct iwn_rx_general_stats_bt general_bt; 1621 struct iwn_rx_ht_phy_stats ht; 1622 } __packed; 1623 1624 struct iwn_tx_stats { 1625 uint32_t preamble; 1626 uint32_t rx_detected; 1627 uint32_t bt_defer; 1628 uint32_t bt_kill; 1629 uint32_t short_len; 1630 uint32_t cts_timeout; 1631 uint32_t ack_timeout; 1632 uint32_t exp_ack; 1633 uint32_t ack; 1634 uint32_t msdu; 1635 uint32_t burst_err1; 1636 uint32_t burst_err2; 1637 uint32_t cts_collision; 1638 uint32_t ack_collision; 1639 uint32_t ba_timeout; 1640 uint32_t ba_resched; 1641 uint32_t query_ampdu; 1642 uint32_t query; 1643 uint32_t query_ampdu_frag; 1644 uint32_t query_mismatch; 1645 uint32_t not_ready; 1646 uint32_t underrun; 1647 uint32_t bt_ht_kill; 1648 uint32_t rx_ba_resp; 1649 /* 1650 * 6000 series only - LSB=ant A, ant B, ant C, MSB=reserved 1651 * TX power on chain in 1/2 dBm. 1652 */ 1653 uint32_t tx_power; 1654 uint32_t reserved[1]; 1655 } __packed; 1656 1657 struct iwn_general_stats { 1658 uint32_t temp; /* radio temperature */ 1659 uint32_t temp_m; /* radio voltage */ 1660 uint32_t burst_check; 1661 uint32_t burst; 1662 uint32_t wait_for_silence_timeout_cnt; 1663 uint32_t reserved1[3]; 1664 uint32_t sleep; 1665 uint32_t slot_out; 1666 uint32_t slot_idle; 1667 uint32_t ttl_tstamp; 1668 uint32_t tx_ant_a; 1669 uint32_t tx_ant_b; 1670 uint32_t exec; 1671 uint32_t probe; 1672 uint32_t reserved2[2]; 1673 uint32_t rx_enabled; 1674 /* 1675 * This is the number of times we have to re-tune 1676 * in order to get out of bad PHY status. 1677 */ 1678 uint32_t num_of_sos_states; 1679 } __packed; 1680 1681 struct iwn_stats { 1682 uint32_t flags; 1683 struct iwn_rx_stats rx; 1684 struct iwn_tx_stats tx; 1685 struct iwn_general_stats general; 1686 uint32_t reserved1[2]; 1687 } __packed; 1688 1689 struct iwn_bt_activity_stats { 1690 /* Tx statistics */ 1691 uint32_t hi_priority_tx_req_cnt; 1692 uint32_t hi_priority_tx_denied_cnt; 1693 uint32_t lo_priority_tx_req_cnt; 1694 uint32_t lo_priority_tx_denied_cnt; 1695 /* Rx statistics */ 1696 uint32_t hi_priority_rx_req_cnt; 1697 uint32_t hi_priority_rx_denied_cnt; 1698 uint32_t lo_priority_rx_req_cnt; 1699 uint32_t lo_priority_rx_denied_cnt; 1700 } __packed; 1701 1702 struct iwn_stats_bt { 1703 uint32_t flags; 1704 struct iwn_rx_stats_bt rx_bt; 1705 struct iwn_tx_stats tx; 1706 struct iwn_general_stats general; 1707 struct iwn_bt_activity_stats activity; 1708 uint32_t reserved1[2]; 1709 }; 1710 1711 /* Firmware error dump. */ 1712 struct iwn_fw_dump { 1713 uint32_t valid; 1714 uint32_t id; 1715 uint32_t pc; 1716 uint32_t branch_link[2]; 1717 uint32_t interrupt_link[2]; 1718 uint32_t error_data[2]; 1719 uint32_t src_line; 1720 uint32_t tsf; 1721 uint32_t time[2]; 1722 } __packed; 1723 1724 /* TLV firmware header. */ 1725 struct iwn_fw_tlv_hdr { 1726 uint32_t zero; /* Always 0, to differentiate from legacy. */ 1727 uint32_t signature; 1728 #define IWN_FW_SIGNATURE 0x0a4c5749 /* "IWL\n" */ 1729 1730 uint8_t descr[64]; 1731 uint32_t rev; 1732 #define IWN_FW_API(x) (((x) >> 8) & 0xff) 1733 1734 uint32_t build; 1735 uint64_t altmask; 1736 } __packed; 1737 1738 /* TLV header. */ 1739 struct iwn_fw_tlv { 1740 uint16_t type; 1741 #define IWN_FW_TLV_MAIN_TEXT 1 1742 #define IWN_FW_TLV_MAIN_DATA 2 1743 #define IWN_FW_TLV_INIT_TEXT 3 1744 #define IWN_FW_TLV_INIT_DATA 4 1745 #define IWN_FW_TLV_BOOT_TEXT 5 1746 #define IWN_FW_TLV_PBREQ_MAXLEN 6 1747 #define IWN_FW_TLV_PAN 7 1748 #define IWN_FW_TLV_RUNT_EVTLOG_PTR 8 1749 #define IWN_FW_TLV_RUNT_EVTLOG_SIZE 9 1750 #define IWN_FW_TLV_RUNT_ERRLOG_PTR 10 1751 #define IWN_FW_TLV_INIT_EVTLOG_PTR 11 1752 #define IWN_FW_TLV_INIT_EVTLOG_SIZE 12 1753 #define IWN_FW_TLV_INIT_ERRLOG_PTR 13 1754 #define IWN_FW_TLV_ENH_SENS 14 1755 #define IWN_FW_TLV_PHY_CALIB 15 1756 #define IWN_FW_TLV_WOWLAN_INST 16 1757 #define IWN_FW_TLV_WOWLAN_DATA 17 1758 #define IWN_FW_TLV_FLAGS 18 1759 1760 uint16_t alt; 1761 uint32_t len; 1762 } __packed; 1763 1764 #define IWN4965_FW_TEXT_MAXSZ ( 96 * 1024) 1765 #define IWN4965_FW_DATA_MAXSZ ( 40 * 1024) 1766 #define IWN5000_FW_TEXT_MAXSZ (256 * 1024) 1767 #define IWN5000_FW_DATA_MAXSZ ( 80 * 1024) 1768 #define IWN_FW_BOOT_TEXT_MAXSZ 1024 1769 #define IWN4965_FWSZ (IWN4965_FW_TEXT_MAXSZ + IWN4965_FW_DATA_MAXSZ) 1770 #define IWN5000_FWSZ IWN5000_FW_TEXT_MAXSZ 1771 1772 /* 1773 * Microcode flags TLV (18.) 1774 */ 1775 1776 /** 1777 * enum iwn_ucode_tlv_flag - ucode API flags 1778 * @IWN_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously 1779 * was a separate TLV but moved here to save space. 1780 * @IWN_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID, 1781 * treats good CRC threshold as a boolean 1782 * @IWN_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). 1783 * @IWN_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P. 1784 * @IWN_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS 1785 * @IWN_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD 1786 * @IWN_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan 1787 * offload profile config command. 1788 * @IWN_UCODE_TLV_FLAGS_RX_ENERGY_API: supports rx signal strength api 1789 * @IWN_UCODE_TLV_FLAGS_TIME_EVENT_API_V2: using the new time event API. 1790 * @IWN_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six 1791 * (rather than two) IPv6 addresses 1792 * @IWN_UCODE_TLV_FLAGS_BF_UPDATED: new beacon filtering API 1793 * @IWN_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element 1794 * from the probe request template. 1795 * @IWN_UCODE_TLV_FLAGS_D3_CONTINUITY_API: modified D3 API to allow keeping 1796 * connection when going back to D0 1797 * @IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version) 1798 * @IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version) 1799 * @IWN_UCODE_TLV_FLAGS_SCHED_SCAN: this uCode image supports scheduled scan. 1800 * @IWN_UCODE_TLV_FLAGS_STA_KEY_CMD: new ADD_STA and ADD_STA_KEY command API 1801 * @IWN_UCODE_TLV_FLAGS_DEVICE_PS_CMD: support device wide power command 1802 * containing CAM (Continuous Active Mode) indication. 1803 */ 1804 enum iwn_ucode_tlv_flag { 1805 IWN_UCODE_TLV_FLAGS_PAN = (1 << 0), 1806 IWN_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1), 1807 IWN_UCODE_TLV_FLAGS_MFP = (1 << 2), 1808 IWN_UCODE_TLV_FLAGS_P2P = (1 << 3), 1809 IWN_UCODE_TLV_FLAGS_DW_BC_TABLE = (1 << 4), 1810 IWN_UCODE_TLV_FLAGS_NEWBT_COEX = (1 << 5), 1811 IWN_UCODE_TLV_FLAGS_UAPSD = (1 << 6), 1812 IWN_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7), 1813 IWN_UCODE_TLV_FLAGS_RX_ENERGY_API = (1 << 8), 1814 IWN_UCODE_TLV_FLAGS_TIME_EVENT_API_V2 = (1 << 9), 1815 IWN_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10), 1816 IWN_UCODE_TLV_FLAGS_BF_UPDATED = (1 << 11), 1817 IWN_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12), 1818 IWN_UCODE_TLV_FLAGS_D3_CONTINUITY_API = (1 << 14), 1819 IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15), 1820 IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16), 1821 IWN_UCODE_TLV_FLAGS_SCHED_SCAN = (1 << 17), 1822 IWN_UCODE_TLV_FLAGS_STA_KEY_CMD = (1 << 19), 1823 IWN_UCODE_TLV_FLAGS_DEVICE_PS_CMD = (1 << 20), 1824 }; 1825 1826 /* 1827 * Offsets into EEPROM. 1828 */ 1829 #define IWN_EEPROM_MAC 0x015 1830 #define IWN_EEPROM_SKU_CAP 0x045 1831 #define IWN_EEPROM_RFCFG 0x048 1832 #define IWN4965_EEPROM_DOMAIN 0x060 1833 #define IWN4965_EEPROM_BAND1 0x063 1834 #define IWN5000_EEPROM_REG 0x066 1835 #define IWN5000_EEPROM_CAL 0x067 1836 #define IWN4965_EEPROM_BAND2 0x072 1837 #define IWN4965_EEPROM_BAND3 0x080 1838 #define IWN4965_EEPROM_BAND4 0x08d 1839 #define IWN4965_EEPROM_BAND5 0x099 1840 #define IWN4965_EEPROM_BAND6 0x0a0 1841 #define IWN4965_EEPROM_BAND7 0x0a8 1842 #define IWN4965_EEPROM_MAXPOW 0x0e8 1843 #define IWN4965_EEPROM_VOLTAGE 0x0e9 1844 #define IWN4965_EEPROM_BANDS 0x0ea 1845 /* Indirect offsets. */ 1846 #define IWN5000_EEPROM_NO_HT40 0x000 1847 #define IWN5000_EEPROM_DOMAIN 0x001 1848 #define IWN5000_EEPROM_BAND1 0x004 1849 #define IWN5000_EEPROM_BAND2 0x013 1850 #define IWN5000_EEPROM_BAND3 0x021 1851 #define IWN5000_EEPROM_BAND4 0x02e 1852 #define IWN5000_EEPROM_BAND5 0x03a 1853 #define IWN5000_EEPROM_BAND6 0x041 1854 #define IWN6000_EEPROM_BAND6 0x040 1855 #define IWN5000_EEPROM_BAND7 0x049 1856 #define IWN6000_EEPROM_ENHINFO 0x054 1857 #define IWN5000_EEPROM_CRYSTAL 0x128 1858 #define IWN5000_EEPROM_TEMP 0x12a 1859 #define IWN5000_EEPROM_VOLT 0x12b 1860 1861 /* Possible flags for IWN_EEPROM_SKU_CAP. */ 1862 #define IWN_EEPROM_SKU_CAP_11N (1 << 6) 1863 #define IWN_EEPROM_SKU_CAP_AMT (1 << 7) 1864 #define IWN_EEPROM_SKU_CAP_IPAN (1 << 8) 1865 1866 /* Possible flags for IWN_EEPROM_RFCFG. */ 1867 #define IWN_RFCFG_TYPE(x) (((x) >> 0) & 0x3) 1868 #define IWN_RFCFG_STEP(x) (((x) >> 2) & 0x3) 1869 #define IWN_RFCFG_DASH(x) (((x) >> 4) & 0x3) 1870 #define IWN_RFCFG_TXANTMSK(x) (((x) >> 8) & 0xf) 1871 #define IWN_RFCFG_RXANTMSK(x) (((x) >> 12) & 0xf) 1872 1873 struct iwn_eeprom_chan { 1874 uint8_t flags; 1875 #define IWN_EEPROM_CHAN_VALID (1 << 0) 1876 #define IWN_EEPROM_CHAN_IBSS (1 << 1) 1877 #define IWN_EEPROM_CHAN_ACTIVE (1 << 3) 1878 #define IWN_EEPROM_CHAN_RADAR (1 << 4) 1879 1880 int8_t maxpwr; 1881 } __packed; 1882 1883 struct iwn_eeprom_enhinfo { 1884 uint8_t flags; 1885 #define IWN_ENHINFO_VALID 0x01 1886 #define IWN_ENHINFO_5GHZ 0x02 1887 #define IWN_ENHINFO_OFDM 0x04 1888 #define IWN_ENHINFO_HT40 0x08 1889 #define IWN_ENHINFO_HTAP 0x10 1890 #define IWN_ENHINFO_RES1 0x20 1891 #define IWN_ENHINFO_RES2 0x40 1892 #define IWN_ENHINFO_COMMON 0x80 1893 1894 uint8_t chan; 1895 int8_t chain[3]; /* max power in half-dBm */ 1896 uint8_t reserved; 1897 int8_t mimo2; /* max power in half-dBm */ 1898 int8_t mimo3; /* max power in half-dBm */ 1899 } __packed; 1900 1901 struct iwn5000_eeprom_calib_hdr { 1902 uint8_t version; 1903 uint8_t pa_type; 1904 uint16_t volt; 1905 } __packed; 1906 1907 #define IWN_NSAMPLES 3 1908 struct iwn4965_eeprom_chan_samples { 1909 uint8_t num; 1910 struct { 1911 uint8_t temp; 1912 uint8_t gain; 1913 uint8_t power; 1914 int8_t pa_det; 1915 } samples[2][IWN_NSAMPLES]; 1916 } __packed; 1917 1918 #define IWN_NBANDS 8 1919 struct iwn4965_eeprom_band { 1920 uint8_t lo; /* low channel number */ 1921 uint8_t hi; /* high channel number */ 1922 struct iwn4965_eeprom_chan_samples chans[2]; 1923 } __packed; 1924 1925 /* 1926 * Offsets of channels descriptions in EEPROM. 1927 */ 1928 static const uint32_t iwn4965_regulatory_bands[IWN_NBANDS] = { 1929 IWN4965_EEPROM_BAND1, 1930 IWN4965_EEPROM_BAND2, 1931 IWN4965_EEPROM_BAND3, 1932 IWN4965_EEPROM_BAND4, 1933 IWN4965_EEPROM_BAND5, 1934 IWN4965_EEPROM_BAND6, 1935 IWN4965_EEPROM_BAND7 1936 }; 1937 1938 static const uint32_t iwn5000_regulatory_bands[IWN_NBANDS] = { 1939 IWN5000_EEPROM_BAND1, 1940 IWN5000_EEPROM_BAND2, 1941 IWN5000_EEPROM_BAND3, 1942 IWN5000_EEPROM_BAND4, 1943 IWN5000_EEPROM_BAND5, 1944 IWN5000_EEPROM_BAND6, 1945 IWN5000_EEPROM_BAND7 1946 }; 1947 1948 static const uint32_t iwn6000_regulatory_bands[IWN_NBANDS] = { 1949 IWN5000_EEPROM_BAND1, 1950 IWN5000_EEPROM_BAND2, 1951 IWN5000_EEPROM_BAND3, 1952 IWN5000_EEPROM_BAND4, 1953 IWN5000_EEPROM_BAND5, 1954 IWN6000_EEPROM_BAND6, 1955 IWN5000_EEPROM_BAND7 1956 }; 1957 1958 static const uint32_t iwn1000_regulatory_bands[IWN_NBANDS] = { 1959 IWN5000_EEPROM_BAND1, 1960 IWN5000_EEPROM_BAND2, 1961 IWN5000_EEPROM_BAND3, 1962 IWN5000_EEPROM_BAND4, 1963 IWN5000_EEPROM_BAND5, 1964 IWN5000_EEPROM_BAND6, 1965 IWN5000_EEPROM_NO_HT40, 1966 }; 1967 1968 static const uint32_t iwn2030_regulatory_bands[IWN_NBANDS] = { 1969 IWN5000_EEPROM_BAND1, 1970 IWN5000_EEPROM_BAND2, 1971 IWN5000_EEPROM_BAND3, 1972 IWN5000_EEPROM_BAND4, 1973 IWN5000_EEPROM_BAND5, 1974 IWN6000_EEPROM_BAND6, 1975 IWN5000_EEPROM_BAND7 1976 }; 1977 1978 #define IWN_CHAN_BANDS_COUNT 7 1979 #define IWN_MAX_CHAN_PER_BAND 14 1980 static const struct iwn_chan_band { 1981 uint8_t nchan; 1982 uint8_t chan[IWN_MAX_CHAN_PER_BAND]; 1983 } iwn_bands[] = { 1984 /* 20MHz channels, 2GHz band. */ 1985 { 14, { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 1986 /* 20MHz channels, 5GHz band. */ 1987 { 13, { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 1988 { 12, { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 1989 { 11, { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 1990 { 6, { 145, 149, 153, 157, 161, 165 } }, 1991 /* 40MHz channels (primary channels), 2GHz band. */ 1992 { 7, { 1, 2, 3, 4, 5, 6, 7 } }, 1993 /* 40MHz channels (primary channels), 5GHz band. */ 1994 { 11, { 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 } } 1995 }; 1996 1997 static const uint8_t iwn_bss_ac_to_queue[] = { 1998 2, 3, 1, 0, 1999 }; 2000 2001 static const uint8_t iwn_pan_ac_to_queue[] = { 2002 5, 4, 6, 7, 2003 }; 2004 #define IWN1000_OTP_NBLOCKS 3 2005 #define IWN6000_OTP_NBLOCKS 4 2006 #define IWN6050_OTP_NBLOCKS 7 2007 2008 /* HW rate indices. */ 2009 #define IWN_RIDX_CCK1 0 2010 #define IWN_RIDX_OFDM6 4 2011 2012 #define IWN4965_MAX_PWR_INDEX 107 2013 #define IWN_POWERSAVE_LVL_NONE 0 2014 #define IWN_POWERSAVE_LVL_VOIP_COMPATIBLE 1 2015 #define IWN_POWERSAVE_LVL_MAX 5 2016 2017 #define IWN_POWERSAVE_LVL_DEFAULT IWN_POWERSAVE_LVL_NONE 2018 2019 /* DTIM value to pass in for IWN_POWERSAVE_LVL_VOIP_COMPATIBLE */ 2020 #define IWN_POWERSAVE_DTIM_VOIP_COMPATIBLE 2 2021 2022 /* 2023 * RF Tx gain values from highest to lowest power (values obtained from 2024 * the reference driver.) 2025 */ 2026 static const uint8_t iwn4965_rf_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 2027 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 2028 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 0x39, 0x38, 2029 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 0x35, 0x35, 2030 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x31, 0x31, 2031 0x31, 0x30, 0x30, 0x30, 0x06, 0x06, 0x06, 0x05, 0x05, 0x05, 0x04, 2032 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 2033 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 2034 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 2035 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 2036 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 2037 }; 2038 2039 static const uint8_t iwn4965_rf_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 2040 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 2041 0x3c, 0x3c, 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 2042 0x39, 0x38, 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 2043 0x35, 0x35, 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 2044 0x31, 0x31, 0x31, 0x30, 0x30, 0x30, 0x25, 0x25, 0x25, 0x24, 0x24, 2045 0x24, 0x23, 0x23, 0x23, 0x22, 0x18, 0x18, 0x17, 0x17, 0x17, 0x16, 2046 0x16, 0x16, 0x15, 0x15, 0x15, 0x14, 0x14, 0x14, 0x13, 0x13, 0x13, 2047 0x12, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x06, 0x05, 0x05, 2048 0x05, 0x04, 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 2049 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 2050 }; 2051 2052 /* 2053 * DSP pre-DAC gain values from highest to lowest power (values obtained 2054 * from the reference driver.) 2055 */ 2056 static const uint8_t iwn4965_dsp_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 2057 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 2058 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 2059 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 2060 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 2061 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 2062 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 2063 0x6e, 0x68, 0x62, 0x61, 0x60, 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a, 2064 0x59, 0x58, 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50, 0x4f, 2065 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44, 2066 0x43, 0x42, 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b 2067 }; 2068 2069 static const uint8_t iwn4965_dsp_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 2070 0x7b, 0x75, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 2071 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 2072 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 2073 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 2074 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 2075 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 2076 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 2077 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 2078 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 2079 0x68, 0x62, 0x6e, 0x68, 0x62, 0x5d, 0x58, 0x53, 0x4e 2080 }; 2081 2082 /* 2083 * Power saving settings (values obtained from the reference driver.) 2084 */ 2085 #define IWN_NDTIMRANGES 3 2086 #define IWN_NPOWERLEVELS 6 2087 static const struct iwn_pmgt { 2088 uint32_t rxtimeout; 2089 uint32_t txtimeout; 2090 uint32_t intval[5]; 2091 int skip_dtim; 2092 } iwn_pmgt[IWN_NDTIMRANGES][IWN_NPOWERLEVELS] = { 2093 /* DTIM <= 2 */ 2094 { 2095 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 2096 { 200, 500, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 1 */ 2097 { 200, 300, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 2 */ 2098 { 50, 100, { 2, 2, 2, 2, -1 }, 0 }, /* PS level 3 */ 2099 { 50, 25, { 2, 2, 4, 4, -1 }, 1 }, /* PS level 4 */ 2100 { 25, 25, { 2, 2, 4, 6, -1 }, 2 } /* PS level 5 */ 2101 }, 2102 /* 3 <= DTIM <= 10 */ 2103 { 2104 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 2105 { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */ 2106 { 200, 300, { 1, 2, 3, 4, 7 }, 0 }, /* PS level 2 */ 2107 { 50, 100, { 2, 4, 6, 7, 9 }, 0 }, /* PS level 3 */ 2108 { 50, 25, { 2, 4, 6, 9, 10 }, 1 }, /* PS level 4 */ 2109 { 25, 25, { 2, 4, 7, 10, 10 }, 2 } /* PS level 5 */ 2110 }, 2111 /* DTIM >= 11 */ 2112 { 2113 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 2114 { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */ 2115 { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */ 2116 { 50, 100, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 3 */ 2117 { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */ 2118 { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */ 2119 } 2120 }; 2121 2122 struct iwn_sensitivity_limits { 2123 uint32_t min_ofdm_x1; 2124 uint32_t max_ofdm_x1; 2125 uint32_t min_ofdm_mrc_x1; 2126 uint32_t max_ofdm_mrc_x1; 2127 uint32_t min_ofdm_x4; 2128 uint32_t max_ofdm_x4; 2129 uint32_t min_ofdm_mrc_x4; 2130 uint32_t max_ofdm_mrc_x4; 2131 uint32_t min_cck_x4; 2132 uint32_t max_cck_x4; 2133 uint32_t min_cck_mrc_x4; 2134 uint32_t max_cck_mrc_x4; 2135 uint32_t min_energy_cck; 2136 uint32_t energy_cck; 2137 uint32_t energy_ofdm; 2138 uint32_t barker_mrc; 2139 }; 2140 2141 /* 2142 * RX sensitivity limits (values obtained from the reference driver.) 2143 */ 2144 static const struct iwn_sensitivity_limits iwn4965_sensitivity_limits = { 2145 105, 140, 2146 220, 270, 2147 85, 120, 2148 170, 210, 2149 125, 200, 2150 200, 400, 2151 97, 2152 100, 2153 100, 2154 390 2155 }; 2156 2157 static const struct iwn_sensitivity_limits iwn5000_sensitivity_limits = { 2158 120, 120, /* min = max for performance bug in DSP. */ 2159 240, 240, /* min = max for performance bug in DSP. */ 2160 90, 120, 2161 170, 210, 2162 125, 200, 2163 170, 400, 2164 95, 2165 95, 2166 95, 2167 390 2168 }; 2169 2170 static const struct iwn_sensitivity_limits iwn5150_sensitivity_limits = { 2171 105, 105, /* min = max for performance bug in DSP. */ 2172 220, 220, /* min = max for performance bug in DSP. */ 2173 90, 120, 2174 170, 210, 2175 125, 200, 2176 170, 400, 2177 95, 2178 95, 2179 95, 2180 390, 2181 }; 2182 2183 static const struct iwn_sensitivity_limits iwn1000_sensitivity_limits = { 2184 120, 155, 2185 240, 290, 2186 90, 120, 2187 170, 210, 2188 125, 200, 2189 170, 400, 2190 95, 2191 95, 2192 95, 2193 390, 2194 }; 2195 2196 static const struct iwn_sensitivity_limits iwn6000_sensitivity_limits = { 2197 105, 110, 2198 192, 232, 2199 80, 145, 2200 128, 232, 2201 125, 175, 2202 160, 310, 2203 97, 2204 97, 2205 100, 2206 390 2207 }; 2208 2209 static const struct iwn_sensitivity_limits iwn6235_sensitivity_limits = { 2210 105, 110, 2211 192, 232, 2212 80, 145, 2213 128, 232, 2214 125, 175, 2215 160, 310, 2216 100, 2217 110, 2218 110, 2219 336 2220 }; 2221 2222 2223 /* Get value from linux kernel 3.2.+ in Drivers/net/wireless/iwlwifi/iwl-2000.c*/ 2224 static const struct iwn_sensitivity_limits iwn2030_sensitivity_limits = { 2225 105,110, 2226 128,232, 2227 80,145, 2228 128,232, 2229 125,175, 2230 160,310, 2231 97, 2232 97, 2233 110 2234 }; 2235 2236 /* Map TID to TX scheduler's FIFO. */ 2237 static const uint8_t iwn_tid2fifo[] = { 2238 1, 0, 0, 1, 2, 2, 3, 3, 7, 7, 7, 7, 7, 7, 7, 7, 3 2239 }; 2240 2241 /* WiFi/WiMAX coexist event priority table for 6050. */ 2242 static const struct iwn5000_wimax_event iwn6050_wimax_events[] = { 2243 { 0x04, 0x03, 0x00, 0x00 }, 2244 { 0x04, 0x03, 0x00, 0x03 }, 2245 { 0x04, 0x03, 0x00, 0x03 }, 2246 { 0x04, 0x03, 0x00, 0x03 }, 2247 { 0x04, 0x03, 0x00, 0x00 }, 2248 { 0x04, 0x03, 0x00, 0x07 }, 2249 { 0x04, 0x03, 0x00, 0x00 }, 2250 { 0x04, 0x03, 0x00, 0x03 }, 2251 { 0x04, 0x03, 0x00, 0x03 }, 2252 { 0x04, 0x03, 0x00, 0x00 }, 2253 { 0x06, 0x03, 0x00, 0x07 }, 2254 { 0x04, 0x03, 0x00, 0x00 }, 2255 { 0x06, 0x06, 0x00, 0x03 }, 2256 { 0x04, 0x03, 0x00, 0x07 }, 2257 { 0x04, 0x03, 0x00, 0x00 }, 2258 { 0x04, 0x03, 0x00, 0x00 } 2259 }; 2260 2261 /* Firmware errors. */ 2262 static const char * const iwn_fw_errmsg[] = { 2263 "OK", 2264 "FAIL", 2265 "BAD_PARAM", 2266 "BAD_CHECKSUM", 2267 "NMI_INTERRUPT_WDG", 2268 "SYSASSERT", 2269 "FATAL_ERROR", 2270 "BAD_COMMAND", 2271 "HW_ERROR_TUNE_LOCK", 2272 "HW_ERROR_TEMPERATURE", 2273 "ILLEGAL_CHAN_FREQ", 2274 "VCC_NOT_STABLE", 2275 "FH_ERROR", 2276 "NMI_INTERRUPT_HOST", 2277 "NMI_INTERRUPT_ACTION_PT", 2278 "NMI_INTERRUPT_UNKNOWN", 2279 "UCODE_VERSION_MISMATCH", 2280 "HW_ERROR_ABS_LOCK", 2281 "HW_ERROR_CAL_LOCK_FAIL", 2282 "NMI_INTERRUPT_INST_ACTION_PT", 2283 "NMI_INTERRUPT_DATA_ACTION_PT", 2284 "NMI_TRM_HW_ER", 2285 "NMI_INTERRUPT_TRM", 2286 "NMI_INTERRUPT_BREAKPOINT", 2287 "DEBUG_0", 2288 "DEBUG_1", 2289 "DEBUG_2", 2290 "DEBUG_3", 2291 "ADVANCED_SYSASSERT" 2292 }; 2293 2294 /* Find least significant bit that is set. */ 2295 #define IWN_LSB(x) ((((x) - 1) & (x)) ^ (x)) 2296 2297 #define IWN_READ(sc, reg) \ 2298 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 2299 2300 #define IWN_WRITE(sc, reg, val) \ 2301 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 2302 2303 #define IWN_WRITE_1(sc, reg, val) \ 2304 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 2305 2306 #define IWN_SETBITS(sc, reg, mask) \ 2307 IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask)) 2308 2309 #define IWN_CLRBITS(sc, reg, mask) \ 2310 IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask)) 2311 2312 #define IWN_BARRIER_WRITE(sc) \ 2313 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 2314 BUS_SPACE_BARRIER_WRITE) 2315 2316 #define IWN_BARRIER_READ_WRITE(sc) \ 2317 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 2318 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 2319 2320 #endif /* __IF_IWNREG_H__ */ 2321