1 /****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2017, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 ******************************************************************************/ 34 /*$FreeBSD$*/ 35 36 #include "ixgbe_api.h" 37 #include "ixgbe_common.h" 38 39 #define IXGBE_EMPTY_PARAM 40 41 static const u32 ixgbe_mvals_base[IXGBE_MVALS_IDX_LIMIT] = { 42 IXGBE_MVALS_INIT(IXGBE_EMPTY_PARAM) 43 }; 44 45 static const u32 ixgbe_mvals_X540[IXGBE_MVALS_IDX_LIMIT] = { 46 IXGBE_MVALS_INIT(_X540) 47 }; 48 49 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = { 50 IXGBE_MVALS_INIT(_X550) 51 }; 52 53 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = { 54 IXGBE_MVALS_INIT(_X550EM_x) 55 }; 56 57 static const u32 ixgbe_mvals_X550EM_a[IXGBE_MVALS_IDX_LIMIT] = { 58 IXGBE_MVALS_INIT(_X550EM_a) 59 }; 60 61 /** 62 * ixgbe_dcb_get_rtrup2tc - read rtrup2tc reg 63 * @hw: pointer to hardware structure 64 * @map: pointer to u8 arr for returning map 65 * 66 * Read the rtrup2tc HW register and resolve its content into map 67 **/ 68 void ixgbe_dcb_get_rtrup2tc(struct ixgbe_hw *hw, u8 *map) 69 { 70 if (hw->mac.ops.get_rtrup2tc) 71 hw->mac.ops.get_rtrup2tc(hw, map); 72 } 73 74 /** 75 * ixgbe_init_shared_code - Initialize the shared code 76 * @hw: pointer to hardware structure 77 * 78 * This will assign function pointers and assign the MAC type and PHY code. 79 * Does not touch the hardware. This function must be called prior to any 80 * other function in the shared code. The ixgbe_hw structure should be 81 * memset to 0 prior to calling this function. The following fields in 82 * hw structure should be filled in prior to calling this function: 83 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 84 * subsystem_vendor_id, and revision_id 85 **/ 86 s32 ixgbe_init_shared_code(struct ixgbe_hw *hw) 87 { 88 s32 status; 89 90 DEBUGFUNC("ixgbe_init_shared_code"); 91 92 /* 93 * Set the mac type 94 */ 95 ixgbe_set_mac_type(hw); 96 97 switch (hw->mac.type) { 98 case ixgbe_mac_82598EB: 99 status = ixgbe_init_ops_82598(hw); 100 break; 101 case ixgbe_mac_82599EB: 102 status = ixgbe_init_ops_82599(hw); 103 break; 104 case ixgbe_mac_X540: 105 status = ixgbe_init_ops_X540(hw); 106 break; 107 case ixgbe_mac_X550: 108 status = ixgbe_init_ops_X550(hw); 109 break; 110 case ixgbe_mac_X550EM_x: 111 status = ixgbe_init_ops_X550EM_x(hw); 112 break; 113 case ixgbe_mac_X550EM_a: 114 status = ixgbe_init_ops_X550EM_a(hw); 115 break; 116 default: 117 status = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 118 break; 119 } 120 hw->mac.max_link_up_time = IXGBE_LINK_UP_TIME; 121 122 return status; 123 } 124 125 /** 126 * ixgbe_set_mac_type - Sets MAC type 127 * @hw: pointer to the HW structure 128 * 129 * This function sets the mac type of the adapter based on the 130 * vendor ID and device ID stored in the hw structure. 131 **/ 132 s32 ixgbe_set_mac_type(struct ixgbe_hw *hw) 133 { 134 s32 ret_val = IXGBE_SUCCESS; 135 136 DEBUGFUNC("ixgbe_set_mac_type\n"); 137 138 if (hw->vendor_id != IXGBE_INTEL_VENDOR_ID) { 139 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 140 "Unsupported vendor id: %x", hw->vendor_id); 141 return IXGBE_ERR_DEVICE_NOT_SUPPORTED; 142 } 143 144 hw->mvals = ixgbe_mvals_base; 145 146 switch (hw->device_id) { 147 case IXGBE_DEV_ID_82598: 148 case IXGBE_DEV_ID_82598_BX: 149 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 150 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 151 case IXGBE_DEV_ID_82598AT: 152 case IXGBE_DEV_ID_82598AT2: 153 case IXGBE_DEV_ID_82598EB_CX4: 154 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 155 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 156 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 157 case IXGBE_DEV_ID_82598EB_XF_LR: 158 case IXGBE_DEV_ID_82598EB_SFP_LOM: 159 hw->mac.type = ixgbe_mac_82598EB; 160 break; 161 case IXGBE_DEV_ID_82599_KX4: 162 case IXGBE_DEV_ID_82599_KX4_MEZZ: 163 case IXGBE_DEV_ID_82599_XAUI_LOM: 164 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 165 case IXGBE_DEV_ID_82599_KR: 166 case IXGBE_DEV_ID_82599_SFP: 167 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 168 case IXGBE_DEV_ID_82599_SFP_FCOE: 169 case IXGBE_DEV_ID_82599_SFP_EM: 170 case IXGBE_DEV_ID_82599_SFP_SF2: 171 case IXGBE_DEV_ID_82599_SFP_SF_QP: 172 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 173 case IXGBE_DEV_ID_82599EN_SFP: 174 case IXGBE_DEV_ID_82599_CX4: 175 case IXGBE_DEV_ID_82599_BYPASS: 176 case IXGBE_DEV_ID_82599_T3_LOM: 177 hw->mac.type = ixgbe_mac_82599EB; 178 break; 179 case IXGBE_DEV_ID_X540T: 180 case IXGBE_DEV_ID_X540T1: 181 case IXGBE_DEV_ID_X540_BYPASS: 182 hw->mac.type = ixgbe_mac_X540; 183 hw->mvals = ixgbe_mvals_X540; 184 break; 185 case IXGBE_DEV_ID_X550T: 186 case IXGBE_DEV_ID_X550T1: 187 hw->mac.type = ixgbe_mac_X550; 188 hw->mvals = ixgbe_mvals_X550; 189 break; 190 case IXGBE_DEV_ID_X550EM_X_KX4: 191 case IXGBE_DEV_ID_X550EM_X_KR: 192 case IXGBE_DEV_ID_X550EM_X_10G_T: 193 case IXGBE_DEV_ID_X550EM_X_1G_T: 194 case IXGBE_DEV_ID_X550EM_X_SFP: 195 case IXGBE_DEV_ID_X550EM_X_XFI: 196 hw->mac.type = ixgbe_mac_X550EM_x; 197 hw->mvals = ixgbe_mvals_X550EM_x; 198 break; 199 case IXGBE_DEV_ID_X550EM_A_KR: 200 case IXGBE_DEV_ID_X550EM_A_KR_L: 201 case IXGBE_DEV_ID_X550EM_A_SFP_N: 202 case IXGBE_DEV_ID_X550EM_A_SGMII: 203 case IXGBE_DEV_ID_X550EM_A_SGMII_L: 204 case IXGBE_DEV_ID_X550EM_A_1G_T: 205 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 206 case IXGBE_DEV_ID_X550EM_A_10G_T: 207 case IXGBE_DEV_ID_X550EM_A_QSFP: 208 case IXGBE_DEV_ID_X550EM_A_QSFP_N: 209 case IXGBE_DEV_ID_X550EM_A_SFP: 210 hw->mac.type = ixgbe_mac_X550EM_a; 211 hw->mvals = ixgbe_mvals_X550EM_a; 212 break; 213 default: 214 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 215 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 216 "Unsupported device id: %x", 217 hw->device_id); 218 break; 219 } 220 221 DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n", 222 hw->mac.type, ret_val); 223 return ret_val; 224 } 225 226 /** 227 * ixgbe_init_hw - Initialize the hardware 228 * @hw: pointer to hardware structure 229 * 230 * Initialize the hardware by resetting and then starting the hardware 231 **/ 232 s32 ixgbe_init_hw(struct ixgbe_hw *hw) 233 { 234 return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw), 235 IXGBE_NOT_IMPLEMENTED); 236 } 237 238 /** 239 * ixgbe_reset_hw - Performs a hardware reset 240 * @hw: pointer to hardware structure 241 * 242 * Resets the hardware by resetting the transmit and receive units, masks and 243 * clears all interrupts, performs a PHY reset, and performs a MAC reset 244 **/ 245 s32 ixgbe_reset_hw(struct ixgbe_hw *hw) 246 { 247 return ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw), 248 IXGBE_NOT_IMPLEMENTED); 249 } 250 251 /** 252 * ixgbe_start_hw - Prepares hardware for Rx/Tx 253 * @hw: pointer to hardware structure 254 * 255 * Starts the hardware by filling the bus info structure and media type, 256 * clears all on chip counters, initializes receive address registers, 257 * multicast table, VLAN filter table, calls routine to setup link and 258 * flow control settings, and leaves transmit and receive units disabled 259 * and uninitialized. 260 **/ 261 s32 ixgbe_start_hw(struct ixgbe_hw *hw) 262 { 263 return ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw), 264 IXGBE_NOT_IMPLEMENTED); 265 } 266 267 /** 268 * ixgbe_enable_relaxed_ordering - Enables tx relaxed ordering, 269 * which is disabled by default in ixgbe_start_hw(); 270 * 271 * @hw: pointer to hardware structure 272 * 273 * Enable relaxed ordering; 274 **/ 275 void ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw) 276 { 277 if (hw->mac.ops.enable_relaxed_ordering) 278 hw->mac.ops.enable_relaxed_ordering(hw); 279 } 280 281 /** 282 * ixgbe_clear_hw_cntrs - Clear hardware counters 283 * @hw: pointer to hardware structure 284 * 285 * Clears all hardware statistics counters by reading them from the hardware 286 * Statistics counters are clear on read. 287 **/ 288 s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw) 289 { 290 return ixgbe_call_func(hw, hw->mac.ops.clear_hw_cntrs, (hw), 291 IXGBE_NOT_IMPLEMENTED); 292 } 293 294 /** 295 * ixgbe_get_media_type - Get media type 296 * @hw: pointer to hardware structure 297 * 298 * Returns the media type (fiber, copper, backplane) 299 **/ 300 enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw) 301 { 302 return ixgbe_call_func(hw, hw->mac.ops.get_media_type, (hw), 303 ixgbe_media_type_unknown); 304 } 305 306 /** 307 * ixgbe_get_mac_addr - Get MAC address 308 * @hw: pointer to hardware structure 309 * @mac_addr: Adapter MAC address 310 * 311 * Reads the adapter's MAC address from the first Receive Address Register 312 * (RAR0) A reset of the adapter must have been performed prior to calling 313 * this function in order for the MAC address to have been loaded from the 314 * EEPROM into RAR0 315 **/ 316 s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr) 317 { 318 return ixgbe_call_func(hw, hw->mac.ops.get_mac_addr, 319 (hw, mac_addr), IXGBE_NOT_IMPLEMENTED); 320 } 321 322 /** 323 * ixgbe_get_san_mac_addr - Get SAN MAC address 324 * @hw: pointer to hardware structure 325 * @san_mac_addr: SAN MAC address 326 * 327 * Reads the SAN MAC address from the EEPROM, if it's available. This is 328 * per-port, so set_lan_id() must be called before reading the addresses. 329 **/ 330 s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 331 { 332 return ixgbe_call_func(hw, hw->mac.ops.get_san_mac_addr, 333 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 334 } 335 336 /** 337 * ixgbe_set_san_mac_addr - Write a SAN MAC address 338 * @hw: pointer to hardware structure 339 * @san_mac_addr: SAN MAC address 340 * 341 * Writes A SAN MAC address to the EEPROM. 342 **/ 343 s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 344 { 345 return ixgbe_call_func(hw, hw->mac.ops.set_san_mac_addr, 346 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 347 } 348 349 /** 350 * ixgbe_get_device_caps - Get additional device capabilities 351 * @hw: pointer to hardware structure 352 * @device_caps: the EEPROM word for device capabilities 353 * 354 * Reads the extra device capabilities from the EEPROM 355 **/ 356 s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps) 357 { 358 return ixgbe_call_func(hw, hw->mac.ops.get_device_caps, 359 (hw, device_caps), IXGBE_NOT_IMPLEMENTED); 360 } 361 362 /** 363 * ixgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from the EEPROM 364 * @hw: pointer to hardware structure 365 * @wwnn_prefix: the alternative WWNN prefix 366 * @wwpn_prefix: the alternative WWPN prefix 367 * 368 * This function will read the EEPROM from the alternative SAN MAC address 369 * block to check the support for the alternative WWNN/WWPN prefix support. 370 **/ 371 s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix, 372 u16 *wwpn_prefix) 373 { 374 return ixgbe_call_func(hw, hw->mac.ops.get_wwn_prefix, 375 (hw, wwnn_prefix, wwpn_prefix), 376 IXGBE_NOT_IMPLEMENTED); 377 } 378 379 /** 380 * ixgbe_get_fcoe_boot_status - Get FCOE boot status from EEPROM 381 * @hw: pointer to hardware structure 382 * @bs: the fcoe boot status 383 * 384 * This function will read the FCOE boot status from the iSCSI FCOE block 385 **/ 386 s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs) 387 { 388 return ixgbe_call_func(hw, hw->mac.ops.get_fcoe_boot_status, 389 (hw, bs), 390 IXGBE_NOT_IMPLEMENTED); 391 } 392 393 /** 394 * ixgbe_get_bus_info - Set PCI bus info 395 * @hw: pointer to hardware structure 396 * 397 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 398 **/ 399 s32 ixgbe_get_bus_info(struct ixgbe_hw *hw) 400 { 401 return ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw), 402 IXGBE_NOT_IMPLEMENTED); 403 } 404 405 /** 406 * ixgbe_get_num_of_tx_queues - Get Tx queues 407 * @hw: pointer to hardware structure 408 * 409 * Returns the number of transmit queues for the given adapter. 410 **/ 411 u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw) 412 { 413 return hw->mac.max_tx_queues; 414 } 415 416 /** 417 * ixgbe_get_num_of_rx_queues - Get Rx queues 418 * @hw: pointer to hardware structure 419 * 420 * Returns the number of receive queues for the given adapter. 421 **/ 422 u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw) 423 { 424 return hw->mac.max_rx_queues; 425 } 426 427 /** 428 * ixgbe_stop_adapter - Disable Rx/Tx units 429 * @hw: pointer to hardware structure 430 * 431 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 432 * disables transmit and receive units. The adapter_stopped flag is used by 433 * the shared code and drivers to determine if the adapter is in a stopped 434 * state and should not touch the hardware. 435 **/ 436 s32 ixgbe_stop_adapter(struct ixgbe_hw *hw) 437 { 438 return ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw), 439 IXGBE_NOT_IMPLEMENTED); 440 } 441 442 /** 443 * ixgbe_read_pba_string - Reads part number string from EEPROM 444 * @hw: pointer to hardware structure 445 * @pba_num: stores the part number string from the EEPROM 446 * @pba_num_size: part number string buffer length 447 * 448 * Reads the part number string from the EEPROM. 449 **/ 450 s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size) 451 { 452 return ixgbe_read_pba_string_generic(hw, pba_num, pba_num_size); 453 } 454 455 /** 456 * ixgbe_read_pba_num - Reads part number from EEPROM 457 * @hw: pointer to hardware structure 458 * @pba_num: stores the part number from the EEPROM 459 * 460 * Reads the part number from the EEPROM. 461 **/ 462 s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num) 463 { 464 return ixgbe_read_pba_num_generic(hw, pba_num); 465 } 466 467 /** 468 * ixgbe_identify_phy - Get PHY type 469 * @hw: pointer to hardware structure 470 * 471 * Determines the physical layer module found on the current adapter. 472 **/ 473 s32 ixgbe_identify_phy(struct ixgbe_hw *hw) 474 { 475 s32 status = IXGBE_SUCCESS; 476 477 if (hw->phy.type == ixgbe_phy_unknown) { 478 status = ixgbe_call_func(hw, hw->phy.ops.identify, (hw), 479 IXGBE_NOT_IMPLEMENTED); 480 } 481 482 return status; 483 } 484 485 /** 486 * ixgbe_reset_phy - Perform a PHY reset 487 * @hw: pointer to hardware structure 488 **/ 489 s32 ixgbe_reset_phy(struct ixgbe_hw *hw) 490 { 491 s32 status = IXGBE_SUCCESS; 492 493 if (hw->phy.type == ixgbe_phy_unknown) { 494 if (ixgbe_identify_phy(hw) != IXGBE_SUCCESS) 495 status = IXGBE_ERR_PHY; 496 } 497 498 if (status == IXGBE_SUCCESS) { 499 status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw), 500 IXGBE_NOT_IMPLEMENTED); 501 } 502 return status; 503 } 504 505 /** 506 * ixgbe_get_phy_firmware_version - 507 * @hw: pointer to hardware structure 508 * @firmware_version: pointer to firmware version 509 **/ 510 s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version) 511 { 512 s32 status = IXGBE_SUCCESS; 513 514 status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version, 515 (hw, firmware_version), 516 IXGBE_NOT_IMPLEMENTED); 517 return status; 518 } 519 520 /** 521 * ixgbe_read_phy_reg - Read PHY register 522 * @hw: pointer to hardware structure 523 * @reg_addr: 32 bit address of PHY register to read 524 * @phy_data: Pointer to read data from PHY register 525 * 526 * Reads a value from a specified PHY register 527 **/ 528 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 529 u16 *phy_data) 530 { 531 if (hw->phy.id == 0) 532 ixgbe_identify_phy(hw); 533 534 return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr, 535 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 536 } 537 538 /** 539 * ixgbe_write_phy_reg - Write PHY register 540 * @hw: pointer to hardware structure 541 * @reg_addr: 32 bit PHY register to write 542 * @phy_data: Data to write to the PHY register 543 * 544 * Writes a value to specified PHY register 545 **/ 546 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 547 u16 phy_data) 548 { 549 if (hw->phy.id == 0) 550 ixgbe_identify_phy(hw); 551 552 return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr, 553 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 554 } 555 556 /** 557 * ixgbe_setup_phy_link - Restart PHY autoneg 558 * @hw: pointer to hardware structure 559 * 560 * Restart autonegotiation and PHY and waits for completion. 561 **/ 562 s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw) 563 { 564 return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw), 565 IXGBE_NOT_IMPLEMENTED); 566 } 567 568 /** 569 * ixgbe_setup_internal_phy - Configure integrated PHY 570 * @hw: pointer to hardware structure 571 * 572 * Reconfigure the integrated PHY in order to enable talk to the external PHY. 573 * Returns success if not implemented, since nothing needs to be done in this 574 * case. 575 */ 576 s32 ixgbe_setup_internal_phy(struct ixgbe_hw *hw) 577 { 578 return ixgbe_call_func(hw, hw->phy.ops.setup_internal_link, (hw), 579 IXGBE_SUCCESS); 580 } 581 582 /** 583 * ixgbe_check_phy_link - Determine link and speed status 584 * @hw: pointer to hardware structure 585 * 586 * Reads a PHY register to determine if link is up and the current speed for 587 * the PHY. 588 **/ 589 s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 590 bool *link_up) 591 { 592 return ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed, 593 link_up), IXGBE_NOT_IMPLEMENTED); 594 } 595 596 /** 597 * ixgbe_setup_phy_link_speed - Set auto advertise 598 * @hw: pointer to hardware structure 599 * @speed: new link speed 600 * 601 * Sets the auto advertised capabilities 602 **/ 603 s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed, 604 bool autoneg_wait_to_complete) 605 { 606 return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed, 607 autoneg_wait_to_complete), 608 IXGBE_NOT_IMPLEMENTED); 609 } 610 611 /** 612 * ixgbe_set_phy_power - Control the phy power state 613 * @hw: pointer to hardware structure 614 * @on: TRUE for on, FALSE for off 615 */ 616 s32 ixgbe_set_phy_power(struct ixgbe_hw *hw, bool on) 617 { 618 return ixgbe_call_func(hw, hw->phy.ops.set_phy_power, (hw, on), 619 IXGBE_NOT_IMPLEMENTED); 620 } 621 622 /** 623 * ixgbe_check_link - Get link and speed status 624 * @hw: pointer to hardware structure 625 * 626 * Reads the links register to determine if link is up and the current speed 627 **/ 628 s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 629 bool *link_up, bool link_up_wait_to_complete) 630 { 631 return ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed, 632 link_up, link_up_wait_to_complete), 633 IXGBE_NOT_IMPLEMENTED); 634 } 635 636 /** 637 * ixgbe_disable_tx_laser - Disable Tx laser 638 * @hw: pointer to hardware structure 639 * 640 * If the driver needs to disable the laser on SFI optics. 641 **/ 642 void ixgbe_disable_tx_laser(struct ixgbe_hw *hw) 643 { 644 if (hw->mac.ops.disable_tx_laser) 645 hw->mac.ops.disable_tx_laser(hw); 646 } 647 648 /** 649 * ixgbe_enable_tx_laser - Enable Tx laser 650 * @hw: pointer to hardware structure 651 * 652 * If the driver needs to enable the laser on SFI optics. 653 **/ 654 void ixgbe_enable_tx_laser(struct ixgbe_hw *hw) 655 { 656 if (hw->mac.ops.enable_tx_laser) 657 hw->mac.ops.enable_tx_laser(hw); 658 } 659 660 /** 661 * ixgbe_flap_tx_laser - flap Tx laser to start autotry process 662 * @hw: pointer to hardware structure 663 * 664 * When the driver changes the link speeds that it can support then 665 * flap the tx laser to alert the link partner to start autotry 666 * process on its end. 667 **/ 668 void ixgbe_flap_tx_laser(struct ixgbe_hw *hw) 669 { 670 if (hw->mac.ops.flap_tx_laser) 671 hw->mac.ops.flap_tx_laser(hw); 672 } 673 674 /** 675 * ixgbe_setup_link - Set link speed 676 * @hw: pointer to hardware structure 677 * @speed: new link speed 678 * 679 * Configures link settings. Restarts the link. 680 * Performs autonegotiation if needed. 681 **/ 682 s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 683 bool autoneg_wait_to_complete) 684 { 685 return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed, 686 autoneg_wait_to_complete), 687 IXGBE_NOT_IMPLEMENTED); 688 } 689 690 /** 691 * ixgbe_setup_mac_link - Set link speed 692 * @hw: pointer to hardware structure 693 * @speed: new link speed 694 * 695 * Configures link settings. Restarts the link. 696 * Performs autonegotiation if needed. 697 **/ 698 s32 ixgbe_setup_mac_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 699 bool autoneg_wait_to_complete) 700 { 701 return ixgbe_call_func(hw, hw->mac.ops.setup_mac_link, (hw, speed, 702 autoneg_wait_to_complete), 703 IXGBE_NOT_IMPLEMENTED); 704 } 705 706 /** 707 * ixgbe_get_link_capabilities - Returns link capabilities 708 * @hw: pointer to hardware structure 709 * 710 * Determines the link capabilities of the current configuration. 711 **/ 712 s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 713 bool *autoneg) 714 { 715 return ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw, 716 speed, autoneg), IXGBE_NOT_IMPLEMENTED); 717 } 718 719 /** 720 * ixgbe_led_on - Turn on LEDs 721 * @hw: pointer to hardware structure 722 * @index: led number to turn on 723 * 724 * Turns on the software controllable LEDs. 725 **/ 726 s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index) 727 { 728 return ixgbe_call_func(hw, hw->mac.ops.led_on, (hw, index), 729 IXGBE_NOT_IMPLEMENTED); 730 } 731 732 /** 733 * ixgbe_led_off - Turn off LEDs 734 * @hw: pointer to hardware structure 735 * @index: led number to turn off 736 * 737 * Turns off the software controllable LEDs. 738 **/ 739 s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index) 740 { 741 return ixgbe_call_func(hw, hw->mac.ops.led_off, (hw, index), 742 IXGBE_NOT_IMPLEMENTED); 743 } 744 745 /** 746 * ixgbe_blink_led_start - Blink LEDs 747 * @hw: pointer to hardware structure 748 * @index: led number to blink 749 * 750 * Blink LED based on index. 751 **/ 752 s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index) 753 { 754 return ixgbe_call_func(hw, hw->mac.ops.blink_led_start, (hw, index), 755 IXGBE_NOT_IMPLEMENTED); 756 } 757 758 /** 759 * ixgbe_blink_led_stop - Stop blinking LEDs 760 * @hw: pointer to hardware structure 761 * 762 * Stop blinking LED based on index. 763 **/ 764 s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index) 765 { 766 return ixgbe_call_func(hw, hw->mac.ops.blink_led_stop, (hw, index), 767 IXGBE_NOT_IMPLEMENTED); 768 } 769 770 /** 771 * ixgbe_init_eeprom_params - Initialize EEPROM parameters 772 * @hw: pointer to hardware structure 773 * 774 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 775 * ixgbe_hw struct in order to set up EEPROM access. 776 **/ 777 s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw) 778 { 779 return ixgbe_call_func(hw, hw->eeprom.ops.init_params, (hw), 780 IXGBE_NOT_IMPLEMENTED); 781 } 782 783 784 /** 785 * ixgbe_write_eeprom - Write word to EEPROM 786 * @hw: pointer to hardware structure 787 * @offset: offset within the EEPROM to be written to 788 * @data: 16 bit word to be written to the EEPROM 789 * 790 * Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not 791 * called after this function, the EEPROM will most likely contain an 792 * invalid checksum. 793 **/ 794 s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data) 795 { 796 return ixgbe_call_func(hw, hw->eeprom.ops.write, (hw, offset, data), 797 IXGBE_NOT_IMPLEMENTED); 798 } 799 800 /** 801 * ixgbe_write_eeprom_buffer - Write word(s) to EEPROM 802 * @hw: pointer to hardware structure 803 * @offset: offset within the EEPROM to be written to 804 * @data: 16 bit word(s) to be written to the EEPROM 805 * @words: number of words 806 * 807 * Writes 16 bit word(s) to EEPROM. If ixgbe_eeprom_update_checksum is not 808 * called after this function, the EEPROM will most likely contain an 809 * invalid checksum. 810 **/ 811 s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, u16 words, 812 u16 *data) 813 { 814 return ixgbe_call_func(hw, hw->eeprom.ops.write_buffer, 815 (hw, offset, words, data), 816 IXGBE_NOT_IMPLEMENTED); 817 } 818 819 /** 820 * ixgbe_read_eeprom - Read word from EEPROM 821 * @hw: pointer to hardware structure 822 * @offset: offset within the EEPROM to be read 823 * @data: read 16 bit value from EEPROM 824 * 825 * Reads 16 bit value from EEPROM 826 **/ 827 s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data) 828 { 829 return ixgbe_call_func(hw, hw->eeprom.ops.read, (hw, offset, data), 830 IXGBE_NOT_IMPLEMENTED); 831 } 832 833 /** 834 * ixgbe_read_eeprom_buffer - Read word(s) from EEPROM 835 * @hw: pointer to hardware structure 836 * @offset: offset within the EEPROM to be read 837 * @data: read 16 bit word(s) from EEPROM 838 * @words: number of words 839 * 840 * Reads 16 bit word(s) from EEPROM 841 **/ 842 s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, 843 u16 words, u16 *data) 844 { 845 return ixgbe_call_func(hw, hw->eeprom.ops.read_buffer, 846 (hw, offset, words, data), 847 IXGBE_NOT_IMPLEMENTED); 848 } 849 850 /** 851 * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum 852 * @hw: pointer to hardware structure 853 * @checksum_val: calculated checksum 854 * 855 * Performs checksum calculation and validates the EEPROM checksum 856 **/ 857 s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val) 858 { 859 return ixgbe_call_func(hw, hw->eeprom.ops.validate_checksum, 860 (hw, checksum_val), IXGBE_NOT_IMPLEMENTED); 861 } 862 863 /** 864 * ixgbe_eeprom_update_checksum - Updates the EEPROM checksum 865 * @hw: pointer to hardware structure 866 **/ 867 s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw) 868 { 869 return ixgbe_call_func(hw, hw->eeprom.ops.update_checksum, (hw), 870 IXGBE_NOT_IMPLEMENTED); 871 } 872 873 /** 874 * ixgbe_insert_mac_addr - Find a RAR for this mac address 875 * @hw: pointer to hardware structure 876 * @addr: Address to put into receive address register 877 * @vmdq: VMDq pool to assign 878 * 879 * Puts an ethernet address into a receive address register, or 880 * finds the rar that it is already in; adds to the pool list 881 **/ 882 s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 883 { 884 return ixgbe_call_func(hw, hw->mac.ops.insert_mac_addr, 885 (hw, addr, vmdq), 886 IXGBE_NOT_IMPLEMENTED); 887 } 888 889 /** 890 * ixgbe_set_rar - Set Rx address register 891 * @hw: pointer to hardware structure 892 * @index: Receive address register to write 893 * @addr: Address to put into receive address register 894 * @vmdq: VMDq "set" 895 * @enable_addr: set flag that address is active 896 * 897 * Puts an ethernet address into a receive address register. 898 **/ 899 s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 900 u32 enable_addr) 901 { 902 return ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq, 903 enable_addr), IXGBE_NOT_IMPLEMENTED); 904 } 905 906 /** 907 * ixgbe_clear_rar - Clear Rx address register 908 * @hw: pointer to hardware structure 909 * @index: Receive address register to write 910 * 911 * Puts an ethernet address into a receive address register. 912 **/ 913 s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index) 914 { 915 return ixgbe_call_func(hw, hw->mac.ops.clear_rar, (hw, index), 916 IXGBE_NOT_IMPLEMENTED); 917 } 918 919 /** 920 * ixgbe_set_vmdq - Associate a VMDq index with a receive address 921 * @hw: pointer to hardware structure 922 * @rar: receive address register index to associate with VMDq index 923 * @vmdq: VMDq set or pool index 924 **/ 925 s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 926 { 927 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq), 928 IXGBE_NOT_IMPLEMENTED); 929 930 } 931 932 /** 933 * ixgbe_set_vmdq_san_mac - Associate VMDq index 127 with a receive address 934 * @hw: pointer to hardware structure 935 * @vmdq: VMDq default pool index 936 **/ 937 s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq) 938 { 939 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq_san_mac, 940 (hw, vmdq), IXGBE_NOT_IMPLEMENTED); 941 } 942 943 /** 944 * ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address 945 * @hw: pointer to hardware structure 946 * @rar: receive address register index to disassociate with VMDq index 947 * @vmdq: VMDq set or pool index 948 **/ 949 s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 950 { 951 return ixgbe_call_func(hw, hw->mac.ops.clear_vmdq, (hw, rar, vmdq), 952 IXGBE_NOT_IMPLEMENTED); 953 } 954 955 /** 956 * ixgbe_init_rx_addrs - Initializes receive address filters. 957 * @hw: pointer to hardware structure 958 * 959 * Places the MAC address in receive address register 0 and clears the rest 960 * of the receive address registers. Clears the multicast table. Assumes 961 * the receiver is in reset when the routine is called. 962 **/ 963 s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw) 964 { 965 return ixgbe_call_func(hw, hw->mac.ops.init_rx_addrs, (hw), 966 IXGBE_NOT_IMPLEMENTED); 967 } 968 969 /** 970 * ixgbe_get_num_rx_addrs - Returns the number of RAR entries. 971 * @hw: pointer to hardware structure 972 **/ 973 u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw) 974 { 975 return hw->mac.num_rar_entries; 976 } 977 978 /** 979 * ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses 980 * @hw: pointer to hardware structure 981 * @addr_list: the list of new multicast addresses 982 * @addr_count: number of addresses 983 * @func: iterator function to walk the multicast address list 984 * 985 * The given list replaces any existing list. Clears the secondary addrs from 986 * receive address registers. Uses unused receive address registers for the 987 * first secondary addresses, and falls back to promiscuous mode as needed. 988 **/ 989 s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list, 990 u32 addr_count, ixgbe_mc_addr_itr func) 991 { 992 return ixgbe_call_func(hw, hw->mac.ops.update_uc_addr_list, (hw, 993 addr_list, addr_count, func), 994 IXGBE_NOT_IMPLEMENTED); 995 } 996 997 /** 998 * ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses 999 * @hw: pointer to hardware structure 1000 * @mc_addr_list: the list of new multicast addresses 1001 * @mc_addr_count: number of addresses 1002 * @func: iterator function to walk the multicast address list 1003 * 1004 * The given list replaces any existing list. Clears the MC addrs from receive 1005 * address registers and the multicast table. Uses unused receive address 1006 * registers for the first multicast addresses, and hashes the rest into the 1007 * multicast table. 1008 **/ 1009 s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list, 1010 u32 mc_addr_count, ixgbe_mc_addr_itr func, 1011 bool clear) 1012 { 1013 return ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw, 1014 mc_addr_list, mc_addr_count, func, clear), 1015 IXGBE_NOT_IMPLEMENTED); 1016 } 1017 1018 /** 1019 * ixgbe_enable_mc - Enable multicast address in RAR 1020 * @hw: pointer to hardware structure 1021 * 1022 * Enables multicast address in RAR and the use of the multicast hash table. 1023 **/ 1024 s32 ixgbe_enable_mc(struct ixgbe_hw *hw) 1025 { 1026 return ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw), 1027 IXGBE_NOT_IMPLEMENTED); 1028 } 1029 1030 /** 1031 * ixgbe_disable_mc - Disable multicast address in RAR 1032 * @hw: pointer to hardware structure 1033 * 1034 * Disables multicast address in RAR and the use of the multicast hash table. 1035 **/ 1036 s32 ixgbe_disable_mc(struct ixgbe_hw *hw) 1037 { 1038 return ixgbe_call_func(hw, hw->mac.ops.disable_mc, (hw), 1039 IXGBE_NOT_IMPLEMENTED); 1040 } 1041 1042 /** 1043 * ixgbe_clear_vfta - Clear VLAN filter table 1044 * @hw: pointer to hardware structure 1045 * 1046 * Clears the VLAN filer table, and the VMDq index associated with the filter 1047 **/ 1048 s32 ixgbe_clear_vfta(struct ixgbe_hw *hw) 1049 { 1050 return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw), 1051 IXGBE_NOT_IMPLEMENTED); 1052 } 1053 1054 /** 1055 * ixgbe_set_vfta - Set VLAN filter table 1056 * @hw: pointer to hardware structure 1057 * @vlan: VLAN id to write to VLAN filter 1058 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 1059 * @vlan_on: boolean flag to turn on/off VLAN 1060 * @vlvf_bypass: boolean flag indicating updating the default pool is okay 1061 * 1062 * Turn on/off specified VLAN in the VLAN filter table. 1063 **/ 1064 s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on, 1065 bool vlvf_bypass) 1066 { 1067 return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind, 1068 vlan_on, vlvf_bypass), IXGBE_NOT_IMPLEMENTED); 1069 } 1070 1071 /** 1072 * ixgbe_set_vlvf - Set VLAN Pool Filter 1073 * @hw: pointer to hardware structure 1074 * @vlan: VLAN id to write to VLAN filter 1075 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 1076 * @vlan_on: boolean flag to turn on/off VLAN in VLVF 1077 * @vfta_delta: pointer to the difference between the current value of VFTA 1078 * and the desired value 1079 * @vfta: the desired value of the VFTA 1080 * @vlvf_bypass: boolean flag indicating updating the default pool is okay 1081 * 1082 * Turn on/off specified bit in VLVF table. 1083 **/ 1084 s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on, 1085 u32 *vfta_delta, u32 vfta, bool vlvf_bypass) 1086 { 1087 return ixgbe_call_func(hw, hw->mac.ops.set_vlvf, (hw, vlan, vind, 1088 vlan_on, vfta_delta, vfta, vlvf_bypass), 1089 IXGBE_NOT_IMPLEMENTED); 1090 } 1091 1092 /** 1093 * ixgbe_fc_enable - Enable flow control 1094 * @hw: pointer to hardware structure 1095 * 1096 * Configures the flow control settings based on SW configuration. 1097 **/ 1098 s32 ixgbe_fc_enable(struct ixgbe_hw *hw) 1099 { 1100 return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw), 1101 IXGBE_NOT_IMPLEMENTED); 1102 } 1103 1104 /** 1105 * ixgbe_setup_fc - Set up flow control 1106 * @hw: pointer to hardware structure 1107 * 1108 * Called at init time to set up flow control. 1109 **/ 1110 s32 ixgbe_setup_fc(struct ixgbe_hw *hw) 1111 { 1112 return ixgbe_call_func(hw, hw->mac.ops.setup_fc, (hw), 1113 IXGBE_NOT_IMPLEMENTED); 1114 } 1115 1116 /** 1117 * ixgbe_set_fw_drv_ver - Try to send the driver version number FW 1118 * @hw: pointer to hardware structure 1119 * @maj: driver major number to be sent to firmware 1120 * @min: driver minor number to be sent to firmware 1121 * @build: driver build number to be sent to firmware 1122 * @ver: driver version number to be sent to firmware 1123 * @len: length of driver_ver string 1124 * @driver_ver: driver string 1125 **/ 1126 s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build, 1127 u8 ver, u16 len, char *driver_ver) 1128 { 1129 return ixgbe_call_func(hw, hw->mac.ops.set_fw_drv_ver, (hw, maj, min, 1130 build, ver, len, driver_ver), 1131 IXGBE_NOT_IMPLEMENTED); 1132 } 1133 1134 1135 1136 /** 1137 * ixgbe_dmac_config - Configure DMA Coalescing registers. 1138 * @hw: pointer to hardware structure 1139 * 1140 * Configure DMA coalescing. If enabling dmac, dmac is activated. 1141 * When disabling dmac, dmac enable dmac bit is cleared. 1142 **/ 1143 s32 ixgbe_dmac_config(struct ixgbe_hw *hw) 1144 { 1145 return ixgbe_call_func(hw, hw->mac.ops.dmac_config, (hw), 1146 IXGBE_NOT_IMPLEMENTED); 1147 } 1148 1149 /** 1150 * ixgbe_dmac_update_tcs - Configure DMA Coalescing registers. 1151 * @hw: pointer to hardware structure 1152 * 1153 * Disables dmac, updates per TC settings, and then enable dmac. 1154 **/ 1155 s32 ixgbe_dmac_update_tcs(struct ixgbe_hw *hw) 1156 { 1157 return ixgbe_call_func(hw, hw->mac.ops.dmac_update_tcs, (hw), 1158 IXGBE_NOT_IMPLEMENTED); 1159 } 1160 1161 /** 1162 * ixgbe_dmac_config_tcs - Configure DMA Coalescing registers. 1163 * @hw: pointer to hardware structure 1164 * 1165 * Configure DMA coalescing threshold per TC and set high priority bit for 1166 * FCOE TC. The dmac enable bit must be cleared before configuring. 1167 **/ 1168 s32 ixgbe_dmac_config_tcs(struct ixgbe_hw *hw) 1169 { 1170 return ixgbe_call_func(hw, hw->mac.ops.dmac_config_tcs, (hw), 1171 IXGBE_NOT_IMPLEMENTED); 1172 } 1173 1174 /** 1175 * ixgbe_setup_eee - Enable/disable EEE support 1176 * @hw: pointer to the HW structure 1177 * @enable_eee: boolean flag to enable EEE 1178 * 1179 * Enable/disable EEE based on enable_ee flag. 1180 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C 1181 * are modified. 1182 * 1183 **/ 1184 s32 ixgbe_setup_eee(struct ixgbe_hw *hw, bool enable_eee) 1185 { 1186 return ixgbe_call_func(hw, hw->mac.ops.setup_eee, (hw, enable_eee), 1187 IXGBE_NOT_IMPLEMENTED); 1188 } 1189 1190 /** 1191 * ixgbe_set_source_address_pruning - Enable/Disable source address pruning 1192 * @hw: pointer to hardware structure 1193 * @enbale: enable or disable source address pruning 1194 * @pool: Rx pool - Rx pool to toggle source address pruning 1195 **/ 1196 void ixgbe_set_source_address_pruning(struct ixgbe_hw *hw, bool enable, 1197 unsigned int pool) 1198 { 1199 if (hw->mac.ops.set_source_address_pruning) 1200 hw->mac.ops.set_source_address_pruning(hw, enable, pool); 1201 } 1202 1203 /** 1204 * ixgbe_set_ethertype_anti_spoofing - Enable/Disable Ethertype anti-spoofing 1205 * @hw: pointer to hardware structure 1206 * @enable: enable or disable switch for Ethertype anti-spoofing 1207 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing 1208 * 1209 **/ 1210 void ixgbe_set_ethertype_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 1211 { 1212 if (hw->mac.ops.set_ethertype_anti_spoofing) 1213 hw->mac.ops.set_ethertype_anti_spoofing(hw, enable, vf); 1214 } 1215 1216 /** 1217 * ixgbe_read_iosf_sb_reg - Read 32 bit PHY register 1218 * @hw: pointer to hardware structure 1219 * @reg_addr: 32 bit address of PHY register to read 1220 * @device_type: type of device you want to communicate with 1221 * @phy_data: Pointer to read data from PHY register 1222 * 1223 * Reads a value from a specified PHY register 1224 **/ 1225 s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, 1226 u32 device_type, u32 *phy_data) 1227 { 1228 return ixgbe_call_func(hw, hw->mac.ops.read_iosf_sb_reg, (hw, reg_addr, 1229 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 1230 } 1231 1232 /** 1233 * ixgbe_write_iosf_sb_reg - Write 32 bit register through IOSF Sideband 1234 * @hw: pointer to hardware structure 1235 * @reg_addr: 32 bit PHY register to write 1236 * @device_type: type of device you want to communicate with 1237 * @phy_data: Data to write to the PHY register 1238 * 1239 * Writes a value to specified PHY register 1240 **/ 1241 s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, 1242 u32 device_type, u32 phy_data) 1243 { 1244 return ixgbe_call_func(hw, hw->mac.ops.write_iosf_sb_reg, (hw, reg_addr, 1245 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 1246 } 1247 1248 /** 1249 * ixgbe_disable_mdd - Disable malicious driver detection 1250 * @hw: pointer to hardware structure 1251 * 1252 **/ 1253 void ixgbe_disable_mdd(struct ixgbe_hw *hw) 1254 { 1255 if (hw->mac.ops.disable_mdd) 1256 hw->mac.ops.disable_mdd(hw); 1257 } 1258 1259 /** 1260 * ixgbe_enable_mdd - Enable malicious driver detection 1261 * @hw: pointer to hardware structure 1262 * 1263 **/ 1264 void ixgbe_enable_mdd(struct ixgbe_hw *hw) 1265 { 1266 if (hw->mac.ops.enable_mdd) 1267 hw->mac.ops.enable_mdd(hw); 1268 } 1269 1270 /** 1271 * ixgbe_mdd_event - Handle malicious driver detection event 1272 * @hw: pointer to hardware structure 1273 * @vf_bitmap: vf bitmap of malicious vfs 1274 * 1275 **/ 1276 void ixgbe_mdd_event(struct ixgbe_hw *hw, u32 *vf_bitmap) 1277 { 1278 if (hw->mac.ops.mdd_event) 1279 hw->mac.ops.mdd_event(hw, vf_bitmap); 1280 } 1281 1282 /** 1283 * ixgbe_restore_mdd_vf - Restore VF that was disabled during malicious driver 1284 * detection event 1285 * @hw: pointer to hardware structure 1286 * @vf: vf index 1287 * 1288 **/ 1289 void ixgbe_restore_mdd_vf(struct ixgbe_hw *hw, u32 vf) 1290 { 1291 if (hw->mac.ops.restore_mdd_vf) 1292 hw->mac.ops.restore_mdd_vf(hw, vf); 1293 } 1294 1295 /** 1296 * ixgbe_enter_lplu - Transition to low power states 1297 * @hw: pointer to hardware structure 1298 * 1299 * Configures Low Power Link Up on transition to low power states 1300 * (from D0 to non-D0). 1301 **/ 1302 s32 ixgbe_enter_lplu(struct ixgbe_hw *hw) 1303 { 1304 return ixgbe_call_func(hw, hw->phy.ops.enter_lplu, (hw), 1305 IXGBE_NOT_IMPLEMENTED); 1306 } 1307 1308 /** 1309 * ixgbe_handle_lasi - Handle external Base T PHY interrupt 1310 * @hw: pointer to hardware structure 1311 * 1312 * Handle external Base T PHY interrupt. If high temperature 1313 * failure alarm then return error, else if link status change 1314 * then setup internal/external PHY link 1315 * 1316 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 1317 * failure alarm, else return PHY access status. 1318 */ 1319 s32 ixgbe_handle_lasi(struct ixgbe_hw *hw) 1320 { 1321 return ixgbe_call_func(hw, hw->phy.ops.handle_lasi, (hw), 1322 IXGBE_NOT_IMPLEMENTED); 1323 } 1324 1325 /** 1326 * ixgbe_bypass_rw - Bit bang data into by_pass FW 1327 * @hw: pointer to hardware structure 1328 * @cmd: Command we send to the FW 1329 * @status: The reply from the FW 1330 * 1331 * Bit-bangs the cmd to the by_pass FW status points to what is returned. 1332 **/ 1333 s32 ixgbe_bypass_rw(struct ixgbe_hw *hw, u32 cmd, u32 *status) 1334 { 1335 return ixgbe_call_func(hw, hw->mac.ops.bypass_rw, (hw, cmd, status), 1336 IXGBE_NOT_IMPLEMENTED); 1337 } 1338 1339 /** 1340 * ixgbe_bypass_valid_rd - Verify valid return from bit-bang. 1341 * 1342 * If we send a write we can't be sure it took until we can read back 1343 * that same register. It can be a problem as some of the feilds may 1344 * for valid reasons change inbetween the time wrote the register and 1345 * we read it again to verify. So this function check everything we 1346 * can check and then assumes it worked. 1347 * 1348 * @u32 in_reg - The register cmd for the bit-bang read. 1349 * @u32 out_reg - The register returned from a bit-bang read. 1350 **/ 1351 bool ixgbe_bypass_valid_rd(struct ixgbe_hw *hw, u32 in_reg, u32 out_reg) 1352 { 1353 return ixgbe_call_func(hw, hw->mac.ops.bypass_valid_rd, 1354 (in_reg, out_reg), IXGBE_NOT_IMPLEMENTED); 1355 } 1356 1357 /** 1358 * ixgbe_bypass_set - Set a bypass field in the FW CTRL Regiter. 1359 * @hw: pointer to hardware structure 1360 * @cmd: The control word we are setting. 1361 * @event: The event we are setting in the FW. This also happens to 1362 * be the mask for the event we are setting (handy) 1363 * @action: The action we set the event to in the FW. This is in a 1364 * bit field that happens to be what we want to put in 1365 * the event spot (also handy) 1366 * 1367 * Writes to the cmd control the bits in actions. 1368 **/ 1369 s32 ixgbe_bypass_set(struct ixgbe_hw *hw, u32 cmd, u32 event, u32 action) 1370 { 1371 return ixgbe_call_func(hw, hw->mac.ops.bypass_set, 1372 (hw, cmd, event, action), 1373 IXGBE_NOT_IMPLEMENTED); 1374 } 1375 1376 /** 1377 * ixgbe_bypass_rd_eep - Read the bypass FW eeprom address 1378 * @hw: pointer to hardware structure 1379 * @addr: The bypass eeprom address to read. 1380 * @value: The 8b of data at the address above. 1381 **/ 1382 s32 ixgbe_bypass_rd_eep(struct ixgbe_hw *hw, u32 addr, u8 *value) 1383 { 1384 return ixgbe_call_func(hw, hw->mac.ops.bypass_rd_eep, 1385 (hw, addr, value), IXGBE_NOT_IMPLEMENTED); 1386 } 1387 1388 /** 1389 * ixgbe_read_analog_reg8 - Reads 8 bit analog register 1390 * @hw: pointer to hardware structure 1391 * @reg: analog register to read 1392 * @val: read value 1393 * 1394 * Performs write operation to analog register specified. 1395 **/ 1396 s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val) 1397 { 1398 return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg, 1399 val), IXGBE_NOT_IMPLEMENTED); 1400 } 1401 1402 /** 1403 * ixgbe_write_analog_reg8 - Writes 8 bit analog register 1404 * @hw: pointer to hardware structure 1405 * @reg: analog register to write 1406 * @val: value to write 1407 * 1408 * Performs write operation to Atlas analog register specified. 1409 **/ 1410 s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val) 1411 { 1412 return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg, 1413 val), IXGBE_NOT_IMPLEMENTED); 1414 } 1415 1416 /** 1417 * ixgbe_init_uta_tables - Initializes Unicast Table Arrays. 1418 * @hw: pointer to hardware structure 1419 * 1420 * Initializes the Unicast Table Arrays to zero on device load. This 1421 * is part of the Rx init addr execution path. 1422 **/ 1423 s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw) 1424 { 1425 return ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw), 1426 IXGBE_NOT_IMPLEMENTED); 1427 } 1428 1429 /** 1430 * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address 1431 * @hw: pointer to hardware structure 1432 * @byte_offset: byte offset to read 1433 * @dev_addr: I2C bus address to read from 1434 * @data: value read 1435 * 1436 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1437 **/ 1438 s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1439 u8 *data) 1440 { 1441 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset, 1442 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1443 } 1444 1445 /** 1446 * ixgbe_read_i2c_byte_unlocked - Reads 8 bit word via I2C from device address 1447 * @hw: pointer to hardware structure 1448 * @byte_offset: byte offset to read 1449 * @dev_addr: I2C bus address to read from 1450 * @data: value read 1451 * 1452 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1453 **/ 1454 s32 ixgbe_read_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 1455 u8 dev_addr, u8 *data) 1456 { 1457 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte_unlocked, 1458 (hw, byte_offset, dev_addr, data), 1459 IXGBE_NOT_IMPLEMENTED); 1460 } 1461 1462 /** 1463 * ixgbe_read_link - Perform read operation on link device 1464 * @hw: pointer to the hardware structure 1465 * @addr: bus address to read from 1466 * @reg: device register to read from 1467 * @val: pointer to location to receive read value 1468 * 1469 * Returns an error code on error. 1470 */ 1471 s32 ixgbe_read_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val) 1472 { 1473 return ixgbe_call_func(hw, hw->link.ops.read_link, (hw, addr, 1474 reg, val), IXGBE_NOT_IMPLEMENTED); 1475 } 1476 1477 /** 1478 * ixgbe_read_link_unlocked - Perform read operation on link device 1479 * @hw: pointer to the hardware structure 1480 * @addr: bus address to read from 1481 * @reg: device register to read from 1482 * @val: pointer to location to receive read value 1483 * 1484 * Returns an error code on error. 1485 **/ 1486 s32 ixgbe_read_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val) 1487 { 1488 return ixgbe_call_func(hw, hw->link.ops.read_link_unlocked, 1489 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1490 } 1491 1492 /** 1493 * ixgbe_write_i2c_byte - Writes 8 bit word over I2C 1494 * @hw: pointer to hardware structure 1495 * @byte_offset: byte offset to write 1496 * @dev_addr: I2C bus address to write to 1497 * @data: value to write 1498 * 1499 * Performs byte write operation to SFP module's EEPROM over I2C interface 1500 * at a specified device address. 1501 **/ 1502 s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1503 u8 data) 1504 { 1505 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, (hw, byte_offset, 1506 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1507 } 1508 1509 /** 1510 * ixgbe_write_i2c_byte_unlocked - Writes 8 bit word over I2C 1511 * @hw: pointer to hardware structure 1512 * @byte_offset: byte offset to write 1513 * @dev_addr: I2C bus address to write to 1514 * @data: value to write 1515 * 1516 * Performs byte write operation to SFP module's EEPROM over I2C interface 1517 * at a specified device address. 1518 **/ 1519 s32 ixgbe_write_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 1520 u8 dev_addr, u8 data) 1521 { 1522 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte_unlocked, 1523 (hw, byte_offset, dev_addr, data), 1524 IXGBE_NOT_IMPLEMENTED); 1525 } 1526 1527 /** 1528 * ixgbe_write_link - Perform write operation on link device 1529 * @hw: pointer to the hardware structure 1530 * @addr: bus address to write to 1531 * @reg: device register to write to 1532 * @val: value to write 1533 * 1534 * Returns an error code on error. 1535 */ 1536 s32 ixgbe_write_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val) 1537 { 1538 return ixgbe_call_func(hw, hw->link.ops.write_link, 1539 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1540 } 1541 1542 /** 1543 * ixgbe_write_link_unlocked - Perform write operation on link device 1544 * @hw: pointer to the hardware structure 1545 * @addr: bus address to write to 1546 * @reg: device register to write to 1547 * @val: value to write 1548 * 1549 * Returns an error code on error. 1550 **/ 1551 s32 ixgbe_write_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val) 1552 { 1553 return ixgbe_call_func(hw, hw->link.ops.write_link_unlocked, 1554 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1555 } 1556 1557 /** 1558 * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface 1559 * @hw: pointer to hardware structure 1560 * @byte_offset: EEPROM byte offset to write 1561 * @eeprom_data: value to write 1562 * 1563 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1564 **/ 1565 s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, 1566 u8 byte_offset, u8 eeprom_data) 1567 { 1568 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom, 1569 (hw, byte_offset, eeprom_data), 1570 IXGBE_NOT_IMPLEMENTED); 1571 } 1572 1573 /** 1574 * ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface 1575 * @hw: pointer to hardware structure 1576 * @byte_offset: EEPROM byte offset to read 1577 * @eeprom_data: value read 1578 * 1579 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1580 **/ 1581 s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data) 1582 { 1583 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom, 1584 (hw, byte_offset, eeprom_data), 1585 IXGBE_NOT_IMPLEMENTED); 1586 } 1587 1588 /** 1589 * ixgbe_get_supported_physical_layer - Returns physical layer type 1590 * @hw: pointer to hardware structure 1591 * 1592 * Determines physical layer capabilities of the current configuration. 1593 **/ 1594 u64 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw) 1595 { 1596 return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer, 1597 (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN); 1598 } 1599 1600 /** 1601 * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependent on device specifics 1602 * @hw: pointer to hardware structure 1603 * @regval: bitfield to write to the Rx DMA register 1604 * 1605 * Enables the Rx DMA unit of the device. 1606 **/ 1607 s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval) 1608 { 1609 return ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma, 1610 (hw, regval), IXGBE_NOT_IMPLEMENTED); 1611 } 1612 1613 /** 1614 * ixgbe_disable_sec_rx_path - Stops the receive data path 1615 * @hw: pointer to hardware structure 1616 * 1617 * Stops the receive data path. 1618 **/ 1619 s32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw) 1620 { 1621 return ixgbe_call_func(hw, hw->mac.ops.disable_sec_rx_path, 1622 (hw), IXGBE_NOT_IMPLEMENTED); 1623 } 1624 1625 /** 1626 * ixgbe_enable_sec_rx_path - Enables the receive data path 1627 * @hw: pointer to hardware structure 1628 * 1629 * Enables the receive data path. 1630 **/ 1631 s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw) 1632 { 1633 return ixgbe_call_func(hw, hw->mac.ops.enable_sec_rx_path, 1634 (hw), IXGBE_NOT_IMPLEMENTED); 1635 } 1636 1637 /** 1638 * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore 1639 * @hw: pointer to hardware structure 1640 * @mask: Mask to specify which semaphore to acquire 1641 * 1642 * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified 1643 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1644 **/ 1645 s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u32 mask) 1646 { 1647 return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync, 1648 (hw, mask), IXGBE_NOT_IMPLEMENTED); 1649 } 1650 1651 /** 1652 * ixgbe_release_swfw_semaphore - Release SWFW semaphore 1653 * @hw: pointer to hardware structure 1654 * @mask: Mask to specify which semaphore to release 1655 * 1656 * Releases the SWFW semaphore through SW_FW_SYNC register for the specified 1657 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1658 **/ 1659 void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask) 1660 { 1661 if (hw->mac.ops.release_swfw_sync) 1662 hw->mac.ops.release_swfw_sync(hw, mask); 1663 } 1664 1665 /** 1666 * ixgbe_init_swfw_semaphore - Clean up SWFW semaphore 1667 * @hw: pointer to hardware structure 1668 * 1669 * Attempts to acquire the SWFW semaphore through SW_FW_SYNC register. 1670 * Regardless of whether is succeeds or not it then release the semaphore. 1671 * This is function is called to recover from catastrophic failures that 1672 * may have left the semaphore locked. 1673 **/ 1674 void ixgbe_init_swfw_semaphore(struct ixgbe_hw *hw) 1675 { 1676 if (hw->mac.ops.init_swfw_sync) 1677 hw->mac.ops.init_swfw_sync(hw); 1678 } 1679 1680 1681 void ixgbe_disable_rx(struct ixgbe_hw *hw) 1682 { 1683 if (hw->mac.ops.disable_rx) 1684 hw->mac.ops.disable_rx(hw); 1685 } 1686 1687 void ixgbe_enable_rx(struct ixgbe_hw *hw) 1688 { 1689 if (hw->mac.ops.enable_rx) 1690 hw->mac.ops.enable_rx(hw); 1691 } 1692 1693 /** 1694 * ixgbe_set_rate_select_speed - Set module link speed 1695 * @hw: pointer to hardware structure 1696 * @speed: link speed to set 1697 * 1698 * Set module link speed via the rate select. 1699 */ 1700 void ixgbe_set_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed) 1701 { 1702 if (hw->mac.ops.set_rate_select_speed) 1703 hw->mac.ops.set_rate_select_speed(hw, speed); 1704 } 1705