1 /****************************************************************************** 2 3 Copyright (c) 2013-2018, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "i40e_type.h" 36 #include "i40e_adminq.h" 37 #include "i40e_prototype.h" 38 #include "virtchnl.h" 39 40 41 /** 42 * i40e_set_mac_type - Sets MAC type 43 * @hw: pointer to the HW structure 44 * 45 * This function sets the mac type of the adapter based on the 46 * vendor ID and device ID stored in the hw structure. 47 **/ 48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw) 49 { 50 enum i40e_status_code status = I40E_SUCCESS; 51 52 DEBUGFUNC("i40e_set_mac_type\n"); 53 54 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) { 55 switch (hw->device_id) { 56 case I40E_DEV_ID_SFP_XL710: 57 case I40E_DEV_ID_QEMU: 58 case I40E_DEV_ID_KX_B: 59 case I40E_DEV_ID_KX_C: 60 case I40E_DEV_ID_QSFP_A: 61 case I40E_DEV_ID_QSFP_B: 62 case I40E_DEV_ID_QSFP_C: 63 case I40E_DEV_ID_10G_BASE_T: 64 case I40E_DEV_ID_10G_BASE_T4: 65 case I40E_DEV_ID_20G_KR2: 66 case I40E_DEV_ID_20G_KR2_A: 67 case I40E_DEV_ID_25G_B: 68 case I40E_DEV_ID_25G_SFP28: 69 hw->mac.type = I40E_MAC_XL710; 70 break; 71 case I40E_DEV_ID_KX_X722: 72 case I40E_DEV_ID_QSFP_X722: 73 case I40E_DEV_ID_SFP_X722: 74 case I40E_DEV_ID_1G_BASE_T_X722: 75 case I40E_DEV_ID_10G_BASE_T_X722: 76 case I40E_DEV_ID_SFP_I_X722: 77 hw->mac.type = I40E_MAC_X722; 78 break; 79 case I40E_DEV_ID_X722_VF: 80 hw->mac.type = I40E_MAC_X722_VF; 81 break; 82 case I40E_DEV_ID_VF: 83 case I40E_DEV_ID_VF_HV: 84 case I40E_DEV_ID_ADAPTIVE_VF: 85 hw->mac.type = I40E_MAC_VF; 86 break; 87 default: 88 hw->mac.type = I40E_MAC_GENERIC; 89 break; 90 } 91 } else { 92 status = I40E_ERR_DEVICE_NOT_SUPPORTED; 93 } 94 95 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n", 96 hw->mac.type, status); 97 return status; 98 } 99 100 /** 101 * i40e_aq_str - convert AQ err code to a string 102 * @hw: pointer to the HW structure 103 * @aq_err: the AQ error code to convert 104 **/ 105 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err) 106 { 107 switch (aq_err) { 108 case I40E_AQ_RC_OK: 109 return "OK"; 110 case I40E_AQ_RC_EPERM: 111 return "I40E_AQ_RC_EPERM"; 112 case I40E_AQ_RC_ENOENT: 113 return "I40E_AQ_RC_ENOENT"; 114 case I40E_AQ_RC_ESRCH: 115 return "I40E_AQ_RC_ESRCH"; 116 case I40E_AQ_RC_EINTR: 117 return "I40E_AQ_RC_EINTR"; 118 case I40E_AQ_RC_EIO: 119 return "I40E_AQ_RC_EIO"; 120 case I40E_AQ_RC_ENXIO: 121 return "I40E_AQ_RC_ENXIO"; 122 case I40E_AQ_RC_E2BIG: 123 return "I40E_AQ_RC_E2BIG"; 124 case I40E_AQ_RC_EAGAIN: 125 return "I40E_AQ_RC_EAGAIN"; 126 case I40E_AQ_RC_ENOMEM: 127 return "I40E_AQ_RC_ENOMEM"; 128 case I40E_AQ_RC_EACCES: 129 return "I40E_AQ_RC_EACCES"; 130 case I40E_AQ_RC_EFAULT: 131 return "I40E_AQ_RC_EFAULT"; 132 case I40E_AQ_RC_EBUSY: 133 return "I40E_AQ_RC_EBUSY"; 134 case I40E_AQ_RC_EEXIST: 135 return "I40E_AQ_RC_EEXIST"; 136 case I40E_AQ_RC_EINVAL: 137 return "I40E_AQ_RC_EINVAL"; 138 case I40E_AQ_RC_ENOTTY: 139 return "I40E_AQ_RC_ENOTTY"; 140 case I40E_AQ_RC_ENOSPC: 141 return "I40E_AQ_RC_ENOSPC"; 142 case I40E_AQ_RC_ENOSYS: 143 return "I40E_AQ_RC_ENOSYS"; 144 case I40E_AQ_RC_ERANGE: 145 return "I40E_AQ_RC_ERANGE"; 146 case I40E_AQ_RC_EFLUSHED: 147 return "I40E_AQ_RC_EFLUSHED"; 148 case I40E_AQ_RC_BAD_ADDR: 149 return "I40E_AQ_RC_BAD_ADDR"; 150 case I40E_AQ_RC_EMODE: 151 return "I40E_AQ_RC_EMODE"; 152 case I40E_AQ_RC_EFBIG: 153 return "I40E_AQ_RC_EFBIG"; 154 } 155 156 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err); 157 return hw->err_str; 158 } 159 160 /** 161 * i40e_stat_str - convert status err code to a string 162 * @hw: pointer to the HW structure 163 * @stat_err: the status error code to convert 164 **/ 165 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err) 166 { 167 switch (stat_err) { 168 case I40E_SUCCESS: 169 return "OK"; 170 case I40E_ERR_NVM: 171 return "I40E_ERR_NVM"; 172 case I40E_ERR_NVM_CHECKSUM: 173 return "I40E_ERR_NVM_CHECKSUM"; 174 case I40E_ERR_PHY: 175 return "I40E_ERR_PHY"; 176 case I40E_ERR_CONFIG: 177 return "I40E_ERR_CONFIG"; 178 case I40E_ERR_PARAM: 179 return "I40E_ERR_PARAM"; 180 case I40E_ERR_MAC_TYPE: 181 return "I40E_ERR_MAC_TYPE"; 182 case I40E_ERR_UNKNOWN_PHY: 183 return "I40E_ERR_UNKNOWN_PHY"; 184 case I40E_ERR_LINK_SETUP: 185 return "I40E_ERR_LINK_SETUP"; 186 case I40E_ERR_ADAPTER_STOPPED: 187 return "I40E_ERR_ADAPTER_STOPPED"; 188 case I40E_ERR_INVALID_MAC_ADDR: 189 return "I40E_ERR_INVALID_MAC_ADDR"; 190 case I40E_ERR_DEVICE_NOT_SUPPORTED: 191 return "I40E_ERR_DEVICE_NOT_SUPPORTED"; 192 case I40E_ERR_MASTER_REQUESTS_PENDING: 193 return "I40E_ERR_MASTER_REQUESTS_PENDING"; 194 case I40E_ERR_INVALID_LINK_SETTINGS: 195 return "I40E_ERR_INVALID_LINK_SETTINGS"; 196 case I40E_ERR_AUTONEG_NOT_COMPLETE: 197 return "I40E_ERR_AUTONEG_NOT_COMPLETE"; 198 case I40E_ERR_RESET_FAILED: 199 return "I40E_ERR_RESET_FAILED"; 200 case I40E_ERR_SWFW_SYNC: 201 return "I40E_ERR_SWFW_SYNC"; 202 case I40E_ERR_NO_AVAILABLE_VSI: 203 return "I40E_ERR_NO_AVAILABLE_VSI"; 204 case I40E_ERR_NO_MEMORY: 205 return "I40E_ERR_NO_MEMORY"; 206 case I40E_ERR_BAD_PTR: 207 return "I40E_ERR_BAD_PTR"; 208 case I40E_ERR_RING_FULL: 209 return "I40E_ERR_RING_FULL"; 210 case I40E_ERR_INVALID_PD_ID: 211 return "I40E_ERR_INVALID_PD_ID"; 212 case I40E_ERR_INVALID_QP_ID: 213 return "I40E_ERR_INVALID_QP_ID"; 214 case I40E_ERR_INVALID_CQ_ID: 215 return "I40E_ERR_INVALID_CQ_ID"; 216 case I40E_ERR_INVALID_CEQ_ID: 217 return "I40E_ERR_INVALID_CEQ_ID"; 218 case I40E_ERR_INVALID_AEQ_ID: 219 return "I40E_ERR_INVALID_AEQ_ID"; 220 case I40E_ERR_INVALID_SIZE: 221 return "I40E_ERR_INVALID_SIZE"; 222 case I40E_ERR_INVALID_ARP_INDEX: 223 return "I40E_ERR_INVALID_ARP_INDEX"; 224 case I40E_ERR_INVALID_FPM_FUNC_ID: 225 return "I40E_ERR_INVALID_FPM_FUNC_ID"; 226 case I40E_ERR_QP_INVALID_MSG_SIZE: 227 return "I40E_ERR_QP_INVALID_MSG_SIZE"; 228 case I40E_ERR_QP_TOOMANY_WRS_POSTED: 229 return "I40E_ERR_QP_TOOMANY_WRS_POSTED"; 230 case I40E_ERR_INVALID_FRAG_COUNT: 231 return "I40E_ERR_INVALID_FRAG_COUNT"; 232 case I40E_ERR_QUEUE_EMPTY: 233 return "I40E_ERR_QUEUE_EMPTY"; 234 case I40E_ERR_INVALID_ALIGNMENT: 235 return "I40E_ERR_INVALID_ALIGNMENT"; 236 case I40E_ERR_FLUSHED_QUEUE: 237 return "I40E_ERR_FLUSHED_QUEUE"; 238 case I40E_ERR_INVALID_PUSH_PAGE_INDEX: 239 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX"; 240 case I40E_ERR_INVALID_IMM_DATA_SIZE: 241 return "I40E_ERR_INVALID_IMM_DATA_SIZE"; 242 case I40E_ERR_TIMEOUT: 243 return "I40E_ERR_TIMEOUT"; 244 case I40E_ERR_OPCODE_MISMATCH: 245 return "I40E_ERR_OPCODE_MISMATCH"; 246 case I40E_ERR_CQP_COMPL_ERROR: 247 return "I40E_ERR_CQP_COMPL_ERROR"; 248 case I40E_ERR_INVALID_VF_ID: 249 return "I40E_ERR_INVALID_VF_ID"; 250 case I40E_ERR_INVALID_HMCFN_ID: 251 return "I40E_ERR_INVALID_HMCFN_ID"; 252 case I40E_ERR_BACKING_PAGE_ERROR: 253 return "I40E_ERR_BACKING_PAGE_ERROR"; 254 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE: 255 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE"; 256 case I40E_ERR_INVALID_PBLE_INDEX: 257 return "I40E_ERR_INVALID_PBLE_INDEX"; 258 case I40E_ERR_INVALID_SD_INDEX: 259 return "I40E_ERR_INVALID_SD_INDEX"; 260 case I40E_ERR_INVALID_PAGE_DESC_INDEX: 261 return "I40E_ERR_INVALID_PAGE_DESC_INDEX"; 262 case I40E_ERR_INVALID_SD_TYPE: 263 return "I40E_ERR_INVALID_SD_TYPE"; 264 case I40E_ERR_MEMCPY_FAILED: 265 return "I40E_ERR_MEMCPY_FAILED"; 266 case I40E_ERR_INVALID_HMC_OBJ_INDEX: 267 return "I40E_ERR_INVALID_HMC_OBJ_INDEX"; 268 case I40E_ERR_INVALID_HMC_OBJ_COUNT: 269 return "I40E_ERR_INVALID_HMC_OBJ_COUNT"; 270 case I40E_ERR_INVALID_SRQ_ARM_LIMIT: 271 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT"; 272 case I40E_ERR_SRQ_ENABLED: 273 return "I40E_ERR_SRQ_ENABLED"; 274 case I40E_ERR_ADMIN_QUEUE_ERROR: 275 return "I40E_ERR_ADMIN_QUEUE_ERROR"; 276 case I40E_ERR_ADMIN_QUEUE_TIMEOUT: 277 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT"; 278 case I40E_ERR_BUF_TOO_SHORT: 279 return "I40E_ERR_BUF_TOO_SHORT"; 280 case I40E_ERR_ADMIN_QUEUE_FULL: 281 return "I40E_ERR_ADMIN_QUEUE_FULL"; 282 case I40E_ERR_ADMIN_QUEUE_NO_WORK: 283 return "I40E_ERR_ADMIN_QUEUE_NO_WORK"; 284 case I40E_ERR_BAD_IWARP_CQE: 285 return "I40E_ERR_BAD_IWARP_CQE"; 286 case I40E_ERR_NVM_BLANK_MODE: 287 return "I40E_ERR_NVM_BLANK_MODE"; 288 case I40E_ERR_NOT_IMPLEMENTED: 289 return "I40E_ERR_NOT_IMPLEMENTED"; 290 case I40E_ERR_PE_DOORBELL_NOT_ENABLED: 291 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED"; 292 case I40E_ERR_DIAG_TEST_FAILED: 293 return "I40E_ERR_DIAG_TEST_FAILED"; 294 case I40E_ERR_NOT_READY: 295 return "I40E_ERR_NOT_READY"; 296 case I40E_NOT_SUPPORTED: 297 return "I40E_NOT_SUPPORTED"; 298 case I40E_ERR_FIRMWARE_API_VERSION: 299 return "I40E_ERR_FIRMWARE_API_VERSION"; 300 case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR: 301 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR"; 302 } 303 304 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err); 305 return hw->err_str; 306 } 307 308 /** 309 * i40e_debug_aq 310 * @hw: debug mask related to admin queue 311 * @mask: debug mask 312 * @desc: pointer to admin queue descriptor 313 * @buffer: pointer to command buffer 314 * @buf_len: max length of buffer 315 * 316 * Dumps debug log about adminq command with descriptor contents. 317 **/ 318 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, 319 void *buffer, u16 buf_len) 320 { 321 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc; 322 u8 *buf = (u8 *)buffer; 323 u16 len; 324 u16 i = 0; 325 326 if ((!(mask & hw->debug_mask)) || (desc == NULL)) 327 return; 328 329 len = LE16_TO_CPU(aq_desc->datalen); 330 331 i40e_debug(hw, mask, 332 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 333 LE16_TO_CPU(aq_desc->opcode), 334 LE16_TO_CPU(aq_desc->flags), 335 LE16_TO_CPU(aq_desc->datalen), 336 LE16_TO_CPU(aq_desc->retval)); 337 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n", 338 LE32_TO_CPU(aq_desc->cookie_high), 339 LE32_TO_CPU(aq_desc->cookie_low)); 340 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n", 341 LE32_TO_CPU(aq_desc->params.internal.param0), 342 LE32_TO_CPU(aq_desc->params.internal.param1)); 343 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n", 344 LE32_TO_CPU(aq_desc->params.external.addr_high), 345 LE32_TO_CPU(aq_desc->params.external.addr_low)); 346 347 if ((buffer != NULL) && (aq_desc->datalen != 0)) { 348 i40e_debug(hw, mask, "AQ CMD Buffer:\n"); 349 if (buf_len < len) 350 len = buf_len; 351 /* write the full 16-byte chunks */ 352 for (i = 0; i < (len - 16); i += 16) 353 i40e_debug(hw, mask, 354 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n", 355 i, buf[i], buf[i+1], buf[i+2], buf[i+3], 356 buf[i+4], buf[i+5], buf[i+6], buf[i+7], 357 buf[i+8], buf[i+9], buf[i+10], buf[i+11], 358 buf[i+12], buf[i+13], buf[i+14], buf[i+15]); 359 /* the most we could have left is 16 bytes, pad with zeros */ 360 if (i < len) { 361 char d_buf[16]; 362 int j, i_sav; 363 364 i_sav = i; 365 memset(d_buf, 0, sizeof(d_buf)); 366 for (j = 0; i < len; j++, i++) 367 d_buf[j] = buf[i]; 368 i40e_debug(hw, mask, 369 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n", 370 i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3], 371 d_buf[4], d_buf[5], d_buf[6], d_buf[7], 372 d_buf[8], d_buf[9], d_buf[10], d_buf[11], 373 d_buf[12], d_buf[13], d_buf[14], d_buf[15]); 374 } 375 } 376 } 377 378 /** 379 * i40e_check_asq_alive 380 * @hw: pointer to the hw struct 381 * 382 * Returns TRUE if Queue is enabled else FALSE. 383 **/ 384 bool i40e_check_asq_alive(struct i40e_hw *hw) 385 { 386 if (hw->aq.asq.len) { 387 if (!i40e_is_vf(hw)) 388 return !!(rd32(hw, hw->aq.asq.len) & 389 I40E_PF_ATQLEN_ATQENABLE_MASK); 390 else 391 return !!(rd32(hw, hw->aq.asq.len) & 392 I40E_VF_ATQLEN1_ATQENABLE_MASK); 393 } 394 return FALSE; 395 } 396 397 /** 398 * i40e_aq_queue_shutdown 399 * @hw: pointer to the hw struct 400 * @unloading: is the driver unloading itself 401 * 402 * Tell the Firmware that we're shutting down the AdminQ and whether 403 * or not the driver is unloading as well. 404 **/ 405 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw, 406 bool unloading) 407 { 408 struct i40e_aq_desc desc; 409 struct i40e_aqc_queue_shutdown *cmd = 410 (struct i40e_aqc_queue_shutdown *)&desc.params.raw; 411 enum i40e_status_code status; 412 413 i40e_fill_default_direct_cmd_desc(&desc, 414 i40e_aqc_opc_queue_shutdown); 415 416 if (unloading) 417 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING); 418 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 419 420 return status; 421 } 422 423 /** 424 * i40e_aq_get_set_rss_lut 425 * @hw: pointer to the hardware structure 426 * @vsi_id: vsi fw index 427 * @pf_lut: for PF table set TRUE, for VSI table set FALSE 428 * @lut: pointer to the lut buffer provided by the caller 429 * @lut_size: size of the lut buffer 430 * @set: set TRUE to set the table, FALSE to get the table 431 * 432 * Internal function to get or set RSS look up table 433 **/ 434 static enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw, 435 u16 vsi_id, bool pf_lut, 436 u8 *lut, u16 lut_size, 437 bool set) 438 { 439 enum i40e_status_code status; 440 struct i40e_aq_desc desc; 441 struct i40e_aqc_get_set_rss_lut *cmd_resp = 442 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw; 443 444 if (set) 445 i40e_fill_default_direct_cmd_desc(&desc, 446 i40e_aqc_opc_set_rss_lut); 447 else 448 i40e_fill_default_direct_cmd_desc(&desc, 449 i40e_aqc_opc_get_rss_lut); 450 451 /* Indirect command */ 452 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 453 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 454 455 cmd_resp->vsi_id = 456 CPU_TO_LE16((u16)((vsi_id << 457 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) & 458 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK)); 459 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID); 460 461 if (pf_lut) 462 cmd_resp->flags |= CPU_TO_LE16((u16) 463 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF << 464 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 465 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 466 else 467 cmd_resp->flags |= CPU_TO_LE16((u16) 468 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI << 469 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 470 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 471 472 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL); 473 474 return status; 475 } 476 477 /** 478 * i40e_aq_get_rss_lut 479 * @hw: pointer to the hardware structure 480 * @vsi_id: vsi fw index 481 * @pf_lut: for PF table set TRUE, for VSI table set FALSE 482 * @lut: pointer to the lut buffer provided by the caller 483 * @lut_size: size of the lut buffer 484 * 485 * get the RSS lookup table, PF or VSI type 486 **/ 487 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id, 488 bool pf_lut, u8 *lut, u16 lut_size) 489 { 490 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, 491 FALSE); 492 } 493 494 /** 495 * i40e_aq_set_rss_lut 496 * @hw: pointer to the hardware structure 497 * @vsi_id: vsi fw index 498 * @pf_lut: for PF table set TRUE, for VSI table set FALSE 499 * @lut: pointer to the lut buffer provided by the caller 500 * @lut_size: size of the lut buffer 501 * 502 * set the RSS lookup table, PF or VSI type 503 **/ 504 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id, 505 bool pf_lut, u8 *lut, u16 lut_size) 506 { 507 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, TRUE); 508 } 509 510 /** 511 * i40e_aq_get_set_rss_key 512 * @hw: pointer to the hw struct 513 * @vsi_id: vsi fw index 514 * @key: pointer to key info struct 515 * @set: set TRUE to set the key, FALSE to get the key 516 * 517 * get the RSS key per VSI 518 **/ 519 static enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw, 520 u16 vsi_id, 521 struct i40e_aqc_get_set_rss_key_data *key, 522 bool set) 523 { 524 enum i40e_status_code status; 525 struct i40e_aq_desc desc; 526 struct i40e_aqc_get_set_rss_key *cmd_resp = 527 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw; 528 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data); 529 530 if (set) 531 i40e_fill_default_direct_cmd_desc(&desc, 532 i40e_aqc_opc_set_rss_key); 533 else 534 i40e_fill_default_direct_cmd_desc(&desc, 535 i40e_aqc_opc_get_rss_key); 536 537 /* Indirect command */ 538 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 539 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 540 541 cmd_resp->vsi_id = 542 CPU_TO_LE16((u16)((vsi_id << 543 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) & 544 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK)); 545 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID); 546 547 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL); 548 549 return status; 550 } 551 552 /** 553 * i40e_aq_get_rss_key 554 * @hw: pointer to the hw struct 555 * @vsi_id: vsi fw index 556 * @key: pointer to key info struct 557 * 558 **/ 559 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw, 560 u16 vsi_id, 561 struct i40e_aqc_get_set_rss_key_data *key) 562 { 563 return i40e_aq_get_set_rss_key(hw, vsi_id, key, FALSE); 564 } 565 566 /** 567 * i40e_aq_set_rss_key 568 * @hw: pointer to the hw struct 569 * @vsi_id: vsi fw index 570 * @key: pointer to key info struct 571 * 572 * set the RSS key per VSI 573 **/ 574 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw, 575 u16 vsi_id, 576 struct i40e_aqc_get_set_rss_key_data *key) 577 { 578 return i40e_aq_get_set_rss_key(hw, vsi_id, key, TRUE); 579 } 580 581 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the 582 * hardware to a bit-field that can be used by SW to more easily determine the 583 * packet type. 584 * 585 * Macros are used to shorten the table lines and make this table human 586 * readable. 587 * 588 * We store the PTYPE in the top byte of the bit field - this is just so that 589 * we can check that the table doesn't have a row missing, as the index into 590 * the table should be the PTYPE. 591 * 592 * Typical work flow: 593 * 594 * IF NOT i40e_ptype_lookup[ptype].known 595 * THEN 596 * Packet is unknown 597 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP 598 * Use the rest of the fields to look at the tunnels, inner protocols, etc 599 * ELSE 600 * Use the enum i40e_rx_l2_ptype to decode the packet type 601 * ENDIF 602 */ 603 604 /* macro to make the table lines short */ 605 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\ 606 { PTYPE, \ 607 1, \ 608 I40E_RX_PTYPE_OUTER_##OUTER_IP, \ 609 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \ 610 I40E_RX_PTYPE_##OUTER_FRAG, \ 611 I40E_RX_PTYPE_TUNNEL_##T, \ 612 I40E_RX_PTYPE_TUNNEL_END_##TE, \ 613 I40E_RX_PTYPE_##TEF, \ 614 I40E_RX_PTYPE_INNER_PROT_##I, \ 615 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL } 616 617 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \ 618 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 619 620 /* shorter macros makes the table fit but are terse */ 621 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG 622 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG 623 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC 624 625 /* Lookup table mapping the HW PTYPE to the bit field for decoding */ 626 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = { 627 /* L2 Packet types */ 628 I40E_PTT_UNUSED_ENTRY(0), 629 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 630 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2), 631 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 632 I40E_PTT_UNUSED_ENTRY(4), 633 I40E_PTT_UNUSED_ENTRY(5), 634 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 635 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 636 I40E_PTT_UNUSED_ENTRY(8), 637 I40E_PTT_UNUSED_ENTRY(9), 638 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 639 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 640 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 641 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 642 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 643 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 644 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 645 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 646 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 647 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 648 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 649 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 650 651 /* Non Tunneled IPv4 */ 652 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3), 653 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3), 654 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4), 655 I40E_PTT_UNUSED_ENTRY(25), 656 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4), 657 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4), 658 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4), 659 660 /* IPv4 --> IPv4 */ 661 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 662 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 663 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 664 I40E_PTT_UNUSED_ENTRY(32), 665 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 666 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 667 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 668 669 /* IPv4 --> IPv6 */ 670 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 671 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 672 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 673 I40E_PTT_UNUSED_ENTRY(39), 674 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 675 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 676 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 677 678 /* IPv4 --> GRE/NAT */ 679 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 680 681 /* IPv4 --> GRE/NAT --> IPv4 */ 682 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 683 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 684 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 685 I40E_PTT_UNUSED_ENTRY(47), 686 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 687 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 688 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 689 690 /* IPv4 --> GRE/NAT --> IPv6 */ 691 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 692 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 693 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 694 I40E_PTT_UNUSED_ENTRY(54), 695 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 696 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 697 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 698 699 /* IPv4 --> GRE/NAT --> MAC */ 700 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 701 702 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */ 703 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 704 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 705 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 706 I40E_PTT_UNUSED_ENTRY(62), 707 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 708 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 709 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 710 711 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */ 712 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 713 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 714 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 715 I40E_PTT_UNUSED_ENTRY(69), 716 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 717 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 718 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 719 720 /* IPv4 --> GRE/NAT --> MAC/VLAN */ 721 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 722 723 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */ 724 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 725 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 726 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 727 I40E_PTT_UNUSED_ENTRY(77), 728 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 729 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 730 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 731 732 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */ 733 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 734 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 735 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 736 I40E_PTT_UNUSED_ENTRY(84), 737 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 738 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 739 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 740 741 /* Non Tunneled IPv6 */ 742 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3), 743 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3), 744 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4), 745 I40E_PTT_UNUSED_ENTRY(91), 746 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4), 747 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4), 748 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4), 749 750 /* IPv6 --> IPv4 */ 751 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 752 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 753 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 754 I40E_PTT_UNUSED_ENTRY(98), 755 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 756 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 757 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 758 759 /* IPv6 --> IPv6 */ 760 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 761 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 762 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 763 I40E_PTT_UNUSED_ENTRY(105), 764 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 765 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 766 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 767 768 /* IPv6 --> GRE/NAT */ 769 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 770 771 /* IPv6 --> GRE/NAT -> IPv4 */ 772 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 773 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 774 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 775 I40E_PTT_UNUSED_ENTRY(113), 776 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 777 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 778 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 779 780 /* IPv6 --> GRE/NAT -> IPv6 */ 781 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 782 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 783 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 784 I40E_PTT_UNUSED_ENTRY(120), 785 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 786 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 787 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 788 789 /* IPv6 --> GRE/NAT -> MAC */ 790 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 791 792 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */ 793 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 794 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 795 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 796 I40E_PTT_UNUSED_ENTRY(128), 797 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 798 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 799 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 800 801 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */ 802 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 803 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 804 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 805 I40E_PTT_UNUSED_ENTRY(135), 806 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 807 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 808 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 809 810 /* IPv6 --> GRE/NAT -> MAC/VLAN */ 811 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 812 813 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */ 814 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 815 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 816 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 817 I40E_PTT_UNUSED_ENTRY(143), 818 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 819 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 820 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 821 822 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */ 823 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 824 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 825 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 826 I40E_PTT_UNUSED_ENTRY(150), 827 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 828 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 829 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 830 831 /* unused entries */ 832 I40E_PTT_UNUSED_ENTRY(154), 833 I40E_PTT_UNUSED_ENTRY(155), 834 I40E_PTT_UNUSED_ENTRY(156), 835 I40E_PTT_UNUSED_ENTRY(157), 836 I40E_PTT_UNUSED_ENTRY(158), 837 I40E_PTT_UNUSED_ENTRY(159), 838 839 I40E_PTT_UNUSED_ENTRY(160), 840 I40E_PTT_UNUSED_ENTRY(161), 841 I40E_PTT_UNUSED_ENTRY(162), 842 I40E_PTT_UNUSED_ENTRY(163), 843 I40E_PTT_UNUSED_ENTRY(164), 844 I40E_PTT_UNUSED_ENTRY(165), 845 I40E_PTT_UNUSED_ENTRY(166), 846 I40E_PTT_UNUSED_ENTRY(167), 847 I40E_PTT_UNUSED_ENTRY(168), 848 I40E_PTT_UNUSED_ENTRY(169), 849 850 I40E_PTT_UNUSED_ENTRY(170), 851 I40E_PTT_UNUSED_ENTRY(171), 852 I40E_PTT_UNUSED_ENTRY(172), 853 I40E_PTT_UNUSED_ENTRY(173), 854 I40E_PTT_UNUSED_ENTRY(174), 855 I40E_PTT_UNUSED_ENTRY(175), 856 I40E_PTT_UNUSED_ENTRY(176), 857 I40E_PTT_UNUSED_ENTRY(177), 858 I40E_PTT_UNUSED_ENTRY(178), 859 I40E_PTT_UNUSED_ENTRY(179), 860 861 I40E_PTT_UNUSED_ENTRY(180), 862 I40E_PTT_UNUSED_ENTRY(181), 863 I40E_PTT_UNUSED_ENTRY(182), 864 I40E_PTT_UNUSED_ENTRY(183), 865 I40E_PTT_UNUSED_ENTRY(184), 866 I40E_PTT_UNUSED_ENTRY(185), 867 I40E_PTT_UNUSED_ENTRY(186), 868 I40E_PTT_UNUSED_ENTRY(187), 869 I40E_PTT_UNUSED_ENTRY(188), 870 I40E_PTT_UNUSED_ENTRY(189), 871 872 I40E_PTT_UNUSED_ENTRY(190), 873 I40E_PTT_UNUSED_ENTRY(191), 874 I40E_PTT_UNUSED_ENTRY(192), 875 I40E_PTT_UNUSED_ENTRY(193), 876 I40E_PTT_UNUSED_ENTRY(194), 877 I40E_PTT_UNUSED_ENTRY(195), 878 I40E_PTT_UNUSED_ENTRY(196), 879 I40E_PTT_UNUSED_ENTRY(197), 880 I40E_PTT_UNUSED_ENTRY(198), 881 I40E_PTT_UNUSED_ENTRY(199), 882 883 I40E_PTT_UNUSED_ENTRY(200), 884 I40E_PTT_UNUSED_ENTRY(201), 885 I40E_PTT_UNUSED_ENTRY(202), 886 I40E_PTT_UNUSED_ENTRY(203), 887 I40E_PTT_UNUSED_ENTRY(204), 888 I40E_PTT_UNUSED_ENTRY(205), 889 I40E_PTT_UNUSED_ENTRY(206), 890 I40E_PTT_UNUSED_ENTRY(207), 891 I40E_PTT_UNUSED_ENTRY(208), 892 I40E_PTT_UNUSED_ENTRY(209), 893 894 I40E_PTT_UNUSED_ENTRY(210), 895 I40E_PTT_UNUSED_ENTRY(211), 896 I40E_PTT_UNUSED_ENTRY(212), 897 I40E_PTT_UNUSED_ENTRY(213), 898 I40E_PTT_UNUSED_ENTRY(214), 899 I40E_PTT_UNUSED_ENTRY(215), 900 I40E_PTT_UNUSED_ENTRY(216), 901 I40E_PTT_UNUSED_ENTRY(217), 902 I40E_PTT_UNUSED_ENTRY(218), 903 I40E_PTT_UNUSED_ENTRY(219), 904 905 I40E_PTT_UNUSED_ENTRY(220), 906 I40E_PTT_UNUSED_ENTRY(221), 907 I40E_PTT_UNUSED_ENTRY(222), 908 I40E_PTT_UNUSED_ENTRY(223), 909 I40E_PTT_UNUSED_ENTRY(224), 910 I40E_PTT_UNUSED_ENTRY(225), 911 I40E_PTT_UNUSED_ENTRY(226), 912 I40E_PTT_UNUSED_ENTRY(227), 913 I40E_PTT_UNUSED_ENTRY(228), 914 I40E_PTT_UNUSED_ENTRY(229), 915 916 I40E_PTT_UNUSED_ENTRY(230), 917 I40E_PTT_UNUSED_ENTRY(231), 918 I40E_PTT_UNUSED_ENTRY(232), 919 I40E_PTT_UNUSED_ENTRY(233), 920 I40E_PTT_UNUSED_ENTRY(234), 921 I40E_PTT_UNUSED_ENTRY(235), 922 I40E_PTT_UNUSED_ENTRY(236), 923 I40E_PTT_UNUSED_ENTRY(237), 924 I40E_PTT_UNUSED_ENTRY(238), 925 I40E_PTT_UNUSED_ENTRY(239), 926 927 I40E_PTT_UNUSED_ENTRY(240), 928 I40E_PTT_UNUSED_ENTRY(241), 929 I40E_PTT_UNUSED_ENTRY(242), 930 I40E_PTT_UNUSED_ENTRY(243), 931 I40E_PTT_UNUSED_ENTRY(244), 932 I40E_PTT_UNUSED_ENTRY(245), 933 I40E_PTT_UNUSED_ENTRY(246), 934 I40E_PTT_UNUSED_ENTRY(247), 935 I40E_PTT_UNUSED_ENTRY(248), 936 I40E_PTT_UNUSED_ENTRY(249), 937 938 I40E_PTT_UNUSED_ENTRY(250), 939 I40E_PTT_UNUSED_ENTRY(251), 940 I40E_PTT_UNUSED_ENTRY(252), 941 I40E_PTT_UNUSED_ENTRY(253), 942 I40E_PTT_UNUSED_ENTRY(254), 943 I40E_PTT_UNUSED_ENTRY(255) 944 }; 945 946 947 /** 948 * i40e_validate_mac_addr - Validate unicast MAC address 949 * @mac_addr: pointer to MAC address 950 * 951 * Tests a MAC address to ensure it is a valid Individual Address 952 **/ 953 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr) 954 { 955 enum i40e_status_code status = I40E_SUCCESS; 956 957 DEBUGFUNC("i40e_validate_mac_addr"); 958 959 /* Broadcast addresses ARE multicast addresses 960 * Make sure it is not a multicast address 961 * Reject the zero address 962 */ 963 if (I40E_IS_MULTICAST(mac_addr) || 964 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 965 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0)) 966 status = I40E_ERR_INVALID_MAC_ADDR; 967 968 return status; 969 } 970 971 /** 972 * i40e_init_shared_code - Initialize the shared code 973 * @hw: pointer to hardware structure 974 * 975 * This assigns the MAC type and PHY code and inits the NVM. 976 * Does not touch the hardware. This function must be called prior to any 977 * other function in the shared code. The i40e_hw structure should be 978 * memset to 0 prior to calling this function. The following fields in 979 * hw structure should be filled in prior to calling this function: 980 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 981 * subsystem_vendor_id, and revision_id 982 **/ 983 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw) 984 { 985 enum i40e_status_code status = I40E_SUCCESS; 986 u32 port, ari, func_rid; 987 988 DEBUGFUNC("i40e_init_shared_code"); 989 990 i40e_set_mac_type(hw); 991 992 switch (hw->mac.type) { 993 case I40E_MAC_XL710: 994 case I40E_MAC_X722: 995 break; 996 default: 997 return I40E_ERR_DEVICE_NOT_SUPPORTED; 998 } 999 1000 hw->phy.get_link_info = TRUE; 1001 1002 /* Determine port number and PF number*/ 1003 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) 1004 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT; 1005 hw->port = (u8)port; 1006 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >> 1007 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; 1008 func_rid = rd32(hw, I40E_PF_FUNC_RID); 1009 if (ari) 1010 hw->pf_id = (u8)(func_rid & 0xff); 1011 else 1012 hw->pf_id = (u8)(func_rid & 0x7); 1013 1014 if (hw->mac.type == I40E_MAC_X722) 1015 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE | 1016 I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK; 1017 1018 status = i40e_init_nvm(hw); 1019 return status; 1020 } 1021 1022 /** 1023 * i40e_aq_mac_address_read - Retrieve the MAC addresses 1024 * @hw: pointer to the hw struct 1025 * @flags: a return indicator of what addresses were added to the addr store 1026 * @addrs: the requestor's mac addr store 1027 * @cmd_details: pointer to command details structure or NULL 1028 **/ 1029 static enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw, 1030 u16 *flags, 1031 struct i40e_aqc_mac_address_read_data *addrs, 1032 struct i40e_asq_cmd_details *cmd_details) 1033 { 1034 struct i40e_aq_desc desc; 1035 struct i40e_aqc_mac_address_read *cmd_data = 1036 (struct i40e_aqc_mac_address_read *)&desc.params.raw; 1037 enum i40e_status_code status; 1038 1039 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read); 1040 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 1041 1042 status = i40e_asq_send_command(hw, &desc, addrs, 1043 sizeof(*addrs), cmd_details); 1044 *flags = LE16_TO_CPU(cmd_data->command_flags); 1045 1046 return status; 1047 } 1048 1049 /** 1050 * i40e_aq_mac_address_write - Change the MAC addresses 1051 * @hw: pointer to the hw struct 1052 * @flags: indicates which MAC to be written 1053 * @mac_addr: address to write 1054 * @cmd_details: pointer to command details structure or NULL 1055 **/ 1056 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw, 1057 u16 flags, u8 *mac_addr, 1058 struct i40e_asq_cmd_details *cmd_details) 1059 { 1060 struct i40e_aq_desc desc; 1061 struct i40e_aqc_mac_address_write *cmd_data = 1062 (struct i40e_aqc_mac_address_write *)&desc.params.raw; 1063 enum i40e_status_code status; 1064 1065 i40e_fill_default_direct_cmd_desc(&desc, 1066 i40e_aqc_opc_mac_address_write); 1067 cmd_data->command_flags = CPU_TO_LE16(flags); 1068 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]); 1069 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) | 1070 ((u32)mac_addr[3] << 16) | 1071 ((u32)mac_addr[4] << 8) | 1072 mac_addr[5]); 1073 1074 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1075 1076 return status; 1077 } 1078 1079 /** 1080 * i40e_get_mac_addr - get MAC address 1081 * @hw: pointer to the HW structure 1082 * @mac_addr: pointer to MAC address 1083 * 1084 * Reads the adapter's MAC address from register 1085 **/ 1086 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1087 { 1088 struct i40e_aqc_mac_address_read_data addrs; 1089 enum i40e_status_code status; 1090 u16 flags = 0; 1091 1092 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1093 1094 if (flags & I40E_AQC_LAN_ADDR_VALID) 1095 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac), 1096 I40E_NONDMA_TO_NONDMA); 1097 1098 return status; 1099 } 1100 1101 /** 1102 * i40e_get_port_mac_addr - get Port MAC address 1103 * @hw: pointer to the HW structure 1104 * @mac_addr: pointer to Port MAC address 1105 * 1106 * Reads the adapter's Port MAC address 1107 **/ 1108 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1109 { 1110 struct i40e_aqc_mac_address_read_data addrs; 1111 enum i40e_status_code status; 1112 u16 flags = 0; 1113 1114 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1115 if (status) 1116 return status; 1117 1118 if (flags & I40E_AQC_PORT_ADDR_VALID) 1119 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac), 1120 I40E_NONDMA_TO_NONDMA); 1121 else 1122 status = I40E_ERR_INVALID_MAC_ADDR; 1123 1124 return status; 1125 } 1126 1127 /** 1128 * i40e_pre_tx_queue_cfg - pre tx queue configure 1129 * @hw: pointer to the HW structure 1130 * @queue: target pf queue index 1131 * @enable: state change request 1132 * 1133 * Handles hw requirement to indicate intention to enable 1134 * or disable target queue. 1135 **/ 1136 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable) 1137 { 1138 u32 abs_queue_idx = hw->func_caps.base_queue + queue; 1139 u32 reg_block = 0; 1140 u32 reg_val; 1141 1142 if (abs_queue_idx >= 128) { 1143 reg_block = abs_queue_idx / 128; 1144 abs_queue_idx %= 128; 1145 } 1146 1147 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1148 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1149 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1150 1151 if (enable) 1152 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK; 1153 else 1154 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1155 1156 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); 1157 } 1158 1159 /** 1160 * i40e_read_pba_string - Reads part number string from EEPROM 1161 * @hw: pointer to hardware structure 1162 * @pba_num: stores the part number string from the EEPROM 1163 * @pba_num_size: part number string buffer length 1164 * 1165 * Reads the part number string from the EEPROM. 1166 **/ 1167 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num, 1168 u32 pba_num_size) 1169 { 1170 enum i40e_status_code status = I40E_SUCCESS; 1171 u16 pba_word = 0; 1172 u16 pba_size = 0; 1173 u16 pba_ptr = 0; 1174 u16 i = 0; 1175 1176 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word); 1177 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) { 1178 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n"); 1179 return status; 1180 } 1181 1182 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr); 1183 if (status != I40E_SUCCESS) { 1184 DEBUGOUT("Failed to read PBA Block pointer.\n"); 1185 return status; 1186 } 1187 1188 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size); 1189 if (status != I40E_SUCCESS) { 1190 DEBUGOUT("Failed to read PBA Block size.\n"); 1191 return status; 1192 } 1193 1194 /* Subtract one to get PBA word count (PBA Size word is included in 1195 * total size) 1196 */ 1197 pba_size--; 1198 if (pba_num_size < (((u32)pba_size * 2) + 1)) { 1199 DEBUGOUT("Buffer to small for PBA data.\n"); 1200 return I40E_ERR_PARAM; 1201 } 1202 1203 for (i = 0; i < pba_size; i++) { 1204 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word); 1205 if (status != I40E_SUCCESS) { 1206 DEBUGOUT1("Failed to read PBA Block word %d.\n", i); 1207 return status; 1208 } 1209 1210 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF; 1211 pba_num[(i * 2) + 1] = pba_word & 0xFF; 1212 } 1213 pba_num[(pba_size * 2)] = '\0'; 1214 1215 return status; 1216 } 1217 1218 /** 1219 * i40e_get_media_type - Gets media type 1220 * @hw: pointer to the hardware structure 1221 **/ 1222 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) 1223 { 1224 enum i40e_media_type media; 1225 1226 switch (hw->phy.link_info.phy_type) { 1227 case I40E_PHY_TYPE_10GBASE_SR: 1228 case I40E_PHY_TYPE_10GBASE_LR: 1229 case I40E_PHY_TYPE_1000BASE_SX: 1230 case I40E_PHY_TYPE_1000BASE_LX: 1231 case I40E_PHY_TYPE_40GBASE_SR4: 1232 case I40E_PHY_TYPE_40GBASE_LR4: 1233 case I40E_PHY_TYPE_25GBASE_LR: 1234 case I40E_PHY_TYPE_25GBASE_SR: 1235 media = I40E_MEDIA_TYPE_FIBER; 1236 break; 1237 case I40E_PHY_TYPE_100BASE_TX: 1238 case I40E_PHY_TYPE_1000BASE_T: 1239 case I40E_PHY_TYPE_10GBASE_T: 1240 media = I40E_MEDIA_TYPE_BASET; 1241 break; 1242 case I40E_PHY_TYPE_10GBASE_CR1_CU: 1243 case I40E_PHY_TYPE_40GBASE_CR4_CU: 1244 case I40E_PHY_TYPE_10GBASE_CR1: 1245 case I40E_PHY_TYPE_40GBASE_CR4: 1246 case I40E_PHY_TYPE_10GBASE_SFPP_CU: 1247 case I40E_PHY_TYPE_40GBASE_AOC: 1248 case I40E_PHY_TYPE_10GBASE_AOC: 1249 case I40E_PHY_TYPE_25GBASE_CR: 1250 case I40E_PHY_TYPE_25GBASE_AOC: 1251 case I40E_PHY_TYPE_25GBASE_ACC: 1252 media = I40E_MEDIA_TYPE_DA; 1253 break; 1254 case I40E_PHY_TYPE_1000BASE_KX: 1255 case I40E_PHY_TYPE_10GBASE_KX4: 1256 case I40E_PHY_TYPE_10GBASE_KR: 1257 case I40E_PHY_TYPE_40GBASE_KR4: 1258 case I40E_PHY_TYPE_20GBASE_KR2: 1259 case I40E_PHY_TYPE_25GBASE_KR: 1260 media = I40E_MEDIA_TYPE_BACKPLANE; 1261 break; 1262 case I40E_PHY_TYPE_SGMII: 1263 case I40E_PHY_TYPE_XAUI: 1264 case I40E_PHY_TYPE_XFI: 1265 case I40E_PHY_TYPE_XLAUI: 1266 case I40E_PHY_TYPE_XLPPI: 1267 default: 1268 media = I40E_MEDIA_TYPE_UNKNOWN; 1269 break; 1270 } 1271 1272 return media; 1273 } 1274 1275 #define I40E_PF_RESET_WAIT_COUNT 200 1276 /** 1277 * i40e_pf_reset - Reset the PF 1278 * @hw: pointer to the hardware structure 1279 * 1280 * Assuming someone else has triggered a global reset, 1281 * assure the global reset is complete and then reset the PF 1282 **/ 1283 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw) 1284 { 1285 u32 cnt = 0; 1286 u32 cnt1 = 0; 1287 u32 reg = 0; 1288 u32 grst_del; 1289 1290 /* Poll for Global Reset steady state in case of recent GRST. 1291 * The grst delay value is in 100ms units, and we'll wait a 1292 * couple counts longer to be sure we don't just miss the end. 1293 */ 1294 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) & 1295 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >> 1296 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; 1297 1298 grst_del = grst_del * 20; 1299 1300 for (cnt = 0; cnt < grst_del; cnt++) { 1301 reg = rd32(hw, I40E_GLGEN_RSTAT); 1302 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 1303 break; 1304 i40e_msec_delay(100); 1305 } 1306 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 1307 DEBUGOUT("Global reset polling failed to complete.\n"); 1308 return I40E_ERR_RESET_FAILED; 1309 } 1310 1311 /* Now Wait for the FW to be ready */ 1312 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 1313 reg = rd32(hw, I40E_GLNVM_ULD); 1314 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1315 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 1316 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1317 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) { 1318 DEBUGOUT1("Core and Global modules ready %d\n", cnt1); 1319 break; 1320 } 1321 i40e_msec_delay(10); 1322 } 1323 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1324 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 1325 DEBUGOUT("wait for FW Reset complete timedout\n"); 1326 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg); 1327 return I40E_ERR_RESET_FAILED; 1328 } 1329 1330 /* If there was a Global Reset in progress when we got here, 1331 * we don't need to do the PF Reset 1332 */ 1333 if (!cnt) { 1334 u32 reg2 = 0; 1335 1336 reg = rd32(hw, I40E_PFGEN_CTRL); 1337 wr32(hw, I40E_PFGEN_CTRL, 1338 (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); 1339 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) { 1340 reg = rd32(hw, I40E_PFGEN_CTRL); 1341 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 1342 break; 1343 reg2 = rd32(hw, I40E_GLGEN_RSTAT); 1344 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 1345 DEBUGOUT("Core reset upcoming. Skipping PF reset request.\n"); 1346 DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg2); 1347 return I40E_ERR_NOT_READY; 1348 } 1349 i40e_msec_delay(1); 1350 } 1351 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 1352 DEBUGOUT("PF reset polling failed to complete.\n"); 1353 return I40E_ERR_RESET_FAILED; 1354 } 1355 } 1356 1357 i40e_clear_pxe_mode(hw); 1358 1359 1360 return I40E_SUCCESS; 1361 } 1362 1363 /** 1364 * i40e_clear_hw - clear out any left over hw state 1365 * @hw: pointer to the hw struct 1366 * 1367 * Clear queues and interrupts, typically called at init time, 1368 * but after the capabilities have been found so we know how many 1369 * queues and msix vectors have been allocated. 1370 **/ 1371 void i40e_clear_hw(struct i40e_hw *hw) 1372 { 1373 u32 num_queues, base_queue; 1374 u32 num_pf_int; 1375 u32 num_vf_int; 1376 u32 num_vfs; 1377 u32 i, j; 1378 u32 val; 1379 u32 eol = 0x7ff; 1380 1381 /* get number of interrupts, queues, and vfs */ 1382 val = rd32(hw, I40E_GLPCI_CNF2); 1383 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> 1384 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; 1385 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> 1386 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; 1387 1388 val = rd32(hw, I40E_PFLAN_QALLOC); 1389 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 1390 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 1391 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> 1392 I40E_PFLAN_QALLOC_LASTQ_SHIFT; 1393 if (val & I40E_PFLAN_QALLOC_VALID_MASK) 1394 num_queues = (j - base_queue) + 1; 1395 else 1396 num_queues = 0; 1397 1398 val = rd32(hw, I40E_PF_VT_PFALLOC); 1399 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> 1400 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; 1401 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> 1402 I40E_PF_VT_PFALLOC_LASTVF_SHIFT; 1403 if (val & I40E_PF_VT_PFALLOC_VALID_MASK) 1404 num_vfs = (j - i) + 1; 1405 else 1406 num_vfs = 0; 1407 1408 /* stop all the interrupts */ 1409 wr32(hw, I40E_PFINT_ICR0_ENA, 0); 1410 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 1411 for (i = 0; i < num_pf_int - 2; i++) 1412 wr32(hw, I40E_PFINT_DYN_CTLN(i), val); 1413 1414 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 1415 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1416 wr32(hw, I40E_PFINT_LNKLST0, val); 1417 for (i = 0; i < num_pf_int - 2; i++) 1418 wr32(hw, I40E_PFINT_LNKLSTN(i), val); 1419 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1420 for (i = 0; i < num_vfs; i++) 1421 wr32(hw, I40E_VPINT_LNKLST0(i), val); 1422 for (i = 0; i < num_vf_int - 2; i++) 1423 wr32(hw, I40E_VPINT_LNKLSTN(i), val); 1424 1425 /* warn the HW of the coming Tx disables */ 1426 for (i = 0; i < num_queues; i++) { 1427 u32 abs_queue_idx = base_queue + i; 1428 u32 reg_block = 0; 1429 1430 if (abs_queue_idx >= 128) { 1431 reg_block = abs_queue_idx / 128; 1432 abs_queue_idx %= 128; 1433 } 1434 1435 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1436 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1437 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1438 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1439 1440 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 1441 } 1442 i40e_usec_delay(400); 1443 1444 /* stop all the queues */ 1445 for (i = 0; i < num_queues; i++) { 1446 wr32(hw, I40E_QINT_TQCTL(i), 0); 1447 wr32(hw, I40E_QTX_ENA(i), 0); 1448 wr32(hw, I40E_QINT_RQCTL(i), 0); 1449 wr32(hw, I40E_QRX_ENA(i), 0); 1450 } 1451 1452 /* short wait for all queue disables to settle */ 1453 i40e_usec_delay(50); 1454 } 1455 1456 /** 1457 * i40e_clear_pxe_mode - clear pxe operations mode 1458 * @hw: pointer to the hw struct 1459 * 1460 * Make sure all PXE mode settings are cleared, including things 1461 * like descriptor fetch/write-back mode. 1462 **/ 1463 void i40e_clear_pxe_mode(struct i40e_hw *hw) 1464 { 1465 if (i40e_check_asq_alive(hw)) 1466 i40e_aq_clear_pxe_mode(hw, NULL); 1467 } 1468 1469 /** 1470 * i40e_led_is_mine - helper to find matching led 1471 * @hw: pointer to the hw struct 1472 * @idx: index into GPIO registers 1473 * 1474 * returns: 0 if no match, otherwise the value of the GPIO_CTL register 1475 */ 1476 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx) 1477 { 1478 u32 gpio_val = 0; 1479 u32 port; 1480 1481 if (!hw->func_caps.led[idx]) 1482 return 0; 1483 1484 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx)); 1485 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >> 1486 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT; 1487 1488 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR 1489 * if it is not our port then ignore 1490 */ 1491 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) || 1492 (port != hw->port)) 1493 return 0; 1494 1495 return gpio_val; 1496 } 1497 1498 #define I40E_COMBINED_ACTIVITY 0xA 1499 #define I40E_FILTER_ACTIVITY 0xE 1500 #define I40E_LINK_ACTIVITY 0xC 1501 #define I40E_MAC_ACTIVITY 0xD 1502 #define I40E_LED0 22 1503 1504 /** 1505 * i40e_led_get - return current on/off mode 1506 * @hw: pointer to the hw struct 1507 * 1508 * The value returned is the 'mode' field as defined in the 1509 * GPIO register definitions: 0x0 = off, 0xf = on, and other 1510 * values are variations of possible behaviors relating to 1511 * blink, link, and wire. 1512 **/ 1513 u32 i40e_led_get(struct i40e_hw *hw) 1514 { 1515 u32 current_mode = 0; 1516 u32 mode = 0; 1517 int i; 1518 1519 /* as per the documentation GPIO 22-29 are the LED 1520 * GPIO pins named LED0..LED7 1521 */ 1522 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1523 u32 gpio_val = i40e_led_is_mine(hw, i); 1524 1525 if (!gpio_val) 1526 continue; 1527 1528 /* ignore gpio LED src mode entries related to the activity 1529 * LEDs 1530 */ 1531 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1532 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1533 switch (current_mode) { 1534 case I40E_COMBINED_ACTIVITY: 1535 case I40E_FILTER_ACTIVITY: 1536 case I40E_MAC_ACTIVITY: 1537 case I40E_LINK_ACTIVITY: 1538 continue; 1539 default: 1540 break; 1541 } 1542 1543 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >> 1544 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT; 1545 break; 1546 } 1547 1548 return mode; 1549 } 1550 1551 /** 1552 * i40e_led_set - set new on/off mode 1553 * @hw: pointer to the hw struct 1554 * @mode: 0=off, 0xf=on (else see manual for mode details) 1555 * @blink: TRUE if the LED should blink when on, FALSE if steady 1556 * 1557 * if this function is used to turn on the blink it should 1558 * be used to disable the blink when restoring the original state. 1559 **/ 1560 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink) 1561 { 1562 u32 current_mode = 0; 1563 int i; 1564 1565 if (mode & 0xfffffff0) 1566 DEBUGOUT1("invalid mode passed in %X\n", mode); 1567 1568 /* as per the documentation GPIO 22-29 are the LED 1569 * GPIO pins named LED0..LED7 1570 */ 1571 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1572 u32 gpio_val = i40e_led_is_mine(hw, i); 1573 1574 if (!gpio_val) 1575 continue; 1576 1577 /* ignore gpio LED src mode entries related to the activity 1578 * LEDs 1579 */ 1580 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1581 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1582 switch (current_mode) { 1583 case I40E_COMBINED_ACTIVITY: 1584 case I40E_FILTER_ACTIVITY: 1585 case I40E_MAC_ACTIVITY: 1586 case I40E_LINK_ACTIVITY: 1587 continue; 1588 default: 1589 break; 1590 } 1591 1592 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK; 1593 /* this & is a bit of paranoia, but serves as a range check */ 1594 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) & 1595 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK); 1596 1597 if (blink) 1598 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1599 else 1600 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1601 1602 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val); 1603 break; 1604 } 1605 } 1606 1607 /* Admin command wrappers */ 1608 1609 /** 1610 * i40e_aq_get_phy_capabilities 1611 * @hw: pointer to the hw struct 1612 * @abilities: structure for PHY capabilities to be filled 1613 * @qualified_modules: report Qualified Modules 1614 * @report_init: report init capabilities (active are default) 1615 * @cmd_details: pointer to command details structure or NULL 1616 * 1617 * Returns the various PHY abilities supported on the Port. 1618 **/ 1619 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw, 1620 bool qualified_modules, bool report_init, 1621 struct i40e_aq_get_phy_abilities_resp *abilities, 1622 struct i40e_asq_cmd_details *cmd_details) 1623 { 1624 struct i40e_aq_desc desc; 1625 enum i40e_status_code status; 1626 u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0; 1627 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp); 1628 1629 if (!abilities) 1630 return I40E_ERR_PARAM; 1631 1632 do { 1633 i40e_fill_default_direct_cmd_desc(&desc, 1634 i40e_aqc_opc_get_phy_abilities); 1635 1636 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 1637 if (abilities_size > I40E_AQ_LARGE_BUF) 1638 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 1639 1640 if (qualified_modules) 1641 desc.params.external.param0 |= 1642 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES); 1643 1644 if (report_init) 1645 desc.params.external.param0 |= 1646 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES); 1647 1648 status = i40e_asq_send_command(hw, &desc, abilities, 1649 abilities_size, cmd_details); 1650 1651 if (status != I40E_SUCCESS) 1652 break; 1653 1654 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) { 1655 status = I40E_ERR_UNKNOWN_PHY; 1656 break; 1657 } else if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) { 1658 i40e_msec_delay(1); 1659 total_delay++; 1660 status = I40E_ERR_TIMEOUT; 1661 } 1662 } while ((hw->aq.asq_last_status != I40E_AQ_RC_OK) && 1663 (total_delay < max_delay)); 1664 1665 if (status != I40E_SUCCESS) 1666 return status; 1667 1668 if (report_init) { 1669 if (hw->mac.type == I40E_MAC_XL710 && 1670 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && 1671 hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) { 1672 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL); 1673 } else { 1674 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type); 1675 hw->phy.phy_types |= 1676 ((u64)abilities->phy_type_ext << 32); 1677 } 1678 } 1679 1680 return status; 1681 } 1682 1683 /** 1684 * i40e_aq_set_phy_config 1685 * @hw: pointer to the hw struct 1686 * @config: structure with PHY configuration to be set 1687 * @cmd_details: pointer to command details structure or NULL 1688 * 1689 * Set the various PHY configuration parameters 1690 * supported on the Port.One or more of the Set PHY config parameters may be 1691 * ignored in an MFP mode as the PF may not have the privilege to set some 1692 * of the PHY Config parameters. This status will be indicated by the 1693 * command response. 1694 **/ 1695 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw, 1696 struct i40e_aq_set_phy_config *config, 1697 struct i40e_asq_cmd_details *cmd_details) 1698 { 1699 struct i40e_aq_desc desc; 1700 struct i40e_aq_set_phy_config *cmd = 1701 (struct i40e_aq_set_phy_config *)&desc.params.raw; 1702 enum i40e_status_code status; 1703 1704 if (!config) 1705 return I40E_ERR_PARAM; 1706 1707 i40e_fill_default_direct_cmd_desc(&desc, 1708 i40e_aqc_opc_set_phy_config); 1709 1710 *cmd = *config; 1711 1712 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1713 1714 return status; 1715 } 1716 1717 /** 1718 * i40e_set_fc 1719 * @hw: pointer to the hw struct 1720 * @aq_failures: buffer to return AdminQ failure information 1721 * @atomic_restart: whether to enable atomic link restart 1722 * 1723 * Set the requested flow control mode using set_phy_config. 1724 **/ 1725 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures, 1726 bool atomic_restart) 1727 { 1728 enum i40e_fc_mode fc_mode = hw->fc.requested_mode; 1729 struct i40e_aq_get_phy_abilities_resp abilities; 1730 struct i40e_aq_set_phy_config config; 1731 enum i40e_status_code status; 1732 u8 pause_mask = 0x0; 1733 1734 *aq_failures = 0x0; 1735 1736 switch (fc_mode) { 1737 case I40E_FC_FULL: 1738 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1739 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1740 break; 1741 case I40E_FC_RX_PAUSE: 1742 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1743 break; 1744 case I40E_FC_TX_PAUSE: 1745 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1746 break; 1747 default: 1748 break; 1749 } 1750 1751 /* Get the current phy config */ 1752 status = i40e_aq_get_phy_capabilities(hw, FALSE, false, &abilities, 1753 NULL); 1754 if (status) { 1755 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET; 1756 return status; 1757 } 1758 1759 memset(&config, 0, sizeof(config)); 1760 /* clear the old pause settings */ 1761 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) & 1762 ~(I40E_AQ_PHY_FLAG_PAUSE_RX); 1763 /* set the new abilities */ 1764 config.abilities |= pause_mask; 1765 /* If the abilities have changed, then set the new config */ 1766 if (config.abilities != abilities.abilities) { 1767 /* Auto restart link so settings take effect */ 1768 if (atomic_restart) 1769 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 1770 /* Copy over all the old settings */ 1771 config.phy_type = abilities.phy_type; 1772 config.phy_type_ext = abilities.phy_type_ext; 1773 config.link_speed = abilities.link_speed; 1774 config.eee_capability = abilities.eee_capability; 1775 config.eeer = abilities.eeer_val; 1776 config.low_power_ctrl = abilities.d3_lpan; 1777 config.fec_config = abilities.fec_cfg_curr_mod_ext_info & 1778 I40E_AQ_PHY_FEC_CONFIG_MASK; 1779 status = i40e_aq_set_phy_config(hw, &config, NULL); 1780 1781 if (status) 1782 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET; 1783 } 1784 /* Update the link info */ 1785 status = i40e_update_link_info(hw); 1786 if (status) { 1787 /* Wait a little bit (on 40G cards it sometimes takes a really 1788 * long time for link to come back from the atomic reset) 1789 * and try once more 1790 */ 1791 i40e_msec_delay(1000); 1792 status = i40e_update_link_info(hw); 1793 } 1794 if (status) 1795 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE; 1796 1797 return status; 1798 } 1799 1800 /** 1801 * i40e_aq_set_mac_config 1802 * @hw: pointer to the hw struct 1803 * @max_frame_size: Maximum Frame Size to be supported by the port 1804 * @crc_en: Tell HW to append a CRC to outgoing frames 1805 * @pacing: Pacing configurations 1806 * @cmd_details: pointer to command details structure or NULL 1807 * 1808 * Configure MAC settings for frame size, jumbo frame support and the 1809 * addition of a CRC by the hardware. 1810 **/ 1811 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw, 1812 u16 max_frame_size, 1813 bool crc_en, u16 pacing, 1814 struct i40e_asq_cmd_details *cmd_details) 1815 { 1816 struct i40e_aq_desc desc; 1817 struct i40e_aq_set_mac_config *cmd = 1818 (struct i40e_aq_set_mac_config *)&desc.params.raw; 1819 enum i40e_status_code status; 1820 1821 if (max_frame_size == 0) 1822 return I40E_ERR_PARAM; 1823 1824 i40e_fill_default_direct_cmd_desc(&desc, 1825 i40e_aqc_opc_set_mac_config); 1826 1827 cmd->max_frame_size = CPU_TO_LE16(max_frame_size); 1828 cmd->params = ((u8)pacing & 0x0F) << 3; 1829 if (crc_en) 1830 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN; 1831 1832 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1833 1834 return status; 1835 } 1836 1837 /** 1838 * i40e_aq_clear_pxe_mode 1839 * @hw: pointer to the hw struct 1840 * @cmd_details: pointer to command details structure or NULL 1841 * 1842 * Tell the firmware that the driver is taking over from PXE 1843 **/ 1844 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw, 1845 struct i40e_asq_cmd_details *cmd_details) 1846 { 1847 enum i40e_status_code status; 1848 struct i40e_aq_desc desc; 1849 struct i40e_aqc_clear_pxe *cmd = 1850 (struct i40e_aqc_clear_pxe *)&desc.params.raw; 1851 1852 i40e_fill_default_direct_cmd_desc(&desc, 1853 i40e_aqc_opc_clear_pxe_mode); 1854 1855 cmd->rx_cnt = 0x2; 1856 1857 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1858 1859 wr32(hw, I40E_GLLAN_RCTL_0, 0x1); 1860 1861 return status; 1862 } 1863 1864 /** 1865 * i40e_aq_set_link_restart_an 1866 * @hw: pointer to the hw struct 1867 * @enable_link: if TRUE: enable link, if FALSE: disable link 1868 * @cmd_details: pointer to command details structure or NULL 1869 * 1870 * Sets up the link and restarts the Auto-Negotiation over the link. 1871 **/ 1872 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw, 1873 bool enable_link, struct i40e_asq_cmd_details *cmd_details) 1874 { 1875 struct i40e_aq_desc desc; 1876 struct i40e_aqc_set_link_restart_an *cmd = 1877 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw; 1878 enum i40e_status_code status; 1879 1880 i40e_fill_default_direct_cmd_desc(&desc, 1881 i40e_aqc_opc_set_link_restart_an); 1882 1883 cmd->command = I40E_AQ_PHY_RESTART_AN; 1884 if (enable_link) 1885 cmd->command |= I40E_AQ_PHY_LINK_ENABLE; 1886 else 1887 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE; 1888 1889 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1890 1891 return status; 1892 } 1893 1894 /** 1895 * i40e_aq_get_link_info 1896 * @hw: pointer to the hw struct 1897 * @enable_lse: enable/disable LinkStatusEvent reporting 1898 * @link: pointer to link status structure - optional 1899 * @cmd_details: pointer to command details structure or NULL 1900 * 1901 * Returns the link status of the adapter. 1902 **/ 1903 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw, 1904 bool enable_lse, struct i40e_link_status *link, 1905 struct i40e_asq_cmd_details *cmd_details) 1906 { 1907 struct i40e_aq_desc desc; 1908 struct i40e_aqc_get_link_status *resp = 1909 (struct i40e_aqc_get_link_status *)&desc.params.raw; 1910 struct i40e_link_status *hw_link_info = &hw->phy.link_info; 1911 enum i40e_status_code status; 1912 bool tx_pause, rx_pause; 1913 u16 command_flags; 1914 1915 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status); 1916 1917 if (enable_lse) 1918 command_flags = I40E_AQ_LSE_ENABLE; 1919 else 1920 command_flags = I40E_AQ_LSE_DISABLE; 1921 resp->command_flags = CPU_TO_LE16(command_flags); 1922 1923 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1924 1925 if (status != I40E_SUCCESS) 1926 goto aq_get_link_info_exit; 1927 1928 /* save off old link status information */ 1929 i40e_memcpy(&hw->phy.link_info_old, hw_link_info, 1930 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA); 1931 1932 /* update link status */ 1933 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type; 1934 hw->phy.media_type = i40e_get_media_type(hw); 1935 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed; 1936 hw_link_info->link_info = resp->link_info; 1937 hw_link_info->an_info = resp->an_info; 1938 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA | 1939 I40E_AQ_CONFIG_FEC_RS_ENA); 1940 hw_link_info->ext_info = resp->ext_info; 1941 hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK; 1942 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size); 1943 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK; 1944 1945 /* update fc info */ 1946 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX); 1947 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX); 1948 if (tx_pause & rx_pause) 1949 hw->fc.current_mode = I40E_FC_FULL; 1950 else if (tx_pause) 1951 hw->fc.current_mode = I40E_FC_TX_PAUSE; 1952 else if (rx_pause) 1953 hw->fc.current_mode = I40E_FC_RX_PAUSE; 1954 else 1955 hw->fc.current_mode = I40E_FC_NONE; 1956 1957 if (resp->config & I40E_AQ_CONFIG_CRC_ENA) 1958 hw_link_info->crc_enable = TRUE; 1959 else 1960 hw_link_info->crc_enable = FALSE; 1961 1962 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED)) 1963 hw_link_info->lse_enable = TRUE; 1964 else 1965 hw_link_info->lse_enable = FALSE; 1966 1967 if ((hw->mac.type == I40E_MAC_XL710) && 1968 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 && 1969 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE) 1970 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU; 1971 1972 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && 1973 hw->aq.api_min_ver >= 7) { 1974 __le32 tmp; 1975 1976 i40e_memcpy(&tmp, resp->link_type, sizeof(tmp), 1977 I40E_NONDMA_TO_NONDMA); 1978 hw->phy.phy_types = LE32_TO_CPU(tmp); 1979 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32); 1980 } 1981 1982 /* save link status information */ 1983 if (link) 1984 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info), 1985 I40E_NONDMA_TO_NONDMA); 1986 1987 /* flag cleared so helper functions don't call AQ again */ 1988 hw->phy.get_link_info = FALSE; 1989 1990 aq_get_link_info_exit: 1991 return status; 1992 } 1993 1994 /** 1995 * i40e_aq_set_phy_int_mask 1996 * @hw: pointer to the hw struct 1997 * @mask: interrupt mask to be set 1998 * @cmd_details: pointer to command details structure or NULL 1999 * 2000 * Set link interrupt mask. 2001 **/ 2002 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw, 2003 u16 mask, 2004 struct i40e_asq_cmd_details *cmd_details) 2005 { 2006 struct i40e_aq_desc desc; 2007 struct i40e_aqc_set_phy_int_mask *cmd = 2008 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw; 2009 enum i40e_status_code status; 2010 2011 i40e_fill_default_direct_cmd_desc(&desc, 2012 i40e_aqc_opc_set_phy_int_mask); 2013 2014 cmd->event_mask = CPU_TO_LE16(mask); 2015 2016 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2017 2018 return status; 2019 } 2020 2021 /** 2022 * i40e_aq_get_local_advt_reg 2023 * @hw: pointer to the hw struct 2024 * @advt_reg: local AN advertisement register value 2025 * @cmd_details: pointer to command details structure or NULL 2026 * 2027 * Get the Local AN advertisement register value. 2028 **/ 2029 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw, 2030 u64 *advt_reg, 2031 struct i40e_asq_cmd_details *cmd_details) 2032 { 2033 struct i40e_aq_desc desc; 2034 struct i40e_aqc_an_advt_reg *resp = 2035 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 2036 enum i40e_status_code status; 2037 2038 i40e_fill_default_direct_cmd_desc(&desc, 2039 i40e_aqc_opc_get_local_advt_reg); 2040 2041 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2042 2043 if (status != I40E_SUCCESS) 2044 goto aq_get_local_advt_reg_exit; 2045 2046 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32; 2047 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0); 2048 2049 aq_get_local_advt_reg_exit: 2050 return status; 2051 } 2052 2053 /** 2054 * i40e_aq_set_local_advt_reg 2055 * @hw: pointer to the hw struct 2056 * @advt_reg: local AN advertisement register value 2057 * @cmd_details: pointer to command details structure or NULL 2058 * 2059 * Get the Local AN advertisement register value. 2060 **/ 2061 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw, 2062 u64 advt_reg, 2063 struct i40e_asq_cmd_details *cmd_details) 2064 { 2065 struct i40e_aq_desc desc; 2066 struct i40e_aqc_an_advt_reg *cmd = 2067 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 2068 enum i40e_status_code status; 2069 2070 i40e_fill_default_direct_cmd_desc(&desc, 2071 i40e_aqc_opc_get_local_advt_reg); 2072 2073 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg)); 2074 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg)); 2075 2076 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2077 2078 return status; 2079 } 2080 2081 /** 2082 * i40e_aq_get_partner_advt 2083 * @hw: pointer to the hw struct 2084 * @advt_reg: AN partner advertisement register value 2085 * @cmd_details: pointer to command details structure or NULL 2086 * 2087 * Get the link partner AN advertisement register value. 2088 **/ 2089 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw, 2090 u64 *advt_reg, 2091 struct i40e_asq_cmd_details *cmd_details) 2092 { 2093 struct i40e_aq_desc desc; 2094 struct i40e_aqc_an_advt_reg *resp = 2095 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 2096 enum i40e_status_code status; 2097 2098 i40e_fill_default_direct_cmd_desc(&desc, 2099 i40e_aqc_opc_get_partner_advt); 2100 2101 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2102 2103 if (status != I40E_SUCCESS) 2104 goto aq_get_partner_advt_exit; 2105 2106 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32; 2107 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0); 2108 2109 aq_get_partner_advt_exit: 2110 return status; 2111 } 2112 2113 /** 2114 * i40e_aq_set_lb_modes 2115 * @hw: pointer to the hw struct 2116 * @lb_modes: loopback mode to be set 2117 * @cmd_details: pointer to command details structure or NULL 2118 * 2119 * Sets loopback modes. 2120 **/ 2121 enum i40e_status_code 2122 i40e_aq_set_lb_modes(struct i40e_hw *hw, u8 lb_level, u8 lb_type, u8 speed, 2123 struct i40e_asq_cmd_details *cmd_details) 2124 { 2125 struct i40e_aq_desc desc; 2126 struct i40e_aqc_set_lb_mode *cmd = 2127 (struct i40e_aqc_set_lb_mode *)&desc.params.raw; 2128 enum i40e_status_code status; 2129 2130 i40e_fill_default_direct_cmd_desc(&desc, 2131 i40e_aqc_opc_set_lb_modes); 2132 2133 cmd->lb_level = lb_level; 2134 cmd->lb_type = lb_type; 2135 cmd->speed = speed; 2136 if (speed) 2137 cmd->force_speed = 1; 2138 2139 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2140 2141 return status; 2142 } 2143 2144 /** 2145 * i40e_aq_set_phy_debug 2146 * @hw: pointer to the hw struct 2147 * @cmd_flags: debug command flags 2148 * @cmd_details: pointer to command details structure or NULL 2149 * 2150 * Reset the external PHY. 2151 **/ 2152 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags, 2153 struct i40e_asq_cmd_details *cmd_details) 2154 { 2155 struct i40e_aq_desc desc; 2156 struct i40e_aqc_set_phy_debug *cmd = 2157 (struct i40e_aqc_set_phy_debug *)&desc.params.raw; 2158 enum i40e_status_code status; 2159 2160 i40e_fill_default_direct_cmd_desc(&desc, 2161 i40e_aqc_opc_set_phy_debug); 2162 2163 cmd->command_flags = cmd_flags; 2164 2165 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2166 2167 return status; 2168 } 2169 2170 /** 2171 * i40e_aq_add_vsi 2172 * @hw: pointer to the hw struct 2173 * @vsi_ctx: pointer to a vsi context struct 2174 * @cmd_details: pointer to command details structure or NULL 2175 * 2176 * Add a VSI context to the hardware. 2177 **/ 2178 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw, 2179 struct i40e_vsi_context *vsi_ctx, 2180 struct i40e_asq_cmd_details *cmd_details) 2181 { 2182 struct i40e_aq_desc desc; 2183 struct i40e_aqc_add_get_update_vsi *cmd = 2184 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2185 struct i40e_aqc_add_get_update_vsi_completion *resp = 2186 (struct i40e_aqc_add_get_update_vsi_completion *) 2187 &desc.params.raw; 2188 enum i40e_status_code status; 2189 2190 i40e_fill_default_direct_cmd_desc(&desc, 2191 i40e_aqc_opc_add_vsi); 2192 2193 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid); 2194 cmd->connection_type = vsi_ctx->connection_type; 2195 cmd->vf_id = vsi_ctx->vf_num; 2196 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags); 2197 2198 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2199 2200 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2201 sizeof(vsi_ctx->info), cmd_details); 2202 2203 if (status != I40E_SUCCESS) 2204 goto aq_add_vsi_exit; 2205 2206 vsi_ctx->seid = LE16_TO_CPU(resp->seid); 2207 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number); 2208 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 2209 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 2210 2211 aq_add_vsi_exit: 2212 return status; 2213 } 2214 2215 /** 2216 * i40e_aq_set_default_vsi 2217 * @hw: pointer to the hw struct 2218 * @seid: vsi number 2219 * @cmd_details: pointer to command details structure or NULL 2220 **/ 2221 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw, 2222 u16 seid, 2223 struct i40e_asq_cmd_details *cmd_details) 2224 { 2225 struct i40e_aq_desc desc; 2226 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2227 (struct i40e_aqc_set_vsi_promiscuous_modes *) 2228 &desc.params.raw; 2229 enum i40e_status_code status; 2230 2231 i40e_fill_default_direct_cmd_desc(&desc, 2232 i40e_aqc_opc_set_vsi_promiscuous_modes); 2233 2234 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 2235 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 2236 cmd->seid = CPU_TO_LE16(seid); 2237 2238 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2239 2240 return status; 2241 } 2242 2243 /** 2244 * i40e_aq_clear_default_vsi 2245 * @hw: pointer to the hw struct 2246 * @seid: vsi number 2247 * @cmd_details: pointer to command details structure or NULL 2248 **/ 2249 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw, 2250 u16 seid, 2251 struct i40e_asq_cmd_details *cmd_details) 2252 { 2253 struct i40e_aq_desc desc; 2254 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2255 (struct i40e_aqc_set_vsi_promiscuous_modes *) 2256 &desc.params.raw; 2257 enum i40e_status_code status; 2258 2259 i40e_fill_default_direct_cmd_desc(&desc, 2260 i40e_aqc_opc_set_vsi_promiscuous_modes); 2261 2262 cmd->promiscuous_flags = CPU_TO_LE16(0); 2263 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 2264 cmd->seid = CPU_TO_LE16(seid); 2265 2266 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2267 2268 return status; 2269 } 2270 2271 /** 2272 * i40e_aq_set_vsi_unicast_promiscuous 2273 * @hw: pointer to the hw struct 2274 * @seid: vsi number 2275 * @set: set unicast promiscuous enable/disable 2276 * @cmd_details: pointer to command details structure or NULL 2277 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc 2278 **/ 2279 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw, 2280 u16 seid, bool set, 2281 struct i40e_asq_cmd_details *cmd_details, 2282 bool rx_only_promisc) 2283 { 2284 struct i40e_aq_desc desc; 2285 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2286 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2287 enum i40e_status_code status; 2288 u16 flags = 0; 2289 2290 i40e_fill_default_direct_cmd_desc(&desc, 2291 i40e_aqc_opc_set_vsi_promiscuous_modes); 2292 2293 if (set) { 2294 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2295 if (rx_only_promisc && 2296 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) || 2297 (hw->aq.api_maj_ver > 1))) 2298 flags |= I40E_AQC_SET_VSI_PROMISC_TX; 2299 } 2300 2301 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2302 2303 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2304 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) || 2305 (hw->aq.api_maj_ver > 1)) 2306 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX); 2307 2308 cmd->seid = CPU_TO_LE16(seid); 2309 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2310 2311 return status; 2312 } 2313 2314 /** 2315 * i40e_aq_set_vsi_multicast_promiscuous 2316 * @hw: pointer to the hw struct 2317 * @seid: vsi number 2318 * @set: set multicast promiscuous enable/disable 2319 * @cmd_details: pointer to command details structure or NULL 2320 **/ 2321 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw, 2322 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details) 2323 { 2324 struct i40e_aq_desc desc; 2325 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2326 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2327 enum i40e_status_code status; 2328 u16 flags = 0; 2329 2330 i40e_fill_default_direct_cmd_desc(&desc, 2331 i40e_aqc_opc_set_vsi_promiscuous_modes); 2332 2333 if (set) 2334 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2335 2336 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2337 2338 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2339 2340 cmd->seid = CPU_TO_LE16(seid); 2341 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2342 2343 return status; 2344 } 2345 2346 /** 2347 * i40e_aq_set_vsi_full_promiscuous 2348 * @hw: pointer to the hw struct 2349 * @seid: VSI number 2350 * @set: set promiscuous enable/disable 2351 * @cmd_details: pointer to command details structure or NULL 2352 **/ 2353 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw, 2354 u16 seid, bool set, 2355 struct i40e_asq_cmd_details *cmd_details) 2356 { 2357 struct i40e_aq_desc desc; 2358 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2359 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2360 enum i40e_status_code status; 2361 u16 flags = 0; 2362 2363 i40e_fill_default_direct_cmd_desc(&desc, 2364 i40e_aqc_opc_set_vsi_promiscuous_modes); 2365 2366 if (set) 2367 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST | 2368 I40E_AQC_SET_VSI_PROMISC_MULTICAST | 2369 I40E_AQC_SET_VSI_PROMISC_BROADCAST; 2370 2371 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2372 2373 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST | 2374 I40E_AQC_SET_VSI_PROMISC_MULTICAST | 2375 I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2376 2377 cmd->seid = CPU_TO_LE16(seid); 2378 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2379 2380 return status; 2381 } 2382 2383 /** 2384 * i40e_aq_set_vsi_mc_promisc_on_vlan 2385 * @hw: pointer to the hw struct 2386 * @seid: vsi number 2387 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2388 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag 2389 * @cmd_details: pointer to command details structure or NULL 2390 **/ 2391 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw, 2392 u16 seid, bool enable, u16 vid, 2393 struct i40e_asq_cmd_details *cmd_details) 2394 { 2395 struct i40e_aq_desc desc; 2396 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2397 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2398 enum i40e_status_code status; 2399 u16 flags = 0; 2400 2401 i40e_fill_default_direct_cmd_desc(&desc, 2402 i40e_aqc_opc_set_vsi_promiscuous_modes); 2403 2404 if (enable) 2405 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2406 2407 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2408 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2409 cmd->seid = CPU_TO_LE16(seid); 2410 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2411 2412 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2413 2414 return status; 2415 } 2416 2417 /** 2418 * i40e_aq_set_vsi_uc_promisc_on_vlan 2419 * @hw: pointer to the hw struct 2420 * @seid: vsi number 2421 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2422 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag 2423 * @cmd_details: pointer to command details structure or NULL 2424 **/ 2425 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw, 2426 u16 seid, bool enable, u16 vid, 2427 struct i40e_asq_cmd_details *cmd_details) 2428 { 2429 struct i40e_aq_desc desc; 2430 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2431 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2432 enum i40e_status_code status; 2433 u16 flags = 0; 2434 2435 i40e_fill_default_direct_cmd_desc(&desc, 2436 i40e_aqc_opc_set_vsi_promiscuous_modes); 2437 2438 if (enable) 2439 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2440 2441 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2442 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2443 cmd->seid = CPU_TO_LE16(seid); 2444 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2445 2446 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2447 2448 return status; 2449 } 2450 2451 /** 2452 * i40e_aq_set_vsi_bc_promisc_on_vlan 2453 * @hw: pointer to the hw struct 2454 * @seid: vsi number 2455 * @enable: set broadcast promiscuous enable/disable for a given VLAN 2456 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag 2457 * @cmd_details: pointer to command details structure or NULL 2458 **/ 2459 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw, 2460 u16 seid, bool enable, u16 vid, 2461 struct i40e_asq_cmd_details *cmd_details) 2462 { 2463 struct i40e_aq_desc desc; 2464 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2465 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2466 enum i40e_status_code status; 2467 u16 flags = 0; 2468 2469 i40e_fill_default_direct_cmd_desc(&desc, 2470 i40e_aqc_opc_set_vsi_promiscuous_modes); 2471 2472 if (enable) 2473 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST; 2474 2475 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2476 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2477 cmd->seid = CPU_TO_LE16(seid); 2478 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2479 2480 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2481 2482 return status; 2483 } 2484 2485 /** 2486 * i40e_aq_set_vsi_broadcast 2487 * @hw: pointer to the hw struct 2488 * @seid: vsi number 2489 * @set_filter: TRUE to set filter, FALSE to clear filter 2490 * @cmd_details: pointer to command details structure or NULL 2491 * 2492 * Set or clear the broadcast promiscuous flag (filter) for a given VSI. 2493 **/ 2494 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw, 2495 u16 seid, bool set_filter, 2496 struct i40e_asq_cmd_details *cmd_details) 2497 { 2498 struct i40e_aq_desc desc; 2499 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2500 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2501 enum i40e_status_code status; 2502 2503 i40e_fill_default_direct_cmd_desc(&desc, 2504 i40e_aqc_opc_set_vsi_promiscuous_modes); 2505 2506 if (set_filter) 2507 cmd->promiscuous_flags 2508 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2509 else 2510 cmd->promiscuous_flags 2511 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2512 2513 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2514 cmd->seid = CPU_TO_LE16(seid); 2515 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2516 2517 return status; 2518 } 2519 2520 /** 2521 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting 2522 * @hw: pointer to the hw struct 2523 * @seid: vsi number 2524 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2525 * @cmd_details: pointer to command details structure or NULL 2526 **/ 2527 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw, 2528 u16 seid, bool enable, 2529 struct i40e_asq_cmd_details *cmd_details) 2530 { 2531 struct i40e_aq_desc desc; 2532 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2533 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2534 enum i40e_status_code status; 2535 u16 flags = 0; 2536 2537 i40e_fill_default_direct_cmd_desc(&desc, 2538 i40e_aqc_opc_set_vsi_promiscuous_modes); 2539 if (enable) 2540 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN; 2541 2542 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2543 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN); 2544 cmd->seid = CPU_TO_LE16(seid); 2545 2546 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2547 2548 return status; 2549 } 2550 2551 /** 2552 * i40e_get_vsi_params - get VSI configuration info 2553 * @hw: pointer to the hw struct 2554 * @vsi_ctx: pointer to a vsi context struct 2555 * @cmd_details: pointer to command details structure or NULL 2556 **/ 2557 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw, 2558 struct i40e_vsi_context *vsi_ctx, 2559 struct i40e_asq_cmd_details *cmd_details) 2560 { 2561 struct i40e_aq_desc desc; 2562 struct i40e_aqc_add_get_update_vsi *cmd = 2563 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2564 struct i40e_aqc_add_get_update_vsi_completion *resp = 2565 (struct i40e_aqc_add_get_update_vsi_completion *) 2566 &desc.params.raw; 2567 enum i40e_status_code status; 2568 2569 i40e_fill_default_direct_cmd_desc(&desc, 2570 i40e_aqc_opc_get_vsi_parameters); 2571 2572 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid); 2573 2574 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 2575 2576 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2577 sizeof(vsi_ctx->info), NULL); 2578 2579 if (status != I40E_SUCCESS) 2580 goto aq_get_vsi_params_exit; 2581 2582 vsi_ctx->seid = LE16_TO_CPU(resp->seid); 2583 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number); 2584 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 2585 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 2586 2587 aq_get_vsi_params_exit: 2588 return status; 2589 } 2590 2591 /** 2592 * i40e_aq_update_vsi_params 2593 * @hw: pointer to the hw struct 2594 * @vsi_ctx: pointer to a vsi context struct 2595 * @cmd_details: pointer to command details structure or NULL 2596 * 2597 * Update a VSI context. 2598 **/ 2599 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw, 2600 struct i40e_vsi_context *vsi_ctx, 2601 struct i40e_asq_cmd_details *cmd_details) 2602 { 2603 struct i40e_aq_desc desc; 2604 struct i40e_aqc_add_get_update_vsi *cmd = 2605 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2606 struct i40e_aqc_add_get_update_vsi_completion *resp = 2607 (struct i40e_aqc_add_get_update_vsi_completion *) 2608 &desc.params.raw; 2609 enum i40e_status_code status; 2610 2611 i40e_fill_default_direct_cmd_desc(&desc, 2612 i40e_aqc_opc_update_vsi_parameters); 2613 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid); 2614 2615 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2616 2617 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2618 sizeof(vsi_ctx->info), cmd_details); 2619 2620 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 2621 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 2622 2623 return status; 2624 } 2625 2626 /** 2627 * i40e_aq_get_switch_config 2628 * @hw: pointer to the hardware structure 2629 * @buf: pointer to the result buffer 2630 * @buf_size: length of input buffer 2631 * @start_seid: seid to start for the report, 0 == beginning 2632 * @cmd_details: pointer to command details structure or NULL 2633 * 2634 * Fill the buf with switch configuration returned from AdminQ command 2635 **/ 2636 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw, 2637 struct i40e_aqc_get_switch_config_resp *buf, 2638 u16 buf_size, u16 *start_seid, 2639 struct i40e_asq_cmd_details *cmd_details) 2640 { 2641 struct i40e_aq_desc desc; 2642 struct i40e_aqc_switch_seid *scfg = 2643 (struct i40e_aqc_switch_seid *)&desc.params.raw; 2644 enum i40e_status_code status; 2645 2646 i40e_fill_default_direct_cmd_desc(&desc, 2647 i40e_aqc_opc_get_switch_config); 2648 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 2649 if (buf_size > I40E_AQ_LARGE_BUF) 2650 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2651 scfg->seid = CPU_TO_LE16(*start_seid); 2652 2653 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details); 2654 *start_seid = LE16_TO_CPU(scfg->seid); 2655 2656 return status; 2657 } 2658 2659 /** 2660 * i40e_aq_set_switch_config 2661 * @hw: pointer to the hardware structure 2662 * @flags: bit flag values to set 2663 * @mode: cloud filter mode 2664 * @valid_flags: which bit flags to set 2665 * @cmd_details: pointer to command details structure or NULL 2666 * 2667 * Set switch configuration bits 2668 **/ 2669 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw, 2670 u16 flags, u16 valid_flags, u8 mode, 2671 struct i40e_asq_cmd_details *cmd_details) 2672 { 2673 struct i40e_aq_desc desc; 2674 struct i40e_aqc_set_switch_config *scfg = 2675 (struct i40e_aqc_set_switch_config *)&desc.params.raw; 2676 enum i40e_status_code status; 2677 2678 i40e_fill_default_direct_cmd_desc(&desc, 2679 i40e_aqc_opc_set_switch_config); 2680 scfg->flags = CPU_TO_LE16(flags); 2681 scfg->valid_flags = CPU_TO_LE16(valid_flags); 2682 scfg->mode = mode; 2683 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) { 2684 scfg->switch_tag = CPU_TO_LE16(hw->switch_tag); 2685 scfg->first_tag = CPU_TO_LE16(hw->first_tag); 2686 scfg->second_tag = CPU_TO_LE16(hw->second_tag); 2687 } 2688 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2689 2690 return status; 2691 } 2692 2693 /** 2694 * i40e_aq_get_firmware_version 2695 * @hw: pointer to the hw struct 2696 * @fw_major_version: firmware major version 2697 * @fw_minor_version: firmware minor version 2698 * @fw_build: firmware build number 2699 * @api_major_version: major queue version 2700 * @api_minor_version: minor queue version 2701 * @cmd_details: pointer to command details structure or NULL 2702 * 2703 * Get the firmware version from the admin queue commands 2704 **/ 2705 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw, 2706 u16 *fw_major_version, u16 *fw_minor_version, 2707 u32 *fw_build, 2708 u16 *api_major_version, u16 *api_minor_version, 2709 struct i40e_asq_cmd_details *cmd_details) 2710 { 2711 struct i40e_aq_desc desc; 2712 struct i40e_aqc_get_version *resp = 2713 (struct i40e_aqc_get_version *)&desc.params.raw; 2714 enum i40e_status_code status; 2715 2716 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version); 2717 2718 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2719 2720 if (status == I40E_SUCCESS) { 2721 if (fw_major_version != NULL) 2722 *fw_major_version = LE16_TO_CPU(resp->fw_major); 2723 if (fw_minor_version != NULL) 2724 *fw_minor_version = LE16_TO_CPU(resp->fw_minor); 2725 if (fw_build != NULL) 2726 *fw_build = LE32_TO_CPU(resp->fw_build); 2727 if (api_major_version != NULL) 2728 *api_major_version = LE16_TO_CPU(resp->api_major); 2729 if (api_minor_version != NULL) 2730 *api_minor_version = LE16_TO_CPU(resp->api_minor); 2731 2732 /* A workaround to fix the API version in SW */ 2733 if (api_major_version && api_minor_version && 2734 fw_major_version && fw_minor_version && 2735 ((*api_major_version == 1) && (*api_minor_version == 1)) && 2736 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) || 2737 (*fw_major_version > 4))) 2738 *api_minor_version = 2; 2739 } 2740 2741 return status; 2742 } 2743 2744 /** 2745 * i40e_aq_send_driver_version 2746 * @hw: pointer to the hw struct 2747 * @dv: driver's major, minor version 2748 * @cmd_details: pointer to command details structure or NULL 2749 * 2750 * Send the driver version to the firmware 2751 **/ 2752 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw, 2753 struct i40e_driver_version *dv, 2754 struct i40e_asq_cmd_details *cmd_details) 2755 { 2756 struct i40e_aq_desc desc; 2757 struct i40e_aqc_driver_version *cmd = 2758 (struct i40e_aqc_driver_version *)&desc.params.raw; 2759 enum i40e_status_code status; 2760 u16 len; 2761 2762 if (dv == NULL) 2763 return I40E_ERR_PARAM; 2764 2765 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version); 2766 2767 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 2768 cmd->driver_major_ver = dv->major_version; 2769 cmd->driver_minor_ver = dv->minor_version; 2770 cmd->driver_build_ver = dv->build_version; 2771 cmd->driver_subbuild_ver = dv->subbuild_version; 2772 2773 len = 0; 2774 while (len < sizeof(dv->driver_string) && 2775 (dv->driver_string[len] < 0x80) && 2776 dv->driver_string[len]) 2777 len++; 2778 status = i40e_asq_send_command(hw, &desc, dv->driver_string, 2779 len, cmd_details); 2780 2781 return status; 2782 } 2783 2784 /** 2785 * i40e_get_link_status - get status of the HW network link 2786 * @hw: pointer to the hw struct 2787 * @link_up: pointer to bool (TRUE/FALSE = linkup/linkdown) 2788 * 2789 * Variable link_up TRUE if link is up, FALSE if link is down. 2790 * The variable link_up is invalid if returned value of status != I40E_SUCCESS 2791 * 2792 * Side effect: LinkStatusEvent reporting becomes enabled 2793 **/ 2794 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up) 2795 { 2796 enum i40e_status_code status = I40E_SUCCESS; 2797 2798 if (hw->phy.get_link_info) { 2799 status = i40e_update_link_info(hw); 2800 2801 if (status != I40E_SUCCESS) 2802 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n", 2803 status); 2804 } 2805 2806 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP; 2807 2808 return status; 2809 } 2810 2811 /** 2812 * i40e_updatelink_status - update status of the HW network link 2813 * @hw: pointer to the hw struct 2814 **/ 2815 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw) 2816 { 2817 struct i40e_aq_get_phy_abilities_resp abilities; 2818 enum i40e_status_code status = I40E_SUCCESS; 2819 2820 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL); 2821 if (status) 2822 return status; 2823 2824 /* extra checking needed to ensure link info to user is timely */ 2825 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) && 2826 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) || 2827 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) { 2828 status = i40e_aq_get_phy_capabilities(hw, FALSE, false, 2829 &abilities, NULL); 2830 if (status) 2831 return status; 2832 2833 hw->phy.link_info.req_fec_info = 2834 abilities.fec_cfg_curr_mod_ext_info & 2835 (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS); 2836 2837 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type, 2838 sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA); 2839 } 2840 return status; 2841 } 2842 2843 2844 /** 2845 * i40e_get_link_speed 2846 * @hw: pointer to the hw struct 2847 * 2848 * Returns the link speed of the adapter. 2849 **/ 2850 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw) 2851 { 2852 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN; 2853 enum i40e_status_code status = I40E_SUCCESS; 2854 2855 if (hw->phy.get_link_info) { 2856 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL); 2857 2858 if (status != I40E_SUCCESS) 2859 goto i40e_link_speed_exit; 2860 } 2861 2862 speed = hw->phy.link_info.link_speed; 2863 2864 i40e_link_speed_exit: 2865 return speed; 2866 } 2867 2868 /** 2869 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC 2870 * @hw: pointer to the hw struct 2871 * @uplink_seid: the MAC or other gizmo SEID 2872 * @downlink_seid: the VSI SEID 2873 * @enabled_tc: bitmap of TCs to be enabled 2874 * @default_port: TRUE for default port VSI, FALSE for control port 2875 * @veb_seid: pointer to where to put the resulting VEB SEID 2876 * @enable_stats: TRUE to turn on VEB stats 2877 * @cmd_details: pointer to command details structure or NULL 2878 * 2879 * This asks the FW to add a VEB between the uplink and downlink 2880 * elements. If the uplink SEID is 0, this will be a floating VEB. 2881 **/ 2882 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid, 2883 u16 downlink_seid, u8 enabled_tc, 2884 bool default_port, u16 *veb_seid, 2885 bool enable_stats, 2886 struct i40e_asq_cmd_details *cmd_details) 2887 { 2888 struct i40e_aq_desc desc; 2889 struct i40e_aqc_add_veb *cmd = 2890 (struct i40e_aqc_add_veb *)&desc.params.raw; 2891 struct i40e_aqc_add_veb_completion *resp = 2892 (struct i40e_aqc_add_veb_completion *)&desc.params.raw; 2893 enum i40e_status_code status; 2894 u16 veb_flags = 0; 2895 2896 /* SEIDs need to either both be set or both be 0 for floating VEB */ 2897 if (!!uplink_seid != !!downlink_seid) 2898 return I40E_ERR_PARAM; 2899 2900 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb); 2901 2902 cmd->uplink_seid = CPU_TO_LE16(uplink_seid); 2903 cmd->downlink_seid = CPU_TO_LE16(downlink_seid); 2904 cmd->enable_tcs = enabled_tc; 2905 if (!uplink_seid) 2906 veb_flags |= I40E_AQC_ADD_VEB_FLOATING; 2907 if (default_port) 2908 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT; 2909 else 2910 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA; 2911 2912 /* reverse logic here: set the bitflag to disable the stats */ 2913 if (!enable_stats) 2914 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS; 2915 2916 cmd->veb_flags = CPU_TO_LE16(veb_flags); 2917 2918 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2919 2920 if (!status && veb_seid) 2921 *veb_seid = LE16_TO_CPU(resp->veb_seid); 2922 2923 return status; 2924 } 2925 2926 /** 2927 * i40e_aq_get_veb_parameters - Retrieve VEB parameters 2928 * @hw: pointer to the hw struct 2929 * @veb_seid: the SEID of the VEB to query 2930 * @switch_id: the uplink switch id 2931 * @floating: set to TRUE if the VEB is floating 2932 * @statistic_index: index of the stats counter block for this VEB 2933 * @vebs_used: number of VEB's used by function 2934 * @vebs_free: total VEB's not reserved by any function 2935 * @cmd_details: pointer to command details structure or NULL 2936 * 2937 * This retrieves the parameters for a particular VEB, specified by 2938 * uplink_seid, and returns them to the caller. 2939 **/ 2940 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw, 2941 u16 veb_seid, u16 *switch_id, 2942 bool *floating, u16 *statistic_index, 2943 u16 *vebs_used, u16 *vebs_free, 2944 struct i40e_asq_cmd_details *cmd_details) 2945 { 2946 struct i40e_aq_desc desc; 2947 struct i40e_aqc_get_veb_parameters_completion *cmd_resp = 2948 (struct i40e_aqc_get_veb_parameters_completion *) 2949 &desc.params.raw; 2950 enum i40e_status_code status; 2951 2952 if (veb_seid == 0) 2953 return I40E_ERR_PARAM; 2954 2955 i40e_fill_default_direct_cmd_desc(&desc, 2956 i40e_aqc_opc_get_veb_parameters); 2957 cmd_resp->seid = CPU_TO_LE16(veb_seid); 2958 2959 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2960 if (status) 2961 goto get_veb_exit; 2962 2963 if (switch_id) 2964 *switch_id = LE16_TO_CPU(cmd_resp->switch_id); 2965 if (statistic_index) 2966 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index); 2967 if (vebs_used) 2968 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used); 2969 if (vebs_free) 2970 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free); 2971 if (floating) { 2972 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags); 2973 2974 if (flags & I40E_AQC_ADD_VEB_FLOATING) 2975 *floating = TRUE; 2976 else 2977 *floating = FALSE; 2978 } 2979 2980 get_veb_exit: 2981 return status; 2982 } 2983 2984 /** 2985 * i40e_aq_add_macvlan 2986 * @hw: pointer to the hw struct 2987 * @seid: VSI for the mac address 2988 * @mv_list: list of macvlans to be added 2989 * @count: length of the list 2990 * @cmd_details: pointer to command details structure or NULL 2991 * 2992 * Add MAC/VLAN addresses to the HW filtering 2993 **/ 2994 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid, 2995 struct i40e_aqc_add_macvlan_element_data *mv_list, 2996 u16 count, struct i40e_asq_cmd_details *cmd_details) 2997 { 2998 struct i40e_aq_desc desc; 2999 struct i40e_aqc_macvlan *cmd = 3000 (struct i40e_aqc_macvlan *)&desc.params.raw; 3001 enum i40e_status_code status; 3002 u16 buf_size; 3003 int i; 3004 3005 if (count == 0 || !mv_list || !hw) 3006 return I40E_ERR_PARAM; 3007 3008 buf_size = count * sizeof(*mv_list); 3009 3010 /* prep the rest of the request */ 3011 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan); 3012 cmd->num_addresses = CPU_TO_LE16(count); 3013 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 3014 cmd->seid[1] = 0; 3015 cmd->seid[2] = 0; 3016 3017 for (i = 0; i < count; i++) 3018 if (I40E_IS_MULTICAST(mv_list[i].mac_addr)) 3019 mv_list[i].flags |= 3020 CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC); 3021 3022 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3023 if (buf_size > I40E_AQ_LARGE_BUF) 3024 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3025 3026 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 3027 cmd_details); 3028 3029 return status; 3030 } 3031 3032 /** 3033 * i40e_aq_remove_macvlan 3034 * @hw: pointer to the hw struct 3035 * @seid: VSI for the mac address 3036 * @mv_list: list of macvlans to be removed 3037 * @count: length of the list 3038 * @cmd_details: pointer to command details structure or NULL 3039 * 3040 * Remove MAC/VLAN addresses from the HW filtering 3041 **/ 3042 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid, 3043 struct i40e_aqc_remove_macvlan_element_data *mv_list, 3044 u16 count, struct i40e_asq_cmd_details *cmd_details) 3045 { 3046 struct i40e_aq_desc desc; 3047 struct i40e_aqc_macvlan *cmd = 3048 (struct i40e_aqc_macvlan *)&desc.params.raw; 3049 enum i40e_status_code status; 3050 u16 buf_size; 3051 3052 if (count == 0 || !mv_list || !hw) 3053 return I40E_ERR_PARAM; 3054 3055 buf_size = count * sizeof(*mv_list); 3056 3057 /* prep the rest of the request */ 3058 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 3059 cmd->num_addresses = CPU_TO_LE16(count); 3060 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 3061 cmd->seid[1] = 0; 3062 cmd->seid[2] = 0; 3063 3064 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3065 if (buf_size > I40E_AQ_LARGE_BUF) 3066 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3067 3068 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 3069 cmd_details); 3070 3071 return status; 3072 } 3073 3074 /** 3075 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule 3076 * @hw: pointer to the hw struct 3077 * @opcode: AQ opcode for add or delete mirror rule 3078 * @sw_seid: Switch SEID (to which rule refers) 3079 * @rule_type: Rule Type (ingress/egress/VLAN) 3080 * @id: Destination VSI SEID or Rule ID 3081 * @count: length of the list 3082 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 3083 * @cmd_details: pointer to command details structure or NULL 3084 * @rule_id: Rule ID returned from FW 3085 * @rules_used: Number of rules used in internal switch 3086 * @rules_free: Number of rules free in internal switch 3087 * 3088 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for 3089 * VEBs/VEPA elements only 3090 **/ 3091 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw, 3092 u16 opcode, u16 sw_seid, u16 rule_type, u16 id, 3093 u16 count, __le16 *mr_list, 3094 struct i40e_asq_cmd_details *cmd_details, 3095 u16 *rule_id, u16 *rules_used, u16 *rules_free) 3096 { 3097 struct i40e_aq_desc desc; 3098 struct i40e_aqc_add_delete_mirror_rule *cmd = 3099 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw; 3100 struct i40e_aqc_add_delete_mirror_rule_completion *resp = 3101 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw; 3102 enum i40e_status_code status; 3103 u16 buf_size; 3104 3105 buf_size = count * sizeof(*mr_list); 3106 3107 /* prep the rest of the request */ 3108 i40e_fill_default_direct_cmd_desc(&desc, opcode); 3109 cmd->seid = CPU_TO_LE16(sw_seid); 3110 cmd->rule_type = CPU_TO_LE16(rule_type & 3111 I40E_AQC_MIRROR_RULE_TYPE_MASK); 3112 cmd->num_entries = CPU_TO_LE16(count); 3113 /* Dest VSI for add, rule_id for delete */ 3114 cmd->destination = CPU_TO_LE16(id); 3115 if (mr_list) { 3116 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | 3117 I40E_AQ_FLAG_RD)); 3118 if (buf_size > I40E_AQ_LARGE_BUF) 3119 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3120 } 3121 3122 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size, 3123 cmd_details); 3124 if (status == I40E_SUCCESS || 3125 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) { 3126 if (rule_id) 3127 *rule_id = LE16_TO_CPU(resp->rule_id); 3128 if (rules_used) 3129 *rules_used = LE16_TO_CPU(resp->mirror_rules_used); 3130 if (rules_free) 3131 *rules_free = LE16_TO_CPU(resp->mirror_rules_free); 3132 } 3133 return status; 3134 } 3135 3136 /** 3137 * i40e_aq_add_mirrorrule - add a mirror rule 3138 * @hw: pointer to the hw struct 3139 * @sw_seid: Switch SEID (to which rule refers) 3140 * @rule_type: Rule Type (ingress/egress/VLAN) 3141 * @dest_vsi: SEID of VSI to which packets will be mirrored 3142 * @count: length of the list 3143 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 3144 * @cmd_details: pointer to command details structure or NULL 3145 * @rule_id: Rule ID returned from FW 3146 * @rules_used: Number of rules used in internal switch 3147 * @rules_free: Number of rules free in internal switch 3148 * 3149 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only 3150 **/ 3151 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 3152 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list, 3153 struct i40e_asq_cmd_details *cmd_details, 3154 u16 *rule_id, u16 *rules_used, u16 *rules_free) 3155 { 3156 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS || 3157 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) { 3158 if (count == 0 || !mr_list) 3159 return I40E_ERR_PARAM; 3160 } 3161 3162 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid, 3163 rule_type, dest_vsi, count, mr_list, 3164 cmd_details, rule_id, rules_used, rules_free); 3165 } 3166 3167 /** 3168 * i40e_aq_delete_mirrorrule - delete a mirror rule 3169 * @hw: pointer to the hw struct 3170 * @sw_seid: Switch SEID (to which rule refers) 3171 * @rule_type: Rule Type (ingress/egress/VLAN) 3172 * @count: length of the list 3173 * @rule_id: Rule ID that is returned in the receive desc as part of 3174 * add_mirrorrule. 3175 * @mr_list: list of mirrored VLAN IDs to be removed 3176 * @cmd_details: pointer to command details structure or NULL 3177 * @rules_used: Number of rules used in internal switch 3178 * @rules_free: Number of rules free in internal switch 3179 * 3180 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only 3181 **/ 3182 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 3183 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list, 3184 struct i40e_asq_cmd_details *cmd_details, 3185 u16 *rules_used, u16 *rules_free) 3186 { 3187 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */ 3188 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) { 3189 /* count and mr_list shall be valid for rule_type INGRESS VLAN 3190 * mirroring. For other rule_type, count and rule_type should 3191 * not matter. 3192 */ 3193 if (count == 0 || !mr_list) 3194 return I40E_ERR_PARAM; 3195 } 3196 3197 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid, 3198 rule_type, rule_id, count, mr_list, 3199 cmd_details, NULL, rules_used, rules_free); 3200 } 3201 3202 /** 3203 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering 3204 * @hw: pointer to the hw struct 3205 * @seid: VSI for the vlan filters 3206 * @v_list: list of vlan filters to be added 3207 * @count: length of the list 3208 * @cmd_details: pointer to command details structure or NULL 3209 **/ 3210 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid, 3211 struct i40e_aqc_add_remove_vlan_element_data *v_list, 3212 u8 count, struct i40e_asq_cmd_details *cmd_details) 3213 { 3214 struct i40e_aq_desc desc; 3215 struct i40e_aqc_macvlan *cmd = 3216 (struct i40e_aqc_macvlan *)&desc.params.raw; 3217 enum i40e_status_code status; 3218 u16 buf_size; 3219 3220 if (count == 0 || !v_list || !hw) 3221 return I40E_ERR_PARAM; 3222 3223 buf_size = count * sizeof(*v_list); 3224 3225 /* prep the rest of the request */ 3226 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan); 3227 cmd->num_addresses = CPU_TO_LE16(count); 3228 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID); 3229 cmd->seid[1] = 0; 3230 cmd->seid[2] = 0; 3231 3232 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3233 if (buf_size > I40E_AQ_LARGE_BUF) 3234 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3235 3236 status = i40e_asq_send_command(hw, &desc, v_list, buf_size, 3237 cmd_details); 3238 3239 return status; 3240 } 3241 3242 /** 3243 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering 3244 * @hw: pointer to the hw struct 3245 * @seid: VSI for the vlan filters 3246 * @v_list: list of macvlans to be removed 3247 * @count: length of the list 3248 * @cmd_details: pointer to command details structure or NULL 3249 **/ 3250 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid, 3251 struct i40e_aqc_add_remove_vlan_element_data *v_list, 3252 u8 count, struct i40e_asq_cmd_details *cmd_details) 3253 { 3254 struct i40e_aq_desc desc; 3255 struct i40e_aqc_macvlan *cmd = 3256 (struct i40e_aqc_macvlan *)&desc.params.raw; 3257 enum i40e_status_code status; 3258 u16 buf_size; 3259 3260 if (count == 0 || !v_list || !hw) 3261 return I40E_ERR_PARAM; 3262 3263 buf_size = count * sizeof(*v_list); 3264 3265 /* prep the rest of the request */ 3266 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan); 3267 cmd->num_addresses = CPU_TO_LE16(count); 3268 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID); 3269 cmd->seid[1] = 0; 3270 cmd->seid[2] = 0; 3271 3272 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3273 if (buf_size > I40E_AQ_LARGE_BUF) 3274 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3275 3276 status = i40e_asq_send_command(hw, &desc, v_list, buf_size, 3277 cmd_details); 3278 3279 return status; 3280 } 3281 3282 /** 3283 * i40e_aq_send_msg_to_vf 3284 * @hw: pointer to the hardware structure 3285 * @vfid: vf id to send msg 3286 * @v_opcode: opcodes for VF-PF communication 3287 * @v_retval: return error code 3288 * @msg: pointer to the msg buffer 3289 * @msglen: msg length 3290 * @cmd_details: pointer to command details 3291 * 3292 * send msg to vf 3293 **/ 3294 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid, 3295 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen, 3296 struct i40e_asq_cmd_details *cmd_details) 3297 { 3298 struct i40e_aq_desc desc; 3299 struct i40e_aqc_pf_vf_message *cmd = 3300 (struct i40e_aqc_pf_vf_message *)&desc.params.raw; 3301 enum i40e_status_code status; 3302 3303 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf); 3304 cmd->id = CPU_TO_LE32(vfid); 3305 desc.cookie_high = CPU_TO_LE32(v_opcode); 3306 desc.cookie_low = CPU_TO_LE32(v_retval); 3307 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI); 3308 if (msglen) { 3309 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | 3310 I40E_AQ_FLAG_RD)); 3311 if (msglen > I40E_AQ_LARGE_BUF) 3312 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3313 desc.datalen = CPU_TO_LE16(msglen); 3314 } 3315 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details); 3316 3317 return status; 3318 } 3319 3320 /** 3321 * i40e_aq_debug_read_register 3322 * @hw: pointer to the hw struct 3323 * @reg_addr: register address 3324 * @reg_val: register value 3325 * @cmd_details: pointer to command details structure or NULL 3326 * 3327 * Read the register using the admin queue commands 3328 **/ 3329 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw, 3330 u32 reg_addr, u64 *reg_val, 3331 struct i40e_asq_cmd_details *cmd_details) 3332 { 3333 struct i40e_aq_desc desc; 3334 struct i40e_aqc_debug_reg_read_write *cmd_resp = 3335 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 3336 enum i40e_status_code status; 3337 3338 if (reg_val == NULL) 3339 return I40E_ERR_PARAM; 3340 3341 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg); 3342 3343 cmd_resp->address = CPU_TO_LE32(reg_addr); 3344 3345 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3346 3347 if (status == I40E_SUCCESS) { 3348 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) | 3349 (u64)LE32_TO_CPU(cmd_resp->value_low); 3350 } 3351 3352 return status; 3353 } 3354 3355 /** 3356 * i40e_aq_debug_write_register 3357 * @hw: pointer to the hw struct 3358 * @reg_addr: register address 3359 * @reg_val: register value 3360 * @cmd_details: pointer to command details structure or NULL 3361 * 3362 * Write to a register using the admin queue commands 3363 **/ 3364 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw, 3365 u32 reg_addr, u64 reg_val, 3366 struct i40e_asq_cmd_details *cmd_details) 3367 { 3368 struct i40e_aq_desc desc; 3369 struct i40e_aqc_debug_reg_read_write *cmd = 3370 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 3371 enum i40e_status_code status; 3372 3373 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg); 3374 3375 cmd->address = CPU_TO_LE32(reg_addr); 3376 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32)); 3377 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF)); 3378 3379 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3380 3381 return status; 3382 } 3383 3384 /** 3385 * i40e_aq_request_resource 3386 * @hw: pointer to the hw struct 3387 * @resource: resource id 3388 * @access: access type 3389 * @sdp_number: resource number 3390 * @timeout: the maximum time in ms that the driver may hold the resource 3391 * @cmd_details: pointer to command details structure or NULL 3392 * 3393 * requests common resource using the admin queue commands 3394 **/ 3395 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw, 3396 enum i40e_aq_resources_ids resource, 3397 enum i40e_aq_resource_access_type access, 3398 u8 sdp_number, u64 *timeout, 3399 struct i40e_asq_cmd_details *cmd_details) 3400 { 3401 struct i40e_aq_desc desc; 3402 struct i40e_aqc_request_resource *cmd_resp = 3403 (struct i40e_aqc_request_resource *)&desc.params.raw; 3404 enum i40e_status_code status; 3405 3406 DEBUGFUNC("i40e_aq_request_resource"); 3407 3408 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource); 3409 3410 cmd_resp->resource_id = CPU_TO_LE16(resource); 3411 cmd_resp->access_type = CPU_TO_LE16(access); 3412 cmd_resp->resource_number = CPU_TO_LE32(sdp_number); 3413 3414 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3415 /* The completion specifies the maximum time in ms that the driver 3416 * may hold the resource in the Timeout field. 3417 * If the resource is held by someone else, the command completes with 3418 * busy return value and the timeout field indicates the maximum time 3419 * the current owner of the resource has to free it. 3420 */ 3421 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) 3422 *timeout = LE32_TO_CPU(cmd_resp->timeout); 3423 3424 return status; 3425 } 3426 3427 /** 3428 * i40e_aq_release_resource 3429 * @hw: pointer to the hw struct 3430 * @resource: resource id 3431 * @sdp_number: resource number 3432 * @cmd_details: pointer to command details structure or NULL 3433 * 3434 * release common resource using the admin queue commands 3435 **/ 3436 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw, 3437 enum i40e_aq_resources_ids resource, 3438 u8 sdp_number, 3439 struct i40e_asq_cmd_details *cmd_details) 3440 { 3441 struct i40e_aq_desc desc; 3442 struct i40e_aqc_request_resource *cmd = 3443 (struct i40e_aqc_request_resource *)&desc.params.raw; 3444 enum i40e_status_code status; 3445 3446 DEBUGFUNC("i40e_aq_release_resource"); 3447 3448 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource); 3449 3450 cmd->resource_id = CPU_TO_LE16(resource); 3451 cmd->resource_number = CPU_TO_LE32(sdp_number); 3452 3453 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3454 3455 return status; 3456 } 3457 3458 /** 3459 * i40e_aq_read_nvm 3460 * @hw: pointer to the hw struct 3461 * @module_pointer: module pointer location in words from the NVM beginning 3462 * @offset: byte offset from the module beginning 3463 * @length: length of the section to be read (in bytes from the offset) 3464 * @data: command buffer (size [bytes] = length) 3465 * @last_command: tells if this is the last command in a series 3466 * @cmd_details: pointer to command details structure or NULL 3467 * 3468 * Read the NVM using the admin queue commands 3469 **/ 3470 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer, 3471 u32 offset, u16 length, void *data, 3472 bool last_command, 3473 struct i40e_asq_cmd_details *cmd_details) 3474 { 3475 struct i40e_aq_desc desc; 3476 struct i40e_aqc_nvm_update *cmd = 3477 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3478 enum i40e_status_code status; 3479 3480 DEBUGFUNC("i40e_aq_read_nvm"); 3481 3482 /* In offset the highest byte must be zeroed. */ 3483 if (offset & 0xFF000000) { 3484 status = I40E_ERR_PARAM; 3485 goto i40e_aq_read_nvm_exit; 3486 } 3487 3488 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read); 3489 3490 /* If this is the last command in a series, set the proper flag. */ 3491 if (last_command) 3492 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3493 cmd->module_pointer = module_pointer; 3494 cmd->offset = CPU_TO_LE32(offset); 3495 cmd->length = CPU_TO_LE16(length); 3496 3497 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 3498 if (length > I40E_AQ_LARGE_BUF) 3499 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3500 3501 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3502 3503 i40e_aq_read_nvm_exit: 3504 return status; 3505 } 3506 3507 /** 3508 * i40e_aq_read_nvm_config - read an nvm config block 3509 * @hw: pointer to the hw struct 3510 * @cmd_flags: NVM access admin command bits 3511 * @field_id: field or feature id 3512 * @data: buffer for result 3513 * @buf_size: buffer size 3514 * @element_count: pointer to count of elements read by FW 3515 * @cmd_details: pointer to command details structure or NULL 3516 **/ 3517 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw, 3518 u8 cmd_flags, u32 field_id, void *data, 3519 u16 buf_size, u16 *element_count, 3520 struct i40e_asq_cmd_details *cmd_details) 3521 { 3522 struct i40e_aq_desc desc; 3523 struct i40e_aqc_nvm_config_read *cmd = 3524 (struct i40e_aqc_nvm_config_read *)&desc.params.raw; 3525 enum i40e_status_code status; 3526 3527 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read); 3528 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF)); 3529 if (buf_size > I40E_AQ_LARGE_BUF) 3530 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3531 3532 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 3533 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id)); 3534 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK) 3535 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16)); 3536 else 3537 cmd->element_id_msw = 0; 3538 3539 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details); 3540 3541 if (!status && element_count) 3542 *element_count = LE16_TO_CPU(cmd->element_count); 3543 3544 return status; 3545 } 3546 3547 /** 3548 * i40e_aq_write_nvm_config - write an nvm config block 3549 * @hw: pointer to the hw struct 3550 * @cmd_flags: NVM access admin command bits 3551 * @data: buffer for result 3552 * @buf_size: buffer size 3553 * @element_count: count of elements to be written 3554 * @cmd_details: pointer to command details structure or NULL 3555 **/ 3556 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw, 3557 u8 cmd_flags, void *data, u16 buf_size, 3558 u16 element_count, 3559 struct i40e_asq_cmd_details *cmd_details) 3560 { 3561 struct i40e_aq_desc desc; 3562 struct i40e_aqc_nvm_config_write *cmd = 3563 (struct i40e_aqc_nvm_config_write *)&desc.params.raw; 3564 enum i40e_status_code status; 3565 3566 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write); 3567 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3568 if (buf_size > I40E_AQ_LARGE_BUF) 3569 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3570 3571 cmd->element_count = CPU_TO_LE16(element_count); 3572 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 3573 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details); 3574 3575 return status; 3576 } 3577 3578 /** 3579 * i40e_aq_oem_post_update - triggers an OEM specific flow after update 3580 * @hw: pointer to the hw struct 3581 * @buff: buffer for result 3582 * @buff_size: buffer size 3583 * @cmd_details: pointer to command details structure or NULL 3584 **/ 3585 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw, 3586 void *buff, u16 buff_size, 3587 struct i40e_asq_cmd_details *cmd_details) 3588 { 3589 struct i40e_aq_desc desc; 3590 enum i40e_status_code status; 3591 3592 3593 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update); 3594 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3595 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH) 3596 status = I40E_ERR_NOT_IMPLEMENTED; 3597 3598 return status; 3599 } 3600 3601 /** 3602 * i40e_aq_erase_nvm 3603 * @hw: pointer to the hw struct 3604 * @module_pointer: module pointer location in words from the NVM beginning 3605 * @offset: offset in the module (expressed in 4 KB from module's beginning) 3606 * @length: length of the section to be erased (expressed in 4 KB) 3607 * @last_command: tells if this is the last command in a series 3608 * @cmd_details: pointer to command details structure or NULL 3609 * 3610 * Erase the NVM sector using the admin queue commands 3611 **/ 3612 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer, 3613 u32 offset, u16 length, bool last_command, 3614 struct i40e_asq_cmd_details *cmd_details) 3615 { 3616 struct i40e_aq_desc desc; 3617 struct i40e_aqc_nvm_update *cmd = 3618 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3619 enum i40e_status_code status; 3620 3621 DEBUGFUNC("i40e_aq_erase_nvm"); 3622 3623 /* In offset the highest byte must be zeroed. */ 3624 if (offset & 0xFF000000) { 3625 status = I40E_ERR_PARAM; 3626 goto i40e_aq_erase_nvm_exit; 3627 } 3628 3629 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase); 3630 3631 /* If this is the last command in a series, set the proper flag. */ 3632 if (last_command) 3633 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3634 cmd->module_pointer = module_pointer; 3635 cmd->offset = CPU_TO_LE32(offset); 3636 cmd->length = CPU_TO_LE16(length); 3637 3638 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3639 3640 i40e_aq_erase_nvm_exit: 3641 return status; 3642 } 3643 3644 /** 3645 * i40e_parse_discover_capabilities 3646 * @hw: pointer to the hw struct 3647 * @buff: pointer to a buffer containing device/function capability records 3648 * @cap_count: number of capability records in the list 3649 * @list_type_opc: type of capabilities list to parse 3650 * 3651 * Parse the device/function capabilities list. 3652 **/ 3653 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, 3654 u32 cap_count, 3655 enum i40e_admin_queue_opc list_type_opc) 3656 { 3657 struct i40e_aqc_list_capabilities_element_resp *cap; 3658 u32 valid_functions, num_functions; 3659 u32 number, logical_id, phys_id; 3660 struct i40e_hw_capabilities *p; 3661 enum i40e_status_code status; 3662 u16 id, ocp_cfg_word0; 3663 u8 major_rev; 3664 u32 i = 0; 3665 3666 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff; 3667 3668 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities) 3669 p = (struct i40e_hw_capabilities *)&hw->dev_caps; 3670 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities) 3671 p = (struct i40e_hw_capabilities *)&hw->func_caps; 3672 else 3673 return; 3674 3675 for (i = 0; i < cap_count; i++, cap++) { 3676 id = LE16_TO_CPU(cap->id); 3677 number = LE32_TO_CPU(cap->number); 3678 logical_id = LE32_TO_CPU(cap->logical_id); 3679 phys_id = LE32_TO_CPU(cap->phys_id); 3680 major_rev = cap->major_rev; 3681 3682 switch (id) { 3683 case I40E_AQ_CAP_ID_SWITCH_MODE: 3684 p->switch_mode = number; 3685 i40e_debug(hw, I40E_DEBUG_INIT, 3686 "HW Capability: Switch mode = %d\n", 3687 p->switch_mode); 3688 break; 3689 case I40E_AQ_CAP_ID_MNG_MODE: 3690 p->management_mode = number; 3691 if (major_rev > 1) { 3692 p->mng_protocols_over_mctp = logical_id; 3693 i40e_debug(hw, I40E_DEBUG_INIT, 3694 "HW Capability: Protocols over MCTP = %d\n", 3695 p->mng_protocols_over_mctp); 3696 } else { 3697 p->mng_protocols_over_mctp = 0; 3698 } 3699 i40e_debug(hw, I40E_DEBUG_INIT, 3700 "HW Capability: Management Mode = %d\n", 3701 p->management_mode); 3702 break; 3703 case I40E_AQ_CAP_ID_NPAR_ACTIVE: 3704 p->npar_enable = number; 3705 i40e_debug(hw, I40E_DEBUG_INIT, 3706 "HW Capability: NPAR enable = %d\n", 3707 p->npar_enable); 3708 break; 3709 case I40E_AQ_CAP_ID_OS2BMC_CAP: 3710 p->os2bmc = number; 3711 i40e_debug(hw, I40E_DEBUG_INIT, 3712 "HW Capability: OS2BMC = %d\n", p->os2bmc); 3713 break; 3714 case I40E_AQ_CAP_ID_FUNCTIONS_VALID: 3715 p->valid_functions = number; 3716 i40e_debug(hw, I40E_DEBUG_INIT, 3717 "HW Capability: Valid Functions = %d\n", 3718 p->valid_functions); 3719 break; 3720 case I40E_AQ_CAP_ID_SRIOV: 3721 if (number == 1) 3722 p->sr_iov_1_1 = TRUE; 3723 i40e_debug(hw, I40E_DEBUG_INIT, 3724 "HW Capability: SR-IOV = %d\n", 3725 p->sr_iov_1_1); 3726 break; 3727 case I40E_AQ_CAP_ID_VF: 3728 p->num_vfs = number; 3729 p->vf_base_id = logical_id; 3730 i40e_debug(hw, I40E_DEBUG_INIT, 3731 "HW Capability: VF count = %d\n", 3732 p->num_vfs); 3733 i40e_debug(hw, I40E_DEBUG_INIT, 3734 "HW Capability: VF base_id = %d\n", 3735 p->vf_base_id); 3736 break; 3737 case I40E_AQ_CAP_ID_VMDQ: 3738 if (number == 1) 3739 p->vmdq = TRUE; 3740 i40e_debug(hw, I40E_DEBUG_INIT, 3741 "HW Capability: VMDQ = %d\n", p->vmdq); 3742 break; 3743 case I40E_AQ_CAP_ID_8021QBG: 3744 if (number == 1) 3745 p->evb_802_1_qbg = TRUE; 3746 i40e_debug(hw, I40E_DEBUG_INIT, 3747 "HW Capability: 802.1Qbg = %d\n", number); 3748 break; 3749 case I40E_AQ_CAP_ID_8021QBR: 3750 if (number == 1) 3751 p->evb_802_1_qbh = TRUE; 3752 i40e_debug(hw, I40E_DEBUG_INIT, 3753 "HW Capability: 802.1Qbh = %d\n", number); 3754 break; 3755 case I40E_AQ_CAP_ID_VSI: 3756 p->num_vsis = number; 3757 i40e_debug(hw, I40E_DEBUG_INIT, 3758 "HW Capability: VSI count = %d\n", 3759 p->num_vsis); 3760 break; 3761 case I40E_AQ_CAP_ID_DCB: 3762 if (number == 1) { 3763 p->dcb = TRUE; 3764 p->enabled_tcmap = logical_id; 3765 p->maxtc = phys_id; 3766 } 3767 i40e_debug(hw, I40E_DEBUG_INIT, 3768 "HW Capability: DCB = %d\n", p->dcb); 3769 i40e_debug(hw, I40E_DEBUG_INIT, 3770 "HW Capability: TC Mapping = %d\n", 3771 logical_id); 3772 i40e_debug(hw, I40E_DEBUG_INIT, 3773 "HW Capability: TC Max = %d\n", p->maxtc); 3774 break; 3775 case I40E_AQ_CAP_ID_FCOE: 3776 if (number == 1) 3777 p->fcoe = TRUE; 3778 i40e_debug(hw, I40E_DEBUG_INIT, 3779 "HW Capability: FCOE = %d\n", p->fcoe); 3780 break; 3781 case I40E_AQ_CAP_ID_ISCSI: 3782 if (number == 1) 3783 p->iscsi = TRUE; 3784 i40e_debug(hw, I40E_DEBUG_INIT, 3785 "HW Capability: iSCSI = %d\n", p->iscsi); 3786 break; 3787 case I40E_AQ_CAP_ID_RSS: 3788 p->rss = TRUE; 3789 p->rss_table_size = number; 3790 p->rss_table_entry_width = logical_id; 3791 i40e_debug(hw, I40E_DEBUG_INIT, 3792 "HW Capability: RSS = %d\n", p->rss); 3793 i40e_debug(hw, I40E_DEBUG_INIT, 3794 "HW Capability: RSS table size = %d\n", 3795 p->rss_table_size); 3796 i40e_debug(hw, I40E_DEBUG_INIT, 3797 "HW Capability: RSS table width = %d\n", 3798 p->rss_table_entry_width); 3799 break; 3800 case I40E_AQ_CAP_ID_RXQ: 3801 p->num_rx_qp = number; 3802 p->base_queue = phys_id; 3803 i40e_debug(hw, I40E_DEBUG_INIT, 3804 "HW Capability: Rx QP = %d\n", number); 3805 i40e_debug(hw, I40E_DEBUG_INIT, 3806 "HW Capability: base_queue = %d\n", 3807 p->base_queue); 3808 break; 3809 case I40E_AQ_CAP_ID_TXQ: 3810 p->num_tx_qp = number; 3811 p->base_queue = phys_id; 3812 i40e_debug(hw, I40E_DEBUG_INIT, 3813 "HW Capability: Tx QP = %d\n", number); 3814 i40e_debug(hw, I40E_DEBUG_INIT, 3815 "HW Capability: base_queue = %d\n", 3816 p->base_queue); 3817 break; 3818 case I40E_AQ_CAP_ID_MSIX: 3819 p->num_msix_vectors = number; 3820 i40e_debug(hw, I40E_DEBUG_INIT, 3821 "HW Capability: MSIX vector count = %d\n", 3822 p->num_msix_vectors); 3823 break; 3824 case I40E_AQ_CAP_ID_VF_MSIX: 3825 p->num_msix_vectors_vf = number; 3826 i40e_debug(hw, I40E_DEBUG_INIT, 3827 "HW Capability: MSIX VF vector count = %d\n", 3828 p->num_msix_vectors_vf); 3829 break; 3830 case I40E_AQ_CAP_ID_FLEX10: 3831 if (major_rev == 1) { 3832 if (number == 1) { 3833 p->flex10_enable = TRUE; 3834 p->flex10_capable = TRUE; 3835 } 3836 } else { 3837 /* Capability revision >= 2 */ 3838 if (number & 1) 3839 p->flex10_enable = TRUE; 3840 if (number & 2) 3841 p->flex10_capable = TRUE; 3842 } 3843 p->flex10_mode = logical_id; 3844 p->flex10_status = phys_id; 3845 i40e_debug(hw, I40E_DEBUG_INIT, 3846 "HW Capability: Flex10 mode = %d\n", 3847 p->flex10_mode); 3848 i40e_debug(hw, I40E_DEBUG_INIT, 3849 "HW Capability: Flex10 status = %d\n", 3850 p->flex10_status); 3851 break; 3852 case I40E_AQ_CAP_ID_CEM: 3853 if (number == 1) 3854 p->mgmt_cem = TRUE; 3855 i40e_debug(hw, I40E_DEBUG_INIT, 3856 "HW Capability: CEM = %d\n", p->mgmt_cem); 3857 break; 3858 case I40E_AQ_CAP_ID_IWARP: 3859 if (number == 1) 3860 p->iwarp = TRUE; 3861 i40e_debug(hw, I40E_DEBUG_INIT, 3862 "HW Capability: iWARP = %d\n", p->iwarp); 3863 break; 3864 case I40E_AQ_CAP_ID_LED: 3865 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3866 p->led[phys_id] = TRUE; 3867 i40e_debug(hw, I40E_DEBUG_INIT, 3868 "HW Capability: LED - PIN %d\n", phys_id); 3869 break; 3870 case I40E_AQ_CAP_ID_SDP: 3871 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3872 p->sdp[phys_id] = TRUE; 3873 i40e_debug(hw, I40E_DEBUG_INIT, 3874 "HW Capability: SDP - PIN %d\n", phys_id); 3875 break; 3876 case I40E_AQ_CAP_ID_MDIO: 3877 if (number == 1) { 3878 p->mdio_port_num = phys_id; 3879 p->mdio_port_mode = logical_id; 3880 } 3881 i40e_debug(hw, I40E_DEBUG_INIT, 3882 "HW Capability: MDIO port number = %d\n", 3883 p->mdio_port_num); 3884 i40e_debug(hw, I40E_DEBUG_INIT, 3885 "HW Capability: MDIO port mode = %d\n", 3886 p->mdio_port_mode); 3887 break; 3888 case I40E_AQ_CAP_ID_1588: 3889 if (number == 1) 3890 p->ieee_1588 = TRUE; 3891 i40e_debug(hw, I40E_DEBUG_INIT, 3892 "HW Capability: IEEE 1588 = %d\n", 3893 p->ieee_1588); 3894 break; 3895 case I40E_AQ_CAP_ID_FLOW_DIRECTOR: 3896 p->fd = TRUE; 3897 p->fd_filters_guaranteed = number; 3898 p->fd_filters_best_effort = logical_id; 3899 i40e_debug(hw, I40E_DEBUG_INIT, 3900 "HW Capability: Flow Director = 1\n"); 3901 i40e_debug(hw, I40E_DEBUG_INIT, 3902 "HW Capability: Guaranteed FD filters = %d\n", 3903 p->fd_filters_guaranteed); 3904 break; 3905 case I40E_AQ_CAP_ID_WSR_PROT: 3906 p->wr_csr_prot = (u64)number; 3907 p->wr_csr_prot |= (u64)logical_id << 32; 3908 i40e_debug(hw, I40E_DEBUG_INIT, 3909 "HW Capability: wr_csr_prot = 0x%llX\n\n", 3910 (p->wr_csr_prot & 0xffff)); 3911 break; 3912 case I40E_AQ_CAP_ID_NVM_MGMT: 3913 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED) 3914 p->sec_rev_disabled = TRUE; 3915 if (number & I40E_NVM_MGMT_UPDATE_DISABLED) 3916 p->update_disabled = TRUE; 3917 break; 3918 case I40E_AQ_CAP_ID_WOL_AND_PROXY: 3919 hw->num_wol_proxy_filters = (u16)number; 3920 hw->wol_proxy_vsi_seid = (u16)logical_id; 3921 p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK; 3922 if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK) 3923 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK; 3924 else 3925 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL; 3926 p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0; 3927 i40e_debug(hw, I40E_DEBUG_INIT, 3928 "HW Capability: WOL proxy filters = %d\n", 3929 hw->num_wol_proxy_filters); 3930 break; 3931 default: 3932 break; 3933 } 3934 } 3935 3936 if (p->fcoe) 3937 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n"); 3938 3939 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */ 3940 p->fcoe = FALSE; 3941 3942 /* count the enabled ports (aka the "not disabled" ports) */ 3943 hw->num_ports = 0; 3944 for (i = 0; i < 4; i++) { 3945 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i); 3946 u64 port_cfg = 0; 3947 3948 /* use AQ read to get the physical register offset instead 3949 * of the port relative offset 3950 */ 3951 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL); 3952 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK)) 3953 hw->num_ports++; 3954 } 3955 3956 /* OCP cards case: if a mezz is removed the ethernet port is at 3957 * disabled state in PRTGEN_CNF register. Additional NVM read is 3958 * needed in order to check if we are dealing with OCP card. 3959 * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting 3960 * physical ports results in wrong partition id calculation and thus 3961 * not supporting WoL. 3962 */ 3963 if (hw->mac.type == I40E_MAC_X722) { 3964 if (i40e_acquire_nvm(hw, I40E_RESOURCE_READ) == I40E_SUCCESS) { 3965 status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR, 3966 2 * I40E_SR_OCP_CFG_WORD0, 3967 sizeof(ocp_cfg_word0), 3968 &ocp_cfg_word0, TRUE, NULL); 3969 if (status == I40E_SUCCESS && 3970 (ocp_cfg_word0 & I40E_SR_OCP_ENABLED)) 3971 hw->num_ports = 4; 3972 i40e_release_nvm(hw); 3973 } 3974 } 3975 3976 valid_functions = p->valid_functions; 3977 num_functions = 0; 3978 while (valid_functions) { 3979 if (valid_functions & 1) 3980 num_functions++; 3981 valid_functions >>= 1; 3982 } 3983 3984 /* partition id is 1-based, and functions are evenly spread 3985 * across the ports as partitions 3986 */ 3987 if (hw->num_ports != 0) { 3988 hw->partition_id = (hw->pf_id / hw->num_ports) + 1; 3989 hw->num_partitions = num_functions / hw->num_ports; 3990 } 3991 3992 /* additional HW specific goodies that might 3993 * someday be HW version specific 3994 */ 3995 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS; 3996 } 3997 3998 /** 3999 * i40e_aq_discover_capabilities 4000 * @hw: pointer to the hw struct 4001 * @buff: a virtual buffer to hold the capabilities 4002 * @buff_size: Size of the virtual buffer 4003 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM 4004 * @list_type_opc: capabilities type to discover - pass in the command opcode 4005 * @cmd_details: pointer to command details structure or NULL 4006 * 4007 * Get the device capabilities descriptions from the firmware 4008 **/ 4009 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw, 4010 void *buff, u16 buff_size, u16 *data_size, 4011 enum i40e_admin_queue_opc list_type_opc, 4012 struct i40e_asq_cmd_details *cmd_details) 4013 { 4014 struct i40e_aqc_list_capabilites *cmd; 4015 struct i40e_aq_desc desc; 4016 enum i40e_status_code status = I40E_SUCCESS; 4017 4018 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw; 4019 4020 if (list_type_opc != i40e_aqc_opc_list_func_capabilities && 4021 list_type_opc != i40e_aqc_opc_list_dev_capabilities) { 4022 status = I40E_ERR_PARAM; 4023 goto exit; 4024 } 4025 4026 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc); 4027 4028 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4029 if (buff_size > I40E_AQ_LARGE_BUF) 4030 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4031 4032 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4033 *data_size = LE16_TO_CPU(desc.datalen); 4034 4035 if (status) 4036 goto exit; 4037 4038 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count), 4039 list_type_opc); 4040 4041 exit: 4042 return status; 4043 } 4044 4045 /** 4046 * i40e_aq_update_nvm 4047 * @hw: pointer to the hw struct 4048 * @module_pointer: module pointer location in words from the NVM beginning 4049 * @offset: byte offset from the module beginning 4050 * @length: length of the section to be written (in bytes from the offset) 4051 * @data: command buffer (size [bytes] = length) 4052 * @last_command: tells if this is the last command in a series 4053 * @preservation_flags: Preservation mode flags 4054 * @cmd_details: pointer to command details structure or NULL 4055 * 4056 * Update the NVM using the admin queue commands 4057 **/ 4058 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer, 4059 u32 offset, u16 length, void *data, 4060 bool last_command, u8 preservation_flags, 4061 struct i40e_asq_cmd_details *cmd_details) 4062 { 4063 struct i40e_aq_desc desc; 4064 struct i40e_aqc_nvm_update *cmd = 4065 (struct i40e_aqc_nvm_update *)&desc.params.raw; 4066 enum i40e_status_code status; 4067 4068 DEBUGFUNC("i40e_aq_update_nvm"); 4069 4070 /* In offset the highest byte must be zeroed. */ 4071 if (offset & 0xFF000000) { 4072 status = I40E_ERR_PARAM; 4073 goto i40e_aq_update_nvm_exit; 4074 } 4075 4076 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 4077 4078 /* If this is the last command in a series, set the proper flag. */ 4079 if (last_command) 4080 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 4081 if (hw->mac.type == I40E_MAC_X722) { 4082 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED) 4083 cmd->command_flags |= 4084 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED << 4085 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT); 4086 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL) 4087 cmd->command_flags |= 4088 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL << 4089 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT); 4090 } 4091 cmd->module_pointer = module_pointer; 4092 cmd->offset = CPU_TO_LE32(offset); 4093 cmd->length = CPU_TO_LE16(length); 4094 4095 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4096 if (length > I40E_AQ_LARGE_BUF) 4097 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4098 4099 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 4100 4101 i40e_aq_update_nvm_exit: 4102 return status; 4103 } 4104 4105 /** 4106 * i40e_aq_nvm_progress 4107 * @hw: pointer to the hw struct 4108 * @progress: pointer to progress returned from AQ 4109 * @cmd_details: pointer to command details structure or NULL 4110 * 4111 * Gets progress of flash rearrangement process 4112 **/ 4113 enum i40e_status_code i40e_aq_nvm_progress(struct i40e_hw *hw, u8 *progress, 4114 struct i40e_asq_cmd_details *cmd_details) 4115 { 4116 enum i40e_status_code status; 4117 struct i40e_aq_desc desc; 4118 4119 DEBUGFUNC("i40e_aq_nvm_progress"); 4120 4121 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_progress); 4122 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4123 *progress = desc.params.raw[0]; 4124 return status; 4125 } 4126 4127 /** 4128 * i40e_aq_get_lldp_mib 4129 * @hw: pointer to the hw struct 4130 * @bridge_type: type of bridge requested 4131 * @mib_type: Local, Remote or both Local and Remote MIBs 4132 * @buff: pointer to a user supplied buffer to store the MIB block 4133 * @buff_size: size of the buffer (in bytes) 4134 * @local_len : length of the returned Local LLDP MIB 4135 * @remote_len: length of the returned Remote LLDP MIB 4136 * @cmd_details: pointer to command details structure or NULL 4137 * 4138 * Requests the complete LLDP MIB (entire packet). 4139 **/ 4140 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type, 4141 u8 mib_type, void *buff, u16 buff_size, 4142 u16 *local_len, u16 *remote_len, 4143 struct i40e_asq_cmd_details *cmd_details) 4144 { 4145 struct i40e_aq_desc desc; 4146 struct i40e_aqc_lldp_get_mib *cmd = 4147 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 4148 struct i40e_aqc_lldp_get_mib *resp = 4149 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 4150 enum i40e_status_code status; 4151 4152 if (buff_size == 0 || !buff) 4153 return I40E_ERR_PARAM; 4154 4155 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib); 4156 /* Indirect Command */ 4157 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4158 4159 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK; 4160 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 4161 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 4162 4163 desc.datalen = CPU_TO_LE16(buff_size); 4164 4165 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4166 if (buff_size > I40E_AQ_LARGE_BUF) 4167 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4168 4169 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4170 if (!status) { 4171 if (local_len != NULL) 4172 *local_len = LE16_TO_CPU(resp->local_len); 4173 if (remote_len != NULL) 4174 *remote_len = LE16_TO_CPU(resp->remote_len); 4175 } 4176 4177 return status; 4178 } 4179 4180 /** 4181 * i40e_aq_set_lldp_mib - Set the LLDP MIB 4182 * @hw: pointer to the hw struct 4183 * @mib_type: Local, Remote or both Local and Remote MIBs 4184 * @buff: pointer to a user supplied buffer to store the MIB block 4185 * @buff_size: size of the buffer (in bytes) 4186 * @cmd_details: pointer to command details structure or NULL 4187 * 4188 * Set the LLDP MIB. 4189 **/ 4190 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw, 4191 u8 mib_type, void *buff, u16 buff_size, 4192 struct i40e_asq_cmd_details *cmd_details) 4193 { 4194 struct i40e_aq_desc desc; 4195 struct i40e_aqc_lldp_set_local_mib *cmd = 4196 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw; 4197 enum i40e_status_code status; 4198 4199 if (buff_size == 0 || !buff) 4200 return I40E_ERR_PARAM; 4201 4202 i40e_fill_default_direct_cmd_desc(&desc, 4203 i40e_aqc_opc_lldp_set_local_mib); 4204 /* Indirect Command */ 4205 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4206 if (buff_size > I40E_AQ_LARGE_BUF) 4207 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4208 desc.datalen = CPU_TO_LE16(buff_size); 4209 4210 cmd->type = mib_type; 4211 cmd->length = CPU_TO_LE16(buff_size); 4212 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff)); 4213 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff)); 4214 4215 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4216 return status; 4217 } 4218 4219 /** 4220 * i40e_aq_cfg_lldp_mib_change_event 4221 * @hw: pointer to the hw struct 4222 * @enable_update: Enable or Disable event posting 4223 * @cmd_details: pointer to command details structure or NULL 4224 * 4225 * Enable or Disable posting of an event on ARQ when LLDP MIB 4226 * associated with the interface changes 4227 **/ 4228 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw, 4229 bool enable_update, 4230 struct i40e_asq_cmd_details *cmd_details) 4231 { 4232 struct i40e_aq_desc desc; 4233 struct i40e_aqc_lldp_update_mib *cmd = 4234 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw; 4235 enum i40e_status_code status; 4236 4237 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib); 4238 4239 if (!enable_update) 4240 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE; 4241 4242 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4243 4244 return status; 4245 } 4246 4247 /** 4248 * i40e_aq_add_lldp_tlv 4249 * @hw: pointer to the hw struct 4250 * @bridge_type: type of bridge 4251 * @buff: buffer with TLV to add 4252 * @buff_size: length of the buffer 4253 * @tlv_len: length of the TLV to be added 4254 * @mib_len: length of the LLDP MIB returned in response 4255 * @cmd_details: pointer to command details structure or NULL 4256 * 4257 * Add the specified TLV to LLDP Local MIB for the given bridge type, 4258 * it is responsibility of the caller to make sure that the TLV is not 4259 * already present in the LLDPDU. 4260 * In return firmware will write the complete LLDP MIB with the newly 4261 * added TLV in the response buffer. 4262 **/ 4263 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type, 4264 void *buff, u16 buff_size, u16 tlv_len, 4265 u16 *mib_len, 4266 struct i40e_asq_cmd_details *cmd_details) 4267 { 4268 struct i40e_aq_desc desc; 4269 struct i40e_aqc_lldp_add_tlv *cmd = 4270 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw; 4271 enum i40e_status_code status; 4272 4273 if (buff_size == 0 || !buff || tlv_len == 0) 4274 return I40E_ERR_PARAM; 4275 4276 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv); 4277 4278 /* Indirect Command */ 4279 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4280 if (buff_size > I40E_AQ_LARGE_BUF) 4281 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4282 desc.datalen = CPU_TO_LE16(buff_size); 4283 4284 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 4285 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 4286 cmd->len = CPU_TO_LE16(tlv_len); 4287 4288 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4289 if (!status) { 4290 if (mib_len != NULL) 4291 *mib_len = LE16_TO_CPU(desc.datalen); 4292 } 4293 4294 return status; 4295 } 4296 4297 /** 4298 * i40e_aq_update_lldp_tlv 4299 * @hw: pointer to the hw struct 4300 * @bridge_type: type of bridge 4301 * @buff: buffer with TLV to update 4302 * @buff_size: size of the buffer holding original and updated TLVs 4303 * @old_len: Length of the Original TLV 4304 * @new_len: Length of the Updated TLV 4305 * @offset: offset of the updated TLV in the buff 4306 * @mib_len: length of the returned LLDP MIB 4307 * @cmd_details: pointer to command details structure or NULL 4308 * 4309 * Update the specified TLV to the LLDP Local MIB for the given bridge type. 4310 * Firmware will place the complete LLDP MIB in response buffer with the 4311 * updated TLV. 4312 **/ 4313 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw, 4314 u8 bridge_type, void *buff, u16 buff_size, 4315 u16 old_len, u16 new_len, u16 offset, 4316 u16 *mib_len, 4317 struct i40e_asq_cmd_details *cmd_details) 4318 { 4319 struct i40e_aq_desc desc; 4320 struct i40e_aqc_lldp_update_tlv *cmd = 4321 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw; 4322 enum i40e_status_code status; 4323 4324 if (buff_size == 0 || !buff || offset == 0 || 4325 old_len == 0 || new_len == 0) 4326 return I40E_ERR_PARAM; 4327 4328 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv); 4329 4330 /* Indirect Command */ 4331 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4332 if (buff_size > I40E_AQ_LARGE_BUF) 4333 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4334 desc.datalen = CPU_TO_LE16(buff_size); 4335 4336 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 4337 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 4338 cmd->old_len = CPU_TO_LE16(old_len); 4339 cmd->new_offset = CPU_TO_LE16(offset); 4340 cmd->new_len = CPU_TO_LE16(new_len); 4341 4342 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4343 if (!status) { 4344 if (mib_len != NULL) 4345 *mib_len = LE16_TO_CPU(desc.datalen); 4346 } 4347 4348 return status; 4349 } 4350 4351 /** 4352 * i40e_aq_delete_lldp_tlv 4353 * @hw: pointer to the hw struct 4354 * @bridge_type: type of bridge 4355 * @buff: pointer to a user supplied buffer that has the TLV 4356 * @buff_size: length of the buffer 4357 * @tlv_len: length of the TLV to be deleted 4358 * @mib_len: length of the returned LLDP MIB 4359 * @cmd_details: pointer to command details structure or NULL 4360 * 4361 * Delete the specified TLV from LLDP Local MIB for the given bridge type. 4362 * The firmware places the entire LLDP MIB in the response buffer. 4363 **/ 4364 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw, 4365 u8 bridge_type, void *buff, u16 buff_size, 4366 u16 tlv_len, u16 *mib_len, 4367 struct i40e_asq_cmd_details *cmd_details) 4368 { 4369 struct i40e_aq_desc desc; 4370 struct i40e_aqc_lldp_add_tlv *cmd = 4371 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw; 4372 enum i40e_status_code status; 4373 4374 if (buff_size == 0 || !buff) 4375 return I40E_ERR_PARAM; 4376 4377 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv); 4378 4379 /* Indirect Command */ 4380 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4381 if (buff_size > I40E_AQ_LARGE_BUF) 4382 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4383 desc.datalen = CPU_TO_LE16(buff_size); 4384 cmd->len = CPU_TO_LE16(tlv_len); 4385 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 4386 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 4387 4388 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4389 if (!status) { 4390 if (mib_len != NULL) 4391 *mib_len = LE16_TO_CPU(desc.datalen); 4392 } 4393 4394 return status; 4395 } 4396 4397 /** 4398 * i40e_aq_stop_lldp 4399 * @hw: pointer to the hw struct 4400 * @shutdown_agent: True if LLDP Agent needs to be Shutdown 4401 * @cmd_details: pointer to command details structure or NULL 4402 * 4403 * Stop or Shutdown the embedded LLDP Agent 4404 **/ 4405 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent, 4406 struct i40e_asq_cmd_details *cmd_details) 4407 { 4408 struct i40e_aq_desc desc; 4409 struct i40e_aqc_lldp_stop *cmd = 4410 (struct i40e_aqc_lldp_stop *)&desc.params.raw; 4411 enum i40e_status_code status; 4412 4413 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop); 4414 4415 if (shutdown_agent) 4416 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN; 4417 4418 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4419 4420 return status; 4421 } 4422 4423 /** 4424 * i40e_aq_start_lldp 4425 * @hw: pointer to the hw struct 4426 * @cmd_details: pointer to command details structure or NULL 4427 * 4428 * Start the embedded LLDP Agent on all ports. 4429 **/ 4430 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw, 4431 struct i40e_asq_cmd_details *cmd_details) 4432 { 4433 struct i40e_aq_desc desc; 4434 struct i40e_aqc_lldp_start *cmd = 4435 (struct i40e_aqc_lldp_start *)&desc.params.raw; 4436 enum i40e_status_code status; 4437 4438 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start); 4439 4440 cmd->command = I40E_AQ_LLDP_AGENT_START; 4441 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4442 4443 return status; 4444 } 4445 4446 /** 4447 * i40e_aq_set_dcb_parameters 4448 * @hw: pointer to the hw struct 4449 * @cmd_details: pointer to command details structure or NULL 4450 * @dcb_enable: True if DCB configuration needs to be applied 4451 * 4452 **/ 4453 enum i40e_status_code 4454 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable, 4455 struct i40e_asq_cmd_details *cmd_details) 4456 { 4457 struct i40e_aq_desc desc; 4458 struct i40e_aqc_set_dcb_parameters *cmd = 4459 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw; 4460 enum i40e_status_code status; 4461 4462 if ((hw->mac.type != I40E_MAC_XL710) || 4463 ((hw->aq.api_maj_ver < 1) || 4464 ((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 6)))) 4465 return I40E_ERR_DEVICE_NOT_SUPPORTED; 4466 4467 i40e_fill_default_direct_cmd_desc(&desc, 4468 i40e_aqc_opc_set_dcb_parameters); 4469 4470 if (dcb_enable) { 4471 cmd->valid_flags = I40E_DCB_VALID; 4472 cmd->command = I40E_AQ_DCB_SET_AGENT; 4473 } 4474 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4475 4476 return status; 4477 } 4478 4479 /** 4480 * i40e_aq_get_cee_dcb_config 4481 * @hw: pointer to the hw struct 4482 * @buff: response buffer that stores CEE operational configuration 4483 * @buff_size: size of the buffer passed 4484 * @cmd_details: pointer to command details structure or NULL 4485 * 4486 * Get CEE DCBX mode operational configuration from firmware 4487 **/ 4488 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw, 4489 void *buff, u16 buff_size, 4490 struct i40e_asq_cmd_details *cmd_details) 4491 { 4492 struct i40e_aq_desc desc; 4493 enum i40e_status_code status; 4494 4495 if (buff_size == 0 || !buff) 4496 return I40E_ERR_PARAM; 4497 4498 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg); 4499 4500 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4501 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size, 4502 cmd_details); 4503 4504 return status; 4505 } 4506 4507 /** 4508 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW 4509 * @hw: pointer to the hw struct 4510 * @start_agent: True if DCBx Agent needs to be Started 4511 * False if DCBx Agent needs to be Stopped 4512 * @cmd_details: pointer to command details structure or NULL 4513 * 4514 * Start/Stop the embedded dcbx Agent 4515 **/ 4516 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw, 4517 bool start_agent, 4518 struct i40e_asq_cmd_details *cmd_details) 4519 { 4520 struct i40e_aq_desc desc; 4521 struct i40e_aqc_lldp_stop_start_specific_agent *cmd = 4522 (struct i40e_aqc_lldp_stop_start_specific_agent *) 4523 &desc.params.raw; 4524 enum i40e_status_code status; 4525 4526 i40e_fill_default_direct_cmd_desc(&desc, 4527 i40e_aqc_opc_lldp_stop_start_spec_agent); 4528 4529 if (start_agent) 4530 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK; 4531 4532 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4533 4534 return status; 4535 } 4536 4537 /** 4538 * i40e_aq_add_udp_tunnel 4539 * @hw: pointer to the hw struct 4540 * @udp_port: the UDP port to add in Host byte order 4541 * @protocol_index: protocol index type 4542 * @filter_index: pointer to filter index 4543 * @cmd_details: pointer to command details structure or NULL 4544 * 4545 * Note: Firmware expects the udp_port value to be in Little Endian format, 4546 * and this function will call CPU_TO_LE16 to convert from Host byte order to 4547 * Little Endian order. 4548 **/ 4549 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw, 4550 u16 udp_port, u8 protocol_index, 4551 u8 *filter_index, 4552 struct i40e_asq_cmd_details *cmd_details) 4553 { 4554 struct i40e_aq_desc desc; 4555 struct i40e_aqc_add_udp_tunnel *cmd = 4556 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw; 4557 struct i40e_aqc_del_udp_tunnel_completion *resp = 4558 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw; 4559 enum i40e_status_code status; 4560 4561 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel); 4562 4563 cmd->udp_port = CPU_TO_LE16(udp_port); 4564 cmd->protocol_type = protocol_index; 4565 4566 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4567 4568 if (!status && filter_index) 4569 *filter_index = resp->index; 4570 4571 return status; 4572 } 4573 4574 /** 4575 * i40e_aq_del_udp_tunnel 4576 * @hw: pointer to the hw struct 4577 * @index: filter index 4578 * @cmd_details: pointer to command details structure or NULL 4579 **/ 4580 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index, 4581 struct i40e_asq_cmd_details *cmd_details) 4582 { 4583 struct i40e_aq_desc desc; 4584 struct i40e_aqc_remove_udp_tunnel *cmd = 4585 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw; 4586 enum i40e_status_code status; 4587 4588 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel); 4589 4590 cmd->index = index; 4591 4592 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4593 4594 return status; 4595 } 4596 4597 /** 4598 * i40e_aq_get_switch_resource_alloc (0x0204) 4599 * @hw: pointer to the hw struct 4600 * @num_entries: pointer to u8 to store the number of resource entries returned 4601 * @buf: pointer to a user supplied buffer. This buffer must be large enough 4602 * to store the resource information for all resource types. Each 4603 * resource type is a i40e_aqc_switch_resource_alloc_data structure. 4604 * @count: size, in bytes, of the buffer provided 4605 * @cmd_details: pointer to command details structure or NULL 4606 * 4607 * Query the resources allocated to a function. 4608 **/ 4609 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw, 4610 u8 *num_entries, 4611 struct i40e_aqc_switch_resource_alloc_element_resp *buf, 4612 u16 count, 4613 struct i40e_asq_cmd_details *cmd_details) 4614 { 4615 struct i40e_aq_desc desc; 4616 struct i40e_aqc_get_switch_resource_alloc *cmd_resp = 4617 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw; 4618 enum i40e_status_code status; 4619 u16 length = count * sizeof(*buf); 4620 4621 i40e_fill_default_direct_cmd_desc(&desc, 4622 i40e_aqc_opc_get_switch_resource_alloc); 4623 4624 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4625 if (length > I40E_AQ_LARGE_BUF) 4626 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4627 4628 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details); 4629 4630 if (!status && num_entries) 4631 *num_entries = cmd_resp->num_entries; 4632 4633 return status; 4634 } 4635 4636 /** 4637 * i40e_aq_delete_element - Delete switch element 4638 * @hw: pointer to the hw struct 4639 * @seid: the SEID to delete from the switch 4640 * @cmd_details: pointer to command details structure or NULL 4641 * 4642 * This deletes a switch element from the switch. 4643 **/ 4644 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid, 4645 struct i40e_asq_cmd_details *cmd_details) 4646 { 4647 struct i40e_aq_desc desc; 4648 struct i40e_aqc_switch_seid *cmd = 4649 (struct i40e_aqc_switch_seid *)&desc.params.raw; 4650 enum i40e_status_code status; 4651 4652 if (seid == 0) 4653 return I40E_ERR_PARAM; 4654 4655 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element); 4656 4657 cmd->seid = CPU_TO_LE16(seid); 4658 4659 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4660 4661 return status; 4662 } 4663 4664 /** 4665 * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port 4666 * @hw: pointer to the hw struct 4667 * @flags: component flags 4668 * @mac_seid: uplink seid (MAC SEID) 4669 * @vsi_seid: connected vsi seid 4670 * @ret_seid: seid of create pv component 4671 * 4672 * This instantiates an i40e port virtualizer with specified flags. 4673 * Depending on specified flags the port virtualizer can act as a 4674 * 802.1Qbr port virtualizer or a 802.1Qbg S-component. 4675 */ 4676 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags, 4677 u16 mac_seid, u16 vsi_seid, 4678 u16 *ret_seid) 4679 { 4680 struct i40e_aq_desc desc; 4681 struct i40e_aqc_add_update_pv *cmd = 4682 (struct i40e_aqc_add_update_pv *)&desc.params.raw; 4683 struct i40e_aqc_add_update_pv_completion *resp = 4684 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw; 4685 enum i40e_status_code status; 4686 4687 if (vsi_seid == 0) 4688 return I40E_ERR_PARAM; 4689 4690 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv); 4691 cmd->command_flags = CPU_TO_LE16(flags); 4692 cmd->uplink_seid = CPU_TO_LE16(mac_seid); 4693 cmd->connected_seid = CPU_TO_LE16(vsi_seid); 4694 4695 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 4696 if (!status && ret_seid) 4697 *ret_seid = LE16_TO_CPU(resp->pv_seid); 4698 4699 return status; 4700 } 4701 4702 /** 4703 * i40e_aq_add_tag - Add an S/E-tag 4704 * @hw: pointer to the hw struct 4705 * @direct_to_queue: should s-tag direct flow to a specific queue 4706 * @vsi_seid: VSI SEID to use this tag 4707 * @tag: value of the tag 4708 * @queue_num: queue number, only valid is direct_to_queue is TRUE 4709 * @tags_used: return value, number of tags in use by this PF 4710 * @tags_free: return value, number of unallocated tags 4711 * @cmd_details: pointer to command details structure or NULL 4712 * 4713 * This associates an S- or E-tag to a VSI in the switch complex. It returns 4714 * the number of tags allocated by the PF, and the number of unallocated 4715 * tags available. 4716 **/ 4717 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue, 4718 u16 vsi_seid, u16 tag, u16 queue_num, 4719 u16 *tags_used, u16 *tags_free, 4720 struct i40e_asq_cmd_details *cmd_details) 4721 { 4722 struct i40e_aq_desc desc; 4723 struct i40e_aqc_add_tag *cmd = 4724 (struct i40e_aqc_add_tag *)&desc.params.raw; 4725 struct i40e_aqc_add_remove_tag_completion *resp = 4726 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw; 4727 enum i40e_status_code status; 4728 4729 if (vsi_seid == 0) 4730 return I40E_ERR_PARAM; 4731 4732 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag); 4733 4734 cmd->seid = CPU_TO_LE16(vsi_seid); 4735 cmd->tag = CPU_TO_LE16(tag); 4736 if (direct_to_queue) { 4737 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE); 4738 cmd->queue_number = CPU_TO_LE16(queue_num); 4739 } 4740 4741 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4742 4743 if (!status) { 4744 if (tags_used != NULL) 4745 *tags_used = LE16_TO_CPU(resp->tags_used); 4746 if (tags_free != NULL) 4747 *tags_free = LE16_TO_CPU(resp->tags_free); 4748 } 4749 4750 return status; 4751 } 4752 4753 /** 4754 * i40e_aq_remove_tag - Remove an S- or E-tag 4755 * @hw: pointer to the hw struct 4756 * @vsi_seid: VSI SEID this tag is associated with 4757 * @tag: value of the S-tag to delete 4758 * @tags_used: return value, number of tags in use by this PF 4759 * @tags_free: return value, number of unallocated tags 4760 * @cmd_details: pointer to command details structure or NULL 4761 * 4762 * This deletes an S- or E-tag from a VSI in the switch complex. It returns 4763 * the number of tags allocated by the PF, and the number of unallocated 4764 * tags available. 4765 **/ 4766 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid, 4767 u16 tag, u16 *tags_used, u16 *tags_free, 4768 struct i40e_asq_cmd_details *cmd_details) 4769 { 4770 struct i40e_aq_desc desc; 4771 struct i40e_aqc_remove_tag *cmd = 4772 (struct i40e_aqc_remove_tag *)&desc.params.raw; 4773 struct i40e_aqc_add_remove_tag_completion *resp = 4774 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw; 4775 enum i40e_status_code status; 4776 4777 if (vsi_seid == 0) 4778 return I40E_ERR_PARAM; 4779 4780 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag); 4781 4782 cmd->seid = CPU_TO_LE16(vsi_seid); 4783 cmd->tag = CPU_TO_LE16(tag); 4784 4785 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4786 4787 if (!status) { 4788 if (tags_used != NULL) 4789 *tags_used = LE16_TO_CPU(resp->tags_used); 4790 if (tags_free != NULL) 4791 *tags_free = LE16_TO_CPU(resp->tags_free); 4792 } 4793 4794 return status; 4795 } 4796 4797 /** 4798 * i40e_aq_add_mcast_etag - Add a multicast E-tag 4799 * @hw: pointer to the hw struct 4800 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with 4801 * @etag: value of E-tag to add 4802 * @num_tags_in_buf: number of unicast E-tags in indirect buffer 4803 * @buf: address of indirect buffer 4804 * @tags_used: return value, number of E-tags in use by this port 4805 * @tags_free: return value, number of unallocated M-tags 4806 * @cmd_details: pointer to command details structure or NULL 4807 * 4808 * This associates a multicast E-tag to a port virtualizer. It will return 4809 * the number of tags allocated by the PF, and the number of unallocated 4810 * tags available. 4811 * 4812 * The indirect buffer pointed to by buf is a list of 2-byte E-tags, 4813 * num_tags_in_buf long. 4814 **/ 4815 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid, 4816 u16 etag, u8 num_tags_in_buf, void *buf, 4817 u16 *tags_used, u16 *tags_free, 4818 struct i40e_asq_cmd_details *cmd_details) 4819 { 4820 struct i40e_aq_desc desc; 4821 struct i40e_aqc_add_remove_mcast_etag *cmd = 4822 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw; 4823 struct i40e_aqc_add_remove_mcast_etag_completion *resp = 4824 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw; 4825 enum i40e_status_code status; 4826 u16 length = sizeof(u16) * num_tags_in_buf; 4827 4828 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0)) 4829 return I40E_ERR_PARAM; 4830 4831 i40e_fill_default_direct_cmd_desc(&desc, 4832 i40e_aqc_opc_add_multicast_etag); 4833 4834 cmd->pv_seid = CPU_TO_LE16(pv_seid); 4835 cmd->etag = CPU_TO_LE16(etag); 4836 cmd->num_unicast_etags = num_tags_in_buf; 4837 4838 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4839 if (length > I40E_AQ_LARGE_BUF) 4840 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4841 4842 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details); 4843 4844 if (!status) { 4845 if (tags_used != NULL) 4846 *tags_used = LE16_TO_CPU(resp->mcast_etags_used); 4847 if (tags_free != NULL) 4848 *tags_free = LE16_TO_CPU(resp->mcast_etags_free); 4849 } 4850 4851 return status; 4852 } 4853 4854 /** 4855 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag 4856 * @hw: pointer to the hw struct 4857 * @pv_seid: Port Virtualizer SEID this M-tag is associated with 4858 * @etag: value of the E-tag to remove 4859 * @tags_used: return value, number of tags in use by this port 4860 * @tags_free: return value, number of unallocated tags 4861 * @cmd_details: pointer to command details structure or NULL 4862 * 4863 * This deletes an E-tag from the port virtualizer. It will return 4864 * the number of tags allocated by the port, and the number of unallocated 4865 * tags available. 4866 **/ 4867 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid, 4868 u16 etag, u16 *tags_used, u16 *tags_free, 4869 struct i40e_asq_cmd_details *cmd_details) 4870 { 4871 struct i40e_aq_desc desc; 4872 struct i40e_aqc_add_remove_mcast_etag *cmd = 4873 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw; 4874 struct i40e_aqc_add_remove_mcast_etag_completion *resp = 4875 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw; 4876 enum i40e_status_code status; 4877 4878 4879 if (pv_seid == 0) 4880 return I40E_ERR_PARAM; 4881 4882 i40e_fill_default_direct_cmd_desc(&desc, 4883 i40e_aqc_opc_remove_multicast_etag); 4884 4885 cmd->pv_seid = CPU_TO_LE16(pv_seid); 4886 cmd->etag = CPU_TO_LE16(etag); 4887 4888 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4889 4890 if (!status) { 4891 if (tags_used != NULL) 4892 *tags_used = LE16_TO_CPU(resp->mcast_etags_used); 4893 if (tags_free != NULL) 4894 *tags_free = LE16_TO_CPU(resp->mcast_etags_free); 4895 } 4896 4897 return status; 4898 } 4899 4900 /** 4901 * i40e_aq_update_tag - Update an S/E-tag 4902 * @hw: pointer to the hw struct 4903 * @vsi_seid: VSI SEID using this S-tag 4904 * @old_tag: old tag value 4905 * @new_tag: new tag value 4906 * @tags_used: return value, number of tags in use by this PF 4907 * @tags_free: return value, number of unallocated tags 4908 * @cmd_details: pointer to command details structure or NULL 4909 * 4910 * This updates the value of the tag currently attached to this VSI 4911 * in the switch complex. It will return the number of tags allocated 4912 * by the PF, and the number of unallocated tags available. 4913 **/ 4914 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid, 4915 u16 old_tag, u16 new_tag, u16 *tags_used, 4916 u16 *tags_free, 4917 struct i40e_asq_cmd_details *cmd_details) 4918 { 4919 struct i40e_aq_desc desc; 4920 struct i40e_aqc_update_tag *cmd = 4921 (struct i40e_aqc_update_tag *)&desc.params.raw; 4922 struct i40e_aqc_update_tag_completion *resp = 4923 (struct i40e_aqc_update_tag_completion *)&desc.params.raw; 4924 enum i40e_status_code status; 4925 4926 if (vsi_seid == 0) 4927 return I40E_ERR_PARAM; 4928 4929 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag); 4930 4931 cmd->seid = CPU_TO_LE16(vsi_seid); 4932 cmd->old_tag = CPU_TO_LE16(old_tag); 4933 cmd->new_tag = CPU_TO_LE16(new_tag); 4934 4935 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4936 4937 if (!status) { 4938 if (tags_used != NULL) 4939 *tags_used = LE16_TO_CPU(resp->tags_used); 4940 if (tags_free != NULL) 4941 *tags_free = LE16_TO_CPU(resp->tags_free); 4942 } 4943 4944 return status; 4945 } 4946 4947 /** 4948 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs 4949 * @hw: pointer to the hw struct 4950 * @tcmap: TC map for request/release any ignore PFC condition 4951 * @request: request or release ignore PFC condition 4952 * @tcmap_ret: return TCs for which PFC is currently ignored 4953 * @cmd_details: pointer to command details structure or NULL 4954 * 4955 * This sends out request/release to ignore PFC condition for a TC. 4956 * It will return the TCs for which PFC is currently ignored. 4957 **/ 4958 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap, 4959 bool request, u8 *tcmap_ret, 4960 struct i40e_asq_cmd_details *cmd_details) 4961 { 4962 struct i40e_aq_desc desc; 4963 struct i40e_aqc_pfc_ignore *cmd_resp = 4964 (struct i40e_aqc_pfc_ignore *)&desc.params.raw; 4965 enum i40e_status_code status; 4966 4967 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc); 4968 4969 if (request) 4970 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET; 4971 4972 cmd_resp->tc_bitmap = tcmap; 4973 4974 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4975 4976 if (!status) { 4977 if (tcmap_ret != NULL) 4978 *tcmap_ret = cmd_resp->tc_bitmap; 4979 } 4980 4981 return status; 4982 } 4983 4984 /** 4985 * i40e_aq_dcb_updated - DCB Updated Command 4986 * @hw: pointer to the hw struct 4987 * @cmd_details: pointer to command details structure or NULL 4988 * 4989 * When LLDP is handled in PF this command is used by the PF 4990 * to notify EMP that a DCB setting is modified. 4991 * When LLDP is handled in EMP this command is used by the PF 4992 * to notify EMP whenever one of the following parameters get 4993 * modified: 4994 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA 4995 * - PCIRTT in PRTDCB_GENC.PCIRTT 4996 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME. 4997 * EMP will return when the shared RPB settings have been 4998 * recomputed and modified. The retval field in the descriptor 4999 * will be set to 0 when RPB is modified. 5000 **/ 5001 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw, 5002 struct i40e_asq_cmd_details *cmd_details) 5003 { 5004 struct i40e_aq_desc desc; 5005 enum i40e_status_code status; 5006 5007 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated); 5008 5009 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5010 5011 return status; 5012 } 5013 5014 /** 5015 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch. 5016 * @hw: pointer to the hw struct 5017 * @seid: defines the SEID of the switch for which the stats are requested 5018 * @vlan_id: the VLAN ID for which the statistics are requested 5019 * @stat_index: index of the statistics counters block assigned to this VLAN 5020 * @cmd_details: pointer to command details structure or NULL 5021 * 5022 * XL710 supports 128 smonVlanStats counters.This command is used to 5023 * allocate a set of smonVlanStats counters to a specific VLAN in a specific 5024 * switch. 5025 **/ 5026 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid, 5027 u16 vlan_id, u16 *stat_index, 5028 struct i40e_asq_cmd_details *cmd_details) 5029 { 5030 struct i40e_aq_desc desc; 5031 struct i40e_aqc_add_remove_statistics *cmd_resp = 5032 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw; 5033 enum i40e_status_code status; 5034 5035 if ((seid == 0) || (stat_index == NULL)) 5036 return I40E_ERR_PARAM; 5037 5038 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics); 5039 5040 cmd_resp->seid = CPU_TO_LE16(seid); 5041 cmd_resp->vlan = CPU_TO_LE16(vlan_id); 5042 5043 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5044 5045 if (!status && stat_index) 5046 *stat_index = LE16_TO_CPU(cmd_resp->stat_index); 5047 5048 return status; 5049 } 5050 5051 /** 5052 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch. 5053 * @hw: pointer to the hw struct 5054 * @seid: defines the SEID of the switch for which the stats are requested 5055 * @vlan_id: the VLAN ID for which the statistics are requested 5056 * @stat_index: index of the statistics counters block assigned to this VLAN 5057 * @cmd_details: pointer to command details structure or NULL 5058 * 5059 * XL710 supports 128 smonVlanStats counters.This command is used to 5060 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific 5061 * switch. 5062 **/ 5063 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid, 5064 u16 vlan_id, u16 stat_index, 5065 struct i40e_asq_cmd_details *cmd_details) 5066 { 5067 struct i40e_aq_desc desc; 5068 struct i40e_aqc_add_remove_statistics *cmd = 5069 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw; 5070 enum i40e_status_code status; 5071 5072 if (seid == 0) 5073 return I40E_ERR_PARAM; 5074 5075 i40e_fill_default_direct_cmd_desc(&desc, 5076 i40e_aqc_opc_remove_statistics); 5077 5078 cmd->seid = CPU_TO_LE16(seid); 5079 cmd->vlan = CPU_TO_LE16(vlan_id); 5080 cmd->stat_index = CPU_TO_LE16(stat_index); 5081 5082 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5083 5084 return status; 5085 } 5086 5087 /** 5088 * i40e_aq_set_port_parameters - set physical port parameters. 5089 * @hw: pointer to the hw struct 5090 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded 5091 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI 5092 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded 5093 * @double_vlan: if set double VLAN is enabled 5094 * @cmd_details: pointer to command details structure or NULL 5095 **/ 5096 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw, 5097 u16 bad_frame_vsi, bool save_bad_pac, 5098 bool pad_short_pac, bool double_vlan, 5099 struct i40e_asq_cmd_details *cmd_details) 5100 { 5101 struct i40e_aqc_set_port_parameters *cmd; 5102 enum i40e_status_code status; 5103 struct i40e_aq_desc desc; 5104 u16 command_flags = 0; 5105 5106 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw; 5107 5108 i40e_fill_default_direct_cmd_desc(&desc, 5109 i40e_aqc_opc_set_port_parameters); 5110 5111 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi); 5112 if (save_bad_pac) 5113 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS; 5114 if (pad_short_pac) 5115 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS; 5116 if (double_vlan) 5117 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA; 5118 cmd->command_flags = CPU_TO_LE16(command_flags); 5119 5120 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5121 5122 return status; 5123 } 5124 5125 /** 5126 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler 5127 * @hw: pointer to the hw struct 5128 * @seid: seid for the physical port/switching component/vsi 5129 * @buff: Indirect buffer to hold data parameters and response 5130 * @buff_size: Indirect buffer size 5131 * @opcode: Tx scheduler AQ command opcode 5132 * @cmd_details: pointer to command details structure or NULL 5133 * 5134 * Generic command handler for Tx scheduler AQ commands 5135 **/ 5136 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid, 5137 void *buff, u16 buff_size, 5138 enum i40e_admin_queue_opc opcode, 5139 struct i40e_asq_cmd_details *cmd_details) 5140 { 5141 struct i40e_aq_desc desc; 5142 struct i40e_aqc_tx_sched_ind *cmd = 5143 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; 5144 enum i40e_status_code status; 5145 bool cmd_param_flag = FALSE; 5146 5147 switch (opcode) { 5148 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit: 5149 case i40e_aqc_opc_configure_vsi_tc_bw: 5150 case i40e_aqc_opc_enable_switching_comp_ets: 5151 case i40e_aqc_opc_modify_switching_comp_ets: 5152 case i40e_aqc_opc_disable_switching_comp_ets: 5153 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit: 5154 case i40e_aqc_opc_configure_switching_comp_bw_config: 5155 cmd_param_flag = TRUE; 5156 break; 5157 case i40e_aqc_opc_query_vsi_bw_config: 5158 case i40e_aqc_opc_query_vsi_ets_sla_config: 5159 case i40e_aqc_opc_query_switching_comp_ets_config: 5160 case i40e_aqc_opc_query_port_ets_config: 5161 case i40e_aqc_opc_query_switching_comp_bw_config: 5162 cmd_param_flag = FALSE; 5163 break; 5164 default: 5165 return I40E_ERR_PARAM; 5166 } 5167 5168 i40e_fill_default_direct_cmd_desc(&desc, opcode); 5169 5170 /* Indirect command */ 5171 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 5172 if (cmd_param_flag) 5173 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 5174 if (buff_size > I40E_AQ_LARGE_BUF) 5175 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 5176 5177 desc.datalen = CPU_TO_LE16(buff_size); 5178 5179 cmd->vsi_seid = CPU_TO_LE16(seid); 5180 5181 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 5182 5183 return status; 5184 } 5185 5186 /** 5187 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit 5188 * @hw: pointer to the hw struct 5189 * @seid: VSI seid 5190 * @credit: BW limit credits (0 = disabled) 5191 * @max_credit: Max BW limit credits 5192 * @cmd_details: pointer to command details structure or NULL 5193 **/ 5194 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw, 5195 u16 seid, u16 credit, u8 max_credit, 5196 struct i40e_asq_cmd_details *cmd_details) 5197 { 5198 struct i40e_aq_desc desc; 5199 struct i40e_aqc_configure_vsi_bw_limit *cmd = 5200 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw; 5201 enum i40e_status_code status; 5202 5203 i40e_fill_default_direct_cmd_desc(&desc, 5204 i40e_aqc_opc_configure_vsi_bw_limit); 5205 5206 cmd->vsi_seid = CPU_TO_LE16(seid); 5207 cmd->credit = CPU_TO_LE16(credit); 5208 cmd->max_credit = max_credit; 5209 5210 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5211 5212 return status; 5213 } 5214 5215 /** 5216 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit 5217 * @hw: pointer to the hw struct 5218 * @seid: switching component seid 5219 * @credit: BW limit credits (0 = disabled) 5220 * @max_bw: Max BW limit credits 5221 * @cmd_details: pointer to command details structure or NULL 5222 **/ 5223 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw, 5224 u16 seid, u16 credit, u8 max_bw, 5225 struct i40e_asq_cmd_details *cmd_details) 5226 { 5227 struct i40e_aq_desc desc; 5228 struct i40e_aqc_configure_switching_comp_bw_limit *cmd = 5229 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw; 5230 enum i40e_status_code status; 5231 5232 i40e_fill_default_direct_cmd_desc(&desc, 5233 i40e_aqc_opc_configure_switching_comp_bw_limit); 5234 5235 cmd->seid = CPU_TO_LE16(seid); 5236 cmd->credit = CPU_TO_LE16(credit); 5237 cmd->max_bw = max_bw; 5238 5239 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5240 5241 return status; 5242 } 5243 5244 /** 5245 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC 5246 * @hw: pointer to the hw struct 5247 * @seid: VSI seid 5248 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits 5249 * @cmd_details: pointer to command details structure or NULL 5250 **/ 5251 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw, 5252 u16 seid, 5253 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data, 5254 struct i40e_asq_cmd_details *cmd_details) 5255 { 5256 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5257 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit, 5258 cmd_details); 5259 } 5260 5261 /** 5262 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC 5263 * @hw: pointer to the hw struct 5264 * @seid: VSI seid 5265 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits 5266 * @cmd_details: pointer to command details structure or NULL 5267 **/ 5268 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, 5269 u16 seid, 5270 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data, 5271 struct i40e_asq_cmd_details *cmd_details) 5272 { 5273 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5274 i40e_aqc_opc_configure_vsi_tc_bw, 5275 cmd_details); 5276 } 5277 5278 /** 5279 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC 5280 * @hw: pointer to the hw struct 5281 * @seid: seid of the switching component 5282 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits 5283 * @cmd_details: pointer to command details structure or NULL 5284 **/ 5285 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit( 5286 struct i40e_hw *hw, u16 seid, 5287 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data, 5288 struct i40e_asq_cmd_details *cmd_details) 5289 { 5290 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5291 i40e_aqc_opc_configure_switching_comp_ets_bw_limit, 5292 cmd_details); 5293 } 5294 5295 /** 5296 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration 5297 * @hw: pointer to the hw struct 5298 * @seid: seid of the VSI 5299 * @bw_data: Buffer to hold VSI BW configuration 5300 * @cmd_details: pointer to command details structure or NULL 5301 **/ 5302 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw, 5303 u16 seid, 5304 struct i40e_aqc_query_vsi_bw_config_resp *bw_data, 5305 struct i40e_asq_cmd_details *cmd_details) 5306 { 5307 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5308 i40e_aqc_opc_query_vsi_bw_config, 5309 cmd_details); 5310 } 5311 5312 /** 5313 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC 5314 * @hw: pointer to the hw struct 5315 * @seid: seid of the VSI 5316 * @bw_data: Buffer to hold VSI BW configuration per TC 5317 * @cmd_details: pointer to command details structure or NULL 5318 **/ 5319 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw, 5320 u16 seid, 5321 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data, 5322 struct i40e_asq_cmd_details *cmd_details) 5323 { 5324 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5325 i40e_aqc_opc_query_vsi_ets_sla_config, 5326 cmd_details); 5327 } 5328 5329 /** 5330 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC 5331 * @hw: pointer to the hw struct 5332 * @seid: seid of the switching component 5333 * @bw_data: Buffer to hold switching component's per TC BW config 5334 * @cmd_details: pointer to command details structure or NULL 5335 **/ 5336 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw, 5337 u16 seid, 5338 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data, 5339 struct i40e_asq_cmd_details *cmd_details) 5340 { 5341 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5342 i40e_aqc_opc_query_switching_comp_ets_config, 5343 cmd_details); 5344 } 5345 5346 /** 5347 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration 5348 * @hw: pointer to the hw struct 5349 * @seid: seid of the VSI or switching component connected to Physical Port 5350 * @bw_data: Buffer to hold current ETS configuration for the Physical Port 5351 * @cmd_details: pointer to command details structure or NULL 5352 **/ 5353 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw, 5354 u16 seid, 5355 struct i40e_aqc_query_port_ets_config_resp *bw_data, 5356 struct i40e_asq_cmd_details *cmd_details) 5357 { 5358 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5359 i40e_aqc_opc_query_port_ets_config, 5360 cmd_details); 5361 } 5362 5363 /** 5364 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration 5365 * @hw: pointer to the hw struct 5366 * @seid: seid of the switching component 5367 * @bw_data: Buffer to hold switching component's BW configuration 5368 * @cmd_details: pointer to command details structure or NULL 5369 **/ 5370 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw, 5371 u16 seid, 5372 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data, 5373 struct i40e_asq_cmd_details *cmd_details) 5374 { 5375 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5376 i40e_aqc_opc_query_switching_comp_bw_config, 5377 cmd_details); 5378 } 5379 5380 /** 5381 * i40e_validate_filter_settings 5382 * @hw: pointer to the hardware structure 5383 * @settings: Filter control settings 5384 * 5385 * Check and validate the filter control settings passed. 5386 * The function checks for the valid filter/context sizes being 5387 * passed for FCoE and PE. 5388 * 5389 * Returns I40E_SUCCESS if the values passed are valid and within 5390 * range else returns an error. 5391 **/ 5392 static enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw, 5393 struct i40e_filter_control_settings *settings) 5394 { 5395 u32 fcoe_cntx_size, fcoe_filt_size; 5396 u32 pe_cntx_size, pe_filt_size; 5397 u32 fcoe_fmax; 5398 5399 u32 val; 5400 5401 /* Validate FCoE settings passed */ 5402 switch (settings->fcoe_filt_num) { 5403 case I40E_HASH_FILTER_SIZE_1K: 5404 case I40E_HASH_FILTER_SIZE_2K: 5405 case I40E_HASH_FILTER_SIZE_4K: 5406 case I40E_HASH_FILTER_SIZE_8K: 5407 case I40E_HASH_FILTER_SIZE_16K: 5408 case I40E_HASH_FILTER_SIZE_32K: 5409 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 5410 fcoe_filt_size <<= (u32)settings->fcoe_filt_num; 5411 break; 5412 default: 5413 return I40E_ERR_PARAM; 5414 } 5415 5416 switch (settings->fcoe_cntx_num) { 5417 case I40E_DMA_CNTX_SIZE_512: 5418 case I40E_DMA_CNTX_SIZE_1K: 5419 case I40E_DMA_CNTX_SIZE_2K: 5420 case I40E_DMA_CNTX_SIZE_4K: 5421 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 5422 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num; 5423 break; 5424 default: 5425 return I40E_ERR_PARAM; 5426 } 5427 5428 /* Validate PE settings passed */ 5429 switch (settings->pe_filt_num) { 5430 case I40E_HASH_FILTER_SIZE_1K: 5431 case I40E_HASH_FILTER_SIZE_2K: 5432 case I40E_HASH_FILTER_SIZE_4K: 5433 case I40E_HASH_FILTER_SIZE_8K: 5434 case I40E_HASH_FILTER_SIZE_16K: 5435 case I40E_HASH_FILTER_SIZE_32K: 5436 case I40E_HASH_FILTER_SIZE_64K: 5437 case I40E_HASH_FILTER_SIZE_128K: 5438 case I40E_HASH_FILTER_SIZE_256K: 5439 case I40E_HASH_FILTER_SIZE_512K: 5440 case I40E_HASH_FILTER_SIZE_1M: 5441 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 5442 pe_filt_size <<= (u32)settings->pe_filt_num; 5443 break; 5444 default: 5445 return I40E_ERR_PARAM; 5446 } 5447 5448 switch (settings->pe_cntx_num) { 5449 case I40E_DMA_CNTX_SIZE_512: 5450 case I40E_DMA_CNTX_SIZE_1K: 5451 case I40E_DMA_CNTX_SIZE_2K: 5452 case I40E_DMA_CNTX_SIZE_4K: 5453 case I40E_DMA_CNTX_SIZE_8K: 5454 case I40E_DMA_CNTX_SIZE_16K: 5455 case I40E_DMA_CNTX_SIZE_32K: 5456 case I40E_DMA_CNTX_SIZE_64K: 5457 case I40E_DMA_CNTX_SIZE_128K: 5458 case I40E_DMA_CNTX_SIZE_256K: 5459 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 5460 pe_cntx_size <<= (u32)settings->pe_cntx_num; 5461 break; 5462 default: 5463 return I40E_ERR_PARAM; 5464 } 5465 5466 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */ 5467 val = rd32(hw, I40E_GLHMC_FCOEFMAX); 5468 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK) 5469 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT; 5470 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax) 5471 return I40E_ERR_INVALID_SIZE; 5472 5473 return I40E_SUCCESS; 5474 } 5475 5476 /** 5477 * i40e_set_filter_control 5478 * @hw: pointer to the hardware structure 5479 * @settings: Filter control settings 5480 * 5481 * Set the Queue Filters for PE/FCoE and enable filters required 5482 * for a single PF. It is expected that these settings are programmed 5483 * at the driver initialization time. 5484 **/ 5485 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw, 5486 struct i40e_filter_control_settings *settings) 5487 { 5488 enum i40e_status_code ret = I40E_SUCCESS; 5489 u32 hash_lut_size = 0; 5490 u32 val; 5491 5492 if (!settings) 5493 return I40E_ERR_PARAM; 5494 5495 /* Validate the input settings */ 5496 ret = i40e_validate_filter_settings(hw, settings); 5497 if (ret) 5498 return ret; 5499 5500 /* Read the PF Queue Filter control register */ 5501 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0); 5502 5503 /* Program required PE hash buckets for the PF */ 5504 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK; 5505 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) & 5506 I40E_PFQF_CTL_0_PEHSIZE_MASK; 5507 /* Program required PE contexts for the PF */ 5508 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK; 5509 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) & 5510 I40E_PFQF_CTL_0_PEDSIZE_MASK; 5511 5512 /* Program required FCoE hash buckets for the PF */ 5513 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 5514 val |= ((u32)settings->fcoe_filt_num << 5515 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) & 5516 I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 5517 /* Program required FCoE DDP contexts for the PF */ 5518 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 5519 val |= ((u32)settings->fcoe_cntx_num << 5520 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) & 5521 I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 5522 5523 /* Program Hash LUT size for the PF */ 5524 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 5525 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512) 5526 hash_lut_size = 1; 5527 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) & 5528 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 5529 5530 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */ 5531 if (settings->enable_fdir) 5532 val |= I40E_PFQF_CTL_0_FD_ENA_MASK; 5533 if (settings->enable_ethtype) 5534 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK; 5535 if (settings->enable_macvlan) 5536 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK; 5537 5538 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val); 5539 5540 return I40E_SUCCESS; 5541 } 5542 5543 /** 5544 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter 5545 * @hw: pointer to the hw struct 5546 * @mac_addr: MAC address to use in the filter 5547 * @ethtype: Ethertype to use in the filter 5548 * @flags: Flags that needs to be applied to the filter 5549 * @vsi_seid: seid of the control VSI 5550 * @queue: VSI queue number to send the packet to 5551 * @is_add: Add control packet filter if True else remove 5552 * @stats: Structure to hold information on control filter counts 5553 * @cmd_details: pointer to command details structure or NULL 5554 * 5555 * This command will Add or Remove control packet filter for a control VSI. 5556 * In return it will update the total number of perfect filter count in 5557 * the stats member. 5558 **/ 5559 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw, 5560 u8 *mac_addr, u16 ethtype, u16 flags, 5561 u16 vsi_seid, u16 queue, bool is_add, 5562 struct i40e_control_filter_stats *stats, 5563 struct i40e_asq_cmd_details *cmd_details) 5564 { 5565 struct i40e_aq_desc desc; 5566 struct i40e_aqc_add_remove_control_packet_filter *cmd = 5567 (struct i40e_aqc_add_remove_control_packet_filter *) 5568 &desc.params.raw; 5569 struct i40e_aqc_add_remove_control_packet_filter_completion *resp = 5570 (struct i40e_aqc_add_remove_control_packet_filter_completion *) 5571 &desc.params.raw; 5572 enum i40e_status_code status; 5573 5574 if (vsi_seid == 0) 5575 return I40E_ERR_PARAM; 5576 5577 if (is_add) { 5578 i40e_fill_default_direct_cmd_desc(&desc, 5579 i40e_aqc_opc_add_control_packet_filter); 5580 cmd->queue = CPU_TO_LE16(queue); 5581 } else { 5582 i40e_fill_default_direct_cmd_desc(&desc, 5583 i40e_aqc_opc_remove_control_packet_filter); 5584 } 5585 5586 if (mac_addr) 5587 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN, 5588 I40E_NONDMA_TO_NONDMA); 5589 5590 cmd->etype = CPU_TO_LE16(ethtype); 5591 cmd->flags = CPU_TO_LE16(flags); 5592 cmd->seid = CPU_TO_LE16(vsi_seid); 5593 5594 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5595 5596 if (!status && stats) { 5597 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used); 5598 stats->etype_used = LE16_TO_CPU(resp->etype_used); 5599 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free); 5600 stats->etype_free = LE16_TO_CPU(resp->etype_free); 5601 } 5602 5603 return status; 5604 } 5605 5606 /** 5607 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control 5608 * @hw: pointer to the hw struct 5609 * @seid: VSI seid to add ethertype filter from 5610 **/ 5611 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw, 5612 u16 seid) 5613 { 5614 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808 5615 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC | 5616 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP | 5617 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX; 5618 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE; 5619 enum i40e_status_code status; 5620 5621 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag, 5622 seid, 0, TRUE, NULL, 5623 NULL); 5624 if (status) 5625 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n"); 5626 } 5627 5628 /** 5629 * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue 5630 * @filters: list of cloud filters 5631 * @filter_count: length of list 5632 * 5633 * There's an issue in the device where the Geneve VNI layout needs 5634 * to be shifted 1 byte over from the VxLAN VNI 5635 **/ 5636 static void i40e_fix_up_geneve_vni( 5637 struct i40e_aqc_add_remove_cloud_filters_element_data *filters, 5638 u8 filter_count) 5639 { 5640 struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters; 5641 int i; 5642 5643 for (i = 0; i < filter_count; i++) { 5644 u16 tnl_type; 5645 u32 ti; 5646 5647 tnl_type = (LE16_TO_CPU(f[i].flags) & 5648 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >> 5649 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT; 5650 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) { 5651 ti = LE32_TO_CPU(f[i].tenant_id); 5652 f[i].tenant_id = CPU_TO_LE32(ti << 8); 5653 } 5654 } 5655 } 5656 5657 /** 5658 * i40e_aq_add_cloud_filters 5659 * @hw: pointer to the hardware structure 5660 * @seid: VSI seid to add cloud filters from 5661 * @filters: Buffer which contains the filters to be added 5662 * @filter_count: number of filters contained in the buffer 5663 * 5664 * Set the cloud filters for a given VSI. The contents of the 5665 * i40e_aqc_add_remove_cloud_filters_element_data are filled 5666 * in by the caller of the function. 5667 * 5668 **/ 5669 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw, 5670 u16 seid, 5671 struct i40e_aqc_add_remove_cloud_filters_element_data *filters, 5672 u8 filter_count) 5673 { 5674 struct i40e_aq_desc desc; 5675 struct i40e_aqc_add_remove_cloud_filters *cmd = 5676 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5677 enum i40e_status_code status; 5678 u16 buff_len; 5679 5680 i40e_fill_default_direct_cmd_desc(&desc, 5681 i40e_aqc_opc_add_cloud_filters); 5682 5683 buff_len = filter_count * sizeof(*filters); 5684 desc.datalen = CPU_TO_LE16(buff_len); 5685 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5686 cmd->num_filters = filter_count; 5687 cmd->seid = CPU_TO_LE16(seid); 5688 5689 i40e_fix_up_geneve_vni(filters, filter_count); 5690 5691 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5692 5693 return status; 5694 } 5695 5696 /** 5697 * i40e_aq_remove_cloud_filters 5698 * @hw: pointer to the hardware structure 5699 * @seid: VSI seid to remove cloud filters from 5700 * @filters: Buffer which contains the filters to be removed 5701 * @filter_count: number of filters contained in the buffer 5702 * 5703 * Remove the cloud filters for a given VSI. The contents of the 5704 * i40e_aqc_add_remove_cloud_filters_element_data are filled 5705 * in by the caller of the function. 5706 * 5707 **/ 5708 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw, 5709 u16 seid, 5710 struct i40e_aqc_add_remove_cloud_filters_element_data *filters, 5711 u8 filter_count) 5712 { 5713 struct i40e_aq_desc desc; 5714 struct i40e_aqc_add_remove_cloud_filters *cmd = 5715 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5716 enum i40e_status_code status; 5717 u16 buff_len; 5718 5719 i40e_fill_default_direct_cmd_desc(&desc, 5720 i40e_aqc_opc_remove_cloud_filters); 5721 5722 buff_len = filter_count * sizeof(*filters); 5723 desc.datalen = CPU_TO_LE16(buff_len); 5724 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5725 cmd->num_filters = filter_count; 5726 cmd->seid = CPU_TO_LE16(seid); 5727 5728 i40e_fix_up_geneve_vni(filters, filter_count); 5729 5730 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5731 5732 return status; 5733 } 5734 5735 /** 5736 * i40e_aq_alternate_write 5737 * @hw: pointer to the hardware structure 5738 * @reg_addr0: address of first dword to be read 5739 * @reg_val0: value to be written under 'reg_addr0' 5740 * @reg_addr1: address of second dword to be read 5741 * @reg_val1: value to be written under 'reg_addr1' 5742 * 5743 * Write one or two dwords to alternate structure. Fields are indicated 5744 * by 'reg_addr0' and 'reg_addr1' register numbers. 5745 * 5746 **/ 5747 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw, 5748 u32 reg_addr0, u32 reg_val0, 5749 u32 reg_addr1, u32 reg_val1) 5750 { 5751 struct i40e_aq_desc desc; 5752 struct i40e_aqc_alternate_write *cmd_resp = 5753 (struct i40e_aqc_alternate_write *)&desc.params.raw; 5754 enum i40e_status_code status; 5755 5756 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write); 5757 cmd_resp->address0 = CPU_TO_LE32(reg_addr0); 5758 cmd_resp->address1 = CPU_TO_LE32(reg_addr1); 5759 cmd_resp->data0 = CPU_TO_LE32(reg_val0); 5760 cmd_resp->data1 = CPU_TO_LE32(reg_val1); 5761 5762 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5763 5764 return status; 5765 } 5766 5767 /** 5768 * i40e_aq_alternate_write_indirect 5769 * @hw: pointer to the hardware structure 5770 * @addr: address of a first register to be modified 5771 * @dw_count: number of alternate structure fields to write 5772 * @buffer: pointer to the command buffer 5773 * 5774 * Write 'dw_count' dwords from 'buffer' to alternate structure 5775 * starting at 'addr'. 5776 * 5777 **/ 5778 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw, 5779 u32 addr, u32 dw_count, void *buffer) 5780 { 5781 struct i40e_aq_desc desc; 5782 struct i40e_aqc_alternate_ind_write *cmd_resp = 5783 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw; 5784 enum i40e_status_code status; 5785 5786 if (buffer == NULL) 5787 return I40E_ERR_PARAM; 5788 5789 /* Indirect command */ 5790 i40e_fill_default_direct_cmd_desc(&desc, 5791 i40e_aqc_opc_alternate_write_indirect); 5792 5793 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD); 5794 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 5795 if (dw_count > (I40E_AQ_LARGE_BUF/4)) 5796 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 5797 5798 cmd_resp->address = CPU_TO_LE32(addr); 5799 cmd_resp->length = CPU_TO_LE32(dw_count); 5800 5801 status = i40e_asq_send_command(hw, &desc, buffer, 5802 I40E_LO_DWORD(4*dw_count), NULL); 5803 5804 return status; 5805 } 5806 5807 /** 5808 * i40e_aq_alternate_read 5809 * @hw: pointer to the hardware structure 5810 * @reg_addr0: address of first dword to be read 5811 * @reg_val0: pointer for data read from 'reg_addr0' 5812 * @reg_addr1: address of second dword to be read 5813 * @reg_val1: pointer for data read from 'reg_addr1' 5814 * 5815 * Read one or two dwords from alternate structure. Fields are indicated 5816 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer 5817 * is not passed then only register at 'reg_addr0' is read. 5818 * 5819 **/ 5820 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw, 5821 u32 reg_addr0, u32 *reg_val0, 5822 u32 reg_addr1, u32 *reg_val1) 5823 { 5824 struct i40e_aq_desc desc; 5825 struct i40e_aqc_alternate_write *cmd_resp = 5826 (struct i40e_aqc_alternate_write *)&desc.params.raw; 5827 enum i40e_status_code status; 5828 5829 if (reg_val0 == NULL) 5830 return I40E_ERR_PARAM; 5831 5832 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read); 5833 cmd_resp->address0 = CPU_TO_LE32(reg_addr0); 5834 cmd_resp->address1 = CPU_TO_LE32(reg_addr1); 5835 5836 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5837 5838 if (status == I40E_SUCCESS) { 5839 *reg_val0 = LE32_TO_CPU(cmd_resp->data0); 5840 5841 if (reg_val1 != NULL) 5842 *reg_val1 = LE32_TO_CPU(cmd_resp->data1); 5843 } 5844 5845 return status; 5846 } 5847 5848 /** 5849 * i40e_aq_alternate_read_indirect 5850 * @hw: pointer to the hardware structure 5851 * @addr: address of the alternate structure field 5852 * @dw_count: number of alternate structure fields to read 5853 * @buffer: pointer to the command buffer 5854 * 5855 * Read 'dw_count' dwords from alternate structure starting at 'addr' and 5856 * place them in 'buffer'. The buffer should be allocated by caller. 5857 * 5858 **/ 5859 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw, 5860 u32 addr, u32 dw_count, void *buffer) 5861 { 5862 struct i40e_aq_desc desc; 5863 struct i40e_aqc_alternate_ind_write *cmd_resp = 5864 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw; 5865 enum i40e_status_code status; 5866 5867 if (buffer == NULL) 5868 return I40E_ERR_PARAM; 5869 5870 /* Indirect command */ 5871 i40e_fill_default_direct_cmd_desc(&desc, 5872 i40e_aqc_opc_alternate_read_indirect); 5873 5874 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD); 5875 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 5876 if (dw_count > (I40E_AQ_LARGE_BUF/4)) 5877 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 5878 5879 cmd_resp->address = CPU_TO_LE32(addr); 5880 cmd_resp->length = CPU_TO_LE32(dw_count); 5881 5882 status = i40e_asq_send_command(hw, &desc, buffer, 5883 I40E_LO_DWORD(4*dw_count), NULL); 5884 5885 return status; 5886 } 5887 5888 /** 5889 * i40e_aq_alternate_clear 5890 * @hw: pointer to the HW structure. 5891 * 5892 * Clear the alternate structures of the port from which the function 5893 * is called. 5894 * 5895 **/ 5896 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw) 5897 { 5898 struct i40e_aq_desc desc; 5899 enum i40e_status_code status; 5900 5901 i40e_fill_default_direct_cmd_desc(&desc, 5902 i40e_aqc_opc_alternate_clear_port); 5903 5904 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5905 5906 return status; 5907 } 5908 5909 /** 5910 * i40e_aq_alternate_write_done 5911 * @hw: pointer to the HW structure. 5912 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS 5913 * @reset_needed: indicates the SW should trigger GLOBAL reset 5914 * 5915 * Indicates to the FW that alternate structures have been changed. 5916 * 5917 **/ 5918 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw, 5919 u8 bios_mode, bool *reset_needed) 5920 { 5921 struct i40e_aq_desc desc; 5922 struct i40e_aqc_alternate_write_done *cmd = 5923 (struct i40e_aqc_alternate_write_done *)&desc.params.raw; 5924 enum i40e_status_code status; 5925 5926 if (reset_needed == NULL) 5927 return I40E_ERR_PARAM; 5928 5929 i40e_fill_default_direct_cmd_desc(&desc, 5930 i40e_aqc_opc_alternate_write_done); 5931 5932 cmd->cmd_flags = CPU_TO_LE16(bios_mode); 5933 5934 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5935 if (!status && reset_needed) 5936 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) & 5937 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0); 5938 5939 return status; 5940 } 5941 5942 /** 5943 * i40e_aq_set_oem_mode 5944 * @hw: pointer to the HW structure. 5945 * @oem_mode: the OEM mode to be used 5946 * 5947 * Sets the device to a specific operating mode. Currently the only supported 5948 * mode is no_clp, which causes FW to refrain from using Alternate RAM. 5949 * 5950 **/ 5951 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw, 5952 u8 oem_mode) 5953 { 5954 struct i40e_aq_desc desc; 5955 struct i40e_aqc_alternate_write_done *cmd = 5956 (struct i40e_aqc_alternate_write_done *)&desc.params.raw; 5957 enum i40e_status_code status; 5958 5959 i40e_fill_default_direct_cmd_desc(&desc, 5960 i40e_aqc_opc_alternate_set_mode); 5961 5962 cmd->cmd_flags = CPU_TO_LE16(oem_mode); 5963 5964 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5965 5966 return status; 5967 } 5968 5969 /** 5970 * i40e_aq_resume_port_tx 5971 * @hw: pointer to the hardware structure 5972 * @cmd_details: pointer to command details structure or NULL 5973 * 5974 * Resume port's Tx traffic 5975 **/ 5976 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw, 5977 struct i40e_asq_cmd_details *cmd_details) 5978 { 5979 struct i40e_aq_desc desc; 5980 enum i40e_status_code status; 5981 5982 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx); 5983 5984 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5985 5986 return status; 5987 } 5988 5989 /** 5990 * i40e_set_pci_config_data - store PCI bus info 5991 * @hw: pointer to hardware structure 5992 * @link_status: the link status word from PCI config space 5993 * 5994 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure 5995 **/ 5996 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status) 5997 { 5998 hw->bus.type = i40e_bus_type_pci_express; 5999 6000 switch (link_status & I40E_PCI_LINK_WIDTH) { 6001 case I40E_PCI_LINK_WIDTH_1: 6002 hw->bus.width = i40e_bus_width_pcie_x1; 6003 break; 6004 case I40E_PCI_LINK_WIDTH_2: 6005 hw->bus.width = i40e_bus_width_pcie_x2; 6006 break; 6007 case I40E_PCI_LINK_WIDTH_4: 6008 hw->bus.width = i40e_bus_width_pcie_x4; 6009 break; 6010 case I40E_PCI_LINK_WIDTH_8: 6011 hw->bus.width = i40e_bus_width_pcie_x8; 6012 break; 6013 default: 6014 hw->bus.width = i40e_bus_width_unknown; 6015 break; 6016 } 6017 6018 switch (link_status & I40E_PCI_LINK_SPEED) { 6019 case I40E_PCI_LINK_SPEED_2500: 6020 hw->bus.speed = i40e_bus_speed_2500; 6021 break; 6022 case I40E_PCI_LINK_SPEED_5000: 6023 hw->bus.speed = i40e_bus_speed_5000; 6024 break; 6025 case I40E_PCI_LINK_SPEED_8000: 6026 hw->bus.speed = i40e_bus_speed_8000; 6027 break; 6028 default: 6029 hw->bus.speed = i40e_bus_speed_unknown; 6030 break; 6031 } 6032 } 6033 6034 /** 6035 * i40e_aq_debug_dump 6036 * @hw: pointer to the hardware structure 6037 * @cluster_id: specific cluster to dump 6038 * @table_id: table id within cluster 6039 * @start_index: index of line in the block to read 6040 * @buff_size: dump buffer size 6041 * @buff: dump buffer 6042 * @ret_buff_size: actual buffer size returned 6043 * @ret_next_table: next block to read 6044 * @ret_next_index: next index to read 6045 * @cmd_details: pointer to command details structure or NULL 6046 * 6047 * Dump internal FW/HW data for debug purposes. 6048 * 6049 **/ 6050 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id, 6051 u8 table_id, u32 start_index, u16 buff_size, 6052 void *buff, u16 *ret_buff_size, 6053 u8 *ret_next_table, u32 *ret_next_index, 6054 struct i40e_asq_cmd_details *cmd_details) 6055 { 6056 struct i40e_aq_desc desc; 6057 struct i40e_aqc_debug_dump_internals *cmd = 6058 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 6059 struct i40e_aqc_debug_dump_internals *resp = 6060 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 6061 enum i40e_status_code status; 6062 6063 if (buff_size == 0 || !buff) 6064 return I40E_ERR_PARAM; 6065 6066 i40e_fill_default_direct_cmd_desc(&desc, 6067 i40e_aqc_opc_debug_dump_internals); 6068 /* Indirect Command */ 6069 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 6070 if (buff_size > I40E_AQ_LARGE_BUF) 6071 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 6072 6073 cmd->cluster_id = cluster_id; 6074 cmd->table_id = table_id; 6075 cmd->idx = CPU_TO_LE32(start_index); 6076 6077 desc.datalen = CPU_TO_LE16(buff_size); 6078 6079 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 6080 if (!status) { 6081 if (ret_buff_size != NULL) 6082 *ret_buff_size = LE16_TO_CPU(desc.datalen); 6083 if (ret_next_table != NULL) 6084 *ret_next_table = resp->table_id; 6085 if (ret_next_index != NULL) 6086 *ret_next_index = LE32_TO_CPU(resp->idx); 6087 } 6088 6089 return status; 6090 } 6091 6092 /** 6093 * i40e_read_bw_from_alt_ram 6094 * @hw: pointer to the hardware structure 6095 * @max_bw: pointer for max_bw read 6096 * @min_bw: pointer for min_bw read 6097 * @min_valid: pointer for bool that is TRUE if min_bw is a valid value 6098 * @max_valid: pointer for bool that is TRUE if max_bw is a valid value 6099 * 6100 * Read bw from the alternate ram for the given pf 6101 **/ 6102 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw, 6103 u32 *max_bw, u32 *min_bw, 6104 bool *min_valid, bool *max_valid) 6105 { 6106 enum i40e_status_code status; 6107 u32 max_bw_addr, min_bw_addr; 6108 6109 /* Calculate the address of the min/max bw registers */ 6110 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 6111 I40E_ALT_STRUCT_MAX_BW_OFFSET + 6112 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 6113 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 6114 I40E_ALT_STRUCT_MIN_BW_OFFSET + 6115 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 6116 6117 /* Read the bandwidths from alt ram */ 6118 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw, 6119 min_bw_addr, min_bw); 6120 6121 if (*min_bw & I40E_ALT_BW_VALID_MASK) 6122 *min_valid = TRUE; 6123 else 6124 *min_valid = FALSE; 6125 6126 if (*max_bw & I40E_ALT_BW_VALID_MASK) 6127 *max_valid = TRUE; 6128 else 6129 *max_valid = FALSE; 6130 6131 return status; 6132 } 6133 6134 /** 6135 * i40e_aq_configure_partition_bw 6136 * @hw: pointer to the hardware structure 6137 * @bw_data: Buffer holding valid pfs and bw limits 6138 * @cmd_details: pointer to command details 6139 * 6140 * Configure partitions guaranteed/max bw 6141 **/ 6142 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw, 6143 struct i40e_aqc_configure_partition_bw_data *bw_data, 6144 struct i40e_asq_cmd_details *cmd_details) 6145 { 6146 enum i40e_status_code status; 6147 struct i40e_aq_desc desc; 6148 u16 bwd_size = sizeof(*bw_data); 6149 6150 i40e_fill_default_direct_cmd_desc(&desc, 6151 i40e_aqc_opc_configure_partition_bw); 6152 6153 /* Indirect command */ 6154 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 6155 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 6156 6157 desc.datalen = CPU_TO_LE16(bwd_size); 6158 6159 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details); 6160 6161 return status; 6162 } 6163 6164 /** 6165 * i40e_read_phy_register_clause22 6166 * @hw: pointer to the HW structure 6167 * @reg: register address in the page 6168 * @phy_addr: PHY address on MDIO interface 6169 * @value: PHY register value 6170 * 6171 * Reads specified PHY register value 6172 **/ 6173 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw, 6174 u16 reg, u8 phy_addr, u16 *value) 6175 { 6176 enum i40e_status_code status = I40E_ERR_TIMEOUT; 6177 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6178 u32 command = 0; 6179 u16 retry = 1000; 6180 6181 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6182 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6183 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) | 6184 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 6185 (I40E_GLGEN_MSCA_MDICMD_MASK); 6186 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6187 do { 6188 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6189 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6190 status = I40E_SUCCESS; 6191 break; 6192 } 6193 i40e_usec_delay(10); 6194 retry--; 6195 } while (retry); 6196 6197 if (status) { 6198 i40e_debug(hw, I40E_DEBUG_PHY, 6199 "PHY: Can't write command to external PHY.\n"); 6200 } else { 6201 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 6202 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 6203 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 6204 } 6205 6206 return status; 6207 } 6208 6209 /** 6210 * i40e_write_phy_register_clause22 6211 * @hw: pointer to the HW structure 6212 * @reg: register address in the page 6213 * @phy_addr: PHY address on MDIO interface 6214 * @value: PHY register value 6215 * 6216 * Writes specified PHY register value 6217 **/ 6218 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw, 6219 u16 reg, u8 phy_addr, u16 value) 6220 { 6221 enum i40e_status_code status = I40E_ERR_TIMEOUT; 6222 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6223 u32 command = 0; 6224 u16 retry = 1000; 6225 6226 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 6227 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 6228 6229 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6230 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6231 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) | 6232 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 6233 (I40E_GLGEN_MSCA_MDICMD_MASK); 6234 6235 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6236 do { 6237 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6238 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6239 status = I40E_SUCCESS; 6240 break; 6241 } 6242 i40e_usec_delay(10); 6243 retry--; 6244 } while (retry); 6245 6246 return status; 6247 } 6248 6249 /** 6250 * i40e_read_phy_register_clause45 6251 * @hw: pointer to the HW structure 6252 * @page: registers page number 6253 * @reg: register address in the page 6254 * @phy_addr: PHY address on MDIO interface 6255 * @value: PHY register value 6256 * 6257 * Reads specified PHY register value 6258 **/ 6259 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw, 6260 u8 page, u16 reg, u8 phy_addr, u16 *value) 6261 { 6262 enum i40e_status_code status = I40E_ERR_TIMEOUT; 6263 u32 command = 0; 6264 u16 retry = 1000; 6265 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6266 6267 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 6268 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6269 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6270 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 6271 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 6272 (I40E_GLGEN_MSCA_MDICMD_MASK) | 6273 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 6274 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6275 do { 6276 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6277 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6278 status = I40E_SUCCESS; 6279 break; 6280 } 6281 i40e_usec_delay(10); 6282 retry--; 6283 } while (retry); 6284 6285 if (status) { 6286 i40e_debug(hw, I40E_DEBUG_PHY, 6287 "PHY: Can't write command to external PHY.\n"); 6288 goto phy_read_end; 6289 } 6290 6291 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6292 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6293 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) | 6294 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 6295 (I40E_GLGEN_MSCA_MDICMD_MASK) | 6296 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 6297 status = I40E_ERR_TIMEOUT; 6298 retry = 1000; 6299 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6300 do { 6301 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6302 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6303 status = I40E_SUCCESS; 6304 break; 6305 } 6306 i40e_usec_delay(10); 6307 retry--; 6308 } while (retry); 6309 6310 if (!status) { 6311 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 6312 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 6313 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 6314 } else { 6315 i40e_debug(hw, I40E_DEBUG_PHY, 6316 "PHY: Can't read register value from external PHY.\n"); 6317 } 6318 6319 phy_read_end: 6320 return status; 6321 } 6322 6323 /** 6324 * i40e_write_phy_register_clause45 6325 * @hw: pointer to the HW structure 6326 * @page: registers page number 6327 * @reg: register address in the page 6328 * @phy_addr: PHY address on MDIO interface 6329 * @value: PHY register value 6330 * 6331 * Writes value to specified PHY register 6332 **/ 6333 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw, 6334 u8 page, u16 reg, u8 phy_addr, u16 value) 6335 { 6336 enum i40e_status_code status = I40E_ERR_TIMEOUT; 6337 u32 command = 0; 6338 u16 retry = 1000; 6339 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6340 6341 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 6342 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6343 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6344 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 6345 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 6346 (I40E_GLGEN_MSCA_MDICMD_MASK) | 6347 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 6348 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6349 do { 6350 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6351 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6352 status = I40E_SUCCESS; 6353 break; 6354 } 6355 i40e_usec_delay(10); 6356 retry--; 6357 } while (retry); 6358 if (status) { 6359 i40e_debug(hw, I40E_DEBUG_PHY, 6360 "PHY: Can't write command to external PHY.\n"); 6361 goto phy_write_end; 6362 } 6363 6364 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 6365 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 6366 6367 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6368 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6369 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) | 6370 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 6371 (I40E_GLGEN_MSCA_MDICMD_MASK) | 6372 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 6373 status = I40E_ERR_TIMEOUT; 6374 retry = 1000; 6375 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6376 do { 6377 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6378 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6379 status = I40E_SUCCESS; 6380 break; 6381 } 6382 i40e_usec_delay(10); 6383 retry--; 6384 } while (retry); 6385 6386 phy_write_end: 6387 return status; 6388 } 6389 6390 /** 6391 * i40e_write_phy_register 6392 * @hw: pointer to the HW structure 6393 * @page: registers page number 6394 * @reg: register address in the page 6395 * @phy_addr: PHY address on MDIO interface 6396 * @value: PHY register value 6397 * 6398 * Writes value to specified PHY register 6399 **/ 6400 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw, 6401 u8 page, u16 reg, u8 phy_addr, u16 value) 6402 { 6403 enum i40e_status_code status; 6404 6405 switch (hw->device_id) { 6406 case I40E_DEV_ID_1G_BASE_T_X722: 6407 status = i40e_write_phy_register_clause22(hw, 6408 reg, phy_addr, value); 6409 break; 6410 case I40E_DEV_ID_10G_BASE_T: 6411 case I40E_DEV_ID_10G_BASE_T4: 6412 case I40E_DEV_ID_10G_BASE_T_X722: 6413 case I40E_DEV_ID_25G_B: 6414 case I40E_DEV_ID_25G_SFP28: 6415 status = i40e_write_phy_register_clause45(hw, 6416 page, reg, phy_addr, value); 6417 break; 6418 default: 6419 status = I40E_ERR_UNKNOWN_PHY; 6420 break; 6421 } 6422 6423 return status; 6424 } 6425 6426 /** 6427 * i40e_read_phy_register 6428 * @hw: pointer to the HW structure 6429 * @page: registers page number 6430 * @reg: register address in the page 6431 * @phy_addr: PHY address on MDIO interface 6432 * @value: PHY register value 6433 * 6434 * Reads specified PHY register value 6435 **/ 6436 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw, 6437 u8 page, u16 reg, u8 phy_addr, u16 *value) 6438 { 6439 enum i40e_status_code status; 6440 6441 switch (hw->device_id) { 6442 case I40E_DEV_ID_1G_BASE_T_X722: 6443 status = i40e_read_phy_register_clause22(hw, reg, phy_addr, 6444 value); 6445 break; 6446 case I40E_DEV_ID_10G_BASE_T: 6447 case I40E_DEV_ID_10G_BASE_T4: 6448 case I40E_DEV_ID_10G_BASE_T_X722: 6449 case I40E_DEV_ID_25G_B: 6450 case I40E_DEV_ID_25G_SFP28: 6451 status = i40e_read_phy_register_clause45(hw, page, reg, 6452 phy_addr, value); 6453 break; 6454 default: 6455 status = I40E_ERR_UNKNOWN_PHY; 6456 break; 6457 } 6458 6459 return status; 6460 } 6461 6462 /** 6463 * i40e_get_phy_address 6464 * @hw: pointer to the HW structure 6465 * @dev_num: PHY port num that address we want 6466 * 6467 * Gets PHY address for current port 6468 **/ 6469 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num) 6470 { 6471 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6472 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num)); 6473 6474 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f; 6475 } 6476 6477 /** 6478 * i40e_blink_phy_led 6479 * @hw: pointer to the HW structure 6480 * @time: time how long led will blinks in secs 6481 * @interval: gap between LED on and off in msecs 6482 * 6483 * Blinks PHY link LED 6484 **/ 6485 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw, 6486 u32 time, u32 interval) 6487 { 6488 enum i40e_status_code status = I40E_SUCCESS; 6489 u32 i; 6490 u16 led_ctl = 0; 6491 u16 gpio_led_port; 6492 u16 led_reg; 6493 u16 led_addr = I40E_PHY_LED_PROV_REG_1; 6494 u8 phy_addr = 0; 6495 u8 port_num; 6496 6497 i = rd32(hw, I40E_PFGEN_PORTNUM); 6498 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 6499 phy_addr = i40e_get_phy_address(hw, port_num); 6500 6501 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 6502 led_addr++) { 6503 status = i40e_read_phy_register_clause45(hw, 6504 I40E_PHY_COM_REG_PAGE, 6505 led_addr, phy_addr, 6506 &led_reg); 6507 if (status) 6508 goto phy_blinking_end; 6509 led_ctl = led_reg; 6510 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 6511 led_reg = 0; 6512 status = i40e_write_phy_register_clause45(hw, 6513 I40E_PHY_COM_REG_PAGE, 6514 led_addr, phy_addr, 6515 led_reg); 6516 if (status) 6517 goto phy_blinking_end; 6518 break; 6519 } 6520 } 6521 6522 if (time > 0 && interval > 0) { 6523 for (i = 0; i < time * 1000; i += interval) { 6524 status = i40e_read_phy_register_clause45(hw, 6525 I40E_PHY_COM_REG_PAGE, 6526 led_addr, phy_addr, &led_reg); 6527 if (status) 6528 goto restore_config; 6529 if (led_reg & I40E_PHY_LED_MANUAL_ON) 6530 led_reg = 0; 6531 else 6532 led_reg = I40E_PHY_LED_MANUAL_ON; 6533 status = i40e_write_phy_register_clause45(hw, 6534 I40E_PHY_COM_REG_PAGE, 6535 led_addr, phy_addr, led_reg); 6536 if (status) 6537 goto restore_config; 6538 i40e_msec_delay(interval); 6539 } 6540 } 6541 6542 restore_config: 6543 status = i40e_write_phy_register_clause45(hw, 6544 I40E_PHY_COM_REG_PAGE, 6545 led_addr, phy_addr, led_ctl); 6546 6547 phy_blinking_end: 6548 return status; 6549 } 6550 6551 /** 6552 * i40e_led_get_reg - read LED register 6553 * @hw: pointer to the HW structure 6554 * @led_addr: LED register address 6555 * @reg_val: read register value 6556 **/ 6557 static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr, 6558 u32 *reg_val) 6559 { 6560 enum i40e_status_code status; 6561 u8 phy_addr = 0; 6562 6563 *reg_val = 0; 6564 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 6565 status = i40e_aq_get_phy_register(hw, 6566 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 6567 I40E_PHY_COM_REG_PAGE, 6568 I40E_PHY_LED_PROV_REG_1, 6569 reg_val, NULL); 6570 } else { 6571 phy_addr = i40e_get_phy_address(hw, hw->port); 6572 status = i40e_read_phy_register_clause45(hw, 6573 I40E_PHY_COM_REG_PAGE, 6574 led_addr, phy_addr, 6575 (u16 *)reg_val); 6576 } 6577 return status; 6578 } 6579 6580 /** 6581 * i40e_led_set_reg - write LED register 6582 * @hw: pointer to the HW structure 6583 * @led_addr: LED register address 6584 * @reg_val: register value to write 6585 **/ 6586 static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr, 6587 u32 reg_val) 6588 { 6589 enum i40e_status_code status; 6590 u8 phy_addr = 0; 6591 6592 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 6593 status = i40e_aq_set_phy_register(hw, 6594 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 6595 I40E_PHY_COM_REG_PAGE, 6596 I40E_PHY_LED_PROV_REG_1, 6597 reg_val, NULL); 6598 } else { 6599 phy_addr = i40e_get_phy_address(hw, hw->port); 6600 status = i40e_write_phy_register_clause45(hw, 6601 I40E_PHY_COM_REG_PAGE, 6602 led_addr, phy_addr, 6603 (u16)reg_val); 6604 } 6605 6606 return status; 6607 } 6608 6609 /** 6610 * i40e_led_get_phy - return current on/off mode 6611 * @hw: pointer to the hw struct 6612 * @led_addr: address of led register to use 6613 * @val: original value of register to use 6614 * 6615 **/ 6616 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr, 6617 u16 *val) 6618 { 6619 enum i40e_status_code status = I40E_SUCCESS; 6620 u16 gpio_led_port; 6621 u32 reg_val_aq; 6622 u16 temp_addr; 6623 u8 phy_addr = 0; 6624 u16 reg_val; 6625 6626 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 6627 status = i40e_aq_get_phy_register(hw, 6628 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 6629 I40E_PHY_COM_REG_PAGE, 6630 I40E_PHY_LED_PROV_REG_1, 6631 ®_val_aq, NULL); 6632 if (status == I40E_SUCCESS) 6633 *val = (u16)reg_val_aq; 6634 return status; 6635 } 6636 temp_addr = I40E_PHY_LED_PROV_REG_1; 6637 phy_addr = i40e_get_phy_address(hw, hw->port); 6638 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 6639 temp_addr++) { 6640 status = i40e_read_phy_register_clause45(hw, 6641 I40E_PHY_COM_REG_PAGE, 6642 temp_addr, phy_addr, 6643 ®_val); 6644 if (status) 6645 return status; 6646 *val = reg_val; 6647 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) { 6648 *led_addr = temp_addr; 6649 break; 6650 } 6651 } 6652 return status; 6653 } 6654 6655 /** 6656 * i40e_led_set_phy 6657 * @hw: pointer to the HW structure 6658 * @on: TRUE or FALSE 6659 * @led_addr: address of led register to use 6660 * @mode: original val plus bit for set or ignore 6661 * 6662 * Set led's on or off when controlled by the PHY 6663 * 6664 **/ 6665 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on, 6666 u16 led_addr, u32 mode) 6667 { 6668 enum i40e_status_code status = I40E_SUCCESS; 6669 u32 led_ctl = 0; 6670 u32 led_reg = 0; 6671 6672 status = i40e_led_get_reg(hw, led_addr, &led_reg); 6673 if (status) 6674 return status; 6675 led_ctl = led_reg; 6676 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 6677 led_reg = 0; 6678 status = i40e_led_set_reg(hw, led_addr, led_reg); 6679 if (status) 6680 return status; 6681 } 6682 status = i40e_led_get_reg(hw, led_addr, &led_reg); 6683 if (status) 6684 goto restore_config; 6685 if (on) 6686 led_reg = I40E_PHY_LED_MANUAL_ON; 6687 else 6688 led_reg = 0; 6689 status = i40e_led_set_reg(hw, led_addr, led_reg); 6690 if (status) 6691 goto restore_config; 6692 if (mode & I40E_PHY_LED_MODE_ORIG) { 6693 led_ctl = (mode & I40E_PHY_LED_MODE_MASK); 6694 status = i40e_led_set_reg(hw, led_addr, led_ctl); 6695 } 6696 return status; 6697 6698 restore_config: 6699 status = i40e_led_set_reg(hw, led_addr, led_ctl); 6700 return status; 6701 } 6702 6703 /** 6704 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register 6705 * @hw: pointer to the hw struct 6706 * @reg_addr: register address 6707 * @reg_val: ptr to register value 6708 * @cmd_details: pointer to command details structure or NULL 6709 * 6710 * Use the firmware to read the Rx control register, 6711 * especially useful if the Rx unit is under heavy pressure 6712 **/ 6713 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw, 6714 u32 reg_addr, u32 *reg_val, 6715 struct i40e_asq_cmd_details *cmd_details) 6716 { 6717 struct i40e_aq_desc desc; 6718 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp = 6719 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 6720 enum i40e_status_code status; 6721 6722 if (reg_val == NULL) 6723 return I40E_ERR_PARAM; 6724 6725 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read); 6726 6727 cmd_resp->address = CPU_TO_LE32(reg_addr); 6728 6729 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 6730 6731 if (status == I40E_SUCCESS) 6732 *reg_val = LE32_TO_CPU(cmd_resp->value); 6733 6734 return status; 6735 } 6736 6737 /** 6738 * i40e_read_rx_ctl - read from an Rx control register 6739 * @hw: pointer to the hw struct 6740 * @reg_addr: register address 6741 **/ 6742 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr) 6743 { 6744 enum i40e_status_code status = I40E_SUCCESS; 6745 bool use_register; 6746 int retry = 5; 6747 u32 val = 0; 6748 6749 use_register = (((hw->aq.api_maj_ver == 1) && 6750 (hw->aq.api_min_ver < 5)) || 6751 (hw->mac.type == I40E_MAC_X722)); 6752 if (!use_register) { 6753 do_retry: 6754 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL); 6755 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 6756 i40e_msec_delay(1); 6757 retry--; 6758 goto do_retry; 6759 } 6760 } 6761 6762 /* if the AQ access failed, try the old-fashioned way */ 6763 if (status || use_register) 6764 val = rd32(hw, reg_addr); 6765 6766 return val; 6767 } 6768 6769 /** 6770 * i40e_aq_rx_ctl_write_register 6771 * @hw: pointer to the hw struct 6772 * @reg_addr: register address 6773 * @reg_val: register value 6774 * @cmd_details: pointer to command details structure or NULL 6775 * 6776 * Use the firmware to write to an Rx control register, 6777 * especially useful if the Rx unit is under heavy pressure 6778 **/ 6779 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw, 6780 u32 reg_addr, u32 reg_val, 6781 struct i40e_asq_cmd_details *cmd_details) 6782 { 6783 struct i40e_aq_desc desc; 6784 struct i40e_aqc_rx_ctl_reg_read_write *cmd = 6785 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 6786 enum i40e_status_code status; 6787 6788 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write); 6789 6790 cmd->address = CPU_TO_LE32(reg_addr); 6791 cmd->value = CPU_TO_LE32(reg_val); 6792 6793 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 6794 6795 return status; 6796 } 6797 6798 /** 6799 * i40e_write_rx_ctl - write to an Rx control register 6800 * @hw: pointer to the hw struct 6801 * @reg_addr: register address 6802 * @reg_val: register value 6803 **/ 6804 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val) 6805 { 6806 enum i40e_status_code status = I40E_SUCCESS; 6807 bool use_register; 6808 int retry = 5; 6809 6810 use_register = (((hw->aq.api_maj_ver == 1) && 6811 (hw->aq.api_min_ver < 5)) || 6812 (hw->mac.type == I40E_MAC_X722)); 6813 if (!use_register) { 6814 do_retry: 6815 status = i40e_aq_rx_ctl_write_register(hw, reg_addr, 6816 reg_val, NULL); 6817 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 6818 i40e_msec_delay(1); 6819 retry--; 6820 goto do_retry; 6821 } 6822 } 6823 6824 /* if the AQ access failed, try the old-fashioned way */ 6825 if (status || use_register) 6826 wr32(hw, reg_addr, reg_val); 6827 } 6828 6829 /** 6830 * i40e_aq_set_phy_register 6831 * @hw: pointer to the hw struct 6832 * @phy_select: select which phy should be accessed 6833 * @dev_addr: PHY device address 6834 * @reg_addr: PHY register address 6835 * @reg_val: new register value 6836 * @cmd_details: pointer to command details structure or NULL 6837 * 6838 * Write the external PHY register. 6839 **/ 6840 enum i40e_status_code i40e_aq_set_phy_register(struct i40e_hw *hw, 6841 u8 phy_select, u8 dev_addr, 6842 u32 reg_addr, u32 reg_val, 6843 struct i40e_asq_cmd_details *cmd_details) 6844 { 6845 struct i40e_aq_desc desc; 6846 struct i40e_aqc_phy_register_access *cmd = 6847 (struct i40e_aqc_phy_register_access *)&desc.params.raw; 6848 enum i40e_status_code status; 6849 6850 i40e_fill_default_direct_cmd_desc(&desc, 6851 i40e_aqc_opc_set_phy_register); 6852 6853 cmd->phy_interface = phy_select; 6854 cmd->dev_addres = dev_addr; 6855 cmd->reg_address = CPU_TO_LE32(reg_addr); 6856 cmd->reg_value = CPU_TO_LE32(reg_val); 6857 6858 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 6859 6860 return status; 6861 } 6862 6863 /** 6864 * i40e_aq_get_phy_register 6865 * @hw: pointer to the hw struct 6866 * @phy_select: select which phy should be accessed 6867 * @dev_addr: PHY device address 6868 * @reg_addr: PHY register address 6869 * @reg_val: read register value 6870 * @cmd_details: pointer to command details structure or NULL 6871 * 6872 * Read the external PHY register. 6873 **/ 6874 enum i40e_status_code i40e_aq_get_phy_register(struct i40e_hw *hw, 6875 u8 phy_select, u8 dev_addr, 6876 u32 reg_addr, u32 *reg_val, 6877 struct i40e_asq_cmd_details *cmd_details) 6878 { 6879 struct i40e_aq_desc desc; 6880 struct i40e_aqc_phy_register_access *cmd = 6881 (struct i40e_aqc_phy_register_access *)&desc.params.raw; 6882 enum i40e_status_code status; 6883 6884 i40e_fill_default_direct_cmd_desc(&desc, 6885 i40e_aqc_opc_get_phy_register); 6886 6887 cmd->phy_interface = phy_select; 6888 cmd->dev_addres = dev_addr; 6889 cmd->reg_address = CPU_TO_LE32(reg_addr); 6890 6891 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 6892 if (!status) 6893 *reg_val = LE32_TO_CPU(cmd->reg_value); 6894 6895 return status; 6896 } 6897 6898 6899 /** 6900 * i40e_aq_send_msg_to_pf 6901 * @hw: pointer to the hardware structure 6902 * @v_opcode: opcodes for VF-PF communication 6903 * @v_retval: return error code 6904 * @msg: pointer to the msg buffer 6905 * @msglen: msg length 6906 * @cmd_details: pointer to command details 6907 * 6908 * Send message to PF driver using admin queue. By default, this message 6909 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for 6910 * completion before returning. 6911 **/ 6912 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw, 6913 enum virtchnl_ops v_opcode, 6914 enum i40e_status_code v_retval, 6915 u8 *msg, u16 msglen, 6916 struct i40e_asq_cmd_details *cmd_details) 6917 { 6918 struct i40e_aq_desc desc; 6919 struct i40e_asq_cmd_details details; 6920 enum i40e_status_code status; 6921 6922 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf); 6923 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI); 6924 desc.cookie_high = CPU_TO_LE32(v_opcode); 6925 desc.cookie_low = CPU_TO_LE32(v_retval); 6926 if (msglen) { 6927 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF 6928 | I40E_AQ_FLAG_RD)); 6929 if (msglen > I40E_AQ_LARGE_BUF) 6930 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 6931 desc.datalen = CPU_TO_LE16(msglen); 6932 } 6933 if (!cmd_details) { 6934 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM); 6935 details.async = TRUE; 6936 cmd_details = &details; 6937 } 6938 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg, 6939 msglen, cmd_details); 6940 return status; 6941 } 6942 6943 /** 6944 * i40e_vf_parse_hw_config 6945 * @hw: pointer to the hardware structure 6946 * @msg: pointer to the virtual channel VF resource structure 6947 * 6948 * Given a VF resource message from the PF, populate the hw struct 6949 * with appropriate information. 6950 **/ 6951 void i40e_vf_parse_hw_config(struct i40e_hw *hw, 6952 struct virtchnl_vf_resource *msg) 6953 { 6954 struct virtchnl_vsi_resource *vsi_res; 6955 int i; 6956 6957 vsi_res = &msg->vsi_res[0]; 6958 6959 hw->dev_caps.num_vsis = msg->num_vsis; 6960 hw->dev_caps.num_rx_qp = msg->num_queue_pairs; 6961 hw->dev_caps.num_tx_qp = msg->num_queue_pairs; 6962 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors; 6963 hw->dev_caps.dcb = msg->vf_cap_flags & 6964 VIRTCHNL_VF_OFFLOAD_L2; 6965 hw->dev_caps.iwarp = (msg->vf_cap_flags & 6966 VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0; 6967 for (i = 0; i < msg->num_vsis; i++) { 6968 if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) { 6969 i40e_memcpy(hw->mac.perm_addr, 6970 vsi_res->default_mac_addr, 6971 ETH_ALEN, 6972 I40E_NONDMA_TO_NONDMA); 6973 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr, 6974 ETH_ALEN, 6975 I40E_NONDMA_TO_NONDMA); 6976 } 6977 vsi_res++; 6978 } 6979 } 6980 6981 /** 6982 * i40e_vf_reset 6983 * @hw: pointer to the hardware structure 6984 * 6985 * Send a VF_RESET message to the PF. Does not wait for response from PF 6986 * as none will be forthcoming. Immediately after calling this function, 6987 * the admin queue should be shut down and (optionally) reinitialized. 6988 **/ 6989 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw) 6990 { 6991 return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF, 6992 I40E_SUCCESS, NULL, 0, NULL); 6993 } 6994 6995 /** 6996 * i40e_aq_set_arp_proxy_config 6997 * @hw: pointer to the HW structure 6998 * @proxy_config: pointer to proxy config command table struct 6999 * @cmd_details: pointer to command details 7000 * 7001 * Set ARP offload parameters from pre-populated 7002 * i40e_aqc_arp_proxy_data struct 7003 **/ 7004 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw, 7005 struct i40e_aqc_arp_proxy_data *proxy_config, 7006 struct i40e_asq_cmd_details *cmd_details) 7007 { 7008 struct i40e_aq_desc desc; 7009 enum i40e_status_code status; 7010 7011 if (!proxy_config) 7012 return I40E_ERR_PARAM; 7013 7014 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config); 7015 7016 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 7017 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 7018 desc.params.external.addr_high = 7019 CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config)); 7020 desc.params.external.addr_low = 7021 CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config)); 7022 desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data)); 7023 7024 status = i40e_asq_send_command(hw, &desc, proxy_config, 7025 sizeof(struct i40e_aqc_arp_proxy_data), 7026 cmd_details); 7027 7028 return status; 7029 } 7030 7031 /** 7032 * i40e_aq_opc_set_ns_proxy_table_entry 7033 * @hw: pointer to the HW structure 7034 * @ns_proxy_table_entry: pointer to NS table entry command struct 7035 * @cmd_details: pointer to command details 7036 * 7037 * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters 7038 * from pre-populated i40e_aqc_ns_proxy_data struct 7039 **/ 7040 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw, 7041 struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry, 7042 struct i40e_asq_cmd_details *cmd_details) 7043 { 7044 struct i40e_aq_desc desc; 7045 enum i40e_status_code status; 7046 7047 if (!ns_proxy_table_entry) 7048 return I40E_ERR_PARAM; 7049 7050 i40e_fill_default_direct_cmd_desc(&desc, 7051 i40e_aqc_opc_set_ns_proxy_table_entry); 7052 7053 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 7054 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 7055 desc.params.external.addr_high = 7056 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry)); 7057 desc.params.external.addr_low = 7058 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry)); 7059 desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data)); 7060 7061 status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry, 7062 sizeof(struct i40e_aqc_ns_proxy_data), 7063 cmd_details); 7064 7065 return status; 7066 } 7067 7068 /** 7069 * i40e_aq_set_clear_wol_filter 7070 * @hw: pointer to the hw struct 7071 * @filter_index: index of filter to modify (0-7) 7072 * @filter: buffer containing filter to be set 7073 * @set_filter: TRUE to set filter, FALSE to clear filter 7074 * @no_wol_tco: if TRUE, pass through packets cannot cause wake-up 7075 * if FALSE, pass through packets may cause wake-up 7076 * @filter_valid: TRUE if filter action is valid 7077 * @no_wol_tco_valid: TRUE if no WoL in TCO traffic action valid 7078 * @cmd_details: pointer to command details structure or NULL 7079 * 7080 * Set or clear WoL filter for port attached to the PF 7081 **/ 7082 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw, 7083 u8 filter_index, 7084 struct i40e_aqc_set_wol_filter_data *filter, 7085 bool set_filter, bool no_wol_tco, 7086 bool filter_valid, bool no_wol_tco_valid, 7087 struct i40e_asq_cmd_details *cmd_details) 7088 { 7089 struct i40e_aq_desc desc; 7090 struct i40e_aqc_set_wol_filter *cmd = 7091 (struct i40e_aqc_set_wol_filter *)&desc.params.raw; 7092 enum i40e_status_code status; 7093 u16 cmd_flags = 0; 7094 u16 valid_flags = 0; 7095 u16 buff_len = 0; 7096 7097 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter); 7098 7099 if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS) 7100 return I40E_ERR_PARAM; 7101 cmd->filter_index = CPU_TO_LE16(filter_index); 7102 7103 if (set_filter) { 7104 if (!filter) 7105 return I40E_ERR_PARAM; 7106 7107 cmd_flags |= I40E_AQC_SET_WOL_FILTER; 7108 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR; 7109 } 7110 7111 if (no_wol_tco) 7112 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL; 7113 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 7114 7115 if (filter_valid) 7116 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID; 7117 if (no_wol_tco_valid) 7118 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID; 7119 cmd->valid_flags = CPU_TO_LE16(valid_flags); 7120 7121 buff_len = sizeof(*filter); 7122 desc.datalen = CPU_TO_LE16(buff_len); 7123 7124 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 7125 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 7126 7127 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter)); 7128 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter)); 7129 7130 status = i40e_asq_send_command(hw, &desc, filter, 7131 buff_len, cmd_details); 7132 7133 return status; 7134 } 7135 7136 /** 7137 * i40e_aq_get_wake_event_reason 7138 * @hw: pointer to the hw struct 7139 * @wake_reason: return value, index of matching filter 7140 * @cmd_details: pointer to command details structure or NULL 7141 * 7142 * Get information for the reason of a Wake Up event 7143 **/ 7144 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw, 7145 u16 *wake_reason, 7146 struct i40e_asq_cmd_details *cmd_details) 7147 { 7148 struct i40e_aq_desc desc; 7149 struct i40e_aqc_get_wake_reason_completion *resp = 7150 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw; 7151 enum i40e_status_code status; 7152 7153 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason); 7154 7155 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 7156 7157 if (status == I40E_SUCCESS) 7158 *wake_reason = LE16_TO_CPU(resp->wake_reason); 7159 7160 return status; 7161 } 7162 7163 /** 7164 * i40e_aq_clear_all_wol_filters 7165 * @hw: pointer to the hw struct 7166 * @cmd_details: pointer to command details structure or NULL 7167 * 7168 * Get information for the reason of a Wake Up event 7169 **/ 7170 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw, 7171 struct i40e_asq_cmd_details *cmd_details) 7172 { 7173 struct i40e_aq_desc desc; 7174 enum i40e_status_code status; 7175 7176 i40e_fill_default_direct_cmd_desc(&desc, 7177 i40e_aqc_opc_clear_all_wol_filters); 7178 7179 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 7180 7181 return status; 7182 } 7183 7184