1 /****************************************************************************** 2 3 Copyright (c) 2013-2018, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #ifndef _I40E_TYPE_H_ 36 #define _I40E_TYPE_H_ 37 38 #include "i40e_status.h" 39 #include "i40e_osdep.h" 40 #include "i40e_register.h" 41 #include "i40e_adminq.h" 42 #include "i40e_hmc.h" 43 #include "i40e_lan_hmc.h" 44 #include "i40e_devids.h" 45 46 47 #define BIT(a) (1UL << (a)) 48 #define BIT_ULL(a) (1ULL << (a)) 49 50 #ifndef I40E_MASK 51 /* I40E_MASK is a macro used on 32 bit registers */ 52 #define I40E_MASK(mask, shift) (mask << shift) 53 #endif 54 55 #define I40E_MAX_PF 16 56 #define I40E_MAX_PF_VSI 64 57 #define I40E_MAX_PF_QP 128 58 #define I40E_MAX_VSI_QP 16 59 #define I40E_MAX_VF_VSI 4 60 #define I40E_MAX_CHAINED_RX_BUFFERS 5 61 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16 62 63 /* something less than 1 minute */ 64 #define I40E_HEARTBEAT_TIMEOUT (HZ * 50) 65 66 /* Max default timeout in ms, */ 67 #define I40E_MAX_NVM_TIMEOUT 18000 68 69 /* Max timeout in ms for the phy to respond */ 70 #define I40E_MAX_PHY_TIMEOUT 500 71 72 /* Check whether address is multicast. */ 73 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01)) 74 75 /* Check whether an address is broadcast. */ 76 #define I40E_IS_BROADCAST(address) \ 77 ((((u8 *)(address))[0] == ((u8)0xff)) && \ 78 (((u8 *)(address))[1] == ((u8)0xff))) 79 80 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */ 81 #define I40E_MS_TO_GTIME(time) ((time) * 1000) 82 83 /* forward declaration */ 84 struct i40e_hw; 85 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *); 86 87 #define ETH_ALEN 6 88 /* Data type manipulation macros. */ 89 #define I40E_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF)) 90 #define I40E_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF)) 91 92 #define I40E_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF)) 93 #define I40E_LO_WORD(x) ((u16)((x) & 0xFFFF)) 94 95 #define I40E_HI_BYTE(x) ((u8)(((x) >> 8) & 0xFF)) 96 #define I40E_LO_BYTE(x) ((u8)((x) & 0xFF)) 97 98 /* Number of Transmit Descriptors must be a multiple of 32. */ 99 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 32 100 /* Number of Receive Descriptors must be a multiple of 32 if 101 * the number of descriptors is greater than 32. 102 */ 103 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32 104 105 #define I40E_DESC_UNUSED(R) \ 106 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ 107 (R)->next_to_clean - (R)->next_to_use - 1) 108 109 /* bitfields for Tx queue mapping in QTX_CTL */ 110 #define I40E_QTX_CTL_VF_QUEUE 0x0 111 #define I40E_QTX_CTL_VM_QUEUE 0x1 112 #define I40E_QTX_CTL_PF_QUEUE 0x2 113 114 /* debug masks - set these bits in hw->debug_mask to control output */ 115 enum i40e_debug_mask { 116 I40E_DEBUG_INIT = 0x00000001, 117 I40E_DEBUG_RELEASE = 0x00000002, 118 119 I40E_DEBUG_LINK = 0x00000010, 120 I40E_DEBUG_PHY = 0x00000020, 121 I40E_DEBUG_HMC = 0x00000040, 122 I40E_DEBUG_NVM = 0x00000080, 123 I40E_DEBUG_LAN = 0x00000100, 124 I40E_DEBUG_FLOW = 0x00000200, 125 I40E_DEBUG_DCB = 0x00000400, 126 I40E_DEBUG_DIAG = 0x00000800, 127 I40E_DEBUG_FD = 0x00001000, 128 129 I40E_DEBUG_IWARP = 0x00F00000, 130 131 I40E_DEBUG_AQ_MESSAGE = 0x01000000, 132 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000, 133 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000, 134 I40E_DEBUG_AQ_COMMAND = 0x06000000, 135 I40E_DEBUG_AQ = 0x0F000000, 136 137 I40E_DEBUG_USER = 0xF0000000, 138 139 I40E_DEBUG_ALL = 0xFFFFFFFF 140 }; 141 142 /* PCI Bus Info */ 143 #define I40E_PCI_LINK_STATUS 0xB2 144 #define I40E_PCI_LINK_WIDTH 0x3F0 145 #define I40E_PCI_LINK_WIDTH_1 0x10 146 #define I40E_PCI_LINK_WIDTH_2 0x20 147 #define I40E_PCI_LINK_WIDTH_4 0x40 148 #define I40E_PCI_LINK_WIDTH_8 0x80 149 #define I40E_PCI_LINK_SPEED 0xF 150 #define I40E_PCI_LINK_SPEED_2500 0x1 151 #define I40E_PCI_LINK_SPEED_5000 0x2 152 #define I40E_PCI_LINK_SPEED_8000 0x3 153 154 #define I40E_MDIO_CLAUSE22_STCODE_MASK I40E_MASK(1, \ 155 I40E_GLGEN_MSCA_STCODE_SHIFT) 156 #define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK I40E_MASK(1, \ 157 I40E_GLGEN_MSCA_OPCODE_SHIFT) 158 #define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK I40E_MASK(2, \ 159 I40E_GLGEN_MSCA_OPCODE_SHIFT) 160 161 #define I40E_MDIO_CLAUSE45_STCODE_MASK I40E_MASK(0, \ 162 I40E_GLGEN_MSCA_STCODE_SHIFT) 163 #define I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK I40E_MASK(0, \ 164 I40E_GLGEN_MSCA_OPCODE_SHIFT) 165 #define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK I40E_MASK(1, \ 166 I40E_GLGEN_MSCA_OPCODE_SHIFT) 167 #define I40E_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK I40E_MASK(2, \ 168 I40E_GLGEN_MSCA_OPCODE_SHIFT) 169 #define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK I40E_MASK(3, \ 170 I40E_GLGEN_MSCA_OPCODE_SHIFT) 171 172 #define I40E_PHY_COM_REG_PAGE 0x1E 173 #define I40E_PHY_LED_LINK_MODE_MASK 0xF0 174 #define I40E_PHY_LED_MANUAL_ON 0x100 175 #define I40E_PHY_LED_PROV_REG_1 0xC430 176 #define I40E_PHY_LED_MODE_MASK 0xFFFF 177 #define I40E_PHY_LED_MODE_ORIG 0x80000000 178 179 /* Memory types */ 180 enum i40e_memset_type { 181 I40E_NONDMA_MEM = 0, 182 I40E_DMA_MEM 183 }; 184 185 /* Memcpy types */ 186 enum i40e_memcpy_type { 187 I40E_NONDMA_TO_NONDMA = 0, 188 I40E_NONDMA_TO_DMA, 189 I40E_DMA_TO_DMA, 190 I40E_DMA_TO_NONDMA 191 }; 192 193 /* These are structs for managing the hardware information and the operations. 194 * The structures of function pointers are filled out at init time when we 195 * know for sure exactly which hardware we're working with. This gives us the 196 * flexibility of using the same main driver code but adapting to slightly 197 * different hardware needs as new parts are developed. For this architecture, 198 * the Firmware and AdminQ are intended to insulate the driver from most of the 199 * future changes, but these structures will also do part of the job. 200 */ 201 enum i40e_mac_type { 202 I40E_MAC_UNKNOWN = 0, 203 I40E_MAC_XL710, 204 I40E_MAC_VF, 205 I40E_MAC_X722, 206 I40E_MAC_X722_VF, 207 I40E_MAC_GENERIC, 208 }; 209 210 enum i40e_media_type { 211 I40E_MEDIA_TYPE_UNKNOWN = 0, 212 I40E_MEDIA_TYPE_FIBER, 213 I40E_MEDIA_TYPE_BASET, 214 I40E_MEDIA_TYPE_BACKPLANE, 215 I40E_MEDIA_TYPE_CX4, 216 I40E_MEDIA_TYPE_DA, 217 I40E_MEDIA_TYPE_VIRTUAL 218 }; 219 220 enum i40e_fc_mode { 221 I40E_FC_NONE = 0, 222 I40E_FC_RX_PAUSE, 223 I40E_FC_TX_PAUSE, 224 I40E_FC_FULL, 225 I40E_FC_PFC, 226 I40E_FC_DEFAULT 227 }; 228 229 enum i40e_set_fc_aq_failures { 230 I40E_SET_FC_AQ_FAIL_NONE = 0, 231 I40E_SET_FC_AQ_FAIL_GET = 1, 232 I40E_SET_FC_AQ_FAIL_SET = 2, 233 I40E_SET_FC_AQ_FAIL_UPDATE = 4, 234 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6 235 }; 236 237 enum i40e_vsi_type { 238 I40E_VSI_MAIN = 0, 239 I40E_VSI_VMDQ1 = 1, 240 I40E_VSI_VMDQ2 = 2, 241 I40E_VSI_CTRL = 3, 242 I40E_VSI_FCOE = 4, 243 I40E_VSI_MIRROR = 5, 244 I40E_VSI_SRIOV = 6, 245 I40E_VSI_FDIR = 7, 246 I40E_VSI_IWARP = 8, 247 I40E_VSI_TYPE_UNKNOWN 248 }; 249 250 enum i40e_queue_type { 251 I40E_QUEUE_TYPE_RX = 0, 252 I40E_QUEUE_TYPE_TX, 253 I40E_QUEUE_TYPE_PE_CEQ, 254 I40E_QUEUE_TYPE_UNKNOWN 255 }; 256 257 struct i40e_link_status { 258 enum i40e_aq_phy_type phy_type; 259 enum i40e_aq_link_speed link_speed; 260 u8 link_info; 261 u8 an_info; 262 u8 req_fec_info; 263 u8 fec_info; 264 u8 ext_info; 265 u8 loopback; 266 /* is Link Status Event notification to SW enabled */ 267 bool lse_enable; 268 u16 max_frame_size; 269 bool crc_enable; 270 u8 pacing; 271 u8 requested_speeds; 272 u8 module_type[3]; 273 /* 1st byte: module identifier */ 274 #define I40E_MODULE_TYPE_SFP 0x03 275 #define I40E_MODULE_TYPE_QSFP 0x0D 276 /* 2nd byte: ethernet compliance codes for 10/40G */ 277 #define I40E_MODULE_TYPE_40G_ACTIVE 0x01 278 #define I40E_MODULE_TYPE_40G_LR4 0x02 279 #define I40E_MODULE_TYPE_40G_SR4 0x04 280 #define I40E_MODULE_TYPE_40G_CR4 0x08 281 #define I40E_MODULE_TYPE_10G_BASE_SR 0x10 282 #define I40E_MODULE_TYPE_10G_BASE_LR 0x20 283 #define I40E_MODULE_TYPE_10G_BASE_LRM 0x40 284 #define I40E_MODULE_TYPE_10G_BASE_ER 0x80 285 /* 3rd byte: ethernet compliance codes for 1G */ 286 #define I40E_MODULE_TYPE_1000BASE_SX 0x01 287 #define I40E_MODULE_TYPE_1000BASE_LX 0x02 288 #define I40E_MODULE_TYPE_1000BASE_CX 0x04 289 #define I40E_MODULE_TYPE_1000BASE_T 0x08 290 }; 291 292 struct i40e_phy_info { 293 struct i40e_link_status link_info; 294 struct i40e_link_status link_info_old; 295 bool get_link_info; 296 enum i40e_media_type media_type; 297 /* all the phy types the NVM is capable of */ 298 u64 phy_types; 299 }; 300 301 #define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII) 302 #define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) 303 #define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) 304 #define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) 305 #define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) 306 #define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI) 307 #define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI) 308 #define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI) 309 #define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI) 310 #define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI) 311 #define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) 312 #define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) 313 #define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) 314 #define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) 315 #define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX) 316 #define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T) 317 #define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T) 318 #define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) 319 #define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR) 320 #define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) 321 #define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) 322 #define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) 323 #define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) 324 #define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) 325 #define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX) 326 #define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) 327 #define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \ 328 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) 329 #define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) 330 /* 331 * Defining the macro I40E_TYPE_OFFSET to implement a bit shift for some 332 * PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit 333 * fields but no corresponding gap in the i40e_aq_phy_type enumeration. So, 334 * a shift is needed to adjust for this with values larger than 31. The 335 * only affected values are I40E_PHY_TYPE_25GBASE_*. 336 */ 337 #define I40E_PHY_TYPE_OFFSET 1 338 #define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \ 339 I40E_PHY_TYPE_OFFSET) 340 #define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \ 341 I40E_PHY_TYPE_OFFSET) 342 #define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \ 343 I40E_PHY_TYPE_OFFSET) 344 #define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \ 345 I40E_PHY_TYPE_OFFSET) 346 #define I40E_CAP_PHY_TYPE_25GBASE_AOC BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC + \ 347 I40E_PHY_TYPE_OFFSET) 348 #define I40E_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC + \ 349 I40E_PHY_TYPE_OFFSET) 350 #define I40E_CAP_PHY_TYPE_2_5GBASE_T BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T) 351 #define I40E_CAP_PHY_TYPE_5GBASE_T BIT_ULL(I40E_PHY_TYPE_5GBASE_T) 352 #define I40E_HW_CAP_MAX_GPIO 30 353 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO 0 354 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C 1 355 356 enum i40e_acpi_programming_method { 357 I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0, 358 I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1 359 }; 360 361 #define I40E_WOL_SUPPORT_MASK 0x1 362 #define I40E_ACPI_PROGRAMMING_METHOD_MASK 0x2 363 #define I40E_PROXY_SUPPORT_MASK 0x4 364 365 /* Capabilities of a PF or a VF or the whole device */ 366 struct i40e_hw_capabilities { 367 u32 switch_mode; 368 #define I40E_NVM_IMAGE_TYPE_EVB 0x0 369 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2 370 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3 371 372 /* Cloud filter modes: 373 * Mode1: Filter on L4 port only 374 * Mode2: Filter for non-tunneled traffic 375 * Mode3: Filter for tunnel traffic 376 */ 377 #define I40E_CLOUD_FILTER_MODE1 0x6 378 #define I40E_CLOUD_FILTER_MODE2 0x7 379 #define I40E_CLOUD_FILTER_MODE3 0x8 380 #define I40E_SWITCH_MODE_MASK 0xF 381 382 u32 management_mode; 383 u32 mng_protocols_over_mctp; 384 #define I40E_MNG_PROTOCOL_PLDM 0x2 385 #define I40E_MNG_PROTOCOL_OEM_COMMANDS 0x4 386 #define I40E_MNG_PROTOCOL_NCSI 0x8 387 u32 npar_enable; 388 u32 os2bmc; 389 u32 valid_functions; 390 bool sr_iov_1_1; 391 bool vmdq; 392 bool evb_802_1_qbg; /* Edge Virtual Bridging */ 393 bool evb_802_1_qbh; /* Bridge Port Extension */ 394 bool dcb; 395 bool fcoe; 396 bool iscsi; /* Indicates iSCSI enabled */ 397 bool flex10_enable; 398 bool flex10_capable; 399 u32 flex10_mode; 400 #define I40E_FLEX10_MODE_UNKNOWN 0x0 401 #define I40E_FLEX10_MODE_DCC 0x1 402 #define I40E_FLEX10_MODE_DCI 0x2 403 404 u32 flex10_status; 405 #define I40E_FLEX10_STATUS_DCC_ERROR 0x1 406 #define I40E_FLEX10_STATUS_VC_MODE 0x2 407 408 bool sec_rev_disabled; 409 bool update_disabled; 410 #define I40E_NVM_MGMT_SEC_REV_DISABLED 0x1 411 #define I40E_NVM_MGMT_UPDATE_DISABLED 0x2 412 413 bool mgmt_cem; 414 bool ieee_1588; 415 bool iwarp; 416 bool fd; 417 u32 fd_filters_guaranteed; 418 u32 fd_filters_best_effort; 419 bool rss; 420 u32 rss_table_size; 421 u32 rss_table_entry_width; 422 bool led[I40E_HW_CAP_MAX_GPIO]; 423 bool sdp[I40E_HW_CAP_MAX_GPIO]; 424 u32 nvm_image_type; 425 u32 num_flow_director_filters; 426 u32 num_vfs; 427 u32 vf_base_id; 428 u32 num_vsis; 429 u32 num_rx_qp; 430 u32 num_tx_qp; 431 u32 base_queue; 432 u32 num_msix_vectors; 433 u32 num_msix_vectors_vf; 434 u32 led_pin_num; 435 u32 sdp_pin_num; 436 u32 mdio_port_num; 437 u32 mdio_port_mode; 438 u8 rx_buf_chain_len; 439 u32 enabled_tcmap; 440 u32 maxtc; 441 u64 wr_csr_prot; 442 bool dis_unused_ports; 443 bool apm_wol_support; 444 enum i40e_acpi_programming_method acpi_prog_method; 445 bool proxy_support; 446 }; 447 448 struct i40e_mac_info { 449 enum i40e_mac_type type; 450 u8 addr[ETH_ALEN]; 451 u8 perm_addr[ETH_ALEN]; 452 u8 san_addr[ETH_ALEN]; 453 u8 port_addr[ETH_ALEN]; 454 u16 max_fcoeq; 455 }; 456 457 enum i40e_aq_resources_ids { 458 I40E_NVM_RESOURCE_ID = 1 459 }; 460 461 enum i40e_aq_resource_access_type { 462 I40E_RESOURCE_READ = 1, 463 I40E_RESOURCE_WRITE 464 }; 465 466 struct i40e_nvm_info { 467 u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */ 468 u32 timeout; /* [ms] */ 469 u16 sr_size; /* Shadow RAM size in words */ 470 bool blank_nvm_mode; /* is NVM empty (no FW present)*/ 471 u16 version; /* NVM package version */ 472 u32 eetrack; /* NVM data version */ 473 u32 oem_ver; /* OEM version info */ 474 }; 475 476 /* definitions used in NVM update support */ 477 478 enum i40e_nvmupd_cmd { 479 I40E_NVMUPD_INVALID, 480 I40E_NVMUPD_READ_CON, 481 I40E_NVMUPD_READ_SNT, 482 I40E_NVMUPD_READ_LCB, 483 I40E_NVMUPD_READ_SA, 484 I40E_NVMUPD_WRITE_ERA, 485 I40E_NVMUPD_WRITE_CON, 486 I40E_NVMUPD_WRITE_SNT, 487 I40E_NVMUPD_WRITE_LCB, 488 I40E_NVMUPD_WRITE_SA, 489 I40E_NVMUPD_CSUM_CON, 490 I40E_NVMUPD_CSUM_SA, 491 I40E_NVMUPD_CSUM_LCB, 492 I40E_NVMUPD_STATUS, 493 I40E_NVMUPD_EXEC_AQ, 494 I40E_NVMUPD_GET_AQ_RESULT, 495 I40E_NVMUPD_GET_AQ_EVENT, 496 I40E_NVMUPD_FEATURES, 497 }; 498 499 enum i40e_nvmupd_state { 500 I40E_NVMUPD_STATE_INIT, 501 I40E_NVMUPD_STATE_READING, 502 I40E_NVMUPD_STATE_WRITING, 503 I40E_NVMUPD_STATE_INIT_WAIT, 504 I40E_NVMUPD_STATE_WRITE_WAIT, 505 I40E_NVMUPD_STATE_ERROR 506 }; 507 508 /* nvm_access definition and its masks/shifts need to be accessible to 509 * application, core driver, and shared code. Where is the right file? 510 */ 511 #define I40E_NVM_READ 0xB 512 #define I40E_NVM_WRITE 0xC 513 514 #define I40E_NVM_MOD_PNT_MASK 0xFF 515 516 #define I40E_NVM_TRANS_SHIFT 8 517 #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT) 518 #define I40E_NVM_PRESERVATION_FLAGS_SHIFT 12 519 #define I40E_NVM_PRESERVATION_FLAGS_MASK \ 520 (0x3 << I40E_NVM_PRESERVATION_FLAGS_SHIFT) 521 #define I40E_NVM_PRESERVATION_FLAGS_SELECTED 0x01 522 #define I40E_NVM_PRESERVATION_FLAGS_ALL 0x02 523 #define I40E_NVM_CON 0x0 524 #define I40E_NVM_SNT 0x1 525 #define I40E_NVM_LCB 0x2 526 #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB) 527 #define I40E_NVM_ERA 0x4 528 #define I40E_NVM_CSUM 0x8 529 #define I40E_NVM_AQE 0xe 530 #define I40E_NVM_EXEC 0xf 531 532 #define I40E_NVM_EXEC_GET_AQ_RESULT 0x0 533 #define I40E_NVM_EXEC_FEATURES 0xe 534 #define I40E_NVM_EXEC_STATUS 0xf 535 536 #define I40E_NVM_ADAPT_SHIFT 16 537 #define I40E_NVM_ADAPT_MASK (0xffffULL << I40E_NVM_ADAPT_SHIFT) 538 539 #define I40E_NVMUPD_MAX_DATA 4096 540 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */ 541 542 struct i40e_nvm_access { 543 u32 command; 544 u32 config; 545 u32 offset; /* in bytes */ 546 u32 data_size; /* in bytes */ 547 u8 data[1]; 548 }; 549 550 /* NVMUpdate features API */ 551 #define I40E_NVMUPD_FEATURES_API_VER_MAJOR 0 552 #define I40E_NVMUPD_FEATURES_API_VER_MINOR 14 553 #define I40E_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN 12 554 555 #define I40E_NVMUPD_FEATURE_FLAT_NVM_SUPPORT BIT(0) 556 557 struct i40e_nvmupd_features { 558 u8 major; 559 u8 minor; 560 u16 size; 561 u8 features[I40E_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN]; 562 }; 563 564 /* (Q)SFP module access definitions */ 565 #define I40E_I2C_EEPROM_DEV_ADDR 0xA0 566 #define I40E_I2C_EEPROM_DEV_ADDR2 0xA2 567 #define I40E_MODULE_TYPE_ADDR 0x00 568 #define I40E_MODULE_REVISION_ADDR 0x01 569 #define I40E_MODULE_SFF_8472_COMP 0x5E 570 #define I40E_MODULE_SFF_8472_SWAP 0x5C 571 #define I40E_MODULE_SFF_ADDR_MODE 0x04 572 #define I40E_MODULE_SFF_DIAG_CAPAB 0x40 573 #define I40E_MODULE_TYPE_QSFP_PLUS 0x0D 574 #define I40E_MODULE_TYPE_QSFP28 0x11 575 #define I40E_MODULE_QSFP_MAX_LEN 640 576 577 /* PCI bus types */ 578 enum i40e_bus_type { 579 i40e_bus_type_unknown = 0, 580 i40e_bus_type_pci, 581 i40e_bus_type_pcix, 582 i40e_bus_type_pci_express, 583 i40e_bus_type_reserved 584 }; 585 586 /* PCI bus speeds */ 587 enum i40e_bus_speed { 588 i40e_bus_speed_unknown = 0, 589 i40e_bus_speed_33 = 33, 590 i40e_bus_speed_66 = 66, 591 i40e_bus_speed_100 = 100, 592 i40e_bus_speed_120 = 120, 593 i40e_bus_speed_133 = 133, 594 i40e_bus_speed_2500 = 2500, 595 i40e_bus_speed_5000 = 5000, 596 i40e_bus_speed_8000 = 8000, 597 i40e_bus_speed_reserved 598 }; 599 600 /* PCI bus widths */ 601 enum i40e_bus_width { 602 i40e_bus_width_unknown = 0, 603 i40e_bus_width_pcie_x1 = 1, 604 i40e_bus_width_pcie_x2 = 2, 605 i40e_bus_width_pcie_x4 = 4, 606 i40e_bus_width_pcie_x8 = 8, 607 i40e_bus_width_32 = 32, 608 i40e_bus_width_64 = 64, 609 i40e_bus_width_reserved 610 }; 611 612 /* Bus parameters */ 613 struct i40e_bus_info { 614 enum i40e_bus_speed speed; 615 enum i40e_bus_width width; 616 enum i40e_bus_type type; 617 618 u16 func; 619 u16 device; 620 u16 lan_id; 621 u16 bus_id; 622 }; 623 624 /* Flow control (FC) parameters */ 625 struct i40e_fc_info { 626 enum i40e_fc_mode current_mode; /* FC mode in effect */ 627 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */ 628 }; 629 630 #define I40E_MAX_TRAFFIC_CLASS 8 631 #define I40E_MAX_USER_PRIORITY 8 632 #define I40E_DCBX_MAX_APPS 32 633 #define I40E_LLDPDU_SIZE 1500 634 #define I40E_TLV_STATUS_OPER 0x1 635 #define I40E_TLV_STATUS_SYNC 0x2 636 #define I40E_TLV_STATUS_ERR 0x4 637 #define I40E_CEE_OPER_MAX_APPS 3 638 #define I40E_APP_PROTOID_FCOE 0x8906 639 #define I40E_APP_PROTOID_ISCSI 0x0cbc 640 #define I40E_APP_PROTOID_FIP 0x8914 641 #define I40E_APP_SEL_ETHTYPE 0x1 642 #define I40E_APP_SEL_TCPIP 0x2 643 #define I40E_CEE_APP_SEL_ETHTYPE 0x0 644 #define I40E_CEE_APP_SEL_TCPIP 0x1 645 646 /* CEE or IEEE 802.1Qaz ETS Configuration data */ 647 struct i40e_dcb_ets_config { 648 u8 willing; 649 u8 cbs; 650 u8 maxtcs; 651 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS]; 652 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS]; 653 u8 tsatable[I40E_MAX_TRAFFIC_CLASS]; 654 }; 655 656 /* CEE or IEEE 802.1Qaz PFC Configuration data */ 657 struct i40e_dcb_pfc_config { 658 u8 willing; 659 u8 mbc; 660 u8 pfccap; 661 u8 pfcenable; 662 }; 663 664 /* CEE or IEEE 802.1Qaz Application Priority data */ 665 struct i40e_dcb_app_priority_table { 666 u8 priority; 667 u8 selector; 668 u16 protocolid; 669 }; 670 671 struct i40e_dcbx_config { 672 u8 dcbx_mode; 673 #define I40E_DCBX_MODE_CEE 0x1 674 #define I40E_DCBX_MODE_IEEE 0x2 675 u8 app_mode; 676 #define I40E_DCBX_APPS_NON_WILLING 0x1 677 u32 numapps; 678 u32 tlv_status; /* CEE mode TLV status */ 679 struct i40e_dcb_ets_config etscfg; 680 struct i40e_dcb_ets_config etsrec; 681 struct i40e_dcb_pfc_config pfc; 682 struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS]; 683 }; 684 685 /* Port hardware description */ 686 struct i40e_hw { 687 u8 *hw_addr; 688 void *back; 689 690 /* subsystem structs */ 691 struct i40e_phy_info phy; 692 struct i40e_mac_info mac; 693 struct i40e_bus_info bus; 694 struct i40e_nvm_info nvm; 695 struct i40e_fc_info fc; 696 697 /* pci info */ 698 u16 device_id; 699 u16 vendor_id; 700 u16 subsystem_device_id; 701 u16 subsystem_vendor_id; 702 u8 revision_id; 703 u8 port; 704 bool adapter_stopped; 705 706 /* capabilities for entire device and PCI func */ 707 struct i40e_hw_capabilities dev_caps; 708 struct i40e_hw_capabilities func_caps; 709 710 /* Flow Director shared filter space */ 711 u16 fdir_shared_filter_count; 712 713 /* device profile info */ 714 u8 pf_id; 715 u16 main_vsi_seid; 716 717 /* for multi-function MACs */ 718 u16 partition_id; 719 u16 num_partitions; 720 u16 num_ports; 721 722 /* Closest numa node to the device */ 723 u16 numa_node; 724 725 /* Admin Queue info */ 726 struct i40e_adminq_info aq; 727 728 /* state of nvm update process */ 729 enum i40e_nvmupd_state nvmupd_state; 730 struct i40e_aq_desc nvm_wb_desc; 731 struct i40e_aq_desc nvm_aq_event_desc; 732 struct i40e_virt_mem nvm_buff; 733 bool nvm_release_on_done; 734 u16 nvm_wait_opcode; 735 736 /* HMC info */ 737 struct i40e_hmc_info hmc; /* HMC info struct */ 738 739 /* LLDP/DCBX Status */ 740 u16 dcbx_status; 741 742 /* DCBX info */ 743 struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */ 744 struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */ 745 struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */ 746 747 /* WoL and proxy support */ 748 u16 num_wol_proxy_filters; 749 u16 wol_proxy_vsi_seid; 750 751 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0) 752 #define I40E_HW_FLAG_802_1AD_CAPABLE BIT_ULL(1) 753 #define I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE BIT_ULL(2) 754 #define I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3) 755 #define I40E_HW_FLAG_FW_LLDP_STOPPABLE BIT_ULL(4) 756 #define I40E_HW_FLAG_FW_LLDP_PERSISTENT BIT_ULL(5) 757 #define I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED BIT_ULL(6) 758 #define I40E_HW_FLAG_DROP_MODE BIT_ULL(7) 759 #define I40E_HW_FLAG_X722_FEC_REQUEST_CAPABLE BIT_ULL(8) 760 u64 flags; 761 762 /* Used in set switch config AQ command */ 763 u16 switch_tag; 764 u16 first_tag; 765 u16 second_tag; 766 767 /* NVMUpdate features */ 768 struct i40e_nvmupd_features nvmupd_features; 769 770 /* debug mask */ 771 u32 debug_mask; 772 char err_str[16]; 773 }; 774 775 static INLINE bool i40e_is_vf(struct i40e_hw *hw) 776 { 777 return (hw->mac.type == I40E_MAC_VF || 778 hw->mac.type == I40E_MAC_X722_VF); 779 } 780 781 struct i40e_driver_version { 782 u8 major_version; 783 u8 minor_version; 784 u8 build_version; 785 u8 subbuild_version; 786 u8 driver_string[32]; 787 }; 788 789 /* RX Descriptors */ 790 union i40e_16byte_rx_desc { 791 struct { 792 __le64 pkt_addr; /* Packet buffer address */ 793 __le64 hdr_addr; /* Header buffer address */ 794 } read; 795 struct { 796 struct { 797 struct { 798 union { 799 __le16 mirroring_status; 800 __le16 fcoe_ctx_id; 801 } mirr_fcoe; 802 __le16 l2tag1; 803 } lo_dword; 804 union { 805 __le32 rss; /* RSS Hash */ 806 __le32 fd_id; /* Flow director filter id */ 807 __le32 fcoe_param; /* FCoE DDP Context id */ 808 } hi_dword; 809 } qword0; 810 struct { 811 /* ext status/error/pktype/length */ 812 __le64 status_error_len; 813 } qword1; 814 } wb; /* writeback */ 815 }; 816 817 union i40e_32byte_rx_desc { 818 struct { 819 __le64 pkt_addr; /* Packet buffer address */ 820 __le64 hdr_addr; /* Header buffer address */ 821 /* bit 0 of hdr_buffer_addr is DD bit */ 822 __le64 rsvd1; 823 __le64 rsvd2; 824 } read; 825 struct { 826 struct { 827 struct { 828 union { 829 __le16 mirroring_status; 830 __le16 fcoe_ctx_id; 831 } mirr_fcoe; 832 __le16 l2tag1; 833 } lo_dword; 834 union { 835 __le32 rss; /* RSS Hash */ 836 __le32 fcoe_param; /* FCoE DDP Context id */ 837 /* Flow director filter id in case of 838 * Programming status desc WB 839 */ 840 __le32 fd_id; 841 } hi_dword; 842 } qword0; 843 struct { 844 /* status/error/pktype/length */ 845 __le64 status_error_len; 846 } qword1; 847 struct { 848 __le16 ext_status; /* extended status */ 849 __le16 rsvd; 850 __le16 l2tag2_1; 851 __le16 l2tag2_2; 852 } qword2; 853 struct { 854 union { 855 __le32 flex_bytes_lo; 856 __le32 pe_status; 857 } lo_dword; 858 union { 859 __le32 flex_bytes_hi; 860 __le32 fd_id; 861 } hi_dword; 862 } qword3; 863 } wb; /* writeback */ 864 }; 865 866 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT 8 867 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \ 868 I40E_RXD_QW0_MIRROR_STATUS_SHIFT) 869 #define I40E_RXD_QW0_FCOEINDX_SHIFT 0 870 #define I40E_RXD_QW0_FCOEINDX_MASK (0xFFFUL << \ 871 I40E_RXD_QW0_FCOEINDX_SHIFT) 872 873 enum i40e_rx_desc_status_bits { 874 /* Note: These are predefined bit offsets */ 875 I40E_RX_DESC_STATUS_DD_SHIFT = 0, 876 I40E_RX_DESC_STATUS_EOF_SHIFT = 1, 877 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2, 878 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3, 879 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4, 880 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */ 881 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7, 882 I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8, 883 884 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */ 885 I40E_RX_DESC_STATUS_FLM_SHIFT = 11, 886 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */ 887 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14, 888 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15, 889 I40E_RX_DESC_STATUS_RESERVED2_SHIFT = 16, /* 2 BITS */ 890 I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18, 891 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */ 892 }; 893 894 #define I40E_RXD_QW1_STATUS_SHIFT 0 895 #define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \ 896 I40E_RXD_QW1_STATUS_SHIFT) 897 898 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT 899 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \ 900 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT) 901 902 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT 903 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT) 904 905 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT I40E_RX_DESC_STATUS_UMBCAST 906 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK (0x3UL << \ 907 I40E_RXD_QW1_STATUS_UMBCAST_SHIFT) 908 909 enum i40e_rx_desc_fltstat_values { 910 I40E_RX_DESC_FLTSTAT_NO_DATA = 0, 911 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */ 912 I40E_RX_DESC_FLTSTAT_RSV = 2, 913 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3, 914 }; 915 916 #define I40E_RXD_PACKET_TYPE_UNICAST 0 917 #define I40E_RXD_PACKET_TYPE_MULTICAST 1 918 #define I40E_RXD_PACKET_TYPE_BROADCAST 2 919 #define I40E_RXD_PACKET_TYPE_MIRRORED 3 920 921 #define I40E_RXD_QW1_ERROR_SHIFT 19 922 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT) 923 924 enum i40e_rx_desc_error_bits { 925 /* Note: These are predefined bit offsets */ 926 I40E_RX_DESC_ERROR_RXE_SHIFT = 0, 927 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1, 928 I40E_RX_DESC_ERROR_HBO_SHIFT = 2, 929 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */ 930 I40E_RX_DESC_ERROR_IPE_SHIFT = 3, 931 I40E_RX_DESC_ERROR_L4E_SHIFT = 4, 932 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5, 933 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6, 934 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7 935 }; 936 937 enum i40e_rx_desc_error_l3l4e_fcoe_masks { 938 I40E_RX_DESC_ERROR_L3L4E_NONE = 0, 939 I40E_RX_DESC_ERROR_L3L4E_PROT = 1, 940 I40E_RX_DESC_ERROR_L3L4E_FC = 2, 941 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3, 942 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4 943 }; 944 945 #define I40E_RXD_QW1_PTYPE_SHIFT 30 946 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT) 947 948 /* Packet type non-ip values */ 949 enum i40e_rx_l2_ptype { 950 I40E_RX_PTYPE_L2_RESERVED = 0, 951 I40E_RX_PTYPE_L2_MAC_PAY2 = 1, 952 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2, 953 I40E_RX_PTYPE_L2_FIP_PAY2 = 3, 954 I40E_RX_PTYPE_L2_OUI_PAY2 = 4, 955 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5, 956 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6, 957 I40E_RX_PTYPE_L2_ECP_PAY2 = 7, 958 I40E_RX_PTYPE_L2_EVB_PAY2 = 8, 959 I40E_RX_PTYPE_L2_QCN_PAY2 = 9, 960 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10, 961 I40E_RX_PTYPE_L2_ARP = 11, 962 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12, 963 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13, 964 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14, 965 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15, 966 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16, 967 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17, 968 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18, 969 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19, 970 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20, 971 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21, 972 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58, 973 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87, 974 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124, 975 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153, 976 I40E_RX_PTYPE_PARSER_ABORTED = 255 977 }; 978 979 struct i40e_rx_ptype_decoded { 980 u32 ptype:8; 981 u32 known:1; 982 u32 outer_ip:1; 983 u32 outer_ip_ver:1; 984 u32 outer_frag:1; 985 u32 tunnel_type:3; 986 u32 tunnel_end_prot:2; 987 u32 tunnel_end_frag:1; 988 u32 inner_prot:4; 989 u32 payload_layer:3; 990 }; 991 992 enum i40e_rx_ptype_outer_ip { 993 I40E_RX_PTYPE_OUTER_L2 = 0, 994 I40E_RX_PTYPE_OUTER_IP = 1 995 }; 996 997 enum i40e_rx_ptype_outer_ip_ver { 998 I40E_RX_PTYPE_OUTER_NONE = 0, 999 I40E_RX_PTYPE_OUTER_IPV4 = 0, 1000 I40E_RX_PTYPE_OUTER_IPV6 = 1 1001 }; 1002 1003 enum i40e_rx_ptype_outer_fragmented { 1004 I40E_RX_PTYPE_NOT_FRAG = 0, 1005 I40E_RX_PTYPE_FRAG = 1 1006 }; 1007 1008 enum i40e_rx_ptype_tunnel_type { 1009 I40E_RX_PTYPE_TUNNEL_NONE = 0, 1010 I40E_RX_PTYPE_TUNNEL_IP_IP = 1, 1011 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2, 1012 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3, 1013 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4, 1014 }; 1015 1016 enum i40e_rx_ptype_tunnel_end_prot { 1017 I40E_RX_PTYPE_TUNNEL_END_NONE = 0, 1018 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1, 1019 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2, 1020 }; 1021 1022 enum i40e_rx_ptype_inner_prot { 1023 I40E_RX_PTYPE_INNER_PROT_NONE = 0, 1024 I40E_RX_PTYPE_INNER_PROT_UDP = 1, 1025 I40E_RX_PTYPE_INNER_PROT_TCP = 2, 1026 I40E_RX_PTYPE_INNER_PROT_SCTP = 3, 1027 I40E_RX_PTYPE_INNER_PROT_ICMP = 4, 1028 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5 1029 }; 1030 1031 enum i40e_rx_ptype_payload_layer { 1032 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0, 1033 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1, 1034 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2, 1035 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3, 1036 }; 1037 1038 #define I40E_RX_PTYPE_BIT_MASK 0x0FFFFFFF 1039 #define I40E_RX_PTYPE_SHIFT 56 1040 1041 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38 1042 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \ 1043 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) 1044 1045 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52 1046 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \ 1047 I40E_RXD_QW1_LENGTH_HBUF_SHIFT) 1048 1049 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63 1050 #define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT) 1051 1052 #define I40E_RXD_QW1_NEXTP_SHIFT 38 1053 #define I40E_RXD_QW1_NEXTP_MASK (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT) 1054 1055 #define I40E_RXD_QW2_EXT_STATUS_SHIFT 0 1056 #define I40E_RXD_QW2_EXT_STATUS_MASK (0xFFFFFUL << \ 1057 I40E_RXD_QW2_EXT_STATUS_SHIFT) 1058 1059 enum i40e_rx_desc_ext_status_bits { 1060 /* Note: These are predefined bit offsets */ 1061 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0, 1062 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1, 1063 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */ 1064 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */ 1065 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9, 1066 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10, 1067 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11, 1068 }; 1069 1070 #define I40E_RXD_QW2_L2TAG2_SHIFT 0 1071 #define I40E_RXD_QW2_L2TAG2_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT) 1072 1073 #define I40E_RXD_QW2_L2TAG3_SHIFT 16 1074 #define I40E_RXD_QW2_L2TAG3_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT) 1075 1076 enum i40e_rx_desc_pe_status_bits { 1077 /* Note: These are predefined bit offsets */ 1078 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */ 1079 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */ 1080 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */ 1081 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24, 1082 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25, 1083 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26, 1084 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27, 1085 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28, 1086 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29 1087 }; 1088 1089 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38 1090 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000 1091 1092 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2 1093 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \ 1094 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT) 1095 1096 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT 0 1097 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK (0x7FFFUL << \ 1098 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT) 1099 1100 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19 1101 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \ 1102 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT) 1103 1104 enum i40e_rx_prog_status_desc_status_bits { 1105 /* Note: These are predefined bit offsets */ 1106 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0, 1107 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */ 1108 }; 1109 1110 enum i40e_rx_prog_status_desc_prog_id_masks { 1111 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1, 1112 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2, 1113 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4, 1114 }; 1115 1116 enum i40e_rx_prog_status_desc_error_bits { 1117 /* Note: These are predefined bit offsets */ 1118 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0, 1119 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1, 1120 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2, 1121 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3 1122 }; 1123 1124 #define I40E_TWO_BIT_MASK 0x3 1125 #define I40E_THREE_BIT_MASK 0x7 1126 #define I40E_FOUR_BIT_MASK 0xF 1127 #define I40E_EIGHTEEN_BIT_MASK 0x3FFFF 1128 1129 /* TX Descriptor */ 1130 struct i40e_tx_desc { 1131 __le64 buffer_addr; /* Address of descriptor's data buf */ 1132 __le64 cmd_type_offset_bsz; 1133 }; 1134 1135 #define I40E_TXD_QW1_DTYPE_SHIFT 0 1136 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT) 1137 1138 enum i40e_tx_desc_dtype_value { 1139 I40E_TX_DESC_DTYPE_DATA = 0x0, 1140 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */ 1141 I40E_TX_DESC_DTYPE_CONTEXT = 0x1, 1142 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2, 1143 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8, 1144 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9, 1145 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB, 1146 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC, 1147 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD, 1148 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF 1149 }; 1150 1151 #define I40E_TXD_QW1_CMD_SHIFT 4 1152 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT) 1153 1154 enum i40e_tx_desc_cmd_bits { 1155 I40E_TX_DESC_CMD_EOP = 0x0001, 1156 I40E_TX_DESC_CMD_RS = 0x0002, 1157 I40E_TX_DESC_CMD_ICRC = 0x0004, 1158 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008, 1159 I40E_TX_DESC_CMD_DUMMY = 0x0010, 1160 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */ 1161 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */ 1162 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */ 1163 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */ 1164 I40E_TX_DESC_CMD_FCOET = 0x0080, 1165 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */ 1166 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */ 1167 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */ 1168 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */ 1169 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */ 1170 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */ 1171 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */ 1172 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */ 1173 }; 1174 1175 #define I40E_TXD_QW1_OFFSET_SHIFT 16 1176 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \ 1177 I40E_TXD_QW1_OFFSET_SHIFT) 1178 1179 enum i40e_tx_desc_length_fields { 1180 /* Note: These are predefined bit offsets */ 1181 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */ 1182 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */ 1183 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */ 1184 }; 1185 1186 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT) 1187 #define I40E_TXD_QW1_IPLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT) 1188 #define I40E_TXD_QW1_L4LEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT) 1189 #define I40E_TXD_QW1_FCLEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT) 1190 1191 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34 1192 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \ 1193 I40E_TXD_QW1_TX_BUF_SZ_SHIFT) 1194 1195 #define I40E_TXD_QW1_L2TAG1_SHIFT 48 1196 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT) 1197 1198 /* Context descriptors */ 1199 struct i40e_tx_context_desc { 1200 __le32 tunneling_params; 1201 __le16 l2tag2; 1202 __le16 rsvd; 1203 __le64 type_cmd_tso_mss; 1204 }; 1205 1206 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0 1207 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT) 1208 1209 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4 1210 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT) 1211 1212 enum i40e_tx_ctx_desc_cmd_bits { 1213 I40E_TX_CTX_DESC_TSO = 0x01, 1214 I40E_TX_CTX_DESC_TSYN = 0x02, 1215 I40E_TX_CTX_DESC_IL2TAG2 = 0x04, 1216 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08, 1217 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00, 1218 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10, 1219 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20, 1220 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30, 1221 I40E_TX_CTX_DESC_SWPE = 0x40 1222 }; 1223 1224 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30 1225 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \ 1226 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) 1227 1228 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50 1229 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \ 1230 I40E_TXD_CTX_QW1_MSS_SHIFT) 1231 1232 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50 1233 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT) 1234 1235 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0 1236 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \ 1237 I40E_TXD_CTX_QW0_EXT_IP_SHIFT) 1238 1239 enum i40e_tx_ctx_desc_eipt_offload { 1240 I40E_TX_CTX_EXT_IP_NONE = 0x0, 1241 I40E_TX_CTX_EXT_IP_IPV6 = 0x1, 1242 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2, 1243 I40E_TX_CTX_EXT_IP_IPV4 = 0x3 1244 }; 1245 1246 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2 1247 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \ 1248 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT) 1249 1250 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9 1251 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT) 1252 1253 #define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT) 1254 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT) 1255 1256 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11 1257 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT) 1258 1259 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK 1260 1261 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12 1262 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \ 1263 I40E_TXD_CTX_QW0_NATLEN_SHIFT) 1264 1265 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19 1266 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \ 1267 I40E_TXD_CTX_QW0_DECTTL_SHIFT) 1268 1269 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23 1270 #define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT) 1271 struct i40e_nop_desc { 1272 __le64 rsvd; 1273 __le64 dtype_cmd; 1274 }; 1275 1276 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT 0 1277 #define I40E_TXD_NOP_QW1_DTYPE_MASK (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT) 1278 1279 #define I40E_TXD_NOP_QW1_CMD_SHIFT 4 1280 #define I40E_TXD_NOP_QW1_CMD_MASK (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT) 1281 1282 enum i40e_tx_nop_desc_cmd_bits { 1283 /* Note: These are predefined bit offsets */ 1284 I40E_TX_NOP_DESC_EOP_SHIFT = 0, 1285 I40E_TX_NOP_DESC_RS_SHIFT = 1, 1286 I40E_TX_NOP_DESC_RSV_SHIFT = 2 /* 5 bits */ 1287 }; 1288 1289 struct i40e_filter_program_desc { 1290 __le32 qindex_flex_ptype_vsi; 1291 __le32 rsvd; 1292 __le32 dtype_cmd_cntindex; 1293 __le32 fd_id; 1294 }; 1295 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0 1296 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \ 1297 I40E_TXD_FLTR_QW0_QINDEX_SHIFT) 1298 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11 1299 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \ 1300 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) 1301 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17 1302 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \ 1303 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) 1304 1305 /* Packet Classifier Types for filters */ 1306 enum i40e_filter_pctype { 1307 /* Note: Values 0-28 are reserved for future use. 1308 * Value 29, 30, 32 are not supported on XL710 and X710. 1309 */ 1310 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29, 1311 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30, 1312 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31, 1313 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32, 1314 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33, 1315 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34, 1316 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35, 1317 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36, 1318 /* Note: Values 37-38 are reserved for future use. 1319 * Value 39, 40, 42 are not supported on XL710 and X710. 1320 */ 1321 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39, 1322 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40, 1323 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41, 1324 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42, 1325 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43, 1326 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44, 1327 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45, 1328 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46, 1329 /* Note: Value 47 is reserved for future use */ 1330 I40E_FILTER_PCTYPE_FCOE_OX = 48, 1331 I40E_FILTER_PCTYPE_FCOE_RX = 49, 1332 I40E_FILTER_PCTYPE_FCOE_OTHER = 50, 1333 /* Note: Values 51-62 are reserved for future use */ 1334 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63, 1335 }; 1336 1337 enum i40e_filter_program_desc_dest { 1338 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0, 1339 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1, 1340 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2, 1341 }; 1342 1343 enum i40e_filter_program_desc_fd_status { 1344 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0, 1345 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1, 1346 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2, 1347 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3, 1348 }; 1349 1350 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23 1351 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \ 1352 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) 1353 1354 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT 0 1355 #define I40E_TXD_FLTR_QW1_DTYPE_MASK (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT) 1356 1357 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4 1358 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \ 1359 I40E_TXD_FLTR_QW1_CMD_SHIFT) 1360 1361 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) 1362 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT) 1363 1364 enum i40e_filter_program_desc_pcmd { 1365 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1, 1366 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2, 1367 }; 1368 1369 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) 1370 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT) 1371 1372 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) 1373 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT) 1374 1375 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \ 1376 I40E_TXD_FLTR_QW1_CMD_SHIFT) 1377 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \ 1378 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) 1379 1380 #define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \ 1381 I40E_TXD_FLTR_QW1_CMD_SHIFT) 1382 #define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT) 1383 1384 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20 1385 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \ 1386 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) 1387 1388 enum i40e_filter_type { 1389 I40E_FLOW_DIRECTOR_FLTR = 0, 1390 I40E_PE_QUAD_HASH_FLTR = 1, 1391 I40E_ETHERTYPE_FLTR, 1392 I40E_FCOE_CTX_FLTR, 1393 I40E_MAC_VLAN_FLTR, 1394 I40E_HASH_FLTR 1395 }; 1396 1397 struct i40e_vsi_context { 1398 u16 seid; 1399 u16 uplink_seid; 1400 u16 vsi_number; 1401 u16 vsis_allocated; 1402 u16 vsis_unallocated; 1403 u16 flags; 1404 u8 pf_num; 1405 u8 vf_num; 1406 u8 connection_type; 1407 struct i40e_aqc_vsi_properties_data info; 1408 }; 1409 1410 struct i40e_veb_context { 1411 u16 seid; 1412 u16 uplink_seid; 1413 u16 veb_number; 1414 u16 vebs_allocated; 1415 u16 vebs_unallocated; 1416 u16 flags; 1417 struct i40e_aqc_get_veb_parameters_completion info; 1418 }; 1419 1420 /* Statistics collected by each port, VSI, VEB, and S-channel */ 1421 struct i40e_eth_stats { 1422 u64 rx_bytes; /* gorc */ 1423 u64 rx_unicast; /* uprc */ 1424 u64 rx_multicast; /* mprc */ 1425 u64 rx_broadcast; /* bprc */ 1426 u64 rx_discards; /* rdpc */ 1427 u64 rx_unknown_protocol; /* rupp */ 1428 u64 tx_bytes; /* gotc */ 1429 u64 tx_unicast; /* uptc */ 1430 u64 tx_multicast; /* mptc */ 1431 u64 tx_broadcast; /* bptc */ 1432 u64 tx_discards; /* tdpc */ 1433 u64 tx_errors; /* tepc */ 1434 }; 1435 1436 /* Statistics collected per VEB per TC */ 1437 struct i40e_veb_tc_stats { 1438 u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS]; 1439 u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS]; 1440 u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS]; 1441 u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS]; 1442 }; 1443 1444 /* Statistics collected by the MAC */ 1445 struct i40e_hw_port_stats { 1446 /* eth stats collected by the port */ 1447 struct i40e_eth_stats eth; 1448 1449 /* additional port specific stats */ 1450 u64 tx_dropped_link_down; /* tdold */ 1451 u64 crc_errors; /* crcerrs */ 1452 u64 illegal_bytes; /* illerrc */ 1453 u64 error_bytes; /* errbc */ 1454 u64 mac_local_faults; /* mlfc */ 1455 u64 mac_remote_faults; /* mrfc */ 1456 u64 rx_length_errors; /* rlec */ 1457 u64 link_xon_rx; /* lxonrxc */ 1458 u64 link_xoff_rx; /* lxoffrxc */ 1459 u64 priority_xon_rx[8]; /* pxonrxc[8] */ 1460 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */ 1461 u64 link_xon_tx; /* lxontxc */ 1462 u64 link_xoff_tx; /* lxofftxc */ 1463 u64 priority_xon_tx[8]; /* pxontxc[8] */ 1464 u64 priority_xoff_tx[8]; /* pxofftxc[8] */ 1465 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */ 1466 u64 rx_size_64; /* prc64 */ 1467 u64 rx_size_127; /* prc127 */ 1468 u64 rx_size_255; /* prc255 */ 1469 u64 rx_size_511; /* prc511 */ 1470 u64 rx_size_1023; /* prc1023 */ 1471 u64 rx_size_1522; /* prc1522 */ 1472 u64 rx_size_big; /* prc9522 */ 1473 u64 rx_undersize; /* ruc */ 1474 u64 rx_fragments; /* rfc */ 1475 u64 rx_oversize; /* roc */ 1476 u64 rx_jabber; /* rjc */ 1477 u64 tx_size_64; /* ptc64 */ 1478 u64 tx_size_127; /* ptc127 */ 1479 u64 tx_size_255; /* ptc255 */ 1480 u64 tx_size_511; /* ptc511 */ 1481 u64 tx_size_1023; /* ptc1023 */ 1482 u64 tx_size_1522; /* ptc1522 */ 1483 u64 tx_size_big; /* ptc9522 */ 1484 u64 mac_short_packet_dropped; /* mspdc */ 1485 u64 checksum_error; /* xec */ 1486 /* flow director stats */ 1487 u64 fd_atr_match; 1488 u64 fd_sb_match; 1489 u64 fd_atr_tunnel_match; 1490 u32 fd_atr_status; 1491 u32 fd_sb_status; 1492 /* EEE LPI */ 1493 u32 tx_lpi_status; 1494 u32 rx_lpi_status; 1495 u64 tx_lpi_count; /* etlpic */ 1496 u64 rx_lpi_count; /* erlpic */ 1497 u64 tx_lpi_duration; 1498 u64 rx_lpi_duration; 1499 }; 1500 1501 /* Checksum and Shadow RAM pointers */ 1502 #define I40E_SR_NVM_CONTROL_WORD 0x00 1503 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR 0x03 1504 #define I40E_SR_PHY_ANALOG_CONFIG_PTR 0x04 1505 #define I40E_SR_OPTION_ROM_PTR 0x05 1506 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06 1507 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR 0x07 1508 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08 1509 #define I40E_SR_EMP_GLOBAL_MODULE_PTR 0x09 1510 #define I40E_SR_RO_PCIE_LCB_PTR 0x0A 1511 #define I40E_SR_EMP_IMAGE_PTR 0x0B 1512 #define I40E_SR_PE_IMAGE_PTR 0x0C 1513 #define I40E_SR_CSR_PROTECTED_LIST_PTR 0x0D 1514 #define I40E_SR_MNG_CONFIG_PTR 0x0E 1515 #define I40E_EMP_MODULE_PTR 0x0F 1516 #define I40E_SR_EMP_MODULE_PTR 0x48 1517 #define I40E_SR_PBA_FLAGS 0x15 1518 #define I40E_SR_PBA_BLOCK_PTR 0x16 1519 #define I40E_SR_BOOT_CONFIG_PTR 0x17 1520 #define I40E_NVM_OEM_VER_OFF 0x83 1521 #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18 1522 #define I40E_SR_NVM_WAKE_ON_LAN 0x19 1523 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27 1524 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR 0x28 1525 #define I40E_SR_NVM_MAP_VERSION 0x29 1526 #define I40E_SR_NVM_IMAGE_VERSION 0x2A 1527 #define I40E_SR_NVM_STRUCTURE_VERSION 0x2B 1528 #define I40E_SR_NVM_EETRACK_LO 0x2D 1529 #define I40E_SR_NVM_EETRACK_HI 0x2E 1530 #define I40E_SR_VPD_PTR 0x2F 1531 #define I40E_SR_PXE_SETUP_PTR 0x30 1532 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR 0x31 1533 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO 0x34 1534 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI 0x35 1535 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR 0x37 1536 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR 0x38 1537 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A 1538 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B 1539 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C 1540 #define I40E_SR_PHY_ACTIVITY_LIST_PTR 0x3D 1541 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E 1542 #define I40E_SR_SW_CHECKSUM_WORD 0x3F 1543 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR 0x40 1544 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR 0x42 1545 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR 0x44 1546 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR 0x46 1547 #define I40E_SR_EMP_SR_SETTINGS_PTR 0x48 1548 #define I40E_SR_FEATURE_CONFIGURATION_PTR 0x49 1549 #define I40E_SR_CONFIGURATION_METADATA_PTR 0x4D 1550 #define I40E_SR_IMMEDIATE_VALUES_PTR 0x4E 1551 #define I40E_SR_5TH_FREE_PROVISION_AREA_PTR 0x50 1552 #define I40E_SR_PRESERVATION_RULES_PTR 0x70 1553 #define I40E_FPK_SR_5TH_FREE_PROVISION_AREA_PTR 0x71 1554 #define I40E_SR_6TH_FREE_PROVISION_AREA_PTR 0x71 1555 1556 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */ 1557 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024 1558 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024 1559 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06 1560 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT) 1561 #define I40E_SR_CONTROL_WORD_1_NVM_BANK_VALID BIT(5) 1562 #define I40E_SR_NVM_MAP_STRUCTURE_TYPE BIT(12) 1563 #define I40E_PTR_TYPE BIT(15) 1564 #define I40E_SR_OCP_CFG_WORD0 0x2B 1565 #define I40E_SR_OCP_ENABLED BIT(15) 1566 1567 /* Shadow RAM related */ 1568 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800 1569 #define I40E_SR_BUF_ALIGNMENT 4096 1570 #define I40E_SR_WORDS_IN_1KB 512 1571 /* Checksum should be calculated such that after adding all the words, 1572 * including the checksum word itself, the sum should be 0xBABA. 1573 */ 1574 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA 1575 1576 #define I40E_SRRD_SRCTL_ATTEMPTS 100000 1577 1578 enum i40e_switch_element_types { 1579 I40E_SWITCH_ELEMENT_TYPE_MAC = 1, 1580 I40E_SWITCH_ELEMENT_TYPE_PF = 2, 1581 I40E_SWITCH_ELEMENT_TYPE_VF = 3, 1582 I40E_SWITCH_ELEMENT_TYPE_EMP = 4, 1583 I40E_SWITCH_ELEMENT_TYPE_BMC = 6, 1584 I40E_SWITCH_ELEMENT_TYPE_PE = 16, 1585 I40E_SWITCH_ELEMENT_TYPE_VEB = 17, 1586 I40E_SWITCH_ELEMENT_TYPE_PA = 18, 1587 I40E_SWITCH_ELEMENT_TYPE_VSI = 19, 1588 }; 1589 1590 /* Supported EtherType filters */ 1591 enum i40e_ether_type_index { 1592 I40E_ETHER_TYPE_1588 = 0, 1593 I40E_ETHER_TYPE_FIP = 1, 1594 I40E_ETHER_TYPE_OUI_EXTENDED = 2, 1595 I40E_ETHER_TYPE_MAC_CONTROL = 3, 1596 I40E_ETHER_TYPE_LLDP = 4, 1597 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5, 1598 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6, 1599 I40E_ETHER_TYPE_QCN_CNM = 7, 1600 I40E_ETHER_TYPE_8021X = 8, 1601 I40E_ETHER_TYPE_ARP = 9, 1602 I40E_ETHER_TYPE_RSV1 = 10, 1603 I40E_ETHER_TYPE_RSV2 = 11, 1604 }; 1605 1606 /* Filter context base size is 1K */ 1607 #define I40E_HASH_FILTER_BASE_SIZE 1024 1608 /* Supported Hash filter values */ 1609 enum i40e_hash_filter_size { 1610 I40E_HASH_FILTER_SIZE_1K = 0, 1611 I40E_HASH_FILTER_SIZE_2K = 1, 1612 I40E_HASH_FILTER_SIZE_4K = 2, 1613 I40E_HASH_FILTER_SIZE_8K = 3, 1614 I40E_HASH_FILTER_SIZE_16K = 4, 1615 I40E_HASH_FILTER_SIZE_32K = 5, 1616 I40E_HASH_FILTER_SIZE_64K = 6, 1617 I40E_HASH_FILTER_SIZE_128K = 7, 1618 I40E_HASH_FILTER_SIZE_256K = 8, 1619 I40E_HASH_FILTER_SIZE_512K = 9, 1620 I40E_HASH_FILTER_SIZE_1M = 10, 1621 }; 1622 1623 /* DMA context base size is 0.5K */ 1624 #define I40E_DMA_CNTX_BASE_SIZE 512 1625 /* Supported DMA context values */ 1626 enum i40e_dma_cntx_size { 1627 I40E_DMA_CNTX_SIZE_512 = 0, 1628 I40E_DMA_CNTX_SIZE_1K = 1, 1629 I40E_DMA_CNTX_SIZE_2K = 2, 1630 I40E_DMA_CNTX_SIZE_4K = 3, 1631 I40E_DMA_CNTX_SIZE_8K = 4, 1632 I40E_DMA_CNTX_SIZE_16K = 5, 1633 I40E_DMA_CNTX_SIZE_32K = 6, 1634 I40E_DMA_CNTX_SIZE_64K = 7, 1635 I40E_DMA_CNTX_SIZE_128K = 8, 1636 I40E_DMA_CNTX_SIZE_256K = 9, 1637 }; 1638 1639 /* Supported Hash look up table (LUT) sizes */ 1640 enum i40e_hash_lut_size { 1641 I40E_HASH_LUT_SIZE_128 = 0, 1642 I40E_HASH_LUT_SIZE_512 = 1, 1643 }; 1644 1645 /* Structure to hold a per PF filter control settings */ 1646 struct i40e_filter_control_settings { 1647 /* number of PE Quad Hash filter buckets */ 1648 enum i40e_hash_filter_size pe_filt_num; 1649 /* number of PE Quad Hash contexts */ 1650 enum i40e_dma_cntx_size pe_cntx_num; 1651 /* number of FCoE filter buckets */ 1652 enum i40e_hash_filter_size fcoe_filt_num; 1653 /* number of FCoE DDP contexts */ 1654 enum i40e_dma_cntx_size fcoe_cntx_num; 1655 /* size of the Hash LUT */ 1656 enum i40e_hash_lut_size hash_lut_size; 1657 /* enable FDIR filters for PF and its VFs */ 1658 bool enable_fdir; 1659 /* enable Ethertype filters for PF and its VFs */ 1660 bool enable_ethtype; 1661 /* enable MAC/VLAN filters for PF and its VFs */ 1662 bool enable_macvlan; 1663 }; 1664 1665 /* Structure to hold device level control filter counts */ 1666 struct i40e_control_filter_stats { 1667 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */ 1668 u16 etype_used; /* Used perfect EtherType filters */ 1669 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */ 1670 u16 etype_free; /* Un-used perfect EtherType filters */ 1671 }; 1672 1673 enum i40e_reset_type { 1674 I40E_RESET_POR = 0, 1675 I40E_RESET_CORER = 1, 1676 I40E_RESET_GLOBR = 2, 1677 I40E_RESET_EMPR = 3, 1678 }; 1679 1680 /* IEEE 802.1AB LLDP Agent Variables from NVM */ 1681 #define I40E_NVM_LLDP_CFG_PTR 0x06 1682 #define I40E_SR_LLDP_CFG_PTR 0x31 1683 struct i40e_lldp_variables { 1684 u16 length; 1685 u16 adminstatus; 1686 u16 msgfasttx; 1687 u16 msgtxinterval; 1688 u16 txparams; 1689 u16 timers; 1690 u16 crc8; 1691 }; 1692 1693 /* Offsets into Alternate Ram */ 1694 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */ 1695 #define I40E_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */ 1696 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */ 1697 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */ 1698 #define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */ 1699 #define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */ 1700 1701 /* Alternate Ram Bandwidth Masks */ 1702 #define I40E_ALT_BW_VALUE_MASK 0xFF 1703 #define I40E_ALT_BW_RELATIVE_MASK 0x40000000 1704 #define I40E_ALT_BW_VALID_MASK 0x80000000 1705 1706 /* RSS Hash Table Size */ 1707 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000 1708 1709 /* INPUT SET MASK for RSS, flow director, and flexible payload */ 1710 #define I40E_L3_SRC_SHIFT 47 1711 #define I40E_L3_SRC_MASK (0x3ULL << I40E_L3_SRC_SHIFT) 1712 #define I40E_L3_V6_SRC_SHIFT 43 1713 #define I40E_L3_V6_SRC_MASK (0xFFULL << I40E_L3_V6_SRC_SHIFT) 1714 #define I40E_L3_DST_SHIFT 35 1715 #define I40E_L3_DST_MASK (0x3ULL << I40E_L3_DST_SHIFT) 1716 #define I40E_L3_V6_DST_SHIFT 35 1717 #define I40E_L3_V6_DST_MASK (0xFFULL << I40E_L3_V6_DST_SHIFT) 1718 #define I40E_L4_SRC_SHIFT 34 1719 #define I40E_L4_SRC_MASK (0x1ULL << I40E_L4_SRC_SHIFT) 1720 #define I40E_L4_DST_SHIFT 33 1721 #define I40E_L4_DST_MASK (0x1ULL << I40E_L4_DST_SHIFT) 1722 #define I40E_VERIFY_TAG_SHIFT 31 1723 #define I40E_VERIFY_TAG_MASK (0x3ULL << I40E_VERIFY_TAG_SHIFT) 1724 #define I40E_VLAN_SRC_SHIFT 55 1725 #define I40E_VLAN_SRC_MASK (0x1ULL << I40E_VLAN_SRC_SHIFT) 1726 1727 #define I40E_FLEX_50_SHIFT 13 1728 #define I40E_FLEX_50_MASK (0x1ULL << I40E_FLEX_50_SHIFT) 1729 #define I40E_FLEX_51_SHIFT 12 1730 #define I40E_FLEX_51_MASK (0x1ULL << I40E_FLEX_51_SHIFT) 1731 #define I40E_FLEX_52_SHIFT 11 1732 #define I40E_FLEX_52_MASK (0x1ULL << I40E_FLEX_52_SHIFT) 1733 #define I40E_FLEX_53_SHIFT 10 1734 #define I40E_FLEX_53_MASK (0x1ULL << I40E_FLEX_53_SHIFT) 1735 #define I40E_FLEX_54_SHIFT 9 1736 #define I40E_FLEX_54_MASK (0x1ULL << I40E_FLEX_54_SHIFT) 1737 #define I40E_FLEX_55_SHIFT 8 1738 #define I40E_FLEX_55_MASK (0x1ULL << I40E_FLEX_55_SHIFT) 1739 #define I40E_FLEX_56_SHIFT 7 1740 #define I40E_FLEX_56_MASK (0x1ULL << I40E_FLEX_56_SHIFT) 1741 #define I40E_FLEX_57_SHIFT 6 1742 #define I40E_FLEX_57_MASK (0x1ULL << I40E_FLEX_57_SHIFT) 1743 #define I40E_BCM_PHY_PCS_STATUS1_PAGE 0x3 1744 #define I40E_BCM_PHY_PCS_STATUS1_REG 0x0001 1745 #define I40E_BCM_PHY_PCS_STATUS1_RX_LPI BIT(8) 1746 #define I40E_BCM_PHY_PCS_STATUS1_TX_LPI BIT(9) 1747 1748 #endif /* _I40E_TYPE_H_ */ 1749