1 /*- 2 * Copyright (c) 2013-2019, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef MLX5_DEVICE_H 29 #define MLX5_DEVICE_H 30 31 #include <linux/types.h> 32 #include <rdma/ib_verbs.h> 33 #include <dev/mlx5/mlx5_ifc.h> 34 35 #define FW_INIT_TIMEOUT_MILI 2000 36 #define FW_INIT_WAIT_MS 2 37 #define FW_PRE_INIT_TIMEOUT_MILI 120000 38 #define FW_INIT_WARN_MESSAGE_INTERVAL 20000 39 40 #if defined(__LITTLE_ENDIAN) 41 #define MLX5_SET_HOST_ENDIANNESS 0 42 #elif defined(__BIG_ENDIAN) 43 #define MLX5_SET_HOST_ENDIANNESS 0x80 44 #else 45 #error Host endianness not defined 46 #endif 47 48 /* helper macros */ 49 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0) 50 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld) 51 #define __mlx5_bit_off(typ, fld) __offsetof(struct mlx5_ifc_##typ##_bits, fld) 52 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16) 53 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32) 54 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64) 55 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf)) 56 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f)) 57 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 58 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld)) 59 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 60 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << __mlx5_16_bit_off(typ, fld)) 61 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits) 62 63 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8) 64 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8) 65 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32) 66 #define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64) 67 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8) 68 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32) 69 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8) 70 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld)) 71 72 /* insert a value to a struct */ 73 #define MLX5_SET(typ, p, fld, v) do { \ 74 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 75 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \ 76 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 77 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 78 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \ 79 << __mlx5_dw_bit_off(typ, fld))); \ 80 } while (0) 81 82 #define MLX5_SET_TO_ONES(typ, p, fld) do { \ 83 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 84 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \ 85 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 86 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 87 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \ 88 << __mlx5_dw_bit_off(typ, fld))); \ 89 } while (0) 90 91 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\ 92 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 93 __mlx5_mask(typ, fld)) 94 95 #define MLX5_GET_PR(typ, p, fld) ({ \ 96 u32 ___t = MLX5_GET(typ, p, fld); \ 97 pr_debug(#fld " = 0x%x\n", ___t); \ 98 ___t; \ 99 }) 100 101 #define __MLX5_SET64(typ, p, fld, v) do { \ 102 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \ 103 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \ 104 } while (0) 105 106 #define MLX5_SET64(typ, p, fld, v) do { \ 107 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ 108 __MLX5_SET64(typ, p, fld, v); \ 109 } while (0) 110 111 #define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \ 112 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ 113 __MLX5_SET64(typ, p, fld[idx], v); \ 114 } while (0) 115 116 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld))) 117 118 #define MLX5_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) +\ 119 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \ 120 __mlx5_mask16(typ, fld)) 121 122 #define MLX5_SET16(typ, p, fld, v) do { \ 123 u16 _v = v; \ 124 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 16); \ 125 *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \ 126 cpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __mlx5_16_off(typ, fld))) & \ 127 (~__mlx5_16_mask(typ, fld))) | (((_v) & __mlx5_mask16(typ, fld)) \ 128 << __mlx5_16_bit_off(typ, fld))); \ 129 } while (0) 130 131 #define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\ 132 __mlx5_64_off(typ, fld))) 133 134 #define MLX5_GET_BE(type_t, typ, p, fld) ({ \ 135 type_t tmp; \ 136 switch (sizeof(tmp)) { \ 137 case sizeof(u8): \ 138 tmp = (__force type_t)MLX5_GET(typ, p, fld); \ 139 break; \ 140 case sizeof(u16): \ 141 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \ 142 break; \ 143 case sizeof(u32): \ 144 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \ 145 break; \ 146 case sizeof(u64): \ 147 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \ 148 break; \ 149 } \ 150 tmp; \ 151 }) 152 153 #define MLX5_BY_PASS_NUM_REGULAR_PRIOS 8 154 #define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 8 155 #define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1 156 #define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\ 157 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\ 158 MLX5_BY_PASS_NUM_MULTICAST_PRIOS) 159 160 /* insert a value to a struct */ 161 #define MLX5_VSC_SET(typ, p, fld, v) do { \ 162 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 163 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \ 164 *((__le32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 165 cpu_to_le32((le32_to_cpu(*((__le32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 166 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \ 167 << __mlx5_dw_bit_off(typ, fld))); \ 168 } while (0) 169 170 #define MLX5_VSC_GET(typ, p, fld) ((le32_to_cpu(*((__le32 *)(p) +\ 171 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 172 __mlx5_mask(typ, fld)) 173 174 #define MLX5_VSC_GET_PR(typ, p, fld) ({ \ 175 u32 ___t = MLX5_VSC_GET(typ, p, fld); \ 176 pr_debug(#fld " = 0x%x\n", ___t); \ 177 ___t; \ 178 }) 179 180 enum { 181 MLX5_MAX_COMMANDS = 32, 182 MLX5_CMD_DATA_BLOCK_SIZE = 512, 183 MLX5_CMD_MBOX_SIZE = 1024, 184 MLX5_PCI_CMD_XPORT = 7, 185 MLX5_MKEY_BSF_OCTO_SIZE = 4, 186 MLX5_MAX_PSVS = 4, 187 }; 188 189 enum { 190 MLX5_EXTENDED_UD_AV = 0x80000000, 191 }; 192 193 enum { 194 MLX5_CQ_FLAGS_OI = 2, 195 }; 196 197 enum { 198 MLX5_STAT_RATE_OFFSET = 5, 199 }; 200 201 enum { 202 MLX5_INLINE_SEG = 0x80000000, 203 }; 204 205 enum { 206 MLX5_HW_START_PADDING = MLX5_INLINE_SEG, 207 }; 208 209 enum { 210 MLX5_MIN_PKEY_TABLE_SIZE = 128, 211 MLX5_MAX_LOG_PKEY_TABLE = 5, 212 }; 213 214 enum { 215 MLX5_MKEY_INBOX_PG_ACCESS = 1U << 31 216 }; 217 218 enum { 219 MLX5_PERM_LOCAL_READ = 1 << 2, 220 MLX5_PERM_LOCAL_WRITE = 1 << 3, 221 MLX5_PERM_REMOTE_READ = 1 << 4, 222 MLX5_PERM_REMOTE_WRITE = 1 << 5, 223 MLX5_PERM_ATOMIC = 1 << 6, 224 MLX5_PERM_UMR_EN = 1 << 7, 225 }; 226 227 enum { 228 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0, 229 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2, 230 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3, 231 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6, 232 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4, 233 }; 234 235 enum { 236 MLX5_MKEY_REMOTE_INVAL = 1 << 24, 237 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29, 238 MLX5_MKEY_BSF_EN = 1 << 30, 239 MLX5_MKEY_LEN64 = 1U << 31, 240 }; 241 242 enum { 243 MLX5_EN_RD = (u64)1, 244 MLX5_EN_WR = (u64)2 245 }; 246 247 enum { 248 MLX5_ADAPTER_PAGE_SHIFT = 12, 249 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT, 250 }; 251 252 enum { 253 MLX5_BFREGS_PER_UAR = 4, 254 MLX5_MAX_UARS = 1 << 8, 255 MLX5_NON_FP_BFREGS_PER_UAR = 2, 256 MLX5_FP_BFREGS_PER_UAR = MLX5_BFREGS_PER_UAR - 257 MLX5_NON_FP_BFREGS_PER_UAR, 258 MLX5_MAX_BFREGS = MLX5_MAX_UARS * 259 MLX5_NON_FP_BFREGS_PER_UAR, 260 MLX5_UARS_IN_PAGE = PAGE_SIZE / MLX5_ADAPTER_PAGE_SIZE, 261 MLX5_NON_FP_BFREGS_IN_PAGE = MLX5_NON_FP_BFREGS_PER_UAR * MLX5_UARS_IN_PAGE, 262 MLX5_MIN_DYN_BFREGS = 512, 263 MLX5_MAX_DYN_BFREGS = 1024, 264 }; 265 266 enum { 267 MLX5_MKEY_MASK_LEN = 1ull << 0, 268 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1, 269 MLX5_MKEY_MASK_START_ADDR = 1ull << 6, 270 MLX5_MKEY_MASK_PD = 1ull << 7, 271 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8, 272 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9, 273 MLX5_MKEY_MASK_BSF_EN = 1ull << 12, 274 MLX5_MKEY_MASK_KEY = 1ull << 13, 275 MLX5_MKEY_MASK_QPN = 1ull << 14, 276 MLX5_MKEY_MASK_LR = 1ull << 17, 277 MLX5_MKEY_MASK_LW = 1ull << 18, 278 MLX5_MKEY_MASK_RR = 1ull << 19, 279 MLX5_MKEY_MASK_RW = 1ull << 20, 280 MLX5_MKEY_MASK_A = 1ull << 21, 281 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23, 282 MLX5_MKEY_MASK_FREE = 1ull << 29, 283 }; 284 285 enum { 286 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4), 287 288 MLX5_UMR_CHECK_NOT_FREE = (1 << 5), 289 MLX5_UMR_CHECK_FREE = (2 << 5), 290 291 MLX5_UMR_INLINE = (1 << 7), 292 }; 293 294 #define MLX5_UMR_MTT_ALIGNMENT 0x40 295 #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1) 296 #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT 297 298 enum { 299 MLX5_EVENT_QUEUE_TYPE_QP = 0, 300 MLX5_EVENT_QUEUE_TYPE_RQ = 1, 301 MLX5_EVENT_QUEUE_TYPE_SQ = 2, 302 MLX5_EVENT_QUEUE_TYPE_DCT = 6, 303 }; 304 305 enum { 306 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1, 307 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4, 308 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5, 309 MLX5_PORT_CHANGE_SUBTYPE_LID = 6, 310 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7, 311 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8, 312 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9, 313 }; 314 315 enum { 316 MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX = 1, 317 MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE, 318 MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE, 319 MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE, 320 MLX5_MAX_INLINE_RECEIVE_SIZE = 64 321 }; 322 323 enum { 324 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3, 325 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 326 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 327 MLX5_DEV_CAP_FLAG_APM = 1LL << 17, 328 MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD = 1LL << 21, 329 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23, 330 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29, 331 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30, 332 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 33, 333 MLX5_DEV_CAP_FLAG_ROCE = 1LL << 34, 334 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37, 335 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40, 336 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46, 337 MLX5_DEV_CAP_FLAG_DRAIN_SIGERR = 1LL << 48, 338 }; 339 340 enum { 341 MLX5_ROCE_VERSION_1 = 0, 342 MLX5_ROCE_VERSION_1_5 = 1, 343 MLX5_ROCE_VERSION_2 = 2, 344 }; 345 346 enum { 347 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1, 348 MLX5_ROCE_VERSION_1_5_CAP = 1 << MLX5_ROCE_VERSION_1_5, 349 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2, 350 }; 351 352 enum { 353 MLX5_ROCE_L3_TYPE_IPV4 = 0, 354 MLX5_ROCE_L3_TYPE_IPV6 = 1, 355 }; 356 357 enum { 358 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1, 359 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2, 360 }; 361 362 enum { 363 MLX5_OPCODE_NOP = 0x00, 364 MLX5_OPCODE_SEND_INVAL = 0x01, 365 MLX5_OPCODE_RDMA_WRITE = 0x08, 366 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09, 367 MLX5_OPCODE_SEND = 0x0a, 368 MLX5_OPCODE_SEND_IMM = 0x0b, 369 MLX5_OPCODE_LSO = 0x0e, 370 MLX5_OPCODE_RDMA_READ = 0x10, 371 MLX5_OPCODE_ATOMIC_CS = 0x11, 372 MLX5_OPCODE_ATOMIC_FA = 0x12, 373 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14, 374 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15, 375 MLX5_OPCODE_BIND_MW = 0x18, 376 MLX5_OPCODE_CONFIG_CMD = 0x1f, 377 MLX5_OPCODE_DUMP = 0x23, 378 379 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 380 MLX5_RECV_OPCODE_SEND = 0x01, 381 MLX5_RECV_OPCODE_SEND_IMM = 0x02, 382 MLX5_RECV_OPCODE_SEND_INVAL = 0x03, 383 384 MLX5_CQE_OPCODE_ERROR = 0x1e, 385 MLX5_CQE_OPCODE_RESIZE = 0x16, 386 387 MLX5_OPCODE_SET_PSV = 0x20, 388 MLX5_OPCODE_GET_PSV = 0x21, 389 MLX5_OPCODE_CHECK_PSV = 0x22, 390 MLX5_OPCODE_RGET_PSV = 0x26, 391 MLX5_OPCODE_RCHECK_PSV = 0x27, 392 393 MLX5_OPCODE_UMR = 0x25, 394 395 MLX5_OPCODE_SIGNATURE_CANCELED = (1 << 15), 396 }; 397 398 enum { 399 MLX5_OPCODE_MOD_UMR_UMR = 0x0, 400 MLX5_OPCODE_MOD_UMR_TLS_TIS_STATIC_PARAMS = 0x1, 401 MLX5_OPCODE_MOD_UMR_TLS_TIR_STATIC_PARAMS = 0x2, 402 }; 403 404 enum { 405 MLX5_OPCODE_MOD_PSV_PSV = 0x0, 406 MLX5_OPCODE_MOD_PSV_TLS_TIS_PROGRESS_PARAMS = 0x1, 407 MLX5_OPCODE_MOD_PSV_TLS_TIR_PROGRESS_PARAMS = 0x2, 408 }; 409 410 enum { 411 MLX5_SET_PORT_RESET_QKEY = 0, 412 MLX5_SET_PORT_GUID0 = 16, 413 MLX5_SET_PORT_NODE_GUID = 17, 414 MLX5_SET_PORT_SYS_GUID = 18, 415 MLX5_SET_PORT_GID_TABLE = 19, 416 MLX5_SET_PORT_PKEY_TABLE = 20, 417 }; 418 419 enum { 420 MLX5_MAX_PAGE_SHIFT = 31 421 }; 422 423 enum { 424 MLX5_CAP_OFF_CMDIF_CSUM = 46, 425 }; 426 427 enum { 428 /* 429 * Max wqe size for rdma read is 512 bytes, so this 430 * limits our max_sge_rd as the wqe needs to fit: 431 * - ctrl segment (16 bytes) 432 * - rdma segment (16 bytes) 433 * - scatter elements (16 bytes each) 434 */ 435 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16 436 }; 437 438 struct mlx5_cmd_layout { 439 u8 type; 440 u8 rsvd0[3]; 441 __be32 inlen; 442 __be64 in_ptr; 443 __be32 in[4]; 444 __be32 out[4]; 445 __be64 out_ptr; 446 __be32 outlen; 447 u8 token; 448 u8 sig; 449 u8 rsvd1; 450 u8 status_own; 451 }; 452 453 enum mlx5_fatal_assert_bit_offsets { 454 MLX5_RFR_OFFSET = 31, 455 }; 456 457 struct mlx5_health_buffer { 458 __be32 assert_var[5]; 459 __be32 rsvd0[3]; 460 __be32 assert_exit_ptr; 461 __be32 assert_callra; 462 __be32 rsvd1[2]; 463 __be32 fw_ver; 464 __be32 hw_id; 465 __be32 rfr; 466 u8 irisc_index; 467 u8 synd; 468 __be16 ext_synd; 469 }; 470 471 enum mlx5_initializing_bit_offsets { 472 MLX5_FW_RESET_SUPPORTED_OFFSET = 30, 473 }; 474 475 enum mlx5_cmd_addr_l_sz_offset { 476 MLX5_NIC_IFC_OFFSET = 8, 477 }; 478 479 struct mlx5_init_seg { 480 __be32 fw_rev; 481 __be32 cmdif_rev_fw_sub; 482 __be32 rsvd0[2]; 483 __be32 cmdq_addr_h; 484 __be32 cmdq_addr_l_sz; 485 __be32 cmd_dbell; 486 __be32 rsvd1[120]; 487 __be32 initializing; 488 struct mlx5_health_buffer health; 489 __be32 rsvd2[880]; 490 __be32 internal_timer_h; 491 __be32 internal_timer_l; 492 __be32 rsvd3[2]; 493 __be32 health_counter; 494 __be32 rsvd4[1019]; 495 __be64 ieee1588_clk; 496 __be32 ieee1588_clk_type; 497 __be32 clr_intx; 498 }; 499 500 struct mlx5_eqe_comp { 501 __be32 reserved[6]; 502 __be32 cqn; 503 }; 504 505 struct mlx5_eqe_qp_srq { 506 __be32 reserved1[5]; 507 u8 type; 508 u8 reserved2[3]; 509 __be32 qp_srq_n; 510 }; 511 512 struct mlx5_eqe_cq_err { 513 __be32 cqn; 514 u8 reserved1[7]; 515 u8 syndrome; 516 }; 517 518 struct mlx5_eqe_xrq_err { 519 __be32 reserved1[5]; 520 __be32 type_xrqn; 521 __be32 reserved2; 522 }; 523 524 struct mlx5_eqe_port_state { 525 u8 reserved0[8]; 526 u8 port; 527 }; 528 529 struct mlx5_eqe_gpio { 530 __be32 reserved0[2]; 531 __be64 gpio_event; 532 }; 533 534 struct mlx5_eqe_congestion { 535 u8 type; 536 u8 rsvd0; 537 u8 congestion_level; 538 }; 539 540 struct mlx5_eqe_stall_vl { 541 u8 rsvd0[3]; 542 u8 port_vl; 543 }; 544 545 struct mlx5_eqe_cmd { 546 __be32 vector; 547 __be32 rsvd[6]; 548 }; 549 550 struct mlx5_eqe_page_req { 551 u8 rsvd0[2]; 552 __be16 func_id; 553 __be32 num_pages; 554 __be32 rsvd1[5]; 555 }; 556 557 struct mlx5_eqe_vport_change { 558 u8 rsvd0[2]; 559 __be16 vport_num; 560 __be32 rsvd1[6]; 561 }; 562 563 564 #define PORT_MODULE_EVENT_MODULE_STATUS_MASK 0xF 565 #define PORT_MODULE_EVENT_ERROR_TYPE_MASK 0xF 566 567 enum { 568 MLX5_MODULE_STATUS_PLUGGED_ENABLED = 0x1, 569 MLX5_MODULE_STATUS_UNPLUGGED = 0x2, 570 MLX5_MODULE_STATUS_ERROR = 0x3, 571 MLX5_MODULE_STATUS_NUM , 572 }; 573 574 enum { 575 MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED = 0x0, 576 MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE = 0x1, 577 MLX5_MODULE_EVENT_ERROR_BUS_STUCK = 0x2, 578 MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT = 0x3, 579 MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST = 0x4, 580 MLX5_MODULE_EVENT_ERROR_UNSUPPORTED_CABLE = 0x5, 581 MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE = 0x6, 582 MLX5_MODULE_EVENT_ERROR_CABLE_IS_SHORTED = 0x7, 583 MLX5_MODULE_EVENT_ERROR_PMD_TYPE_NOT_ENABLED = 0x8, 584 MLX5_MODULE_EVENT_ERROR_LASTER_TEC_FAILURE = 0x9, 585 MLX5_MODULE_EVENT_ERROR_HIGH_CURRENT = 0xa, 586 MLX5_MODULE_EVENT_ERROR_HIGH_VOLTAGE = 0xb, 587 MLX5_MODULE_EVENT_ERROR_PCIE_SYS_POWER_SLOT_EXCEEDED = 0xc, 588 MLX5_MODULE_EVENT_ERROR_HIGH_POWER = 0xd, 589 MLX5_MODULE_EVENT_ERROR_MODULE_STATE_MACHINE_FAULT = 0xe, 590 MLX5_MODULE_EVENT_ERROR_NUM , 591 }; 592 593 struct mlx5_eqe_port_module_event { 594 u8 rsvd0; 595 u8 module; 596 u8 rsvd1; 597 u8 module_status; 598 u8 rsvd2[2]; 599 u8 error_type; 600 }; 601 602 struct mlx5_eqe_general_notification_event { 603 u32 rq_user_index_delay_drop; 604 u32 rsvd0[6]; 605 }; 606 607 struct mlx5_eqe_dct { 608 __be32 reserved[6]; 609 __be32 dctn; 610 }; 611 612 struct mlx5_eqe_temp_warning { 613 __be64 sensor_warning_msb; 614 __be64 sensor_warning_lsb; 615 } __packed; 616 617 union ev_data { 618 __be32 raw[7]; 619 struct mlx5_eqe_cmd cmd; 620 struct mlx5_eqe_comp comp; 621 struct mlx5_eqe_qp_srq qp_srq; 622 struct mlx5_eqe_cq_err cq_err; 623 struct mlx5_eqe_port_state port; 624 struct mlx5_eqe_gpio gpio; 625 struct mlx5_eqe_congestion cong; 626 struct mlx5_eqe_stall_vl stall_vl; 627 struct mlx5_eqe_page_req req_pages; 628 struct mlx5_eqe_port_module_event port_module_event; 629 struct mlx5_eqe_vport_change vport_change; 630 struct mlx5_eqe_general_notification_event general_notifications; 631 struct mlx5_eqe_dct dct; 632 struct mlx5_eqe_temp_warning temp_warning; 633 struct mlx5_eqe_xrq_err xrq_err; 634 } __packed; 635 636 struct mlx5_eqe { 637 u8 rsvd0; 638 u8 type; 639 u8 rsvd1; 640 u8 sub_type; 641 __be32 rsvd2[7]; 642 union ev_data data; 643 __be16 rsvd3; 644 u8 signature; 645 u8 owner; 646 } __packed; 647 648 struct mlx5_cmd_prot_block { 649 u8 data[MLX5_CMD_DATA_BLOCK_SIZE]; 650 u8 rsvd0[48]; 651 __be64 next; 652 __be32 block_num; 653 u8 rsvd1; 654 u8 token; 655 u8 ctrl_sig; 656 u8 sig; 657 }; 658 659 #define MLX5_NUM_CMDS_IN_ADAPTER_PAGE \ 660 (MLX5_ADAPTER_PAGE_SIZE / MLX5_CMD_MBOX_SIZE) 661 CTASSERT(MLX5_CMD_MBOX_SIZE >= sizeof(struct mlx5_cmd_prot_block)); 662 CTASSERT(MLX5_CMD_MBOX_SIZE <= MLX5_ADAPTER_PAGE_SIZE); 663 664 enum { 665 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5, 666 }; 667 668 struct mlx5_err_cqe { 669 u8 rsvd0[32]; 670 __be32 srqn; 671 u8 rsvd1[18]; 672 u8 vendor_err_synd; 673 u8 syndrome; 674 __be32 s_wqe_opcode_qpn; 675 __be16 wqe_counter; 676 u8 signature; 677 u8 op_own; 678 }; 679 680 struct mlx5_cqe64 { 681 u8 tls_outer_l3_tunneled; 682 u8 rsvd0; 683 __be16 wqe_id; 684 u8 lro_tcppsh_abort_dupack; 685 u8 lro_min_ttl; 686 __be16 lro_tcp_win; 687 __be32 lro_ack_seq_num; 688 __be32 rss_hash_result; 689 u8 rss_hash_type; 690 u8 ml_path; 691 u8 rsvd20[2]; 692 __be16 check_sum; 693 __be16 slid; 694 __be32 flags_rqpn; 695 u8 hds_ip_ext; 696 u8 l4_hdr_type_etc; 697 __be16 vlan_info; 698 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */ 699 __be32 imm_inval_pkey; 700 u8 rsvd40[4]; 701 __be32 byte_cnt; 702 __be64 timestamp; 703 __be32 sop_drop_qpn; 704 __be16 wqe_counter; 705 u8 signature; 706 u8 op_own; 707 }; 708 709 #define MLX5_CQE_TSTMP_PTP (1ULL << 63) 710 711 static inline u8 get_cqe_opcode(struct mlx5_cqe64 *cqe) 712 { 713 return (cqe->op_own >> 4); 714 } 715 716 static inline bool get_cqe_lro_timestamp_valid(struct mlx5_cqe64 *cqe) 717 { 718 return (cqe->lro_tcppsh_abort_dupack >> 7) & 1; 719 } 720 721 static inline bool get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe) 722 { 723 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1; 724 } 725 726 static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe) 727 { 728 return (cqe->l4_hdr_type_etc >> 4) & 0x7; 729 } 730 731 static inline u16 get_cqe_vlan(struct mlx5_cqe64 *cqe) 732 { 733 return be16_to_cpu(cqe->vlan_info) & 0xfff; 734 } 735 736 static inline void get_cqe_smac(struct mlx5_cqe64 *cqe, u8 *smac) 737 { 738 memcpy(smac, &cqe->rss_hash_type , 4); 739 memcpy(smac + 4, &cqe->slid , 2); 740 } 741 742 static inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe) 743 { 744 return cqe->l4_hdr_type_etc & 0x1; 745 } 746 747 static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe) 748 { 749 return cqe->tls_outer_l3_tunneled & 0x1; 750 } 751 752 enum { 753 CQE_L4_HDR_TYPE_NONE = 0x0, 754 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1, 755 CQE_L4_HDR_TYPE_UDP = 0x2, 756 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3, 757 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4, 758 }; 759 760 enum { 761 /* source L3 hash types */ 762 CQE_RSS_SRC_HTYPE_IP = 0x3 << 0, 763 CQE_RSS_SRC_HTYPE_IPV4 = 0x1 << 0, 764 CQE_RSS_SRC_HTYPE_IPV6 = 0x2 << 0, 765 766 /* destination L3 hash types */ 767 CQE_RSS_DST_HTYPE_IP = 0x3 << 2, 768 CQE_RSS_DST_HTYPE_IPV4 = 0x1 << 2, 769 CQE_RSS_DST_HTYPE_IPV6 = 0x2 << 2, 770 771 /* source L4 hash types */ 772 CQE_RSS_SRC_HTYPE_L4 = 0x3 << 4, 773 CQE_RSS_SRC_HTYPE_TCP = 0x1 << 4, 774 CQE_RSS_SRC_HTYPE_UDP = 0x2 << 4, 775 CQE_RSS_SRC_HTYPE_IPSEC = 0x3 << 4, 776 777 /* destination L4 hash types */ 778 CQE_RSS_DST_HTYPE_L4 = 0x3 << 6, 779 CQE_RSS_DST_HTYPE_TCP = 0x1 << 6, 780 CQE_RSS_DST_HTYPE_UDP = 0x2 << 6, 781 CQE_RSS_DST_HTYPE_IPSEC = 0x3 << 6, 782 }; 783 784 enum { 785 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0, 786 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1, 787 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2, 788 }; 789 790 enum { 791 CQE_L2_OK = 1 << 0, 792 CQE_L3_OK = 1 << 1, 793 CQE_L4_OK = 1 << 2, 794 }; 795 796 struct mlx5_sig_err_cqe { 797 u8 rsvd0[16]; 798 __be32 expected_trans_sig; 799 __be32 actual_trans_sig; 800 __be32 expected_reftag; 801 __be32 actual_reftag; 802 __be16 syndrome; 803 u8 rsvd22[2]; 804 __be32 mkey; 805 __be64 err_offset; 806 u8 rsvd30[8]; 807 __be32 qpn; 808 u8 rsvd38[2]; 809 u8 signature; 810 u8 op_own; 811 }; 812 813 struct mlx5_wqe_srq_next_seg { 814 u8 rsvd0[2]; 815 __be16 next_wqe_index; 816 u8 signature; 817 u8 rsvd1[11]; 818 }; 819 820 union mlx5_ext_cqe { 821 struct ib_grh grh; 822 u8 inl[64]; 823 }; 824 825 struct mlx5_cqe128 { 826 union mlx5_ext_cqe inl_grh; 827 struct mlx5_cqe64 cqe64; 828 }; 829 830 enum { 831 MLX5_MKEY_STATUS_FREE = 1 << 6, 832 }; 833 834 struct mlx5_mkey_seg { 835 /* This is a two bit field occupying bits 31-30. 836 * bit 31 is always 0, 837 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation 838 */ 839 u8 status; 840 u8 pcie_control; 841 u8 flags; 842 u8 version; 843 __be32 qpn_mkey7_0; 844 u8 rsvd1[4]; 845 __be32 flags_pd; 846 __be64 start_addr; 847 __be64 len; 848 __be32 bsfs_octo_size; 849 u8 rsvd2[16]; 850 __be32 xlt_oct_size; 851 u8 rsvd3[3]; 852 u8 log2_page_size; 853 u8 rsvd4[4]; 854 }; 855 856 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 857 858 enum { 859 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0 860 }; 861 862 static inline int mlx5_host_is_le(void) 863 { 864 #if defined(__LITTLE_ENDIAN) 865 return 1; 866 #elif defined(__BIG_ENDIAN) 867 return 0; 868 #else 869 #error Host endianness not defined 870 #endif 871 } 872 873 #define MLX5_CMD_OP_MAX 0x939 874 875 enum { 876 VPORT_STATE_DOWN = 0x0, 877 VPORT_STATE_UP = 0x1, 878 VPORT_STATE_FOLLOW = 0x2, 879 }; 880 881 enum { 882 MLX5_L3_PROT_TYPE_IPV4 = 0, 883 MLX5_L3_PROT_TYPE_IPV6 = 1, 884 }; 885 886 enum { 887 MLX5_L4_PROT_TYPE_TCP = 0, 888 MLX5_L4_PROT_TYPE_UDP = 1, 889 }; 890 891 enum { 892 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0, 893 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1, 894 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2, 895 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3, 896 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4, 897 }; 898 899 enum { 900 MLX5_MATCH_OUTER_HEADERS = 1 << 0, 901 MLX5_MATCH_MISC_PARAMETERS = 1 << 1, 902 MLX5_MATCH_INNER_HEADERS = 1 << 2, 903 904 }; 905 906 enum { 907 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0, 908 MLX5_FLOW_TABLE_TYPE_EGRESS_ACL = 2, 909 MLX5_FLOW_TABLE_TYPE_INGRESS_ACL = 3, 910 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4, 911 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 5, 912 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 6, 913 MLX5_FLOW_TABLE_TYPE_NIC_RX_RDMA = 7, 914 }; 915 916 enum { 917 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_NONE = 0, 918 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_IF_NO_VLAN = 1, 919 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_OVERWRITE = 2 920 }; 921 922 enum { 923 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_SVLAN_STRIP = 1 << 0, 924 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_CVLAN_STRIP = 1 << 1, 925 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_SVLAN_INSERT = 1 << 2, 926 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_CVLAN_INSERT = 1 << 3 927 }; 928 929 enum { 930 MLX5_UC_ADDR_CHANGE = (1 << 0), 931 MLX5_MC_ADDR_CHANGE = (1 << 1), 932 MLX5_VLAN_CHANGE = (1 << 2), 933 MLX5_PROMISC_CHANGE = (1 << 3), 934 MLX5_MTU_CHANGE = (1 << 4), 935 }; 936 937 enum mlx5_list_type { 938 MLX5_NIC_VPORT_LIST_TYPE_UC = 0x0, 939 MLX5_NIC_VPORT_LIST_TYPE_MC = 0x1, 940 MLX5_NIC_VPORT_LIST_TYPE_VLAN = 0x2, 941 }; 942 943 enum { 944 MLX5_ESW_VPORT_ADMIN_STATE_DOWN = 0x0, 945 MLX5_ESW_VPORT_ADMIN_STATE_UP = 0x1, 946 MLX5_ESW_VPORT_ADMIN_STATE_AUTO = 0x2, 947 }; 948 949 /* MLX5 DEV CAPs */ 950 951 /* TODO: EAT.ME */ 952 enum mlx5_cap_mode { 953 HCA_CAP_OPMOD_GET_MAX = 0, 954 HCA_CAP_OPMOD_GET_CUR = 1, 955 }; 956 957 enum mlx5_cap_type { 958 MLX5_CAP_GENERAL = 0, 959 MLX5_CAP_ETHERNET_OFFLOADS, 960 MLX5_CAP_ODP, 961 MLX5_CAP_ATOMIC, 962 MLX5_CAP_ROCE, 963 MLX5_CAP_IPOIB_OFFLOADS, 964 MLX5_CAP_EOIB_OFFLOADS, 965 MLX5_CAP_FLOW_TABLE, 966 MLX5_CAP_ESWITCH_FLOW_TABLE, 967 MLX5_CAP_ESWITCH, 968 MLX5_CAP_SNAPSHOT, 969 MLX5_CAP_VECTOR_CALC, 970 MLX5_CAP_QOS, 971 MLX5_CAP_DEBUG, 972 MLX5_CAP_NVME, 973 MLX5_CAP_DMC, 974 MLX5_CAP_DEC, 975 MLX5_CAP_TLS, 976 MLX5_CAP_DEV_EVENT = 0x14, 977 /* NUM OF CAP Types */ 978 MLX5_CAP_NUM 979 }; 980 981 enum mlx5_qcam_reg_groups { 982 MLX5_QCAM_REGS_FIRST_128 = 0x0, 983 }; 984 985 enum mlx5_qcam_feature_groups { 986 MLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0x0, 987 }; 988 989 enum mlx5_pcam_reg_groups { 990 MLX5_PCAM_REGS_5000_TO_507F = 0x0, 991 }; 992 993 enum mlx5_pcam_feature_groups { 994 MLX5_PCAM_FEATURE_ENHANCED_FEATURES = 0x0, 995 }; 996 997 enum mlx5_mcam_reg_groups { 998 MLX5_MCAM_REGS_FIRST_128 = 0x0, 999 }; 1000 1001 enum mlx5_mcam_feature_groups { 1002 MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0, 1003 }; 1004 1005 /* GET Dev Caps macros */ 1006 #define MLX5_CAP_GEN(mdev, cap) \ 1007 MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap) 1008 1009 #define MLX5_CAP_GEN_64(mdev, cap) \ 1010 MLX5_GET64(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap) 1011 1012 #define MLX5_CAP_GEN_MAX(mdev, cap) \ 1013 MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap) 1014 1015 #define MLX5_CAP_ETH(mdev, cap) \ 1016 MLX5_GET(per_protocol_networking_offload_caps,\ 1017 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap) 1018 1019 #define MLX5_CAP_ETH_MAX(mdev, cap) \ 1020 MLX5_GET(per_protocol_networking_offload_caps,\ 1021 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap) 1022 1023 #define MLX5_CAP_ROCE(mdev, cap) \ 1024 MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap) 1025 1026 #define MLX5_CAP_ROCE_MAX(mdev, cap) \ 1027 MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap) 1028 1029 #define MLX5_CAP_ATOMIC(mdev, cap) \ 1030 MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap) 1031 1032 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \ 1033 MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap) 1034 1035 #define MLX5_CAP_FLOWTABLE(mdev, cap) \ 1036 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap) 1037 1038 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \ 1039 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap) 1040 1041 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \ 1042 MLX5_GET(flow_table_eswitch_cap, \ 1043 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 1044 1045 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \ 1046 MLX5_GET(flow_table_eswitch_cap, \ 1047 mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 1048 1049 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \ 1050 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap) 1051 1052 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \ 1053 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap) 1054 1055 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \ 1056 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap) 1057 1058 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \ 1059 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap) 1060 1061 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \ 1062 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap) 1063 1064 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \ 1065 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap) 1066 1067 #define MLX5_CAP_ESW(mdev, cap) \ 1068 MLX5_GET(e_switch_cap, \ 1069 mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap) 1070 1071 #define MLX5_CAP_ESW_MAX(mdev, cap) \ 1072 MLX5_GET(e_switch_cap, \ 1073 mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap) 1074 1075 #define MLX5_CAP_ODP(mdev, cap)\ 1076 MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap) 1077 1078 #define MLX5_CAP_ODP_MAX(mdev, cap)\ 1079 MLX5_GET(odp_cap, mdev->hca_caps_max[MLX5_CAP_ODP], cap) 1080 1081 #define MLX5_CAP_SNAPSHOT(mdev, cap) \ 1082 MLX5_GET(snapshot_cap, \ 1083 mdev->hca_caps_cur[MLX5_CAP_SNAPSHOT], cap) 1084 1085 #define MLX5_CAP_SNAPSHOT_MAX(mdev, cap) \ 1086 MLX5_GET(snapshot_cap, \ 1087 mdev->hca_caps_max[MLX5_CAP_SNAPSHOT], cap) 1088 1089 #define MLX5_CAP_EOIB_OFFLOADS(mdev, cap) \ 1090 MLX5_GET(per_protocol_networking_offload_caps,\ 1091 mdev->hca_caps_cur[MLX5_CAP_EOIB_OFFLOADS], cap) 1092 1093 #define MLX5_CAP_EOIB_OFFLOADS_MAX(mdev, cap) \ 1094 MLX5_GET(per_protocol_networking_offload_caps,\ 1095 mdev->hca_caps_max[MLX5_CAP_EOIB_OFFLOADS], cap) 1096 1097 #define MLX5_CAP_DEBUG(mdev, cap) \ 1098 MLX5_GET(debug_cap, \ 1099 mdev->hca_caps_cur[MLX5_CAP_DEBUG], cap) 1100 1101 #define MLX5_CAP_DEBUG_MAX(mdev, cap) \ 1102 MLX5_GET(debug_cap, \ 1103 mdev->hca_caps_max[MLX5_CAP_DEBUG], cap) 1104 1105 #define MLX5_CAP_QOS(mdev, cap) \ 1106 MLX5_GET(qos_cap,\ 1107 mdev->hca_caps_cur[MLX5_CAP_QOS], cap) 1108 1109 #define MLX5_CAP_QOS_MAX(mdev, cap) \ 1110 MLX5_GET(qos_cap,\ 1111 mdev->hca_caps_max[MLX5_CAP_QOS], cap) 1112 1113 #define MLX5_CAP_PCAM_FEATURE(mdev, fld) \ 1114 MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld) 1115 1116 #define MLX5_CAP_PCAM_REG(mdev, reg) \ 1117 MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg) 1118 1119 #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \ 1120 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld) 1121 1122 #define MLX5_CAP_MCAM_REG(mdev, reg) \ 1123 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs.reg) 1124 1125 #define MLX5_CAP_QCAM_REG(mdev, fld) \ 1126 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld) 1127 1128 #define MLX5_CAP_QCAM_FEATURE(mdev, fld) \ 1129 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld) 1130 1131 #define MLX5_CAP_FPGA(mdev, cap) \ 1132 MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap) 1133 1134 #define MLX5_CAP64_FPGA(mdev, cap) \ 1135 MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap) 1136 1137 #define MLX5_CAP_TLS(mdev, cap) \ 1138 MLX5_GET(tls_capabilities, (mdev)->hca_caps_cur[MLX5_CAP_TLS], cap) 1139 1140 #define MLX5_CAP_DEV_EVENT(mdev, cap)\ 1141 MLX5_ADDR_OF(device_event_cap, (mdev)->hca_caps_cur[MLX5_CAP_DEV_EVENT], cap) 1142 1143 enum { 1144 MLX5_CMD_STAT_OK = 0x0, 1145 MLX5_CMD_STAT_INT_ERR = 0x1, 1146 MLX5_CMD_STAT_BAD_OP_ERR = 0x2, 1147 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3, 1148 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4, 1149 MLX5_CMD_STAT_BAD_RES_ERR = 0x5, 1150 MLX5_CMD_STAT_RES_BUSY = 0x6, 1151 MLX5_CMD_STAT_LIM_ERR = 0x8, 1152 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9, 1153 MLX5_CMD_STAT_IX_ERR = 0xa, 1154 MLX5_CMD_STAT_NO_RES_ERR = 0xf, 1155 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50, 1156 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51, 1157 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10, 1158 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30, 1159 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40, 1160 }; 1161 1162 enum { 1163 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0, 1164 MLX5_RFC_2863_COUNTERS_GROUP = 0x1, 1165 MLX5_RFC_2819_COUNTERS_GROUP = 0x2, 1166 MLX5_RFC_3635_COUNTERS_GROUP = 0x3, 1167 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5, 1168 MLX5_ETHERNET_DISCARD_COUNTERS_GROUP = 0x6, 1169 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10, 1170 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11, 1171 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12, 1172 MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16, 1173 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20, 1174 }; 1175 1176 enum { 1177 MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0, 1178 MLX5_PCIE_LANE_COUNTERS_GROUP = 0x1, 1179 MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP = 0x2, 1180 }; 1181 1182 enum { 1183 MLX5_CAP_PORT_TYPE_IB = 0x0, 1184 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1185 }; 1186 1187 enum { 1188 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_L2 = 0x0, 1189 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_VPORT_CONFIG = 0x1, 1190 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_NOT_REQUIRED = 0x2 1191 }; 1192 1193 enum mlx5_inline_modes { 1194 MLX5_INLINE_MODE_NONE, 1195 MLX5_INLINE_MODE_L2, 1196 MLX5_INLINE_MODE_IP, 1197 MLX5_INLINE_MODE_TCP_UDP, 1198 }; 1199 1200 enum { 1201 MLX5_QUERY_VPORT_STATE_OUT_STATE_FOLLOW = 0x2, 1202 }; 1203 1204 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz) 1205 { 1206 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE) 1207 return 0; 1208 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz; 1209 } 1210 1211 struct mlx5_ifc_mcia_reg_bits { 1212 u8 l[0x1]; 1213 u8 reserved_0[0x7]; 1214 u8 module[0x8]; 1215 u8 reserved_1[0x8]; 1216 u8 status[0x8]; 1217 1218 u8 i2c_device_address[0x8]; 1219 u8 page_number[0x8]; 1220 u8 device_address[0x10]; 1221 1222 u8 reserved_2[0x10]; 1223 u8 size[0x10]; 1224 1225 u8 reserved_3[0x20]; 1226 1227 u8 dword_0[0x20]; 1228 u8 dword_1[0x20]; 1229 u8 dword_2[0x20]; 1230 u8 dword_3[0x20]; 1231 u8 dword_4[0x20]; 1232 u8 dword_5[0x20]; 1233 u8 dword_6[0x20]; 1234 u8 dword_7[0x20]; 1235 u8 dword_8[0x20]; 1236 u8 dword_9[0x20]; 1237 u8 dword_10[0x20]; 1238 u8 dword_11[0x20]; 1239 }; 1240 1241 #define MLX5_CMD_OP_QUERY_EEPROM 0x93c 1242 1243 struct mlx5_mini_cqe8 { 1244 union { 1245 __be32 rx_hash_result; 1246 __be16 checksum; 1247 __be16 rsvd; 1248 struct { 1249 __be16 wqe_counter; 1250 u8 s_wqe_opcode; 1251 u8 reserved; 1252 } s_wqe_info; 1253 }; 1254 __be32 byte_cnt; 1255 }; 1256 1257 enum { 1258 MLX5_NO_INLINE_DATA, 1259 MLX5_INLINE_DATA32_SEG, 1260 MLX5_INLINE_DATA64_SEG, 1261 MLX5_COMPRESSED, 1262 }; 1263 1264 enum mlx5_exp_cqe_zip_recv_type { 1265 MLX5_CQE_FORMAT_HASH, 1266 MLX5_CQE_FORMAT_CSUM, 1267 }; 1268 1269 #define MLX5E_CQE_FORMAT_MASK 0xc 1270 static inline int mlx5_get_cqe_format(const struct mlx5_cqe64 *cqe) 1271 { 1272 return (cqe->op_own & MLX5E_CQE_FORMAT_MASK) >> 2; 1273 } 1274 1275 enum { 1276 MLX5_GEN_EVENT_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1, 1277 MLX5_GEN_EVENT_SUBTYPE_PCI_POWER_CHANGE_EVENT = 0x5, 1278 }; 1279 1280 enum { 1281 MLX5_FRL_LEVEL3 = 0x8, 1282 MLX5_FRL_LEVEL6 = 0x40, 1283 }; 1284 1285 /* 8 regular priorities + 1 for multicast */ 1286 #define MLX5_NUM_BYPASS_FTS 9 1287 1288 #endif /* MLX5_DEVICE_H */ 1289