1 /*- 2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #define LINUXKPI_PARAM_PREFIX mlx5_ 29 30 #include <linux/kmod.h> 31 #include <linux/module.h> 32 #include <linux/errno.h> 33 #include <linux/pci.h> 34 #include <linux/dma-mapping.h> 35 #include <linux/slab.h> 36 #include <linux/io-mapping.h> 37 #include <linux/interrupt.h> 38 #include <dev/mlx5/driver.h> 39 #include <dev/mlx5/cq.h> 40 #include <dev/mlx5/qp.h> 41 #include <dev/mlx5/srq.h> 42 #include <linux/delay.h> 43 #include <dev/mlx5/mlx5_ifc.h> 44 #include "mlx5_core.h" 45 #include "fs_core.h" 46 47 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 48 MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver"); 49 MODULE_LICENSE("Dual BSD/GPL"); 50 #if (__FreeBSD_version >= 1100000) 51 MODULE_DEPEND(mlx5, linuxkpi, 1, 1, 1); 52 #endif 53 MODULE_VERSION(mlx5, 1); 54 55 int mlx5_core_debug_mask; 56 module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644); 57 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); 58 59 #define MLX5_DEFAULT_PROF 2 60 static int prof_sel = MLX5_DEFAULT_PROF; 61 module_param_named(prof_sel, prof_sel, int, 0444); 62 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); 63 64 #define NUMA_NO_NODE -1 65 66 static LIST_HEAD(intf_list); 67 static LIST_HEAD(dev_list); 68 static DEFINE_MUTEX(intf_mutex); 69 70 struct mlx5_device_context { 71 struct list_head list; 72 struct mlx5_interface *intf; 73 void *context; 74 }; 75 76 enum { 77 MLX5_ATOMIC_REQ_MODE_BE = 0x0, 78 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, 79 }; 80 81 static struct mlx5_profile profiles[] = { 82 [0] = { 83 .mask = 0, 84 }, 85 [1] = { 86 .mask = MLX5_PROF_MASK_QP_SIZE, 87 .log_max_qp = 12, 88 }, 89 [2] = { 90 .mask = MLX5_PROF_MASK_QP_SIZE | 91 MLX5_PROF_MASK_MR_CACHE, 92 .log_max_qp = 17, 93 .mr_cache[0] = { 94 .size = 500, 95 .limit = 250 96 }, 97 .mr_cache[1] = { 98 .size = 500, 99 .limit = 250 100 }, 101 .mr_cache[2] = { 102 .size = 500, 103 .limit = 250 104 }, 105 .mr_cache[3] = { 106 .size = 500, 107 .limit = 250 108 }, 109 .mr_cache[4] = { 110 .size = 500, 111 .limit = 250 112 }, 113 .mr_cache[5] = { 114 .size = 500, 115 .limit = 250 116 }, 117 .mr_cache[6] = { 118 .size = 500, 119 .limit = 250 120 }, 121 .mr_cache[7] = { 122 .size = 500, 123 .limit = 250 124 }, 125 .mr_cache[8] = { 126 .size = 500, 127 .limit = 250 128 }, 129 .mr_cache[9] = { 130 .size = 500, 131 .limit = 250 132 }, 133 .mr_cache[10] = { 134 .size = 500, 135 .limit = 250 136 }, 137 .mr_cache[11] = { 138 .size = 500, 139 .limit = 250 140 }, 141 .mr_cache[12] = { 142 .size = 64, 143 .limit = 32 144 }, 145 .mr_cache[13] = { 146 .size = 32, 147 .limit = 16 148 }, 149 .mr_cache[14] = { 150 .size = 16, 151 .limit = 8 152 }, 153 }, 154 [3] = { 155 .mask = MLX5_PROF_MASK_QP_SIZE, 156 .log_max_qp = 17, 157 }, 158 }; 159 160 static int set_dma_caps(struct pci_dev *pdev) 161 { 162 int err; 163 164 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 165 if (err) { 166 device_printf((&pdev->dev)->bsddev, "WARN: ""Warning: couldn't set 64-bit PCI DMA mask\n"); 167 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 168 if (err) { 169 device_printf((&pdev->dev)->bsddev, "ERR: ""Can't set PCI DMA mask, aborting\n"); 170 return err; 171 } 172 } 173 174 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 175 if (err) { 176 device_printf((&pdev->dev)->bsddev, "WARN: ""Warning: couldn't set 64-bit consistent PCI DMA mask\n"); 177 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 178 if (err) { 179 device_printf((&pdev->dev)->bsddev, "ERR: ""Can't set consistent PCI DMA mask, aborting\n"); 180 return err; 181 } 182 } 183 184 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); 185 return err; 186 } 187 188 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) 189 { 190 struct pci_dev *pdev = dev->pdev; 191 int err = 0; 192 193 mutex_lock(&dev->pci_status_mutex); 194 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { 195 err = pci_enable_device(pdev); 196 if (!err) 197 dev->pci_status = MLX5_PCI_STATUS_ENABLED; 198 } 199 mutex_unlock(&dev->pci_status_mutex); 200 201 return err; 202 } 203 204 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) 205 { 206 struct pci_dev *pdev = dev->pdev; 207 208 mutex_lock(&dev->pci_status_mutex); 209 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { 210 pci_disable_device(pdev); 211 dev->pci_status = MLX5_PCI_STATUS_DISABLED; 212 } 213 mutex_unlock(&dev->pci_status_mutex); 214 } 215 216 static int request_bar(struct pci_dev *pdev) 217 { 218 int err = 0; 219 220 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 221 device_printf((&pdev->dev)->bsddev, "ERR: ""Missing registers BAR, aborting\n"); 222 return -ENODEV; 223 } 224 225 err = pci_request_regions(pdev, DRIVER_NAME); 226 if (err) 227 device_printf((&pdev->dev)->bsddev, "ERR: ""Couldn't get PCI resources, aborting\n"); 228 229 return err; 230 } 231 232 static void release_bar(struct pci_dev *pdev) 233 { 234 pci_release_regions(pdev); 235 } 236 237 static int mlx5_enable_msix(struct mlx5_core_dev *dev) 238 { 239 struct mlx5_priv *priv = &dev->priv; 240 struct mlx5_eq_table *table = &priv->eq_table; 241 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq); 242 int limit = dev->msix_eqvec; 243 int nvec = MLX5_EQ_VEC_COMP_BASE; 244 int i; 245 246 if (limit > 0) 247 nvec += limit; 248 else 249 nvec += MLX5_CAP_GEN(dev, num_ports) * num_online_cpus(); 250 251 nvec = min_t(int, nvec, num_eqs); 252 if (nvec <= MLX5_EQ_VEC_COMP_BASE) 253 return -ENOMEM; 254 255 priv->msix_arr = kzalloc(nvec * sizeof(*priv->msix_arr), GFP_KERNEL); 256 257 priv->irq_info = kzalloc(nvec * sizeof(*priv->irq_info), GFP_KERNEL); 258 259 for (i = 0; i < nvec; i++) 260 priv->msix_arr[i].entry = i; 261 262 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr, 263 MLX5_EQ_VEC_COMP_BASE + 1, nvec); 264 if (nvec < 0) 265 return nvec; 266 267 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE; 268 269 return 0; 270 271 } 272 273 static void mlx5_disable_msix(struct mlx5_core_dev *dev) 274 { 275 struct mlx5_priv *priv = &dev->priv; 276 277 pci_disable_msix(dev->pdev); 278 kfree(priv->irq_info); 279 kfree(priv->msix_arr); 280 } 281 282 struct mlx5_reg_host_endianess { 283 u8 he; 284 u8 rsvd[15]; 285 }; 286 287 288 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) 289 290 enum { 291 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | 292 MLX5_DEV_CAP_FLAG_DCT | 293 MLX5_DEV_CAP_FLAG_DRAIN_SIGERR, 294 }; 295 296 static u16 to_fw_pkey_sz(u32 size) 297 { 298 switch (size) { 299 case 128: 300 return 0; 301 case 256: 302 return 1; 303 case 512: 304 return 2; 305 case 1024: 306 return 3; 307 case 2048: 308 return 4; 309 case 4096: 310 return 5; 311 default: 312 printf("mlx5_core: WARN: ""invalid pkey table size %d\n", size); 313 return 0; 314 } 315 } 316 317 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, 318 enum mlx5_cap_type cap_type, 319 enum mlx5_cap_mode cap_mode) 320 { 321 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; 322 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); 323 void *out, *hca_caps; 324 u16 opmod = (cap_type << 1) | (cap_mode & 0x01); 325 int err; 326 327 memset(in, 0, sizeof(in)); 328 out = kzalloc(out_sz, GFP_KERNEL); 329 330 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 331 MLX5_SET(query_hca_cap_in, in, op_mod, opmod); 332 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz); 333 if (err) { 334 mlx5_core_warn(dev, 335 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", 336 cap_type, cap_mode, err); 337 goto query_ex; 338 } 339 340 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 341 342 switch (cap_mode) { 343 case HCA_CAP_OPMOD_GET_MAX: 344 memcpy(dev->hca_caps_max[cap_type], hca_caps, 345 MLX5_UN_SZ_BYTES(hca_cap_union)); 346 break; 347 case HCA_CAP_OPMOD_GET_CUR: 348 memcpy(dev->hca_caps_cur[cap_type], hca_caps, 349 MLX5_UN_SZ_BYTES(hca_cap_union)); 350 break; 351 default: 352 mlx5_core_warn(dev, 353 "Tried to query dev cap type(%x) with wrong opmode(%x)\n", 354 cap_type, cap_mode); 355 err = -EINVAL; 356 break; 357 } 358 query_ex: 359 kfree(out); 360 return err; 361 } 362 363 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) 364 { 365 int ret; 366 367 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); 368 if (ret) 369 return ret; 370 371 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); 372 } 373 374 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz) 375 { 376 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0}; 377 378 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); 379 380 return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out)); 381 } 382 383 static int handle_hca_cap(struct mlx5_core_dev *dev) 384 { 385 void *set_ctx = NULL; 386 struct mlx5_profile *prof = dev->profile; 387 int err = -ENOMEM; 388 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 389 void *set_hca_cap; 390 391 set_ctx = kzalloc(set_sz, GFP_KERNEL); 392 393 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 394 if (err) 395 goto query_ex; 396 397 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 398 capability); 399 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL], 400 MLX5_ST_SZ_BYTES(cmd_hca_cap)); 401 402 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", 403 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), 404 128); 405 /* we limit the size of the pkey table to 128 entries for now */ 406 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, 407 to_fw_pkey_sz(128)); 408 409 if (prof->mask & MLX5_PROF_MASK_QP_SIZE) 410 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, 411 prof->log_max_qp); 412 413 /* disable cmdif checksum */ 414 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); 415 416 /* enable drain sigerr */ 417 MLX5_SET(cmd_hca_cap, set_hca_cap, drain_sigerr, 1); 418 419 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); 420 421 err = set_caps(dev, set_ctx, set_sz); 422 423 query_ex: 424 kfree(set_ctx); 425 return err; 426 } 427 428 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev) 429 { 430 void *set_ctx; 431 void *set_hca_cap; 432 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 433 int req_endianness; 434 int err; 435 436 if (MLX5_CAP_GEN(dev, atomic)) { 437 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); 438 if (err) 439 return err; 440 } else { 441 return 0; 442 } 443 444 req_endianness = 445 MLX5_CAP_ATOMIC(dev, 446 supported_atomic_req_8B_endianess_mode_1); 447 448 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) 449 return 0; 450 451 set_ctx = kzalloc(set_sz, GFP_KERNEL); 452 if (!set_ctx) 453 return -ENOMEM; 454 455 MLX5_SET(set_hca_cap_in, set_ctx, op_mod, 456 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC << 1); 457 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 458 459 /* Set requestor to host endianness */ 460 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianess_mode, 461 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); 462 463 err = set_caps(dev, set_ctx, set_sz); 464 465 kfree(set_ctx); 466 return err; 467 } 468 469 static int set_hca_ctrl(struct mlx5_core_dev *dev) 470 { 471 struct mlx5_reg_host_endianess he_in; 472 struct mlx5_reg_host_endianess he_out; 473 int err; 474 475 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH && 476 !MLX5_CAP_GEN(dev, roce)) 477 return 0; 478 479 memset(&he_in, 0, sizeof(he_in)); 480 he_in.he = MLX5_SET_HOST_ENDIANNESS; 481 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), 482 &he_out, sizeof(he_out), 483 MLX5_REG_HOST_ENDIANNESS, 0, 1); 484 return err; 485 } 486 487 static int mlx5_core_enable_hca(struct mlx5_core_dev *dev) 488 { 489 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0}; 490 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0}; 491 492 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); 493 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out)); 494 } 495 496 static int mlx5_core_disable_hca(struct mlx5_core_dev *dev) 497 { 498 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0}; 499 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0}; 500 501 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); 502 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 503 } 504 505 static int mlx5_core_set_issi(struct mlx5_core_dev *dev) 506 { 507 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0}; 508 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0}; 509 u32 sup_issi; 510 int err; 511 512 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); 513 514 err = mlx5_cmd_exec(dev, query_in, sizeof(query_in), query_out, sizeof(query_out)); 515 if (err) { 516 u32 syndrome; 517 u8 status; 518 519 mlx5_cmd_mbox_status(query_out, &status, &syndrome); 520 if (status == MLX5_CMD_STAT_BAD_OP_ERR) { 521 pr_debug("Only ISSI 0 is supported\n"); 522 return 0; 523 } 524 525 printf("mlx5_core: ERR: ""failed to query ISSI\n"); 526 return err; 527 } 528 529 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); 530 531 if (sup_issi & (1 << 1)) { 532 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0}; 533 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0}; 534 535 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); 536 MLX5_SET(set_issi_in, set_in, current_issi, 1); 537 538 err = mlx5_cmd_exec(dev, set_in, sizeof(set_in), set_out, sizeof(set_out)); 539 if (err) { 540 printf("mlx5_core: ERR: ""failed to set ISSI=1 err(%d)\n", err); 541 return err; 542 } 543 544 dev->issi = 1; 545 546 return 0; 547 } else if (sup_issi & (1 << 0)) { 548 return 0; 549 } 550 551 return -ENOTSUPP; 552 } 553 554 555 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn) 556 { 557 struct mlx5_eq_table *table = &dev->priv.eq_table; 558 struct mlx5_eq *eq; 559 int err = -ENOENT; 560 561 spin_lock(&table->lock); 562 list_for_each_entry(eq, &table->comp_eqs_list, list) { 563 if (eq->index == vector) { 564 *eqn = eq->eqn; 565 *irqn = eq->irqn; 566 err = 0; 567 break; 568 } 569 } 570 spin_unlock(&table->lock); 571 572 return err; 573 } 574 EXPORT_SYMBOL(mlx5_vector2eqn); 575 576 int mlx5_rename_eq(struct mlx5_core_dev *dev, int eq_ix, char *name) 577 { 578 struct mlx5_priv *priv = &dev->priv; 579 struct mlx5_eq_table *table = &priv->eq_table; 580 struct mlx5_eq *eq; 581 int err = -ENOENT; 582 583 spin_lock(&table->lock); 584 list_for_each_entry(eq, &table->comp_eqs_list, list) { 585 if (eq->index == eq_ix) { 586 int irq_ix = eq_ix + MLX5_EQ_VEC_COMP_BASE; 587 588 snprintf(priv->irq_info[irq_ix].name, MLX5_MAX_IRQ_NAME, 589 "%s-%d", name, eq_ix); 590 591 err = 0; 592 break; 593 } 594 } 595 spin_unlock(&table->lock); 596 597 return err; 598 } 599 600 static void free_comp_eqs(struct mlx5_core_dev *dev) 601 { 602 struct mlx5_eq_table *table = &dev->priv.eq_table; 603 struct mlx5_eq *eq, *n; 604 605 spin_lock(&table->lock); 606 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) { 607 list_del(&eq->list); 608 spin_unlock(&table->lock); 609 if (mlx5_destroy_unmap_eq(dev, eq)) 610 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n", 611 eq->eqn); 612 kfree(eq); 613 spin_lock(&table->lock); 614 } 615 spin_unlock(&table->lock); 616 } 617 618 static int alloc_comp_eqs(struct mlx5_core_dev *dev) 619 { 620 struct mlx5_eq_table *table = &dev->priv.eq_table; 621 char name[MLX5_MAX_IRQ_NAME]; 622 struct mlx5_eq *eq; 623 int ncomp_vec; 624 int nent; 625 int err; 626 int i; 627 628 INIT_LIST_HEAD(&table->comp_eqs_list); 629 ncomp_vec = table->num_comp_vectors; 630 nent = MLX5_COMP_EQ_SIZE; 631 for (i = 0; i < ncomp_vec; i++) { 632 eq = kzalloc(sizeof(*eq), GFP_KERNEL); 633 634 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i); 635 err = mlx5_create_map_eq(dev, eq, 636 i + MLX5_EQ_VEC_COMP_BASE, nent, 0, 637 name, &dev->priv.uuari.uars[0]); 638 if (err) { 639 kfree(eq); 640 goto clean; 641 } 642 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn); 643 eq->index = i; 644 spin_lock(&table->lock); 645 list_add_tail(&eq->list, &table->comp_eqs_list); 646 spin_unlock(&table->lock); 647 } 648 649 return 0; 650 651 clean: 652 free_comp_eqs(dev); 653 return err; 654 } 655 656 static int map_bf_area(struct mlx5_core_dev *dev) 657 { 658 resource_size_t bf_start = pci_resource_start(dev->pdev, 0); 659 resource_size_t bf_len = pci_resource_len(dev->pdev, 0); 660 661 dev->priv.bf_mapping = io_mapping_create_wc(bf_start, bf_len); 662 663 return dev->priv.bf_mapping ? 0 : -ENOMEM; 664 } 665 666 static void unmap_bf_area(struct mlx5_core_dev *dev) 667 { 668 if (dev->priv.bf_mapping) 669 io_mapping_free(dev->priv.bf_mapping); 670 } 671 672 static inline int fw_initializing(struct mlx5_core_dev *dev) 673 { 674 return ioread32be(&dev->iseg->initializing) >> 31; 675 } 676 677 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili) 678 { 679 u64 end = jiffies + msecs_to_jiffies(max_wait_mili); 680 int err = 0; 681 682 while (fw_initializing(dev)) { 683 if (time_after(jiffies, end)) { 684 err = -EBUSY; 685 break; 686 } 687 msleep(FW_INIT_WAIT_MS); 688 } 689 690 return err; 691 } 692 693 static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv) 694 { 695 struct mlx5_device_context *dev_ctx; 696 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv); 697 698 dev_ctx = kzalloc(sizeof(*dev_ctx), GFP_KERNEL); 699 if (!dev_ctx) 700 return; 701 702 dev_ctx->intf = intf; 703 CURVNET_SET_QUIET(vnet0); 704 dev_ctx->context = intf->add(dev); 705 CURVNET_RESTORE(); 706 707 if (dev_ctx->context) { 708 spin_lock_irq(&priv->ctx_lock); 709 list_add_tail(&dev_ctx->list, &priv->ctx_list); 710 spin_unlock_irq(&priv->ctx_lock); 711 } else { 712 kfree(dev_ctx); 713 } 714 } 715 716 static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv) 717 { 718 struct mlx5_device_context *dev_ctx; 719 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv); 720 721 list_for_each_entry(dev_ctx, &priv->ctx_list, list) 722 if (dev_ctx->intf == intf) { 723 spin_lock_irq(&priv->ctx_lock); 724 list_del(&dev_ctx->list); 725 spin_unlock_irq(&priv->ctx_lock); 726 727 intf->remove(dev, dev_ctx->context); 728 kfree(dev_ctx); 729 return; 730 } 731 } 732 733 static int mlx5_register_device(struct mlx5_core_dev *dev) 734 { 735 struct mlx5_priv *priv = &dev->priv; 736 struct mlx5_interface *intf; 737 738 mutex_lock(&intf_mutex); 739 list_add_tail(&priv->dev_list, &dev_list); 740 list_for_each_entry(intf, &intf_list, list) 741 mlx5_add_device(intf, priv); 742 mutex_unlock(&intf_mutex); 743 744 return 0; 745 } 746 747 static void mlx5_unregister_device(struct mlx5_core_dev *dev) 748 { 749 struct mlx5_priv *priv = &dev->priv; 750 struct mlx5_interface *intf; 751 752 mutex_lock(&intf_mutex); 753 list_for_each_entry(intf, &intf_list, list) 754 mlx5_remove_device(intf, priv); 755 list_del(&priv->dev_list); 756 mutex_unlock(&intf_mutex); 757 } 758 759 int mlx5_register_interface(struct mlx5_interface *intf) 760 { 761 struct mlx5_priv *priv; 762 763 if (!intf->add || !intf->remove) 764 return -EINVAL; 765 766 mutex_lock(&intf_mutex); 767 list_add_tail(&intf->list, &intf_list); 768 list_for_each_entry(priv, &dev_list, dev_list) 769 mlx5_add_device(intf, priv); 770 mutex_unlock(&intf_mutex); 771 772 return 0; 773 } 774 EXPORT_SYMBOL(mlx5_register_interface); 775 776 void mlx5_unregister_interface(struct mlx5_interface *intf) 777 { 778 struct mlx5_priv *priv; 779 780 mutex_lock(&intf_mutex); 781 list_for_each_entry(priv, &dev_list, dev_list) 782 mlx5_remove_device(intf, priv); 783 list_del(&intf->list); 784 mutex_unlock(&intf_mutex); 785 } 786 EXPORT_SYMBOL(mlx5_unregister_interface); 787 788 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol) 789 { 790 struct mlx5_priv *priv = &mdev->priv; 791 struct mlx5_device_context *dev_ctx; 792 unsigned long flags; 793 void *result = NULL; 794 795 spin_lock_irqsave(&priv->ctx_lock, flags); 796 797 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list) 798 if ((dev_ctx->intf->protocol == protocol) && 799 dev_ctx->intf->get_dev) { 800 result = dev_ctx->intf->get_dev(dev_ctx->context); 801 break; 802 } 803 804 spin_unlock_irqrestore(&priv->ctx_lock, flags); 805 806 return result; 807 } 808 EXPORT_SYMBOL(mlx5_get_protocol_dev); 809 810 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv) 811 { 812 struct pci_dev *pdev = dev->pdev; 813 int err = 0; 814 815 pci_set_drvdata(dev->pdev, dev); 816 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN); 817 priv->name[MLX5_MAX_NAME_LEN - 1] = 0; 818 819 mutex_init(&priv->pgdir_mutex); 820 INIT_LIST_HEAD(&priv->pgdir_list); 821 spin_lock_init(&priv->mkey_lock); 822 823 priv->numa_node = NUMA_NO_NODE; 824 825 err = mlx5_pci_enable_device(dev); 826 if (err) { 827 device_printf((&pdev->dev)->bsddev, "ERR: ""Cannot enable PCI device, aborting\n"); 828 goto err_dbg; 829 } 830 831 err = request_bar(pdev); 832 if (err) { 833 device_printf((&pdev->dev)->bsddev, "ERR: ""error requesting BARs, aborting\n"); 834 goto err_disable; 835 } 836 837 pci_set_master(pdev); 838 839 err = set_dma_caps(pdev); 840 if (err) { 841 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed setting DMA capabilities mask, aborting\n"); 842 goto err_clr_master; 843 } 844 845 dev->iseg_base = pci_resource_start(dev->pdev, 0); 846 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); 847 if (!dev->iseg) { 848 err = -ENOMEM; 849 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed mapping initialization segment, aborting\n"); 850 goto err_clr_master; 851 } 852 853 return 0; 854 855 err_clr_master: 856 pci_clear_master(dev->pdev); 857 release_bar(dev->pdev); 858 err_disable: 859 mlx5_pci_disable_device(dev); 860 err_dbg: 861 return err; 862 } 863 864 static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv) 865 { 866 iounmap(dev->iseg); 867 pci_clear_master(dev->pdev); 868 release_bar(dev->pdev); 869 mlx5_pci_disable_device(dev); 870 } 871 872 static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv) 873 { 874 struct pci_dev *pdev = dev->pdev; 875 int err; 876 877 err = mlx5_vsc_find_cap(dev); 878 if (err) 879 dev_err(&pdev->dev, "Unable to find vendor specific capabilities\n"); 880 881 err = mlx5_query_hca_caps(dev); 882 if (err) { 883 dev_err(&pdev->dev, "query hca failed\n"); 884 goto out; 885 } 886 887 err = mlx5_query_board_id(dev); 888 if (err) { 889 dev_err(&pdev->dev, "query board id failed\n"); 890 goto out; 891 } 892 893 err = mlx5_eq_init(dev); 894 if (err) { 895 dev_err(&pdev->dev, "failed to initialize eq\n"); 896 goto out; 897 } 898 899 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock); 900 901 err = mlx5_init_cq_table(dev); 902 if (err) { 903 dev_err(&pdev->dev, "failed to initialize cq table\n"); 904 goto err_eq_cleanup; 905 } 906 907 mlx5_init_qp_table(dev); 908 mlx5_init_srq_table(dev); 909 mlx5_init_mr_table(dev); 910 911 #ifdef RATELIMIT 912 err = mlx5_init_rl_table(dev); 913 if (err) { 914 dev_err(&pdev->dev, "Failed to init rate limiting\n"); 915 goto err_tables_cleanup; 916 } 917 #endif 918 return 0; 919 920 #ifdef RATELIMIT 921 err_tables_cleanup: 922 mlx5_cleanup_mr_table(dev); 923 mlx5_cleanup_srq_table(dev); 924 mlx5_cleanup_qp_table(dev); 925 mlx5_cleanup_cq_table(dev); 926 #endif 927 928 err_eq_cleanup: 929 mlx5_eq_cleanup(dev); 930 931 out: 932 return err; 933 } 934 935 static void mlx5_cleanup_once(struct mlx5_core_dev *dev) 936 { 937 #ifdef RATELIMIT 938 mlx5_cleanup_rl_table(dev); 939 #endif 940 mlx5_cleanup_mr_table(dev); 941 mlx5_cleanup_srq_table(dev); 942 mlx5_cleanup_qp_table(dev); 943 mlx5_cleanup_cq_table(dev); 944 mlx5_eq_cleanup(dev); 945 } 946 947 static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, 948 bool boot) 949 { 950 struct pci_dev *pdev = dev->pdev; 951 int err; 952 953 mutex_lock(&dev->intf_state_mutex); 954 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 955 dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n", 956 __func__); 957 goto out; 958 } 959 960 device_printf((&pdev->dev)->bsddev, "INFO: ""firmware version: %d.%d.%d\n", fw_rev_maj(dev), fw_rev_min(dev), fw_rev_sub(dev)); 961 962 /* 963 * On load removing any previous indication of internal error, 964 * device is up 965 */ 966 dev->state = MLX5_DEVICE_STATE_UP; 967 968 err = mlx5_cmd_init(dev); 969 if (err) { 970 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed initializing command interface, aborting\n"); 971 goto out_err; 972 } 973 974 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI); 975 if (err) { 976 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""Firmware over %d MS in initializing state, aborting\n", FW_INIT_TIMEOUT_MILI); 977 goto err_cmd_cleanup; 978 } 979 980 err = mlx5_core_enable_hca(dev); 981 if (err) { 982 device_printf((&pdev->dev)->bsddev, "ERR: ""enable hca failed\n"); 983 goto err_cmd_cleanup; 984 } 985 986 err = mlx5_core_set_issi(dev); 987 if (err) { 988 device_printf((&pdev->dev)->bsddev, "ERR: ""failed to set issi\n"); 989 goto err_disable_hca; 990 } 991 992 err = mlx5_pagealloc_start(dev); 993 if (err) { 994 device_printf((&pdev->dev)->bsddev, "ERR: ""mlx5_pagealloc_start failed\n"); 995 goto err_disable_hca; 996 } 997 998 err = mlx5_satisfy_startup_pages(dev, 1); 999 if (err) { 1000 device_printf((&pdev->dev)->bsddev, "ERR: ""failed to allocate boot pages\n"); 1001 goto err_pagealloc_stop; 1002 } 1003 1004 err = set_hca_ctrl(dev); 1005 if (err) { 1006 device_printf((&pdev->dev)->bsddev, "ERR: ""set_hca_ctrl failed\n"); 1007 goto reclaim_boot_pages; 1008 } 1009 1010 err = handle_hca_cap(dev); 1011 if (err) { 1012 device_printf((&pdev->dev)->bsddev, "ERR: ""handle_hca_cap failed\n"); 1013 goto reclaim_boot_pages; 1014 } 1015 1016 err = handle_hca_cap_atomic(dev); 1017 if (err) { 1018 device_printf((&pdev->dev)->bsddev, "ERR: ""handle_hca_cap_atomic failed\n"); 1019 goto reclaim_boot_pages; 1020 } 1021 1022 err = mlx5_satisfy_startup_pages(dev, 0); 1023 if (err) { 1024 device_printf((&pdev->dev)->bsddev, "ERR: ""failed to allocate init pages\n"); 1025 goto reclaim_boot_pages; 1026 } 1027 1028 err = mlx5_cmd_init_hca(dev); 1029 if (err) { 1030 device_printf((&pdev->dev)->bsddev, "ERR: ""init hca failed\n"); 1031 goto reclaim_boot_pages; 1032 } 1033 1034 mlx5_start_health_poll(dev); 1035 1036 if (boot && mlx5_init_once(dev, priv)) { 1037 dev_err(&pdev->dev, "sw objs init failed\n"); 1038 goto err_stop_poll; 1039 } 1040 1041 err = mlx5_enable_msix(dev); 1042 if (err) { 1043 device_printf((&pdev->dev)->bsddev, "ERR: ""enable msix failed\n"); 1044 goto err_cleanup_once; 1045 } 1046 1047 err = mlx5_alloc_uuars(dev, &priv->uuari); 1048 if (err) { 1049 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed allocating uar, aborting\n"); 1050 goto err_disable_msix; 1051 } 1052 1053 err = mlx5_start_eqs(dev); 1054 if (err) { 1055 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed to start pages and async EQs\n"); 1056 goto err_free_uar; 1057 } 1058 1059 err = alloc_comp_eqs(dev); 1060 if (err) { 1061 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed to alloc completion EQs\n"); 1062 goto err_stop_eqs; 1063 } 1064 1065 if (map_bf_area(dev)) 1066 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed to map blue flame area\n"); 1067 1068 err = mlx5_init_fs(dev); 1069 if (err) { 1070 mlx5_core_err(dev, "flow steering init %d\n", err); 1071 goto err_free_comp_eqs; 1072 } 1073 1074 err = mlx5_register_device(dev); 1075 if (err) { 1076 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err); 1077 goto err_fs; 1078 } 1079 1080 clear_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state); 1081 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1082 1083 out: 1084 mutex_unlock(&dev->intf_state_mutex); 1085 return 0; 1086 1087 err_fs: 1088 mlx5_cleanup_fs(dev); 1089 1090 err_free_comp_eqs: 1091 free_comp_eqs(dev); 1092 unmap_bf_area(dev); 1093 1094 err_stop_eqs: 1095 mlx5_stop_eqs(dev); 1096 1097 err_free_uar: 1098 mlx5_free_uuars(dev, &priv->uuari); 1099 1100 err_disable_msix: 1101 mlx5_disable_msix(dev); 1102 1103 err_cleanup_once: 1104 if (boot) 1105 mlx5_cleanup_once(dev); 1106 1107 err_stop_poll: 1108 mlx5_stop_health_poll(dev); 1109 if (mlx5_cmd_teardown_hca(dev)) { 1110 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""tear_down_hca failed, skip cleanup\n"); 1111 goto out_err; 1112 } 1113 1114 reclaim_boot_pages: 1115 mlx5_reclaim_startup_pages(dev); 1116 1117 err_pagealloc_stop: 1118 mlx5_pagealloc_stop(dev); 1119 1120 err_disable_hca: 1121 mlx5_core_disable_hca(dev); 1122 1123 err_cmd_cleanup: 1124 mlx5_cmd_cleanup(dev); 1125 1126 out_err: 1127 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1128 mutex_unlock(&dev->intf_state_mutex); 1129 1130 return err; 1131 } 1132 1133 static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, 1134 bool cleanup) 1135 { 1136 int err = 0; 1137 1138 if (cleanup) 1139 mlx5_drain_health_recovery(dev); 1140 1141 mutex_lock(&dev->intf_state_mutex); 1142 if (test_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state)) { 1143 dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n", __func__); 1144 if (cleanup) 1145 mlx5_cleanup_once(dev); 1146 goto out; 1147 } 1148 1149 mlx5_unregister_device(dev); 1150 1151 mlx5_cleanup_fs(dev); 1152 unmap_bf_area(dev); 1153 mlx5_wait_for_reclaim_vfs_pages(dev); 1154 free_comp_eqs(dev); 1155 mlx5_stop_eqs(dev); 1156 mlx5_free_uuars(dev, &priv->uuari); 1157 mlx5_disable_msix(dev); 1158 if (cleanup) 1159 mlx5_cleanup_once(dev); 1160 mlx5_stop_health_poll(dev); 1161 err = mlx5_cmd_teardown_hca(dev); 1162 if (err) { 1163 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""tear_down_hca failed, skip cleanup\n"); 1164 goto out; 1165 } 1166 mlx5_pagealloc_stop(dev); 1167 mlx5_reclaim_startup_pages(dev); 1168 mlx5_core_disable_hca(dev); 1169 mlx5_cmd_cleanup(dev); 1170 1171 out: 1172 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1173 set_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state); 1174 mutex_unlock(&dev->intf_state_mutex); 1175 return err; 1176 } 1177 1178 void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event, 1179 unsigned long param) 1180 { 1181 struct mlx5_priv *priv = &dev->priv; 1182 struct mlx5_device_context *dev_ctx; 1183 unsigned long flags; 1184 1185 spin_lock_irqsave(&priv->ctx_lock, flags); 1186 1187 list_for_each_entry(dev_ctx, &priv->ctx_list, list) 1188 if (dev_ctx->intf->event) 1189 dev_ctx->intf->event(dev, dev_ctx->context, event, param); 1190 1191 spin_unlock_irqrestore(&priv->ctx_lock, flags); 1192 } 1193 1194 struct mlx5_core_event_handler { 1195 void (*event)(struct mlx5_core_dev *dev, 1196 enum mlx5_dev_event event, 1197 void *data); 1198 }; 1199 1200 static int init_one(struct pci_dev *pdev, 1201 const struct pci_device_id *id) 1202 { 1203 struct mlx5_core_dev *dev; 1204 struct mlx5_priv *priv; 1205 device_t bsddev = pdev->dev.bsddev; 1206 int err; 1207 1208 dev = kzalloc(sizeof(*dev), GFP_KERNEL); 1209 priv = &dev->priv; 1210 if (id) 1211 priv->pci_dev_data = id->driver_data; 1212 1213 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profiles)) { 1214 printf("mlx5_core: WARN: ""selected profile out of range, selecting default (%d)\n", MLX5_DEFAULT_PROF); 1215 prof_sel = MLX5_DEFAULT_PROF; 1216 } 1217 dev->profile = &profiles[prof_sel]; 1218 dev->pdev = pdev; 1219 dev->event = mlx5_core_event; 1220 1221 sysctl_ctx_init(&dev->sysctl_ctx); 1222 SYSCTL_ADD_INT(&dev->sysctl_ctx, 1223 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)), 1224 OID_AUTO, "msix_eqvec", CTLFLAG_RDTUN, &dev->msix_eqvec, 0, 1225 "Maximum number of MSIX event queue vectors, if set"); 1226 1227 INIT_LIST_HEAD(&priv->ctx_list); 1228 spin_lock_init(&priv->ctx_lock); 1229 mutex_init(&dev->pci_status_mutex); 1230 mutex_init(&dev->intf_state_mutex); 1231 err = mlx5_pci_init(dev, priv); 1232 if (err) { 1233 device_printf((&pdev->dev)->bsddev, "ERR: ""mlx5_pci_init failed %d\n", err); 1234 goto clean_dev; 1235 } 1236 1237 err = mlx5_health_init(dev); 1238 if (err) { 1239 device_printf((&pdev->dev)->bsddev, "ERR: ""mlx5_health_init failed %d\n", err); 1240 goto close_pci; 1241 } 1242 1243 mlx5_pagealloc_init(dev); 1244 1245 err = mlx5_load_one(dev, priv, true); 1246 if (err) { 1247 device_printf((&pdev->dev)->bsddev, "ERR: ""mlx5_register_device failed %d\n", err); 1248 goto clean_health; 1249 } 1250 1251 mlx5_fwdump_prep(dev); 1252 1253 pci_save_state(pdev->dev.bsddev); 1254 return 0; 1255 1256 clean_health: 1257 mlx5_pagealloc_cleanup(dev); 1258 mlx5_health_cleanup(dev); 1259 close_pci: 1260 mlx5_pci_close(dev, priv); 1261 clean_dev: 1262 sysctl_ctx_free(&dev->sysctl_ctx); 1263 kfree(dev); 1264 return err; 1265 } 1266 1267 static void remove_one(struct pci_dev *pdev) 1268 { 1269 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1270 struct mlx5_priv *priv = &dev->priv; 1271 1272 if (mlx5_unload_one(dev, priv, true)) { 1273 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n"); 1274 mlx5_health_cleanup(dev); 1275 return; 1276 } 1277 1278 mlx5_fwdump_clean(dev); 1279 mlx5_pagealloc_cleanup(dev); 1280 mlx5_health_cleanup(dev); 1281 mlx5_pci_close(dev, priv); 1282 pci_set_drvdata(pdev, NULL); 1283 sysctl_ctx_free(&dev->sysctl_ctx); 1284 kfree(dev); 1285 } 1286 1287 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, 1288 pci_channel_state_t state) 1289 { 1290 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1291 struct mlx5_priv *priv = &dev->priv; 1292 1293 dev_info(&pdev->dev, "%s was called\n", __func__); 1294 mlx5_enter_error_state(dev, false); 1295 mlx5_unload_one(dev, priv, false); 1296 1297 if (state) { 1298 mlx5_drain_health_wq(dev); 1299 mlx5_pci_disable_device(dev); 1300 } 1301 1302 return state == pci_channel_io_perm_failure ? 1303 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 1304 } 1305 1306 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) 1307 { 1308 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1309 int err = 0; 1310 1311 dev_info(&pdev->dev, "%s was called\n", __func__); 1312 1313 err = mlx5_pci_enable_device(dev); 1314 if (err) { 1315 dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n" 1316 , __func__, err); 1317 return PCI_ERS_RESULT_DISCONNECT; 1318 } 1319 pci_set_master(pdev); 1320 pci_set_powerstate(pdev->dev.bsddev, PCI_POWERSTATE_D0); 1321 pci_restore_state(pdev->dev.bsddev); 1322 pci_save_state(pdev->dev.bsddev); 1323 1324 return err ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED; 1325 } 1326 1327 /* wait for the device to show vital signs. For now we check 1328 * that we can read the device ID and that the health buffer 1329 * shows a non zero value which is different than 0xffffffff 1330 */ 1331 static void wait_vital(struct pci_dev *pdev) 1332 { 1333 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1334 struct mlx5_core_health *health = &dev->priv.health; 1335 const int niter = 100; 1336 u32 count; 1337 u16 did; 1338 int i; 1339 1340 /* Wait for firmware to be ready after reset */ 1341 msleep(1000); 1342 for (i = 0; i < niter; i++) { 1343 if (pci_read_config_word(pdev, 2, &did)) { 1344 dev_warn(&pdev->dev, "failed reading config word\n"); 1345 break; 1346 } 1347 if (did == pdev->device) { 1348 dev_info(&pdev->dev, "device ID correctly read after %d iterations\n", i); 1349 break; 1350 } 1351 msleep(50); 1352 } 1353 if (i == niter) 1354 dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__); 1355 1356 for (i = 0; i < niter; i++) { 1357 count = ioread32be(health->health_counter); 1358 if (count && count != 0xffffffff) { 1359 dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i); 1360 break; 1361 } 1362 msleep(50); 1363 } 1364 1365 if (i == niter) 1366 dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__); 1367 } 1368 1369 static void mlx5_pci_resume(struct pci_dev *pdev) 1370 { 1371 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1372 struct mlx5_priv *priv = &dev->priv; 1373 int err; 1374 1375 dev_info(&pdev->dev, "%s was called\n", __func__); 1376 1377 wait_vital(pdev); 1378 1379 err = mlx5_load_one(dev, priv, false); 1380 if (err) 1381 dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n" 1382 , __func__, err); 1383 else 1384 dev_info(&pdev->dev, "%s: device recovered\n", __func__); 1385 } 1386 1387 static const struct pci_error_handlers mlx5_err_handler = { 1388 .error_detected = mlx5_pci_err_detected, 1389 .slot_reset = mlx5_pci_slot_reset, 1390 .resume = mlx5_pci_resume 1391 }; 1392 1393 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) 1394 { 1395 int err; 1396 1397 if (!MLX5_CAP_GEN(dev, force_teardown)) { 1398 mlx5_core_dbg(dev, "force teardown is not supported in the firmware\n"); 1399 return -EOPNOTSUPP; 1400 } 1401 1402 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 1403 mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); 1404 return -EAGAIN; 1405 } 1406 1407 err = mlx5_cmd_force_teardown_hca(dev); 1408 if (err) { 1409 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", err); 1410 return err; 1411 } 1412 1413 mlx5_enter_error_state(dev, true); 1414 1415 return 0; 1416 } 1417 1418 static void shutdown_one(struct pci_dev *pdev) 1419 { 1420 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1421 struct mlx5_priv *priv = &dev->priv; 1422 int err; 1423 1424 set_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &dev->intf_state); 1425 err = mlx5_try_fast_unload(dev); 1426 if (err) 1427 mlx5_unload_one(dev, priv, false); 1428 mlx5_pci_disable_device(dev); 1429 } 1430 1431 static const struct pci_device_id mlx5_core_pci_table[] = { 1432 { PCI_VDEVICE(MELLANOX, 4113) }, /* Connect-IB */ 1433 { PCI_VDEVICE(MELLANOX, 4114) }, /* Connect-IB VF */ 1434 { PCI_VDEVICE(MELLANOX, 4115) }, /* ConnectX-4 */ 1435 { PCI_VDEVICE(MELLANOX, 4116) }, /* ConnectX-4 VF */ 1436 { PCI_VDEVICE(MELLANOX, 4117) }, /* ConnectX-4LX */ 1437 { PCI_VDEVICE(MELLANOX, 4118) }, /* ConnectX-4LX VF */ 1438 { PCI_VDEVICE(MELLANOX, 4119) }, /* ConnectX-5 */ 1439 { PCI_VDEVICE(MELLANOX, 4120) }, /* ConnectX-5 VF */ 1440 { PCI_VDEVICE(MELLANOX, 4121) }, 1441 { PCI_VDEVICE(MELLANOX, 4122) }, 1442 { PCI_VDEVICE(MELLANOX, 4123) }, 1443 { PCI_VDEVICE(MELLANOX, 4124) }, 1444 { PCI_VDEVICE(MELLANOX, 4125) }, 1445 { PCI_VDEVICE(MELLANOX, 4126) }, 1446 { PCI_VDEVICE(MELLANOX, 4127) }, 1447 { PCI_VDEVICE(MELLANOX, 4128) }, 1448 { PCI_VDEVICE(MELLANOX, 4129) }, 1449 { PCI_VDEVICE(MELLANOX, 4130) }, 1450 { PCI_VDEVICE(MELLANOX, 4131) }, 1451 { PCI_VDEVICE(MELLANOX, 4132) }, 1452 { PCI_VDEVICE(MELLANOX, 4133) }, 1453 { PCI_VDEVICE(MELLANOX, 4134) }, 1454 { PCI_VDEVICE(MELLANOX, 4135) }, 1455 { PCI_VDEVICE(MELLANOX, 4136) }, 1456 { PCI_VDEVICE(MELLANOX, 4137) }, 1457 { PCI_VDEVICE(MELLANOX, 4138) }, 1458 { PCI_VDEVICE(MELLANOX, 4139) }, 1459 { PCI_VDEVICE(MELLANOX, 4140) }, 1460 { PCI_VDEVICE(MELLANOX, 4141) }, 1461 { PCI_VDEVICE(MELLANOX, 4142) }, 1462 { PCI_VDEVICE(MELLANOX, 4143) }, 1463 { PCI_VDEVICE(MELLANOX, 4144) }, 1464 { 0, } 1465 }; 1466 1467 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); 1468 1469 void mlx5_disable_device(struct mlx5_core_dev *dev) 1470 { 1471 mlx5_pci_err_detected(dev->pdev, 0); 1472 } 1473 1474 void mlx5_recover_device(struct mlx5_core_dev *dev) 1475 { 1476 mlx5_pci_disable_device(dev); 1477 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED) 1478 mlx5_pci_resume(dev->pdev); 1479 } 1480 1481 struct pci_driver mlx5_core_driver = { 1482 .name = DRIVER_NAME, 1483 .id_table = mlx5_core_pci_table, 1484 .shutdown = shutdown_one, 1485 .probe = init_one, 1486 .remove = remove_one, 1487 .err_handler = &mlx5_err_handler 1488 }; 1489 1490 static int __init init(void) 1491 { 1492 int err; 1493 1494 err = pci_register_driver(&mlx5_core_driver); 1495 if (err) 1496 goto err_debug; 1497 1498 err = mlx5_fwdump_init(); 1499 if (err) 1500 goto err_fwdump; 1501 1502 return 0; 1503 1504 err_fwdump: 1505 pci_unregister_driver(&mlx5_core_driver); 1506 1507 err_debug: 1508 return err; 1509 } 1510 1511 static void __exit cleanup(void) 1512 { 1513 mlx5_fwdump_fini(); 1514 pci_unregister_driver(&mlx5_core_driver); 1515 } 1516 1517 module_init(init); 1518 module_exit(cleanup); 1519