1 /* 2 * Copyright (c) 2015, AVAGO Tech. All rights reserved. Authors: Marian Choy 3 * Copyright (c) 2014, LSI Corp. All rights reserved. Authors: Marian Choy 4 * Support: freebsdraid@avagotech.com 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 2. Redistributions 12 * in binary form must reproduce the above copyright notice, this list of 13 * conditions and the following disclaimer in the documentation and/or other 14 * materials provided with the distribution. 3. Neither the name of the 15 * <ORGANIZATION> nor the names of its contributors may be used to endorse or 16 * promote products derived from this software without specific prior written 17 * permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 * 31 * The views and conclusions contained in the software and documentation are 32 * those of the authors and should not be interpreted as representing 33 * official policies,either expressed or implied, of the FreeBSD Project. 34 * 35 * Send feedback to: <megaraidfbsd@avagotech.com> Mail to: AVAGO TECHNOLOGIES, 1621 36 * Barber Lane, Milpitas, CA 95035 ATTN: MegaRaid FreeBSD 37 * 38 */ 39 40 #include <sys/cdefs.h> 41 __FBSDID("$FreeBSD$"); 42 43 #ifndef MRSAS_H 44 #define MRSAS_H 45 46 #include <sys/param.h> /* defines used in kernel.h */ 47 #include <sys/module.h> 48 #include <sys/systm.h> 49 #include <sys/proc.h> 50 #include <sys/errno.h> 51 #include <sys/kernel.h> /* types used in module initialization */ 52 #include <sys/conf.h> /* cdevsw struct */ 53 #include <sys/uio.h> /* uio struct */ 54 #include <sys/malloc.h> 55 #include <sys/bus.h> /* structs, prototypes for pci bus 56 * stuff */ 57 #include <sys/rman.h> 58 #include <sys/types.h> 59 #include <sys/lock.h> 60 #include <sys/mutex.h> 61 #include <sys/sema.h> 62 #include <sys/sysctl.h> 63 #include <sys/stat.h> 64 #include <sys/taskqueue.h> 65 #include <sys/poll.h> 66 #include <sys/selinfo.h> 67 68 #include <machine/bus.h> 69 #include <machine/resource.h> 70 #include <machine/atomic.h> 71 72 #include <dev/pci/pcivar.h> /* For pci_get macros! */ 73 #include <dev/pci/pcireg.h> 74 75 #define IOCTL_SEMA_DESCRIPTION "mrsas semaphore for MFI pool" 76 77 /* 78 * Device IDs and PCI 79 */ 80 #define MRSAS_TBOLT 0x005b 81 #define MRSAS_INVADER 0x005d 82 #define MRSAS_FURY 0x005f 83 #define MRSAS_INTRUDER 0x00ce 84 #define MRSAS_INTRUDER_24 0x00cf 85 #define MRSAS_CUTLASS_52 0x0052 86 #define MRSAS_CUTLASS_53 0x0053 87 /* Gen3.5 Conroller */ 88 #define MRSAS_VENTURA 0x0014 89 #define MRSAS_CRUSADER 0x0015 90 #define MRSAS_HARPOON 0x0016 91 #define MRSAS_TOMCAT 0x0017 92 #define MRSAS_VENTURA_4PORT 0x001B 93 #define MRSAS_CRUSADER_4PORT 0x001C 94 #define MRSAS_AERO_10E0 0x10E0 95 #define MRSAS_AERO_10E1 0x10E1 96 #define MRSAS_AERO_10E2 0x10E2 97 #define MRSAS_AERO_10E3 0x10E3 98 #define MRSAS_AERO_10E4 0x10E4 99 #define MRSAS_AERO_10E5 0x10E5 100 #define MRSAS_AERO_10E6 0x10E6 101 #define MRSAS_AERO_10E7 0x10E7 102 103 /* 104 * Firmware State Defines 105 */ 106 #define MRSAS_FWSTATE_MAXCMD_MASK 0x0000FFFF 107 #define MRSAS_FWSTATE_SGE_MASK 0x00FF0000 108 #define MRSAS_FW_STATE_CHNG_INTERRUPT 1 109 110 /* 111 * Message Frame Defines 112 */ 113 #define MRSAS_SENSE_LEN 96 114 #define MRSAS_FUSION_MAX_RESET_TRIES 3 115 116 /* 117 * Miscellaneous Defines 118 */ 119 #define BYTE_ALIGNMENT 1 120 #define MRSAS_MAX_NAME_LENGTH 32 121 #define MRSAS_VERSION "07.709.04.00-fbsd" 122 #define MRSAS_ULONG_MAX 0xFFFFFFFFFFFFFFFF 123 #define MRSAS_DEFAULT_TIMEOUT 0x14 /* Temporarily set */ 124 #define DONE 0 125 #define MRSAS_PAGE_SIZE 4096 126 #define MRSAS_RESET_NOTICE_INTERVAL 5 127 #define MRSAS_IO_TIMEOUT 180000 /* 180 second timeout */ 128 #define MRSAS_LDIO_QUEUE_DEPTH 70 /* 70 percent as default */ 129 #define THRESHOLD_REPLY_COUNT 50 130 #define MAX_MSIX_COUNT 128 131 132 #define MAX_STREAMS_TRACKED 8 133 #define MR_STREAM_BITMAP 0x76543210 134 #define BITS_PER_INDEX_STREAM 4 /* number of bits per index in U32 TrackStream */ 135 #define STREAM_MASK ((1 << BITS_PER_INDEX_STREAM) - 1) 136 #define ZERO_LAST_STREAM 0x0fffffff 137 138 /* 139 * Boolean types 140 */ 141 #if (__FreeBSD_version < 901000) 142 typedef enum _boolean { 143 false, true 144 } boolean; 145 146 #endif 147 enum err { 148 SUCCESS, FAIL 149 }; 150 151 MALLOC_DECLARE(M_MRSAS); 152 SYSCTL_DECL(_hw_mrsas); 153 154 #define MRSAS_INFO (1 << 0) 155 #define MRSAS_TRACE (1 << 1) 156 #define MRSAS_FAULT (1 << 2) 157 #define MRSAS_OCR (1 << 3) 158 #define MRSAS_TOUT MRSAS_OCR 159 #define MRSAS_AEN (1 << 4) 160 #define MRSAS_PRL11 (1 << 5) 161 162 #define mrsas_dprint(sc, level, msg, args...) \ 163 do { \ 164 if (sc->mrsas_debug & level) \ 165 device_printf(sc->mrsas_dev, msg, ##args); \ 166 } while (0) 167 168 /**************************************************************************** 169 * Raid Context structure which describes MegaRAID specific IO Paramenters 170 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames 171 ****************************************************************************/ 172 173 typedef struct _RAID_CONTEXT { 174 u_int8_t Type:4; 175 u_int8_t nseg:4; 176 u_int8_t resvd0; 177 u_int16_t timeoutValue; 178 u_int8_t regLockFlags; 179 u_int8_t resvd1; 180 u_int16_t VirtualDiskTgtId; 181 u_int64_t regLockRowLBA; 182 u_int32_t regLockLength; 183 u_int16_t nextLMId; 184 u_int8_t exStatus; 185 u_int8_t status; 186 u_int8_t RAIDFlags; 187 u_int8_t numSGE; 188 u_int16_t configSeqNum; 189 u_int8_t spanArm; 190 u_int8_t priority; /* 0x1D MR_PRIORITY_RANGE */ 191 u_int8_t numSGEExt; /* 0x1E 1M IO support */ 192 u_int8_t resvd2; /* 0x1F */ 193 } RAID_CONTEXT; 194 195 /* 196 * Raid Context structure which describes ventura MegaRAID specific IO Paramenters 197 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames 198 */ 199 typedef struct _RAID_CONTEXT_G35 { 200 u_int16_t Type:4; 201 u_int16_t nseg:4; 202 u_int16_t resvd0:8; 203 u_int16_t timeoutValue; 204 union { 205 struct { 206 u_int16_t reserved:1; 207 u_int16_t sld:1; 208 u_int16_t c2f:1; 209 u_int16_t fwn:1; 210 u_int16_t sqn:1; 211 u_int16_t sbs:1; 212 u_int16_t rw:1; 213 u_int16_t log:1; 214 u_int16_t cpuSel:4; 215 u_int16_t setDivert:4; 216 } bits; 217 u_int16_t s; 218 } routingFlags; 219 u_int16_t VirtualDiskTgtId; 220 u_int64_t regLockRowLBA; 221 u_int32_t regLockLength; 222 union { 223 u_int16_t nextLMId; 224 u_int16_t peerSMID; 225 } smid; 226 u_int8_t exStatus; 227 u_int8_t status; 228 u_int8_t RAIDFlags; 229 u_int8_t spanArm; 230 u_int16_t configSeqNum; 231 u_int16_t numSGE:12; 232 u_int16_t reserved:3; 233 u_int16_t streamDetected:1; 234 u_int8_t resvd2[2]; 235 } RAID_CONTEXT_G35; 236 237 typedef union _RAID_CONTEXT_UNION { 238 RAID_CONTEXT raid_context; 239 RAID_CONTEXT_G35 raid_context_g35; 240 } RAID_CONTEXT_UNION, *PRAID_CONTEXT_UNION; 241 242 /************************************************************************* 243 * MPI2 Defines 244 ************************************************************************/ 245 246 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 247 #define MPI2_WHOINIT_HOST_DRIVER (0x04) 248 #define MPI2_VERSION_MAJOR (0x02) 249 #define MPI2_VERSION_MINOR (0x00) 250 #define MPI2_VERSION_MAJOR_MASK (0xFF00) 251 #define MPI2_VERSION_MAJOR_SHIFT (8) 252 #define MPI2_VERSION_MINOR_MASK (0x00FF) 253 #define MPI2_VERSION_MINOR_SHIFT (0) 254 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 255 MPI2_VERSION_MINOR) 256 #define MPI2_HEADER_VERSION_UNIT (0x10) 257 #define MPI2_HEADER_VERSION_DEV (0x00) 258 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 259 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 260 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 261 #define MPI2_HEADER_VERSION_DEV_SHIFT (0) 262 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV) 263 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 264 #define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000) 265 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400) 266 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003) 267 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200) 268 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100) 269 #define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004) 270 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 271 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) 272 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x03) 273 #define MPI2_REQ_DESCRIPT_FLAGS_FP_IO (0x06) 274 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 275 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 276 #define MPI2_SCSIIO_CONTROL_WRITE (0x01000000) 277 #define MPI2_SCSIIO_CONTROL_READ (0x02000000) 278 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 279 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 280 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 281 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 282 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) 283 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) 284 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF) 285 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4) 286 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB) 287 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2) 288 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) 289 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) 290 291 #ifndef MPI2_POINTER 292 #define MPI2_POINTER * 293 #endif 294 295 /*************************************** 296 * MPI2 Structures 297 ***************************************/ 298 299 typedef struct _MPI25_IEEE_SGE_CHAIN64 { 300 u_int64_t Address; 301 u_int32_t Length; 302 u_int16_t Reserved1; 303 u_int8_t NextChainOffset; 304 u_int8_t Flags; 305 } MPI25_IEEE_SGE_CHAIN64, MPI2_POINTER PTR_MPI25_IEEE_SGE_CHAIN64, 306 Mpi25IeeeSgeChain64_t, MPI2_POINTER pMpi25IeeeSgeChain64_t; 307 308 typedef struct _MPI2_SGE_SIMPLE_UNION { 309 u_int32_t FlagsLength; 310 union { 311 u_int32_t Address32; 312 u_int64_t Address64; 313 } u; 314 } MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION, 315 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t; 316 317 typedef struct { 318 u_int8_t CDB[20]; /* 0x00 */ 319 u_int32_t PrimaryReferenceTag; /* 0x14 */ 320 u_int16_t PrimaryApplicationTag;/* 0x18 */ 321 u_int16_t PrimaryApplicationTagMask; /* 0x1A */ 322 u_int32_t TransferLength; /* 0x1C */ 323 } MPI2_SCSI_IO_CDB_EEDP32, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_EEDP32, 324 Mpi2ScsiIoCdbEedp32_t, MPI2_POINTER pMpi2ScsiIoCdbEedp32_t; 325 326 typedef struct _MPI2_SGE_CHAIN_UNION { 327 u_int16_t Length; 328 u_int8_t NextChainOffset; 329 u_int8_t Flags; 330 union { 331 u_int32_t Address32; 332 u_int64_t Address64; 333 } u; 334 } MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION, 335 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t; 336 337 typedef struct _MPI2_IEEE_SGE_SIMPLE32 { 338 u_int32_t Address; 339 u_int32_t FlagsLength; 340 } MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32, 341 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t; 342 typedef struct _MPI2_IEEE_SGE_SIMPLE64 { 343 u_int64_t Address; 344 u_int32_t Length; 345 u_int16_t Reserved1; 346 u_int8_t Reserved2; 347 u_int8_t Flags; 348 } MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64, 349 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t; 350 351 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION { 352 MPI2_IEEE_SGE_SIMPLE32 Simple32; 353 MPI2_IEEE_SGE_SIMPLE64 Simple64; 354 } MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION, 355 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t; 356 357 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32; 358 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64; 359 360 typedef union _MPI2_IEEE_SGE_CHAIN_UNION { 361 MPI2_IEEE_SGE_CHAIN32 Chain32; 362 MPI2_IEEE_SGE_CHAIN64 Chain64; 363 } MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION, 364 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t; 365 366 typedef union _MPI2_SGE_IO_UNION { 367 MPI2_SGE_SIMPLE_UNION MpiSimple; 368 MPI2_SGE_CHAIN_UNION MpiChain; 369 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 370 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 371 } MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION, 372 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t; 373 374 typedef union { 375 u_int8_t CDB32[32]; 376 MPI2_SCSI_IO_CDB_EEDP32 EEDP32; 377 MPI2_SGE_SIMPLE_UNION SGE; 378 } MPI2_SCSI_IO_CDB_UNION, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_UNION, 379 Mpi2ScsiIoCdb_t, MPI2_POINTER pMpi2ScsiIoCdb_t; 380 381 /**************************************************************************** 382 * * SCSI Task Management messages 383 * ****************************************************************************/ 384 385 /*SCSI Task Management Request Message */ 386 typedef struct _MPI2_SCSI_TASK_MANAGE_REQUEST { 387 u_int16_t DevHandle; /*0x00 */ 388 u_int8_t ChainOffset; /*0x02 */ 389 u_int8_t Function; /*0x03 */ 390 u_int8_t Reserved1; /*0x04 */ 391 u_int8_t TaskType; /*0x05 */ 392 u_int8_t Reserved2; /*0x06 */ 393 u_int8_t MsgFlags; /*0x07 */ 394 u_int8_t VP_ID; /*0x08 */ 395 u_int8_t VF_ID; /*0x09 */ 396 u_int16_t Reserved3; /*0x0A */ 397 u_int8_t LUN[8]; /*0x0C */ 398 u_int32_t Reserved4[7]; /*0x14 */ 399 u_int16_t TaskMID; /*0x30 */ 400 u_int16_t Reserved5; /*0x32 */ 401 } MPI2_SCSI_TASK_MANAGE_REQUEST; 402 403 /*SCSI Task Management Reply Message */ 404 typedef struct _MPI2_SCSI_TASK_MANAGE_REPLY { 405 u_int16_t DevHandle; /*0x00 */ 406 u_int8_t MsgLength; /*0x02 */ 407 u_int8_t Function; /*0x03 */ 408 u_int8_t ResponseCode; /*0x04 */ 409 u_int8_t TaskType; /*0x05 */ 410 u_int8_t Reserved1; /*0x06 */ 411 u_int8_t MsgFlags; /*0x07 */ 412 u_int8_t VP_ID; /*0x08 */ 413 u_int8_t VF_ID; /*0x09 */ 414 u_int16_t Reserved2; /*0x0A */ 415 u_int16_t Reserved3; /*0x0C */ 416 u_int16_t IOCStatus; /*0x0E */ 417 u_int32_t IOCLogInfo; /*0x10 */ 418 u_int32_t TerminationCount; /*0x14 */ 419 u_int32_t ResponseInfo; /*0x18 */ 420 } MPI2_SCSI_TASK_MANAGE_REPLY; 421 422 typedef struct _MR_TM_REQUEST { 423 char request[128]; 424 } MR_TM_REQUEST; 425 426 typedef struct _MR_TM_REPLY { 427 char reply[128]; 428 } MR_TM_REPLY; 429 430 /* SCSI Task Management Request Message */ 431 typedef struct _MR_TASK_MANAGE_REQUEST { 432 /*To be type casted to struct MPI2_SCSI_TASK_MANAGE_REQUEST */ 433 MR_TM_REQUEST TmRequest; 434 union { 435 struct { 436 u_int32_t isTMForLD:1; 437 u_int32_t isTMForPD:1; 438 u_int32_t reserved1:30; 439 u_int32_t reserved2; 440 } tmReqFlags; 441 MR_TM_REPLY TMReply; 442 } uTmReqReply; 443 } MR_TASK_MANAGE_REQUEST; 444 445 /* TaskType values */ 446 #define MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK (0x01) 447 #define MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET (0x02) 448 #define MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET (0x03) 449 #define MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET (0x05) 450 #define MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET (0x06) 451 #define MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK (0x07) 452 #define MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA (0x08) 453 #define MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET (0x09) 454 #define MPI2_SCSITASKMGMT_TASKTYPE_QRY_ASYNC_EVENT (0x0A) 455 456 /* ResponseCode values */ 457 #define MPI2_SCSITASKMGMT_RSP_TM_COMPLETE (0x00) 458 #define MPI2_SCSITASKMGMT_RSP_INVALID_FRAME (0x02) 459 #define MPI2_SCSITASKMGMT_RSP_TM_NOT_SUPPORTED (0x04) 460 #define MPI2_SCSITASKMGMT_RSP_TM_FAILED (0x05) 461 #define MPI2_SCSITASKMGMT_RSP_TM_SUCCEEDED (0x08) 462 #define MPI2_SCSITASKMGMT_RSP_TM_INVALID_LUN (0x09) 463 #define MPI2_SCSITASKMGMT_RSP_TM_OVERLAPPED_TAG (0x0A) 464 #define MPI2_SCSITASKMGMT_RSP_IO_QUEUED_ON_IOC (0x80) 465 466 /* 467 * RAID SCSI IO Request Message Total SGE count will be one less than 468 * _MPI2_SCSI_IO_REQUEST 469 */ 470 typedef struct _MPI2_RAID_SCSI_IO_REQUEST { 471 u_int16_t DevHandle; /* 0x00 */ 472 u_int8_t ChainOffset; /* 0x02 */ 473 u_int8_t Function; /* 0x03 */ 474 u_int16_t Reserved1; /* 0x04 */ 475 u_int8_t Reserved2; /* 0x06 */ 476 u_int8_t MsgFlags; /* 0x07 */ 477 u_int8_t VP_ID; /* 0x08 */ 478 u_int8_t VF_ID; /* 0x09 */ 479 u_int16_t Reserved3; /* 0x0A */ 480 u_int32_t SenseBufferLowAddress;/* 0x0C */ 481 u_int16_t SGLFlags; /* 0x10 */ 482 u_int8_t SenseBufferLength; /* 0x12 */ 483 u_int8_t Reserved4; /* 0x13 */ 484 u_int8_t SGLOffset0; /* 0x14 */ 485 u_int8_t SGLOffset1; /* 0x15 */ 486 u_int8_t SGLOffset2; /* 0x16 */ 487 u_int8_t SGLOffset3; /* 0x17 */ 488 u_int32_t SkipCount; /* 0x18 */ 489 u_int32_t DataLength; /* 0x1C */ 490 u_int32_t BidirectionalDataLength; /* 0x20 */ 491 u_int16_t IoFlags; /* 0x24 */ 492 u_int16_t EEDPFlags; /* 0x26 */ 493 u_int32_t EEDPBlockSize; /* 0x28 */ 494 u_int32_t SecondaryReferenceTag;/* 0x2C */ 495 u_int16_t SecondaryApplicationTag; /* 0x30 */ 496 u_int16_t ApplicationTagTranslationMask; /* 0x32 */ 497 u_int8_t LUN[8]; /* 0x34 */ 498 u_int32_t Control; /* 0x3C */ 499 MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */ 500 RAID_CONTEXT_UNION RaidContext; /* 0x60 */ 501 MPI2_SGE_IO_UNION SGL; /* 0x80 */ 502 } MRSAS_RAID_SCSI_IO_REQUEST, MPI2_POINTER PTR_MRSAS_RAID_SCSI_IO_REQUEST, 503 MRSASRaidSCSIIORequest_t, MPI2_POINTER pMRSASRaidSCSIIORequest_t; 504 505 /* 506 * MPT RAID MFA IO Descriptor. 507 */ 508 typedef struct _MRSAS_RAID_MFA_IO_DESCRIPTOR { 509 u_int32_t RequestFlags:8; 510 u_int32_t MessageAddress1:24; /* bits 31:8 */ 511 u_int32_t MessageAddress2; /* bits 61:32 */ 512 } MRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR, *PMRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR; 513 514 /* Default Request Descriptor */ 515 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR { 516 u_int8_t RequestFlags; /* 0x00 */ 517 u_int8_t MSIxIndex; /* 0x01 */ 518 u_int16_t SMID; /* 0x02 */ 519 u_int16_t LMID; /* 0x04 */ 520 u_int16_t DescriptorTypeDependent; /* 0x06 */ 521 } MPI2_DEFAULT_REQUEST_DESCRIPTOR, 522 523 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR, 524 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t; 525 526 /* High Priority Request Descriptor */ 527 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR { 528 u_int8_t RequestFlags; /* 0x00 */ 529 u_int8_t MSIxIndex; /* 0x01 */ 530 u_int16_t SMID; /* 0x02 */ 531 u_int16_t LMID; /* 0x04 */ 532 u_int16_t Reserved1; /* 0x06 */ 533 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 534 535 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 536 Mpi2HighPriorityRequestDescriptor_t, MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t; 537 538 /* SCSI IO Request Descriptor */ 539 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR { 540 u_int8_t RequestFlags; /* 0x00 */ 541 u_int8_t MSIxIndex; /* 0x01 */ 542 u_int16_t SMID; /* 0x02 */ 543 u_int16_t LMID; /* 0x04 */ 544 u_int16_t DevHandle; /* 0x06 */ 545 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 546 547 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 548 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t; 549 550 /* SCSI Target Request Descriptor */ 551 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR { 552 u_int8_t RequestFlags; /* 0x00 */ 553 u_int8_t MSIxIndex; /* 0x01 */ 554 u_int16_t SMID; /* 0x02 */ 555 u_int16_t LMID; /* 0x04 */ 556 u_int16_t IoIndex; /* 0x06 */ 557 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 558 559 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 560 Mpi2SCSITargetRequestDescriptor_t, MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t; 561 562 /* RAID Accelerator Request Descriptor */ 563 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR { 564 u_int8_t RequestFlags; /* 0x00 */ 565 u_int8_t MSIxIndex; /* 0x01 */ 566 u_int16_t SMID; /* 0x02 */ 567 u_int16_t LMID; /* 0x04 */ 568 u_int16_t Reserved; /* 0x06 */ 569 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 570 571 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 572 Mpi2RAIDAcceleratorRequestDescriptor_t, MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t; 573 574 /* union of Request Descriptors */ 575 typedef union _MRSAS_REQUEST_DESCRIPTOR_UNION { 576 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default; 577 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority; 578 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO; 579 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; 580 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; 581 MRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR MFAIo; 582 union { 583 struct { 584 u_int32_t low; 585 u_int32_t high; 586 } u; 587 u_int64_t Words; 588 } addr; 589 } MRSAS_REQUEST_DESCRIPTOR_UNION; 590 591 /* Default Reply Descriptor */ 592 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR { 593 u_int8_t ReplyFlags; /* 0x00 */ 594 u_int8_t MSIxIndex; /* 0x01 */ 595 u_int16_t DescriptorTypeDependent1; /* 0x02 */ 596 u_int32_t DescriptorTypeDependent2; /* 0x04 */ 597 } MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR, 598 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t; 599 600 /* Address Reply Descriptor */ 601 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR { 602 u_int8_t ReplyFlags; /* 0x00 */ 603 u_int8_t MSIxIndex; /* 0x01 */ 604 u_int16_t SMID; /* 0x02 */ 605 u_int32_t ReplyFrameAddress; /* 0x04 */ 606 } MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR, 607 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t; 608 609 /* SCSI IO Success Reply Descriptor */ 610 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR { 611 u_int8_t ReplyFlags; /* 0x00 */ 612 u_int8_t MSIxIndex; /* 0x01 */ 613 u_int16_t SMID; /* 0x02 */ 614 u_int16_t TaskTag; /* 0x04 */ 615 u_int16_t Reserved1; /* 0x06 */ 616 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 617 618 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 619 Mpi2SCSIIOSuccessReplyDescriptor_t, MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t; 620 621 /* TargetAssist Success Reply Descriptor */ 622 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR { 623 u_int8_t ReplyFlags; /* 0x00 */ 624 u_int8_t MSIxIndex; /* 0x01 */ 625 u_int16_t SMID; /* 0x02 */ 626 u_int8_t SequenceNumber; /* 0x04 */ 627 u_int8_t Reserved1; /* 0x05 */ 628 u_int16_t IoIndex; /* 0x06 */ 629 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 630 631 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 632 Mpi2TargetAssistSuccessReplyDescriptor_t, MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t; 633 634 /* Target Command Buffer Reply Descriptor */ 635 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR { 636 u_int8_t ReplyFlags; /* 0x00 */ 637 u_int8_t MSIxIndex; /* 0x01 */ 638 u_int8_t VP_ID; /* 0x02 */ 639 u_int8_t Flags; /* 0x03 */ 640 u_int16_t InitiatorDevHandle; /* 0x04 */ 641 u_int16_t IoIndex; /* 0x06 */ 642 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 643 644 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 645 Mpi2TargetCommandBufferReplyDescriptor_t, MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t; 646 647 /* RAID Accelerator Success Reply Descriptor */ 648 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR { 649 u_int8_t ReplyFlags; /* 0x00 */ 650 u_int8_t MSIxIndex; /* 0x01 */ 651 u_int16_t SMID; /* 0x02 */ 652 u_int32_t Reserved; /* 0x04 */ 653 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 654 655 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 656 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t, MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t; 657 658 /* union of Reply Descriptors */ 659 typedef union _MPI2_REPLY_DESCRIPTORS_UNION { 660 MPI2_DEFAULT_REPLY_DESCRIPTOR Default; 661 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply; 662 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess; 663 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess; 664 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; 665 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess; 666 u_int64_t Words; 667 } MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION, 668 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t; 669 670 typedef union { 671 volatile unsigned int val; 672 unsigned int val_rdonly; 673 } mrsas_atomic_t; 674 675 #define mrsas_atomic_read(v) atomic_load_acq_int(&(v)->val) 676 #define mrsas_atomic_set(v,i) atomic_store_rel_int(&(v)->val, i) 677 #define mrsas_atomic_dec(v) atomic_subtract_int(&(v)->val, 1) 678 #define mrsas_atomic_inc(v) atomic_add_int(&(v)->val, 1) 679 680 static inline int 681 mrsas_atomic_inc_return(mrsas_atomic_t *v) 682 { 683 return 1 + atomic_fetchadd_int(&(v)->val, 1); 684 } 685 686 /* IOCInit Request message */ 687 typedef struct _MPI2_IOC_INIT_REQUEST { 688 u_int8_t WhoInit; /* 0x00 */ 689 u_int8_t Reserved1; /* 0x01 */ 690 u_int8_t ChainOffset; /* 0x02 */ 691 u_int8_t Function; /* 0x03 */ 692 u_int16_t Reserved2; /* 0x04 */ 693 u_int8_t Reserved3; /* 0x06 */ 694 u_int8_t MsgFlags; /* 0x07 */ 695 u_int8_t VP_ID; /* 0x08 */ 696 u_int8_t VF_ID; /* 0x09 */ 697 u_int16_t Reserved4; /* 0x0A */ 698 u_int16_t MsgVersion; /* 0x0C */ 699 u_int16_t HeaderVersion; /* 0x0E */ 700 u_int32_t Reserved5; /* 0x10 */ 701 u_int16_t Reserved6; /* 0x14 */ 702 u_int8_t HostPageSize; /* 0x16 */ 703 u_int8_t HostMSIxVectors; /* 0x17 */ 704 u_int16_t Reserved8; /* 0x18 */ 705 u_int16_t SystemRequestFrameSize; /* 0x1A */ 706 u_int16_t ReplyDescriptorPostQueueDepth; /* 0x1C */ 707 u_int16_t ReplyFreeQueueDepth; /* 0x1E */ 708 u_int32_t SenseBufferAddressHigh; /* 0x20 */ 709 u_int32_t SystemReplyAddressHigh; /* 0x24 */ 710 u_int64_t SystemRequestFrameBaseAddress; /* 0x28 */ 711 u_int64_t ReplyDescriptorPostQueueAddress; /* 0x30 */ 712 u_int64_t ReplyFreeQueueAddress;/* 0x38 */ 713 u_int64_t TimeStamp; /* 0x40 */ 714 } MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST, 715 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t; 716 717 /* 718 * MR private defines 719 */ 720 #define MR_PD_INVALID 0xFFFF 721 #define MR_DEVHANDLE_INVALID 0xFFFF 722 #define MAX_SPAN_DEPTH 8 723 #define MAX_QUAD_DEPTH MAX_SPAN_DEPTH 724 #define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH) 725 #define MAX_ROW_SIZE 32 726 #define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE) 727 #define MAX_LOGICAL_DRIVES 64 728 #define MAX_LOGICAL_DRIVES_EXT 256 729 #define MAX_LOGICAL_DRIVES_DYN 512 730 731 #define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES) 732 #define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES) 733 734 #define MAX_ARRAYS 128 735 #define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS) 736 737 #define MAX_ARRAYS_EXT 256 738 #define MAX_API_ARRAYS_EXT MAX_ARRAYS_EXT 739 #define MAX_API_ARRAYS_DYN 512 740 741 #define MAX_PHYSICAL_DEVICES 256 742 #define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES) 743 #define MAX_RAIDMAP_PHYSICAL_DEVICES_DYN 512 744 #define MR_DCMD_LD_MAP_GET_INFO 0x0300e101 745 #define MR_DCMD_SYSTEM_PD_MAP_GET_INFO 0x0200e102 746 #define MR_DCMD_PD_MFI_TASK_MGMT 0x0200e100 747 748 #define MR_DCMD_PD_GET_INFO 0x02020000 749 #define MRSAS_MAX_PD_CHANNELS 1 750 #define MRSAS_MAX_LD_CHANNELS 1 751 #define MRSAS_MAX_DEV_PER_CHANNEL 256 752 #define MRSAS_DEFAULT_INIT_ID -1 753 #define MRSAS_MAX_LUN 8 754 #define MRSAS_DEFAULT_CMD_PER_LUN 256 755 #define MRSAS_MAX_PD (MRSAS_MAX_PD_CHANNELS * \ 756 MRSAS_MAX_DEV_PER_CHANNEL) 757 #define MRSAS_MAX_LD_IDS (MRSAS_MAX_LD_CHANNELS * \ 758 MRSAS_MAX_DEV_PER_CHANNEL) 759 760 #define VD_EXT_DEBUG 0 761 #define TM_DEBUG 1 762 763 /******************************************************************* 764 * RAID map related structures 765 ********************************************************************/ 766 #pragma pack(1) 767 typedef struct _MR_DEV_HANDLE_INFO { 768 u_int16_t curDevHdl; 769 u_int8_t validHandles; 770 u_int8_t interfaceType; 771 u_int16_t devHandle[2]; 772 } MR_DEV_HANDLE_INFO; 773 774 #pragma pack() 775 776 typedef struct _MR_ARRAY_INFO { 777 u_int16_t pd[MAX_RAIDMAP_ROW_SIZE]; 778 } MR_ARRAY_INFO; 779 780 typedef struct _MR_QUAD_ELEMENT { 781 u_int64_t logStart; 782 u_int64_t logEnd; 783 u_int64_t offsetInSpan; 784 u_int32_t diff; 785 u_int32_t reserved1; 786 } MR_QUAD_ELEMENT; 787 788 typedef struct _MR_SPAN_INFO { 789 u_int32_t noElements; 790 u_int32_t reserved1; 791 MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH]; 792 } MR_SPAN_INFO; 793 794 typedef struct _MR_LD_SPAN_ { 795 u_int64_t startBlk; 796 u_int64_t numBlks; 797 u_int16_t arrayRef; 798 u_int8_t spanRowSize; 799 u_int8_t spanRowDataSize; 800 u_int8_t reserved[4]; 801 } MR_LD_SPAN; 802 803 typedef struct _MR_SPAN_BLOCK_INFO { 804 u_int64_t num_rows; 805 MR_LD_SPAN span; 806 MR_SPAN_INFO block_span_info; 807 } MR_SPAN_BLOCK_INFO; 808 809 typedef struct _MR_LD_RAID { 810 struct { 811 u_int32_t fpCapable:1; 812 u_int32_t raCapable:1; 813 u_int32_t reserved5:2; 814 u_int32_t ldPiMode:4; 815 u_int32_t pdPiMode:4; 816 u_int32_t encryptionType:8; 817 u_int32_t fpWriteCapable:1; 818 u_int32_t fpReadCapable:1; 819 u_int32_t fpWriteAcrossStripe:1; 820 u_int32_t fpReadAcrossStripe:1; 821 u_int32_t fpNonRWCapable:1; 822 u_int32_t tmCapable:1; 823 u_int32_t fpCacheBypassCapable:1; 824 u_int32_t reserved4:5; 825 } capability; 826 u_int32_t reserved6; 827 u_int64_t size; 828 829 u_int8_t spanDepth; 830 u_int8_t level; 831 u_int8_t stripeShift; 832 u_int8_t rowSize; 833 834 u_int8_t rowDataSize; 835 u_int8_t writeMode; 836 u_int8_t PRL; 837 u_int8_t SRL; 838 839 u_int16_t targetId; 840 u_int8_t ldState; 841 u_int8_t regTypeReqOnWrite; 842 u_int8_t modFactor; 843 u_int8_t regTypeReqOnRead; 844 u_int16_t seqNum; 845 846 struct { 847 u_int32_t ldSyncRequired:1; 848 u_int32_t regTypeReqOnReadLsValid:1; 849 u_int32_t reserved:30; 850 } flags; 851 852 u_int8_t LUN[8]; 853 u_int8_t fpIoTimeoutForLd; 854 u_int8_t reserved2[3]; 855 u_int32_t logicalBlockLength; 856 struct { 857 u_int32_t LdPiExp:4; 858 u_int32_t LdLogicalBlockExp:4; 859 u_int32_t reserved1:24; 860 } exponent; 861 u_int8_t reserved3[0x80 - 0x38]; 862 } MR_LD_RAID; 863 864 typedef struct _MR_LD_SPAN_MAP { 865 MR_LD_RAID ldRaid; 866 u_int8_t dataArmMap[MAX_RAIDMAP_ROW_SIZE]; 867 MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH]; 868 } MR_LD_SPAN_MAP; 869 870 typedef struct _MR_FW_RAID_MAP { 871 u_int32_t totalSize; 872 union { 873 struct { 874 u_int32_t maxLd; 875 u_int32_t maxSpanDepth; 876 u_int32_t maxRowSize; 877 u_int32_t maxPdCount; 878 u_int32_t maxArrays; 879 } validationInfo; 880 u_int32_t version[5]; 881 u_int32_t reserved1[5]; 882 } raid_desc; 883 u_int32_t ldCount; 884 u_int32_t Reserved1; 885 886 /* 887 * This doesn't correspond to FW Ld Tgt Id to LD, but will purge. For 888 * example: if tgt Id is 4 and FW LD is 2, and there is only one LD, 889 * FW will populate the array like this. [0xFF, 0xFF, 0xFF, 0xFF, 890 * 0x0,.....]. This is to help reduce the entire strcture size if 891 * there are few LDs or driver is looking info for 1 LD only. 892 */ 893 u_int8_t ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES + MAX_RAIDMAP_VIEWS]; 894 u_int8_t fpPdIoTimeoutSec; 895 u_int8_t reserved2[7]; 896 MR_ARRAY_INFO arMapInfo[MAX_RAIDMAP_ARRAYS]; 897 MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; 898 MR_LD_SPAN_MAP ldSpanMap[1]; 899 } MR_FW_RAID_MAP; 900 901 typedef struct _MR_FW_RAID_MAP_EXT { 902 /* Not used in new map */ 903 u_int32_t reserved; 904 905 union { 906 struct { 907 u_int32_t maxLd; 908 u_int32_t maxSpanDepth; 909 u_int32_t maxRowSize; 910 u_int32_t maxPdCount; 911 u_int32_t maxArrays; 912 } validationInfo; 913 u_int32_t version[5]; 914 u_int32_t reserved1[5]; 915 } fw_raid_desc; 916 917 u_int8_t fpPdIoTimeoutSec; 918 u_int8_t reserved2[7]; 919 920 u_int16_t ldCount; 921 u_int16_t arCount; 922 u_int16_t spanCount; 923 u_int16_t reserve3; 924 925 MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; 926 u_int8_t ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT]; 927 MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_EXT]; 928 MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT]; 929 } MR_FW_RAID_MAP_EXT; 930 931 typedef struct _MR_DRV_RAID_MAP { 932 /* 933 * Total size of this structure, including this field. This feild 934 * will be manupulated by driver for ext raid map, else pick the 935 * value from firmware raid map. 936 */ 937 u_int32_t totalSize; 938 939 union { 940 struct { 941 u_int32_t maxLd; 942 u_int32_t maxSpanDepth; 943 u_int32_t maxRowSize; 944 u_int32_t maxPdCount; 945 u_int32_t maxArrays; 946 } validationInfo; 947 u_int32_t version[5]; 948 u_int32_t reserved1[5]; 949 } drv_raid_desc; 950 951 /* timeout value used by driver in FP IOs */ 952 u_int8_t fpPdIoTimeoutSec; 953 u_int8_t reserved2[7]; 954 955 u_int16_t ldCount; 956 u_int16_t arCount; 957 u_int16_t spanCount; 958 u_int16_t reserve3; 959 960 MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES_DYN]; 961 u_int16_t ldTgtIdToLd[MAX_LOGICAL_DRIVES_DYN]; 962 MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_DYN]; 963 MR_LD_SPAN_MAP ldSpanMap[1]; 964 965 } MR_DRV_RAID_MAP; 966 967 /* 968 * Driver raid map size is same as raid map ext MR_DRV_RAID_MAP_ALL is 969 * created to sync with old raid. And it is mainly for code re-use purpose. 970 */ 971 972 #pragma pack(1) 973 typedef struct _MR_DRV_RAID_MAP_ALL { 974 MR_DRV_RAID_MAP raidMap; 975 MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_DYN - 1]; 976 } MR_DRV_RAID_MAP_ALL; 977 978 #pragma pack() 979 980 typedef struct _LD_LOAD_BALANCE_INFO { 981 u_int8_t loadBalanceFlag; 982 u_int8_t reserved1; 983 mrsas_atomic_t scsi_pending_cmds[MAX_PHYSICAL_DEVICES]; 984 u_int64_t last_accessed_block[MAX_PHYSICAL_DEVICES]; 985 } LD_LOAD_BALANCE_INFO, *PLD_LOAD_BALANCE_INFO; 986 987 /* SPAN_SET is info caclulated from span info from Raid map per ld */ 988 typedef struct _LD_SPAN_SET { 989 u_int64_t log_start_lba; 990 u_int64_t log_end_lba; 991 u_int64_t span_row_start; 992 u_int64_t span_row_end; 993 u_int64_t data_strip_start; 994 u_int64_t data_strip_end; 995 u_int64_t data_row_start; 996 u_int64_t data_row_end; 997 u_int8_t strip_offset[MAX_SPAN_DEPTH]; 998 u_int32_t span_row_data_width; 999 u_int32_t diff; 1000 u_int32_t reserved[2]; 1001 } LD_SPAN_SET, *PLD_SPAN_SET; 1002 1003 typedef struct LOG_BLOCK_SPAN_INFO { 1004 LD_SPAN_SET span_set[MAX_SPAN_DEPTH]; 1005 } LD_SPAN_INFO, *PLD_SPAN_INFO; 1006 1007 #pragma pack(1) 1008 typedef struct _MR_FW_RAID_MAP_ALL { 1009 MR_FW_RAID_MAP raidMap; 1010 MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1]; 1011 } MR_FW_RAID_MAP_ALL; 1012 1013 #pragma pack() 1014 1015 struct IO_REQUEST_INFO { 1016 u_int64_t ldStartBlock; 1017 u_int32_t numBlocks; 1018 u_int16_t ldTgtId; 1019 u_int8_t isRead; 1020 u_int16_t devHandle; 1021 u_int8_t pdInterface; 1022 u_int64_t pdBlock; 1023 u_int8_t fpOkForIo; 1024 u_int8_t IoforUnevenSpan; 1025 u_int8_t start_span; 1026 u_int8_t reserved; 1027 u_int64_t start_row; 1028 /* span[7:5], arm[4:0] */ 1029 u_int8_t span_arm; 1030 u_int8_t pd_after_lb; 1031 boolean_t raCapable; 1032 u_int16_t r1_alt_dev_handle; 1033 }; 1034 1035 /* 1036 * define MR_PD_CFG_SEQ structure for system PDs 1037 */ 1038 struct MR_PD_CFG_SEQ { 1039 u_int16_t seqNum; 1040 u_int16_t devHandle; 1041 struct { 1042 u_int8_t tmCapable:1; 1043 u_int8_t reserved:7; 1044 } capability; 1045 u_int8_t reserved; 1046 u_int16_t pdTargetId; 1047 } __packed; 1048 1049 struct MR_PD_CFG_SEQ_NUM_SYNC { 1050 u_int32_t size; 1051 u_int32_t count; 1052 struct MR_PD_CFG_SEQ seq[1]; 1053 } __packed; 1054 1055 typedef struct _STREAM_DETECT { 1056 u_int64_t nextSeqLBA; 1057 struct megasas_cmd_fusion *first_cmd_fusion; 1058 struct megasas_cmd_fusion *last_cmd_fusion; 1059 u_int32_t countCmdsInStream; 1060 u_int16_t numSGEsInGroup; 1061 u_int8_t isRead; 1062 u_int8_t groupDepth; 1063 boolean_t groupFlush; 1064 u_int8_t reserved[7]; 1065 } STREAM_DETECT, *PTR_STREAM_DETECT; 1066 1067 typedef struct _LD_STREAM_DETECT { 1068 boolean_t writeBack; 1069 boolean_t FPWriteEnabled; 1070 boolean_t membersSSDs; 1071 boolean_t fpCacheBypassCapable; 1072 u_int32_t mruBitMap; 1073 volatile long iosToFware; 1074 volatile long writeBytesOutstanding; 1075 STREAM_DETECT streamTrack[MAX_STREAMS_TRACKED]; 1076 } LD_STREAM_DETECT, *PTR_LD_STREAM_DETECT; 1077 1078 typedef struct _MR_LD_TARGET_SYNC { 1079 u_int8_t targetId; 1080 u_int8_t reserved; 1081 u_int16_t seqNum; 1082 } MR_LD_TARGET_SYNC; 1083 1084 /* 1085 * RAID Map descriptor Types. 1086 * Each element should uniquely idetify one data structure in the RAID map 1087 */ 1088 typedef enum _MR_RAID_MAP_DESC_TYPE { 1089 RAID_MAP_DESC_TYPE_DEVHDL_INFO = 0, /* MR_DEV_HANDLE_INFO data */ 1090 RAID_MAP_DESC_TYPE_TGTID_INFO = 1, /* target to Ld num Index map */ 1091 RAID_MAP_DESC_TYPE_ARRAY_INFO = 2, /* MR_ARRAY_INFO data */ 1092 RAID_MAP_DESC_TYPE_SPAN_INFO = 3, /* MR_LD_SPAN_MAP data */ 1093 RAID_MAP_DESC_TYPE_COUNT, 1094 } MR_RAID_MAP_DESC_TYPE; 1095 1096 /* 1097 * This table defines the offset, size and num elements of each descriptor 1098 * type in the RAID Map buffer 1099 */ 1100 typedef struct _MR_RAID_MAP_DESC_TABLE { 1101 /* Raid map descriptor type */ 1102 u_int32_t raidMapDescType; 1103 /* Offset into the RAID map buffer where descriptor data is saved */ 1104 u_int32_t raidMapDescOffset; 1105 /* total size of the descriptor buffer */ 1106 u_int32_t raidMapDescBufferSize; 1107 /* Number of elements contained in the descriptor buffer */ 1108 u_int32_t raidMapDescElements; 1109 } MR_RAID_MAP_DESC_TABLE; 1110 1111 /* 1112 * Dynamic Raid Map Structure. 1113 */ 1114 typedef struct _MR_FW_RAID_MAP_DYNAMIC { 1115 u_int32_t raidMapSize; 1116 u_int32_t descTableOffset; 1117 u_int32_t descTableSize; 1118 u_int32_t descTableNumElements; 1119 u_int64_t PCIThresholdBandwidth; 1120 u_int32_t reserved2[3]; 1121 1122 u_int8_t fpPdIoTimeoutSec; 1123 u_int8_t reserved3[3]; 1124 u_int32_t rmwFPSeqNum; 1125 u_int16_t ldCount; 1126 u_int16_t arCount; 1127 u_int16_t spanCount; 1128 u_int16_t reserved4[3]; 1129 1130 /* 1131 * The below structure of pointers is only to be used by the driver. 1132 * This is added in the API to reduce the amount of code changes needed in 1133 * the driver to support dynamic RAID map. 1134 * Firmware should not update these pointers while preparing the raid map 1135 */ 1136 union { 1137 struct { 1138 MR_DEV_HANDLE_INFO *devHndlInfo; 1139 u_int16_t *ldTgtIdToLd; 1140 MR_ARRAY_INFO *arMapInfo; 1141 MR_LD_SPAN_MAP *ldSpanMap; 1142 } ptrStruct; 1143 u_int64_t ptrStructureSize[RAID_MAP_DESC_TYPE_COUNT]; 1144 } RaidMapDescPtrs; 1145 1146 /* 1147 * RAID Map descriptor table defines the layout of data in the RAID Map. 1148 * The size of the descriptor table itself could change. 1149 */ 1150 1151 /* Variable Size descriptor Table. */ 1152 MR_RAID_MAP_DESC_TABLE raidMapDescTable[RAID_MAP_DESC_TYPE_COUNT]; 1153 /* Variable Size buffer containing all data */ 1154 u_int32_t raidMapDescData[1]; 1155 1156 } MR_FW_RAID_MAP_DYNAMIC; 1157 1158 #define IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1159 #define IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 1160 #define IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 1161 #define IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1162 #define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 1163 #define IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1164 #define IEEE_SGE_FLAGS_END_OF_LIST (0x40) 1165 1166 /* Few NVME flags defines*/ 1167 #define MPI2_SGE_FLAGS_SHIFT (0x02) 1168 #define IEEE_SGE_FLAGS_FORMAT_MASK (0xC0) 1169 #define IEEE_SGE_FLAGS_FORMAT_IEEE (0x00) 1170 #define IEEE_SGE_FLAGS_FORMAT_PQI (0x01) 1171 #define IEEE_SGE_FLAGS_FORMAT_NVME (0x02) 1172 #define IEEE_SGE_FLAGS_FORMAT_AHCI (0x03) 1173 1174 #define MPI26_IEEE_SGE_FLAGS_NSF_MASK (0x1C) 1175 #define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE (0x00) 1176 #define MPI26_IEEE_SGE_FLAGS_NSF_PQI (0x04) 1177 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP (0x08) 1178 #define MPI26_IEEE_SGE_FLAGS_NSF_AHCI_PRDT (0x0C) 1179 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_SGL (0x10) 1180 1181 union desc_value { 1182 u_int64_t word; 1183 struct { 1184 u_int32_t low; 1185 u_int32_t high; 1186 } u; 1187 }; 1188 1189 /******************************************************************* 1190 * Temporary command 1191 ********************************************************************/ 1192 struct mrsas_tmp_dcmd { 1193 bus_dma_tag_t tmp_dcmd_tag; 1194 bus_dmamap_t tmp_dcmd_dmamap; 1195 void *tmp_dcmd_mem; 1196 bus_addr_t tmp_dcmd_phys_addr; 1197 }; 1198 1199 #define MR_MAX_RAID_MAP_SIZE_OFFSET_SHIFT 16 1200 #define MR_MAX_RAID_MAP_SIZE_MASK 0x1FF 1201 #define MR_MIN_MAP_SIZE 0x10000 1202 1203 /******************************************************************* 1204 * Register set, included legacy controllers 1068 and 1078, 1205 * structure extended for 1078 registers 1206 *******************************************************************/ 1207 #pragma pack(1) 1208 typedef struct _mrsas_register_set { 1209 u_int32_t doorbell; /* 0000h */ 1210 u_int32_t fusion_seq_offset; /* 0004h */ 1211 u_int32_t fusion_host_diag; /* 0008h */ 1212 u_int32_t reserved_01; /* 000Ch */ 1213 1214 u_int32_t inbound_msg_0; /* 0010h */ 1215 u_int32_t inbound_msg_1; /* 0014h */ 1216 u_int32_t outbound_msg_0; /* 0018h */ 1217 u_int32_t outbound_msg_1; /* 001Ch */ 1218 1219 u_int32_t inbound_doorbell; /* 0020h */ 1220 u_int32_t inbound_intr_status; /* 0024h */ 1221 u_int32_t inbound_intr_mask; /* 0028h */ 1222 1223 u_int32_t outbound_doorbell; /* 002Ch */ 1224 u_int32_t outbound_intr_status; /* 0030h */ 1225 u_int32_t outbound_intr_mask; /* 0034h */ 1226 1227 u_int32_t reserved_1[2]; /* 0038h */ 1228 1229 u_int32_t inbound_queue_port; /* 0040h */ 1230 u_int32_t outbound_queue_port; /* 0044h */ 1231 1232 u_int32_t reserved_2[9]; /* 0048h */ 1233 u_int32_t reply_post_host_index;/* 006Ch */ 1234 u_int32_t reserved_2_2[12]; /* 0070h */ 1235 1236 u_int32_t outbound_doorbell_clear; /* 00A0h */ 1237 1238 u_int32_t reserved_3[3]; /* 00A4h */ 1239 1240 u_int32_t outbound_scratch_pad; /* 00B0h */ 1241 u_int32_t outbound_scratch_pad_2; /* 00B4h */ 1242 u_int32_t outbound_scratch_pad_3; /* 00B8h */ 1243 u_int32_t outbound_scratch_pad_4; /* 00BCh */ 1244 1245 u_int32_t inbound_low_queue_port; /* 00C0h */ 1246 1247 u_int32_t inbound_high_queue_port; /* 00C4h */ 1248 1249 u_int32_t inbound_single_queue_port; /* 00C8h */ 1250 u_int32_t res_6[11]; /* CCh */ 1251 u_int32_t host_diag; 1252 u_int32_t seq_offset; 1253 u_int32_t index_registers[807]; /* 00CCh */ 1254 } mrsas_reg_set; 1255 1256 #pragma pack() 1257 1258 /******************************************************************* 1259 * Firmware Interface Defines 1260 ******************************************************************* 1261 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker 1262 * for protocol between the software and firmware. Commands are 1263 * issued using "message frames". 1264 ******************************************************************/ 1265 /* 1266 * FW posts its state in upper 4 bits of outbound_msg_0 register 1267 */ 1268 #define MFI_STATE_MASK 0xF0000000 1269 #define MFI_STATE_UNDEFINED 0x00000000 1270 #define MFI_STATE_BB_INIT 0x10000000 1271 #define MFI_STATE_FW_INIT 0x40000000 1272 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 1273 #define MFI_STATE_FW_INIT_2 0x70000000 1274 #define MFI_STATE_DEVICE_SCAN 0x80000000 1275 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 1276 #define MFI_STATE_FLUSH_CACHE 0xA0000000 1277 #define MFI_STATE_READY 0xB0000000 1278 #define MFI_STATE_OPERATIONAL 0xC0000000 1279 #define MFI_STATE_FAULT 0xF0000000 1280 #define MFI_RESET_REQUIRED 0x00000001 1281 #define MFI_RESET_ADAPTER 0x00000002 1282 #define MEGAMFI_FRAME_SIZE 64 1283 #define MRSAS_MFI_FRAME_SIZE 1024 1284 #define MRSAS_MFI_SENSE_SIZE 128 1285 1286 /* 1287 * During FW init, clear pending cmds & reset state using inbound_msg_0 1288 * 1289 * ABORT : Abort all pending cmds READY : Move from OPERATIONAL to 1290 * READY state; discard queue info MFIMODE : Discard (possible) low MFA 1291 * posted in 64-bit mode (??) CLR_HANDSHAKE: FW is waiting for HANDSHAKE from 1292 * BIOS or Driver HOTPLUG : Resume from Hotplug MFI_STOP_ADP : Send 1293 * signal to FW to stop processing 1294 */ 1295 1296 #define WRITE_SEQUENCE_OFFSET (0x0000000FC) 1297 #define HOST_DIAGNOSTIC_OFFSET (0x000000F8) 1298 #define DIAG_WRITE_ENABLE (0x00000080) 1299 #define DIAG_RESET_ADAPTER (0x00000004) 1300 1301 #define MFI_ADP_RESET 0x00000040 1302 #define MFI_INIT_ABORT 0x00000001 1303 #define MFI_INIT_READY 0x00000002 1304 #define MFI_INIT_MFIMODE 0x00000004 1305 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 1306 #define MFI_INIT_HOTPLUG 0x00000010 1307 #define MFI_STOP_ADP 0x00000020 1308 #define MFI_RESET_FLAGS MFI_INIT_READY| \ 1309 MFI_INIT_MFIMODE| \ 1310 MFI_INIT_ABORT 1311 1312 /* 1313 * MFI frame flags 1314 */ 1315 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 1316 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 1317 #define MFI_FRAME_SGL32 0x0000 1318 #define MFI_FRAME_SGL64 0x0002 1319 #define MFI_FRAME_SENSE32 0x0000 1320 #define MFI_FRAME_SENSE64 0x0004 1321 #define MFI_FRAME_DIR_NONE 0x0000 1322 #define MFI_FRAME_DIR_WRITE 0x0008 1323 #define MFI_FRAME_DIR_READ 0x0010 1324 #define MFI_FRAME_DIR_BOTH 0x0018 1325 #define MFI_FRAME_IEEE 0x0020 1326 1327 /* 1328 * Definition for cmd_status 1329 */ 1330 #define MFI_CMD_STATUS_POLL_MODE 0xFF 1331 1332 /* 1333 * MFI command opcodes 1334 */ 1335 #define MFI_CMD_INIT 0x00 1336 #define MFI_CMD_LD_READ 0x01 1337 #define MFI_CMD_LD_WRITE 0x02 1338 #define MFI_CMD_LD_SCSI_IO 0x03 1339 #define MFI_CMD_PD_SCSI_IO 0x04 1340 #define MFI_CMD_DCMD 0x05 1341 #define MFI_CMD_ABORT 0x06 1342 #define MFI_CMD_SMP 0x07 1343 #define MFI_CMD_STP 0x08 1344 #define MFI_CMD_INVALID 0xff 1345 1346 #define MR_DCMD_CTRL_GET_INFO 0x01010000 1347 #define MR_DCMD_LD_GET_LIST 0x03010000 1348 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 1349 #define MR_FLUSH_CTRL_CACHE 0x01 1350 #define MR_FLUSH_DISK_CACHE 0x02 1351 1352 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 1353 #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000 1354 #define MR_ENABLE_DRIVE_SPINDOWN 0x01 1355 1356 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 1357 #define MR_DCMD_CTRL_EVENT_GET 0x01040300 1358 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 1359 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 1360 1361 #define MR_DCMD_CLUSTER 0x08000000 1362 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 1363 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200 1364 #define MR_DCMD_PD_LIST_QUERY 0x02010100 1365 1366 #define MR_DCMD_CTRL_MISC_CPX 0x0100e200 1367 #define MR_DCMD_CTRL_MISC_CPX_INIT_DATA_GET 0x0100e201 1368 #define MR_DCMD_CTRL_MISC_CPX_QUEUE_DATA 0x0100e202 1369 #define MR_DCMD_CTRL_MISC_CPX_UNREGISTER 0x0100e203 1370 #define MAX_MR_ROW_SIZE 32 1371 #define MR_CPX_DIR_WRITE 1 1372 #define MR_CPX_DIR_READ 0 1373 #define MR_CPX_VERSION 1 1374 1375 #define MR_DCMD_CTRL_IO_METRICS_GET 0x01170200 1376 1377 #define MR_EVT_CFG_CLEARED 0x0004 1378 1379 #define MR_EVT_LD_STATE_CHANGE 0x0051 1380 #define MR_EVT_PD_INSERTED 0x005b 1381 #define MR_EVT_PD_REMOVED 0x0070 1382 #define MR_EVT_LD_CREATED 0x008a 1383 #define MR_EVT_LD_DELETED 0x008b 1384 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db 1385 #define MR_EVT_LD_OFFLINE 0x00fc 1386 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 1387 #define MR_EVT_CTRL_PERF_COLLECTION 0x017e 1388 1389 /* 1390 * MFI command completion codes 1391 */ 1392 enum MFI_STAT { 1393 MFI_STAT_OK = 0x00, 1394 MFI_STAT_INVALID_CMD = 0x01, 1395 MFI_STAT_INVALID_DCMD = 0x02, 1396 MFI_STAT_INVALID_PARAMETER = 0x03, 1397 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 1398 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 1399 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 1400 MFI_STAT_APP_IN_USE = 0x07, 1401 MFI_STAT_APP_NOT_INITIALIZED = 0x08, 1402 MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 1403 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 1404 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 1405 MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 1406 MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 1407 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 1408 MFI_STAT_FLASH_BUSY = 0x0f, 1409 MFI_STAT_FLASH_ERROR = 0x10, 1410 MFI_STAT_FLASH_IMAGE_BAD = 0x11, 1411 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 1412 MFI_STAT_FLASH_NOT_OPEN = 0x13, 1413 MFI_STAT_FLASH_NOT_STARTED = 0x14, 1414 MFI_STAT_FLUSH_FAILED = 0x15, 1415 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 1416 MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 1417 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 1418 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 1419 MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 1420 MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 1421 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 1422 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 1423 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 1424 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 1425 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 1426 MFI_STAT_MFC_HW_ERROR = 0x21, 1427 MFI_STAT_NO_HW_PRESENT = 0x22, 1428 MFI_STAT_NOT_FOUND = 0x23, 1429 MFI_STAT_NOT_IN_ENCL = 0x24, 1430 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 1431 MFI_STAT_PD_TYPE_WRONG = 0x26, 1432 MFI_STAT_PR_DISABLED = 0x27, 1433 MFI_STAT_ROW_INDEX_INVALID = 0x28, 1434 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 1435 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 1436 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 1437 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 1438 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 1439 MFI_STAT_SCSI_IO_FAILED = 0x2e, 1440 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 1441 MFI_STAT_SHUTDOWN_FAILED = 0x30, 1442 MFI_STAT_TIME_NOT_SET = 0x31, 1443 MFI_STAT_WRONG_STATE = 0x32, 1444 MFI_STAT_LD_OFFLINE = 0x33, 1445 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, 1446 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, 1447 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, 1448 MFI_STAT_I2C_ERRORS_DETECTED = 0x37, 1449 MFI_STAT_PCI_ERRORS_DETECTED = 0x38, 1450 MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67, 1451 1452 MFI_STAT_INVALID_STATUS = 0xFF 1453 }; 1454 1455 /* 1456 * Number of mailbox bytes in DCMD message frame 1457 */ 1458 #define MFI_MBOX_SIZE 12 1459 1460 enum MR_EVT_CLASS { 1461 MR_EVT_CLASS_DEBUG = -2, 1462 MR_EVT_CLASS_PROGRESS = -1, 1463 MR_EVT_CLASS_INFO = 0, 1464 MR_EVT_CLASS_WARNING = 1, 1465 MR_EVT_CLASS_CRITICAL = 2, 1466 MR_EVT_CLASS_FATAL = 3, 1467 MR_EVT_CLASS_DEAD = 4, 1468 1469 }; 1470 1471 enum MR_EVT_LOCALE { 1472 MR_EVT_LOCALE_LD = 0x0001, 1473 MR_EVT_LOCALE_PD = 0x0002, 1474 MR_EVT_LOCALE_ENCL = 0x0004, 1475 MR_EVT_LOCALE_BBU = 0x0008, 1476 MR_EVT_LOCALE_SAS = 0x0010, 1477 MR_EVT_LOCALE_CTRL = 0x0020, 1478 MR_EVT_LOCALE_CONFIG = 0x0040, 1479 MR_EVT_LOCALE_CLUSTER = 0x0080, 1480 MR_EVT_LOCALE_ALL = 0xffff, 1481 1482 }; 1483 1484 enum MR_EVT_ARGS { 1485 MR_EVT_ARGS_NONE, 1486 MR_EVT_ARGS_CDB_SENSE, 1487 MR_EVT_ARGS_LD, 1488 MR_EVT_ARGS_LD_COUNT, 1489 MR_EVT_ARGS_LD_LBA, 1490 MR_EVT_ARGS_LD_OWNER, 1491 MR_EVT_ARGS_LD_LBA_PD_LBA, 1492 MR_EVT_ARGS_LD_PROG, 1493 MR_EVT_ARGS_LD_STATE, 1494 MR_EVT_ARGS_LD_STRIP, 1495 MR_EVT_ARGS_PD, 1496 MR_EVT_ARGS_PD_ERR, 1497 MR_EVT_ARGS_PD_LBA, 1498 MR_EVT_ARGS_PD_LBA_LD, 1499 MR_EVT_ARGS_PD_PROG, 1500 MR_EVT_ARGS_PD_STATE, 1501 MR_EVT_ARGS_PCI, 1502 MR_EVT_ARGS_RATE, 1503 MR_EVT_ARGS_STR, 1504 MR_EVT_ARGS_TIME, 1505 MR_EVT_ARGS_ECC, 1506 MR_EVT_ARGS_LD_PROP, 1507 MR_EVT_ARGS_PD_SPARE, 1508 MR_EVT_ARGS_PD_INDEX, 1509 MR_EVT_ARGS_DIAG_PASS, 1510 MR_EVT_ARGS_DIAG_FAIL, 1511 MR_EVT_ARGS_PD_LBA_LBA, 1512 MR_EVT_ARGS_PORT_PHY, 1513 MR_EVT_ARGS_PD_MISSING, 1514 MR_EVT_ARGS_PD_ADDRESS, 1515 MR_EVT_ARGS_BITMAP, 1516 MR_EVT_ARGS_CONNECTOR, 1517 MR_EVT_ARGS_PD_PD, 1518 MR_EVT_ARGS_PD_FRU, 1519 MR_EVT_ARGS_PD_PATHINFO, 1520 MR_EVT_ARGS_PD_POWER_STATE, 1521 MR_EVT_ARGS_GENERIC, 1522 }; 1523 1524 /* 1525 * Thunderbolt (and later) Defines 1526 */ 1527 #define MEGASAS_CHAIN_FRAME_SZ_MIN 1024 1528 #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009) 1529 #define MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256 1530 #define MRSAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0 1531 #define MRSAS_MPI2_FUNCTION_LD_IO_REQUEST 0xF1 1532 #define MRSAS_LOAD_BALANCE_FLAG 0x1 1533 #define MRSAS_DCMD_MBOX_PEND_FLAG 0x1 1534 #define HOST_DIAG_WRITE_ENABLE 0x80 1535 #define HOST_DIAG_RESET_ADAPTER 0x4 1536 #define MRSAS_TBOLT_MAX_RESET_TRIES 3 1537 #define MRSAS_MAX_MFI_CMDS 16 1538 #define MRSAS_MAX_IOCTL_CMDS 3 1539 1540 /* 1541 * Invader Defines 1542 */ 1543 #define MPI2_TYPE_CUDA 0x2 1544 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH 0x4000 1545 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU0 0x00 1546 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU1 0x10 1547 #define MR_RL_FLAGS_GRANT_DESTINATION_CUDA 0x80 1548 #define MR_RL_FLAGS_SEQ_NUM_ENABLE 0x8 1549 #define MR_RL_WRITE_THROUGH_MODE 0x00 1550 #define MR_RL_WRITE_BACK_MODE 0x01 1551 1552 /* 1553 * T10 PI defines 1554 */ 1555 #define MR_PROT_INFO_TYPE_CONTROLLER 0x8 1556 #define MRSAS_SCSI_VARIABLE_LENGTH_CMD 0x7f 1557 #define MRSAS_SCSI_SERVICE_ACTION_READ32 0x9 1558 #define MRSAS_SCSI_SERVICE_ACTION_WRITE32 0xB 1559 #define MRSAS_SCSI_ADDL_CDB_LEN 0x18 1560 #define MRSAS_RD_WR_PROTECT_CHECK_ALL 0x20 1561 #define MRSAS_RD_WR_PROTECT_CHECK_NONE 0x60 1562 #define MRSAS_SCSIBLOCKSIZE 512 1563 1564 /* 1565 * Raid context flags 1566 */ 1567 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4 1568 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30 1569 typedef enum MR_RAID_FLAGS_IO_SUB_TYPE { 1570 MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0, 1571 MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1, 1572 MR_RAID_FLAGS_IO_SUB_TYPE_RMW_DATA = 2, 1573 MR_RAID_FLAGS_IO_SUB_TYPE_RMW_P = 3, 1574 MR_RAID_FLAGS_IO_SUB_TYPE_RMW_Q = 4, 1575 MR_RAID_FLAGS_IO_SUB_TYPE_CACHE_BYPASS = 6, 1576 MR_RAID_FLAGS_IO_SUB_TYPE_LDIO_BW_LIMIT = 7 1577 } MR_RAID_FLAGS_IO_SUB_TYPE; 1578 /* 1579 * Request descriptor types 1580 */ 1581 #define MRSAS_REQ_DESCRIPT_FLAGS_LD_IO 0x7 1582 #define MRSAS_REQ_DESCRIPT_FLAGS_MFA 0x1 1583 #define MRSAS_REQ_DESCRIPT_FLAGS_NO_LOCK 0x2 1584 #define MRSAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 1 1585 #define MRSAS_FP_CMD_LEN 16 1586 #define MRSAS_FUSION_IN_RESET 0 1587 1588 #define RAID_CTX_SPANARM_ARM_SHIFT (0) 1589 #define RAID_CTX_SPANARM_ARM_MASK (0x1f) 1590 #define RAID_CTX_SPANARM_SPAN_SHIFT (5) 1591 #define RAID_CTX_SPANARM_SPAN_MASK (0xE0) 1592 1593 /* 1594 * Define region lock types 1595 */ 1596 typedef enum _REGION_TYPE { 1597 REGION_TYPE_UNUSED = 0, 1598 REGION_TYPE_SHARED_READ = 1, 1599 REGION_TYPE_SHARED_WRITE = 2, 1600 REGION_TYPE_EXCLUSIVE = 3, 1601 } REGION_TYPE; 1602 1603 /* 1604 * SCSI-CAM Related Defines 1605 */ 1606 #define MRSAS_SCSI_MAX_LUNS 0 1607 #define MRSAS_SCSI_INITIATOR_ID 255 1608 #define MRSAS_SCSI_MAX_CMDS 8 1609 #define MRSAS_SCSI_MAX_CDB_LEN 16 1610 #define MRSAS_SCSI_SENSE_BUFFERSIZE 96 1611 #define MRSAS_INTERNAL_CMDS 32 1612 #define MRSAS_FUSION_INT_CMDS 8 1613 1614 #define MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK 0x400000 1615 #define MEGASAS_MAX_CHAIN_SIZE_MASK 0x3E0 1616 #define MEGASAS_256K_IO 128 1617 #define MEGASAS_1MB_IO (MEGASAS_256K_IO * 4) 1618 1619 /* Request types */ 1620 #define MRSAS_REQ_TYPE_INTERNAL_CMD 0x0 1621 #define MRSAS_REQ_TYPE_AEN_FETCH 0x1 1622 #define MRSAS_REQ_TYPE_PASSTHRU 0x2 1623 #define MRSAS_REQ_TYPE_GETSET_PARAM 0x3 1624 #define MRSAS_REQ_TYPE_SCSI_IO 0x4 1625 1626 /* Request states */ 1627 #define MRSAS_REQ_STATE_FREE 0 1628 #define MRSAS_REQ_STATE_BUSY 1 1629 #define MRSAS_REQ_STATE_TRAN 2 1630 #define MRSAS_REQ_STATE_COMPLETE 3 1631 1632 typedef enum _MR_SCSI_CMD_TYPE { 1633 READ_WRITE_LDIO = 0, 1634 NON_READ_WRITE_LDIO = 1, 1635 READ_WRITE_SYSPDIO = 2, 1636 NON_READ_WRITE_SYSPDIO = 3, 1637 } MR_SCSI_CMD_TYPE; 1638 1639 enum mrsas_req_flags { 1640 MRSAS_DIR_UNKNOWN = 0x1, 1641 MRSAS_DIR_IN = 0x2, 1642 MRSAS_DIR_OUT = 0x4, 1643 MRSAS_DIR_NONE = 0x8, 1644 }; 1645 1646 /* 1647 * Adapter Reset States 1648 */ 1649 enum { 1650 MRSAS_HBA_OPERATIONAL = 0, 1651 MRSAS_ADPRESET_SM_INFAULT = 1, 1652 MRSAS_ADPRESET_SM_FW_RESET_SUCCESS = 2, 1653 MRSAS_ADPRESET_SM_OPERATIONAL = 3, 1654 MRSAS_HW_CRITICAL_ERROR = 4, 1655 MRSAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD, 1656 }; 1657 1658 /* 1659 * MPT Command Structure 1660 */ 1661 struct mrsas_mpt_cmd { 1662 MRSAS_RAID_SCSI_IO_REQUEST *io_request; 1663 bus_addr_t io_request_phys_addr; 1664 MPI2_SGE_IO_UNION *chain_frame; 1665 bus_addr_t chain_frame_phys_addr; 1666 u_int32_t sge_count; 1667 u_int8_t *sense; 1668 bus_addr_t sense_phys_addr; 1669 u_int8_t retry_for_fw_reset; 1670 MRSAS_REQUEST_DESCRIPTOR_UNION *request_desc; 1671 u_int32_t sync_cmd_idx; 1672 u_int32_t index; 1673 u_int8_t flags; 1674 u_int8_t pd_r1_lb; 1675 u_int8_t load_balance; 1676 bus_size_t length; 1677 u_int32_t error_code; 1678 bus_dmamap_t data_dmamap; 1679 void *data; 1680 union ccb *ccb_ptr; 1681 struct callout cm_callout; 1682 struct mrsas_softc *sc; 1683 boolean_t tmCapable; 1684 u_int16_t r1_alt_dev_handle; 1685 boolean_t cmd_completed; 1686 struct mrsas_mpt_cmd *peer_cmd; 1687 bool callout_owner; 1688 TAILQ_ENTRY(mrsas_mpt_cmd) next; 1689 u_int8_t pdInterface; 1690 }; 1691 1692 /* 1693 * MFI Command Structure 1694 */ 1695 struct mrsas_mfi_cmd { 1696 union mrsas_frame *frame; 1697 bus_dmamap_t frame_dmamap; 1698 void *frame_mem; 1699 bus_addr_t frame_phys_addr; 1700 u_int8_t *sense; 1701 bus_dmamap_t sense_dmamap; 1702 void *sense_mem; 1703 bus_addr_t sense_phys_addr; 1704 u_int32_t index; 1705 u_int8_t sync_cmd; 1706 u_int8_t cmd_status; 1707 u_int8_t abort_aen; 1708 u_int8_t retry_for_fw_reset; 1709 struct mrsas_softc *sc; 1710 union ccb *ccb_ptr; 1711 union { 1712 struct { 1713 u_int16_t smid; 1714 u_int16_t resvd; 1715 } context; 1716 u_int32_t frame_count; 1717 } cmd_id; 1718 TAILQ_ENTRY(mrsas_mfi_cmd) next; 1719 }; 1720 1721 /* 1722 * define constants for device list query options 1723 */ 1724 enum MR_PD_QUERY_TYPE { 1725 MR_PD_QUERY_TYPE_ALL = 0, 1726 MR_PD_QUERY_TYPE_STATE = 1, 1727 MR_PD_QUERY_TYPE_POWER_STATE = 2, 1728 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 1729 MR_PD_QUERY_TYPE_SPEED = 4, 1730 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5, 1731 }; 1732 1733 #define MR_EVT_CFG_CLEARED 0x0004 1734 #define MR_EVT_LD_STATE_CHANGE 0x0051 1735 #define MR_EVT_PD_INSERTED 0x005b 1736 #define MR_EVT_PD_REMOVED 0x0070 1737 #define MR_EVT_LD_CREATED 0x008a 1738 #define MR_EVT_LD_DELETED 0x008b 1739 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db 1740 #define MR_EVT_LD_OFFLINE 0x00fc 1741 #define MR_EVT_CTRL_PROP_CHANGED 0x012f 1742 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 1743 1744 enum MR_PD_STATE { 1745 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00, 1746 MR_PD_STATE_UNCONFIGURED_BAD = 0x01, 1747 MR_PD_STATE_HOT_SPARE = 0x02, 1748 MR_PD_STATE_OFFLINE = 0x10, 1749 MR_PD_STATE_FAILED = 0x11, 1750 MR_PD_STATE_REBUILD = 0x14, 1751 MR_PD_STATE_ONLINE = 0x18, 1752 MR_PD_STATE_COPYBACK = 0x20, 1753 MR_PD_STATE_SYSTEM = 0x40, 1754 }; 1755 1756 /* 1757 * defines the physical drive address structure 1758 */ 1759 #pragma pack(1) 1760 struct MR_PD_ADDRESS { 1761 u_int16_t deviceId; 1762 u_int16_t enclDeviceId; 1763 1764 union { 1765 struct { 1766 u_int8_t enclIndex; 1767 u_int8_t slotNumber; 1768 } mrPdAddress; 1769 struct { 1770 u_int8_t enclPosition; 1771 u_int8_t enclConnectorIndex; 1772 } mrEnclAddress; 1773 } u1; 1774 u_int8_t scsiDevType; 1775 union { 1776 u_int8_t connectedPortBitmap; 1777 u_int8_t connectedPortNumbers; 1778 } u2; 1779 u_int64_t sasAddr[2]; 1780 }; 1781 1782 #pragma pack() 1783 1784 /* 1785 * defines the physical drive list structure 1786 */ 1787 #pragma pack(1) 1788 struct MR_PD_LIST { 1789 u_int32_t size; 1790 u_int32_t count; 1791 struct MR_PD_ADDRESS addr[1]; 1792 }; 1793 1794 #pragma pack() 1795 1796 #pragma pack(1) 1797 struct mrsas_pd_list { 1798 u_int16_t tid; 1799 u_int8_t driveType; 1800 u_int8_t driveState; 1801 }; 1802 1803 #pragma pack() 1804 1805 /* 1806 * defines the logical drive reference structure 1807 */ 1808 typedef union _MR_LD_REF { 1809 struct { 1810 u_int8_t targetId; 1811 u_int8_t reserved; 1812 u_int16_t seqNum; 1813 } ld_context; 1814 u_int32_t ref; 1815 } MR_LD_REF; 1816 1817 /* 1818 * defines the logical drive list structure 1819 */ 1820 #pragma pack(1) 1821 struct MR_LD_LIST { 1822 u_int32_t ldCount; 1823 u_int32_t reserved; 1824 struct { 1825 MR_LD_REF ref; 1826 u_int8_t state; 1827 u_int8_t reserved[3]; 1828 u_int64_t size; 1829 } ldList[MAX_LOGICAL_DRIVES_EXT]; 1830 }; 1831 1832 #pragma pack() 1833 1834 /* 1835 * SAS controller properties 1836 */ 1837 #pragma pack(1) 1838 struct mrsas_ctrl_prop { 1839 u_int16_t seq_num; 1840 u_int16_t pred_fail_poll_interval; 1841 u_int16_t intr_throttle_count; 1842 u_int16_t intr_throttle_timeouts; 1843 u_int8_t rebuild_rate; 1844 u_int8_t patrol_read_rate; 1845 u_int8_t bgi_rate; 1846 u_int8_t cc_rate; 1847 u_int8_t recon_rate; 1848 u_int8_t cache_flush_interval; 1849 u_int8_t spinup_drv_count; 1850 u_int8_t spinup_delay; 1851 u_int8_t cluster_enable; 1852 u_int8_t coercion_mode; 1853 u_int8_t alarm_enable; 1854 u_int8_t disable_auto_rebuild; 1855 u_int8_t disable_battery_warn; 1856 u_int8_t ecc_bucket_size; 1857 u_int16_t ecc_bucket_leak_rate; 1858 u_int8_t restore_hotspare_on_insertion; 1859 u_int8_t expose_encl_devices; 1860 u_int8_t maintainPdFailHistory; 1861 u_int8_t disallowHostRequestReordering; 1862 u_int8_t abortCCOnError; 1863 u_int8_t loadBalanceMode; 1864 u_int8_t disableAutoDetectBackplane; 1865 u_int8_t snapVDSpace; 1866 /* 1867 * Add properties that can be controlled by a bit in the following 1868 * structure. 1869 */ 1870 struct { 1871 u_int32_t copyBackDisabled:1; 1872 u_int32_t SMARTerEnabled:1; 1873 u_int32_t prCorrectUnconfiguredAreas:1; 1874 u_int32_t useFdeOnly:1; 1875 u_int32_t disableNCQ:1; 1876 u_int32_t SSDSMARTerEnabled:1; 1877 u_int32_t SSDPatrolReadEnabled:1; 1878 u_int32_t enableSpinDownUnconfigured:1; 1879 u_int32_t autoEnhancedImport:1; 1880 u_int32_t enableSecretKeyControl:1; 1881 u_int32_t disableOnlineCtrlReset:1; 1882 u_int32_t allowBootWithPinnedCache:1; 1883 u_int32_t disableSpinDownHS:1; 1884 u_int32_t enableJBOD:1; 1885 u_int32_t disableCacheBypass:1; 1886 u_int32_t useDiskActivityForLocate:1; 1887 u_int32_t enablePI:1; 1888 u_int32_t preventPIImport:1; 1889 u_int32_t useGlobalSparesForEmergency:1; 1890 u_int32_t useUnconfGoodForEmergency:1; 1891 u_int32_t useEmergencySparesforSMARTer:1; 1892 u_int32_t forceSGPIOForQuadOnly:1; 1893 u_int32_t enableConfigAutoBalance:1; 1894 u_int32_t enableVirtualCache:1; 1895 u_int32_t enableAutoLockRecovery:1; 1896 u_int32_t disableImmediateIO:1; 1897 u_int32_t disableT10RebuildAssist:1; 1898 u_int32_t ignore64ldRestriction:1; 1899 u_int32_t enableSwZone:1; 1900 u_int32_t limitMaxRateSATA3G:1; 1901 u_int32_t reserved:2; 1902 } OnOffProperties; 1903 u_int8_t autoSnapVDSpace; 1904 u_int8_t viewSpace; 1905 u_int16_t spinDownTime; 1906 u_int8_t reserved[24]; 1907 1908 }; 1909 1910 #pragma pack() 1911 1912 /* 1913 * SAS controller information 1914 */ 1915 struct mrsas_ctrl_info { 1916 /* 1917 * PCI device information 1918 */ 1919 struct { 1920 u_int16_t vendor_id; 1921 u_int16_t device_id; 1922 u_int16_t sub_vendor_id; 1923 u_int16_t sub_device_id; 1924 u_int8_t reserved[24]; 1925 } __packed pci; 1926 /* 1927 * Host interface information 1928 */ 1929 struct { 1930 u_int8_t PCIX:1; 1931 u_int8_t PCIE:1; 1932 u_int8_t iSCSI:1; 1933 u_int8_t SAS_3G:1; 1934 u_int8_t reserved_0:4; 1935 u_int8_t reserved_1[6]; 1936 u_int8_t port_count; 1937 u_int64_t port_addr[8]; 1938 } __packed host_interface; 1939 /* 1940 * Device (backend) interface information 1941 */ 1942 struct { 1943 u_int8_t SPI:1; 1944 u_int8_t SAS_3G:1; 1945 u_int8_t SATA_1_5G:1; 1946 u_int8_t SATA_3G:1; 1947 u_int8_t reserved_0:4; 1948 u_int8_t reserved_1[6]; 1949 u_int8_t port_count; 1950 u_int64_t port_addr[8]; 1951 } __packed device_interface; 1952 1953 u_int32_t image_check_word; 1954 u_int32_t image_component_count; 1955 1956 struct { 1957 char name[8]; 1958 char version[32]; 1959 char build_date[16]; 1960 char built_time[16]; 1961 } __packed image_component[8]; 1962 1963 u_int32_t pending_image_component_count; 1964 1965 struct { 1966 char name[8]; 1967 char version[32]; 1968 char build_date[16]; 1969 char build_time[16]; 1970 } __packed pending_image_component[8]; 1971 1972 u_int8_t max_arms; 1973 u_int8_t max_spans; 1974 u_int8_t max_arrays; 1975 u_int8_t max_lds; 1976 char product_name[80]; 1977 char serial_no[32]; 1978 1979 /* 1980 * Other physical/controller/operation information. Indicates the 1981 * presence of the hardware 1982 */ 1983 struct { 1984 u_int32_t bbu:1; 1985 u_int32_t alarm:1; 1986 u_int32_t nvram:1; 1987 u_int32_t uart:1; 1988 u_int32_t reserved:28; 1989 } __packed hw_present; 1990 1991 u_int32_t current_fw_time; 1992 1993 /* 1994 * Maximum data transfer sizes 1995 */ 1996 u_int16_t max_concurrent_cmds; 1997 u_int16_t max_sge_count; 1998 u_int32_t max_request_size; 1999 2000 /* 2001 * Logical and physical device counts 2002 */ 2003 u_int16_t ld_present_count; 2004 u_int16_t ld_degraded_count; 2005 u_int16_t ld_offline_count; 2006 2007 u_int16_t pd_present_count; 2008 u_int16_t pd_disk_present_count; 2009 u_int16_t pd_disk_pred_failure_count; 2010 u_int16_t pd_disk_failed_count; 2011 2012 /* 2013 * Memory size information 2014 */ 2015 u_int16_t nvram_size; 2016 u_int16_t memory_size; 2017 u_int16_t flash_size; 2018 2019 /* 2020 * Error counters 2021 */ 2022 u_int16_t mem_correctable_error_count; 2023 u_int16_t mem_uncorrectable_error_count; 2024 2025 /* 2026 * Cluster information 2027 */ 2028 u_int8_t cluster_permitted; 2029 u_int8_t cluster_active; 2030 2031 /* 2032 * Additional max data transfer sizes 2033 */ 2034 u_int16_t max_strips_per_io; 2035 2036 /* 2037 * Controller capabilities structures 2038 */ 2039 struct { 2040 u_int32_t raid_level_0:1; 2041 u_int32_t raid_level_1:1; 2042 u_int32_t raid_level_5:1; 2043 u_int32_t raid_level_1E:1; 2044 u_int32_t raid_level_6:1; 2045 u_int32_t reserved:27; 2046 } __packed raid_levels; 2047 2048 struct { 2049 u_int32_t rbld_rate:1; 2050 u_int32_t cc_rate:1; 2051 u_int32_t bgi_rate:1; 2052 u_int32_t recon_rate:1; 2053 u_int32_t patrol_rate:1; 2054 u_int32_t alarm_control:1; 2055 u_int32_t cluster_supported:1; 2056 u_int32_t bbu:1; 2057 u_int32_t spanning_allowed:1; 2058 u_int32_t dedicated_hotspares:1; 2059 u_int32_t revertible_hotspares:1; 2060 u_int32_t foreign_config_import:1; 2061 u_int32_t self_diagnostic:1; 2062 u_int32_t mixed_redundancy_arr:1; 2063 u_int32_t global_hot_spares:1; 2064 u_int32_t reserved:17; 2065 } __packed adapter_operations; 2066 2067 struct { 2068 u_int32_t read_policy:1; 2069 u_int32_t write_policy:1; 2070 u_int32_t io_policy:1; 2071 u_int32_t access_policy:1; 2072 u_int32_t disk_cache_policy:1; 2073 u_int32_t reserved:27; 2074 } __packed ld_operations; 2075 2076 struct { 2077 u_int8_t min; 2078 u_int8_t max; 2079 u_int8_t reserved[2]; 2080 } __packed stripe_sz_ops; 2081 2082 struct { 2083 u_int32_t force_online:1; 2084 u_int32_t force_offline:1; 2085 u_int32_t force_rebuild:1; 2086 u_int32_t reserved:29; 2087 } __packed pd_operations; 2088 2089 struct { 2090 u_int32_t ctrl_supports_sas:1; 2091 u_int32_t ctrl_supports_sata:1; 2092 u_int32_t allow_mix_in_encl:1; 2093 u_int32_t allow_mix_in_ld:1; 2094 u_int32_t allow_sata_in_cluster:1; 2095 u_int32_t reserved:27; 2096 } __packed pd_mix_support; 2097 2098 /* 2099 * Define ECC single-bit-error bucket information 2100 */ 2101 u_int8_t ecc_bucket_count; 2102 u_int8_t reserved_2[11]; 2103 2104 /* 2105 * Include the controller properties (changeable items) 2106 */ 2107 struct mrsas_ctrl_prop properties; 2108 2109 /* 2110 * Define FW pkg version (set in envt v'bles on OEM basis) 2111 */ 2112 char package_version[0x60]; 2113 2114 u_int64_t deviceInterfacePortAddr2[8]; 2115 u_int8_t reserved3[128]; 2116 2117 struct { 2118 u_int16_t minPdRaidLevel_0:4; 2119 u_int16_t maxPdRaidLevel_0:12; 2120 2121 u_int16_t minPdRaidLevel_1:4; 2122 u_int16_t maxPdRaidLevel_1:12; 2123 2124 u_int16_t minPdRaidLevel_5:4; 2125 u_int16_t maxPdRaidLevel_5:12; 2126 2127 u_int16_t minPdRaidLevel_1E:4; 2128 u_int16_t maxPdRaidLevel_1E:12; 2129 2130 u_int16_t minPdRaidLevel_6:4; 2131 u_int16_t maxPdRaidLevel_6:12; 2132 2133 u_int16_t minPdRaidLevel_10:4; 2134 u_int16_t maxPdRaidLevel_10:12; 2135 2136 u_int16_t minPdRaidLevel_50:4; 2137 u_int16_t maxPdRaidLevel_50:12; 2138 2139 u_int16_t minPdRaidLevel_60:4; 2140 u_int16_t maxPdRaidLevel_60:12; 2141 2142 u_int16_t minPdRaidLevel_1E_RLQ0:4; 2143 u_int16_t maxPdRaidLevel_1E_RLQ0:12; 2144 2145 u_int16_t minPdRaidLevel_1E0_RLQ0:4; 2146 u_int16_t maxPdRaidLevel_1E0_RLQ0:12; 2147 2148 u_int16_t reserved[6]; 2149 } pdsForRaidLevels; 2150 2151 u_int16_t maxPds; /* 0x780 */ 2152 u_int16_t maxDedHSPs; /* 0x782 */ 2153 u_int16_t maxGlobalHSPs; /* 0x784 */ 2154 u_int16_t ddfSize; /* 0x786 */ 2155 u_int8_t maxLdsPerArray; /* 0x788 */ 2156 u_int8_t partitionsInDDF; /* 0x789 */ 2157 u_int8_t lockKeyBinding; /* 0x78a */ 2158 u_int8_t maxPITsPerLd; /* 0x78b */ 2159 u_int8_t maxViewsPerLd; /* 0x78c */ 2160 u_int8_t maxTargetId; /* 0x78d */ 2161 u_int16_t maxBvlVdSize; /* 0x78e */ 2162 2163 u_int16_t maxConfigurableSSCSize; /* 0x790 */ 2164 u_int16_t currentSSCsize; /* 0x792 */ 2165 2166 char expanderFwVersion[12]; /* 0x794 */ 2167 2168 u_int16_t PFKTrialTimeRemaining;/* 0x7A0 */ 2169 2170 u_int16_t cacheMemorySize; /* 0x7A2 */ 2171 2172 struct { /* 0x7A4 */ 2173 u_int32_t supportPIcontroller:1; 2174 u_int32_t supportLdPIType1:1; 2175 u_int32_t supportLdPIType2:1; 2176 u_int32_t supportLdPIType3:1; 2177 u_int32_t supportLdBBMInfo:1; 2178 u_int32_t supportShieldState:1; 2179 u_int32_t blockSSDWriteCacheChange:1; 2180 u_int32_t supportSuspendResumeBGops:1; 2181 u_int32_t supportEmergencySpares:1; 2182 u_int32_t supportSetLinkSpeed:1; 2183 u_int32_t supportBootTimePFKChange:1; 2184 u_int32_t supportJBOD:1; 2185 u_int32_t disableOnlinePFKChange:1; 2186 u_int32_t supportPerfTuning:1; 2187 u_int32_t supportSSDPatrolRead:1; 2188 u_int32_t realTimeScheduler:1; 2189 2190 u_int32_t supportResetNow:1; 2191 u_int32_t supportEmulatedDrives:1; 2192 u_int32_t headlessMode:1; 2193 u_int32_t dedicatedHotSparesLimited:1; 2194 2195 u_int32_t supportUnevenSpans:1; 2196 u_int32_t reserved:11; 2197 } adapterOperations2; 2198 2199 u_int8_t driverVersion[32]; /* 0x7A8 */ 2200 u_int8_t maxDAPdCountSpinup60; /* 0x7C8 */ 2201 u_int8_t temperatureROC; /* 0x7C9 */ 2202 u_int8_t temperatureCtrl; /* 0x7CA */ 2203 u_int8_t reserved4; /* 0x7CB */ 2204 u_int16_t maxConfigurablePds; /* 0x7CC */ 2205 2206 u_int8_t reserved5[2]; /* 0x7CD reserved */ 2207 2208 struct { 2209 u_int32_t peerIsPresent:1; 2210 u_int32_t peerIsIncompatible:1; 2211 2212 u_int32_t hwIncompatible:1; 2213 u_int32_t fwVersionMismatch:1; 2214 u_int32_t ctrlPropIncompatible:1; 2215 u_int32_t premiumFeatureMismatch:1; 2216 u_int32_t reserved:26; 2217 } cluster; 2218 2219 char clusterId[16]; /* 0x7D4 */ 2220 2221 char reserved6[4]; /* 0x7E4 RESERVED FOR IOV */ 2222 2223 struct { /* 0x7E8 */ 2224 u_int32_t supportPersonalityChange:2; 2225 u_int32_t supportThermalPollInterval:1; 2226 u_int32_t supportDisableImmediateIO:1; 2227 u_int32_t supportT10RebuildAssist:1; 2228 u_int32_t supportMaxExtLDs:1; 2229 u_int32_t supportCrashDump:1; 2230 u_int32_t supportSwZone:1; 2231 u_int32_t supportDebugQueue:1; 2232 u_int32_t supportNVCacheErase:1; 2233 u_int32_t supportForceTo512e:1; 2234 u_int32_t supportHOQRebuild:1; 2235 u_int32_t supportAllowedOpsforDrvRemoval:1; 2236 u_int32_t supportDrvActivityLEDSetting:1; 2237 u_int32_t supportNVDRAM:1; 2238 u_int32_t supportForceFlash:1; 2239 u_int32_t supportDisableSESMonitoring:1; 2240 u_int32_t supportCacheBypassModes:1; 2241 u_int32_t supportSecurityonJBOD:1; 2242 u_int32_t discardCacheDuringLDDelete:1; 2243 u_int32_t supportTTYLogCompression:1; 2244 u_int32_t supportCPLDUpdate:1; 2245 u_int32_t supportDiskCacheSettingForSysPDs:1; 2246 u_int32_t supportExtendedSSCSize:1; 2247 u_int32_t useSeqNumJbodFP:1; 2248 u_int32_t reserved:7; 2249 } adapterOperations3; 2250 2251 u_int8_t pad_cpld[16]; 2252 2253 struct { 2254 u_int16_t ctrlInfoExtSupported:1; 2255 u_int16_t supportIbuttonLess:1; 2256 u_int16_t supportedEncAlgo:1; 2257 u_int16_t supportEncryptedMfc:1; 2258 u_int16_t imageUploadSupported:1; 2259 u_int16_t supportSESCtrlInMultipathCfg:1; 2260 u_int16_t supportPdMapTargetId:1; 2261 u_int16_t FWSwapsBBUVPDInfo:1; 2262 u_int16_t reserved:8; 2263 } adapterOperations4; 2264 2265 u_int8_t pad[0x800 - 0x7FE]; /* 0x7FE */ 2266 } __packed; 2267 2268 /* 2269 * When SCSI mid-layer calls driver's reset routine, driver waits for 2270 * MRSAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note 2271 * that the driver cannot _actually_ abort or reset pending commands. While 2272 * it is waiting for the commands to complete, it prints a diagnostic message 2273 * every MRSAS_RESET_NOTICE_INTERVAL seconds 2274 */ 2275 #define MRSAS_RESET_WAIT_TIME 180 2276 #define MRSAS_INTERNAL_CMD_WAIT_TIME 180 2277 #define MRSAS_RESET_NOTICE_INTERVAL 5 2278 #define MRSAS_IOCTL_CMD 0 2279 #define MRSAS_DEFAULT_CMD_TIMEOUT 90 2280 #define MRSAS_THROTTLE_QUEUE_DEPTH 16 2281 2282 /* 2283 * MSI-x regsiters offset defines 2284 */ 2285 #define MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) 2286 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C) 2287 #define MR_MAX_REPLY_QUEUES_OFFSET (0x0000001F) 2288 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET (0x003FC000) 2289 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT 14 2290 #define MR_MAX_MSIX_REG_ARRAY 16 2291 2292 /* 2293 * SYNC CACHE offset define 2294 */ 2295 #define MR_CAN_HANDLE_SYNC_CACHE_OFFSET 0X01000000 2296 2297 #define MR_ATOMIC_DESCRIPTOR_SUPPORT_OFFSET (1 << 24) 2298 2299 /* 2300 * FW reports the maximum of number of commands that it can accept (maximum 2301 * commands that can be outstanding) at any time. The driver must report a 2302 * lower number to the mid layer because it can issue a few internal commands 2303 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs 2304 * is shown below 2305 */ 2306 #define MRSAS_INT_CMDS 32 2307 #define MRSAS_SKINNY_INT_CMDS 5 2308 #define MRSAS_MAX_MSIX_QUEUES 128 2309 2310 /* 2311 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit SGLs 2312 * based on the size of bus_addr_t 2313 */ 2314 #define IS_DMA64 (sizeof(bus_addr_t) == 8) 2315 2316 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001 2317 #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001 2318 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002 2319 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004 2320 2321 #define MFI_OB_INTR_STATUS_MASK 0x00000002 2322 #define MFI_POLL_TIMEOUT_SECS 60 2323 2324 #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000 2325 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001 2326 #define MFI_GEN2_ENABLE_INTERRUPT_MASK 0x00000001 2327 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000 2328 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001) 2329 #define MFI_1068_PCSR_OFFSET 0x84 2330 #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64 2331 #define MFI_1068_FW_READY 0xDDDD0000 2332 2333 typedef union _MFI_CAPABILITIES { 2334 struct { 2335 u_int32_t support_fp_remote_lun:1; 2336 u_int32_t support_additional_msix:1; 2337 u_int32_t support_fastpath_wb:1; 2338 u_int32_t support_max_255lds:1; 2339 u_int32_t support_ndrive_r1_lb:1; 2340 u_int32_t support_core_affinity:1; 2341 u_int32_t security_protocol_cmds_fw:1; 2342 u_int32_t support_ext_queue_depth:1; 2343 u_int32_t support_ext_io_size:1; 2344 u_int32_t reserved:23; 2345 } mfi_capabilities; 2346 u_int32_t reg; 2347 } MFI_CAPABILITIES; 2348 2349 #pragma pack(1) 2350 struct mrsas_sge32 { 2351 u_int32_t phys_addr; 2352 u_int32_t length; 2353 }; 2354 2355 #pragma pack() 2356 2357 #pragma pack(1) 2358 struct mrsas_sge64 { 2359 u_int64_t phys_addr; 2360 u_int32_t length; 2361 }; 2362 2363 #pragma pack() 2364 2365 #pragma pack() 2366 union mrsas_sgl { 2367 struct mrsas_sge32 sge32[1]; 2368 struct mrsas_sge64 sge64[1]; 2369 }; 2370 2371 #pragma pack() 2372 2373 #pragma pack(1) 2374 struct mrsas_header { 2375 u_int8_t cmd; /* 00e */ 2376 u_int8_t sense_len; /* 01h */ 2377 u_int8_t cmd_status; /* 02h */ 2378 u_int8_t scsi_status; /* 03h */ 2379 2380 u_int8_t target_id; /* 04h */ 2381 u_int8_t lun; /* 05h */ 2382 u_int8_t cdb_len; /* 06h */ 2383 u_int8_t sge_count; /* 07h */ 2384 2385 u_int32_t context; /* 08h */ 2386 u_int32_t pad_0; /* 0Ch */ 2387 2388 u_int16_t flags; /* 10h */ 2389 u_int16_t timeout; /* 12h */ 2390 u_int32_t data_xferlen; /* 14h */ 2391 }; 2392 2393 #pragma pack() 2394 2395 #pragma pack(1) 2396 struct mrsas_init_frame { 2397 u_int8_t cmd; /* 00h */ 2398 u_int8_t reserved_0; /* 01h */ 2399 u_int8_t cmd_status; /* 02h */ 2400 2401 u_int8_t reserved_1; /* 03h */ 2402 MFI_CAPABILITIES driver_operations; /* 04h */ 2403 u_int32_t context; /* 08h */ 2404 u_int32_t pad_0; /* 0Ch */ 2405 2406 u_int16_t flags; /* 10h */ 2407 u_int16_t reserved_3; /* 12h */ 2408 u_int32_t data_xfer_len; /* 14h */ 2409 2410 u_int32_t queue_info_new_phys_addr_lo; /* 18h */ 2411 u_int32_t queue_info_new_phys_addr_hi; /* 1Ch */ 2412 u_int32_t queue_info_old_phys_addr_lo; /* 20h */ 2413 u_int32_t queue_info_old_phys_addr_hi; /* 24h */ 2414 u_int32_t driver_ver_lo; /* 28h */ 2415 u_int32_t driver_ver_hi; /* 2Ch */ 2416 u_int32_t reserved_4[4]; /* 30h */ 2417 }; 2418 2419 #pragma pack() 2420 2421 #pragma pack(1) 2422 struct mrsas_io_frame { 2423 u_int8_t cmd; /* 00h */ 2424 u_int8_t sense_len; /* 01h */ 2425 u_int8_t cmd_status; /* 02h */ 2426 u_int8_t scsi_status; /* 03h */ 2427 2428 u_int8_t target_id; /* 04h */ 2429 u_int8_t access_byte; /* 05h */ 2430 u_int8_t reserved_0; /* 06h */ 2431 u_int8_t sge_count; /* 07h */ 2432 2433 u_int32_t context; /* 08h */ 2434 u_int32_t pad_0; /* 0Ch */ 2435 2436 u_int16_t flags; /* 10h */ 2437 u_int16_t timeout; /* 12h */ 2438 u_int32_t lba_count; /* 14h */ 2439 2440 u_int32_t sense_buf_phys_addr_lo; /* 18h */ 2441 u_int32_t sense_buf_phys_addr_hi; /* 1Ch */ 2442 2443 u_int32_t start_lba_lo; /* 20h */ 2444 u_int32_t start_lba_hi; /* 24h */ 2445 2446 union mrsas_sgl sgl; /* 28h */ 2447 }; 2448 2449 #pragma pack() 2450 2451 #pragma pack(1) 2452 struct mrsas_pthru_frame { 2453 u_int8_t cmd; /* 00h */ 2454 u_int8_t sense_len; /* 01h */ 2455 u_int8_t cmd_status; /* 02h */ 2456 u_int8_t scsi_status; /* 03h */ 2457 2458 u_int8_t target_id; /* 04h */ 2459 u_int8_t lun; /* 05h */ 2460 u_int8_t cdb_len; /* 06h */ 2461 u_int8_t sge_count; /* 07h */ 2462 2463 u_int32_t context; /* 08h */ 2464 u_int32_t pad_0; /* 0Ch */ 2465 2466 u_int16_t flags; /* 10h */ 2467 u_int16_t timeout; /* 12h */ 2468 u_int32_t data_xfer_len; /* 14h */ 2469 2470 u_int32_t sense_buf_phys_addr_lo; /* 18h */ 2471 u_int32_t sense_buf_phys_addr_hi; /* 1Ch */ 2472 2473 u_int8_t cdb[16]; /* 20h */ 2474 union mrsas_sgl sgl; /* 30h */ 2475 }; 2476 2477 #pragma pack() 2478 2479 #pragma pack(1) 2480 struct mrsas_dcmd_frame { 2481 u_int8_t cmd; /* 00h */ 2482 u_int8_t reserved_0; /* 01h */ 2483 u_int8_t cmd_status; /* 02h */ 2484 u_int8_t reserved_1[4]; /* 03h */ 2485 u_int8_t sge_count; /* 07h */ 2486 2487 u_int32_t context; /* 08h */ 2488 u_int32_t pad_0; /* 0Ch */ 2489 2490 u_int16_t flags; /* 10h */ 2491 u_int16_t timeout; /* 12h */ 2492 2493 u_int32_t data_xfer_len; /* 14h */ 2494 u_int32_t opcode; /* 18h */ 2495 2496 union { /* 1Ch */ 2497 u_int8_t b[12]; 2498 u_int16_t s[6]; 2499 u_int32_t w[3]; 2500 } mbox; 2501 2502 union mrsas_sgl sgl; /* 28h */ 2503 }; 2504 2505 #pragma pack() 2506 2507 #pragma pack(1) 2508 struct mrsas_abort_frame { 2509 u_int8_t cmd; /* 00h */ 2510 u_int8_t reserved_0; /* 01h */ 2511 u_int8_t cmd_status; /* 02h */ 2512 2513 u_int8_t reserved_1; /* 03h */ 2514 MFI_CAPABILITIES driver_operations; /* 04h */ 2515 u_int32_t context; /* 08h */ 2516 u_int32_t pad_0; /* 0Ch */ 2517 2518 u_int16_t flags; /* 10h */ 2519 u_int16_t reserved_3; /* 12h */ 2520 u_int32_t reserved_4; /* 14h */ 2521 2522 u_int32_t abort_context; /* 18h */ 2523 u_int32_t pad_1; /* 1Ch */ 2524 2525 u_int32_t abort_mfi_phys_addr_lo; /* 20h */ 2526 u_int32_t abort_mfi_phys_addr_hi; /* 24h */ 2527 2528 u_int32_t reserved_5[6]; /* 28h */ 2529 }; 2530 2531 #pragma pack() 2532 2533 #pragma pack(1) 2534 struct mrsas_smp_frame { 2535 u_int8_t cmd; /* 00h */ 2536 u_int8_t reserved_1; /* 01h */ 2537 u_int8_t cmd_status; /* 02h */ 2538 u_int8_t connection_status; /* 03h */ 2539 2540 u_int8_t reserved_2[3]; /* 04h */ 2541 u_int8_t sge_count; /* 07h */ 2542 2543 u_int32_t context; /* 08h */ 2544 u_int32_t pad_0; /* 0Ch */ 2545 2546 u_int16_t flags; /* 10h */ 2547 u_int16_t timeout; /* 12h */ 2548 2549 u_int32_t data_xfer_len; /* 14h */ 2550 u_int64_t sas_addr; /* 18h */ 2551 2552 union { 2553 struct mrsas_sge32 sge32[2]; /* [0]: resp [1]: req */ 2554 struct mrsas_sge64 sge64[2]; /* [0]: resp [1]: req */ 2555 } sgl; 2556 }; 2557 2558 #pragma pack() 2559 2560 #pragma pack(1) 2561 struct mrsas_stp_frame { 2562 u_int8_t cmd; /* 00h */ 2563 u_int8_t reserved_1; /* 01h */ 2564 u_int8_t cmd_status; /* 02h */ 2565 u_int8_t reserved_2; /* 03h */ 2566 2567 u_int8_t target_id; /* 04h */ 2568 u_int8_t reserved_3[2]; /* 05h */ 2569 u_int8_t sge_count; /* 07h */ 2570 2571 u_int32_t context; /* 08h */ 2572 u_int32_t pad_0; /* 0Ch */ 2573 2574 u_int16_t flags; /* 10h */ 2575 u_int16_t timeout; /* 12h */ 2576 2577 u_int32_t data_xfer_len; /* 14h */ 2578 2579 u_int16_t fis[10]; /* 18h */ 2580 u_int32_t stp_flags; 2581 2582 union { 2583 struct mrsas_sge32 sge32[2]; /* [0]: resp [1]: data */ 2584 struct mrsas_sge64 sge64[2]; /* [0]: resp [1]: data */ 2585 } sgl; 2586 }; 2587 2588 #pragma pack() 2589 2590 union mrsas_frame { 2591 struct mrsas_header hdr; 2592 struct mrsas_init_frame init; 2593 struct mrsas_io_frame io; 2594 struct mrsas_pthru_frame pthru; 2595 struct mrsas_dcmd_frame dcmd; 2596 struct mrsas_abort_frame abort; 2597 struct mrsas_smp_frame smp; 2598 struct mrsas_stp_frame stp; 2599 u_int8_t raw_bytes[64]; 2600 }; 2601 2602 #pragma pack(1) 2603 union mrsas_evt_class_locale { 2604 struct { 2605 u_int16_t locale; 2606 u_int8_t reserved; 2607 int8_t class; 2608 } __packed members; 2609 2610 u_int32_t word; 2611 2612 } __packed; 2613 2614 #pragma pack() 2615 2616 #pragma pack(1) 2617 struct mrsas_evt_log_info { 2618 u_int32_t newest_seq_num; 2619 u_int32_t oldest_seq_num; 2620 u_int32_t clear_seq_num; 2621 u_int32_t shutdown_seq_num; 2622 u_int32_t boot_seq_num; 2623 2624 } __packed; 2625 2626 #pragma pack() 2627 2628 struct mrsas_progress { 2629 u_int16_t progress; 2630 u_int16_t elapsed_seconds; 2631 2632 } __packed; 2633 2634 struct mrsas_evtarg_ld { 2635 u_int16_t target_id; 2636 u_int8_t ld_index; 2637 u_int8_t reserved; 2638 2639 } __packed; 2640 2641 struct mrsas_evtarg_pd { 2642 u_int16_t device_id; 2643 u_int8_t encl_index; 2644 u_int8_t slot_number; 2645 2646 } __packed; 2647 2648 struct mrsas_evt_detail { 2649 u_int32_t seq_num; 2650 u_int32_t time_stamp; 2651 u_int32_t code; 2652 union mrsas_evt_class_locale cl; 2653 u_int8_t arg_type; 2654 u_int8_t reserved1[15]; 2655 2656 union { 2657 struct { 2658 struct mrsas_evtarg_pd pd; 2659 u_int8_t cdb_length; 2660 u_int8_t sense_length; 2661 u_int8_t reserved[2]; 2662 u_int8_t cdb[16]; 2663 u_int8_t sense[64]; 2664 } __packed cdbSense; 2665 2666 struct mrsas_evtarg_ld ld; 2667 2668 struct { 2669 struct mrsas_evtarg_ld ld; 2670 u_int64_t count; 2671 } __packed ld_count; 2672 2673 struct { 2674 u_int64_t lba; 2675 struct mrsas_evtarg_ld ld; 2676 } __packed ld_lba; 2677 2678 struct { 2679 struct mrsas_evtarg_ld ld; 2680 u_int32_t prevOwner; 2681 u_int32_t newOwner; 2682 } __packed ld_owner; 2683 2684 struct { 2685 u_int64_t ld_lba; 2686 u_int64_t pd_lba; 2687 struct mrsas_evtarg_ld ld; 2688 struct mrsas_evtarg_pd pd; 2689 } __packed ld_lba_pd_lba; 2690 2691 struct { 2692 struct mrsas_evtarg_ld ld; 2693 struct mrsas_progress prog; 2694 } __packed ld_prog; 2695 2696 struct { 2697 struct mrsas_evtarg_ld ld; 2698 u_int32_t prev_state; 2699 u_int32_t new_state; 2700 } __packed ld_state; 2701 2702 struct { 2703 u_int64_t strip; 2704 struct mrsas_evtarg_ld ld; 2705 } __packed ld_strip; 2706 2707 struct mrsas_evtarg_pd pd; 2708 2709 struct { 2710 struct mrsas_evtarg_pd pd; 2711 u_int32_t err; 2712 } __packed pd_err; 2713 2714 struct { 2715 u_int64_t lba; 2716 struct mrsas_evtarg_pd pd; 2717 } __packed pd_lba; 2718 2719 struct { 2720 u_int64_t lba; 2721 struct mrsas_evtarg_pd pd; 2722 struct mrsas_evtarg_ld ld; 2723 } __packed pd_lba_ld; 2724 2725 struct { 2726 struct mrsas_evtarg_pd pd; 2727 struct mrsas_progress prog; 2728 } __packed pd_prog; 2729 2730 struct { 2731 struct mrsas_evtarg_pd pd; 2732 u_int32_t prevState; 2733 u_int32_t newState; 2734 } __packed pd_state; 2735 2736 struct { 2737 u_int16_t vendorId; 2738 u_int16_t deviceId; 2739 u_int16_t subVendorId; 2740 u_int16_t subDeviceId; 2741 } __packed pci; 2742 2743 u_int32_t rate; 2744 char str[96]; 2745 2746 struct { 2747 u_int32_t rtc; 2748 u_int32_t elapsedSeconds; 2749 } __packed time; 2750 2751 struct { 2752 u_int32_t ecar; 2753 u_int32_t elog; 2754 char str[64]; 2755 } __packed ecc; 2756 2757 u_int8_t b[96]; 2758 u_int16_t s[48]; 2759 u_int32_t w[24]; 2760 u_int64_t d[12]; 2761 } args; 2762 2763 char description[128]; 2764 2765 } __packed; 2766 2767 struct mrsas_irq_context { 2768 struct mrsas_softc *sc; 2769 uint32_t MSIxIndex; 2770 }; 2771 2772 enum MEGASAS_OCR_REASON { 2773 FW_FAULT_OCR = 0, 2774 MFI_DCMD_TIMEOUT_OCR = 1, 2775 }; 2776 2777 /* Controller management info added to support Linux Emulator */ 2778 #define MAX_MGMT_ADAPTERS 1024 2779 2780 struct mrsas_mgmt_info { 2781 u_int16_t count; 2782 struct mrsas_softc *sc_ptr[MAX_MGMT_ADAPTERS]; 2783 int max_index; 2784 }; 2785 2786 #define PCI_TYPE0_ADDRESSES 6 2787 #define PCI_TYPE1_ADDRESSES 2 2788 #define PCI_TYPE2_ADDRESSES 5 2789 2790 typedef struct _MRSAS_DRV_PCI_COMMON_HEADER { 2791 u_int16_t vendorID; 2792 //(ro) 2793 u_int16_t deviceID; 2794 //(ro) 2795 u_int16_t command; 2796 //Device control 2797 u_int16_t status; 2798 u_int8_t revisionID; 2799 //(ro) 2800 u_int8_t progIf; 2801 //(ro) 2802 u_int8_t subClass; 2803 //(ro) 2804 u_int8_t baseClass; 2805 //(ro) 2806 u_int8_t cacheLineSize; 2807 //(ro +) 2808 u_int8_t latencyTimer; 2809 //(ro +) 2810 u_int8_t headerType; 2811 //(ro) 2812 u_int8_t bist; 2813 //Built in self test 2814 2815 union { 2816 struct _MRSAS_DRV_PCI_HEADER_TYPE_0 { 2817 u_int32_t baseAddresses[PCI_TYPE0_ADDRESSES]; 2818 u_int32_t cis; 2819 u_int16_t subVendorID; 2820 u_int16_t subSystemID; 2821 u_int32_t romBaseAddress; 2822 u_int8_t capabilitiesPtr; 2823 u_int8_t reserved1[3]; 2824 u_int32_t reserved2; 2825 u_int8_t interruptLine; 2826 u_int8_t interruptPin; 2827 //(ro) 2828 u_int8_t minimumGrant; 2829 //(ro) 2830 u_int8_t maximumLatency; 2831 //(ro) 2832 } type0; 2833 2834 /* 2835 * PCI to PCI Bridge 2836 */ 2837 2838 struct _MRSAS_DRV_PCI_HEADER_TYPE_1 { 2839 u_int32_t baseAddresses[PCI_TYPE1_ADDRESSES]; 2840 u_int8_t primaryBus; 2841 u_int8_t secondaryBus; 2842 u_int8_t subordinateBus; 2843 u_int8_t secondaryLatency; 2844 u_int8_t ioBase; 2845 u_int8_t ioLimit; 2846 u_int16_t secondaryStatus; 2847 u_int16_t memoryBase; 2848 u_int16_t memoryLimit; 2849 u_int16_t prefetchBase; 2850 u_int16_t prefetchLimit; 2851 u_int32_t prefetchBaseUpper32; 2852 u_int32_t prefetchLimitUpper32; 2853 u_int16_t ioBaseUpper16; 2854 u_int16_t ioLimitUpper16; 2855 u_int8_t capabilitiesPtr; 2856 u_int8_t reserved1[3]; 2857 u_int32_t romBaseAddress; 2858 u_int8_t interruptLine; 2859 u_int8_t interruptPin; 2860 u_int16_t bridgeControl; 2861 } type1; 2862 2863 /* 2864 * PCI to CARDBUS Bridge 2865 */ 2866 2867 struct _MRSAS_DRV_PCI_HEADER_TYPE_2 { 2868 u_int32_t socketRegistersBaseAddress; 2869 u_int8_t capabilitiesPtr; 2870 u_int8_t reserved; 2871 u_int16_t secondaryStatus; 2872 u_int8_t primaryBus; 2873 u_int8_t secondaryBus; 2874 u_int8_t subordinateBus; 2875 u_int8_t secondaryLatency; 2876 struct { 2877 u_int32_t base; 2878 u_int32_t limit; 2879 } range [PCI_TYPE2_ADDRESSES - 1]; 2880 u_int8_t interruptLine; 2881 u_int8_t interruptPin; 2882 u_int16_t bridgeControl; 2883 } type2; 2884 } u; 2885 2886 } MRSAS_DRV_PCI_COMMON_HEADER, *PMRSAS_DRV_PCI_COMMON_HEADER; 2887 2888 #define MRSAS_DRV_PCI_COMMON_HEADER_SIZE sizeof(MRSAS_DRV_PCI_COMMON_HEADER) //64 bytes 2889 2890 typedef struct _MRSAS_DRV_PCI_LINK_CAPABILITY { 2891 union { 2892 struct { 2893 u_int32_t linkSpeed:4; 2894 u_int32_t linkWidth:6; 2895 u_int32_t aspmSupport:2; 2896 u_int32_t losExitLatency:3; 2897 u_int32_t l1ExitLatency:3; 2898 u_int32_t rsvdp:6; 2899 u_int32_t portNumber:8; 2900 } bits; 2901 2902 u_int32_t asUlong; 2903 } u; 2904 } MRSAS_DRV_PCI_LINK_CAPABILITY, *PMRSAS_DRV_PCI_LINK_CAPABILITY; 2905 2906 #define MRSAS_DRV_PCI_LINK_CAPABILITY_SIZE sizeof(MRSAS_DRV_PCI_LINK_CAPABILITY) 2907 2908 typedef struct _MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY { 2909 union { 2910 struct { 2911 u_int16_t linkSpeed:4; 2912 u_int16_t negotiatedLinkWidth:6; 2913 u_int16_t linkTrainingError:1; 2914 u_int16_t linkTraning:1; 2915 u_int16_t slotClockConfig:1; 2916 u_int16_t rsvdZ:3; 2917 } bits; 2918 2919 u_int16_t asUshort; 2920 } u; 2921 u_int16_t reserved; 2922 } MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY, *PMRSAS_DRV_PCI_LINK_STATUS_CAPABILITY; 2923 2924 #define MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY_SIZE sizeof(MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY) 2925 2926 typedef struct _MRSAS_DRV_PCI_CAPABILITIES { 2927 MRSAS_DRV_PCI_LINK_CAPABILITY linkCapability; 2928 MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY linkStatusCapability; 2929 } MRSAS_DRV_PCI_CAPABILITIES, *PMRSAS_DRV_PCI_CAPABILITIES; 2930 2931 #define MRSAS_DRV_PCI_CAPABILITIES_SIZE sizeof(MRSAS_DRV_PCI_CAPABILITIES) 2932 2933 /* PCI information */ 2934 typedef struct _MRSAS_DRV_PCI_INFORMATION { 2935 u_int32_t busNumber; 2936 u_int8_t deviceNumber; 2937 u_int8_t functionNumber; 2938 u_int8_t interruptVector; 2939 u_int8_t reserved1; 2940 MRSAS_DRV_PCI_COMMON_HEADER pciHeaderInfo; 2941 MRSAS_DRV_PCI_CAPABILITIES capability; 2942 u_int32_t domainID; 2943 u_int8_t reserved2[28]; 2944 } MRSAS_DRV_PCI_INFORMATION, *PMRSAS_DRV_PCI_INFORMATION; 2945 2946 typedef enum _MR_PD_TYPE { 2947 UNKNOWN_DRIVE = 0, 2948 PARALLEL_SCSI = 1, 2949 SAS_PD = 2, 2950 SATA_PD = 3, 2951 FC_PD = 4, 2952 NVME_PD = 5, 2953 } MR_PD_TYPE; 2954 2955 typedef union _MR_PD_REF { 2956 struct { 2957 u_int16_t deviceId; 2958 u_int16_t seqNum; 2959 } mrPdRef; 2960 u_int32_t ref; 2961 } MR_PD_REF; 2962 2963 /* 2964 * define the DDF Type bit structure 2965 */ 2966 union MR_PD_DDF_TYPE { 2967 struct { 2968 union { 2969 struct { 2970 u_int16_t forcedPDGUID:1; 2971 u_int16_t inVD:1; 2972 u_int16_t isGlobalSpare:1; 2973 u_int16_t isSpare:1; 2974 u_int16_t isForeign:1; 2975 u_int16_t reserved:7; 2976 u_int16_t intf:4; 2977 } pdType; 2978 u_int16_t type; 2979 }; 2980 u_int16_t reserved; 2981 } ddf; 2982 struct { 2983 u_int32_t reserved; 2984 } nonDisk; 2985 u_int32_t type; 2986 } __packed; 2987 2988 /* 2989 * defines the progress structure 2990 */ 2991 union MR_PROGRESS { 2992 struct { 2993 u_int16_t progress; 2994 union { 2995 u_int16_t elapsedSecs; 2996 u_int16_t elapsedSecsForLastPercent; 2997 }; 2998 } mrProgress; 2999 u_int32_t w; 3000 } __packed; 3001 3002 /* 3003 * defines the physical drive progress structure 3004 */ 3005 struct MR_PD_PROGRESS { 3006 struct { 3007 u_int32_t rbld:1; 3008 u_int32_t patrol:1; 3009 u_int32_t clear:1; 3010 u_int32_t copyBack:1; 3011 u_int32_t erase:1; 3012 u_int32_t locate:1; 3013 u_int32_t reserved:26; 3014 } active; 3015 union MR_PROGRESS rbld; 3016 union MR_PROGRESS patrol; 3017 union { 3018 union MR_PROGRESS clear; 3019 union MR_PROGRESS erase; 3020 }; 3021 3022 struct { 3023 u_int32_t rbld:1; 3024 u_int32_t patrol:1; 3025 u_int32_t clear:1; 3026 u_int32_t copyBack:1; 3027 u_int32_t erase:1; 3028 u_int32_t reserved:27; 3029 } pause; 3030 3031 union MR_PROGRESS reserved[3]; 3032 } __packed; 3033 3034 struct mrsas_pd_info { 3035 MR_PD_REF ref; 3036 u_int8_t inquiryData[96]; 3037 u_int8_t vpdPage83[64]; 3038 3039 u_int8_t notSupported; 3040 u_int8_t scsiDevType; 3041 3042 union { 3043 u_int8_t connectedPortBitmap; 3044 u_int8_t connectedPortNumbers; 3045 }; 3046 3047 u_int8_t deviceSpeed; 3048 u_int32_t mediaErrCount; 3049 u_int32_t otherErrCount; 3050 u_int32_t predFailCount; 3051 u_int32_t lastPredFailEventSeqNum; 3052 3053 u_int16_t fwState; 3054 u_int8_t disabledForRemoval; 3055 u_int8_t linkSpeed; 3056 union MR_PD_DDF_TYPE state; 3057 3058 struct { 3059 u_int8_t count; 3060 u_int8_t isPathBroken:4; 3061 u_int8_t reserved3:3; 3062 u_int8_t widePortCapable:1; 3063 3064 u_int8_t connectorIndex[2]; 3065 u_int8_t reserved[4]; 3066 u_int64_t sasAddr[2]; 3067 u_int8_t reserved2[16]; 3068 } pathInfo; 3069 3070 u_int64_t rawSize; 3071 u_int64_t nonCoercedSize; 3072 u_int64_t coercedSize; 3073 u_int16_t enclDeviceId; 3074 u_int8_t enclIndex; 3075 3076 union { 3077 u_int8_t slotNumber; 3078 u_int8_t enclConnectorIndex; 3079 }; 3080 3081 struct MR_PD_PROGRESS progInfo; 3082 u_int8_t badBlockTableFull; 3083 u_int8_t unusableInCurrentConfig; 3084 u_int8_t vpdPage83Ext[64]; 3085 u_int8_t powerState; 3086 u_int8_t enclPosition; 3087 u_int32_t allowedOps; 3088 u_int16_t copyBackPartnerId; 3089 u_int16_t enclPartnerDeviceId; 3090 struct { 3091 u_int16_t fdeCapable:1; 3092 u_int16_t fdeEnabled:1; 3093 u_int16_t secured:1; 3094 u_int16_t locked:1; 3095 u_int16_t foreign:1; 3096 u_int16_t needsEKM:1; 3097 u_int16_t reserved:10; 3098 } security; 3099 u_int8_t mediaType; 3100 u_int8_t notCertified; 3101 u_int8_t bridgeVendor[8]; 3102 u_int8_t bridgeProductIdentification[16]; 3103 u_int8_t bridgeProductRevisionLevel[4]; 3104 u_int8_t satBridgeExists; 3105 3106 u_int8_t interfaceType; 3107 u_int8_t temperature; 3108 u_int8_t emulatedBlockSize; 3109 u_int16_t userDataBlockSize; 3110 u_int16_t reserved2; 3111 3112 struct { 3113 u_int32_t piType:3; 3114 u_int32_t piFormatted:1; 3115 u_int32_t piEligible:1; 3116 u_int32_t NCQ:1; 3117 u_int32_t WCE:1; 3118 u_int32_t commissionedSpare:1; 3119 u_int32_t emergencySpare:1; 3120 u_int32_t ineligibleForSSCD:1; 3121 u_int32_t ineligibleForLd:1; 3122 u_int32_t useSSEraseType:1; 3123 u_int32_t wceUnchanged:1; 3124 u_int32_t supportScsiUnmap:1; 3125 u_int32_t reserved:18; 3126 } properties; 3127 3128 u_int64_t shieldDiagCompletionTime; 3129 u_int8_t shieldCounter; 3130 3131 u_int8_t linkSpeedOther; 3132 u_int8_t reserved4[2]; 3133 3134 struct { 3135 u_int32_t bbmErrCountSupported:1; 3136 u_int32_t bbmErrCount:31; 3137 } bbmErr; 3138 3139 u_int8_t reserved1[512-428]; 3140 } __packed; 3141 3142 struct mrsas_target { 3143 u_int16_t target_id; 3144 u_int32_t queue_depth; 3145 u_int8_t interface_type; 3146 u_int32_t max_io_size_kb; 3147 } __packed; 3148 3149 #define MR_NVME_PAGE_SIZE_MASK 0x000000FF 3150 #define MR_DEFAULT_NVME_PAGE_SIZE 4096 3151 #define MR_DEFAULT_NVME_PAGE_SHIFT 12 3152 3153 /******************************************************************* 3154 * per-instance data 3155 ********************************************************************/ 3156 struct mrsas_softc { 3157 device_t mrsas_dev; 3158 struct cdev *mrsas_cdev; 3159 struct intr_config_hook mrsas_ich; 3160 struct cdev *mrsas_linux_emulator_cdev; 3161 uint16_t device_id; 3162 struct resource *reg_res; 3163 int reg_res_id; 3164 bus_space_tag_t bus_tag; 3165 bus_space_handle_t bus_handle; 3166 bus_dma_tag_t mrsas_parent_tag; 3167 bus_dma_tag_t verbuf_tag; 3168 bus_dmamap_t verbuf_dmamap; 3169 void *verbuf_mem; 3170 bus_addr_t verbuf_phys_addr; 3171 bus_dma_tag_t sense_tag; 3172 bus_dmamap_t sense_dmamap; 3173 void *sense_mem; 3174 bus_addr_t sense_phys_addr; 3175 bus_dma_tag_t io_request_tag; 3176 bus_dmamap_t io_request_dmamap; 3177 void *io_request_mem; 3178 bus_addr_t io_request_phys_addr; 3179 bus_dma_tag_t chain_frame_tag; 3180 bus_dmamap_t chain_frame_dmamap; 3181 void *chain_frame_mem; 3182 bus_addr_t chain_frame_phys_addr; 3183 bus_dma_tag_t reply_desc_tag; 3184 bus_dmamap_t reply_desc_dmamap; 3185 void *reply_desc_mem; 3186 bus_addr_t reply_desc_phys_addr; 3187 bus_dma_tag_t ioc_init_tag; 3188 bus_dmamap_t ioc_init_dmamap; 3189 void *ioc_init_mem; 3190 bus_addr_t ioc_init_phys_mem; 3191 bus_dma_tag_t data_tag; 3192 struct cam_sim *sim_0; 3193 struct cam_sim *sim_1; 3194 struct cam_path *path_0; 3195 struct cam_path *path_1; 3196 struct mtx sim_lock; 3197 struct mtx pci_lock; 3198 struct mtx io_lock; 3199 struct mtx ioctl_lock; 3200 struct mtx mpt_cmd_pool_lock; 3201 struct mtx mfi_cmd_pool_lock; 3202 struct mtx raidmap_lock; 3203 struct mtx aen_lock; 3204 struct mtx stream_lock; 3205 struct selinfo mrsas_select; 3206 uint32_t mrsas_aen_triggered; 3207 uint32_t mrsas_poll_waiting; 3208 3209 struct sema ioctl_count_sema; 3210 uint32_t max_fw_cmds; 3211 uint16_t max_scsi_cmds; 3212 uint32_t max_num_sge; 3213 struct resource *mrsas_irq[MAX_MSIX_COUNT]; 3214 void *intr_handle[MAX_MSIX_COUNT]; 3215 int irq_id[MAX_MSIX_COUNT]; 3216 struct mrsas_irq_context irq_context[MAX_MSIX_COUNT]; 3217 int msix_vectors; 3218 int msix_enable; 3219 uint32_t msix_reg_offset[16]; 3220 uint8_t mask_interrupts; 3221 uint16_t max_chain_frame_sz; 3222 struct mrsas_mpt_cmd **mpt_cmd_list; 3223 struct mrsas_mfi_cmd **mfi_cmd_list; 3224 TAILQ_HEAD(, mrsas_mpt_cmd) mrsas_mpt_cmd_list_head; 3225 TAILQ_HEAD(, mrsas_mfi_cmd) mrsas_mfi_cmd_list_head; 3226 bus_addr_t req_frames_desc_phys; 3227 u_int8_t *req_frames_desc; 3228 u_int8_t *req_desc; 3229 bus_addr_t io_request_frames_phys; 3230 u_int8_t *io_request_frames; 3231 bus_addr_t reply_frames_desc_phys; 3232 u_int16_t last_reply_idx[MAX_MSIX_COUNT]; 3233 u_int32_t reply_q_depth; 3234 u_int32_t request_alloc_sz; 3235 u_int32_t reply_alloc_sz; 3236 u_int32_t io_frames_alloc_sz; 3237 u_int32_t chain_frames_alloc_sz; 3238 u_int16_t max_sge_in_main_msg; 3239 u_int16_t max_sge_in_chain; 3240 u_int8_t chain_offset_io_request; 3241 u_int8_t chain_offset_mfi_pthru; 3242 u_int32_t map_sz; 3243 u_int64_t map_id; 3244 u_int64_t pd_seq_map_id; 3245 struct mrsas_mfi_cmd *map_update_cmd; 3246 struct mrsas_mfi_cmd *jbod_seq_cmd; 3247 struct mrsas_mfi_cmd *aen_cmd; 3248 u_int8_t fast_path_io; 3249 void *chan; 3250 void *ocr_chan; 3251 u_int8_t adprecovery; 3252 u_int8_t remove_in_progress; 3253 u_int8_t ocr_thread_active; 3254 u_int8_t do_timedout_reset; 3255 u_int32_t reset_in_progress; 3256 u_int32_t reset_count; 3257 u_int32_t block_sync_cache; 3258 u_int32_t drv_stream_detection; 3259 u_int8_t fw_sync_cache_support; 3260 mrsas_atomic_t target_reset_outstanding; 3261 #define MRSAS_MAX_TM_TARGETS (MRSAS_MAX_PD + MRSAS_MAX_LD_IDS) 3262 struct mrsas_mpt_cmd *target_reset_pool[MRSAS_MAX_TM_TARGETS]; 3263 3264 bus_dma_tag_t jbodmap_tag[2]; 3265 bus_dmamap_t jbodmap_dmamap[2]; 3266 void *jbodmap_mem[2]; 3267 bus_addr_t jbodmap_phys_addr[2]; 3268 3269 bus_dma_tag_t raidmap_tag[2]; 3270 bus_dmamap_t raidmap_dmamap[2]; 3271 void *raidmap_mem[2]; 3272 bus_addr_t raidmap_phys_addr[2]; 3273 bus_dma_tag_t mficmd_frame_tag; 3274 bus_dma_tag_t mficmd_sense_tag; 3275 bus_addr_t evt_detail_phys_addr; 3276 bus_dma_tag_t evt_detail_tag; 3277 bus_dmamap_t evt_detail_dmamap; 3278 struct mrsas_evt_detail *evt_detail_mem; 3279 bus_addr_t pd_info_phys_addr; 3280 bus_dma_tag_t pd_info_tag; 3281 bus_dmamap_t pd_info_dmamap; 3282 struct mrsas_pd_info *pd_info_mem; 3283 struct mrsas_ctrl_info *ctrl_info; 3284 bus_dma_tag_t ctlr_info_tag; 3285 bus_dmamap_t ctlr_info_dmamap; 3286 void *ctlr_info_mem; 3287 bus_addr_t ctlr_info_phys_addr; 3288 u_int32_t max_sectors_per_req; 3289 u_int32_t disableOnlineCtrlReset; 3290 mrsas_atomic_t fw_outstanding; 3291 mrsas_atomic_t prp_count; 3292 mrsas_atomic_t sge_holes; 3293 3294 u_int32_t mrsas_debug; 3295 u_int32_t mrsas_io_timeout; 3296 u_int32_t mrsas_fw_fault_check_delay; 3297 u_int32_t io_cmds_highwater; 3298 u_int8_t UnevenSpanSupport; 3299 struct sysctl_ctx_list sysctl_ctx; 3300 struct sysctl_oid *sysctl_tree; 3301 struct proc *ocr_thread; 3302 u_int32_t last_seq_num; 3303 bus_dma_tag_t el_info_tag; 3304 bus_dmamap_t el_info_dmamap; 3305 void *el_info_mem; 3306 bus_addr_t el_info_phys_addr; 3307 struct mrsas_pd_list pd_list[MRSAS_MAX_PD]; 3308 struct mrsas_pd_list local_pd_list[MRSAS_MAX_PD]; 3309 struct mrsas_target target_list[MRSAS_MAX_TM_TARGETS]; 3310 u_int8_t ld_ids[MRSAS_MAX_LD_IDS]; 3311 struct taskqueue *ev_tq; 3312 struct task ev_task; 3313 u_int32_t CurLdCount; 3314 u_int64_t reset_flags; 3315 int lb_pending_cmds; 3316 LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES_EXT]; 3317 LD_SPAN_INFO log_to_span[MAX_LOGICAL_DRIVES_EXT]; 3318 3319 u_int8_t mrsas_gen3_ctrl; 3320 u_int8_t secure_jbod_support; 3321 u_int8_t use_seqnum_jbod_fp; 3322 /* FW suport for more than 256 PD/JBOD */ 3323 u_int32_t support_morethan256jbod; 3324 u_int8_t max256vdSupport; 3325 u_int16_t fw_supported_vd_count; 3326 u_int16_t fw_supported_pd_count; 3327 3328 u_int16_t drv_supported_vd_count; 3329 u_int16_t drv_supported_pd_count; 3330 3331 u_int32_t max_map_sz; 3332 u_int32_t current_map_sz; 3333 u_int32_t old_map_sz; 3334 u_int32_t new_map_sz; 3335 u_int32_t drv_map_sz; 3336 3337 u_int32_t nvme_page_size; 3338 boolean_t is_ventura; 3339 boolean_t is_aero; 3340 boolean_t msix_combined; 3341 boolean_t atomic_desc_support; 3342 u_int16_t maxRaidMapSize; 3343 3344 /* Non dma-able memory. Driver local copy. */ 3345 MR_DRV_RAID_MAP_ALL *ld_drv_map[2]; 3346 PTR_LD_STREAM_DETECT *streamDetectByLD; 3347 }; 3348 3349 /* Compatibility shims for different OS versions */ 3350 #if __FreeBSD_version >= 800001 3351 #define mrsas_kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \ 3352 kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) 3353 #define mrsas_kproc_exit(arg) kproc_exit(arg) 3354 #else 3355 #define mrsas_kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \ 3356 kthread_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) 3357 #define mrsas_kproc_exit(arg) kthread_exit(arg) 3358 #endif 3359 3360 static __inline void 3361 mrsas_clear_bit(int b, volatile void *p) 3362 { 3363 atomic_clear_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f)); 3364 } 3365 3366 static __inline void 3367 mrsas_set_bit(int b, volatile void *p) 3368 { 3369 atomic_set_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f)); 3370 } 3371 3372 static __inline int 3373 mrsas_test_bit(int b, volatile void *p) 3374 { 3375 return ((volatile int *)p)[b >> 5] & (1 << (b & 0x1f)); 3376 } 3377 3378 #endif /* MRSAS_H */ 3379