1 /* 2 * Copyright (c) 2017 Stormshield. 3 * Copyright (c) 2017 Semihalf. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include "opt_platform.h" 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/endian.h> 35 #include <sys/mbuf.h> 36 #include <sys/lock.h> 37 #include <sys/mutex.h> 38 #include <sys/kernel.h> 39 #include <sys/module.h> 40 #include <sys/socket.h> 41 #include <sys/sysctl.h> 42 #include <sys/smp.h> 43 #include <sys/taskqueue.h> 44 #ifdef MVNETA_KTR 45 #include <sys/ktr.h> 46 #endif 47 48 #include <net/ethernet.h> 49 #include <net/bpf.h> 50 #include <net/if.h> 51 #include <net/if_arp.h> 52 #include <net/if_dl.h> 53 #include <net/if_media.h> 54 #include <net/if_types.h> 55 #include <net/if_vlan_var.h> 56 57 #include <netinet/in_systm.h> 58 #include <netinet/in.h> 59 #include <netinet/ip.h> 60 #include <netinet/tcp_lro.h> 61 62 #include <sys/sockio.h> 63 #include <sys/bus.h> 64 #include <machine/bus.h> 65 #include <sys/rman.h> 66 #include <machine/resource.h> 67 68 #include <dev/extres/clk/clk.h> 69 70 #include <dev/mii/mii.h> 71 #include <dev/mii/miivar.h> 72 73 #include <dev/mdio/mdio.h> 74 75 #include <arm/mv/mvvar.h> 76 77 #if !defined(__aarch64__) 78 #include <arm/mv/mvreg.h> 79 #include <arm/mv/mvwin.h> 80 #endif 81 82 #include "if_mvnetareg.h" 83 #include "if_mvnetavar.h" 84 85 #include "miibus_if.h" 86 #include "mdio_if.h" 87 88 #ifdef MVNETA_DEBUG 89 #define STATIC /* nothing */ 90 #else 91 #define STATIC static 92 #endif 93 94 #define DASSERT(x) KASSERT((x), (#x)) 95 96 #define A3700_TCLK_250MHZ 250000000 97 98 /* Device Register Initialization */ 99 STATIC int mvneta_initreg(struct ifnet *); 100 101 /* Descriptor Ring Control for each of queues */ 102 STATIC int mvneta_ring_alloc_rx_queue(struct mvneta_softc *, int); 103 STATIC int mvneta_ring_alloc_tx_queue(struct mvneta_softc *, int); 104 STATIC void mvneta_ring_dealloc_rx_queue(struct mvneta_softc *, int); 105 STATIC void mvneta_ring_dealloc_tx_queue(struct mvneta_softc *, int); 106 STATIC int mvneta_ring_init_rx_queue(struct mvneta_softc *, int); 107 STATIC int mvneta_ring_init_tx_queue(struct mvneta_softc *, int); 108 STATIC void mvneta_ring_flush_rx_queue(struct mvneta_softc *, int); 109 STATIC void mvneta_ring_flush_tx_queue(struct mvneta_softc *, int); 110 STATIC void mvneta_dmamap_cb(void *, bus_dma_segment_t *, int, int); 111 STATIC int mvneta_dma_create(struct mvneta_softc *); 112 113 /* Rx/Tx Queue Control */ 114 STATIC int mvneta_rx_queue_init(struct ifnet *, int); 115 STATIC int mvneta_tx_queue_init(struct ifnet *, int); 116 STATIC int mvneta_rx_queue_enable(struct ifnet *, int); 117 STATIC int mvneta_tx_queue_enable(struct ifnet *, int); 118 STATIC void mvneta_rx_lockq(struct mvneta_softc *, int); 119 STATIC void mvneta_rx_unlockq(struct mvneta_softc *, int); 120 STATIC void mvneta_tx_lockq(struct mvneta_softc *, int); 121 STATIC void mvneta_tx_unlockq(struct mvneta_softc *, int); 122 123 /* Interrupt Handlers */ 124 STATIC void mvneta_disable_intr(struct mvneta_softc *); 125 STATIC void mvneta_enable_intr(struct mvneta_softc *); 126 STATIC void mvneta_rxtxth_intr(void *); 127 STATIC int mvneta_misc_intr(struct mvneta_softc *); 128 STATIC void mvneta_tick(void *); 129 /* struct ifnet and mii callbacks*/ 130 STATIC int mvneta_xmitfast_locked(struct mvneta_softc *, int, struct mbuf **); 131 STATIC int mvneta_xmit_locked(struct mvneta_softc *, int); 132 #ifdef MVNETA_MULTIQUEUE 133 STATIC int mvneta_transmit(struct ifnet *, struct mbuf *); 134 #else /* !MVNETA_MULTIQUEUE */ 135 STATIC void mvneta_start(struct ifnet *); 136 #endif 137 STATIC void mvneta_qflush(struct ifnet *); 138 STATIC void mvneta_tx_task(void *, int); 139 STATIC int mvneta_ioctl(struct ifnet *, u_long, caddr_t); 140 STATIC void mvneta_init(void *); 141 STATIC void mvneta_init_locked(void *); 142 STATIC void mvneta_stop(struct mvneta_softc *); 143 STATIC void mvneta_stop_locked(struct mvneta_softc *); 144 STATIC int mvneta_mediachange(struct ifnet *); 145 STATIC void mvneta_mediastatus(struct ifnet *, struct ifmediareq *); 146 STATIC void mvneta_portup(struct mvneta_softc *); 147 STATIC void mvneta_portdown(struct mvneta_softc *); 148 149 /* Link State Notify */ 150 STATIC void mvneta_update_autoneg(struct mvneta_softc *, int); 151 STATIC int mvneta_update_media(struct mvneta_softc *, int); 152 STATIC void mvneta_adjust_link(struct mvneta_softc *); 153 STATIC void mvneta_update_eee(struct mvneta_softc *); 154 STATIC void mvneta_update_fc(struct mvneta_softc *); 155 STATIC void mvneta_link_isr(struct mvneta_softc *); 156 STATIC void mvneta_linkupdate(struct mvneta_softc *, boolean_t); 157 STATIC void mvneta_linkup(struct mvneta_softc *); 158 STATIC void mvneta_linkdown(struct mvneta_softc *); 159 STATIC void mvneta_linkreset(struct mvneta_softc *); 160 161 /* Tx Subroutines */ 162 STATIC int mvneta_tx_queue(struct mvneta_softc *, struct mbuf **, int); 163 STATIC void mvneta_tx_set_csumflag(struct ifnet *, 164 struct mvneta_tx_desc *, struct mbuf *); 165 STATIC void mvneta_tx_queue_complete(struct mvneta_softc *, int); 166 STATIC void mvneta_tx_drain(struct mvneta_softc *); 167 168 /* Rx Subroutines */ 169 STATIC int mvneta_rx(struct mvneta_softc *, int, int); 170 STATIC void mvneta_rx_queue(struct mvneta_softc *, int, int); 171 STATIC void mvneta_rx_queue_refill(struct mvneta_softc *, int); 172 STATIC void mvneta_rx_set_csumflag(struct ifnet *, 173 struct mvneta_rx_desc *, struct mbuf *); 174 STATIC void mvneta_rx_buf_free(struct mvneta_softc *, struct mvneta_buf *); 175 176 /* MAC address filter */ 177 STATIC void mvneta_filter_setup(struct mvneta_softc *); 178 179 /* sysctl(9) */ 180 STATIC int sysctl_read_mib(SYSCTL_HANDLER_ARGS); 181 STATIC int sysctl_clear_mib(SYSCTL_HANDLER_ARGS); 182 STATIC int sysctl_set_queue_rxthtime(SYSCTL_HANDLER_ARGS); 183 STATIC void sysctl_mvneta_init(struct mvneta_softc *); 184 185 /* MIB */ 186 STATIC void mvneta_clear_mib(struct mvneta_softc *); 187 STATIC uint64_t mvneta_read_mib(struct mvneta_softc *, int); 188 STATIC void mvneta_update_mib(struct mvneta_softc *); 189 190 /* Switch */ 191 STATIC boolean_t mvneta_has_switch(device_t); 192 193 #define mvneta_sc_lock(sc) mtx_lock(&sc->mtx) 194 #define mvneta_sc_unlock(sc) mtx_unlock(&sc->mtx) 195 196 STATIC struct mtx mii_mutex; 197 STATIC int mii_init = 0; 198 199 /* Device */ 200 STATIC int mvneta_detach(device_t); 201 /* MII */ 202 STATIC int mvneta_miibus_readreg(device_t, int, int); 203 STATIC int mvneta_miibus_writereg(device_t, int, int, int); 204 205 static device_method_t mvneta_methods[] = { 206 /* Device interface */ 207 DEVMETHOD(device_detach, mvneta_detach), 208 /* MII interface */ 209 DEVMETHOD(miibus_readreg, mvneta_miibus_readreg), 210 DEVMETHOD(miibus_writereg, mvneta_miibus_writereg), 211 /* MDIO interface */ 212 DEVMETHOD(mdio_readreg, mvneta_miibus_readreg), 213 DEVMETHOD(mdio_writereg, mvneta_miibus_writereg), 214 215 /* End */ 216 DEVMETHOD_END 217 }; 218 219 DEFINE_CLASS_0(mvneta, mvneta_driver, mvneta_methods, sizeof(struct mvneta_softc)); 220 221 DRIVER_MODULE(miibus, mvneta, miibus_driver, 0, 0); 222 DRIVER_MODULE(mdio, mvneta, mdio_driver, 0, 0); 223 MODULE_DEPEND(mvneta, mdio, 1, 1, 1); 224 MODULE_DEPEND(mvneta, ether, 1, 1, 1); 225 MODULE_DEPEND(mvneta, miibus, 1, 1, 1); 226 MODULE_DEPEND(mvneta, mvxpbm, 1, 1, 1); 227 228 /* 229 * List of MIB register and names 230 */ 231 enum mvneta_mib_idx 232 { 233 MVNETA_MIB_RX_GOOD_OCT_IDX, 234 MVNETA_MIB_RX_BAD_OCT_IDX, 235 MVNETA_MIB_TX_MAC_TRNS_ERR_IDX, 236 MVNETA_MIB_RX_GOOD_FRAME_IDX, 237 MVNETA_MIB_RX_BAD_FRAME_IDX, 238 MVNETA_MIB_RX_BCAST_FRAME_IDX, 239 MVNETA_MIB_RX_MCAST_FRAME_IDX, 240 MVNETA_MIB_RX_FRAME64_OCT_IDX, 241 MVNETA_MIB_RX_FRAME127_OCT_IDX, 242 MVNETA_MIB_RX_FRAME255_OCT_IDX, 243 MVNETA_MIB_RX_FRAME511_OCT_IDX, 244 MVNETA_MIB_RX_FRAME1023_OCT_IDX, 245 MVNETA_MIB_RX_FRAMEMAX_OCT_IDX, 246 MVNETA_MIB_TX_GOOD_OCT_IDX, 247 MVNETA_MIB_TX_GOOD_FRAME_IDX, 248 MVNETA_MIB_TX_EXCES_COL_IDX, 249 MVNETA_MIB_TX_MCAST_FRAME_IDX, 250 MVNETA_MIB_TX_BCAST_FRAME_IDX, 251 MVNETA_MIB_TX_MAC_CTL_ERR_IDX, 252 MVNETA_MIB_FC_SENT_IDX, 253 MVNETA_MIB_FC_GOOD_IDX, 254 MVNETA_MIB_FC_BAD_IDX, 255 MVNETA_MIB_PKT_UNDERSIZE_IDX, 256 MVNETA_MIB_PKT_FRAGMENT_IDX, 257 MVNETA_MIB_PKT_OVERSIZE_IDX, 258 MVNETA_MIB_PKT_JABBER_IDX, 259 MVNETA_MIB_MAC_RX_ERR_IDX, 260 MVNETA_MIB_MAC_CRC_ERR_IDX, 261 MVNETA_MIB_MAC_COL_IDX, 262 MVNETA_MIB_MAC_LATE_COL_IDX, 263 }; 264 265 STATIC struct mvneta_mib_def { 266 uint32_t regnum; 267 int reg64; 268 const char *sysctl_name; 269 const char *desc; 270 } mvneta_mib_list[] = { 271 [MVNETA_MIB_RX_GOOD_OCT_IDX] = {MVNETA_MIB_RX_GOOD_OCT, 1, 272 "rx_good_oct", "Good Octets Rx"}, 273 [MVNETA_MIB_RX_BAD_OCT_IDX] = {MVNETA_MIB_RX_BAD_OCT, 0, 274 "rx_bad_oct", "Bad Octets Rx"}, 275 [MVNETA_MIB_TX_MAC_TRNS_ERR_IDX] = {MVNETA_MIB_TX_MAC_TRNS_ERR, 0, 276 "tx_mac_err", "MAC Transmit Error"}, 277 [MVNETA_MIB_RX_GOOD_FRAME_IDX] = {MVNETA_MIB_RX_GOOD_FRAME, 0, 278 "rx_good_frame", "Good Frames Rx"}, 279 [MVNETA_MIB_RX_BAD_FRAME_IDX] = {MVNETA_MIB_RX_BAD_FRAME, 0, 280 "rx_bad_frame", "Bad Frames Rx"}, 281 [MVNETA_MIB_RX_BCAST_FRAME_IDX] = {MVNETA_MIB_RX_BCAST_FRAME, 0, 282 "rx_bcast_frame", "Broadcast Frames Rx"}, 283 [MVNETA_MIB_RX_MCAST_FRAME_IDX] = {MVNETA_MIB_RX_MCAST_FRAME, 0, 284 "rx_mcast_frame", "Multicast Frames Rx"}, 285 [MVNETA_MIB_RX_FRAME64_OCT_IDX] = {MVNETA_MIB_RX_FRAME64_OCT, 0, 286 "rx_frame_1_64", "Frame Size 1 - 64"}, 287 [MVNETA_MIB_RX_FRAME127_OCT_IDX] = {MVNETA_MIB_RX_FRAME127_OCT, 0, 288 "rx_frame_65_127", "Frame Size 65 - 127"}, 289 [MVNETA_MIB_RX_FRAME255_OCT_IDX] = {MVNETA_MIB_RX_FRAME255_OCT, 0, 290 "rx_frame_128_255", "Frame Size 128 - 255"}, 291 [MVNETA_MIB_RX_FRAME511_OCT_IDX] = {MVNETA_MIB_RX_FRAME511_OCT, 0, 292 "rx_frame_256_511", "Frame Size 256 - 511"}, 293 [MVNETA_MIB_RX_FRAME1023_OCT_IDX] = {MVNETA_MIB_RX_FRAME1023_OCT, 0, 294 "rx_frame_512_1023", "Frame Size 512 - 1023"}, 295 [MVNETA_MIB_RX_FRAMEMAX_OCT_IDX] = {MVNETA_MIB_RX_FRAMEMAX_OCT, 0, 296 "rx_fame_1024_max", "Frame Size 1024 - Max"}, 297 [MVNETA_MIB_TX_GOOD_OCT_IDX] = {MVNETA_MIB_TX_GOOD_OCT, 1, 298 "tx_good_oct", "Good Octets Tx"}, 299 [MVNETA_MIB_TX_GOOD_FRAME_IDX] = {MVNETA_MIB_TX_GOOD_FRAME, 0, 300 "tx_good_frame", "Good Frames Tx"}, 301 [MVNETA_MIB_TX_EXCES_COL_IDX] = {MVNETA_MIB_TX_EXCES_COL, 0, 302 "tx_exces_collision", "Excessive Collision"}, 303 [MVNETA_MIB_TX_MCAST_FRAME_IDX] = {MVNETA_MIB_TX_MCAST_FRAME, 0, 304 "tx_mcast_frame", "Multicast Frames Tx"}, 305 [MVNETA_MIB_TX_BCAST_FRAME_IDX] = {MVNETA_MIB_TX_BCAST_FRAME, 0, 306 "tx_bcast_frame", "Broadcast Frames Tx"}, 307 [MVNETA_MIB_TX_MAC_CTL_ERR_IDX] = {MVNETA_MIB_TX_MAC_CTL_ERR, 0, 308 "tx_mac_ctl_err", "Unknown MAC Control"}, 309 [MVNETA_MIB_FC_SENT_IDX] = {MVNETA_MIB_FC_SENT, 0, 310 "fc_tx", "Flow Control Tx"}, 311 [MVNETA_MIB_FC_GOOD_IDX] = {MVNETA_MIB_FC_GOOD, 0, 312 "fc_rx_good", "Good Flow Control Rx"}, 313 [MVNETA_MIB_FC_BAD_IDX] = {MVNETA_MIB_FC_BAD, 0, 314 "fc_rx_bad", "Bad Flow Control Rx"}, 315 [MVNETA_MIB_PKT_UNDERSIZE_IDX] = {MVNETA_MIB_PKT_UNDERSIZE, 0, 316 "pkt_undersize", "Undersized Packets Rx"}, 317 [MVNETA_MIB_PKT_FRAGMENT_IDX] = {MVNETA_MIB_PKT_FRAGMENT, 0, 318 "pkt_fragment", "Fragmented Packets Rx"}, 319 [MVNETA_MIB_PKT_OVERSIZE_IDX] = {MVNETA_MIB_PKT_OVERSIZE, 0, 320 "pkt_oversize", "Oversized Packets Rx"}, 321 [MVNETA_MIB_PKT_JABBER_IDX] = {MVNETA_MIB_PKT_JABBER, 0, 322 "pkt_jabber", "Jabber Packets Rx"}, 323 [MVNETA_MIB_MAC_RX_ERR_IDX] = {MVNETA_MIB_MAC_RX_ERR, 0, 324 "mac_rx_err", "MAC Rx Errors"}, 325 [MVNETA_MIB_MAC_CRC_ERR_IDX] = {MVNETA_MIB_MAC_CRC_ERR, 0, 326 "mac_crc_err", "MAC CRC Errors"}, 327 [MVNETA_MIB_MAC_COL_IDX] = {MVNETA_MIB_MAC_COL, 0, 328 "mac_collision", "MAC Collision"}, 329 [MVNETA_MIB_MAC_LATE_COL_IDX] = {MVNETA_MIB_MAC_LATE_COL, 0, 330 "mac_late_collision", "MAC Late Collision"}, 331 }; 332 333 static struct resource_spec res_spec[] = { 334 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 335 { SYS_RES_IRQ, 0, RF_ACTIVE }, 336 { -1, 0} 337 }; 338 339 static struct { 340 driver_intr_t *handler; 341 char * description; 342 } mvneta_intrs[] = { 343 { mvneta_rxtxth_intr, "MVNETA aggregated interrupt" }, 344 }; 345 346 static int 347 mvneta_set_mac_address(struct mvneta_softc *sc, uint8_t *addr) 348 { 349 unsigned int mac_h; 350 unsigned int mac_l; 351 352 mac_l = (addr[4] << 8) | (addr[5]); 353 mac_h = (addr[0] << 24) | (addr[1] << 16) | 354 (addr[2] << 8) | (addr[3] << 0); 355 356 MVNETA_WRITE(sc, MVNETA_MACAL, mac_l); 357 MVNETA_WRITE(sc, MVNETA_MACAH, mac_h); 358 return (0); 359 } 360 361 static int 362 mvneta_get_mac_address(struct mvneta_softc *sc, uint8_t *addr) 363 { 364 uint32_t mac_l, mac_h; 365 366 #ifdef FDT 367 if (mvneta_fdt_mac_address(sc, addr) == 0) 368 return (0); 369 #endif 370 /* 371 * Fall back -- use the currently programmed address. 372 */ 373 mac_l = MVNETA_READ(sc, MVNETA_MACAL); 374 mac_h = MVNETA_READ(sc, MVNETA_MACAH); 375 if (mac_l == 0 && mac_h == 0) { 376 /* 377 * Generate pseudo-random MAC. 378 * Set lower part to random number | unit number. 379 */ 380 mac_l = arc4random() & ~0xff; 381 mac_l |= device_get_unit(sc->dev) & 0xff; 382 mac_h = arc4random(); 383 mac_h &= ~(3 << 24); /* Clear multicast and LAA bits */ 384 if (bootverbose) { 385 device_printf(sc->dev, 386 "Could not acquire MAC address. " 387 "Using randomized one.\n"); 388 } 389 } 390 391 addr[0] = (mac_h & 0xff000000) >> 24; 392 addr[1] = (mac_h & 0x00ff0000) >> 16; 393 addr[2] = (mac_h & 0x0000ff00) >> 8; 394 addr[3] = (mac_h & 0x000000ff); 395 addr[4] = (mac_l & 0x0000ff00) >> 8; 396 addr[5] = (mac_l & 0x000000ff); 397 return (0); 398 } 399 400 STATIC boolean_t 401 mvneta_has_switch(device_t self) 402 { 403 #ifdef FDT 404 return (mvneta_has_switch_fdt(self)); 405 #endif 406 407 return (false); 408 } 409 410 STATIC int 411 mvneta_dma_create(struct mvneta_softc *sc) 412 { 413 size_t maxsize, maxsegsz; 414 size_t q; 415 int error; 416 417 /* 418 * Create Tx DMA 419 */ 420 maxsize = maxsegsz = sizeof(struct mvneta_tx_desc) * MVNETA_TX_RING_CNT; 421 422 error = bus_dma_tag_create( 423 bus_get_dma_tag(sc->dev), /* parent */ 424 16, 0, /* alignment, boundary */ 425 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 426 BUS_SPACE_MAXADDR, /* highaddr */ 427 NULL, NULL, /* filtfunc, filtfuncarg */ 428 maxsize, /* maxsize */ 429 1, /* nsegments */ 430 maxsegsz, /* maxsegsz */ 431 0, /* flags */ 432 NULL, NULL, /* lockfunc, lockfuncarg */ 433 &sc->tx_dtag); /* dmat */ 434 if (error != 0) { 435 device_printf(sc->dev, 436 "Failed to create DMA tag for Tx descriptors.\n"); 437 goto fail; 438 } 439 error = bus_dma_tag_create( 440 bus_get_dma_tag(sc->dev), /* parent */ 441 1, 0, /* alignment, boundary */ 442 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 443 BUS_SPACE_MAXADDR, /* highaddr */ 444 NULL, NULL, /* filtfunc, filtfuncarg */ 445 MVNETA_MAX_FRAME, /* maxsize */ 446 MVNETA_TX_SEGLIMIT, /* nsegments */ 447 MVNETA_MAX_FRAME, /* maxsegsz */ 448 BUS_DMA_ALLOCNOW, /* flags */ 449 NULL, NULL, /* lockfunc, lockfuncarg */ 450 &sc->txmbuf_dtag); 451 if (error != 0) { 452 device_printf(sc->dev, 453 "Failed to create DMA tag for Tx mbufs.\n"); 454 goto fail; 455 } 456 457 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 458 error = mvneta_ring_alloc_tx_queue(sc, q); 459 if (error != 0) { 460 device_printf(sc->dev, 461 "Failed to allocate DMA safe memory for TxQ: %zu\n", q); 462 goto fail; 463 } 464 } 465 466 /* 467 * Create Rx DMA. 468 */ 469 /* Create tag for Rx descripors */ 470 error = bus_dma_tag_create( 471 bus_get_dma_tag(sc->dev), /* parent */ 472 32, 0, /* alignment, boundary */ 473 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 474 BUS_SPACE_MAXADDR, /* highaddr */ 475 NULL, NULL, /* filtfunc, filtfuncarg */ 476 sizeof(struct mvneta_rx_desc) * MVNETA_RX_RING_CNT, /* maxsize */ 477 1, /* nsegments */ 478 sizeof(struct mvneta_rx_desc) * MVNETA_RX_RING_CNT, /* maxsegsz */ 479 0, /* flags */ 480 NULL, NULL, /* lockfunc, lockfuncarg */ 481 &sc->rx_dtag); /* dmat */ 482 if (error != 0) { 483 device_printf(sc->dev, 484 "Failed to create DMA tag for Rx descriptors.\n"); 485 goto fail; 486 } 487 488 /* Create tag for Rx buffers */ 489 error = bus_dma_tag_create( 490 bus_get_dma_tag(sc->dev), /* parent */ 491 32, 0, /* alignment, boundary */ 492 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 493 BUS_SPACE_MAXADDR, /* highaddr */ 494 NULL, NULL, /* filtfunc, filtfuncarg */ 495 MVNETA_MAX_FRAME, 1, /* maxsize, nsegments */ 496 MVNETA_MAX_FRAME, /* maxsegsz */ 497 0, /* flags */ 498 NULL, NULL, /* lockfunc, lockfuncarg */ 499 &sc->rxbuf_dtag); /* dmat */ 500 if (error != 0) { 501 device_printf(sc->dev, 502 "Failed to create DMA tag for Rx buffers.\n"); 503 goto fail; 504 } 505 506 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 507 if (mvneta_ring_alloc_rx_queue(sc, q) != 0) { 508 device_printf(sc->dev, 509 "Failed to allocate DMA safe memory for RxQ: %zu\n", q); 510 goto fail; 511 } 512 } 513 514 return (0); 515 fail: 516 mvneta_detach(sc->dev); 517 518 return (error); 519 } 520 521 /* ARGSUSED */ 522 int 523 mvneta_attach(device_t self) 524 { 525 struct mvneta_softc *sc; 526 struct ifnet *ifp; 527 device_t child; 528 int ifm_target; 529 int q, error; 530 #if !defined(__aarch64__) 531 uint32_t reg; 532 #endif 533 clk_t clk; 534 535 sc = device_get_softc(self); 536 sc->dev = self; 537 538 mtx_init(&sc->mtx, "mvneta_sc", NULL, MTX_DEF); 539 540 error = bus_alloc_resources(self, res_spec, sc->res); 541 if (error) { 542 device_printf(self, "could not allocate resources\n"); 543 return (ENXIO); 544 } 545 546 sc->version = MVNETA_READ(sc, MVNETA_PV); 547 device_printf(self, "version is %x\n", sc->version); 548 callout_init(&sc->tick_ch, 0); 549 550 /* 551 * make sure DMA engines are in reset state 552 */ 553 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0x00000001); 554 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0x00000001); 555 556 error = clk_get_by_ofw_index(sc->dev, ofw_bus_get_node(sc->dev), 0, 557 &clk); 558 if (error != 0) { 559 #if defined(__aarch64__) 560 device_printf(sc->dev, 561 "Cannot get clock, using default frequency: %d\n", 562 A3700_TCLK_250MHZ); 563 sc->clk_freq = A3700_TCLK_250MHZ; 564 #else 565 device_printf(sc->dev, 566 "Cannot get clock, using get_tclk()\n"); 567 sc->clk_freq = get_tclk(); 568 #endif 569 } else { 570 error = clk_get_freq(clk, &sc->clk_freq); 571 if (error != 0) { 572 device_printf(sc->dev, 573 "Cannot obtain frequency from parent clock\n"); 574 bus_release_resources(sc->dev, res_spec, sc->res); 575 return (error); 576 } 577 } 578 579 #if !defined(__aarch64__) 580 /* 581 * Disable port snoop for buffers and descriptors 582 * to avoid L2 caching of both without DRAM copy. 583 * Obtain coherency settings from the first MBUS 584 * window attribute. 585 */ 586 if ((MVNETA_READ(sc, MV_WIN_NETA_BASE(0)) & IO_WIN_COH_ATTR_MASK) == 0) { 587 reg = MVNETA_READ(sc, MVNETA_PSNPCFG); 588 reg &= ~MVNETA_PSNPCFG_DESCSNP_MASK; 589 reg &= ~MVNETA_PSNPCFG_BUFSNP_MASK; 590 MVNETA_WRITE(sc, MVNETA_PSNPCFG, reg); 591 } 592 #endif 593 594 error = bus_setup_intr(self, sc->res[1], 595 INTR_TYPE_NET | INTR_MPSAFE, NULL, mvneta_intrs[0].handler, sc, 596 &sc->ih_cookie[0]); 597 if (error) { 598 device_printf(self, "could not setup %s\n", 599 mvneta_intrs[0].description); 600 mvneta_detach(self); 601 return (error); 602 } 603 604 /* 605 * MAC address 606 */ 607 if (mvneta_get_mac_address(sc, sc->enaddr)) { 608 device_printf(self, "no mac address.\n"); 609 return (ENXIO); 610 } 611 mvneta_set_mac_address(sc, sc->enaddr); 612 613 mvneta_disable_intr(sc); 614 615 /* Allocate network interface */ 616 ifp = sc->ifp = if_alloc(IFT_ETHER); 617 if (ifp == NULL) { 618 device_printf(self, "if_alloc() failed\n"); 619 mvneta_detach(self); 620 return (ENOMEM); 621 } 622 if_initname(ifp, device_get_name(self), device_get_unit(self)); 623 624 /* 625 * We can support 802.1Q VLAN-sized frames and jumbo 626 * Ethernet frames. 627 */ 628 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_JUMBO_MTU; 629 630 ifp->if_softc = sc; 631 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 632 #ifdef MVNETA_MULTIQUEUE 633 ifp->if_transmit = mvneta_transmit; 634 ifp->if_qflush = mvneta_qflush; 635 #else /* !MVNETA_MULTIQUEUE */ 636 ifp->if_start = mvneta_start; 637 ifp->if_snd.ifq_drv_maxlen = MVNETA_TX_RING_CNT - 1; 638 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 639 IFQ_SET_READY(&ifp->if_snd); 640 #endif 641 ifp->if_init = mvneta_init; 642 ifp->if_ioctl = mvneta_ioctl; 643 644 /* 645 * We can do IPv4/TCPv4/UDPv4/TCPv6/UDPv6 checksums in hardware. 646 */ 647 ifp->if_capabilities |= IFCAP_HWCSUM; 648 649 /* 650 * As VLAN hardware tagging is not supported 651 * but is necessary to perform VLAN hardware checksums, 652 * it is done in the driver 653 */ 654 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM; 655 656 /* 657 * Currently IPv6 HW checksum is broken, so make sure it is disabled. 658 */ 659 ifp->if_capabilities &= ~IFCAP_HWCSUM_IPV6; 660 ifp->if_capenable = ifp->if_capabilities; 661 662 /* 663 * Disabled option(s): 664 * - Support for Large Receive Offload 665 */ 666 ifp->if_capabilities |= IFCAP_LRO; 667 668 ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP; 669 670 sc->rx_frame_size = MCLBYTES; /* ether_ifattach() always sets normal mtu */ 671 672 /* 673 * Device DMA Buffer allocation. 674 * Handles resource deallocation in case of failure. 675 */ 676 error = mvneta_dma_create(sc); 677 if (error != 0) { 678 mvneta_detach(self); 679 return (error); 680 } 681 682 /* Initialize queues */ 683 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 684 error = mvneta_ring_init_tx_queue(sc, q); 685 if (error != 0) { 686 mvneta_detach(self); 687 return (error); 688 } 689 } 690 691 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 692 error = mvneta_ring_init_rx_queue(sc, q); 693 if (error != 0) { 694 mvneta_detach(self); 695 return (error); 696 } 697 } 698 699 /* 700 * Enable DMA engines and Initialize Device Registers. 701 */ 702 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0x00000000); 703 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0x00000000); 704 MVNETA_WRITE(sc, MVNETA_PACC, MVNETA_PACC_ACCELERATIONMODE_EDM); 705 mvneta_sc_lock(sc); 706 mvneta_filter_setup(sc); 707 mvneta_sc_unlock(sc); 708 mvneta_initreg(ifp); 709 710 /* 711 * Now MAC is working, setup MII. 712 */ 713 if (mii_init == 0) { 714 /* 715 * MII bus is shared by all MACs and all PHYs in SoC. 716 * serializing the bus access should be safe. 717 */ 718 mtx_init(&mii_mutex, "mvneta_mii", NULL, MTX_DEF); 719 mii_init = 1; 720 } 721 722 /* Attach PHY(s) */ 723 if ((sc->phy_addr != MII_PHY_ANY) && (!sc->use_inband_status)) { 724 error = mii_attach(self, &sc->miibus, ifp, mvneta_mediachange, 725 mvneta_mediastatus, BMSR_DEFCAPMASK, sc->phy_addr, 726 MII_OFFSET_ANY, 0); 727 if (error != 0) { 728 device_printf(self, "MII attach failed, error: %d\n", 729 error); 730 ether_ifdetach(sc->ifp); 731 mvneta_detach(self); 732 return (error); 733 } 734 sc->mii = device_get_softc(sc->miibus); 735 sc->phy_attached = 1; 736 737 /* Disable auto-negotiation in MAC - rely on PHY layer */ 738 mvneta_update_autoneg(sc, FALSE); 739 } else if (sc->use_inband_status == TRUE) { 740 /* In-band link status */ 741 ifmedia_init(&sc->mvneta_ifmedia, 0, mvneta_mediachange, 742 mvneta_mediastatus); 743 744 /* Configure media */ 745 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 746 0, NULL); 747 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 748 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 749 0, NULL); 750 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 751 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 752 0, NULL); 753 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 754 ifmedia_set(&sc->mvneta_ifmedia, IFM_ETHER | IFM_AUTO); 755 756 /* Enable auto-negotiation */ 757 mvneta_update_autoneg(sc, TRUE); 758 759 mvneta_sc_lock(sc); 760 if (MVNETA_IS_LINKUP(sc)) 761 mvneta_linkup(sc); 762 else 763 mvneta_linkdown(sc); 764 mvneta_sc_unlock(sc); 765 766 } else { 767 /* Fixed-link, use predefined values */ 768 mvneta_update_autoneg(sc, FALSE); 769 ifmedia_init(&sc->mvneta_ifmedia, 0, mvneta_mediachange, 770 mvneta_mediastatus); 771 772 ifm_target = IFM_ETHER; 773 switch (sc->phy_speed) { 774 case 2500: 775 if (sc->phy_mode != MVNETA_PHY_SGMII && 776 sc->phy_mode != MVNETA_PHY_QSGMII) { 777 device_printf(self, 778 "2.5G speed can work only in (Q)SGMII mode\n"); 779 ether_ifdetach(sc->ifp); 780 mvneta_detach(self); 781 return (ENXIO); 782 } 783 ifm_target |= IFM_2500_T; 784 break; 785 case 1000: 786 ifm_target |= IFM_1000_T; 787 break; 788 case 100: 789 ifm_target |= IFM_100_TX; 790 break; 791 case 10: 792 ifm_target |= IFM_10_T; 793 break; 794 default: 795 ether_ifdetach(sc->ifp); 796 mvneta_detach(self); 797 return (ENXIO); 798 } 799 800 if (sc->phy_fdx) 801 ifm_target |= IFM_FDX; 802 else 803 ifm_target |= IFM_HDX; 804 805 ifmedia_add(&sc->mvneta_ifmedia, ifm_target, 0, NULL); 806 ifmedia_set(&sc->mvneta_ifmedia, ifm_target); 807 if_link_state_change(sc->ifp, LINK_STATE_UP); 808 809 if (mvneta_has_switch(self)) { 810 if (bootverbose) 811 device_printf(self, "This device is attached to a switch\n"); 812 child = device_add_child(sc->dev, "mdio", -1); 813 if (child == NULL) { 814 ether_ifdetach(sc->ifp); 815 mvneta_detach(self); 816 return (ENXIO); 817 } 818 bus_generic_attach(sc->dev); 819 bus_generic_attach(child); 820 } 821 822 /* Configure MAC media */ 823 mvneta_update_media(sc, ifm_target); 824 } 825 826 ether_ifattach(ifp, sc->enaddr); 827 828 callout_reset(&sc->tick_ch, 0, mvneta_tick, sc); 829 830 sysctl_mvneta_init(sc); 831 832 return (0); 833 } 834 835 STATIC int 836 mvneta_detach(device_t dev) 837 { 838 struct mvneta_softc *sc; 839 int q; 840 841 sc = device_get_softc(dev); 842 843 if (device_is_attached(dev)) { 844 mvneta_stop(sc); 845 callout_drain(&sc->tick_ch); 846 ether_ifdetach(sc->ifp); 847 } 848 849 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) 850 mvneta_ring_dealloc_rx_queue(sc, q); 851 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) 852 mvneta_ring_dealloc_tx_queue(sc, q); 853 854 device_delete_children(dev); 855 856 if (sc->ih_cookie[0] != NULL) 857 bus_teardown_intr(dev, sc->res[1], sc->ih_cookie[0]); 858 859 if (sc->tx_dtag != NULL) 860 bus_dma_tag_destroy(sc->tx_dtag); 861 if (sc->rx_dtag != NULL) 862 bus_dma_tag_destroy(sc->rx_dtag); 863 if (sc->txmbuf_dtag != NULL) 864 bus_dma_tag_destroy(sc->txmbuf_dtag); 865 if (sc->rxbuf_dtag != NULL) 866 bus_dma_tag_destroy(sc->rxbuf_dtag); 867 868 bus_release_resources(dev, res_spec, sc->res); 869 870 if (sc->ifp) 871 if_free(sc->ifp); 872 873 if (mtx_initialized(&sc->mtx)) 874 mtx_destroy(&sc->mtx); 875 876 return (0); 877 } 878 879 /* 880 * MII 881 */ 882 STATIC int 883 mvneta_miibus_readreg(device_t dev, int phy, int reg) 884 { 885 struct mvneta_softc *sc; 886 struct ifnet *ifp; 887 uint32_t smi, val; 888 int i; 889 890 sc = device_get_softc(dev); 891 ifp = sc->ifp; 892 893 mtx_lock(&mii_mutex); 894 895 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 896 if ((MVNETA_READ(sc, MVNETA_SMI) & MVNETA_SMI_BUSY) == 0) 897 break; 898 DELAY(1); 899 } 900 if (i == MVNETA_PHY_TIMEOUT) { 901 if_printf(ifp, "SMI busy timeout\n"); 902 mtx_unlock(&mii_mutex); 903 return (-1); 904 } 905 906 smi = MVNETA_SMI_PHYAD(phy) | 907 MVNETA_SMI_REGAD(reg) | MVNETA_SMI_OPCODE_READ; 908 MVNETA_WRITE(sc, MVNETA_SMI, smi); 909 910 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 911 if ((MVNETA_READ(sc, MVNETA_SMI) & MVNETA_SMI_BUSY) == 0) 912 break; 913 DELAY(1); 914 } 915 916 if (i == MVNETA_PHY_TIMEOUT) { 917 if_printf(ifp, "SMI busy timeout\n"); 918 mtx_unlock(&mii_mutex); 919 return (-1); 920 } 921 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 922 smi = MVNETA_READ(sc, MVNETA_SMI); 923 if (smi & MVNETA_SMI_READVALID) 924 break; 925 DELAY(1); 926 } 927 928 if (i == MVNETA_PHY_TIMEOUT) { 929 if_printf(ifp, "SMI busy timeout\n"); 930 mtx_unlock(&mii_mutex); 931 return (-1); 932 } 933 934 mtx_unlock(&mii_mutex); 935 936 #ifdef MVNETA_KTR 937 CTR3(KTR_SPARE2, "%s i=%d, timeout=%d\n", ifp->if_xname, i, 938 MVNETA_PHY_TIMEOUT); 939 #endif 940 941 val = smi & MVNETA_SMI_DATA_MASK; 942 943 #ifdef MVNETA_KTR 944 CTR4(KTR_SPARE2, "%s phy=%d, reg=%#x, val=%#x\n", ifp->if_xname, phy, 945 reg, val); 946 #endif 947 return (val); 948 } 949 950 STATIC int 951 mvneta_miibus_writereg(device_t dev, int phy, int reg, int val) 952 { 953 struct mvneta_softc *sc; 954 struct ifnet *ifp; 955 uint32_t smi; 956 int i; 957 958 sc = device_get_softc(dev); 959 ifp = sc->ifp; 960 #ifdef MVNETA_KTR 961 CTR4(KTR_SPARE2, "%s phy=%d, reg=%#x, val=%#x\n", ifp->if_xname, 962 phy, reg, val); 963 #endif 964 965 mtx_lock(&mii_mutex); 966 967 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 968 if ((MVNETA_READ(sc, MVNETA_SMI) & MVNETA_SMI_BUSY) == 0) 969 break; 970 DELAY(1); 971 } 972 if (i == MVNETA_PHY_TIMEOUT) { 973 if_printf(ifp, "SMI busy timeout\n"); 974 mtx_unlock(&mii_mutex); 975 return (0); 976 } 977 978 smi = MVNETA_SMI_PHYAD(phy) | MVNETA_SMI_REGAD(reg) | 979 MVNETA_SMI_OPCODE_WRITE | (val & MVNETA_SMI_DATA_MASK); 980 MVNETA_WRITE(sc, MVNETA_SMI, smi); 981 982 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 983 if ((MVNETA_READ(sc, MVNETA_SMI) & MVNETA_SMI_BUSY) == 0) 984 break; 985 DELAY(1); 986 } 987 988 mtx_unlock(&mii_mutex); 989 990 if (i == MVNETA_PHY_TIMEOUT) 991 if_printf(ifp, "phy write timed out\n"); 992 993 return (0); 994 } 995 996 STATIC void 997 mvneta_portup(struct mvneta_softc *sc) 998 { 999 int q; 1000 1001 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 1002 mvneta_rx_lockq(sc, q); 1003 mvneta_rx_queue_enable(sc->ifp, q); 1004 mvneta_rx_unlockq(sc, q); 1005 } 1006 1007 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1008 mvneta_tx_lockq(sc, q); 1009 mvneta_tx_queue_enable(sc->ifp, q); 1010 mvneta_tx_unlockq(sc, q); 1011 } 1012 1013 } 1014 1015 STATIC void 1016 mvneta_portdown(struct mvneta_softc *sc) 1017 { 1018 struct mvneta_rx_ring *rx; 1019 struct mvneta_tx_ring *tx; 1020 int q, cnt; 1021 uint32_t reg; 1022 1023 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 1024 rx = MVNETA_RX_RING(sc, q); 1025 mvneta_rx_lockq(sc, q); 1026 rx->queue_status = MVNETA_QUEUE_DISABLED; 1027 mvneta_rx_unlockq(sc, q); 1028 } 1029 1030 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1031 tx = MVNETA_TX_RING(sc, q); 1032 mvneta_tx_lockq(sc, q); 1033 tx->queue_status = MVNETA_QUEUE_DISABLED; 1034 mvneta_tx_unlockq(sc, q); 1035 } 1036 1037 /* Wait for all Rx activity to terminate. */ 1038 reg = MVNETA_READ(sc, MVNETA_RQC) & MVNETA_RQC_EN_MASK; 1039 reg = MVNETA_RQC_DIS(reg); 1040 MVNETA_WRITE(sc, MVNETA_RQC, reg); 1041 cnt = 0; 1042 do { 1043 if (cnt >= RX_DISABLE_TIMEOUT) { 1044 if_printf(sc->ifp, 1045 "timeout for RX stopped. rqc 0x%x\n", reg); 1046 break; 1047 } 1048 cnt++; 1049 reg = MVNETA_READ(sc, MVNETA_RQC); 1050 } while ((reg & MVNETA_RQC_EN_MASK) != 0); 1051 1052 /* Wait for all Tx activity to terminate. */ 1053 reg = MVNETA_READ(sc, MVNETA_PIE); 1054 reg &= ~MVNETA_PIE_TXPKTINTRPTENB_MASK; 1055 MVNETA_WRITE(sc, MVNETA_PIE, reg); 1056 1057 reg = MVNETA_READ(sc, MVNETA_PRXTXTIM); 1058 reg &= ~MVNETA_PRXTXTI_TBTCQ_MASK; 1059 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, reg); 1060 1061 reg = MVNETA_READ(sc, MVNETA_TQC) & MVNETA_TQC_EN_MASK; 1062 reg = MVNETA_TQC_DIS(reg); 1063 MVNETA_WRITE(sc, MVNETA_TQC, reg); 1064 cnt = 0; 1065 do { 1066 if (cnt >= TX_DISABLE_TIMEOUT) { 1067 if_printf(sc->ifp, 1068 "timeout for TX stopped. tqc 0x%x\n", reg); 1069 break; 1070 } 1071 cnt++; 1072 reg = MVNETA_READ(sc, MVNETA_TQC); 1073 } while ((reg & MVNETA_TQC_EN_MASK) != 0); 1074 1075 /* Wait for all Tx FIFO is empty */ 1076 cnt = 0; 1077 do { 1078 if (cnt >= TX_FIFO_EMPTY_TIMEOUT) { 1079 if_printf(sc->ifp, 1080 "timeout for TX FIFO drained. ps0 0x%x\n", reg); 1081 break; 1082 } 1083 cnt++; 1084 reg = MVNETA_READ(sc, MVNETA_PS0); 1085 } while (((reg & MVNETA_PS0_TXFIFOEMP) == 0) && 1086 ((reg & MVNETA_PS0_TXINPROG) != 0)); 1087 } 1088 1089 /* 1090 * Device Register Initialization 1091 * reset device registers to device driver default value. 1092 * the device is not enabled here. 1093 */ 1094 STATIC int 1095 mvneta_initreg(struct ifnet *ifp) 1096 { 1097 struct mvneta_softc *sc; 1098 int q; 1099 uint32_t reg; 1100 1101 sc = ifp->if_softc; 1102 #ifdef MVNETA_KTR 1103 CTR1(KTR_SPARE2, "%s initializing device register", ifp->if_xname); 1104 #endif 1105 1106 /* Disable Legacy WRR, Disable EJP, Release from reset. */ 1107 MVNETA_WRITE(sc, MVNETA_TQC_1, 0); 1108 /* Enable mbus retry. */ 1109 MVNETA_WRITE(sc, MVNETA_MBUS_CONF, MVNETA_MBUS_RETRY_EN); 1110 1111 /* Init TX/RX Queue Registers */ 1112 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 1113 mvneta_rx_lockq(sc, q); 1114 if (mvneta_rx_queue_init(ifp, q) != 0) { 1115 device_printf(sc->dev, 1116 "initialization failed: cannot initialize queue\n"); 1117 mvneta_rx_unlockq(sc, q); 1118 return (ENOBUFS); 1119 } 1120 mvneta_rx_unlockq(sc, q); 1121 } 1122 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1123 mvneta_tx_lockq(sc, q); 1124 if (mvneta_tx_queue_init(ifp, q) != 0) { 1125 device_printf(sc->dev, 1126 "initialization failed: cannot initialize queue\n"); 1127 mvneta_tx_unlockq(sc, q); 1128 return (ENOBUFS); 1129 } 1130 mvneta_tx_unlockq(sc, q); 1131 } 1132 1133 /* 1134 * Ethernet Unit Control - disable automatic PHY management by HW. 1135 * In case the port uses SMI-controlled PHY, poll its status with 1136 * mii_tick() and update MAC settings accordingly. 1137 */ 1138 reg = MVNETA_READ(sc, MVNETA_EUC); 1139 reg &= ~MVNETA_EUC_POLLING; 1140 MVNETA_WRITE(sc, MVNETA_EUC, reg); 1141 1142 /* EEE: Low Power Idle */ 1143 reg = MVNETA_LPIC0_LILIMIT(MVNETA_LPI_LI); 1144 reg |= MVNETA_LPIC0_TSLIMIT(MVNETA_LPI_TS); 1145 MVNETA_WRITE(sc, MVNETA_LPIC0, reg); 1146 1147 reg = MVNETA_LPIC1_TWLIMIT(MVNETA_LPI_TW); 1148 MVNETA_WRITE(sc, MVNETA_LPIC1, reg); 1149 1150 reg = MVNETA_LPIC2_MUSTSET; 1151 MVNETA_WRITE(sc, MVNETA_LPIC2, reg); 1152 1153 /* Port MAC Control set 0 */ 1154 reg = MVNETA_PMACC0_MUSTSET; /* must write 0x1 */ 1155 reg &= ~MVNETA_PMACC0_PORTEN; /* port is still disabled */ 1156 reg |= MVNETA_PMACC0_FRAMESIZELIMIT(ifp->if_mtu + MVNETA_ETHER_SIZE); 1157 MVNETA_WRITE(sc, MVNETA_PMACC0, reg); 1158 1159 /* Port MAC Control set 2 */ 1160 reg = MVNETA_READ(sc, MVNETA_PMACC2); 1161 switch (sc->phy_mode) { 1162 case MVNETA_PHY_QSGMII: 1163 reg |= (MVNETA_PMACC2_PCSEN | MVNETA_PMACC2_RGMIIEN); 1164 MVNETA_WRITE(sc, MVNETA_PSERDESCFG, MVNETA_PSERDESCFG_QSGMII); 1165 break; 1166 case MVNETA_PHY_SGMII: 1167 reg |= (MVNETA_PMACC2_PCSEN | MVNETA_PMACC2_RGMIIEN); 1168 MVNETA_WRITE(sc, MVNETA_PSERDESCFG, MVNETA_PSERDESCFG_SGMII); 1169 break; 1170 case MVNETA_PHY_RGMII: 1171 case MVNETA_PHY_RGMII_ID: 1172 reg |= MVNETA_PMACC2_RGMIIEN; 1173 break; 1174 } 1175 reg |= MVNETA_PMACC2_MUSTSET; 1176 reg &= ~MVNETA_PMACC2_PORTMACRESET; 1177 MVNETA_WRITE(sc, MVNETA_PMACC2, reg); 1178 1179 /* Port Configuration Extended: enable Tx CRC generation */ 1180 reg = MVNETA_READ(sc, MVNETA_PXCX); 1181 reg &= ~MVNETA_PXCX_TXCRCDIS; 1182 MVNETA_WRITE(sc, MVNETA_PXCX, reg); 1183 1184 /* clear MIB counter registers(clear by read) */ 1185 mvneta_sc_lock(sc); 1186 mvneta_clear_mib(sc); 1187 mvneta_sc_unlock(sc); 1188 1189 /* Set SDC register except IPGINT bits */ 1190 reg = MVNETA_SDC_RXBSZ_16_64BITWORDS; 1191 reg |= MVNETA_SDC_TXBSZ_16_64BITWORDS; 1192 reg |= MVNETA_SDC_BLMR; 1193 reg |= MVNETA_SDC_BLMT; 1194 MVNETA_WRITE(sc, MVNETA_SDC, reg); 1195 1196 return (0); 1197 } 1198 1199 STATIC void 1200 mvneta_dmamap_cb(void *arg, bus_dma_segment_t * segs, int nseg, int error) 1201 { 1202 1203 if (error != 0) 1204 return; 1205 *(bus_addr_t *)arg = segs->ds_addr; 1206 } 1207 1208 STATIC int 1209 mvneta_ring_alloc_rx_queue(struct mvneta_softc *sc, int q) 1210 { 1211 struct mvneta_rx_ring *rx; 1212 struct mvneta_buf *rxbuf; 1213 bus_dmamap_t dmap; 1214 int i, error; 1215 1216 if (q >= MVNETA_RX_QNUM_MAX) 1217 return (EINVAL); 1218 1219 rx = MVNETA_RX_RING(sc, q); 1220 mtx_init(&rx->ring_mtx, "mvneta_rx", NULL, MTX_DEF); 1221 /* Allocate DMA memory for Rx descriptors */ 1222 error = bus_dmamem_alloc(sc->rx_dtag, 1223 (void**)&(rx->desc), 1224 BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1225 &rx->desc_map); 1226 if (error != 0 || rx->desc == NULL) 1227 goto fail; 1228 error = bus_dmamap_load(sc->rx_dtag, rx->desc_map, 1229 rx->desc, 1230 sizeof(struct mvneta_rx_desc) * MVNETA_RX_RING_CNT, 1231 mvneta_dmamap_cb, &rx->desc_pa, BUS_DMA_NOWAIT); 1232 if (error != 0) 1233 goto fail; 1234 1235 for (i = 0; i < MVNETA_RX_RING_CNT; i++) { 1236 error = bus_dmamap_create(sc->rxbuf_dtag, 0, &dmap); 1237 if (error != 0) { 1238 device_printf(sc->dev, 1239 "Failed to create DMA map for Rx buffer num: %d\n", i); 1240 goto fail; 1241 } 1242 rxbuf = &rx->rxbuf[i]; 1243 rxbuf->dmap = dmap; 1244 rxbuf->m = NULL; 1245 } 1246 1247 return (0); 1248 fail: 1249 mvneta_rx_lockq(sc, q); 1250 mvneta_ring_flush_rx_queue(sc, q); 1251 mvneta_rx_unlockq(sc, q); 1252 mvneta_ring_dealloc_rx_queue(sc, q); 1253 device_printf(sc->dev, "DMA Ring buffer allocation failure.\n"); 1254 return (error); 1255 } 1256 1257 STATIC int 1258 mvneta_ring_alloc_tx_queue(struct mvneta_softc *sc, int q) 1259 { 1260 struct mvneta_tx_ring *tx; 1261 int error; 1262 1263 if (q >= MVNETA_TX_QNUM_MAX) 1264 return (EINVAL); 1265 tx = MVNETA_TX_RING(sc, q); 1266 mtx_init(&tx->ring_mtx, "mvneta_tx", NULL, MTX_DEF); 1267 error = bus_dmamem_alloc(sc->tx_dtag, 1268 (void**)&(tx->desc), 1269 BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1270 &tx->desc_map); 1271 if (error != 0 || tx->desc == NULL) 1272 goto fail; 1273 error = bus_dmamap_load(sc->tx_dtag, tx->desc_map, 1274 tx->desc, 1275 sizeof(struct mvneta_tx_desc) * MVNETA_TX_RING_CNT, 1276 mvneta_dmamap_cb, &tx->desc_pa, BUS_DMA_NOWAIT); 1277 if (error != 0) 1278 goto fail; 1279 1280 #ifdef MVNETA_MULTIQUEUE 1281 tx->br = buf_ring_alloc(MVNETA_BUFRING_SIZE, M_DEVBUF, M_NOWAIT, 1282 &tx->ring_mtx); 1283 if (tx->br == NULL) { 1284 device_printf(sc->dev, 1285 "Could not setup buffer ring for TxQ(%d)\n", q); 1286 error = ENOMEM; 1287 goto fail; 1288 } 1289 #endif 1290 1291 return (0); 1292 fail: 1293 mvneta_tx_lockq(sc, q); 1294 mvneta_ring_flush_tx_queue(sc, q); 1295 mvneta_tx_unlockq(sc, q); 1296 mvneta_ring_dealloc_tx_queue(sc, q); 1297 device_printf(sc->dev, "DMA Ring buffer allocation failure.\n"); 1298 return (error); 1299 } 1300 1301 STATIC void 1302 mvneta_ring_dealloc_tx_queue(struct mvneta_softc *sc, int q) 1303 { 1304 struct mvneta_tx_ring *tx; 1305 struct mvneta_buf *txbuf; 1306 void *kva; 1307 int error; 1308 int i; 1309 1310 if (q >= MVNETA_TX_QNUM_MAX) 1311 return; 1312 tx = MVNETA_TX_RING(sc, q); 1313 1314 if (tx->taskq != NULL) { 1315 /* Remove task */ 1316 while (taskqueue_cancel(tx->taskq, &tx->task, NULL) != 0) 1317 taskqueue_drain(tx->taskq, &tx->task); 1318 } 1319 #ifdef MVNETA_MULTIQUEUE 1320 if (tx->br != NULL) 1321 drbr_free(tx->br, M_DEVBUF); 1322 #endif 1323 1324 if (sc->txmbuf_dtag != NULL) { 1325 for (i = 0; i < MVNETA_TX_RING_CNT; i++) { 1326 txbuf = &tx->txbuf[i]; 1327 if (txbuf->dmap != NULL) { 1328 error = bus_dmamap_destroy(sc->txmbuf_dtag, 1329 txbuf->dmap); 1330 if (error != 0) { 1331 panic("%s: map busy for Tx descriptor (Q%d, %d)", 1332 __func__, q, i); 1333 } 1334 } 1335 } 1336 } 1337 1338 if (tx->desc_pa != 0) 1339 bus_dmamap_unload(sc->tx_dtag, tx->desc_map); 1340 1341 kva = (void *)tx->desc; 1342 if (kva != NULL) 1343 bus_dmamem_free(sc->tx_dtag, tx->desc, tx->desc_map); 1344 1345 if (mtx_name(&tx->ring_mtx) != NULL) 1346 mtx_destroy(&tx->ring_mtx); 1347 1348 memset(tx, 0, sizeof(*tx)); 1349 } 1350 1351 STATIC void 1352 mvneta_ring_dealloc_rx_queue(struct mvneta_softc *sc, int q) 1353 { 1354 struct mvneta_rx_ring *rx; 1355 struct lro_ctrl *lro; 1356 void *kva; 1357 1358 if (q >= MVNETA_RX_QNUM_MAX) 1359 return; 1360 1361 rx = MVNETA_RX_RING(sc, q); 1362 1363 if (rx->desc_pa != 0) 1364 bus_dmamap_unload(sc->rx_dtag, rx->desc_map); 1365 1366 kva = (void *)rx->desc; 1367 if (kva != NULL) 1368 bus_dmamem_free(sc->rx_dtag, rx->desc, rx->desc_map); 1369 1370 lro = &rx->lro; 1371 tcp_lro_free(lro); 1372 1373 if (mtx_name(&rx->ring_mtx) != NULL) 1374 mtx_destroy(&rx->ring_mtx); 1375 1376 memset(rx, 0, sizeof(*rx)); 1377 } 1378 1379 STATIC int 1380 mvneta_ring_init_rx_queue(struct mvneta_softc *sc, int q) 1381 { 1382 struct mvneta_rx_ring *rx; 1383 struct lro_ctrl *lro; 1384 int error; 1385 1386 if (q >= MVNETA_RX_QNUM_MAX) 1387 return (0); 1388 1389 rx = MVNETA_RX_RING(sc, q); 1390 rx->dma = rx->cpu = 0; 1391 rx->queue_th_received = MVNETA_RXTH_COUNT; 1392 rx->queue_th_time = (sc->clk_freq / 1000) / 10; /* 0.1 [ms] */ 1393 1394 /* Initialize LRO */ 1395 rx->lro_enabled = FALSE; 1396 if ((sc->ifp->if_capenable & IFCAP_LRO) != 0) { 1397 lro = &rx->lro; 1398 error = tcp_lro_init(lro); 1399 if (error != 0) 1400 device_printf(sc->dev, "LRO Initialization failed!\n"); 1401 else { 1402 rx->lro_enabled = TRUE; 1403 lro->ifp = sc->ifp; 1404 } 1405 } 1406 1407 return (0); 1408 } 1409 1410 STATIC int 1411 mvneta_ring_init_tx_queue(struct mvneta_softc *sc, int q) 1412 { 1413 struct mvneta_tx_ring *tx; 1414 struct mvneta_buf *txbuf; 1415 int i, error; 1416 1417 if (q >= MVNETA_TX_QNUM_MAX) 1418 return (0); 1419 1420 tx = MVNETA_TX_RING(sc, q); 1421 1422 /* Tx handle */ 1423 for (i = 0; i < MVNETA_TX_RING_CNT; i++) { 1424 txbuf = &tx->txbuf[i]; 1425 txbuf->m = NULL; 1426 /* Tx handle needs DMA map for busdma_load_mbuf() */ 1427 error = bus_dmamap_create(sc->txmbuf_dtag, 0, 1428 &txbuf->dmap); 1429 if (error != 0) { 1430 device_printf(sc->dev, 1431 "can't create dma map (tx ring %d)\n", i); 1432 return (error); 1433 } 1434 } 1435 tx->dma = tx->cpu = 0; 1436 tx->used = 0; 1437 tx->drv_error = 0; 1438 tx->queue_status = MVNETA_QUEUE_DISABLED; 1439 tx->queue_hung = FALSE; 1440 1441 tx->ifp = sc->ifp; 1442 tx->qidx = q; 1443 TASK_INIT(&tx->task, 0, mvneta_tx_task, tx); 1444 tx->taskq = taskqueue_create_fast("mvneta_tx_taskq", M_WAITOK, 1445 taskqueue_thread_enqueue, &tx->taskq); 1446 taskqueue_start_threads(&tx->taskq, 1, PI_NET, "%s: tx_taskq(%d)", 1447 device_get_nameunit(sc->dev), q); 1448 1449 return (0); 1450 } 1451 1452 STATIC void 1453 mvneta_ring_flush_tx_queue(struct mvneta_softc *sc, int q) 1454 { 1455 struct mvneta_tx_ring *tx; 1456 struct mvneta_buf *txbuf; 1457 int i; 1458 1459 tx = MVNETA_TX_RING(sc, q); 1460 KASSERT_TX_MTX(sc, q); 1461 1462 /* Tx handle */ 1463 for (i = 0; i < MVNETA_TX_RING_CNT; i++) { 1464 txbuf = &tx->txbuf[i]; 1465 bus_dmamap_unload(sc->txmbuf_dtag, txbuf->dmap); 1466 if (txbuf->m != NULL) { 1467 m_freem(txbuf->m); 1468 txbuf->m = NULL; 1469 } 1470 } 1471 tx->dma = tx->cpu = 0; 1472 tx->used = 0; 1473 } 1474 1475 STATIC void 1476 mvneta_ring_flush_rx_queue(struct mvneta_softc *sc, int q) 1477 { 1478 struct mvneta_rx_ring *rx; 1479 struct mvneta_buf *rxbuf; 1480 int i; 1481 1482 rx = MVNETA_RX_RING(sc, q); 1483 KASSERT_RX_MTX(sc, q); 1484 1485 /* Rx handle */ 1486 for (i = 0; i < MVNETA_RX_RING_CNT; i++) { 1487 rxbuf = &rx->rxbuf[i]; 1488 mvneta_rx_buf_free(sc, rxbuf); 1489 } 1490 rx->dma = rx->cpu = 0; 1491 } 1492 1493 /* 1494 * Rx/Tx Queue Control 1495 */ 1496 STATIC int 1497 mvneta_rx_queue_init(struct ifnet *ifp, int q) 1498 { 1499 struct mvneta_softc *sc; 1500 struct mvneta_rx_ring *rx; 1501 uint32_t reg; 1502 1503 sc = ifp->if_softc; 1504 KASSERT_RX_MTX(sc, q); 1505 rx = MVNETA_RX_RING(sc, q); 1506 DASSERT(rx->desc_pa != 0); 1507 1508 /* descriptor address */ 1509 MVNETA_WRITE(sc, MVNETA_PRXDQA(q), rx->desc_pa); 1510 1511 /* Rx buffer size and descriptor ring size */ 1512 reg = MVNETA_PRXDQS_BUFFERSIZE(sc->rx_frame_size >> 3); 1513 reg |= MVNETA_PRXDQS_DESCRIPTORSQUEUESIZE(MVNETA_RX_RING_CNT); 1514 MVNETA_WRITE(sc, MVNETA_PRXDQS(q), reg); 1515 #ifdef MVNETA_KTR 1516 CTR3(KTR_SPARE2, "%s PRXDQS(%d): %#x", ifp->if_xname, q, 1517 MVNETA_READ(sc, MVNETA_PRXDQS(q))); 1518 #endif 1519 /* Rx packet offset address */ 1520 reg = MVNETA_PRXC_PACKETOFFSET(MVNETA_PACKET_OFFSET >> 3); 1521 MVNETA_WRITE(sc, MVNETA_PRXC(q), reg); 1522 #ifdef MVNETA_KTR 1523 CTR3(KTR_SPARE2, "%s PRXC(%d): %#x", ifp->if_xname, q, 1524 MVNETA_READ(sc, MVNETA_PRXC(q))); 1525 #endif 1526 1527 /* if DMA is not working, register is not updated */ 1528 DASSERT(MVNETA_READ(sc, MVNETA_PRXDQA(q)) == rx->desc_pa); 1529 return (0); 1530 } 1531 1532 STATIC int 1533 mvneta_tx_queue_init(struct ifnet *ifp, int q) 1534 { 1535 struct mvneta_softc *sc; 1536 struct mvneta_tx_ring *tx; 1537 uint32_t reg; 1538 1539 sc = ifp->if_softc; 1540 KASSERT_TX_MTX(sc, q); 1541 tx = MVNETA_TX_RING(sc, q); 1542 DASSERT(tx->desc_pa != 0); 1543 1544 /* descriptor address */ 1545 MVNETA_WRITE(sc, MVNETA_PTXDQA(q), tx->desc_pa); 1546 1547 /* descriptor ring size */ 1548 reg = MVNETA_PTXDQS_DQS(MVNETA_TX_RING_CNT); 1549 MVNETA_WRITE(sc, MVNETA_PTXDQS(q), reg); 1550 1551 /* if DMA is not working, register is not updated */ 1552 DASSERT(MVNETA_READ(sc, MVNETA_PTXDQA(q)) == tx->desc_pa); 1553 return (0); 1554 } 1555 1556 STATIC int 1557 mvneta_rx_queue_enable(struct ifnet *ifp, int q) 1558 { 1559 struct mvneta_softc *sc; 1560 struct mvneta_rx_ring *rx; 1561 uint32_t reg; 1562 1563 sc = ifp->if_softc; 1564 rx = MVNETA_RX_RING(sc, q); 1565 KASSERT_RX_MTX(sc, q); 1566 1567 /* Set Rx interrupt threshold */ 1568 reg = MVNETA_PRXDQTH_ODT(rx->queue_th_received); 1569 MVNETA_WRITE(sc, MVNETA_PRXDQTH(q), reg); 1570 1571 reg = MVNETA_PRXITTH_RITT(rx->queue_th_time); 1572 MVNETA_WRITE(sc, MVNETA_PRXITTH(q), reg); 1573 1574 /* Unmask RXTX_TH Intr. */ 1575 reg = MVNETA_READ(sc, MVNETA_PRXTXTIM); 1576 reg |= MVNETA_PRXTXTI_RBICTAPQ(q); /* Rx Buffer Interrupt Coalese */ 1577 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, reg); 1578 1579 /* Enable Rx queue */ 1580 reg = MVNETA_READ(sc, MVNETA_RQC) & MVNETA_RQC_EN_MASK; 1581 reg |= MVNETA_RQC_ENQ(q); 1582 MVNETA_WRITE(sc, MVNETA_RQC, reg); 1583 1584 rx->queue_status = MVNETA_QUEUE_WORKING; 1585 return (0); 1586 } 1587 1588 STATIC int 1589 mvneta_tx_queue_enable(struct ifnet *ifp, int q) 1590 { 1591 struct mvneta_softc *sc; 1592 struct mvneta_tx_ring *tx; 1593 1594 sc = ifp->if_softc; 1595 tx = MVNETA_TX_RING(sc, q); 1596 KASSERT_TX_MTX(sc, q); 1597 1598 /* Enable Tx queue */ 1599 MVNETA_WRITE(sc, MVNETA_TQC, MVNETA_TQC_ENQ(q)); 1600 1601 tx->queue_status = MVNETA_QUEUE_IDLE; 1602 tx->queue_hung = FALSE; 1603 return (0); 1604 } 1605 1606 STATIC __inline void 1607 mvneta_rx_lockq(struct mvneta_softc *sc, int q) 1608 { 1609 1610 DASSERT(q >= 0); 1611 DASSERT(q < MVNETA_RX_QNUM_MAX); 1612 mtx_lock(&sc->rx_ring[q].ring_mtx); 1613 } 1614 1615 STATIC __inline void 1616 mvneta_rx_unlockq(struct mvneta_softc *sc, int q) 1617 { 1618 1619 DASSERT(q >= 0); 1620 DASSERT(q < MVNETA_RX_QNUM_MAX); 1621 mtx_unlock(&sc->rx_ring[q].ring_mtx); 1622 } 1623 1624 STATIC __inline int __unused 1625 mvneta_tx_trylockq(struct mvneta_softc *sc, int q) 1626 { 1627 1628 DASSERT(q >= 0); 1629 DASSERT(q < MVNETA_TX_QNUM_MAX); 1630 return (mtx_trylock(&sc->tx_ring[q].ring_mtx)); 1631 } 1632 1633 STATIC __inline void 1634 mvneta_tx_lockq(struct mvneta_softc *sc, int q) 1635 { 1636 1637 DASSERT(q >= 0); 1638 DASSERT(q < MVNETA_TX_QNUM_MAX); 1639 mtx_lock(&sc->tx_ring[q].ring_mtx); 1640 } 1641 1642 STATIC __inline void 1643 mvneta_tx_unlockq(struct mvneta_softc *sc, int q) 1644 { 1645 1646 DASSERT(q >= 0); 1647 DASSERT(q < MVNETA_TX_QNUM_MAX); 1648 mtx_unlock(&sc->tx_ring[q].ring_mtx); 1649 } 1650 1651 /* 1652 * Interrupt Handlers 1653 */ 1654 STATIC void 1655 mvneta_disable_intr(struct mvneta_softc *sc) 1656 { 1657 1658 MVNETA_WRITE(sc, MVNETA_EUIM, 0); 1659 MVNETA_WRITE(sc, MVNETA_EUIC, 0); 1660 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, 0); 1661 MVNETA_WRITE(sc, MVNETA_PRXTXTIC, 0); 1662 MVNETA_WRITE(sc, MVNETA_PRXTXIM, 0); 1663 MVNETA_WRITE(sc, MVNETA_PRXTXIC, 0); 1664 MVNETA_WRITE(sc, MVNETA_PMIM, 0); 1665 MVNETA_WRITE(sc, MVNETA_PMIC, 0); 1666 MVNETA_WRITE(sc, MVNETA_PIE, 0); 1667 } 1668 1669 STATIC void 1670 mvneta_enable_intr(struct mvneta_softc *sc) 1671 { 1672 uint32_t reg; 1673 1674 /* Enable Summary Bit to check all interrupt cause. */ 1675 reg = MVNETA_READ(sc, MVNETA_PRXTXTIM); 1676 reg |= MVNETA_PRXTXTI_PMISCICSUMMARY; 1677 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, reg); 1678 1679 if (!sc->phy_attached || sc->use_inband_status) { 1680 /* Enable Port MISC Intr. (via RXTX_TH_Summary bit) */ 1681 MVNETA_WRITE(sc, MVNETA_PMIM, MVNETA_PMI_PHYSTATUSCHNG | 1682 MVNETA_PMI_LINKCHANGE | MVNETA_PMI_PSCSYNCCHANGE); 1683 } 1684 1685 /* Enable All Queue Interrupt */ 1686 reg = MVNETA_READ(sc, MVNETA_PIE); 1687 reg |= MVNETA_PIE_RXPKTINTRPTENB_MASK; 1688 reg |= MVNETA_PIE_TXPKTINTRPTENB_MASK; 1689 MVNETA_WRITE(sc, MVNETA_PIE, reg); 1690 } 1691 1692 STATIC void 1693 mvneta_rxtxth_intr(void *arg) 1694 { 1695 struct mvneta_softc *sc; 1696 struct ifnet *ifp; 1697 uint32_t ic, queues; 1698 1699 sc = arg; 1700 ifp = sc->ifp; 1701 #ifdef MVNETA_KTR 1702 CTR1(KTR_SPARE2, "%s got RXTX_TH_Intr", ifp->if_xname); 1703 #endif 1704 ic = MVNETA_READ(sc, MVNETA_PRXTXTIC); 1705 if (ic == 0) 1706 return; 1707 MVNETA_WRITE(sc, MVNETA_PRXTXTIC, ~ic); 1708 1709 /* Ack maintenance interrupt first */ 1710 if (__predict_false((ic & MVNETA_PRXTXTI_PMISCICSUMMARY) && 1711 (!sc->phy_attached || sc->use_inband_status))) { 1712 mvneta_sc_lock(sc); 1713 mvneta_misc_intr(sc); 1714 mvneta_sc_unlock(sc); 1715 } 1716 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 1717 return; 1718 /* RxTxTH interrupt */ 1719 queues = MVNETA_PRXTXTI_GET_RBICTAPQ(ic); 1720 if (__predict_true(queues)) { 1721 #ifdef MVNETA_KTR 1722 CTR1(KTR_SPARE2, "%s got PRXTXTIC: +RXEOF", ifp->if_xname); 1723 #endif 1724 /* At the moment the driver support only one RX queue. */ 1725 DASSERT(MVNETA_IS_QUEUE_SET(queues, 0)); 1726 mvneta_rx(sc, 0, 0); 1727 } 1728 } 1729 1730 STATIC int 1731 mvneta_misc_intr(struct mvneta_softc *sc) 1732 { 1733 uint32_t ic; 1734 int claimed = 0; 1735 1736 #ifdef MVNETA_KTR 1737 CTR1(KTR_SPARE2, "%s got MISC_INTR", sc->ifp->if_xname); 1738 #endif 1739 KASSERT_SC_MTX(sc); 1740 1741 for (;;) { 1742 ic = MVNETA_READ(sc, MVNETA_PMIC); 1743 ic &= MVNETA_READ(sc, MVNETA_PMIM); 1744 if (ic == 0) 1745 break; 1746 MVNETA_WRITE(sc, MVNETA_PMIC, ~ic); 1747 claimed = 1; 1748 1749 if (ic & (MVNETA_PMI_PHYSTATUSCHNG | 1750 MVNETA_PMI_LINKCHANGE | MVNETA_PMI_PSCSYNCCHANGE)) 1751 mvneta_link_isr(sc); 1752 } 1753 return (claimed); 1754 } 1755 1756 STATIC void 1757 mvneta_tick(void *arg) 1758 { 1759 struct mvneta_softc *sc; 1760 struct mvneta_tx_ring *tx; 1761 struct mvneta_rx_ring *rx; 1762 int q; 1763 uint32_t fc_prev, fc_curr; 1764 1765 sc = arg; 1766 1767 /* 1768 * This is done before mib update to get the right stats 1769 * for this tick. 1770 */ 1771 mvneta_tx_drain(sc); 1772 1773 /* Extract previous flow-control frame received counter. */ 1774 fc_prev = sc->sysctl_mib[MVNETA_MIB_FC_GOOD_IDX].counter; 1775 /* Read mib registers (clear by read). */ 1776 mvneta_update_mib(sc); 1777 /* Extract current flow-control frame received counter. */ 1778 fc_curr = sc->sysctl_mib[MVNETA_MIB_FC_GOOD_IDX].counter; 1779 1780 1781 if (sc->phy_attached && sc->ifp->if_flags & IFF_UP) { 1782 mvneta_sc_lock(sc); 1783 mii_tick(sc->mii); 1784 1785 /* Adjust MAC settings */ 1786 mvneta_adjust_link(sc); 1787 mvneta_sc_unlock(sc); 1788 } 1789 1790 /* 1791 * We were unable to refill the rx queue and left the rx func, leaving 1792 * the ring without mbuf and no way to call the refill func. 1793 */ 1794 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 1795 rx = MVNETA_RX_RING(sc, q); 1796 if (rx->needs_refill == TRUE) { 1797 mvneta_rx_lockq(sc, q); 1798 mvneta_rx_queue_refill(sc, q); 1799 mvneta_rx_unlockq(sc, q); 1800 } 1801 } 1802 1803 /* 1804 * Watchdog: 1805 * - check if queue is mark as hung. 1806 * - ignore hung status if we received some pause frame 1807 * as hardware may have paused packet transmit. 1808 */ 1809 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1810 /* 1811 * We should take queue lock, but as we only read 1812 * queue status we can do it without lock, we may 1813 * only missdetect queue status for one tick. 1814 */ 1815 tx = MVNETA_TX_RING(sc, q); 1816 1817 if (tx->queue_hung && (fc_curr - fc_prev) == 0) 1818 goto timeout; 1819 } 1820 1821 callout_schedule(&sc->tick_ch, hz); 1822 return; 1823 1824 timeout: 1825 if_printf(sc->ifp, "watchdog timeout\n"); 1826 1827 mvneta_sc_lock(sc); 1828 sc->counter_watchdog++; 1829 sc->counter_watchdog_mib++; 1830 /* Trigger reinitialize sequence. */ 1831 mvneta_stop_locked(sc); 1832 mvneta_init_locked(sc); 1833 mvneta_sc_unlock(sc); 1834 } 1835 1836 STATIC void 1837 mvneta_qflush(struct ifnet *ifp) 1838 { 1839 #ifdef MVNETA_MULTIQUEUE 1840 struct mvneta_softc *sc; 1841 struct mvneta_tx_ring *tx; 1842 struct mbuf *m; 1843 size_t q; 1844 1845 sc = ifp->if_softc; 1846 1847 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1848 tx = MVNETA_TX_RING(sc, q); 1849 mvneta_tx_lockq(sc, q); 1850 while ((m = buf_ring_dequeue_sc(tx->br)) != NULL) 1851 m_freem(m); 1852 mvneta_tx_unlockq(sc, q); 1853 } 1854 #endif 1855 if_qflush(ifp); 1856 } 1857 1858 STATIC void 1859 mvneta_tx_task(void *arg, int pending) 1860 { 1861 struct mvneta_softc *sc; 1862 struct mvneta_tx_ring *tx; 1863 struct ifnet *ifp; 1864 int error; 1865 1866 tx = arg; 1867 ifp = tx->ifp; 1868 sc = ifp->if_softc; 1869 1870 mvneta_tx_lockq(sc, tx->qidx); 1871 error = mvneta_xmit_locked(sc, tx->qidx); 1872 mvneta_tx_unlockq(sc, tx->qidx); 1873 1874 /* Try again */ 1875 if (__predict_false(error != 0 && error != ENETDOWN)) { 1876 pause("mvneta_tx_task_sleep", 1); 1877 taskqueue_enqueue(tx->taskq, &tx->task); 1878 } 1879 } 1880 1881 STATIC int 1882 mvneta_xmitfast_locked(struct mvneta_softc *sc, int q, struct mbuf **m) 1883 { 1884 struct mvneta_tx_ring *tx; 1885 struct ifnet *ifp; 1886 int error; 1887 1888 KASSERT_TX_MTX(sc, q); 1889 tx = MVNETA_TX_RING(sc, q); 1890 error = 0; 1891 1892 ifp = sc->ifp; 1893 1894 /* Dont enqueue packet if the queue is disabled. */ 1895 if (__predict_false(tx->queue_status == MVNETA_QUEUE_DISABLED)) { 1896 m_freem(*m); 1897 *m = NULL; 1898 return (ENETDOWN); 1899 } 1900 1901 /* Reclaim mbuf if above threshold. */ 1902 if (__predict_true(tx->used > MVNETA_TX_RECLAIM_COUNT)) 1903 mvneta_tx_queue_complete(sc, q); 1904 1905 /* Do not call transmit path if queue is already too full. */ 1906 if (__predict_false(tx->used > 1907 MVNETA_TX_RING_CNT - MVNETA_TX_SEGLIMIT)) 1908 return (ENOBUFS); 1909 1910 error = mvneta_tx_queue(sc, m, q); 1911 if (__predict_false(error != 0)) 1912 return (error); 1913 1914 /* Send a copy of the frame to the BPF listener */ 1915 ETHER_BPF_MTAP(ifp, *m); 1916 1917 /* Set watchdog on */ 1918 tx->watchdog_time = ticks; 1919 tx->queue_status = MVNETA_QUEUE_WORKING; 1920 1921 return (error); 1922 } 1923 1924 #ifdef MVNETA_MULTIQUEUE 1925 STATIC int 1926 mvneta_transmit(struct ifnet *ifp, struct mbuf *m) 1927 { 1928 struct mvneta_softc *sc; 1929 struct mvneta_tx_ring *tx; 1930 int error; 1931 int q; 1932 1933 sc = ifp->if_softc; 1934 1935 /* Use default queue if there is no flow id as thread can migrate. */ 1936 if (__predict_true(M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)) 1937 q = m->m_pkthdr.flowid % MVNETA_TX_QNUM_MAX; 1938 else 1939 q = 0; 1940 1941 tx = MVNETA_TX_RING(sc, q); 1942 1943 /* If buf_ring is full start transmit immediately. */ 1944 if (buf_ring_full(tx->br)) { 1945 mvneta_tx_lockq(sc, q); 1946 mvneta_xmit_locked(sc, q); 1947 mvneta_tx_unlockq(sc, q); 1948 } 1949 1950 /* 1951 * If the buf_ring is empty we will not reorder packets. 1952 * If the lock is available transmit without using buf_ring. 1953 */ 1954 if (buf_ring_empty(tx->br) && mvneta_tx_trylockq(sc, q) != 0) { 1955 error = mvneta_xmitfast_locked(sc, q, &m); 1956 mvneta_tx_unlockq(sc, q); 1957 if (__predict_true(error == 0)) 1958 return (0); 1959 1960 /* Transmit can fail in fastpath. */ 1961 if (__predict_false(m == NULL)) 1962 return (error); 1963 } 1964 1965 /* Enqueue then schedule taskqueue. */ 1966 error = drbr_enqueue(ifp, tx->br, m); 1967 if (__predict_false(error != 0)) 1968 return (error); 1969 1970 taskqueue_enqueue(tx->taskq, &tx->task); 1971 return (0); 1972 } 1973 1974 STATIC int 1975 mvneta_xmit_locked(struct mvneta_softc *sc, int q) 1976 { 1977 struct ifnet *ifp; 1978 struct mvneta_tx_ring *tx; 1979 struct mbuf *m; 1980 int error; 1981 1982 KASSERT_TX_MTX(sc, q); 1983 ifp = sc->ifp; 1984 tx = MVNETA_TX_RING(sc, q); 1985 error = 0; 1986 1987 while ((m = drbr_peek(ifp, tx->br)) != NULL) { 1988 error = mvneta_xmitfast_locked(sc, q, &m); 1989 if (__predict_false(error != 0)) { 1990 if (m != NULL) 1991 drbr_putback(ifp, tx->br, m); 1992 else 1993 drbr_advance(ifp, tx->br); 1994 break; 1995 } 1996 drbr_advance(ifp, tx->br); 1997 } 1998 1999 return (error); 2000 } 2001 #else /* !MVNETA_MULTIQUEUE */ 2002 STATIC void 2003 mvneta_start(struct ifnet *ifp) 2004 { 2005 struct mvneta_softc *sc; 2006 struct mvneta_tx_ring *tx; 2007 int error; 2008 2009 sc = ifp->if_softc; 2010 tx = MVNETA_TX_RING(sc, 0); 2011 2012 mvneta_tx_lockq(sc, 0); 2013 error = mvneta_xmit_locked(sc, 0); 2014 mvneta_tx_unlockq(sc, 0); 2015 /* Handle retransmit in the background taskq. */ 2016 if (__predict_false(error != 0 && error != ENETDOWN)) 2017 taskqueue_enqueue(tx->taskq, &tx->task); 2018 } 2019 2020 STATIC int 2021 mvneta_xmit_locked(struct mvneta_softc *sc, int q) 2022 { 2023 struct ifnet *ifp; 2024 struct mbuf *m; 2025 int error; 2026 2027 KASSERT_TX_MTX(sc, q); 2028 ifp = sc->ifp; 2029 error = 0; 2030 2031 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 2032 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 2033 if (m == NULL) 2034 break; 2035 2036 error = mvneta_xmitfast_locked(sc, q, &m); 2037 if (__predict_false(error != 0)) { 2038 if (m != NULL) 2039 IFQ_DRV_PREPEND(&ifp->if_snd, m); 2040 break; 2041 } 2042 } 2043 2044 return (error); 2045 } 2046 #endif 2047 2048 STATIC int 2049 mvneta_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2050 { 2051 struct mvneta_softc *sc; 2052 struct mvneta_rx_ring *rx; 2053 struct ifreq *ifr; 2054 int error, mask; 2055 uint32_t flags; 2056 bool reinit; 2057 int q; 2058 2059 error = 0; 2060 reinit = false; 2061 sc = ifp->if_softc; 2062 ifr = (struct ifreq *)data; 2063 switch (cmd) { 2064 case SIOCSIFFLAGS: 2065 mvneta_sc_lock(sc); 2066 if (ifp->if_flags & IFF_UP) { 2067 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2068 flags = ifp->if_flags ^ sc->mvneta_if_flags; 2069 2070 if (flags != 0) 2071 sc->mvneta_if_flags = ifp->if_flags; 2072 2073 if ((flags & IFF_PROMISC) != 0) 2074 mvneta_filter_setup(sc); 2075 } else { 2076 mvneta_init_locked(sc); 2077 sc->mvneta_if_flags = ifp->if_flags; 2078 if (sc->phy_attached) 2079 mii_mediachg(sc->mii); 2080 mvneta_sc_unlock(sc); 2081 break; 2082 } 2083 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2084 mvneta_stop_locked(sc); 2085 2086 sc->mvneta_if_flags = ifp->if_flags; 2087 mvneta_sc_unlock(sc); 2088 break; 2089 case SIOCSIFCAP: 2090 if (ifp->if_mtu > sc->tx_csum_limit && 2091 ifr->ifr_reqcap & IFCAP_TXCSUM) 2092 ifr->ifr_reqcap &= ~IFCAP_TXCSUM; 2093 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 2094 if (mask & IFCAP_HWCSUM) { 2095 ifp->if_capenable &= ~IFCAP_HWCSUM; 2096 ifp->if_capenable |= IFCAP_HWCSUM & ifr->ifr_reqcap; 2097 if (ifp->if_capenable & IFCAP_TXCSUM) 2098 ifp->if_hwassist = CSUM_IP | CSUM_TCP | 2099 CSUM_UDP; 2100 else 2101 ifp->if_hwassist = 0; 2102 } 2103 if (mask & IFCAP_LRO) { 2104 mvneta_sc_lock(sc); 2105 ifp->if_capenable ^= IFCAP_LRO; 2106 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2107 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 2108 rx = MVNETA_RX_RING(sc, q); 2109 rx->lro_enabled = !rx->lro_enabled; 2110 } 2111 } 2112 mvneta_sc_unlock(sc); 2113 } 2114 VLAN_CAPABILITIES(ifp); 2115 break; 2116 case SIOCSIFMEDIA: 2117 if ((IFM_SUBTYPE(ifr->ifr_media) == IFM_1000_T || 2118 IFM_SUBTYPE(ifr->ifr_media) == IFM_2500_T) && 2119 (ifr->ifr_media & IFM_FDX) == 0) { 2120 device_printf(sc->dev, 2121 "%s half-duplex unsupported\n", 2122 IFM_SUBTYPE(ifr->ifr_media) == IFM_1000_T ? 2123 "1000Base-T" : 2124 "2500Base-T"); 2125 error = EINVAL; 2126 break; 2127 } 2128 case SIOCGIFMEDIA: /* FALLTHROUGH */ 2129 case SIOCGIFXMEDIA: 2130 if (!sc->phy_attached) 2131 error = ifmedia_ioctl(ifp, ifr, &sc->mvneta_ifmedia, 2132 cmd); 2133 else 2134 error = ifmedia_ioctl(ifp, ifr, &sc->mii->mii_media, 2135 cmd); 2136 break; 2137 case SIOCSIFMTU: 2138 if (ifr->ifr_mtu < 68 || ifr->ifr_mtu > MVNETA_MAX_FRAME - 2139 MVNETA_ETHER_SIZE) { 2140 error = EINVAL; 2141 } else { 2142 ifp->if_mtu = ifr->ifr_mtu; 2143 mvneta_sc_lock(sc); 2144 if (ifp->if_mtu + MVNETA_ETHER_SIZE <= MCLBYTES) { 2145 sc->rx_frame_size = MCLBYTES; 2146 } else { 2147 sc->rx_frame_size = MJUM9BYTES; 2148 } 2149 if (ifp->if_mtu > sc->tx_csum_limit) { 2150 ifp->if_capenable &= ~IFCAP_TXCSUM; 2151 ifp->if_hwassist = 0; 2152 } else { 2153 ifp->if_capenable |= IFCAP_TXCSUM; 2154 ifp->if_hwassist = CSUM_IP | CSUM_TCP | 2155 CSUM_UDP; 2156 } 2157 /* 2158 * Reinitialize RX queues. 2159 * We need to update RX descriptor size. 2160 */ 2161 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2162 reinit = true; 2163 mvneta_stop_locked(sc); 2164 } 2165 2166 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 2167 mvneta_rx_lockq(sc, q); 2168 if (mvneta_rx_queue_init(ifp, q) != 0) { 2169 device_printf(sc->dev, 2170 "initialization failed:" 2171 " cannot initialize queue\n"); 2172 mvneta_rx_unlockq(sc, q); 2173 error = ENOBUFS; 2174 break; 2175 } 2176 mvneta_rx_unlockq(sc, q); 2177 } 2178 if (reinit) 2179 mvneta_init_locked(sc); 2180 2181 mvneta_sc_unlock(sc); 2182 } 2183 break; 2184 2185 default: 2186 error = ether_ioctl(ifp, cmd, data); 2187 break; 2188 } 2189 2190 return (error); 2191 } 2192 2193 STATIC void 2194 mvneta_init_locked(void *arg) 2195 { 2196 struct mvneta_softc *sc; 2197 struct ifnet *ifp; 2198 uint32_t reg; 2199 int q, cpu; 2200 2201 sc = arg; 2202 ifp = sc->ifp; 2203 2204 if (!device_is_attached(sc->dev) || 2205 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2206 return; 2207 2208 mvneta_disable_intr(sc); 2209 callout_stop(&sc->tick_ch); 2210 2211 /* Get the latest mac address */ 2212 bcopy(IF_LLADDR(ifp), sc->enaddr, ETHER_ADDR_LEN); 2213 mvneta_set_mac_address(sc, sc->enaddr); 2214 mvneta_filter_setup(sc); 2215 2216 /* Start DMA Engine */ 2217 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0x00000000); 2218 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0x00000000); 2219 MVNETA_WRITE(sc, MVNETA_PACC, MVNETA_PACC_ACCELERATIONMODE_EDM); 2220 2221 /* Enable port */ 2222 reg = MVNETA_READ(sc, MVNETA_PMACC0); 2223 reg |= MVNETA_PMACC0_PORTEN; 2224 reg &= ~MVNETA_PMACC0_FRAMESIZELIMIT_MASK; 2225 reg |= MVNETA_PMACC0_FRAMESIZELIMIT(ifp->if_mtu + MVNETA_ETHER_SIZE); 2226 MVNETA_WRITE(sc, MVNETA_PMACC0, reg); 2227 2228 /* Allow access to each TXQ/RXQ from both CPU's */ 2229 for (cpu = 0; cpu < mp_ncpus; ++cpu) 2230 MVNETA_WRITE(sc, MVNETA_PCP2Q(cpu), 2231 MVNETA_PCP2Q_TXQEN_MASK | MVNETA_PCP2Q_RXQEN_MASK); 2232 2233 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 2234 mvneta_rx_lockq(sc, q); 2235 mvneta_rx_queue_refill(sc, q); 2236 mvneta_rx_unlockq(sc, q); 2237 } 2238 2239 if (!sc->phy_attached) 2240 mvneta_linkup(sc); 2241 2242 /* Enable interrupt */ 2243 mvneta_enable_intr(sc); 2244 2245 /* Set Counter */ 2246 callout_schedule(&sc->tick_ch, hz); 2247 2248 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2249 } 2250 2251 STATIC void 2252 mvneta_init(void *arg) 2253 { 2254 struct mvneta_softc *sc; 2255 2256 sc = arg; 2257 mvneta_sc_lock(sc); 2258 mvneta_init_locked(sc); 2259 if (sc->phy_attached) 2260 mii_mediachg(sc->mii); 2261 mvneta_sc_unlock(sc); 2262 } 2263 2264 /* ARGSUSED */ 2265 STATIC void 2266 mvneta_stop_locked(struct mvneta_softc *sc) 2267 { 2268 struct ifnet *ifp; 2269 uint32_t reg; 2270 int q; 2271 2272 ifp = sc->ifp; 2273 if (ifp == NULL || (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2274 return; 2275 2276 mvneta_disable_intr(sc); 2277 2278 callout_stop(&sc->tick_ch); 2279 2280 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2281 2282 /* Link down */ 2283 if (sc->linkup == TRUE) 2284 mvneta_linkdown(sc); 2285 2286 /* Reset the MAC Port Enable bit */ 2287 reg = MVNETA_READ(sc, MVNETA_PMACC0); 2288 reg &= ~MVNETA_PMACC0_PORTEN; 2289 MVNETA_WRITE(sc, MVNETA_PMACC0, reg); 2290 2291 /* Disable each of queue */ 2292 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 2293 mvneta_rx_lockq(sc, q); 2294 mvneta_ring_flush_rx_queue(sc, q); 2295 mvneta_rx_unlockq(sc, q); 2296 } 2297 2298 /* 2299 * Hold Reset state of DMA Engine 2300 * (must write 0x0 to restart it) 2301 */ 2302 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0x00000001); 2303 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0x00000001); 2304 2305 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 2306 mvneta_tx_lockq(sc, q); 2307 mvneta_ring_flush_tx_queue(sc, q); 2308 mvneta_tx_unlockq(sc, q); 2309 } 2310 } 2311 2312 STATIC void 2313 mvneta_stop(struct mvneta_softc *sc) 2314 { 2315 2316 mvneta_sc_lock(sc); 2317 mvneta_stop_locked(sc); 2318 mvneta_sc_unlock(sc); 2319 } 2320 2321 STATIC int 2322 mvneta_mediachange(struct ifnet *ifp) 2323 { 2324 struct mvneta_softc *sc; 2325 2326 sc = ifp->if_softc; 2327 2328 if (!sc->phy_attached && !sc->use_inband_status) { 2329 /* We shouldn't be here */ 2330 if_printf(ifp, "Cannot change media in fixed-link mode!\n"); 2331 return (0); 2332 } 2333 2334 if (sc->use_inband_status) { 2335 mvneta_update_media(sc, sc->mvneta_ifmedia.ifm_media); 2336 return (0); 2337 } 2338 2339 mvneta_sc_lock(sc); 2340 2341 /* Update PHY */ 2342 mii_mediachg(sc->mii); 2343 2344 mvneta_sc_unlock(sc); 2345 2346 return (0); 2347 } 2348 2349 STATIC void 2350 mvneta_get_media(struct mvneta_softc *sc, struct ifmediareq *ifmr) 2351 { 2352 uint32_t psr; 2353 2354 psr = MVNETA_READ(sc, MVNETA_PSR); 2355 2356 /* Speed */ 2357 if (psr & MVNETA_PSR_GMIISPEED) 2358 ifmr->ifm_active = IFM_ETHER_SUBTYPE_SET(IFM_1000_T); 2359 else if (psr & MVNETA_PSR_MIISPEED) 2360 ifmr->ifm_active = IFM_ETHER_SUBTYPE_SET(IFM_100_TX); 2361 else if (psr & MVNETA_PSR_LINKUP) 2362 ifmr->ifm_active = IFM_ETHER_SUBTYPE_SET(IFM_10_T); 2363 2364 /* Duplex */ 2365 if (psr & MVNETA_PSR_FULLDX) 2366 ifmr->ifm_active |= IFM_FDX; 2367 2368 /* Link */ 2369 ifmr->ifm_status = IFM_AVALID; 2370 if (psr & MVNETA_PSR_LINKUP) 2371 ifmr->ifm_status |= IFM_ACTIVE; 2372 } 2373 2374 STATIC void 2375 mvneta_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2376 { 2377 struct mvneta_softc *sc; 2378 struct mii_data *mii; 2379 2380 sc = ifp->if_softc; 2381 2382 if (!sc->phy_attached && !sc->use_inband_status) { 2383 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE; 2384 return; 2385 } 2386 2387 mvneta_sc_lock(sc); 2388 2389 if (sc->use_inband_status) { 2390 mvneta_get_media(sc, ifmr); 2391 mvneta_sc_unlock(sc); 2392 return; 2393 } 2394 2395 mii = sc->mii; 2396 mii_pollstat(mii); 2397 2398 ifmr->ifm_active = mii->mii_media_active; 2399 ifmr->ifm_status = mii->mii_media_status; 2400 2401 mvneta_sc_unlock(sc); 2402 } 2403 2404 /* 2405 * Link State Notify 2406 */ 2407 STATIC void 2408 mvneta_update_autoneg(struct mvneta_softc *sc, int enable) 2409 { 2410 int reg; 2411 2412 if (enable) { 2413 reg = MVNETA_READ(sc, MVNETA_PANC); 2414 reg &= ~(MVNETA_PANC_FORCELINKFAIL | MVNETA_PANC_FORCELINKPASS | 2415 MVNETA_PANC_ANFCEN); 2416 reg |= MVNETA_PANC_ANDUPLEXEN | MVNETA_PANC_ANSPEEDEN | 2417 MVNETA_PANC_INBANDANEN; 2418 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2419 2420 reg = MVNETA_READ(sc, MVNETA_PMACC2); 2421 reg |= MVNETA_PMACC2_INBANDANMODE; 2422 MVNETA_WRITE(sc, MVNETA_PMACC2, reg); 2423 2424 reg = MVNETA_READ(sc, MVNETA_PSOMSCD); 2425 reg |= MVNETA_PSOMSCD_ENABLE; 2426 MVNETA_WRITE(sc, MVNETA_PSOMSCD, reg); 2427 } else { 2428 reg = MVNETA_READ(sc, MVNETA_PANC); 2429 reg &= ~(MVNETA_PANC_FORCELINKFAIL | MVNETA_PANC_FORCELINKPASS | 2430 MVNETA_PANC_ANDUPLEXEN | MVNETA_PANC_ANSPEEDEN | 2431 MVNETA_PANC_INBANDANEN); 2432 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2433 2434 reg = MVNETA_READ(sc, MVNETA_PMACC2); 2435 reg &= ~MVNETA_PMACC2_INBANDANMODE; 2436 MVNETA_WRITE(sc, MVNETA_PMACC2, reg); 2437 2438 reg = MVNETA_READ(sc, MVNETA_PSOMSCD); 2439 reg &= ~MVNETA_PSOMSCD_ENABLE; 2440 MVNETA_WRITE(sc, MVNETA_PSOMSCD, reg); 2441 } 2442 } 2443 2444 STATIC int 2445 mvneta_update_media(struct mvneta_softc *sc, int media) 2446 { 2447 int reg, err; 2448 boolean_t running; 2449 2450 err = 0; 2451 2452 mvneta_sc_lock(sc); 2453 2454 mvneta_linkreset(sc); 2455 2456 running = (sc->ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; 2457 if (running) 2458 mvneta_stop_locked(sc); 2459 2460 sc->autoneg = (IFM_SUBTYPE(media) == IFM_AUTO); 2461 2462 if (!sc->phy_attached || sc->use_inband_status) 2463 mvneta_update_autoneg(sc, IFM_SUBTYPE(media) == IFM_AUTO); 2464 2465 mvneta_update_eee(sc); 2466 mvneta_update_fc(sc); 2467 2468 if (IFM_SUBTYPE(media) != IFM_AUTO) { 2469 reg = MVNETA_READ(sc, MVNETA_PANC); 2470 reg &= ~(MVNETA_PANC_SETGMIISPEED | 2471 MVNETA_PANC_SETMIISPEED | 2472 MVNETA_PANC_SETFULLDX); 2473 if (IFM_SUBTYPE(media) == IFM_1000_T || 2474 IFM_SUBTYPE(media) == IFM_2500_T) { 2475 if ((media & IFM_FDX) == 0) { 2476 device_printf(sc->dev, 2477 "%s half-duplex unsupported\n", 2478 IFM_SUBTYPE(media) == IFM_1000_T ? 2479 "1000Base-T" : 2480 "2500Base-T"); 2481 err = EINVAL; 2482 goto out; 2483 } 2484 reg |= MVNETA_PANC_SETGMIISPEED; 2485 } else if (IFM_SUBTYPE(media) == IFM_100_TX) 2486 reg |= MVNETA_PANC_SETMIISPEED; 2487 2488 if (media & IFM_FDX) 2489 reg |= MVNETA_PANC_SETFULLDX; 2490 2491 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2492 } 2493 out: 2494 if (running) 2495 mvneta_init_locked(sc); 2496 mvneta_sc_unlock(sc); 2497 return (err); 2498 } 2499 2500 STATIC void 2501 mvneta_adjust_link(struct mvneta_softc *sc) 2502 { 2503 boolean_t phy_linkup; 2504 int reg; 2505 2506 /* Update eee/fc */ 2507 mvneta_update_eee(sc); 2508 mvneta_update_fc(sc); 2509 2510 /* Check for link change */ 2511 phy_linkup = (sc->mii->mii_media_status & 2512 (IFM_AVALID | IFM_ACTIVE)) == (IFM_AVALID | IFM_ACTIVE); 2513 2514 if (sc->linkup != phy_linkup) 2515 mvneta_linkupdate(sc, phy_linkup); 2516 2517 /* Don't update media on disabled link */ 2518 if (!phy_linkup) 2519 return; 2520 2521 /* Check for media type change */ 2522 if (sc->mvneta_media != sc->mii->mii_media_active) { 2523 sc->mvneta_media = sc->mii->mii_media_active; 2524 2525 reg = MVNETA_READ(sc, MVNETA_PANC); 2526 reg &= ~(MVNETA_PANC_SETGMIISPEED | 2527 MVNETA_PANC_SETMIISPEED | 2528 MVNETA_PANC_SETFULLDX); 2529 if (IFM_SUBTYPE(sc->mvneta_media) == IFM_1000_T || 2530 IFM_SUBTYPE(sc->mvneta_media) == IFM_2500_T) { 2531 reg |= MVNETA_PANC_SETGMIISPEED; 2532 } else if (IFM_SUBTYPE(sc->mvneta_media) == IFM_100_TX) 2533 reg |= MVNETA_PANC_SETMIISPEED; 2534 2535 if (sc->mvneta_media & IFM_FDX) 2536 reg |= MVNETA_PANC_SETFULLDX; 2537 2538 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2539 } 2540 } 2541 2542 STATIC void 2543 mvneta_link_isr(struct mvneta_softc *sc) 2544 { 2545 int linkup; 2546 2547 KASSERT_SC_MTX(sc); 2548 2549 linkup = MVNETA_IS_LINKUP(sc) ? TRUE : FALSE; 2550 if (sc->linkup == linkup) 2551 return; 2552 2553 if (linkup == TRUE) 2554 mvneta_linkup(sc); 2555 else 2556 mvneta_linkdown(sc); 2557 2558 #ifdef DEBUG 2559 device_printf(sc->dev, 2560 "%s: link %s\n", sc->ifp->if_xname, linkup ? "up" : "down"); 2561 #endif 2562 } 2563 2564 STATIC void 2565 mvneta_linkupdate(struct mvneta_softc *sc, boolean_t linkup) 2566 { 2567 2568 KASSERT_SC_MTX(sc); 2569 2570 if (linkup == TRUE) 2571 mvneta_linkup(sc); 2572 else 2573 mvneta_linkdown(sc); 2574 2575 #ifdef DEBUG 2576 device_printf(sc->dev, 2577 "%s: link %s\n", sc->ifp->if_xname, linkup ? "up" : "down"); 2578 #endif 2579 } 2580 2581 STATIC void 2582 mvneta_update_eee(struct mvneta_softc *sc) 2583 { 2584 uint32_t reg; 2585 2586 KASSERT_SC_MTX(sc); 2587 2588 /* set EEE parameters */ 2589 reg = MVNETA_READ(sc, MVNETA_LPIC1); 2590 if (sc->cf_lpi) 2591 reg |= MVNETA_LPIC1_LPIRE; 2592 else 2593 reg &= ~MVNETA_LPIC1_LPIRE; 2594 MVNETA_WRITE(sc, MVNETA_LPIC1, reg); 2595 } 2596 2597 STATIC void 2598 mvneta_update_fc(struct mvneta_softc *sc) 2599 { 2600 uint32_t reg; 2601 2602 KASSERT_SC_MTX(sc); 2603 2604 reg = MVNETA_READ(sc, MVNETA_PANC); 2605 if (sc->cf_fc) { 2606 /* Flow control negotiation */ 2607 reg |= MVNETA_PANC_PAUSEADV; 2608 reg |= MVNETA_PANC_ANFCEN; 2609 } else { 2610 /* Disable flow control negotiation */ 2611 reg &= ~MVNETA_PANC_PAUSEADV; 2612 reg &= ~MVNETA_PANC_ANFCEN; 2613 } 2614 2615 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2616 } 2617 2618 STATIC void 2619 mvneta_linkup(struct mvneta_softc *sc) 2620 { 2621 uint32_t reg; 2622 2623 KASSERT_SC_MTX(sc); 2624 2625 if (!sc->phy_attached || !sc->use_inband_status) { 2626 reg = MVNETA_READ(sc, MVNETA_PANC); 2627 reg |= MVNETA_PANC_FORCELINKPASS; 2628 reg &= ~MVNETA_PANC_FORCELINKFAIL; 2629 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2630 } 2631 2632 mvneta_qflush(sc->ifp); 2633 mvneta_portup(sc); 2634 sc->linkup = TRUE; 2635 if_link_state_change(sc->ifp, LINK_STATE_UP); 2636 } 2637 2638 STATIC void 2639 mvneta_linkdown(struct mvneta_softc *sc) 2640 { 2641 uint32_t reg; 2642 2643 KASSERT_SC_MTX(sc); 2644 2645 if (!sc->phy_attached || !sc->use_inband_status) { 2646 reg = MVNETA_READ(sc, MVNETA_PANC); 2647 reg &= ~MVNETA_PANC_FORCELINKPASS; 2648 reg |= MVNETA_PANC_FORCELINKFAIL; 2649 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2650 } 2651 2652 mvneta_portdown(sc); 2653 mvneta_qflush(sc->ifp); 2654 sc->linkup = FALSE; 2655 if_link_state_change(sc->ifp, LINK_STATE_DOWN); 2656 } 2657 2658 STATIC void 2659 mvneta_linkreset(struct mvneta_softc *sc) 2660 { 2661 struct mii_softc *mii; 2662 2663 if (sc->phy_attached) { 2664 /* Force reset PHY */ 2665 mii = LIST_FIRST(&sc->mii->mii_phys); 2666 if (mii) 2667 mii_phy_reset(mii); 2668 } 2669 } 2670 2671 /* 2672 * Tx Subroutines 2673 */ 2674 STATIC int 2675 mvneta_tx_queue(struct mvneta_softc *sc, struct mbuf **mbufp, int q) 2676 { 2677 struct ifnet *ifp; 2678 bus_dma_segment_t txsegs[MVNETA_TX_SEGLIMIT]; 2679 struct mbuf *mtmp, *mbuf; 2680 struct mvneta_tx_ring *tx; 2681 struct mvneta_buf *txbuf; 2682 struct mvneta_tx_desc *t; 2683 uint32_t ptxsu; 2684 int used, error, i, txnsegs; 2685 2686 mbuf = *mbufp; 2687 tx = MVNETA_TX_RING(sc, q); 2688 DASSERT(tx->used >= 0); 2689 DASSERT(tx->used <= MVNETA_TX_RING_CNT); 2690 t = NULL; 2691 ifp = sc->ifp; 2692 2693 if (__predict_false(mbuf->m_flags & M_VLANTAG)) { 2694 mbuf = ether_vlanencap(mbuf, mbuf->m_pkthdr.ether_vtag); 2695 if (mbuf == NULL) { 2696 tx->drv_error++; 2697 *mbufp = NULL; 2698 return (ENOBUFS); 2699 } 2700 mbuf->m_flags &= ~M_VLANTAG; 2701 *mbufp = mbuf; 2702 } 2703 2704 if (__predict_false(mbuf->m_next != NULL && 2705 (mbuf->m_pkthdr.csum_flags & 2706 (CSUM_IP | CSUM_TCP | CSUM_UDP)) != 0)) { 2707 if (M_WRITABLE(mbuf) == 0) { 2708 mtmp = m_dup(mbuf, M_NOWAIT); 2709 m_freem(mbuf); 2710 if (mtmp == NULL) { 2711 tx->drv_error++; 2712 *mbufp = NULL; 2713 return (ENOBUFS); 2714 } 2715 *mbufp = mbuf = mtmp; 2716 } 2717 } 2718 2719 /* load mbuf using dmamap of 1st descriptor */ 2720 txbuf = &tx->txbuf[tx->cpu]; 2721 error = bus_dmamap_load_mbuf_sg(sc->txmbuf_dtag, 2722 txbuf->dmap, mbuf, txsegs, &txnsegs, 2723 BUS_DMA_NOWAIT); 2724 if (__predict_false(error != 0)) { 2725 #ifdef MVNETA_KTR 2726 CTR3(KTR_SPARE2, "%s:%u bus_dmamap_load_mbuf_sg error=%d", ifp->if_xname, q, error); 2727 #endif 2728 /* This is the only recoverable error (except EFBIG). */ 2729 if (error != ENOMEM) { 2730 tx->drv_error++; 2731 m_freem(mbuf); 2732 *mbufp = NULL; 2733 return (ENOBUFS); 2734 } 2735 return (error); 2736 } 2737 2738 if (__predict_false(txnsegs <= 0 2739 || (txnsegs + tx->used) > MVNETA_TX_RING_CNT)) { 2740 /* we have no enough descriptors or mbuf is broken */ 2741 #ifdef MVNETA_KTR 2742 CTR3(KTR_SPARE2, "%s:%u not enough descriptors txnsegs=%d", 2743 ifp->if_xname, q, txnsegs); 2744 #endif 2745 bus_dmamap_unload(sc->txmbuf_dtag, txbuf->dmap); 2746 return (ENOBUFS); 2747 } 2748 DASSERT(txbuf->m == NULL); 2749 2750 /* remember mbuf using 1st descriptor */ 2751 txbuf->m = mbuf; 2752 bus_dmamap_sync(sc->txmbuf_dtag, txbuf->dmap, 2753 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2754 2755 /* load to tx descriptors */ 2756 used = 0; 2757 for (i = 0; i < txnsegs; i++) { 2758 t = &tx->desc[tx->cpu]; 2759 t->command = 0; 2760 t->l4ichk = 0; 2761 t->flags = 0; 2762 if (__predict_true(i == 0)) { 2763 /* 1st descriptor */ 2764 t->command |= MVNETA_TX_CMD_W_PACKET_OFFSET(0); 2765 t->command |= MVNETA_TX_CMD_F; 2766 mvneta_tx_set_csumflag(ifp, t, mbuf); 2767 } 2768 t->bufptr_pa = txsegs[i].ds_addr; 2769 t->bytecnt = txsegs[i].ds_len; 2770 tx->cpu = tx_counter_adv(tx->cpu, 1); 2771 2772 tx->used++; 2773 used++; 2774 } 2775 /* t is last descriptor here */ 2776 DASSERT(t != NULL); 2777 t->command |= MVNETA_TX_CMD_L|MVNETA_TX_CMD_PADDING; 2778 2779 bus_dmamap_sync(sc->tx_dtag, tx->desc_map, 2780 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2781 2782 while (__predict_false(used > 255)) { 2783 ptxsu = MVNETA_PTXSU_NOWD(255); 2784 MVNETA_WRITE(sc, MVNETA_PTXSU(q), ptxsu); 2785 used -= 255; 2786 } 2787 if (__predict_true(used > 0)) { 2788 ptxsu = MVNETA_PTXSU_NOWD(used); 2789 MVNETA_WRITE(sc, MVNETA_PTXSU(q), ptxsu); 2790 } 2791 return (0); 2792 } 2793 2794 STATIC void 2795 mvneta_tx_set_csumflag(struct ifnet *ifp, 2796 struct mvneta_tx_desc *t, struct mbuf *m) 2797 { 2798 struct ether_header *eh; 2799 struct ether_vlan_header *evh; 2800 int csum_flags; 2801 uint32_t iphl, ipoff; 2802 struct ip *ip; 2803 2804 iphl = ipoff = 0; 2805 csum_flags = ifp->if_hwassist & m->m_pkthdr.csum_flags; 2806 eh = mtod(m, struct ether_header *); 2807 2808 switch (ntohs(eh->ether_type)) { 2809 case ETHERTYPE_IP: 2810 ipoff = ETHER_HDR_LEN; 2811 break; 2812 case ETHERTYPE_VLAN: 2813 ipoff = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2814 evh = mtod(m, struct ether_vlan_header *); 2815 if (ntohs(evh->evl_proto) == ETHERTYPE_VLAN) 2816 ipoff += ETHER_VLAN_ENCAP_LEN; 2817 break; 2818 default: 2819 csum_flags = 0; 2820 } 2821 2822 if (__predict_true(csum_flags & (CSUM_IP|CSUM_IP_TCP|CSUM_IP_UDP))) { 2823 ip = (struct ip *)(m->m_data + ipoff); 2824 iphl = ip->ip_hl<<2; 2825 t->command |= MVNETA_TX_CMD_L3_IP4; 2826 } else { 2827 t->command |= MVNETA_TX_CMD_L4_CHECKSUM_NONE; 2828 return; 2829 } 2830 2831 2832 /* L3 */ 2833 if (csum_flags & CSUM_IP) { 2834 t->command |= MVNETA_TX_CMD_IP4_CHECKSUM; 2835 } 2836 2837 /* L4 */ 2838 if (csum_flags & CSUM_IP_TCP) { 2839 t->command |= MVNETA_TX_CMD_L4_CHECKSUM_NOFRAG; 2840 t->command |= MVNETA_TX_CMD_L4_TCP; 2841 } else if (csum_flags & CSUM_IP_UDP) { 2842 t->command |= MVNETA_TX_CMD_L4_CHECKSUM_NOFRAG; 2843 t->command |= MVNETA_TX_CMD_L4_UDP; 2844 } else 2845 t->command |= MVNETA_TX_CMD_L4_CHECKSUM_NONE; 2846 2847 t->l4ichk = 0; 2848 t->command |= MVNETA_TX_CMD_IP_HEADER_LEN(iphl >> 2); 2849 t->command |= MVNETA_TX_CMD_L3_OFFSET(ipoff); 2850 } 2851 2852 STATIC void 2853 mvneta_tx_queue_complete(struct mvneta_softc *sc, int q) 2854 { 2855 struct mvneta_tx_ring *tx; 2856 struct mvneta_buf *txbuf; 2857 struct mvneta_tx_desc *t __diagused; 2858 uint32_t ptxs, ptxsu, ndesc; 2859 int i; 2860 2861 KASSERT_TX_MTX(sc, q); 2862 2863 tx = MVNETA_TX_RING(sc, q); 2864 if (__predict_false(tx->queue_status == MVNETA_QUEUE_DISABLED)) 2865 return; 2866 2867 ptxs = MVNETA_READ(sc, MVNETA_PTXS(q)); 2868 ndesc = MVNETA_PTXS_GET_TBC(ptxs); 2869 2870 if (__predict_false(ndesc == 0)) { 2871 if (tx->used == 0) 2872 tx->queue_status = MVNETA_QUEUE_IDLE; 2873 else if (tx->queue_status == MVNETA_QUEUE_WORKING && 2874 ((ticks - tx->watchdog_time) > MVNETA_WATCHDOG)) 2875 tx->queue_hung = TRUE; 2876 return; 2877 } 2878 2879 #ifdef MVNETA_KTR 2880 CTR3(KTR_SPARE2, "%s:%u tx_complete begin ndesc=%u", 2881 sc->ifp->if_xname, q, ndesc); 2882 #endif 2883 2884 bus_dmamap_sync(sc->tx_dtag, tx->desc_map, 2885 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2886 2887 for (i = 0; i < ndesc; i++) { 2888 t = &tx->desc[tx->dma]; 2889 #ifdef MVNETA_KTR 2890 if (t->flags & MVNETA_TX_F_ES) 2891 CTR3(KTR_SPARE2, "%s tx error queue %d desc %d", 2892 sc->ifp->if_xname, q, tx->dma); 2893 #endif 2894 txbuf = &tx->txbuf[tx->dma]; 2895 if (__predict_true(txbuf->m != NULL)) { 2896 DASSERT((t->command & MVNETA_TX_CMD_F) != 0); 2897 bus_dmamap_unload(sc->txmbuf_dtag, txbuf->dmap); 2898 m_freem(txbuf->m); 2899 txbuf->m = NULL; 2900 } 2901 else 2902 DASSERT((t->flags & MVNETA_TX_CMD_F) == 0); 2903 tx->dma = tx_counter_adv(tx->dma, 1); 2904 tx->used--; 2905 } 2906 DASSERT(tx->used >= 0); 2907 DASSERT(tx->used <= MVNETA_TX_RING_CNT); 2908 while (__predict_false(ndesc > 255)) { 2909 ptxsu = MVNETA_PTXSU_NORB(255); 2910 MVNETA_WRITE(sc, MVNETA_PTXSU(q), ptxsu); 2911 ndesc -= 255; 2912 } 2913 if (__predict_true(ndesc > 0)) { 2914 ptxsu = MVNETA_PTXSU_NORB(ndesc); 2915 MVNETA_WRITE(sc, MVNETA_PTXSU(q), ptxsu); 2916 } 2917 #ifdef MVNETA_KTR 2918 CTR5(KTR_SPARE2, "%s:%u tx_complete tx_cpu=%d tx_dma=%d tx_used=%d", 2919 sc->ifp->if_xname, q, tx->cpu, tx->dma, tx->used); 2920 #endif 2921 2922 tx->watchdog_time = ticks; 2923 2924 if (tx->used == 0) 2925 tx->queue_status = MVNETA_QUEUE_IDLE; 2926 } 2927 2928 /* 2929 * Do a final TX complete when TX is idle. 2930 */ 2931 STATIC void 2932 mvneta_tx_drain(struct mvneta_softc *sc) 2933 { 2934 struct mvneta_tx_ring *tx; 2935 int q; 2936 2937 /* 2938 * Handle trailing mbuf on TX queue. 2939 * Check is done lockess to avoid TX path contention. 2940 */ 2941 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 2942 tx = MVNETA_TX_RING(sc, q); 2943 if ((ticks - tx->watchdog_time) > MVNETA_WATCHDOG_TXCOMP && 2944 tx->used > 0) { 2945 mvneta_tx_lockq(sc, q); 2946 mvneta_tx_queue_complete(sc, q); 2947 mvneta_tx_unlockq(sc, q); 2948 } 2949 } 2950 } 2951 2952 /* 2953 * Rx Subroutines 2954 */ 2955 STATIC int 2956 mvneta_rx(struct mvneta_softc *sc, int q, int count) 2957 { 2958 uint32_t prxs, npkt; 2959 int more; 2960 2961 more = 0; 2962 mvneta_rx_lockq(sc, q); 2963 prxs = MVNETA_READ(sc, MVNETA_PRXS(q)); 2964 npkt = MVNETA_PRXS_GET_ODC(prxs); 2965 if (__predict_false(npkt == 0)) 2966 goto out; 2967 2968 if (count > 0 && npkt > count) { 2969 more = 1; 2970 npkt = count; 2971 } 2972 mvneta_rx_queue(sc, q, npkt); 2973 out: 2974 mvneta_rx_unlockq(sc, q); 2975 return more; 2976 } 2977 2978 /* 2979 * Helper routine for updating PRXSU register of a given queue. 2980 * Handles number of processed descriptors bigger than maximum acceptable value. 2981 */ 2982 STATIC __inline void 2983 mvneta_prxsu_update(struct mvneta_softc *sc, int q, int processed) 2984 { 2985 uint32_t prxsu; 2986 2987 while (__predict_false(processed > 255)) { 2988 prxsu = MVNETA_PRXSU_NOOFPROCESSEDDESCRIPTORS(255); 2989 MVNETA_WRITE(sc, MVNETA_PRXSU(q), prxsu); 2990 processed -= 255; 2991 } 2992 prxsu = MVNETA_PRXSU_NOOFPROCESSEDDESCRIPTORS(processed); 2993 MVNETA_WRITE(sc, MVNETA_PRXSU(q), prxsu); 2994 } 2995 2996 static __inline void 2997 mvneta_prefetch(void *p) 2998 { 2999 3000 __builtin_prefetch(p); 3001 } 3002 3003 STATIC void 3004 mvneta_rx_queue(struct mvneta_softc *sc, int q, int npkt) 3005 { 3006 struct ifnet *ifp; 3007 struct mvneta_rx_ring *rx; 3008 struct mvneta_rx_desc *r; 3009 struct mvneta_buf *rxbuf; 3010 struct mbuf *m; 3011 struct lro_ctrl *lro; 3012 struct lro_entry *queued; 3013 void *pktbuf; 3014 int i, pktlen, processed, ndma; 3015 3016 KASSERT_RX_MTX(sc, q); 3017 3018 ifp = sc->ifp; 3019 rx = MVNETA_RX_RING(sc, q); 3020 processed = 0; 3021 3022 if (__predict_false(rx->queue_status == MVNETA_QUEUE_DISABLED)) 3023 return; 3024 3025 bus_dmamap_sync(sc->rx_dtag, rx->desc_map, 3026 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3027 3028 for (i = 0; i < npkt; i++) { 3029 /* Prefetch next desc, rxbuf. */ 3030 ndma = rx_counter_adv(rx->dma, 1); 3031 mvneta_prefetch(&rx->desc[ndma]); 3032 mvneta_prefetch(&rx->rxbuf[ndma]); 3033 3034 /* get descriptor and packet */ 3035 r = &rx->desc[rx->dma]; 3036 rxbuf = &rx->rxbuf[rx->dma]; 3037 m = rxbuf->m; 3038 rxbuf->m = NULL; 3039 DASSERT(m != NULL); 3040 bus_dmamap_sync(sc->rxbuf_dtag, rxbuf->dmap, 3041 BUS_DMASYNC_POSTREAD); 3042 bus_dmamap_unload(sc->rxbuf_dtag, rxbuf->dmap); 3043 /* Prefetch mbuf header. */ 3044 mvneta_prefetch(m); 3045 3046 processed++; 3047 /* Drop desc with error status or not in a single buffer. */ 3048 DASSERT((r->status & (MVNETA_RX_F|MVNETA_RX_L)) == 3049 (MVNETA_RX_F|MVNETA_RX_L)); 3050 if (__predict_false((r->status & MVNETA_RX_ES) || 3051 (r->status & (MVNETA_RX_F|MVNETA_RX_L)) != 3052 (MVNETA_RX_F|MVNETA_RX_L))) 3053 goto rx_error; 3054 3055 /* 3056 * [ OFF | MH | PKT | CRC ] 3057 * bytecnt cover MH, PKT, CRC 3058 */ 3059 pktlen = r->bytecnt - ETHER_CRC_LEN - MVNETA_HWHEADER_SIZE; 3060 pktbuf = (uint8_t *)rx->rxbuf_virt_addr[rx->dma] + MVNETA_PACKET_OFFSET + 3061 MVNETA_HWHEADER_SIZE; 3062 3063 /* Prefetch mbuf data. */ 3064 mvneta_prefetch(pktbuf); 3065 3066 /* Write value to mbuf (avoid read). */ 3067 m->m_data = pktbuf; 3068 m->m_len = m->m_pkthdr.len = pktlen; 3069 m->m_pkthdr.rcvif = ifp; 3070 mvneta_rx_set_csumflag(ifp, r, m); 3071 3072 /* Increase rx_dma before releasing the lock. */ 3073 rx->dma = ndma; 3074 3075 if (__predict_false(rx->lro_enabled && 3076 ((r->status & MVNETA_RX_L3_IP) != 0) && 3077 ((r->status & MVNETA_RX_L4_MASK) == MVNETA_RX_L4_TCP) && 3078 (m->m_pkthdr.csum_flags & 3079 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR)) == 3080 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR))) { 3081 if (rx->lro.lro_cnt != 0) { 3082 if (tcp_lro_rx(&rx->lro, m, 0) == 0) 3083 goto rx_done; 3084 } 3085 } 3086 3087 mvneta_rx_unlockq(sc, q); 3088 (*ifp->if_input)(ifp, m); 3089 mvneta_rx_lockq(sc, q); 3090 /* 3091 * Check whether this queue has been disabled in the 3092 * meantime. If yes, then clear LRO and exit. 3093 */ 3094 if(__predict_false(rx->queue_status == MVNETA_QUEUE_DISABLED)) 3095 goto rx_lro; 3096 rx_done: 3097 /* Refresh receive ring to avoid stall and minimize jitter. */ 3098 if (processed >= MVNETA_RX_REFILL_COUNT) { 3099 mvneta_prxsu_update(sc, q, processed); 3100 mvneta_rx_queue_refill(sc, q); 3101 processed = 0; 3102 } 3103 continue; 3104 rx_error: 3105 m_freem(m); 3106 rx->dma = ndma; 3107 /* Refresh receive ring to avoid stall and minimize jitter. */ 3108 if (processed >= MVNETA_RX_REFILL_COUNT) { 3109 mvneta_prxsu_update(sc, q, processed); 3110 mvneta_rx_queue_refill(sc, q); 3111 processed = 0; 3112 } 3113 } 3114 #ifdef MVNETA_KTR 3115 CTR3(KTR_SPARE2, "%s:%u %u packets received", ifp->if_xname, q, npkt); 3116 #endif 3117 /* DMA status update */ 3118 mvneta_prxsu_update(sc, q, processed); 3119 /* Refill the rest of buffers if there are any to refill */ 3120 mvneta_rx_queue_refill(sc, q); 3121 3122 rx_lro: 3123 /* 3124 * Flush any outstanding LRO work 3125 */ 3126 lro = &rx->lro; 3127 while (__predict_false((queued = LIST_FIRST(&lro->lro_active)) != NULL)) { 3128 LIST_REMOVE(LIST_FIRST((&lro->lro_active)), next); 3129 tcp_lro_flush(lro, queued); 3130 } 3131 } 3132 3133 STATIC void 3134 mvneta_rx_buf_free(struct mvneta_softc *sc, struct mvneta_buf *rxbuf) 3135 { 3136 3137 bus_dmamap_unload(sc->rxbuf_dtag, rxbuf->dmap); 3138 /* This will remove all data at once */ 3139 m_freem(rxbuf->m); 3140 } 3141 3142 STATIC void 3143 mvneta_rx_queue_refill(struct mvneta_softc *sc, int q) 3144 { 3145 struct mvneta_rx_ring *rx; 3146 struct mvneta_rx_desc *r; 3147 struct mvneta_buf *rxbuf; 3148 bus_dma_segment_t segs; 3149 struct mbuf *m; 3150 uint32_t prxs, prxsu, ndesc; 3151 int npkt, refill, nsegs, error; 3152 3153 KASSERT_RX_MTX(sc, q); 3154 3155 rx = MVNETA_RX_RING(sc, q); 3156 prxs = MVNETA_READ(sc, MVNETA_PRXS(q)); 3157 ndesc = MVNETA_PRXS_GET_NODC(prxs) + MVNETA_PRXS_GET_ODC(prxs); 3158 refill = MVNETA_RX_RING_CNT - ndesc; 3159 #ifdef MVNETA_KTR 3160 CTR3(KTR_SPARE2, "%s:%u refill %u packets", sc->ifp->if_xname, q, 3161 refill); 3162 #endif 3163 if (__predict_false(refill <= 0)) 3164 return; 3165 3166 for (npkt = 0; npkt < refill; npkt++) { 3167 rxbuf = &rx->rxbuf[rx->cpu]; 3168 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, sc->rx_frame_size); 3169 if (__predict_false(m == NULL)) { 3170 error = ENOBUFS; 3171 break; 3172 } 3173 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 3174 3175 error = bus_dmamap_load_mbuf_sg(sc->rxbuf_dtag, rxbuf->dmap, 3176 m, &segs, &nsegs, BUS_DMA_NOWAIT); 3177 if (__predict_false(error != 0 || nsegs != 1)) { 3178 KASSERT(1, ("Failed to load Rx mbuf DMA map")); 3179 m_freem(m); 3180 break; 3181 } 3182 3183 /* Add the packet to the ring */ 3184 rxbuf->m = m; 3185 r = &rx->desc[rx->cpu]; 3186 r->bufptr_pa = segs.ds_addr; 3187 rx->rxbuf_virt_addr[rx->cpu] = m->m_data; 3188 3189 rx->cpu = rx_counter_adv(rx->cpu, 1); 3190 } 3191 if (npkt == 0) { 3192 if (refill == MVNETA_RX_RING_CNT) 3193 rx->needs_refill = TRUE; 3194 return; 3195 } 3196 3197 rx->needs_refill = FALSE; 3198 bus_dmamap_sync(sc->rx_dtag, rx->desc_map, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3199 3200 while (__predict_false(npkt > 255)) { 3201 prxsu = MVNETA_PRXSU_NOOFNEWDESCRIPTORS(255); 3202 MVNETA_WRITE(sc, MVNETA_PRXSU(q), prxsu); 3203 npkt -= 255; 3204 } 3205 if (__predict_true(npkt > 0)) { 3206 prxsu = MVNETA_PRXSU_NOOFNEWDESCRIPTORS(npkt); 3207 MVNETA_WRITE(sc, MVNETA_PRXSU(q), prxsu); 3208 } 3209 } 3210 3211 STATIC __inline void 3212 mvneta_rx_set_csumflag(struct ifnet *ifp, 3213 struct mvneta_rx_desc *r, struct mbuf *m) 3214 { 3215 uint32_t csum_flags; 3216 3217 csum_flags = 0; 3218 if (__predict_false((r->status & 3219 (MVNETA_RX_IP_HEADER_OK|MVNETA_RX_L3_IP)) == 0)) 3220 return; /* not a IP packet */ 3221 3222 /* L3 */ 3223 if (__predict_true((r->status & MVNETA_RX_IP_HEADER_OK) == 3224 MVNETA_RX_IP_HEADER_OK)) 3225 csum_flags |= CSUM_L3_CALC|CSUM_L3_VALID; 3226 3227 if (__predict_true((r->status & (MVNETA_RX_IP_HEADER_OK|MVNETA_RX_L3_IP)) == 3228 (MVNETA_RX_IP_HEADER_OK|MVNETA_RX_L3_IP))) { 3229 /* L4 */ 3230 switch (r->status & MVNETA_RX_L4_MASK) { 3231 case MVNETA_RX_L4_TCP: 3232 case MVNETA_RX_L4_UDP: 3233 csum_flags |= CSUM_L4_CALC; 3234 if (__predict_true((r->status & 3235 MVNETA_RX_L4_CHECKSUM_OK) == MVNETA_RX_L4_CHECKSUM_OK)) { 3236 csum_flags |= CSUM_L4_VALID; 3237 m->m_pkthdr.csum_data = htons(0xffff); 3238 } 3239 break; 3240 case MVNETA_RX_L4_OTH: 3241 default: 3242 break; 3243 } 3244 } 3245 m->m_pkthdr.csum_flags = csum_flags; 3246 } 3247 3248 /* 3249 * MAC address filter 3250 */ 3251 STATIC void 3252 mvneta_filter_setup(struct mvneta_softc *sc) 3253 { 3254 struct ifnet *ifp; 3255 uint32_t dfut[MVNETA_NDFUT], dfsmt[MVNETA_NDFSMT], dfomt[MVNETA_NDFOMT]; 3256 uint32_t pxc; 3257 int i; 3258 3259 KASSERT_SC_MTX(sc); 3260 3261 memset(dfut, 0, sizeof(dfut)); 3262 memset(dfsmt, 0, sizeof(dfsmt)); 3263 memset(dfomt, 0, sizeof(dfomt)); 3264 3265 ifp = sc->ifp; 3266 ifp->if_flags |= IFF_ALLMULTI; 3267 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) { 3268 for (i = 0; i < MVNETA_NDFSMT; i++) { 3269 dfsmt[i] = dfomt[i] = 3270 MVNETA_DF(0, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3271 MVNETA_DF(1, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3272 MVNETA_DF(2, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3273 MVNETA_DF(3, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS); 3274 } 3275 } 3276 3277 pxc = MVNETA_READ(sc, MVNETA_PXC); 3278 pxc &= ~(MVNETA_PXC_UPM | MVNETA_PXC_RXQ_MASK | MVNETA_PXC_RXQARP_MASK | 3279 MVNETA_PXC_TCPQ_MASK | MVNETA_PXC_UDPQ_MASK | MVNETA_PXC_BPDUQ_MASK); 3280 pxc |= MVNETA_PXC_RXQ(MVNETA_RX_QNUM_MAX-1); 3281 pxc |= MVNETA_PXC_RXQARP(MVNETA_RX_QNUM_MAX-1); 3282 pxc |= MVNETA_PXC_TCPQ(MVNETA_RX_QNUM_MAX-1); 3283 pxc |= MVNETA_PXC_UDPQ(MVNETA_RX_QNUM_MAX-1); 3284 pxc |= MVNETA_PXC_BPDUQ(MVNETA_RX_QNUM_MAX-1); 3285 pxc |= MVNETA_PXC_RB | MVNETA_PXC_RBIP | MVNETA_PXC_RBARP; 3286 if (ifp->if_flags & IFF_BROADCAST) { 3287 pxc &= ~(MVNETA_PXC_RB | MVNETA_PXC_RBIP | MVNETA_PXC_RBARP); 3288 } 3289 if (ifp->if_flags & IFF_PROMISC) { 3290 pxc |= MVNETA_PXC_UPM; 3291 } 3292 MVNETA_WRITE(sc, MVNETA_PXC, pxc); 3293 3294 /* Set Destination Address Filter Unicast Table */ 3295 if (ifp->if_flags & IFF_PROMISC) { 3296 /* pass all unicast addresses */ 3297 for (i = 0; i < MVNETA_NDFUT; i++) { 3298 dfut[i] = 3299 MVNETA_DF(0, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3300 MVNETA_DF(1, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3301 MVNETA_DF(2, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3302 MVNETA_DF(3, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS); 3303 } 3304 } else { 3305 i = sc->enaddr[5] & 0xf; /* last nibble */ 3306 dfut[i>>2] = MVNETA_DF(i&3, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS); 3307 } 3308 MVNETA_WRITE_REGION(sc, MVNETA_DFUT(0), dfut, MVNETA_NDFUT); 3309 3310 /* Set Destination Address Filter Multicast Tables */ 3311 MVNETA_WRITE_REGION(sc, MVNETA_DFSMT(0), dfsmt, MVNETA_NDFSMT); 3312 MVNETA_WRITE_REGION(sc, MVNETA_DFOMT(0), dfomt, MVNETA_NDFOMT); 3313 } 3314 3315 /* 3316 * sysctl(9) 3317 */ 3318 STATIC int 3319 sysctl_read_mib(SYSCTL_HANDLER_ARGS) 3320 { 3321 struct mvneta_sysctl_mib *arg; 3322 struct mvneta_softc *sc; 3323 uint64_t val; 3324 3325 arg = (struct mvneta_sysctl_mib *)arg1; 3326 if (arg == NULL) 3327 return (EINVAL); 3328 3329 sc = arg->sc; 3330 if (sc == NULL) 3331 return (EINVAL); 3332 if (arg->index < 0 || arg->index > MVNETA_PORTMIB_NOCOUNTER) 3333 return (EINVAL); 3334 3335 mvneta_sc_lock(sc); 3336 val = arg->counter; 3337 mvneta_sc_unlock(sc); 3338 return sysctl_handle_64(oidp, &val, 0, req); 3339 } 3340 3341 3342 STATIC int 3343 sysctl_clear_mib(SYSCTL_HANDLER_ARGS) 3344 { 3345 struct mvneta_softc *sc; 3346 int err, val; 3347 3348 val = 0; 3349 sc = (struct mvneta_softc *)arg1; 3350 if (sc == NULL) 3351 return (EINVAL); 3352 3353 err = sysctl_handle_int(oidp, &val, 0, req); 3354 if (err != 0) 3355 return (err); 3356 3357 if (val < 0 || val > 1) 3358 return (EINVAL); 3359 3360 if (val == 1) { 3361 mvneta_sc_lock(sc); 3362 mvneta_clear_mib(sc); 3363 mvneta_sc_unlock(sc); 3364 } 3365 3366 return (0); 3367 } 3368 3369 STATIC int 3370 sysctl_set_queue_rxthtime(SYSCTL_HANDLER_ARGS) 3371 { 3372 struct mvneta_sysctl_queue *arg; 3373 struct mvneta_rx_ring *rx; 3374 struct mvneta_softc *sc; 3375 uint32_t reg, time_mvtclk; 3376 int err, time_us; 3377 3378 rx = NULL; 3379 arg = (struct mvneta_sysctl_queue *)arg1; 3380 if (arg == NULL) 3381 return (EINVAL); 3382 if (arg->queue < 0 || arg->queue > MVNETA_RX_RING_CNT) 3383 return (EINVAL); 3384 if (arg->rxtx != MVNETA_SYSCTL_RX) 3385 return (EINVAL); 3386 3387 sc = arg->sc; 3388 if (sc == NULL) 3389 return (EINVAL); 3390 3391 /* read queue length */ 3392 mvneta_sc_lock(sc); 3393 mvneta_rx_lockq(sc, arg->queue); 3394 rx = MVNETA_RX_RING(sc, arg->queue); 3395 time_mvtclk = rx->queue_th_time; 3396 time_us = ((uint64_t)time_mvtclk * 1000ULL * 1000ULL) / sc->clk_freq; 3397 mvneta_rx_unlockq(sc, arg->queue); 3398 mvneta_sc_unlock(sc); 3399 3400 err = sysctl_handle_int(oidp, &time_us, 0, req); 3401 if (err != 0) 3402 return (err); 3403 3404 mvneta_sc_lock(sc); 3405 mvneta_rx_lockq(sc, arg->queue); 3406 3407 /* update queue length (0[sec] - 1[sec]) */ 3408 if (time_us < 0 || time_us > (1000 * 1000)) { 3409 mvneta_rx_unlockq(sc, arg->queue); 3410 mvneta_sc_unlock(sc); 3411 return (EINVAL); 3412 } 3413 time_mvtclk = sc->clk_freq * (uint64_t)time_us / (1000ULL * 1000ULL); 3414 rx->queue_th_time = time_mvtclk; 3415 reg = MVNETA_PRXITTH_RITT(rx->queue_th_time); 3416 MVNETA_WRITE(sc, MVNETA_PRXITTH(arg->queue), reg); 3417 mvneta_rx_unlockq(sc, arg->queue); 3418 mvneta_sc_unlock(sc); 3419 3420 return (0); 3421 } 3422 3423 STATIC void 3424 sysctl_mvneta_init(struct mvneta_softc *sc) 3425 { 3426 struct sysctl_ctx_list *ctx; 3427 struct sysctl_oid_list *children; 3428 struct sysctl_oid_list *rxchildren; 3429 struct sysctl_oid_list *qchildren, *mchildren; 3430 struct sysctl_oid *tree; 3431 int i, q; 3432 struct mvneta_sysctl_queue *rxarg; 3433 #define MVNETA_SYSCTL_NAME(num) "queue" # num 3434 static const char *sysctl_queue_names[] = { 3435 MVNETA_SYSCTL_NAME(0), MVNETA_SYSCTL_NAME(1), 3436 MVNETA_SYSCTL_NAME(2), MVNETA_SYSCTL_NAME(3), 3437 MVNETA_SYSCTL_NAME(4), MVNETA_SYSCTL_NAME(5), 3438 MVNETA_SYSCTL_NAME(6), MVNETA_SYSCTL_NAME(7), 3439 }; 3440 #undef MVNETA_SYSCTL_NAME 3441 3442 #ifndef NO_SYSCTL_DESCR 3443 #define MVNETA_SYSCTL_DESCR(num) "configuration parameters for queue " # num 3444 static const char *sysctl_queue_descrs[] = { 3445 MVNETA_SYSCTL_DESCR(0), MVNETA_SYSCTL_DESCR(1), 3446 MVNETA_SYSCTL_DESCR(2), MVNETA_SYSCTL_DESCR(3), 3447 MVNETA_SYSCTL_DESCR(4), MVNETA_SYSCTL_DESCR(5), 3448 MVNETA_SYSCTL_DESCR(6), MVNETA_SYSCTL_DESCR(7), 3449 }; 3450 #undef MVNETA_SYSCTL_DESCR 3451 #endif 3452 3453 3454 ctx = device_get_sysctl_ctx(sc->dev); 3455 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 3456 3457 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rx", 3458 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "NETA RX"); 3459 rxchildren = SYSCTL_CHILDREN(tree); 3460 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "mib", 3461 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "NETA MIB"); 3462 mchildren = SYSCTL_CHILDREN(tree); 3463 3464 3465 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "flow_control", 3466 CTLFLAG_RW, &sc->cf_fc, 0, "flow control"); 3467 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lpi", 3468 CTLFLAG_RW, &sc->cf_lpi, 0, "Low Power Idle"); 3469 3470 /* 3471 * MIB access 3472 */ 3473 /* dev.mvneta.[unit].mib.<mibs> */ 3474 for (i = 0; i < MVNETA_PORTMIB_NOCOUNTER; i++) { 3475 struct mvneta_sysctl_mib *mib_arg = &sc->sysctl_mib[i]; 3476 3477 mib_arg->sc = sc; 3478 mib_arg->index = i; 3479 SYSCTL_ADD_PROC(ctx, mchildren, OID_AUTO, 3480 mvneta_mib_list[i].sysctl_name, 3481 CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 3482 (void *)mib_arg, 0, sysctl_read_mib, "I", 3483 mvneta_mib_list[i].desc); 3484 } 3485 SYSCTL_ADD_UQUAD(ctx, mchildren, OID_AUTO, "rx_discard", 3486 CTLFLAG_RD, &sc->counter_pdfc, "Port Rx Discard Frame Counter"); 3487 SYSCTL_ADD_UQUAD(ctx, mchildren, OID_AUTO, "overrun", 3488 CTLFLAG_RD, &sc->counter_pofc, "Port Overrun Frame Counter"); 3489 SYSCTL_ADD_UINT(ctx, mchildren, OID_AUTO, "watchdog", 3490 CTLFLAG_RD, &sc->counter_watchdog, 0, "TX Watchdog Counter"); 3491 3492 SYSCTL_ADD_PROC(ctx, mchildren, OID_AUTO, "reset", 3493 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 3494 (void *)sc, 0, sysctl_clear_mib, "I", "Reset MIB counters"); 3495 3496 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 3497 rxarg = &sc->sysctl_rx_queue[q]; 3498 3499 rxarg->sc = sc; 3500 rxarg->queue = q; 3501 rxarg->rxtx = MVNETA_SYSCTL_RX; 3502 3503 /* hw.mvneta.mvneta[unit].rx.[queue] */ 3504 tree = SYSCTL_ADD_NODE(ctx, rxchildren, OID_AUTO, 3505 sysctl_queue_names[q], CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 3506 sysctl_queue_descrs[q]); 3507 qchildren = SYSCTL_CHILDREN(tree); 3508 3509 /* hw.mvneta.mvneta[unit].rx.[queue].threshold_timer_us */ 3510 SYSCTL_ADD_PROC(ctx, qchildren, OID_AUTO, "threshold_timer_us", 3511 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, rxarg, 0, 3512 sysctl_set_queue_rxthtime, "I", 3513 "interrupt coalescing threshold timer [us]"); 3514 } 3515 } 3516 3517 /* 3518 * MIB 3519 */ 3520 STATIC uint64_t 3521 mvneta_read_mib(struct mvneta_softc *sc, int index) 3522 { 3523 struct mvneta_mib_def *mib; 3524 uint64_t val; 3525 3526 mib = &mvneta_mib_list[index]; 3527 val = MVNETA_READ_MIB(sc, mib->regnum); 3528 if (mib->reg64) 3529 val |= (uint64_t)MVNETA_READ_MIB(sc, mib->regnum + 4) << 32; 3530 return (val); 3531 } 3532 3533 STATIC void 3534 mvneta_clear_mib(struct mvneta_softc *sc) 3535 { 3536 int i; 3537 3538 KASSERT_SC_MTX(sc); 3539 3540 for (i = 0; i < nitems(mvneta_mib_list); i++) { 3541 (void)mvneta_read_mib(sc, i); 3542 sc->sysctl_mib[i].counter = 0; 3543 } 3544 MVNETA_READ(sc, MVNETA_PDFC); 3545 sc->counter_pdfc = 0; 3546 MVNETA_READ(sc, MVNETA_POFC); 3547 sc->counter_pofc = 0; 3548 sc->counter_watchdog = 0; 3549 } 3550 3551 STATIC void 3552 mvneta_update_mib(struct mvneta_softc *sc) 3553 { 3554 struct mvneta_tx_ring *tx; 3555 int i; 3556 uint64_t val; 3557 uint32_t reg; 3558 3559 for (i = 0; i < nitems(mvneta_mib_list); i++) { 3560 3561 val = mvneta_read_mib(sc, i); 3562 if (val == 0) 3563 continue; 3564 3565 sc->sysctl_mib[i].counter += val; 3566 switch (mvneta_mib_list[i].regnum) { 3567 case MVNETA_MIB_RX_GOOD_OCT: 3568 if_inc_counter(sc->ifp, IFCOUNTER_IBYTES, val); 3569 break; 3570 case MVNETA_MIB_RX_BAD_FRAME: 3571 if_inc_counter(sc->ifp, IFCOUNTER_IERRORS, val); 3572 break; 3573 case MVNETA_MIB_RX_GOOD_FRAME: 3574 if_inc_counter(sc->ifp, IFCOUNTER_IPACKETS, val); 3575 break; 3576 case MVNETA_MIB_RX_MCAST_FRAME: 3577 if_inc_counter(sc->ifp, IFCOUNTER_IMCASTS, val); 3578 break; 3579 case MVNETA_MIB_TX_GOOD_OCT: 3580 if_inc_counter(sc->ifp, IFCOUNTER_OBYTES, val); 3581 break; 3582 case MVNETA_MIB_TX_GOOD_FRAME: 3583 if_inc_counter(sc->ifp, IFCOUNTER_OPACKETS, val); 3584 break; 3585 case MVNETA_MIB_TX_MCAST_FRAME: 3586 if_inc_counter(sc->ifp, IFCOUNTER_OMCASTS, val); 3587 break; 3588 case MVNETA_MIB_MAC_COL: 3589 if_inc_counter(sc->ifp, IFCOUNTER_COLLISIONS, val); 3590 break; 3591 case MVNETA_MIB_TX_MAC_TRNS_ERR: 3592 case MVNETA_MIB_TX_EXCES_COL: 3593 case MVNETA_MIB_MAC_LATE_COL: 3594 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, val); 3595 break; 3596 } 3597 } 3598 3599 reg = MVNETA_READ(sc, MVNETA_PDFC); 3600 sc->counter_pdfc += reg; 3601 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, reg); 3602 reg = MVNETA_READ(sc, MVNETA_POFC); 3603 sc->counter_pofc += reg; 3604 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, reg); 3605 3606 /* TX watchdog. */ 3607 if (sc->counter_watchdog_mib > 0) { 3608 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, sc->counter_watchdog_mib); 3609 sc->counter_watchdog_mib = 0; 3610 } 3611 /* 3612 * TX driver errors: 3613 * We do not take queue locks to not disrupt TX path. 3614 * We may only miss one drv error which will be fixed at 3615 * next mib update. We may also clear counter when TX path 3616 * is incrementing it but we only do it if counter was not zero 3617 * thus we may only loose one error. 3618 */ 3619 for (i = 0; i < MVNETA_TX_QNUM_MAX; i++) { 3620 tx = MVNETA_TX_RING(sc, i); 3621 3622 if (tx->drv_error > 0) { 3623 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, tx->drv_error); 3624 tx->drv_error = 0; 3625 } 3626 } 3627 } 3628