1 /* 2 * Copyright (c) 2017 Stormshield. 3 * Copyright (c) 2017 Semihalf. 4 * Copyright (c) 2015 Internet Initiative Japan Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 25 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 * 30 */ 31 32 #ifndef _IF_MVNETAREG_H_ 33 #define _IF_MVNETAREG_H_ 34 35 #include "opt_mvneta.h" 36 37 #if BYTE_ORDER == BIG_ENDIAN 38 #error "BIG ENDIAN not supported" 39 #endif 40 41 #define MVNETA_SIZE 0x4000 42 43 #define MVNETA_NWINDOW 6 44 #define MVNETA_NREMAP 4 45 46 #define MVNETA_MAX_QUEUE_SIZE 8 47 #define MVNETA_RX_QNUM_MAX 1 48 /* XXX: Currently multi-queue can be used on the Tx side only */ 49 #ifdef MVNETA_MULTIQUEUE 50 #define MVNETA_TX_QNUM_MAX 2 51 #else 52 #define MVNETA_TX_QNUM_MAX 1 53 #endif 54 55 #if MVNETA_TX_QNUM_MAX & (MVNETA_TX_QNUM_MAX - 1) != 0 56 #error "MVNETA_TX_QNUM_MAX Should be a power of 2" 57 #endif 58 #if MVNETA_RX_QNUM_MAX & (MVNETA_RX_QNUM_MAX - 1) != 0 59 #error "MVNETA_RX_QNUM_MAX Should be a power of 2" 60 #endif 61 62 #define MVNETA_QUEUE(n) (1 << (n)) 63 #define MVNETA_QUEUE_ALL 0xff 64 #define MVNETA_TX_QUEUE_ALL ((1<<MVNETA_TX_QNUM_MAX)-1) 65 #define MVNETA_RX_QUEUE_ALL ((1<<MVNETA_RX_QNUM_MAX)-1) 66 67 /* 68 * Ethernet Unit Registers 69 * GbE0 BASE 0x00007.0000 SIZE 0x4000 70 * GbE1 BASE 0x00007.4000 SIZE 0x4000 71 * 72 * TBD: reasonable bus space submapping.... 73 */ 74 /* Address Decoder Registers */ 75 #define MVNETA_BASEADDR(n) (0x2200 + ((n) << 3)) /* Base Address */ 76 #define MVNETA_S(n) (0x2204 + ((n) << 3)) /* Size */ 77 #define MVNETA_HA(n) (0x2280 + ((n) << 2)) /* High Address Remap */ 78 #define MVNETA_BARE 0x2290 /* Base Address Enable */ 79 #define MVNETA_EPAP 0x2294 /* Ethernet Port Access Protect */ 80 81 /* Global Miscellaneous Registers */ 82 #define MVNETA_PHYADDR 0x2000 83 #define MVNETA_SMI 0x2004 84 #define MVNETA_EUDA 0x2008 /* Ethernet Unit Default Address */ 85 #define MVNETA_EUDID 0x200c /* Ethernet Unit Default ID */ 86 #define MVNETA_MBUS_CONF 0x2010 /* MBUS configuration */ 87 #define MVNETA_MBUS_RETRY_EN 0x20 /* MBUS transactions retry enable */ 88 #define MVNETA_EUIC 0x2080 /* Ethernet Unit Interrupt Cause */ 89 #define MVNETA_EUIM 0x2084 /* Ethernet Unit Interrupt Mask */ 90 #define MVNETA_EUEA 0x2094 /* Ethernet Unit Error Address */ 91 #define MVNETA_EUIAE 0x2098 /* Ethernet Unit Internal Addr Error */ 92 #define MVNETA_EUC 0x20b0 /* Ethernet Unit Control */ 93 94 /* Miscellaneous Registers */ 95 #define MVNETA_SDC 0x241c /* SDMA Configuration */ 96 97 /* Networking Controller Miscellaneous Registers */ 98 #define MVNETA_PACC 0x2500 /* Port Acceleration Mode */ 99 #define MVNETA_PV 0x25bc /* Port Version */ 100 101 /* Rx DMA Hardware Parser Registers */ 102 #define MVNETA_EVLANE 0x2410 /* VLAN EtherType */ 103 #define MVNETA_MACAL 0x2414 /* MAC Address Low */ 104 #define MVNETA_MACAH 0x2418 /* MAC Address High */ 105 #define MVNETA_NDSCP 7 106 #define MVNETA_DSCP(n) (0x2420 + ((n) << 2)) 107 #define MVNETA_VPT2P 0x2440 /* VLAN Priority Tag to Priority */ 108 #define MVNETA_ETP 0x24bc /* Ethernet Type Priority */ 109 #define MVNETA_NDFSMT 64 110 #define MVNETA_DFSMT(n) (0x3400 + ((n) << 2)) 111 /* Destination Address Filter Special Multicast Table */ 112 #define MVNETA_NDFOMT 64 113 #define MVNETA_DFOMT(n) (0x3500 + ((n) << 2)) 114 /* Destination Address Filter Other Multicast Table */ 115 #define MVNETA_NDFUT 4 116 #define MVNETA_DFUT(n) (0x3600 + ((n) << 2)) 117 /* Destination Address Filter Unicast Table */ 118 119 /* Rx DMA Miscellaneous Registers */ 120 #define MVNETA_PMFS 0x247c /* Port Rx Minimal Frame Size */ 121 #define MVNETA_PDFC 0x2484 /* Port Rx Discard Frame Counter */ 122 #define MVNETA_POFC 0x2488 /* Port Overrun Frame Counter */ 123 #define MVNETA_RQC 0x2680 /* Receive Queue Command */ 124 125 /* Rx DMA Networking Controller Miscellaneous Registers */ 126 #define MVNETA_PRXC(q) (0x1400 + ((q) << 2)) /*Port RX queues Config*/ 127 #define MVNETA_PRXSNP(q) (0x1420 + ((q) << 2)) /* Port RX queues Snoop */ 128 #define MVNETA_PRXDQA(q) (0x1480 + ((q) << 2)) /*P RXqueues desc Q Addr*/ 129 #define MVNETA_PRXDQS(q) (0x14a0 + ((q) << 2)) /*P RXqueues desc Q Size*/ 130 #define MVNETA_PRXDQTH(q) (0x14c0 + ((q) << 2)) /*P RXqueues desc Q Thrs*/ 131 #define MVNETA_PRXS(q) (0x14e0 + ((q) << 2)) /*Port RX queues Status */ 132 #define MVNETA_PRXSU(q) (0x1500 + ((q) << 2)) /*P RXqueues Stat Update*/ 133 #define MVNETA_PRXDI(q) (0x1520 + ((q) << 2)) /*P RXqueues Stat Update*/ 134 #define MVNETA_PRXINIT 0x1cc0 /* Port RX Initialization */ 135 136 /* Rx DMA Wake on LAN Registers 0x3690 - 0x36b8 */ 137 138 /* Tx DMA Miscellaneous Registers */ 139 #define MVNETA_TQC 0x2448 /* Transmit Queue Command */ 140 #define MVNETA_TQC_1 0x24e4 141 #define MVNETA_PXTFTT 0x2478 /* Port Tx FIFO Threshold */ 142 #define MVNETA_TXBADFCS 0x3cc0 /*Tx Bad FCS Transmitted Pckts Counter*/ 143 #define MVNETA_TXDROPPED 0x3cc4 /* Tx Dropped Packets Counter */ 144 145 /* Tx DMA Networking Controller Miscellaneous Registers */ 146 #define MVNETA_PTXDQA(q) (0x3c00 + ((q) << 2)) /*P TXqueues desc Q Addr*/ 147 #define MVNETA_PTXDQS(q) (0x3c20 + ((q) << 2)) /*P TXqueues desc Q Size*/ 148 #define MVNETA_PTXS(q) (0x3c40 + ((q) << 2)) /* Port TX queues Status*/ 149 #define MVNETA_PTXSU(q) (0x3c60 + ((q) << 2)) /*P TXqueues Stat Update*/ 150 #define MVNETA_PTXDI(q) (0x3c80 + ((q) << 2)) /* P TXqueues Desc Index*/ 151 #define MVNETA_TXTBC(q) (0x3ca0 + ((q) << 2)) /* TX Trans-ed Buf Count*/ 152 #define MVNETA_PTXINIT 0x3cf0 /* Port TX Initialization */ 153 154 /* Tx DMA Packet Modification Registers */ 155 #define MVNETA_NMH 15 156 #define MVNETA_TXMH(n) (0x3d44 + ((n) << 2)) 157 #define MVNETA_TXMTU 0x3d88 158 159 /* Tx DMA Queue Arbiter Registers (Version 1) */ 160 #define MVNETA_TQFPC_V1 0x24dc /* Transmit Queue Fixed Priority Cfg */ 161 #define MVNETA_TQTBC_V1 0x24e0 /* Transmit Queue Token-Bucket Cfg */ 162 #define MVNETA_MTU_V1 0x24e8 /* MTU */ 163 #define MVNETA_PMTBS_V1 0x24ec /* Port Max Token-Bucket Size */ 164 #define MVNETA_TQTBCOUNT_V1(q) (0x2700 + ((q) << 4)) 165 /* Transmit Queue Token-Bucket Counter */ 166 #define MVNETA_TQTBCONFIG_V1(q) (0x2704 + ((q) << 4)) 167 /* Transmit Queue Token-Bucket Configuration */ 168 #define MVNETA_PTTBC_V1 0x2740 /* Port Transmit Backet Counter */ 169 170 /* Tx DMA Queue Arbiter Registers (Version 3) */ 171 #define MVNETA_TQC1_V3 0x3e00 /* Transmit Queue Command1 */ 172 #define MVNETA_TQFPC_V3 0x3e04 /* Transmit Queue Fixed Priority Cfg */ 173 #define MVNETA_BRC_V3 0x3e08 /* Basic Refill No of Clocks */ 174 #define MVNETA_MTU_V3 0x3e0c /* MTU */ 175 #define MVNETA_PREFILL_V3 0x3e10 /* Port Backet Refill */ 176 #define MVNETA_PMTBS_V3 0x3e14 /* Port Max Token-Bucket Size */ 177 #define MVNETA_QREFILL_V3(q) (0x3e20 + ((q) << 2)) 178 /* Transmit Queue Refill */ 179 #define MVNETA_QMTBS_V3(q) (0x3e40 + ((q) << 2)) 180 /* Transmit Queue Max Token-Bucket Size */ 181 #define MVNETA_QTTBC_V3(q) (0x3e60 + ((q) << 2)) 182 /* Transmit Queue Token-Bucket Counter */ 183 #define MVNETA_TQAC_V3(q) (0x3e80 + ((q) << 2)) 184 /* Transmit Queue Arbiter Cfg */ 185 #define MVNETA_TQIPG_V3(q) (0x3ea0 + ((q) << 2)) 186 /* Transmit Queue IPG(valid q=2..3) */ 187 #define MVNETA_HITKNINLOPKT_V3 0x3eb0 /* High Token in Low Packet */ 188 #define MVNETA_HITKNINASYNCPKT_V3 0x3eb4 /* High Token in Async Packet */ 189 #define MVNETA_LOTKNINASYNCPKT_V3 0x3eb8 /* Low Token in Async Packet */ 190 #define MVNETA_TS_V3 0x3ebc /* Token Speed */ 191 192 /* RX_TX DMA Registers */ 193 #define MVNETA_PXC 0x2400 /* Port Configuration */ 194 #define MVNETA_PXCX 0x2404 /* Port Configuration Extend */ 195 #define MVNETA_MH 0x2454 /* Marvell Header */ 196 197 /* Serial(SMI/MII) Registers */ 198 #define MVNETA_PSC0 0x243c /* Port Serial Control0 */ 199 #define MVNETA_PS0 0x2444 /* Ethernet Port Status */ 200 #define MVNETA_PSERDESCFG 0x24a0 /* Serdes Configuration */ 201 #define MVNETA_PSERDESSTS 0x24a4 /* Serdes Status */ 202 #define MVNETA_PSOMSCD 0x24f4 /* One mS Clock Divider */ 203 #define MVNETA_PSPFCCD 0x24f8 /* Periodic Flow Control Clock Divider*/ 204 205 /* Gigabit Ethernet MAC Serial Parameters Configuration Registers */ 206 #define MVNETA_PSPC 0x2c14 /* Port Serial Parameters Config */ 207 #define MVNETA_PSP1C 0x2c94 /* Port Serial Parameters 1 Config */ 208 209 /* Gigabit Ethernet Auto-Negotiation Configuration Registers */ 210 #define MVNETA_PANC 0x2c0c /* Port Auto-Negotiation Configuration*/ 211 212 /* Gigabit Ethernet MAC Control Registers */ 213 #define MVNETA_PMACC0 0x2c00 /* Port MAC Control 0 */ 214 #define MVNETA_PMACC1 0x2c04 /* Port MAC Control 1 */ 215 #define MVNETA_PMACC2 0x2c08 /* Port MAC Control 2 */ 216 #define MVNETA_PMACC3 0x2c48 /* Port MAC Control 3 */ 217 #define MVNETA_CCFCPST(p) (0x2c58 + ((p) << 2)) /*CCFC Port Speed Timerp*/ 218 #define MVNETA_PMACC4 0x2c90 /* Port MAC Control 4 */ 219 220 /* Gigabit Ethernet MAC Interrupt Registers */ 221 #define MVNETA_PIC 0x2c20 222 #define MVNETA_PIM 0x2c24 223 224 /* Gigabit Ethernet Low Power Idle Registers */ 225 #define MVNETA_LPIC0 0x2cc0 /* LowPowerIdle control 0 */ 226 #define MVNETA_LPIC1 0x2cc4 /* LPI control 1 */ 227 #define MVNETA_LPIC2 0x2cc8 /* LPI control 2 */ 228 #define MVNETA_LPIS 0x2ccc /* LPI status */ 229 #define MVNETA_LPIC 0x2cd0 /* LPI counter */ 230 231 /* Gigabit Ethernet MAC PRBS Check Status Registers */ 232 #define MVNETA_PPRBSS 0x2c38 /* Port PRBS Status */ 233 #define MVNETA_PPRBSEC 0x2c3c /* Port PRBS Error Counter */ 234 235 /* Gigabit Ethernet MAC Status Registers */ 236 #define MVNETA_PSR 0x2c10 /* Port Status Register0 */ 237 238 /* Networking Controller Interrupt Registers */ 239 #define MVNETA_PCP2Q(cpu) (0x2540 + ((cpu) << 2)) 240 #define MVNETA_PRXITTH(q) (0x2580 + ((q) << 2)) 241 /* Port Rx Interrupt Threshold */ 242 #define MVNETA_PRXTXTIC 0x25a0 /*Port RX_TX Threshold Interrupt Cause*/ 243 #define MVNETA_PRXTXTIM 0x25a4 /*Port RX_TX Threshold Interrupt Mask */ 244 #define MVNETA_PRXTXIC 0x25a8 /* Port RX_TX Interrupt Cause */ 245 #define MVNETA_PRXTXIM 0x25ac /* Port RX_TX Interrupt Mask */ 246 #define MVNETA_PMIC 0x25b0 /* Port Misc Interrupt Cause */ 247 #define MVNETA_PMIM 0x25b4 /* Port Misc Interrupt Mask */ 248 #define MVNETA_PIE 0x25b8 /* Port Interrupt Enable */ 249 #define MVNETA_PSNPCFG 0x25e4 /* Port Snoop Config */ 250 #define MVNETA_PSNPCFG_DESCSNP_MASK (0x3 << 4) 251 #define MVNETA_PSNPCFG_BUFSNP_MASK (0x3 << 8) 252 253 /* Miscellaneous Interrupt Registers */ 254 #define MVNETA_PEUIAE 0x2494 /* Port Internal Address Error */ 255 256 /* SGMII PHY Registers */ 257 #define MVNETA_PPLLC 0x2e04 /* Power and PLL Control */ 258 #define MVNETA_TESTC0 0x2e54 /* PHY Test Control 0 */ 259 #define MVNETA_TESTPRBSEC0 0x2e7c /* PHY Test PRBS Error Counter 0 */ 260 #define MVNETA_TESTPRBSEC1 0x2e80 /* PHY Test PRBS Error Counter 1 */ 261 #define MVNETA_TESTOOB0 0x2e84 /* PHY Test OOB 0 */ 262 #define MVNETA_DLE 0x2e8c /* Digital Loopback Enable */ 263 #define MVNETA_RCS 0x2f18 /* Reference Clock Select */ 264 #define MVNETA_COMPHYC 0x2f18 /* COMPHY Control */ 265 266 /* 267 * Ethernet MAC MIB Registers 268 * GbE0 BASE 0x00007.3000 269 * GbE1 BASE 0x00007.7000 270 */ 271 /* MAC MIB Counters 0x3000 - 0x307c */ 272 #define MVNETA_PORTMIB_BASE 0x3000 273 #define MVNETA_PORTMIB_SIZE 0x0080 274 #define MVNETA_PORTMIB_NOCOUNTER 30 275 276 /* Rx */ 277 #define MVNETA_MIB_RX_GOOD_OCT 0x00 /* 64bit */ 278 #define MVNETA_MIB_RX_BAD_OCT 0x08 279 #define MVNETA_MIB_RX_GOOD_FRAME 0x10 280 #define MVNETA_MIB_RX_BAD_FRAME 0x14 281 #define MVNETA_MIB_RX_BCAST_FRAME 0x18 282 #define MVNETA_MIB_RX_MCAST_FRAME 0x1c 283 #define MVNETA_MIB_RX_FRAME64_OCT 0x20 284 #define MVNETA_MIB_RX_FRAME127_OCT 0x24 285 #define MVNETA_MIB_RX_FRAME255_OCT 0x28 286 #define MVNETA_MIB_RX_FRAME511_OCT 0x2c 287 #define MVNETA_MIB_RX_FRAME1023_OCT 0x30 288 #define MVNETA_MIB_RX_FRAMEMAX_OCT 0x34 289 290 /* Tx */ 291 #define MVNETA_MIB_TX_MAC_TRNS_ERR 0x0c 292 #define MVNETA_MIB_TX_GOOD_OCT 0x38 /* 64bit */ 293 #define MVNETA_MIB_TX_GOOD_FRAME 0x40 294 #define MVNETA_MIB_TX_EXCES_COL 0x44 295 #define MVNETA_MIB_TX_MCAST_FRAME 0x48 296 #define MVNETA_MIB_TX_BCAST_FRAME 0x4c 297 #define MVNETA_MIB_TX_MAC_CTL_ERR 0x50 298 299 /* Flow Control */ 300 #define MVNETA_MIB_FC_SENT 0x54 301 #define MVNETA_MIB_FC_GOOD 0x58 302 #define MVNETA_MIB_FC_BAD 0x5c 303 304 /* Packet Processing */ 305 #define MVNETA_MIB_PKT_UNDERSIZE 0x60 306 #define MVNETA_MIB_PKT_FRAGMENT 0x64 307 #define MVNETA_MIB_PKT_OVERSIZE 0x68 308 #define MVNETA_MIB_PKT_JABBER 0x6c 309 310 /* MAC Layer Errors */ 311 #define MVNETA_MIB_MAC_RX_ERR 0x70 312 #define MVNETA_MIB_MAC_CRC_ERR 0x74 313 #define MVNETA_MIB_MAC_COL 0x78 314 #define MVNETA_MIB_MAC_LATE_COL 0x7c 315 316 /* END OF REGISTER NUMBERS */ 317 318 /* 319 * 320 * Register Formats 321 * 322 */ 323 /* 324 * Address Decoder Registers 325 */ 326 /* Base Address (MVNETA_BASEADDR) */ 327 #define MVNETA_BASEADDR_TARGET(target) ((target) & 0xf) 328 #define MVNETA_BASEADDR_ATTR(attr) (((attr) & 0xff) << 8) 329 #define MVNETA_BASEADDR_BASE(base) ((base) & 0xffff0000) 330 331 /* Size (MVNETA_S) */ 332 #define MVNETA_S_SIZE(size) (((size) - 1) & 0xffff0000) 333 334 /* Base Address Enable (MVNETA_BARE) */ 335 #define MVNETA_BARE_EN_MASK ((1 << MVNETA_NWINDOW) - 1) 336 #define MVNETA_BARE_EN(win) ((1 << (win)) & MVNETA_BARE_EN_MASK) 337 338 /* Ethernet Port Access Protect (MVNETA_EPAP) */ 339 #define MVNETA_EPAP_AC_NAC 0x0 /* No access allowed */ 340 #define MVNETA_EPAP_AC_RO 0x1 /* Read Only */ 341 #define MVNETA_EPAP_AC_FA 0x3 /* Full access (r/w) */ 342 #define MVNETA_EPAP_EPAR(win, ac) ((ac) << ((win) * 2)) 343 344 /* 345 * Global Miscellaneous Registers 346 */ 347 /* PHY Address (MVNETA_PHYADDR) */ 348 #define MVNETA_PHYADDR_PHYAD(phy) ((phy) & 0x1f) 349 #define MVNETA_PHYADDR_GET_PHYAD(reg) ((reg) & 0x1f) 350 351 /* SMI register fields (MVNETA_SMI) */ 352 #define MVNETA_SMI_DATA_MASK 0x0000ffff 353 #define MVNETA_SMI_PHYAD(phy) (((phy) & 0x1f) << 16) 354 #define MVNETA_SMI_REGAD(reg) (((reg) & 0x1f) << 21) 355 #define MVNETA_SMI_OPCODE_WRITE (0 << 26) 356 #define MVNETA_SMI_OPCODE_READ (1 << 26) 357 #define MVNETA_SMI_READVALID (1 << 27) 358 #define MVNETA_SMI_BUSY (1 << 28) 359 360 /* Ethernet Unit Default ID (MVNETA_EUDID) */ 361 #define MVNETA_EUDID_DIDR_MASK 0x0000000f 362 #define MVNETA_EUDID_DIDR(id) ((id) & 0x0f) 363 #define MVNETA_EUDID_DATTR_MASK 0x00000ff0 364 #define MVNETA_EUDID_DATTR(attr) (((attr) & 0xff) << 4) 365 366 /* Ethernet Unit Interrupt Cause (MVNETA_EUIC) */ 367 #define MVNETA_EUIC_ETHERINTSUM (1 << 0) 368 #define MVNETA_EUIC_PARITY (1 << 1) 369 #define MVNETA_EUIC_ADDRVIOL (1 << 2) 370 #define MVNETA_EUIC_ADDRVNOMATCH (1 << 3) 371 #define MVNETA_EUIC_SMIDONE (1 << 4) 372 #define MVNETA_EUIC_COUNTWA (1 << 5) 373 #define MVNETA_EUIC_INTADDRERR (1 << 7) 374 #define MVNETA_EUIC_PORT0DPERR (1 << 9) 375 #define MVNETA_EUIC_TOPDPERR (1 << 12) 376 377 /* Ethernet Unit Internal Addr Error (MVNETA_EUIAE) */ 378 #define MVNETA_EUIAE_INTADDR_MASK 0x000001ff 379 #define MVNETA_EUIAE_INTADDR(addr) ((addr) & 0x1ff) 380 #define MVNETA_EUIAE_GET_INTADDR(addr) ((addr) & 0x1ff) 381 382 /* Ethernet Unit Control (MVNETA_EUC) */ 383 #define MVNETA_EUC_POLLING (1 << 1) 384 #define MVNETA_EUC_PORTRESET (1 << 24) 385 #define MVNETA_EUC_RAMSINITIALIZATIONCOMPLETED (1 << 25) 386 387 /* 388 * Miscellaneous Registers 389 */ 390 /* SDMA Configuration (MVNETA_SDC) */ 391 #define MVNETA_SDC_RXBSZ(x) ((x) << 1) 392 #define MVNETA_SDC_RXBSZ_MASK MVNETA_SDC_RXBSZ(7) 393 #define MVNETA_SDC_RXBSZ_1_64BITWORDS MVNETA_SDC_RXBSZ(0) 394 #define MVNETA_SDC_RXBSZ_2_64BITWORDS MVNETA_SDC_RXBSZ(1) 395 #define MVNETA_SDC_RXBSZ_4_64BITWORDS MVNETA_SDC_RXBSZ(2) 396 #define MVNETA_SDC_RXBSZ_8_64BITWORDS MVNETA_SDC_RXBSZ(3) 397 #define MVNETA_SDC_RXBSZ_16_64BITWORDS MVNETA_SDC_RXBSZ(4) 398 #define MVNETA_SDC_BLMR (1 << 4) 399 #define MVNETA_SDC_BLMT (1 << 5) 400 #define MVNETA_SDC_SWAPMODE (1 << 6) 401 #define MVNETA_SDC_TXBSZ(x) ((x) << 22) 402 #define MVNETA_SDC_TXBSZ_MASK MVNETA_SDC_TXBSZ(7) 403 #define MVNETA_SDC_TXBSZ_1_64BITWORDS MVNETA_SDC_TXBSZ(0) 404 #define MVNETA_SDC_TXBSZ_2_64BITWORDS MVNETA_SDC_TXBSZ(1) 405 #define MVNETA_SDC_TXBSZ_4_64BITWORDS MVNETA_SDC_TXBSZ(2) 406 #define MVNETA_SDC_TXBSZ_8_64BITWORDS MVNETA_SDC_TXBSZ(3) 407 #define MVNETA_SDC_TXBSZ_16_64BITWORDS MVNETA_SDC_TXBSZ(4) 408 409 /* 410 * Networking Controller Miscellaneous Registers 411 */ 412 /* Port Acceleration Mode (MVNETA_PACC) */ 413 #define MVNETA_PACC_ACCELERATIONMODE_MASK 0x7 414 #define MVNETA_PACC_ACCELERATIONMODE_EDM 0x1 /* Enhanced Desc Mode */ 415 416 /* Port Version (MVNETA_PV) */ 417 #define MVNETA_PV_VERSION_MASK 0xff 418 #define MVNETA_PV_VERSION(v) ((v) & 0xff) 419 #define MVNETA_PV_GET_VERSION(reg) ((reg) & 0xff) 420 421 /* 422 * Rx DMA Hardware Parser Registers 423 */ 424 /* Ether Type Priority (MVNETA_ETP) */ 425 #define MVNETA_ETP_ETHERTYPEPRIEN (1 << 0) /* EtherType Prio Ena */ 426 #define MVNETA_ETP_ETHERTYPEPRIFRSTEN (1 << 1) 427 #define MVNETA_ETP_ETHERTYPEPRIQ (0x7 << 2) /*EtherType Prio Queue*/ 428 #define MVNETA_ETP_ETHERTYPEPRIVAL (0xffff << 5) /*EtherType Prio Value*/ 429 #define MVNETA_ETP_FORCEUNICSTHIT (1 << 21) /* Force Unicast hit */ 430 431 /* Destination Address Filter Registers (MVNETA_DF{SM,OM,U}T) */ 432 #define MVNETA_DF(n, x) ((x) << (8 * (n))) 433 #define MVNETA_DF_PASS (1 << 0) 434 #define MVNETA_DF_QUEUE(q) ((q) << 1) 435 #define MVNETA_DF_QUEUE_ALL ((MVNETA_RX_QNUM_MAX-1) << 1) 436 #define MVNETA_DF_QUEUE_MASK ((MVNETA_RX_QNUM_MAX-1) << 1) 437 438 /* 439 * Rx DMA Miscellaneous Registers 440 */ 441 /* Port Rx Minimal Frame Size (MVNETA_PMFS) */ 442 #define MVNETA_PMFS_RXMFS(rxmfs) (((rxmfs) - 40) & 0x7c) 443 444 /* Receive Queue Command (MVNETA_RQC) */ 445 #define MVNETA_RQC_EN_MASK (0xff << 0) /* Enable Q */ 446 #define MVNETA_RQC_ENQ(q) (1 << (0 + (q))) 447 #define MVNETA_RQC_EN(n) ((n) << 0) 448 #define MVNETA_RQC_DIS_MASK (0xff << 8) /* Disable Q */ 449 #define MVNETA_RQC_DISQ(q) (1 << (8 + (q))) 450 #define MVNETA_RQC_DIS(n) ((n) << 8) 451 452 /* 453 * Rx DMA Networking Controller Miscellaneous Registers 454 */ 455 /* Port RX queues Configuration (MVNETA_PRXC) */ 456 #define MVNETA_PRXC_PACKETOFFSET(o) (((o) & 0xf) << 8) 457 458 /* Port RX queues Snoop (MVNETA_PRXSNP) */ 459 #define MVNETA_PRXSNP_SNOOPNOOFBYTES(b) (((b) & 0x3fff) << 0) 460 #define MVNETA_PRXSNP_L2DEPOSITNOOFBYTES(b) (((b) & 0x3fff) << 16) 461 462 /* Port RX queues Descriptors Queue Size (MVNETA_PRXDQS) */ 463 #define MVNETA_PRXDQS_DESCRIPTORSQUEUESIZE(s) (((s) & 0x3fff) << 0) 464 #define MVNETA_PRXDQS_BUFFERSIZE(s) (((s) & 0x1fff) << 19) 465 466 /* Port RX queues Descriptors Queue Threshold (MVNETA_PRXDQTH) */ 467 /* Occupied Descriptors Threshold */ 468 #define MVNETA_PRXDQTH_ODT(x) (((x) & 0x3fff) << 0) 469 /* Non Occupied Descriptors Threshold */ 470 #define MVNETA_PRXDQTH_NODT(x) (((x) & 0x3fff) << 16) 471 472 /* Port RX queues Status (MVNETA_PRXS) */ 473 /* Occupied Descriptors Counter */ 474 #define MVNETA_PRXS_ODC(x) (((x) & 0x3fff) << 0) 475 /* Non Occupied Descriptors Counter */ 476 #define MVNETA_PRXS_NODC(x) (((x) & 0x3fff) << 16) 477 #define MVNETA_PRXS_GET_ODC(reg) (((reg) >> 0) & 0x3fff) 478 #define MVNETA_PRXS_GET_NODC(reg) (((reg) >> 16) & 0x3fff) 479 480 /* Port RX queues Status Update (MVNETA_PRXSU) */ 481 #define MVNETA_PRXSU_NOOFPROCESSEDDESCRIPTORS(x) (((x) & 0xff) << 0) 482 #define MVNETA_PRXSU_NOOFNEWDESCRIPTORS(x) (((x) & 0xff) << 16) 483 484 /* Port RX Initialization (MVNETA_PRXINIT) */ 485 #define MVNETA_PRXINIT_RXDMAINIT (1 << 0) 486 487 /* 488 * Tx DMA Miscellaneous Registers 489 */ 490 /* Transmit Queue Command (MVNETA_TQC) */ 491 #define MVNETA_TQC_EN_MASK (0xff << 0) 492 #define MVNETA_TQC_ENQ(q) (1 << ((q) + 0))/* Enable Q */ 493 #define MVNETA_TQC_EN(n) ((n) << 0) 494 #define MVNETA_TQC_DIS_MASK (0xff << 8) 495 #define MVNETA_TQC_DISQ(q) (1 << ((q) + 8))/* Disable Q */ 496 #define MVNETA_TQC_DIS(n) ((n) << 8) 497 498 /* 499 * Tx DMA Networking Controller Miscellaneous Registers 500 */ 501 /* Port TX queues Descriptors Queue Size (MVNETA_PTXDQS) */ 502 /* Descriptors Queue Size */ 503 #define MVNETA_PTXDQS_DQS_MASK (0x3fff << 0) 504 #define MVNETA_PTXDQS_DQS(x) (((x) & 0x3fff) << 0) 505 /* Transmitted Buffer Threshold */ 506 #define MVNETA_PTXDQS_TBT_MASK (0x3fff << 16) 507 #define MVNETA_PTXDQS_TBT(x) (((x) & 0x3fff) << 16) 508 509 /* Port TX queues Status (MVNETA_PTXS) */ 510 /* Transmitted Buffer Counter */ 511 #define MVNETA_PTXS_TBC(x) (((x) & 0x3fff) << 16) 512 513 #define MVNETA_PTXS_GET_TBC(reg) (((reg) >> 16) & 0x3fff) 514 /* Pending Descriptors Counter */ 515 #define MVNETA_PTXS_PDC(x) ((x) & 0x3fff) 516 #define MVNETA_PTXS_GET_PDC(x) ((x) & 0x3fff) 517 518 /* Port TX queues Status Update (MVNETA_PTXSU) */ 519 /* Number Of Written Descriptors */ 520 #define MVNETA_PTXSU_NOWD(x) (((x) & 0xff) << 0) 521 /* Number Of Released Buffers */ 522 #define MVNETA_PTXSU_NORB(x) (((x) & 0xff) << 16) 523 524 /* TX Transmitted Buffers Counter (MVNETA_TXTBC) */ 525 /* Transmitted Buffers Counter */ 526 #define MVNETA_TXTBC_TBC(x) (((x) & 0x3fff) << 16) 527 528 /* Port TX Initialization (MVNETA_PTXINIT) */ 529 #define MVNETA_PTXINIT_TXDMAINIT (1 << 0) 530 531 /* 532 * Tx DMA Queue Arbiter Registers (Version 1 ) 533 */ 534 /* Transmit Queue Fixed Priority Configuration */ 535 #define MVNETA_TQFPC_EN(q) (1 << (q)) 536 537 /* 538 * RX_TX DMA Registers 539 */ 540 /* Port Configuration (MVNETA_PXC) */ 541 #define MVNETA_PXC_UPM (1 << 0) /* Uni Promisc mode */ 542 #define MVNETA_PXC_RXQ(q) ((q) << 1) 543 #define MVNETA_PXC_RXQ_MASK MVNETA_PXC_RXQ(7) 544 #define MVNETA_PXC_RXQARP(q) ((q) << 4) 545 #define MVNETA_PXC_RXQARP_MASK MVNETA_PXC_RXQARP(7) 546 #define MVNETA_PXC_RB (1 << 7) /* Rej mode of MAC */ 547 #define MVNETA_PXC_RBIP (1 << 8) 548 #define MVNETA_PXC_RBARP (1 << 9) 549 #define MVNETA_PXC_AMNOTXES (1 << 12) 550 #define MVNETA_PXC_RBARPF (1 << 13) 551 #define MVNETA_PXC_TCPCAPEN (1 << 14) 552 #define MVNETA_PXC_UDPCAPEN (1 << 15) 553 #define MVNETA_PXC_TCPQ(q) ((q) << 16) 554 #define MVNETA_PXC_TCPQ_MASK MVNETA_PXC_TCPQ(7) 555 #define MVNETA_PXC_UDPQ(q) ((q) << 19) 556 #define MVNETA_PXC_UDPQ_MASK MVNETA_PXC_UDPQ(7) 557 #define MVNETA_PXC_BPDUQ(q) ((q) << 22) 558 #define MVNETA_PXC_BPDUQ_MASK MVNETA_PXC_BPDUQ(7) 559 #define MVNETA_PXC_RXCS (1 << 25) 560 561 /* Port Configuration Extend (MVNETA_PXCX) */ 562 #define MVNETA_PXCX_SPAN (1 << 1) 563 #define MVNETA_PXCX_TXCRCDIS (1 << 3) 564 565 /* Marvell Header (MVNETA_MH) */ 566 #define MVNETA_MH_MHEN (1 << 0) 567 #define MVNETA_MH_DAPREFIX (0x3 << 1) 568 #define MVNETA_MH_SPID (0xf << 4) 569 #define MVNETA_MH_MHMASK (0x3 << 8) 570 #define MVNETA_MH_MHMASK_8QUEUES (0x0 << 8) 571 #define MVNETA_MH_MHMASK_4QUEUES (0x1 << 8) 572 #define MVNETA_MH_MHMASK_2QUEUES (0x3 << 8) 573 #define MVNETA_MH_DSAEN_MASK (0x3 << 10) 574 #define MVNETA_MH_DSAEN_DISABLE (0x0 << 10) 575 #define MVNETA_MH_DSAEN_NONEXTENDED (0x1 << 10) 576 #define MVNETA_MH_DSAEN_EXTENDED (0x2 << 10) 577 578 /* 579 * Serial(SMI/MII) Registers 580 */ 581 #define MVNETA_PSOMSCD_ENABLE (1UL<<31) 582 #define MVNETA_PSERDESCFG_QSGMII (0x0667) 583 #define MVNETA_PSERDESCFG_SGMII (0x0cc7) 584 /* Port Seiral Control0 (MVNETA_PSC0) */ 585 #define MVNETA_PSC0_FORCE_FC_MASK (0x3 << 5) 586 #define MVNETA_PSC0_FORCE_FC(fc) (((fc) & 0x3) << 5) 587 #define MVNETA_PSC0_FORCE_FC_PAUSE MVNETA_PSC0_FORCE_FC(0x1) 588 #define MVNETA_PSC0_FORCE_FC_NO_PAUSE MVNETA_PSC0_FORCE_FC(0x0) 589 #define MVNETA_PSC0_FORCE_BP_MASK (0x3 << 7) 590 #define MVNETA_PSC0_FORCE_BP(fc) (((fc) & 0x3) << 5) 591 #define MVNETA_PSC0_FORCE_BP_JAM MVNETA_PSC0_FORCE_BP(0x1) 592 #define MVNETA_PSC0_FORCE_BP_NO_JAM MVNETA_PSC0_FORCE_BP(0x0) 593 #define MVNETA_PSC0_DTE_ADV (1 << 14) 594 #define MVNETA_PSC0_IGN_RXERR (1 << 28) 595 #define MVNETA_PSC0_IGN_COLLISION (1 << 29) 596 #define MVNETA_PSC0_IGN_CARRIER (1 << 30) 597 598 /* Ethernet Port Status0 (MVNETA_PS0) */ 599 #define MVNETA_PS0_TXINPROG (1 << 0) 600 #define MVNETA_PS0_TXFIFOEMP (1 << 8) 601 #define MVNETA_PS0_RXFIFOEMPTY (1 << 16) 602 603 /* 604 * Gigabit Ethernet MAC Serial Parameters Configuration Registers 605 */ 606 #define MVNETA_PSPC_MUST_SET (1 << 3 | 1 << 4 | 1 << 5 | 0x23 << 6) 607 #define MVNETA_PSP1C_MUST_SET (1 << 0 | 1 << 1 | 1 << 2) 608 609 /* 610 * Gigabit Ethernet Auto-Negotiation Configuration Registers 611 */ 612 /* Port Auto-Negotiation Configuration (MVNETA_PANC) */ 613 #define MVNETA_PANC_FORCELINKFAIL (1 << 0) 614 #define MVNETA_PANC_FORCELINKPASS (1 << 1) 615 #define MVNETA_PANC_INBANDANEN (1 << 2) 616 #define MVNETA_PANC_INBANDANBYPASSEN (1 << 3) 617 #define MVNETA_PANC_INBANDRESTARTAN (1 << 4) 618 #define MVNETA_PANC_SETMIISPEED (1 << 5) 619 #define MVNETA_PANC_SETGMIISPEED (1 << 6) 620 #define MVNETA_PANC_ANSPEEDEN (1 << 7) 621 #define MVNETA_PANC_SETFCEN (1 << 8) 622 #define MVNETA_PANC_PAUSEADV (1 << 9) 623 #define MVNETA_PANC_ANFCEN (1 << 11) 624 #define MVNETA_PANC_SETFULLDX (1 << 12) 625 #define MVNETA_PANC_ANDUPLEXEN (1 << 13) 626 #define MVNETA_PANC_MUSTSET (1 << 15) 627 628 /* 629 * Gigabit Ethernet MAC Control Registers 630 */ 631 /* Port MAC Control 0 (MVNETA_PMACC0) */ 632 #define MVNETA_PMACC0_PORTEN (1 << 0) 633 #define MVNETA_PMACC0_PORTTYPE (1 << 1) 634 #define MVNETA_PMACC0_FRAMESIZELIMIT(x) ((((x) >> 1) << 2) & 0x7ffc) 635 #define MVNETA_PMACC0_FRAMESIZELIMIT_MASK (0x7ffc) 636 #define MVNETA_PMACC0_MUSTSET (1 << 15) 637 638 /* Port MAC Control 1 (MVNETA_PMACC1) */ 639 #define MVNETA_PMACC1_PCSLB (1 << 6) 640 641 /* Port MAC Control 2 (MVNETA_PMACC2) */ 642 #define MVNETA_PMACC2_INBANDANMODE (1 << 0) 643 #define MVNETA_PMACC2_PCSEN (1 << 3) 644 #define MVNETA_PMACC2_PCSEN (1 << 3) 645 #define MVNETA_PMACC2_RGMIIEN (1 << 4) 646 #define MVNETA_PMACC2_PADDINGDIS (1 << 5) 647 #define MVNETA_PMACC2_PORTMACRESET (1 << 6) 648 #define MVNETA_PMACC2_PRBSCHECKEN (1 << 10) 649 #define MVNETA_PMACC2_PRBSGENEN (1 << 11) 650 #define MVNETA_PMACC2_SDTT_MASK (3 << 12) /* Select Data To Transmit */ 651 #define MVNETA_PMACC2_SDTT_RM (0 << 12) /* Regular Mode */ 652 #define MVNETA_PMACC2_SDTT_PRBS (1 << 12) /* PRBS Mode */ 653 #define MVNETA_PMACC2_SDTT_ZC (2 << 12) /* Zero Constant */ 654 #define MVNETA_PMACC2_SDTT_OC (3 << 12) /* One Constant */ 655 #define MVNETA_PMACC2_MUSTSET (3 << 14) 656 657 /* Port MAC Control 3 (MVNETA_PMACC3) */ 658 #define MVNETA_PMACC3_IPG_MASK 0x7f80 659 660 /* 661 * Gigabit Ethernet MAC Interrupt Registers 662 */ 663 /* Port Interrupt Cause/Mask (MVNETA_PIC/MVNETA_PIM) */ 664 #define MVNETA_PI_INTSUM (1 << 0) 665 #define MVNETA_PI_LSC (1 << 1) /* LinkStatus Change */ 666 #define MVNETA_PI_ACOP (1 << 2) /* AnCompleted OnPort */ 667 #define MVNETA_PI_AOOR (1 << 5) /* AddressOut Of Range */ 668 #define MVNETA_PI_SSC (1 << 6) /* SyncStatus Change */ 669 #define MVNETA_PI_PRBSEOP (1 << 7) /* QSGMII PRBS error */ 670 #define MVNETA_PI_MIBCWA (1 << 15) /* MIB counter wrap around */ 671 #define MVNETA_PI_QSGMIIPRBSE (1 << 10) /* QSGMII PRBS error */ 672 #define MVNETA_PI_PCSRXPRLPI (1 << 11) /* PCS Rx path received LPI*/ 673 #define MVNETA_PI_PCSTXPRLPI (1 << 12) /* PCS Tx path received LPI*/ 674 #define MVNETA_PI_MACRXPRLPI (1 << 13) /* MAC Rx path received LPI*/ 675 #define MVNETA_PI_MIBCCD (1 << 14) /* MIB counters copy done */ 676 677 /* 678 * Gigabit Ethernet MAC Low Power Idle Registers 679 */ 680 /* LPI Control 0 (MVNETA_LPIC0) */ 681 #define MVNETA_LPIC0_LILIMIT(x) (((x) & 0xff) << 0) 682 #define MVNETA_LPIC0_TSLIMIT(x) (((x) & 0xff) << 8) 683 684 /* LPI Control 1 (MVNETA_LPIC1) */ 685 #define MVNETA_LPIC1_LPIRE (1 << 0) /* LPI request enable */ 686 #define MVNETA_LPIC1_LPIRF (1 << 1) /* LPI request force */ 687 #define MVNETA_LPIC1_LPIMM (1 << 2) /* LPI manual mode */ 688 #define MVNETA_LPIC1_TWLIMIT(x) (((x) & 0xfff) << 4) 689 690 /* LPI Control 2 (MVNETA_LPIC2) */ 691 #define MVNETA_LPIC2_MUSTSET 0x17d 692 693 /* LPI Status (MVNETA_LPIS) */ 694 #define MVNETA_LPIS_PCSRXPLPIS (1 << 0) /* PCS Rx path LPI status */ 695 #define MVNETA_LPIS_PCSTXPLPIS (1 << 1) /* PCS Tx path LPI status */ 696 #define MVNETA_LPIS_MACRXPLPIS (1 << 2)/* MAC Rx path LP idle status */ 697 #define MVNETA_LPIS_MACTXPLPWS (1 << 3)/* MAC Tx path LP wait status */ 698 #define MVNETA_LPIS_MACTXPLPIS (1 << 4)/* MAC Tx path LP idle status */ 699 700 /* 701 * Gigabit Ethernet MAC PRBS Check Status Registers 702 */ 703 /* Port PRBS Status (MVNETA_PPRBSS) */ 704 #define MVNETA_PPRBSS_PRBSCHECKLOCKED (1 << 0) 705 #define MVNETA_PPRBSS_PRBSCHECKRDY (1 << 1) 706 707 /* 708 * Gigabit Ethernet MAC Status Registers 709 */ 710 /* Port Status Register (MVNETA_PSR) */ 711 #define MVNETA_PSR_LINKUP (1 << 0) 712 #define MVNETA_PSR_GMIISPEED (1 << 1) 713 #define MVNETA_PSR_MIISPEED (1 << 2) 714 #define MVNETA_PSR_FULLDX (1 << 3) 715 #define MVNETA_PSR_RXFCEN (1 << 4) 716 #define MVNETA_PSR_TXFCEN (1 << 5) 717 #define MVNETA_PSR_PRP (1 << 6) /* Port Rx Pause */ 718 #define MVNETA_PSR_PTP (1 << 7) /* Port Tx Pause */ 719 #define MVNETA_PSR_PDP (1 << 8) /*Port is Doing Back-Pressure*/ 720 #define MVNETA_PSR_SYNCFAIL10MS (1 << 10) 721 #define MVNETA_PSR_ANDONE (1 << 11) 722 #define MVNETA_PSR_IBANBA (1 << 12) /* InBand AutoNeg BypassAct */ 723 #define MVNETA_PSR_SYNCOK (1 << 14) 724 725 /* 726 * Networking Controller Interrupt Registers 727 */ 728 /* Port CPU to Queue */ 729 #define MVNETA_MAXCPU 2 730 #define MVNETA_PCP2Q_TXQEN(q) (1 << ((q) + 8)) 731 #define MVNETA_PCP2Q_TXQEN_MASK (0xff << 8) 732 #define MVNETA_PCP2Q_RXQEN(q) (1 << ((q) + 0)) 733 #define MVNETA_PCP2Q_RXQEN_MASK (0xff << 0) 734 735 /* Port RX_TX Interrupt Threshold */ 736 #define MVNETA_PRXITTH_RITT(t) ((t) & 0xffffff) 737 738 /* Port RX_TX Threshold Interrupt Cause/Mask (MVNETA_PRXTXTIC/MVNETA_PRXTXTIM) */ 739 #define MVNETA_PRXTXTI_TBTCQ(q) (1 << ((q) + 0)) 740 #define MVNETA_PRXTXTI_TBTCQ_MASK (0xff << 0) 741 #define MVNETA_PRXTXTI_GET_TBTCQ(reg) (((reg) >> 0) & 0xff) 742 /* Tx Buffer Threshold Cross Queue*/ 743 #define MVNETA_PRXTXTI_RBICTAPQ(q) (1 << ((q) + 8)) 744 #define MVNETA_PRXTXTI_RBICTAPQ_MASK (0xff << 8) 745 #define MVNETA_PRXTXTI_GET_RBICTAPQ(reg) (((reg) >> 8) & 0xff) 746 /* Rx Buffer Int. Coaleasing Th. Pri. Alrt Q */ 747 #define MVNETA_PRXTXTI_RDTAQ(q) (1 << ((q) + 16)) 748 #define MVNETA_PRXTXTI_RDTAQ_MASK (0xff << 16) 749 #define MVNETA_PRXTXTI_GET_RDTAQ(reg) (((reg) >> 16) & 0xff) 750 /* Rx Descriptor Threshold Alert Queue*/ 751 #define MVNETA_PRXTXTI_PRXTXICSUMMARY (1 << 29) /* PRXTXI summary */ 752 #define MVNETA_PRXTXTI_PTXERRORSUMMARY (1 << 30) /* PTEXERROR summary */ 753 #define MVNETA_PRXTXTI_PMISCICSUMMARY (1UL << 31) /* PMISCIC summary */ 754 755 /* Port RX_TX Interrupt Cause/Mask (MVNETA_PRXTXIC/MVNETA_PRXTXIM) */ 756 #define MVNETA_PRXTXI_TBRQ(q) (1 << ((q) + 0)) 757 #define MVNETA_PRXTXI_TBRQ_MASK (0xff << 0) 758 #define MVNETA_PRXTXI_GET_TBRQ(reg) (((reg) >> 0) & 0xff) 759 #define MVNETA_PRXTXI_RPQ(q) (1 << ((q) + 8)) 760 #define MVNETA_PRXTXI_RPQ_MASK (0xff << 8) 761 #define MVNETA_PRXTXI_GET_RPQ(reg) (((reg) >> 8) & 0xff) 762 #define MVNETA_PRXTXI_RREQ(q) (1 << ((q) + 16)) 763 #define MVNETA_PRXTXI_RREQ_MASK (0xff << 16) 764 #define MVNETA_PRXTXI_GET_RREQ(reg) (((reg) >> 16) & 0xff) 765 #define MVNETA_PRXTXI_PRXTXTHICSUMMARY (1 << 29) 766 #define MVNETA_PRXTXI_PTXERRORSUMMARY (1 << 30) 767 #define MVNETA_PRXTXI_PMISCICSUMMARY (1UL << 31) 768 769 /* Port Misc Interrupt Cause/Mask (MVNETA_PMIC/MVNETA_PMIM) */ 770 #define MVNETA_PMI_PHYSTATUSCHNG (1 << 0) 771 #define MVNETA_PMI_LINKCHANGE (1 << 1) 772 #define MVNETA_PMI_IAE (1 << 7) /* Internal Address Error */ 773 #define MVNETA_PMI_RXOVERRUN (1 << 8) 774 #define MVNETA_PMI_RXCRCERROR (1 << 9) 775 #define MVNETA_PMI_RXLARGEPACKET (1 << 10) 776 #define MVNETA_PMI_TXUNDRN (1 << 11) 777 #define MVNETA_PMI_PRBSERROR (1 << 12) 778 #define MVNETA_PMI_PSCSYNCCHANGE (1 << 13) 779 #define MVNETA_PMI_SRSE (1 << 14) /* SerdesRealignSyncError */ 780 #define MVNETA_PMI_TREQ(q) (1 << ((q) + 24)) /* TxResourceErrorQ */ 781 #define MVNETA_PMI_TREQ_MASK (0xff << 24) /* TxResourceErrorQ */ 782 783 /* Port Interrupt Enable (MVNETA_PIE) */ 784 #define MVNETA_PIE_RXPKTINTRPTENB(q) (1 << ((q) + 0)) 785 #define MVNETA_PIE_TXPKTINTRPTENB(q) (1 << ((q) + 8)) 786 #define MVNETA_PIE_RXPKTINTRPTENB_MASK (0xff << 0) 787 #define MVNETA_PIE_TXPKTINTRPTENB_MASK (0xff << 8) 788 789 /* 790 * Miscellaneous Interrupt Registers 791 */ 792 #define MVNETA_PEUIAE_ADDR_MASK (0x3fff) 793 #define MVNETA_PEUIAE_ADDR(addr) ((addr) & 0x3fff) 794 #define MVNETA_PEUIAE_GET_ADDR(reg) ((reg) & 0x3fff) 795 796 /* 797 * SGMII PHY Registers 798 */ 799 /* Power and PLL Control (MVNETA_PPLLC) */ 800 #define MVNETA_PPLLC_REF_FREF_SEL_MASK (0xf << 0) 801 #define MVNETA_PPLLC_PHY_MODE_MASK (7 << 5) 802 #define MVNETA_PPLLC_PHY_MODE_SATA (0 << 5) 803 #define MVNETA_PPLLC_PHY_MODE_SAS (1 << 5) 804 #define MVNETA_PPLLC_PLL_LOCK (1 << 8) 805 #define MVNETA_PPLLC_PU_DFE (1 << 10) 806 #define MVNETA_PPLLC_PU_TX_INTP (1 << 11) 807 #define MVNETA_PPLLC_PU_TX (1 << 12) 808 #define MVNETA_PPLLC_PU_RX (1 << 13) 809 #define MVNETA_PPLLC_PU_PLL (1 << 14) 810 811 /* Digital Loopback Enable (MVNETA_DLE) */ 812 #define MVNETA_DLE_LOCAL_SEL_BITS_MASK (3 << 10) 813 #define MVNETA_DLE_LOCAL_SEL_BITS_10BITS (0 << 10) 814 #define MVNETA_DLE_LOCAL_SEL_BITS_20BITS (1 << 10) 815 #define MVNETA_DLE_LOCAL_SEL_BITS_40BITS (2 << 10) 816 #define MVNETA_DLE_LOCAL_RXPHER_TO_TX_EN (1 << 12) 817 #define MVNETA_DLE_LOCAL_ANA_TX2RX_LPBK_EN (1 << 13) 818 #define MVNETA_DLE_LOCAL_DIG_TX2RX_LPBK_EN (1 << 14) 819 #define MVNETA_DLE_LOCAL_DIG_RX2TX_LPBK_EN (1 << 15) 820 821 /* Reference Clock Select (MVNETA_RCS) */ 822 #define MVNETA_RCS_REFCLK_SEL (1 << 10) 823 824 /* 825 * DMA descriptors 826 */ 827 struct mvneta_tx_desc { 828 /* LITTLE_ENDIAN */ 829 uint32_t command; /* off 0x00: commands */ 830 uint16_t l4ichk; /* initial checksum */ 831 uint16_t bytecnt; /* 0ff 0x04: buffer byte count */ 832 uint32_t bufptr_pa; /* off 0x08: buffer ptr(PA) */ 833 uint32_t flags; /* off 0x0c: flags */ 834 uint32_t reserved0; /* off 0x10 */ 835 uint32_t reserved1; /* off 0x14 */ 836 uint32_t reserved2; /* off 0x18 */ 837 uint32_t reserved3; /* off 0x1c */ 838 }; 839 840 struct mvneta_rx_desc { 841 /* LITTLE_ENDIAN */ 842 uint32_t status; /* status and flags */ 843 uint16_t reserved0; 844 uint16_t bytecnt; /* buffer byte count */ 845 uint32_t bufptr_pa; /* packet buffer pointer */ 846 uint32_t reserved1; 847 uint32_t bufptr_va; 848 uint16_t reserved2; 849 uint16_t l4chk; /* L4 checksum */ 850 uint32_t reserved3; 851 uint32_t reserved4; 852 }; 853 854 /* 855 * Received packet command header: 856 * network controller => software 857 * the controller parse the packet and set some flags. 858 */ 859 #define MVNETA_RX_IPV4_FRAGMENT (1UL << 31) /* Fragment Indicator */ 860 #define MVNETA_RX_L4_CHECKSUM_OK (1 << 30) /* L4 Checksum */ 861 /* bit 29 reserved */ 862 #define MVNETA_RX_U (1 << 28) /* Unknown Destination */ 863 #define MVNETA_RX_F (1 << 27) /* First buffer */ 864 #define MVNETA_RX_L (1 << 26) /* Last buffer */ 865 #define MVNETA_RX_IP_HEADER_OK (1 << 25) /* IP Header is OK */ 866 #define MVNETA_RX_L3_IP (1 << 24) /* IP Type 0:IP6 1:IP4 */ 867 #define MVNETA_RX_L2_EV2 (1 << 23) /* Ethernet v2 frame */ 868 #define MVNETA_RX_L4_MASK (3 << 21) /* L4 Type */ 869 #define MVNETA_RX_L4_TCP (0x00 << 21) 870 #define MVNETA_RX_L4_UDP (0x01 << 21) 871 #define MVNETA_RX_L4_OTH (0x10 << 21) 872 #define MVNETA_RX_BPDU (1 << 20) /* BPDU frame */ 873 #define MVNETA_RX_VLAN (1 << 19) /* VLAN tag found */ 874 #define MVNETA_RX_EC_MASK (3 << 17) /* Error code */ 875 #define MVNETA_RX_EC_CE (0x00 << 17) /* CRC error */ 876 #define MVNETA_RX_EC_OR (0x01 << 17) /* FIFO overrun */ 877 #define MVNETA_RX_EC_MF (0x10 << 17) /* Max. frame len */ 878 #define MVNETA_RX_EC_RE (0x11 << 17) /* Resource error */ 879 #define MVNETA_RX_ES (1 << 16) /* Error summary */ 880 /* bit 15:0 reserved */ 881 882 /* 883 * Transmit packet command header: 884 * software => network controller 885 */ 886 #define MVNETA_TX_CMD_L4_CHECKSUM_MASK (0x3 << 30) /* Do L4 Checksum */ 887 #define MVNETA_TX_CMD_L4_CHECKSUM_FRAG (0x0 << 30) 888 #define MVNETA_TX_CMD_L4_CHECKSUM_NOFRAG (0x1 << 30) 889 #define MVNETA_TX_CMD_L4_CHECKSUM_NONE (0x2 << 30) 890 #define MVNETA_TX_CMD_PACKET_OFFSET_MASK (0x7f << 23) /* Payload offset */ 891 #define MVNETA_TX_CMD_W_PACKET_OFFSET(v) (((v) & 0x7f) << 23) 892 /* bit 22 reserved */ 893 #define MVNETA_TX_CMD_F (1 << 21) /* First buffer */ 894 #define MVNETA_TX_CMD_L (1 << 20) /* Last buffer */ 895 #define MVNETA_TX_CMD_PADDING (1 << 19) /* Pad short frame */ 896 #define MVNETA_TX_CMD_IP4_CHECKSUM (1 << 18) /* Do IPv4 Checksum */ 897 #define MVNETA_TX_CMD_L3_IP4 (0 << 17) 898 #define MVNETA_TX_CMD_L3_IP6 (1 << 17) 899 #define MVNETA_TX_CMD_L4_TCP (0 << 16) 900 #define MVNETA_TX_CMD_L4_UDP (1 << 16) 901 /* bit 15:13 reserved */ 902 #define MVNETA_TX_CMD_IP_HEADER_LEN_MASK (0x1f << 8) /* IP header len >> 2 */ 903 #define MVNETA_TX_CMD_IP_HEADER_LEN(v) (((v) & 0x1f) << 8) 904 /* bit 7 reserved */ 905 #define MVNETA_TX_CMD_L3_OFFSET_MASK (0x7f << 0) /* offset of L3 hdr. */ 906 #define MVNETA_TX_CMD_L3_OFFSET(v) (((v) & 0x7f) << 0) 907 908 /* 909 * Transmit packet extra attributes 910 * and error status returned from network controller. 911 */ 912 #define MVNETA_TX_F_DSA_TAG (3 << 30) /* DSA Tag */ 913 /* bit 29:8 reserved */ 914 #define MVNETA_TX_F_MH_SEL (0xf << 4) /* Marvell Header */ 915 /* bit 3 reserved */ 916 #define MVNETA_TX_F_EC_MASK (3 << 1) /* Error code */ 917 #define MVNETA_TX_F_EC_LC (0x00 << 1) /* Late Collision */ 918 #define MVNETA_TX_F_EC_UR (0x01 << 1) /* Underrun */ 919 #define MVNETA_TX_F_EC_RL (0x10 << 1) /* Excess. Collision */ 920 #define MVNETA_TX_F_EC_RESERVED (0x11 << 1) 921 #define MVNETA_TX_F_ES (1 << 0) /* Error summary */ 922 923 #define MVNETA_ERROR_SUMMARY (1 << 0) 924 #define MVNETA_BUFFER_OWNED_MASK (1UL << 31) 925 #define MVNETA_BUFFER_OWNED_BY_HOST (0UL << 31) 926 #define MVNETA_BUFFER_OWNED_BY_DMA (1UL << 31) 927 928 #endif /* _IF_MVNETAREG_H_ */ 929