1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2012-2014 Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #ifndef __NVME_PRIVATE_H__ 32 #define __NVME_PRIVATE_H__ 33 34 #include <sys/param.h> 35 #include <sys/bio.h> 36 #include <sys/bus.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/module.h> 41 #include <sys/mutex.h> 42 #include <sys/rman.h> 43 #include <sys/systm.h> 44 #include <sys/taskqueue.h> 45 46 #include <vm/uma.h> 47 48 #include <machine/bus.h> 49 50 #include "nvme.h" 51 52 #define DEVICE2SOFTC(dev) ((struct nvme_controller *) device_get_softc(dev)) 53 54 MALLOC_DECLARE(M_NVME); 55 56 #define IDT32_PCI_ID 0x80d0111d /* 32 channel board */ 57 #define IDT8_PCI_ID 0x80d2111d /* 8 channel board */ 58 59 /* 60 * For commands requiring more than 2 PRP entries, one PRP will be 61 * embedded in the command (prp1), and the rest of the PRP entries 62 * will be in a list pointed to by the command (prp2). This means 63 * that real max number of PRP entries we support is 32+1, which 64 * results in a max xfer size of 32*PAGE_SIZE. 65 */ 66 #define NVME_MAX_PRP_LIST_ENTRIES (NVME_MAX_XFER_SIZE / PAGE_SIZE) 67 68 #define NVME_ADMIN_TRACKERS (16) 69 #define NVME_ADMIN_ENTRIES (128) 70 /* min and max are defined in admin queue attributes section of spec */ 71 #define NVME_MIN_ADMIN_ENTRIES (2) 72 #define NVME_MAX_ADMIN_ENTRIES (4096) 73 74 /* 75 * NVME_IO_ENTRIES defines the size of an I/O qpair's submission and completion 76 * queues, while NVME_IO_TRACKERS defines the maximum number of I/O that we 77 * will allow outstanding on an I/O qpair at any time. The only advantage in 78 * having IO_ENTRIES > IO_TRACKERS is for debugging purposes - when dumping 79 * the contents of the submission and completion queues, it will show a longer 80 * history of data. 81 */ 82 #define NVME_IO_ENTRIES (256) 83 #define NVME_IO_TRACKERS (128) 84 #define NVME_MIN_IO_TRACKERS (4) 85 #define NVME_MAX_IO_TRACKERS (1024) 86 87 /* 88 * NVME_MAX_IO_ENTRIES is not defined, since it is specified in CC.MQES 89 * for each controller. 90 */ 91 92 #define NVME_INT_COAL_TIME (0) /* disabled */ 93 #define NVME_INT_COAL_THRESHOLD (0) /* 0-based */ 94 95 #define NVME_MAX_NAMESPACES (16) 96 #define NVME_MAX_CONSUMERS (2) 97 #define NVME_MAX_ASYNC_EVENTS (8) 98 99 #define NVME_DEFAULT_TIMEOUT_PERIOD (30) /* in seconds */ 100 #define NVME_MIN_TIMEOUT_PERIOD (5) 101 #define NVME_MAX_TIMEOUT_PERIOD (120) 102 103 #define NVME_DEFAULT_RETRY_COUNT (4) 104 105 /* Maximum log page size to fetch for AERs. */ 106 #define NVME_MAX_AER_LOG_SIZE (4096) 107 108 /* 109 * Define CACHE_LINE_SIZE here for older FreeBSD versions that do not define 110 * it. 111 */ 112 #ifndef CACHE_LINE_SIZE 113 #define CACHE_LINE_SIZE (64) 114 #endif 115 116 extern uma_zone_t nvme_request_zone; 117 extern int32_t nvme_retry_count; 118 extern bool nvme_verbose_cmd_dump; 119 120 struct nvme_completion_poll_status { 121 struct nvme_completion cpl; 122 int done; 123 }; 124 125 extern devclass_t nvme_devclass; 126 127 #define NVME_REQUEST_VADDR 1 128 #define NVME_REQUEST_NULL 2 /* For requests with no payload. */ 129 #define NVME_REQUEST_UIO 3 130 #define NVME_REQUEST_BIO 4 131 #define NVME_REQUEST_CCB 5 132 133 struct nvme_request { 134 struct nvme_command cmd; 135 struct nvme_qpair *qpair; 136 union { 137 void *payload; 138 struct bio *bio; 139 } u; 140 uint32_t type; 141 uint32_t payload_size; 142 bool timeout; 143 nvme_cb_fn_t cb_fn; 144 void *cb_arg; 145 int32_t retries; 146 STAILQ_ENTRY(nvme_request) stailq; 147 }; 148 149 struct nvme_async_event_request { 150 struct nvme_controller *ctrlr; 151 struct nvme_request *req; 152 struct nvme_completion cpl; 153 uint32_t log_page_id; 154 uint32_t log_page_size; 155 uint8_t log_page_buffer[NVME_MAX_AER_LOG_SIZE]; 156 }; 157 158 struct nvme_tracker { 159 TAILQ_ENTRY(nvme_tracker) tailq; 160 struct nvme_request *req; 161 struct nvme_qpair *qpair; 162 struct callout timer; 163 bus_dmamap_t payload_dma_map; 164 uint16_t cid; 165 166 uint64_t *prp; 167 bus_addr_t prp_bus_addr; 168 }; 169 170 struct nvme_qpair { 171 struct nvme_controller *ctrlr; 172 uint32_t id; 173 int domain; 174 int cpu; 175 176 uint16_t vector; 177 int rid; 178 struct resource *res; 179 void *tag; 180 181 uint32_t num_entries; 182 uint32_t num_trackers; 183 uint32_t sq_tdbl_off; 184 uint32_t cq_hdbl_off; 185 186 uint32_t phase; 187 uint32_t sq_head; 188 uint32_t sq_tail; 189 uint32_t cq_head; 190 191 int64_t num_cmds; 192 int64_t num_intr_handler_calls; 193 int64_t num_retries; 194 int64_t num_failures; 195 196 struct nvme_command *cmd; 197 struct nvme_completion *cpl; 198 199 bus_dma_tag_t dma_tag; 200 bus_dma_tag_t dma_tag_payload; 201 202 bus_dmamap_t queuemem_map; 203 uint64_t cmd_bus_addr; 204 uint64_t cpl_bus_addr; 205 206 TAILQ_HEAD(, nvme_tracker) free_tr; 207 TAILQ_HEAD(, nvme_tracker) outstanding_tr; 208 STAILQ_HEAD(, nvme_request) queued_req; 209 210 struct nvme_tracker **act_tr; 211 212 bool is_enabled; 213 214 struct mtx lock __aligned(CACHE_LINE_SIZE); 215 216 } __aligned(CACHE_LINE_SIZE); 217 218 struct nvme_namespace { 219 struct nvme_controller *ctrlr; 220 struct nvme_namespace_data data; 221 uint32_t id; 222 uint32_t flags; 223 struct cdev *cdev; 224 void *cons_cookie[NVME_MAX_CONSUMERS]; 225 uint32_t boundary; 226 struct mtx lock; 227 }; 228 229 /* 230 * One of these per allocated PCI device. 231 */ 232 struct nvme_controller { 233 device_t dev; 234 235 struct mtx lock; 236 int domain; 237 uint32_t ready_timeout_in_ms; 238 uint32_t quirks; 239 #define QUIRK_DELAY_B4_CHK_RDY 1 /* Can't touch MMIO on disable */ 240 #define QUIRK_DISABLE_TIMEOUT 2 /* Disable broken completion timeout feature */ 241 242 bus_space_tag_t bus_tag; 243 bus_space_handle_t bus_handle; 244 int resource_id; 245 struct resource *resource; 246 247 /* 248 * The NVMe spec allows for the MSI-X table to be placed in BAR 4/5, 249 * separate from the control registers which are in BAR 0/1. These 250 * members track the mapping of BAR 4/5 for that reason. 251 */ 252 int bar4_resource_id; 253 struct resource *bar4_resource; 254 255 uint32_t msix_enabled; 256 uint32_t enable_aborts; 257 258 uint32_t num_io_queues; 259 uint32_t max_hw_pend_io; 260 261 /* Fields for tracking progress during controller initialization. */ 262 struct intr_config_hook config_hook; 263 uint32_t ns_identified; 264 uint32_t queues_created; 265 266 struct task reset_task; 267 struct task fail_req_task; 268 struct taskqueue *taskqueue; 269 270 /* For shared legacy interrupt. */ 271 int rid; 272 struct resource *res; 273 void *tag; 274 275 /** maximum i/o size in bytes */ 276 uint32_t max_xfer_size; 277 278 /** minimum page size supported by this controller in bytes */ 279 uint32_t min_page_size; 280 281 /** interrupt coalescing time period (in microseconds) */ 282 uint32_t int_coal_time; 283 284 /** interrupt coalescing threshold */ 285 uint32_t int_coal_threshold; 286 287 /** timeout period in seconds */ 288 uint32_t timeout_period; 289 290 /** doorbell stride */ 291 uint32_t dstrd; 292 293 struct nvme_qpair adminq; 294 struct nvme_qpair *ioq; 295 296 struct nvme_registers *regs; 297 298 struct nvme_controller_data cdata; 299 struct nvme_namespace ns[NVME_MAX_NAMESPACES]; 300 301 struct cdev *cdev; 302 303 /** bit mask of event types currently enabled for async events */ 304 uint32_t async_event_config; 305 306 uint32_t num_aers; 307 struct nvme_async_event_request aer[NVME_MAX_ASYNC_EVENTS]; 308 309 void *cons_cookie[NVME_MAX_CONSUMERS]; 310 311 uint32_t is_resetting; 312 uint32_t is_initialized; 313 uint32_t notification_sent; 314 315 bool is_failed; 316 STAILQ_HEAD(, nvme_request) fail_req; 317 318 /* Host Memory Buffer */ 319 int hmb_nchunks; 320 size_t hmb_chunk; 321 bus_dma_tag_t hmb_tag; 322 struct nvme_hmb_chunk { 323 bus_dmamap_t hmbc_map; 324 void *hmbc_vaddr; 325 uint64_t hmbc_paddr; 326 } *hmb_chunks; 327 bus_dma_tag_t hmb_desc_tag; 328 bus_dmamap_t hmb_desc_map; 329 struct nvme_hmb_desc *hmb_desc_vaddr; 330 uint64_t hmb_desc_paddr; 331 }; 332 333 #define nvme_mmio_offsetof(reg) \ 334 offsetof(struct nvme_registers, reg) 335 336 #define nvme_mmio_read_4(sc, reg) \ 337 bus_space_read_4((sc)->bus_tag, (sc)->bus_handle, \ 338 nvme_mmio_offsetof(reg)) 339 340 #define nvme_mmio_write_4(sc, reg, val) \ 341 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 342 nvme_mmio_offsetof(reg), val) 343 344 #define nvme_mmio_write_8(sc, reg, val) \ 345 do { \ 346 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 347 nvme_mmio_offsetof(reg), val & 0xFFFFFFFF); \ 348 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 349 nvme_mmio_offsetof(reg)+4, \ 350 (val & 0xFFFFFFFF00000000ULL) >> 32); \ 351 } while (0); 352 353 #define nvme_printf(ctrlr, fmt, args...) \ 354 device_printf(ctrlr->dev, fmt, ##args) 355 356 void nvme_ns_test(struct nvme_namespace *ns, u_long cmd, caddr_t arg); 357 358 void nvme_ctrlr_cmd_identify_controller(struct nvme_controller *ctrlr, 359 void *payload, 360 nvme_cb_fn_t cb_fn, void *cb_arg); 361 void nvme_ctrlr_cmd_identify_namespace(struct nvme_controller *ctrlr, 362 uint32_t nsid, void *payload, 363 nvme_cb_fn_t cb_fn, void *cb_arg); 364 void nvme_ctrlr_cmd_set_interrupt_coalescing(struct nvme_controller *ctrlr, 365 uint32_t microseconds, 366 uint32_t threshold, 367 nvme_cb_fn_t cb_fn, 368 void *cb_arg); 369 void nvme_ctrlr_cmd_get_error_page(struct nvme_controller *ctrlr, 370 struct nvme_error_information_entry *payload, 371 uint32_t num_entries, /* 0 = max */ 372 nvme_cb_fn_t cb_fn, 373 void *cb_arg); 374 void nvme_ctrlr_cmd_get_health_information_page(struct nvme_controller *ctrlr, 375 uint32_t nsid, 376 struct nvme_health_information_page *payload, 377 nvme_cb_fn_t cb_fn, 378 void *cb_arg); 379 void nvme_ctrlr_cmd_get_firmware_page(struct nvme_controller *ctrlr, 380 struct nvme_firmware_page *payload, 381 nvme_cb_fn_t cb_fn, 382 void *cb_arg); 383 void nvme_ctrlr_cmd_create_io_cq(struct nvme_controller *ctrlr, 384 struct nvme_qpair *io_que, 385 nvme_cb_fn_t cb_fn, void *cb_arg); 386 void nvme_ctrlr_cmd_create_io_sq(struct nvme_controller *ctrlr, 387 struct nvme_qpair *io_que, 388 nvme_cb_fn_t cb_fn, void *cb_arg); 389 void nvme_ctrlr_cmd_delete_io_cq(struct nvme_controller *ctrlr, 390 struct nvme_qpair *io_que, 391 nvme_cb_fn_t cb_fn, void *cb_arg); 392 void nvme_ctrlr_cmd_delete_io_sq(struct nvme_controller *ctrlr, 393 struct nvme_qpair *io_que, 394 nvme_cb_fn_t cb_fn, void *cb_arg); 395 void nvme_ctrlr_cmd_set_num_queues(struct nvme_controller *ctrlr, 396 uint32_t num_queues, nvme_cb_fn_t cb_fn, 397 void *cb_arg); 398 void nvme_ctrlr_cmd_set_async_event_config(struct nvme_controller *ctrlr, 399 uint32_t state, 400 nvme_cb_fn_t cb_fn, void *cb_arg); 401 void nvme_ctrlr_cmd_abort(struct nvme_controller *ctrlr, uint16_t cid, 402 uint16_t sqid, nvme_cb_fn_t cb_fn, void *cb_arg); 403 404 void nvme_completion_poll_cb(void *arg, const struct nvme_completion *cpl); 405 406 int nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev); 407 void nvme_ctrlr_destruct(struct nvme_controller *ctrlr, device_t dev); 408 void nvme_ctrlr_shutdown(struct nvme_controller *ctrlr); 409 int nvme_ctrlr_hw_reset(struct nvme_controller *ctrlr); 410 void nvme_ctrlr_reset(struct nvme_controller *ctrlr); 411 /* ctrlr defined as void * to allow use with config_intrhook. */ 412 void nvme_ctrlr_start_config_hook(void *ctrlr_arg); 413 void nvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr, 414 struct nvme_request *req); 415 void nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr, 416 struct nvme_request *req); 417 void nvme_ctrlr_post_failed_request(struct nvme_controller *ctrlr, 418 struct nvme_request *req); 419 420 int nvme_qpair_construct(struct nvme_qpair *qpair, 421 uint32_t num_entries, uint32_t num_trackers, 422 struct nvme_controller *ctrlr); 423 void nvme_qpair_submit_tracker(struct nvme_qpair *qpair, 424 struct nvme_tracker *tr); 425 bool nvme_qpair_process_completions(struct nvme_qpair *qpair); 426 void nvme_qpair_submit_request(struct nvme_qpair *qpair, 427 struct nvme_request *req); 428 void nvme_qpair_reset(struct nvme_qpair *qpair); 429 void nvme_qpair_fail(struct nvme_qpair *qpair); 430 void nvme_qpair_manual_complete_request(struct nvme_qpair *qpair, 431 struct nvme_request *req, 432 uint32_t sct, uint32_t sc); 433 434 void nvme_admin_qpair_enable(struct nvme_qpair *qpair); 435 void nvme_admin_qpair_disable(struct nvme_qpair *qpair); 436 void nvme_admin_qpair_destroy(struct nvme_qpair *qpair); 437 438 void nvme_io_qpair_enable(struct nvme_qpair *qpair); 439 void nvme_io_qpair_disable(struct nvme_qpair *qpair); 440 void nvme_io_qpair_destroy(struct nvme_qpair *qpair); 441 442 int nvme_ns_construct(struct nvme_namespace *ns, uint32_t id, 443 struct nvme_controller *ctrlr); 444 void nvme_ns_destruct(struct nvme_namespace *ns); 445 446 void nvme_sysctl_initialize_ctrlr(struct nvme_controller *ctrlr); 447 448 void nvme_dump_command(struct nvme_command *cmd); 449 void nvme_dump_completion(struct nvme_completion *cpl); 450 451 int nvme_attach(device_t dev); 452 int nvme_shutdown(device_t dev); 453 int nvme_detach(device_t dev); 454 455 /* 456 * Wait for a command to complete using the nvme_completion_poll_cb. 457 * Used in limited contexts where the caller knows it's OK to block 458 * briefly while the command runs. The ISR will run the callback which 459 * will set status->done to true, usually within microseconds. If not, 460 * then after one second timeout handler should reset the controller 461 * and abort all outstanding requests including this polled one. If 462 * still not after ten seconds, then something is wrong with the driver, 463 * and panic is the only way to recover. 464 */ 465 static __inline 466 void 467 nvme_completion_poll(struct nvme_completion_poll_status *status) 468 { 469 int sanity = hz * 10; 470 471 while (!atomic_load_acq_int(&status->done) && --sanity > 0) 472 pause("nvme", 1); 473 if (sanity <= 0) 474 panic("NVME polled command failed to complete within 10s."); 475 } 476 477 static __inline void 478 nvme_single_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 479 { 480 uint64_t *bus_addr = (uint64_t *)arg; 481 482 if (error != 0) 483 printf("nvme_single_map err %d\n", error); 484 *bus_addr = seg[0].ds_addr; 485 } 486 487 static __inline struct nvme_request * 488 _nvme_allocate_request(nvme_cb_fn_t cb_fn, void *cb_arg) 489 { 490 struct nvme_request *req; 491 492 req = uma_zalloc(nvme_request_zone, M_NOWAIT | M_ZERO); 493 if (req != NULL) { 494 req->cb_fn = cb_fn; 495 req->cb_arg = cb_arg; 496 req->timeout = true; 497 } 498 return (req); 499 } 500 501 static __inline struct nvme_request * 502 nvme_allocate_request_vaddr(void *payload, uint32_t payload_size, 503 nvme_cb_fn_t cb_fn, void *cb_arg) 504 { 505 struct nvme_request *req; 506 507 req = _nvme_allocate_request(cb_fn, cb_arg); 508 if (req != NULL) { 509 req->type = NVME_REQUEST_VADDR; 510 req->u.payload = payload; 511 req->payload_size = payload_size; 512 } 513 return (req); 514 } 515 516 static __inline struct nvme_request * 517 nvme_allocate_request_null(nvme_cb_fn_t cb_fn, void *cb_arg) 518 { 519 struct nvme_request *req; 520 521 req = _nvme_allocate_request(cb_fn, cb_arg); 522 if (req != NULL) 523 req->type = NVME_REQUEST_NULL; 524 return (req); 525 } 526 527 static __inline struct nvme_request * 528 nvme_allocate_request_bio(struct bio *bio, nvme_cb_fn_t cb_fn, void *cb_arg) 529 { 530 struct nvme_request *req; 531 532 req = _nvme_allocate_request(cb_fn, cb_arg); 533 if (req != NULL) { 534 req->type = NVME_REQUEST_BIO; 535 req->u.bio = bio; 536 } 537 return (req); 538 } 539 540 static __inline struct nvme_request * 541 nvme_allocate_request_ccb(union ccb *ccb, nvme_cb_fn_t cb_fn, void *cb_arg) 542 { 543 struct nvme_request *req; 544 545 req = _nvme_allocate_request(cb_fn, cb_arg); 546 if (req != NULL) { 547 req->type = NVME_REQUEST_CCB; 548 req->u.payload = ccb; 549 } 550 551 return (req); 552 } 553 554 #define nvme_free_request(req) uma_zfree(nvme_request_zone, req) 555 556 void nvme_notify_async_consumers(struct nvme_controller *ctrlr, 557 const struct nvme_completion *async_cpl, 558 uint32_t log_page_id, void *log_page_buffer, 559 uint32_t log_page_size); 560 void nvme_notify_fail_consumers(struct nvme_controller *ctrlr); 561 void nvme_notify_new_controller(struct nvme_controller *ctrlr); 562 void nvme_notify_ns(struct nvme_controller *ctrlr, int nsid); 563 564 void nvme_ctrlr_intx_handler(void *arg); 565 void nvme_ctrlr_poll(struct nvme_controller *ctrlr); 566 567 int nvme_ctrlr_suspend(struct nvme_controller *ctrlr); 568 int nvme_ctrlr_resume(struct nvme_controller *ctrlr); 569 570 #endif /* __NVME_PRIVATE_H__ */ 571