1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2012-2014 Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/conf.h> 35 #include <sys/domainset.h> 36 #include <sys/proc.h> 37 38 #include <dev/pci/pcivar.h> 39 40 #include "nvme_private.h" 41 42 typedef enum error_print { ERROR_PRINT_NONE, ERROR_PRINT_NO_RETRY, ERROR_PRINT_ALL } error_print_t; 43 #define DO_NOT_RETRY 1 44 45 static void _nvme_qpair_submit_request(struct nvme_qpair *qpair, 46 struct nvme_request *req); 47 static void nvme_qpair_destroy(struct nvme_qpair *qpair); 48 49 struct nvme_opcode_string { 50 51 uint16_t opc; 52 const char * str; 53 }; 54 55 static struct nvme_opcode_string admin_opcode[] = { 56 { NVME_OPC_DELETE_IO_SQ, "DELETE IO SQ" }, 57 { NVME_OPC_CREATE_IO_SQ, "CREATE IO SQ" }, 58 { NVME_OPC_GET_LOG_PAGE, "GET LOG PAGE" }, 59 { NVME_OPC_DELETE_IO_CQ, "DELETE IO CQ" }, 60 { NVME_OPC_CREATE_IO_CQ, "CREATE IO CQ" }, 61 { NVME_OPC_IDENTIFY, "IDENTIFY" }, 62 { NVME_OPC_ABORT, "ABORT" }, 63 { NVME_OPC_SET_FEATURES, "SET FEATURES" }, 64 { NVME_OPC_GET_FEATURES, "GET FEATURES" }, 65 { NVME_OPC_ASYNC_EVENT_REQUEST, "ASYNC EVENT REQUEST" }, 66 { NVME_OPC_FIRMWARE_ACTIVATE, "FIRMWARE ACTIVATE" }, 67 { NVME_OPC_FIRMWARE_IMAGE_DOWNLOAD, "FIRMWARE IMAGE DOWNLOAD" }, 68 { NVME_OPC_DEVICE_SELF_TEST, "DEVICE SELF-TEST" }, 69 { NVME_OPC_NAMESPACE_ATTACHMENT, "NAMESPACE ATTACHMENT" }, 70 { NVME_OPC_KEEP_ALIVE, "KEEP ALIVE" }, 71 { NVME_OPC_DIRECTIVE_SEND, "DIRECTIVE SEND" }, 72 { NVME_OPC_DIRECTIVE_RECEIVE, "DIRECTIVE RECEIVE" }, 73 { NVME_OPC_VIRTUALIZATION_MANAGEMENT, "VIRTUALIZATION MANAGEMENT" }, 74 { NVME_OPC_NVME_MI_SEND, "NVME-MI SEND" }, 75 { NVME_OPC_NVME_MI_RECEIVE, "NVME-MI RECEIVE" }, 76 { NVME_OPC_DOORBELL_BUFFER_CONFIG, "DOORBELL BUFFER CONFIG" }, 77 { NVME_OPC_FORMAT_NVM, "FORMAT NVM" }, 78 { NVME_OPC_SECURITY_SEND, "SECURITY SEND" }, 79 { NVME_OPC_SECURITY_RECEIVE, "SECURITY RECEIVE" }, 80 { NVME_OPC_SANITIZE, "SANITIZE" }, 81 { NVME_OPC_GET_LBA_STATUS, "GET LBA STATUS" }, 82 { 0xFFFF, "ADMIN COMMAND" } 83 }; 84 85 static struct nvme_opcode_string io_opcode[] = { 86 { NVME_OPC_FLUSH, "FLUSH" }, 87 { NVME_OPC_WRITE, "WRITE" }, 88 { NVME_OPC_READ, "READ" }, 89 { NVME_OPC_WRITE_UNCORRECTABLE, "WRITE UNCORRECTABLE" }, 90 { NVME_OPC_COMPARE, "COMPARE" }, 91 { NVME_OPC_WRITE_ZEROES, "WRITE ZEROES" }, 92 { NVME_OPC_DATASET_MANAGEMENT, "DATASET MANAGEMENT" }, 93 { NVME_OPC_VERIFY, "VERIFY" }, 94 { NVME_OPC_RESERVATION_REGISTER, "RESERVATION REGISTER" }, 95 { NVME_OPC_RESERVATION_REPORT, "RESERVATION REPORT" }, 96 { NVME_OPC_RESERVATION_ACQUIRE, "RESERVATION ACQUIRE" }, 97 { NVME_OPC_RESERVATION_RELEASE, "RESERVATION RELEASE" }, 98 { 0xFFFF, "IO COMMAND" } 99 }; 100 101 static const char * 102 get_admin_opcode_string(uint16_t opc) 103 { 104 struct nvme_opcode_string *entry; 105 106 entry = admin_opcode; 107 108 while (entry->opc != 0xFFFF) { 109 if (entry->opc == opc) 110 return (entry->str); 111 entry++; 112 } 113 return (entry->str); 114 } 115 116 static const char * 117 get_io_opcode_string(uint16_t opc) 118 { 119 struct nvme_opcode_string *entry; 120 121 entry = io_opcode; 122 123 while (entry->opc != 0xFFFF) { 124 if (entry->opc == opc) 125 return (entry->str); 126 entry++; 127 } 128 return (entry->str); 129 } 130 131 132 static void 133 nvme_admin_qpair_print_command(struct nvme_qpair *qpair, 134 struct nvme_command *cmd) 135 { 136 137 nvme_printf(qpair->ctrlr, "%s (%02x) sqid:%d cid:%d nsid:%x " 138 "cdw10:%08x cdw11:%08x\n", 139 get_admin_opcode_string(cmd->opc), cmd->opc, qpair->id, cmd->cid, 140 le32toh(cmd->nsid), le32toh(cmd->cdw10), le32toh(cmd->cdw11)); 141 } 142 143 static void 144 nvme_io_qpair_print_command(struct nvme_qpair *qpair, 145 struct nvme_command *cmd) 146 { 147 148 switch (cmd->opc) { 149 case NVME_OPC_WRITE: 150 case NVME_OPC_READ: 151 case NVME_OPC_WRITE_UNCORRECTABLE: 152 case NVME_OPC_COMPARE: 153 case NVME_OPC_WRITE_ZEROES: 154 case NVME_OPC_VERIFY: 155 nvme_printf(qpair->ctrlr, "%s sqid:%d cid:%d nsid:%d " 156 "lba:%llu len:%d\n", 157 get_io_opcode_string(cmd->opc), qpair->id, cmd->cid, le32toh(cmd->nsid), 158 ((unsigned long long)le32toh(cmd->cdw11) << 32) + le32toh(cmd->cdw10), 159 (le32toh(cmd->cdw12) & 0xFFFF) + 1); 160 break; 161 case NVME_OPC_FLUSH: 162 case NVME_OPC_DATASET_MANAGEMENT: 163 case NVME_OPC_RESERVATION_REGISTER: 164 case NVME_OPC_RESERVATION_REPORT: 165 case NVME_OPC_RESERVATION_ACQUIRE: 166 case NVME_OPC_RESERVATION_RELEASE: 167 nvme_printf(qpair->ctrlr, "%s sqid:%d cid:%d nsid:%d\n", 168 get_io_opcode_string(cmd->opc), qpair->id, cmd->cid, le32toh(cmd->nsid)); 169 break; 170 default: 171 nvme_printf(qpair->ctrlr, "%s (%02x) sqid:%d cid:%d nsid:%d\n", 172 get_io_opcode_string(cmd->opc), cmd->opc, qpair->id, 173 cmd->cid, le32toh(cmd->nsid)); 174 break; 175 } 176 } 177 178 static void 179 nvme_qpair_print_command(struct nvme_qpair *qpair, struct nvme_command *cmd) 180 { 181 if (qpair->id == 0) 182 nvme_admin_qpair_print_command(qpair, cmd); 183 else 184 nvme_io_qpair_print_command(qpair, cmd); 185 if (nvme_verbose_cmd_dump) { 186 nvme_printf(qpair->ctrlr, 187 "nsid:%#x rsvd2:%#x rsvd3:%#x mptr:%#jx prp1:%#jx prp2:%#jx\n", 188 cmd->nsid, cmd->rsvd2, cmd->rsvd3, (uintmax_t)cmd->mptr, 189 (uintmax_t)cmd->prp1, (uintmax_t)cmd->prp2); 190 nvme_printf(qpair->ctrlr, 191 "cdw10: %#x cdw11:%#x cdw12:%#x cdw13:%#x cdw14:%#x cdw15:%#x\n", 192 cmd->cdw10, cmd->cdw11, cmd->cdw12, cmd->cdw13, cmd->cdw14, 193 cmd->cdw15); 194 } 195 } 196 197 struct nvme_status_string { 198 199 uint16_t sc; 200 const char * str; 201 }; 202 203 static struct nvme_status_string generic_status[] = { 204 { NVME_SC_SUCCESS, "SUCCESS" }, 205 { NVME_SC_INVALID_OPCODE, "INVALID OPCODE" }, 206 { NVME_SC_INVALID_FIELD, "INVALID_FIELD" }, 207 { NVME_SC_COMMAND_ID_CONFLICT, "COMMAND ID CONFLICT" }, 208 { NVME_SC_DATA_TRANSFER_ERROR, "DATA TRANSFER ERROR" }, 209 { NVME_SC_ABORTED_POWER_LOSS, "ABORTED - POWER LOSS" }, 210 { NVME_SC_INTERNAL_DEVICE_ERROR, "INTERNAL DEVICE ERROR" }, 211 { NVME_SC_ABORTED_BY_REQUEST, "ABORTED - BY REQUEST" }, 212 { NVME_SC_ABORTED_SQ_DELETION, "ABORTED - SQ DELETION" }, 213 { NVME_SC_ABORTED_FAILED_FUSED, "ABORTED - FAILED FUSED" }, 214 { NVME_SC_ABORTED_MISSING_FUSED, "ABORTED - MISSING FUSED" }, 215 { NVME_SC_INVALID_NAMESPACE_OR_FORMAT, "INVALID NAMESPACE OR FORMAT" }, 216 { NVME_SC_COMMAND_SEQUENCE_ERROR, "COMMAND SEQUENCE ERROR" }, 217 { NVME_SC_INVALID_SGL_SEGMENT_DESCR, "INVALID SGL SEGMENT DESCRIPTOR" }, 218 { NVME_SC_INVALID_NUMBER_OF_SGL_DESCR, "INVALID NUMBER OF SGL DESCRIPTORS" }, 219 { NVME_SC_DATA_SGL_LENGTH_INVALID, "DATA SGL LENGTH INVALID" }, 220 { NVME_SC_METADATA_SGL_LENGTH_INVALID, "METADATA SGL LENGTH INVALID" }, 221 { NVME_SC_SGL_DESCRIPTOR_TYPE_INVALID, "SGL DESCRIPTOR TYPE INVALID" }, 222 { NVME_SC_INVALID_USE_OF_CMB, "INVALID USE OF CONTROLLER MEMORY BUFFER" }, 223 { NVME_SC_PRP_OFFET_INVALID, "PRP OFFET INVALID" }, 224 { NVME_SC_ATOMIC_WRITE_UNIT_EXCEEDED, "ATOMIC WRITE UNIT EXCEEDED" }, 225 { NVME_SC_OPERATION_DENIED, "OPERATION DENIED" }, 226 { NVME_SC_SGL_OFFSET_INVALID, "SGL OFFSET INVALID" }, 227 { NVME_SC_HOST_ID_INCONSISTENT_FORMAT, "HOST IDENTIFIER INCONSISTENT FORMAT" }, 228 { NVME_SC_KEEP_ALIVE_TIMEOUT_EXPIRED, "KEEP ALIVE TIMEOUT EXPIRED" }, 229 { NVME_SC_KEEP_ALIVE_TIMEOUT_INVALID, "KEEP ALIVE TIMEOUT INVALID" }, 230 { NVME_SC_ABORTED_DUE_TO_PREEMPT, "COMMAND ABORTED DUE TO PREEMPT AND ABORT" }, 231 { NVME_SC_SANITIZE_FAILED, "SANITIZE FAILED" }, 232 { NVME_SC_SANITIZE_IN_PROGRESS, "SANITIZE IN PROGRESS" }, 233 { NVME_SC_SGL_DATA_BLOCK_GRAN_INVALID, "SGL_DATA_BLOCK_GRANULARITY_INVALID" }, 234 { NVME_SC_NOT_SUPPORTED_IN_CMB, "COMMAND NOT SUPPORTED FOR QUEUE IN CMB" }, 235 { NVME_SC_NAMESPACE_IS_WRITE_PROTECTED, "NAMESPACE IS WRITE PROTECTED" }, 236 { NVME_SC_COMMAND_INTERRUPTED, "COMMAND INTERRUPTED" }, 237 { NVME_SC_TRANSIENT_TRANSPORT_ERROR, "TRANSIENT TRANSPORT ERROR" }, 238 239 { NVME_SC_LBA_OUT_OF_RANGE, "LBA OUT OF RANGE" }, 240 { NVME_SC_CAPACITY_EXCEEDED, "CAPACITY EXCEEDED" }, 241 { NVME_SC_NAMESPACE_NOT_READY, "NAMESPACE NOT READY" }, 242 { NVME_SC_RESERVATION_CONFLICT, "RESERVATION CONFLICT" }, 243 { NVME_SC_FORMAT_IN_PROGRESS, "FORMAT IN PROGRESS" }, 244 { 0xFFFF, "GENERIC" } 245 }; 246 247 static struct nvme_status_string command_specific_status[] = { 248 { NVME_SC_COMPLETION_QUEUE_INVALID, "INVALID COMPLETION QUEUE" }, 249 { NVME_SC_INVALID_QUEUE_IDENTIFIER, "INVALID QUEUE IDENTIFIER" }, 250 { NVME_SC_MAXIMUM_QUEUE_SIZE_EXCEEDED, "MAX QUEUE SIZE EXCEEDED" }, 251 { NVME_SC_ABORT_COMMAND_LIMIT_EXCEEDED, "ABORT CMD LIMIT EXCEEDED" }, 252 { NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED, "ASYNC LIMIT EXCEEDED" }, 253 { NVME_SC_INVALID_FIRMWARE_SLOT, "INVALID FIRMWARE SLOT" }, 254 { NVME_SC_INVALID_FIRMWARE_IMAGE, "INVALID FIRMWARE IMAGE" }, 255 { NVME_SC_INVALID_INTERRUPT_VECTOR, "INVALID INTERRUPT VECTOR" }, 256 { NVME_SC_INVALID_LOG_PAGE, "INVALID LOG PAGE" }, 257 { NVME_SC_INVALID_FORMAT, "INVALID FORMAT" }, 258 { NVME_SC_FIRMWARE_REQUIRES_RESET, "FIRMWARE REQUIRES RESET" }, 259 { NVME_SC_INVALID_QUEUE_DELETION, "INVALID QUEUE DELETION" }, 260 { NVME_SC_FEATURE_NOT_SAVEABLE, "FEATURE IDENTIFIER NOT SAVEABLE" }, 261 { NVME_SC_FEATURE_NOT_CHANGEABLE, "FEATURE NOT CHANGEABLE" }, 262 { NVME_SC_FEATURE_NOT_NS_SPECIFIC, "FEATURE NOT NAMESPACE SPECIFIC" }, 263 { NVME_SC_FW_ACT_REQUIRES_NVMS_RESET, "FIRMWARE ACTIVATION REQUIRES NVM SUBSYSTEM RESET" }, 264 { NVME_SC_FW_ACT_REQUIRES_RESET, "FIRMWARE ACTIVATION REQUIRES RESET" }, 265 { NVME_SC_FW_ACT_REQUIRES_TIME, "FIRMWARE ACTIVATION REQUIRES MAXIMUM TIME VIOLATION" }, 266 { NVME_SC_FW_ACT_PROHIBITED, "FIRMWARE ACTIVATION PROHIBITED" }, 267 { NVME_SC_OVERLAPPING_RANGE, "OVERLAPPING RANGE" }, 268 { NVME_SC_NS_INSUFFICIENT_CAPACITY, "NAMESPACE INSUFFICIENT CAPACITY" }, 269 { NVME_SC_NS_ID_UNAVAILABLE, "NAMESPACE IDENTIFIER UNAVAILABLE" }, 270 { NVME_SC_NS_ALREADY_ATTACHED, "NAMESPACE ALREADY ATTACHED" }, 271 { NVME_SC_NS_IS_PRIVATE, "NAMESPACE IS PRIVATE" }, 272 { NVME_SC_NS_NOT_ATTACHED, "NS NOT ATTACHED" }, 273 { NVME_SC_THIN_PROV_NOT_SUPPORTED, "THIN PROVISIONING NOT SUPPORTED" }, 274 { NVME_SC_CTRLR_LIST_INVALID, "CONTROLLER LIST INVALID" }, 275 { NVME_SC_SELT_TEST_IN_PROGRESS, "DEVICE SELT-TEST IN PROGRESS" }, 276 { NVME_SC_BOOT_PART_WRITE_PROHIB, "BOOT PARTITION WRITE PROHIBITED" }, 277 { NVME_SC_INVALID_CTRLR_ID, "INVALID CONTROLLER IDENTIFIER" }, 278 { NVME_SC_INVALID_SEC_CTRLR_STATE, "INVALID SECONDARY CONTROLLER STATE" }, 279 { NVME_SC_INVALID_NUM_OF_CTRLR_RESRC, "INVALID NUMBER OF CONTROLLER RESOURCES" }, 280 { NVME_SC_INVALID_RESOURCE_ID, "INVALID RESOURCE IDENTIFIER" }, 281 { NVME_SC_SANITIZE_PROHIBITED_WPMRE, "SANITIZE PROHIBITED WRITE PERSISTENT MEMORY REGION ENABLED" }, 282 { NVME_SC_ANA_GROUP_ID_INVALID, "ANA GROUP IDENTIFIED INVALID" }, 283 { NVME_SC_ANA_ATTACH_FAILED, "ANA ATTACH FAILED" }, 284 285 { NVME_SC_CONFLICTING_ATTRIBUTES, "CONFLICTING ATTRIBUTES" }, 286 { NVME_SC_INVALID_PROTECTION_INFO, "INVALID PROTECTION INFO" }, 287 { NVME_SC_ATTEMPTED_WRITE_TO_RO_PAGE, "WRITE TO RO PAGE" }, 288 { 0xFFFF, "COMMAND SPECIFIC" } 289 }; 290 291 static struct nvme_status_string media_error_status[] = { 292 { NVME_SC_WRITE_FAULTS, "WRITE FAULTS" }, 293 { NVME_SC_UNRECOVERED_READ_ERROR, "UNRECOVERED READ ERROR" }, 294 { NVME_SC_GUARD_CHECK_ERROR, "GUARD CHECK ERROR" }, 295 { NVME_SC_APPLICATION_TAG_CHECK_ERROR, "APPLICATION TAG CHECK ERROR" }, 296 { NVME_SC_REFERENCE_TAG_CHECK_ERROR, "REFERENCE TAG CHECK ERROR" }, 297 { NVME_SC_COMPARE_FAILURE, "COMPARE FAILURE" }, 298 { NVME_SC_ACCESS_DENIED, "ACCESS DENIED" }, 299 { NVME_SC_DEALLOCATED_OR_UNWRITTEN, "DEALLOCATED OR UNWRITTEN LOGICAL BLOCK" }, 300 { 0xFFFF, "MEDIA ERROR" } 301 }; 302 303 static struct nvme_status_string path_related_status[] = { 304 { NVME_SC_INTERNAL_PATH_ERROR, "INTERNAL PATH ERROR" }, 305 { NVME_SC_ASYMMETRIC_ACCESS_PERSISTENT_LOSS, "ASYMMETRIC ACCESS PERSISTENT LOSS" }, 306 { NVME_SC_ASYMMETRIC_ACCESS_INACCESSIBLE, "ASYMMETRIC ACCESS INACCESSIBLE" }, 307 { NVME_SC_ASYMMETRIC_ACCESS_TRANSITION, "ASYMMETRIC ACCESS TRANSITION" }, 308 { NVME_SC_CONTROLLER_PATHING_ERROR, "CONTROLLER PATHING ERROR" }, 309 { NVME_SC_HOST_PATHING_ERROR, "HOST PATHING ERROR" }, 310 { NVME_SC_COMMAND_ABOTHED_BY_HOST, "COMMAND ABOTHED BY HOST" }, 311 { 0xFFFF, "PATH RELATED" }, 312 }; 313 314 static const char * 315 get_status_string(uint16_t sct, uint16_t sc) 316 { 317 struct nvme_status_string *entry; 318 319 switch (sct) { 320 case NVME_SCT_GENERIC: 321 entry = generic_status; 322 break; 323 case NVME_SCT_COMMAND_SPECIFIC: 324 entry = command_specific_status; 325 break; 326 case NVME_SCT_MEDIA_ERROR: 327 entry = media_error_status; 328 break; 329 case NVME_SCT_PATH_RELATED: 330 entry = path_related_status; 331 break; 332 case NVME_SCT_VENDOR_SPECIFIC: 333 return ("VENDOR SPECIFIC"); 334 default: 335 return ("RESERVED"); 336 } 337 338 while (entry->sc != 0xFFFF) { 339 if (entry->sc == sc) 340 return (entry->str); 341 entry++; 342 } 343 return (entry->str); 344 } 345 346 static void 347 nvme_qpair_print_completion(struct nvme_qpair *qpair, 348 struct nvme_completion *cpl) 349 { 350 uint16_t sct, sc; 351 352 sct = NVME_STATUS_GET_SCT(cpl->status); 353 sc = NVME_STATUS_GET_SC(cpl->status); 354 355 nvme_printf(qpair->ctrlr, "%s (%02x/%02x) sqid:%d cid:%d cdw0:%x\n", 356 get_status_string(sct, sc), sct, sc, cpl->sqid, cpl->cid, 357 cpl->cdw0); 358 } 359 360 static bool 361 nvme_completion_is_retry(const struct nvme_completion *cpl) 362 { 363 uint8_t sct, sc, dnr; 364 365 sct = NVME_STATUS_GET_SCT(cpl->status); 366 sc = NVME_STATUS_GET_SC(cpl->status); 367 dnr = NVME_STATUS_GET_DNR(cpl->status); /* Do Not Retry Bit */ 368 369 /* 370 * TODO: spec is not clear how commands that are aborted due 371 * to TLER will be marked. So for now, it seems 372 * NAMESPACE_NOT_READY is the only case where we should 373 * look at the DNR bit. Requests failed with ABORTED_BY_REQUEST 374 * set the DNR bit correctly since the driver controls that. 375 */ 376 switch (sct) { 377 case NVME_SCT_GENERIC: 378 switch (sc) { 379 case NVME_SC_ABORTED_BY_REQUEST: 380 case NVME_SC_NAMESPACE_NOT_READY: 381 if (dnr) 382 return (0); 383 else 384 return (1); 385 case NVME_SC_INVALID_OPCODE: 386 case NVME_SC_INVALID_FIELD: 387 case NVME_SC_COMMAND_ID_CONFLICT: 388 case NVME_SC_DATA_TRANSFER_ERROR: 389 case NVME_SC_ABORTED_POWER_LOSS: 390 case NVME_SC_INTERNAL_DEVICE_ERROR: 391 case NVME_SC_ABORTED_SQ_DELETION: 392 case NVME_SC_ABORTED_FAILED_FUSED: 393 case NVME_SC_ABORTED_MISSING_FUSED: 394 case NVME_SC_INVALID_NAMESPACE_OR_FORMAT: 395 case NVME_SC_COMMAND_SEQUENCE_ERROR: 396 case NVME_SC_LBA_OUT_OF_RANGE: 397 case NVME_SC_CAPACITY_EXCEEDED: 398 default: 399 return (0); 400 } 401 case NVME_SCT_COMMAND_SPECIFIC: 402 case NVME_SCT_MEDIA_ERROR: 403 return (0); 404 case NVME_SCT_PATH_RELATED: 405 switch (sc) { 406 case NVME_SC_INTERNAL_PATH_ERROR: 407 if (dnr) 408 return (0); 409 else 410 return (1); 411 default: 412 return (0); 413 } 414 case NVME_SCT_VENDOR_SPECIFIC: 415 default: 416 return (0); 417 } 418 } 419 420 static void 421 nvme_qpair_complete_tracker(struct nvme_tracker *tr, 422 struct nvme_completion *cpl, error_print_t print_on_error) 423 { 424 struct nvme_qpair * qpair = tr->qpair; 425 struct nvme_request *req; 426 bool retry, error, retriable; 427 428 req = tr->req; 429 error = nvme_completion_is_error(cpl); 430 retriable = nvme_completion_is_retry(cpl); 431 retry = error && retriable && req->retries < nvme_retry_count; 432 if (retry) 433 qpair->num_retries++; 434 if (error && req->retries >= nvme_retry_count && retriable) 435 qpair->num_failures++; 436 437 if (error && (print_on_error == ERROR_PRINT_ALL || 438 (!retry && print_on_error == ERROR_PRINT_NO_RETRY))) { 439 nvme_qpair_print_command(qpair, &req->cmd); 440 nvme_qpair_print_completion(qpair, cpl); 441 } 442 443 qpair->act_tr[cpl->cid] = NULL; 444 445 KASSERT(cpl->cid == req->cmd.cid, ("cpl cid does not match cmd cid\n")); 446 447 if (!retry) { 448 if (req->type != NVME_REQUEST_NULL) { 449 bus_dmamap_sync(qpair->dma_tag_payload, 450 tr->payload_dma_map, 451 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 452 } 453 if (req->cb_fn) 454 req->cb_fn(req->cb_arg, cpl); 455 } 456 457 mtx_lock(&qpair->lock); 458 callout_stop(&tr->timer); 459 460 if (retry) { 461 req->retries++; 462 nvme_qpair_submit_tracker(qpair, tr); 463 } else { 464 if (req->type != NVME_REQUEST_NULL) { 465 bus_dmamap_unload(qpair->dma_tag_payload, 466 tr->payload_dma_map); 467 } 468 469 nvme_free_request(req); 470 tr->req = NULL; 471 472 TAILQ_REMOVE(&qpair->outstanding_tr, tr, tailq); 473 TAILQ_INSERT_HEAD(&qpair->free_tr, tr, tailq); 474 475 /* 476 * If the controller is in the middle of resetting, don't 477 * try to submit queued requests here - let the reset logic 478 * handle that instead. 479 */ 480 if (!STAILQ_EMPTY(&qpair->queued_req) && 481 !qpair->ctrlr->is_resetting) { 482 req = STAILQ_FIRST(&qpair->queued_req); 483 STAILQ_REMOVE_HEAD(&qpair->queued_req, stailq); 484 _nvme_qpair_submit_request(qpair, req); 485 } 486 } 487 488 mtx_unlock(&qpair->lock); 489 } 490 491 static void 492 nvme_qpair_manual_complete_tracker( 493 struct nvme_tracker *tr, uint32_t sct, uint32_t sc, uint32_t dnr, 494 error_print_t print_on_error) 495 { 496 struct nvme_completion cpl; 497 498 memset(&cpl, 0, sizeof(cpl)); 499 500 struct nvme_qpair * qpair = tr->qpair; 501 502 cpl.sqid = qpair->id; 503 cpl.cid = tr->cid; 504 cpl.status |= (sct & NVME_STATUS_SCT_MASK) << NVME_STATUS_SCT_SHIFT; 505 cpl.status |= (sc & NVME_STATUS_SC_MASK) << NVME_STATUS_SC_SHIFT; 506 cpl.status |= (dnr & NVME_STATUS_DNR_MASK) << NVME_STATUS_DNR_SHIFT; 507 nvme_qpair_complete_tracker(tr, &cpl, print_on_error); 508 } 509 510 void 511 nvme_qpair_manual_complete_request(struct nvme_qpair *qpair, 512 struct nvme_request *req, uint32_t sct, uint32_t sc) 513 { 514 struct nvme_completion cpl; 515 bool error; 516 517 memset(&cpl, 0, sizeof(cpl)); 518 cpl.sqid = qpair->id; 519 cpl.status |= (sct & NVME_STATUS_SCT_MASK) << NVME_STATUS_SCT_SHIFT; 520 cpl.status |= (sc & NVME_STATUS_SC_MASK) << NVME_STATUS_SC_SHIFT; 521 522 error = nvme_completion_is_error(&cpl); 523 524 if (error) { 525 nvme_qpair_print_command(qpair, &req->cmd); 526 nvme_qpair_print_completion(qpair, &cpl); 527 } 528 529 if (req->cb_fn) 530 req->cb_fn(req->cb_arg, &cpl); 531 532 nvme_free_request(req); 533 } 534 535 bool 536 nvme_qpair_process_completions(struct nvme_qpair *qpair) 537 { 538 struct nvme_tracker *tr; 539 struct nvme_completion cpl; 540 int done = 0; 541 bool in_panic = dumping || SCHEDULER_STOPPED(); 542 543 qpair->num_intr_handler_calls++; 544 545 /* 546 * qpair is not enabled, likely because a controller reset is is in 547 * progress. Ignore the interrupt - any I/O that was associated with 548 * this interrupt will get retried when the reset is complete. 549 */ 550 if (!qpair->is_enabled) 551 return (false); 552 553 /* 554 * A panic can stop the CPU this routine is running on at any point. If 555 * we're called during a panic, complete the sq_head wrap protocol for 556 * the case where we are interrupted just after the increment at 1 557 * below, but before we can reset cq_head to zero at 2. Also cope with 558 * the case where we do the zero at 2, but may or may not have done the 559 * phase adjustment at step 3. The panic machinery flushes all pending 560 * memory writes, so we can make these strong ordering assumptions 561 * that would otherwise be unwise if we were racing in real time. 562 */ 563 if (__predict_false(in_panic)) { 564 if (qpair->cq_head == qpair->num_entries) { 565 /* 566 * Here we know that we need to zero cq_head and then negate 567 * the phase, which hasn't been assigned if cq_head isn't 568 * zero due to the atomic_store_rel. 569 */ 570 qpair->cq_head = 0; 571 qpair->phase = !qpair->phase; 572 } else if (qpair->cq_head == 0) { 573 /* 574 * In this case, we know that the assignment at 2 575 * happened below, but we don't know if it 3 happened or 576 * not. To do this, we look at the last completion 577 * entry and set the phase to the opposite phase 578 * that it has. This gets us back in sync 579 */ 580 cpl = qpair->cpl[qpair->num_entries - 1]; 581 nvme_completion_swapbytes(&cpl); 582 qpair->phase = !NVME_STATUS_GET_P(cpl.status); 583 } 584 } 585 586 bus_dmamap_sync(qpair->dma_tag, qpair->queuemem_map, 587 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 588 while (1) { 589 cpl = qpair->cpl[qpair->cq_head]; 590 591 /* Convert to host endian */ 592 nvme_completion_swapbytes(&cpl); 593 594 if (NVME_STATUS_GET_P(cpl.status) != qpair->phase) 595 break; 596 597 tr = qpair->act_tr[cpl.cid]; 598 599 if (tr != NULL) { 600 nvme_qpair_complete_tracker(tr, &cpl, ERROR_PRINT_ALL); 601 qpair->sq_head = cpl.sqhd; 602 done++; 603 } else if (!in_panic) { 604 /* 605 * A missing tracker is normally an error. However, a 606 * panic can stop the CPU this routine is running on 607 * after completing an I/O but before updating 608 * qpair->cq_head at 1 below. Later, we re-enter this 609 * routine to poll I/O associated with the kernel 610 * dump. We find that the tr has been set to null before 611 * calling the completion routine. If it hasn't 612 * completed (or it triggers a panic), then '1' below 613 * won't have updated cq_head. Rather than panic again, 614 * ignore this condition because it's not unexpected. 615 */ 616 nvme_printf(qpair->ctrlr, 617 "cpl does not map to outstanding cmd\n"); 618 /* nvme_dump_completion expects device endianess */ 619 nvme_dump_completion(&qpair->cpl[qpair->cq_head]); 620 KASSERT(0, ("received completion for unknown cmd")); 621 } 622 623 /* 624 * There's a number of races with the following (see above) when 625 * the system panics. We compensate for each one of them by 626 * using the atomic store to force strong ordering (at least when 627 * viewed in the aftermath of a panic). 628 */ 629 if (++qpair->cq_head == qpair->num_entries) { /* 1 */ 630 atomic_store_rel_int(&qpair->cq_head, 0); /* 2 */ 631 qpair->phase = !qpair->phase; /* 3 */ 632 } 633 634 bus_space_write_4(qpair->ctrlr->bus_tag, qpair->ctrlr->bus_handle, 635 qpair->cq_hdbl_off, qpair->cq_head); 636 } 637 return (done != 0); 638 } 639 640 static void 641 nvme_qpair_msix_handler(void *arg) 642 { 643 struct nvme_qpair *qpair = arg; 644 645 nvme_qpair_process_completions(qpair); 646 } 647 648 int 649 nvme_qpair_construct(struct nvme_qpair *qpair, 650 uint32_t num_entries, uint32_t num_trackers, 651 struct nvme_controller *ctrlr) 652 { 653 struct nvme_tracker *tr; 654 size_t cmdsz, cplsz, prpsz, allocsz, prpmemsz; 655 uint64_t queuemem_phys, prpmem_phys, list_phys; 656 uint8_t *queuemem, *prpmem, *prp_list; 657 int i, err; 658 659 qpair->vector = ctrlr->msix_enabled ? qpair->id : 0; 660 qpair->num_entries = num_entries; 661 qpair->num_trackers = num_trackers; 662 qpair->ctrlr = ctrlr; 663 664 if (ctrlr->msix_enabled) { 665 666 /* 667 * MSI-X vector resource IDs start at 1, so we add one to 668 * the queue's vector to get the corresponding rid to use. 669 */ 670 qpair->rid = qpair->vector + 1; 671 672 qpair->res = bus_alloc_resource_any(ctrlr->dev, SYS_RES_IRQ, 673 &qpair->rid, RF_ACTIVE); 674 bus_setup_intr(ctrlr->dev, qpair->res, 675 INTR_TYPE_MISC | INTR_MPSAFE, NULL, 676 nvme_qpair_msix_handler, qpair, &qpair->tag); 677 if (qpair->id == 0) { 678 bus_describe_intr(ctrlr->dev, qpair->res, qpair->tag, 679 "admin"); 680 } else { 681 bus_describe_intr(ctrlr->dev, qpair->res, qpair->tag, 682 "io%d", qpair->id - 1); 683 } 684 } 685 686 mtx_init(&qpair->lock, "nvme qpair lock", NULL, MTX_DEF); 687 688 /* Note: NVMe PRP format is restricted to 4-byte alignment. */ 689 err = bus_dma_tag_create(bus_get_dma_tag(ctrlr->dev), 690 4, PAGE_SIZE, BUS_SPACE_MAXADDR, 691 BUS_SPACE_MAXADDR, NULL, NULL, NVME_MAX_XFER_SIZE, 692 (NVME_MAX_XFER_SIZE/PAGE_SIZE)+1, PAGE_SIZE, 0, 693 NULL, NULL, &qpair->dma_tag_payload); 694 if (err != 0) { 695 nvme_printf(ctrlr, "payload tag create failed %d\n", err); 696 goto out; 697 } 698 699 /* 700 * Each component must be page aligned, and individual PRP lists 701 * cannot cross a page boundary. 702 */ 703 cmdsz = qpair->num_entries * sizeof(struct nvme_command); 704 cmdsz = roundup2(cmdsz, PAGE_SIZE); 705 cplsz = qpair->num_entries * sizeof(struct nvme_completion); 706 cplsz = roundup2(cplsz, PAGE_SIZE); 707 prpsz = sizeof(uint64_t) * NVME_MAX_PRP_LIST_ENTRIES;; 708 prpmemsz = qpair->num_trackers * prpsz; 709 allocsz = cmdsz + cplsz + prpmemsz; 710 711 err = bus_dma_tag_create(bus_get_dma_tag(ctrlr->dev), 712 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 713 allocsz, 1, allocsz, 0, NULL, NULL, &qpair->dma_tag); 714 if (err != 0) { 715 nvme_printf(ctrlr, "tag create failed %d\n", err); 716 goto out; 717 } 718 bus_dma_tag_set_domain(qpair->dma_tag, qpair->domain); 719 720 if (bus_dmamem_alloc(qpair->dma_tag, (void **)&queuemem, 721 BUS_DMA_NOWAIT, &qpair->queuemem_map)) { 722 nvme_printf(ctrlr, "failed to alloc qpair memory\n"); 723 goto out; 724 } 725 726 if (bus_dmamap_load(qpair->dma_tag, qpair->queuemem_map, 727 queuemem, allocsz, nvme_single_map, &queuemem_phys, 0) != 0) { 728 nvme_printf(ctrlr, "failed to load qpair memory\n"); 729 goto out; 730 } 731 732 qpair->num_cmds = 0; 733 qpair->num_intr_handler_calls = 0; 734 qpair->num_retries = 0; 735 qpair->num_failures = 0; 736 qpair->cmd = (struct nvme_command *)queuemem; 737 qpair->cpl = (struct nvme_completion *)(queuemem + cmdsz); 738 prpmem = (uint8_t *)(queuemem + cmdsz + cplsz); 739 qpair->cmd_bus_addr = queuemem_phys; 740 qpair->cpl_bus_addr = queuemem_phys + cmdsz; 741 prpmem_phys = queuemem_phys + cmdsz + cplsz; 742 743 /* 744 * Calcuate the stride of the doorbell register. Many emulators set this 745 * value to correspond to a cache line. However, some hardware has set 746 * it to various small values. 747 */ 748 qpair->sq_tdbl_off = nvme_mmio_offsetof(doorbell[0]) + 749 (qpair->id << (ctrlr->dstrd + 1)); 750 qpair->cq_hdbl_off = nvme_mmio_offsetof(doorbell[0]) + 751 (qpair->id << (ctrlr->dstrd + 1)) + (1 << ctrlr->dstrd); 752 753 TAILQ_INIT(&qpair->free_tr); 754 TAILQ_INIT(&qpair->outstanding_tr); 755 STAILQ_INIT(&qpair->queued_req); 756 757 list_phys = prpmem_phys; 758 prp_list = prpmem; 759 for (i = 0; i < qpair->num_trackers; i++) { 760 761 if (list_phys + prpsz > prpmem_phys + prpmemsz) { 762 qpair->num_trackers = i; 763 break; 764 } 765 766 /* 767 * Make sure that the PRP list for this tracker doesn't 768 * overflow to another page. 769 */ 770 if (trunc_page(list_phys) != 771 trunc_page(list_phys + prpsz - 1)) { 772 list_phys = roundup2(list_phys, PAGE_SIZE); 773 prp_list = 774 (uint8_t *)roundup2((uintptr_t)prp_list, PAGE_SIZE); 775 } 776 777 tr = malloc_domainset(sizeof(*tr), M_NVME, 778 DOMAINSET_PREF(qpair->domain), M_ZERO | M_WAITOK); 779 bus_dmamap_create(qpair->dma_tag_payload, 0, 780 &tr->payload_dma_map); 781 callout_init(&tr->timer, 1); 782 tr->cid = i; 783 tr->qpair = qpair; 784 tr->prp = (uint64_t *)prp_list; 785 tr->prp_bus_addr = list_phys; 786 TAILQ_INSERT_HEAD(&qpair->free_tr, tr, tailq); 787 list_phys += prpsz; 788 prp_list += prpsz; 789 } 790 791 if (qpair->num_trackers == 0) { 792 nvme_printf(ctrlr, "failed to allocate enough trackers\n"); 793 goto out; 794 } 795 796 qpair->act_tr = malloc_domainset(sizeof(struct nvme_tracker *) * 797 qpair->num_entries, M_NVME, DOMAINSET_PREF(qpair->domain), 798 M_ZERO | M_WAITOK); 799 return (0); 800 801 out: 802 nvme_qpair_destroy(qpair); 803 return (ENOMEM); 804 } 805 806 static void 807 nvme_qpair_destroy(struct nvme_qpair *qpair) 808 { 809 struct nvme_tracker *tr; 810 811 if (qpair->tag) 812 bus_teardown_intr(qpair->ctrlr->dev, qpair->res, qpair->tag); 813 814 if (mtx_initialized(&qpair->lock)) 815 mtx_destroy(&qpair->lock); 816 817 if (qpair->res) 818 bus_release_resource(qpair->ctrlr->dev, SYS_RES_IRQ, 819 rman_get_rid(qpair->res), qpair->res); 820 821 if (qpair->cmd != NULL) { 822 bus_dmamap_unload(qpair->dma_tag, qpair->queuemem_map); 823 bus_dmamem_free(qpair->dma_tag, qpair->cmd, 824 qpair->queuemem_map); 825 } 826 827 if (qpair->act_tr) 828 free_domain(qpair->act_tr, M_NVME); 829 830 while (!TAILQ_EMPTY(&qpair->free_tr)) { 831 tr = TAILQ_FIRST(&qpair->free_tr); 832 TAILQ_REMOVE(&qpair->free_tr, tr, tailq); 833 bus_dmamap_destroy(qpair->dma_tag_payload, 834 tr->payload_dma_map); 835 free_domain(tr, M_NVME); 836 } 837 838 if (qpair->dma_tag) 839 bus_dma_tag_destroy(qpair->dma_tag); 840 841 if (qpair->dma_tag_payload) 842 bus_dma_tag_destroy(qpair->dma_tag_payload); 843 } 844 845 static void 846 nvme_admin_qpair_abort_aers(struct nvme_qpair *qpair) 847 { 848 struct nvme_tracker *tr; 849 850 tr = TAILQ_FIRST(&qpair->outstanding_tr); 851 while (tr != NULL) { 852 if (tr->req->cmd.opc == NVME_OPC_ASYNC_EVENT_REQUEST) { 853 nvme_qpair_manual_complete_tracker(tr, 854 NVME_SCT_GENERIC, NVME_SC_ABORTED_SQ_DELETION, 0, 855 ERROR_PRINT_NONE); 856 tr = TAILQ_FIRST(&qpair->outstanding_tr); 857 } else { 858 tr = TAILQ_NEXT(tr, tailq); 859 } 860 } 861 } 862 863 void 864 nvme_admin_qpair_destroy(struct nvme_qpair *qpair) 865 { 866 867 nvme_admin_qpair_abort_aers(qpair); 868 nvme_qpair_destroy(qpair); 869 } 870 871 void 872 nvme_io_qpair_destroy(struct nvme_qpair *qpair) 873 { 874 875 nvme_qpair_destroy(qpair); 876 } 877 878 static void 879 nvme_abort_complete(void *arg, const struct nvme_completion *status) 880 { 881 struct nvme_tracker *tr = arg; 882 883 /* 884 * If cdw0 == 1, the controller was not able to abort the command 885 * we requested. We still need to check the active tracker array, 886 * to cover race where I/O timed out at same time controller was 887 * completing the I/O. 888 */ 889 if (status->cdw0 == 1 && tr->qpair->act_tr[tr->cid] != NULL) { 890 /* 891 * An I/O has timed out, and the controller was unable to 892 * abort it for some reason. Construct a fake completion 893 * status, and then complete the I/O's tracker manually. 894 */ 895 nvme_printf(tr->qpair->ctrlr, 896 "abort command failed, aborting command manually\n"); 897 nvme_qpair_manual_complete_tracker(tr, 898 NVME_SCT_GENERIC, NVME_SC_ABORTED_BY_REQUEST, 0, ERROR_PRINT_ALL); 899 } 900 } 901 902 static void 903 nvme_timeout(void *arg) 904 { 905 struct nvme_tracker *tr = arg; 906 struct nvme_qpair *qpair = tr->qpair; 907 struct nvme_controller *ctrlr = qpair->ctrlr; 908 uint32_t csts; 909 uint8_t cfs; 910 911 /* 912 * Read csts to get value of cfs - controller fatal status. 913 * If no fatal status, try to call the completion routine, and 914 * if completes transactions, report a missed interrupt and 915 * return (this may need to be rate limited). Otherwise, if 916 * aborts are enabled and the controller is not reporting 917 * fatal status, abort the command. Otherwise, just reset the 918 * controller and hope for the best. 919 */ 920 csts = nvme_mmio_read_4(ctrlr, csts); 921 cfs = (csts >> NVME_CSTS_REG_CFS_SHIFT) & NVME_CSTS_REG_CFS_MASK; 922 if (cfs == 0 && nvme_qpair_process_completions(qpair)) { 923 nvme_printf(ctrlr, "Missing interrupt\n"); 924 return; 925 } 926 if (ctrlr->enable_aborts && cfs == 0) { 927 nvme_printf(ctrlr, "Aborting command due to a timeout.\n"); 928 nvme_ctrlr_cmd_abort(ctrlr, tr->cid, qpair->id, 929 nvme_abort_complete, tr); 930 } else { 931 nvme_printf(ctrlr, "Resetting controller due to a timeout%s.\n", 932 (csts == 0xffffffff) ? " and possible hot unplug" : 933 (cfs ? " and fatal error status" : "")); 934 nvme_ctrlr_reset(ctrlr); 935 } 936 } 937 938 void 939 nvme_qpair_submit_tracker(struct nvme_qpair *qpair, struct nvme_tracker *tr) 940 { 941 struct nvme_request *req; 942 struct nvme_controller *ctrlr; 943 944 mtx_assert(&qpair->lock, MA_OWNED); 945 946 req = tr->req; 947 req->cmd.cid = tr->cid; 948 qpair->act_tr[tr->cid] = tr; 949 ctrlr = qpair->ctrlr; 950 951 if (req->timeout) 952 callout_reset_on(&tr->timer, ctrlr->timeout_period * hz, 953 nvme_timeout, tr, qpair->cpu); 954 955 /* Copy the command from the tracker to the submission queue. */ 956 memcpy(&qpair->cmd[qpair->sq_tail], &req->cmd, sizeof(req->cmd)); 957 958 if (++qpair->sq_tail == qpair->num_entries) 959 qpair->sq_tail = 0; 960 961 bus_dmamap_sync(qpair->dma_tag, qpair->queuemem_map, 962 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 963 #ifndef __powerpc__ 964 /* 965 * powerpc's bus_dmamap_sync() already includes a heavyweight sync, but 966 * no other archs do. 967 */ 968 wmb(); 969 #endif 970 971 bus_space_write_4(qpair->ctrlr->bus_tag, qpair->ctrlr->bus_handle, 972 qpair->sq_tdbl_off, qpair->sq_tail); 973 qpair->num_cmds++; 974 } 975 976 static void 977 nvme_payload_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 978 { 979 struct nvme_tracker *tr = arg; 980 uint32_t cur_nseg; 981 982 /* 983 * If the mapping operation failed, return immediately. The caller 984 * is responsible for detecting the error status and failing the 985 * tracker manually. 986 */ 987 if (error != 0) { 988 nvme_printf(tr->qpair->ctrlr, 989 "nvme_payload_map err %d\n", error); 990 return; 991 } 992 993 /* 994 * Note that we specified PAGE_SIZE for alignment and max 995 * segment size when creating the bus dma tags. So here 996 * we can safely just transfer each segment to its 997 * associated PRP entry. 998 */ 999 tr->req->cmd.prp1 = htole64(seg[0].ds_addr); 1000 1001 if (nseg == 2) { 1002 tr->req->cmd.prp2 = htole64(seg[1].ds_addr); 1003 } else if (nseg > 2) { 1004 cur_nseg = 1; 1005 tr->req->cmd.prp2 = htole64((uint64_t)tr->prp_bus_addr); 1006 while (cur_nseg < nseg) { 1007 tr->prp[cur_nseg-1] = 1008 htole64((uint64_t)seg[cur_nseg].ds_addr); 1009 cur_nseg++; 1010 } 1011 } else { 1012 /* 1013 * prp2 should not be used by the controller 1014 * since there is only one segment, but set 1015 * to 0 just to be safe. 1016 */ 1017 tr->req->cmd.prp2 = 0; 1018 } 1019 1020 bus_dmamap_sync(tr->qpair->dma_tag_payload, tr->payload_dma_map, 1021 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1022 nvme_qpair_submit_tracker(tr->qpair, tr); 1023 } 1024 1025 static void 1026 _nvme_qpair_submit_request(struct nvme_qpair *qpair, struct nvme_request *req) 1027 { 1028 struct nvme_tracker *tr; 1029 int err = 0; 1030 1031 mtx_assert(&qpair->lock, MA_OWNED); 1032 1033 tr = TAILQ_FIRST(&qpair->free_tr); 1034 req->qpair = qpair; 1035 1036 if (tr == NULL || !qpair->is_enabled) { 1037 /* 1038 * No tracker is available, or the qpair is disabled due to 1039 * an in-progress controller-level reset or controller 1040 * failure. 1041 */ 1042 1043 if (qpair->ctrlr->is_failed) { 1044 /* 1045 * The controller has failed. Post the request to a 1046 * task where it will be aborted, so that we do not 1047 * invoke the request's callback in the context 1048 * of the submission. 1049 */ 1050 nvme_ctrlr_post_failed_request(qpair->ctrlr, req); 1051 } else { 1052 /* 1053 * Put the request on the qpair's request queue to be 1054 * processed when a tracker frees up via a command 1055 * completion or when the controller reset is 1056 * completed. 1057 */ 1058 STAILQ_INSERT_TAIL(&qpair->queued_req, req, stailq); 1059 } 1060 return; 1061 } 1062 1063 TAILQ_REMOVE(&qpair->free_tr, tr, tailq); 1064 TAILQ_INSERT_TAIL(&qpair->outstanding_tr, tr, tailq); 1065 tr->req = req; 1066 1067 switch (req->type) { 1068 case NVME_REQUEST_VADDR: 1069 KASSERT(req->payload_size <= qpair->ctrlr->max_xfer_size, 1070 ("payload_size (%d) exceeds max_xfer_size (%d)\n", 1071 req->payload_size, qpair->ctrlr->max_xfer_size)); 1072 err = bus_dmamap_load(tr->qpair->dma_tag_payload, 1073 tr->payload_dma_map, req->u.payload, req->payload_size, 1074 nvme_payload_map, tr, 0); 1075 if (err != 0) 1076 nvme_printf(qpair->ctrlr, 1077 "bus_dmamap_load returned 0x%x!\n", err); 1078 break; 1079 case NVME_REQUEST_NULL: 1080 nvme_qpair_submit_tracker(tr->qpair, tr); 1081 break; 1082 case NVME_REQUEST_BIO: 1083 KASSERT(req->u.bio->bio_bcount <= qpair->ctrlr->max_xfer_size, 1084 ("bio->bio_bcount (%jd) exceeds max_xfer_size (%d)\n", 1085 (intmax_t)req->u.bio->bio_bcount, 1086 qpair->ctrlr->max_xfer_size)); 1087 err = bus_dmamap_load_bio(tr->qpair->dma_tag_payload, 1088 tr->payload_dma_map, req->u.bio, nvme_payload_map, tr, 0); 1089 if (err != 0) 1090 nvme_printf(qpair->ctrlr, 1091 "bus_dmamap_load_bio returned 0x%x!\n", err); 1092 break; 1093 case NVME_REQUEST_CCB: 1094 err = bus_dmamap_load_ccb(tr->qpair->dma_tag_payload, 1095 tr->payload_dma_map, req->u.payload, 1096 nvme_payload_map, tr, 0); 1097 if (err != 0) 1098 nvme_printf(qpair->ctrlr, 1099 "bus_dmamap_load_ccb returned 0x%x!\n", err); 1100 break; 1101 default: 1102 panic("unknown nvme request type 0x%x\n", req->type); 1103 break; 1104 } 1105 1106 if (err != 0) { 1107 /* 1108 * The dmamap operation failed, so we manually fail the 1109 * tracker here with DATA_TRANSFER_ERROR status. 1110 * 1111 * nvme_qpair_manual_complete_tracker must not be called 1112 * with the qpair lock held. 1113 */ 1114 mtx_unlock(&qpair->lock); 1115 nvme_qpair_manual_complete_tracker(tr, NVME_SCT_GENERIC, 1116 NVME_SC_DATA_TRANSFER_ERROR, DO_NOT_RETRY, ERROR_PRINT_ALL); 1117 mtx_lock(&qpair->lock); 1118 } 1119 } 1120 1121 void 1122 nvme_qpair_submit_request(struct nvme_qpair *qpair, struct nvme_request *req) 1123 { 1124 1125 mtx_lock(&qpair->lock); 1126 _nvme_qpair_submit_request(qpair, req); 1127 mtx_unlock(&qpair->lock); 1128 } 1129 1130 static void 1131 nvme_qpair_enable(struct nvme_qpair *qpair) 1132 { 1133 1134 qpair->is_enabled = true; 1135 } 1136 1137 void 1138 nvme_qpair_reset(struct nvme_qpair *qpair) 1139 { 1140 1141 qpair->sq_head = qpair->sq_tail = qpair->cq_head = 0; 1142 1143 /* 1144 * First time through the completion queue, HW will set phase 1145 * bit on completions to 1. So set this to 1 here, indicating 1146 * we're looking for a 1 to know which entries have completed. 1147 * we'll toggle the bit each time when the completion queue 1148 * rolls over. 1149 */ 1150 qpair->phase = 1; 1151 1152 memset(qpair->cmd, 0, 1153 qpair->num_entries * sizeof(struct nvme_command)); 1154 memset(qpair->cpl, 0, 1155 qpair->num_entries * sizeof(struct nvme_completion)); 1156 } 1157 1158 void 1159 nvme_admin_qpair_enable(struct nvme_qpair *qpair) 1160 { 1161 struct nvme_tracker *tr; 1162 struct nvme_tracker *tr_temp; 1163 1164 /* 1165 * Manually abort each outstanding admin command. Do not retry 1166 * admin commands found here, since they will be left over from 1167 * a controller reset and its likely the context in which the 1168 * command was issued no longer applies. 1169 */ 1170 TAILQ_FOREACH_SAFE(tr, &qpair->outstanding_tr, tailq, tr_temp) { 1171 nvme_printf(qpair->ctrlr, 1172 "aborting outstanding admin command\n"); 1173 nvme_qpair_manual_complete_tracker(tr, NVME_SCT_GENERIC, 1174 NVME_SC_ABORTED_BY_REQUEST, DO_NOT_RETRY, ERROR_PRINT_ALL); 1175 } 1176 1177 nvme_qpair_enable(qpair); 1178 } 1179 1180 void 1181 nvme_io_qpair_enable(struct nvme_qpair *qpair) 1182 { 1183 STAILQ_HEAD(, nvme_request) temp; 1184 struct nvme_tracker *tr; 1185 struct nvme_tracker *tr_temp; 1186 struct nvme_request *req; 1187 1188 /* 1189 * Manually abort each outstanding I/O. This normally results in a 1190 * retry, unless the retry count on the associated request has 1191 * reached its limit. 1192 */ 1193 TAILQ_FOREACH_SAFE(tr, &qpair->outstanding_tr, tailq, tr_temp) { 1194 nvme_printf(qpair->ctrlr, "aborting outstanding i/o\n"); 1195 nvme_qpair_manual_complete_tracker(tr, NVME_SCT_GENERIC, 1196 NVME_SC_ABORTED_BY_REQUEST, 0, ERROR_PRINT_NO_RETRY); 1197 } 1198 1199 mtx_lock(&qpair->lock); 1200 1201 nvme_qpair_enable(qpair); 1202 1203 STAILQ_INIT(&temp); 1204 STAILQ_SWAP(&qpair->queued_req, &temp, nvme_request); 1205 1206 while (!STAILQ_EMPTY(&temp)) { 1207 req = STAILQ_FIRST(&temp); 1208 STAILQ_REMOVE_HEAD(&temp, stailq); 1209 nvme_printf(qpair->ctrlr, "resubmitting queued i/o\n"); 1210 nvme_qpair_print_command(qpair, &req->cmd); 1211 _nvme_qpair_submit_request(qpair, req); 1212 } 1213 1214 mtx_unlock(&qpair->lock); 1215 } 1216 1217 static void 1218 nvme_qpair_disable(struct nvme_qpair *qpair) 1219 { 1220 struct nvme_tracker *tr; 1221 1222 qpair->is_enabled = false; 1223 mtx_lock(&qpair->lock); 1224 TAILQ_FOREACH(tr, &qpair->outstanding_tr, tailq) 1225 callout_stop(&tr->timer); 1226 mtx_unlock(&qpair->lock); 1227 } 1228 1229 void 1230 nvme_admin_qpair_disable(struct nvme_qpair *qpair) 1231 { 1232 1233 nvme_qpair_disable(qpair); 1234 nvme_admin_qpair_abort_aers(qpair); 1235 } 1236 1237 void 1238 nvme_io_qpair_disable(struct nvme_qpair *qpair) 1239 { 1240 1241 nvme_qpair_disable(qpair); 1242 } 1243 1244 void 1245 nvme_qpair_fail(struct nvme_qpair *qpair) 1246 { 1247 struct nvme_tracker *tr; 1248 struct nvme_request *req; 1249 1250 if (!mtx_initialized(&qpair->lock)) 1251 return; 1252 1253 mtx_lock(&qpair->lock); 1254 1255 while (!STAILQ_EMPTY(&qpair->queued_req)) { 1256 req = STAILQ_FIRST(&qpair->queued_req); 1257 STAILQ_REMOVE_HEAD(&qpair->queued_req, stailq); 1258 nvme_printf(qpair->ctrlr, "failing queued i/o\n"); 1259 mtx_unlock(&qpair->lock); 1260 nvme_qpair_manual_complete_request(qpair, req, NVME_SCT_GENERIC, 1261 NVME_SC_ABORTED_BY_REQUEST); 1262 mtx_lock(&qpair->lock); 1263 } 1264 1265 /* Manually abort each outstanding I/O. */ 1266 while (!TAILQ_EMPTY(&qpair->outstanding_tr)) { 1267 tr = TAILQ_FIRST(&qpair->outstanding_tr); 1268 /* 1269 * Do not remove the tracker. The abort_tracker path will 1270 * do that for us. 1271 */ 1272 nvme_printf(qpair->ctrlr, "failing outstanding i/o\n"); 1273 mtx_unlock(&qpair->lock); 1274 nvme_qpair_manual_complete_tracker(tr, NVME_SCT_GENERIC, 1275 NVME_SC_ABORTED_BY_REQUEST, DO_NOT_RETRY, ERROR_PRINT_ALL); 1276 mtx_lock(&qpair->lock); 1277 } 1278 1279 mtx_unlock(&qpair->lock); 1280 } 1281