1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2007-2022 Intel Corporation */ 3 /* $FreeBSD$ */ 4 #include "adf_accel_devices.h" 5 #include "adf_gen4vf_hw_csr_data.h" 6 7 static u64 8 build_csr_ring_base_addr(dma_addr_t addr, u32 size) 9 { 10 return BUILD_RING_BASE_ADDR_GEN4(addr, size); 11 } 12 13 static u32 14 read_csr_ring_head(struct resource *csr_base_addr, u32 bank, u32 ring) 15 { 16 return READ_CSR_RING_HEAD_GEN4VF(csr_base_addr, bank, ring); 17 } 18 19 static void 20 write_csr_ring_head(struct resource *csr_base_addr, 21 u32 bank, 22 u32 ring, 23 u32 value) 24 { 25 WRITE_CSR_RING_HEAD_GEN4VF(csr_base_addr, bank, ring, value); 26 } 27 28 static u32 29 read_csr_ring_tail(struct resource *csr_base_addr, u32 bank, u32 ring) 30 { 31 return READ_CSR_RING_TAIL_GEN4VF(csr_base_addr, bank, ring); 32 } 33 34 static void 35 write_csr_ring_tail(struct resource *csr_base_addr, 36 u32 bank, 37 u32 ring, 38 u32 value) 39 { 40 WRITE_CSR_RING_TAIL_GEN4VF(csr_base_addr, bank, ring, value); 41 } 42 43 static u32 44 read_csr_e_stat(struct resource *csr_base_addr, u32 bank) 45 { 46 return READ_CSR_E_STAT_GEN4VF(csr_base_addr, bank); 47 } 48 49 static void 50 write_csr_ring_config(struct resource *csr_base_addr, 51 u32 bank, 52 u32 ring, 53 u32 value) 54 { 55 WRITE_CSR_RING_CONFIG_GEN4VF(csr_base_addr, bank, ring, value); 56 } 57 58 static dma_addr_t 59 read_csr_ring_base(struct resource *csr_base_addr, u32 bank, u32 ring) 60 { 61 return READ_CSR_RING_BASE_GEN4VF(csr_base_addr, bank, ring); 62 } 63 64 static void 65 write_csr_ring_base(struct resource *csr_base_addr, 66 u32 bank, 67 u32 ring, 68 dma_addr_t addr) 69 { 70 WRITE_CSR_RING_BASE_GEN4VF(csr_base_addr, bank, ring, addr); 71 } 72 73 static void 74 write_csr_int_flag(struct resource *csr_base_addr, u32 bank, u32 value) 75 { 76 WRITE_CSR_INT_FLAG_GEN4VF(csr_base_addr, bank, value); 77 } 78 79 static void 80 write_csr_int_srcsel(struct resource *csr_base_addr, u32 bank) 81 { 82 WRITE_CSR_INT_SRCSEL_GEN4VF(csr_base_addr, bank); 83 } 84 85 static void 86 write_csr_int_col_en(struct resource *csr_base_addr, u32 bank, u32 value) 87 { 88 WRITE_CSR_INT_COL_EN_GEN4VF(csr_base_addr, bank, value); 89 } 90 91 static void 92 write_csr_int_col_ctl(struct resource *csr_base_addr, u32 bank, u32 value) 93 { 94 WRITE_CSR_INT_COL_CTL_GEN4VF(csr_base_addr, bank, value); 95 } 96 97 static void 98 write_csr_int_flag_and_col(struct resource *csr_base_addr, u32 bank, u32 value) 99 { 100 WRITE_CSR_INT_FLAG_AND_COL_GEN4VF(csr_base_addr, bank, value); 101 } 102 103 static u32 104 read_csr_ring_srv_arb_en(struct resource *csr_base_addr, u32 bank) 105 { 106 return READ_CSR_RING_SRV_ARB_EN_GEN4VF(csr_base_addr, bank); 107 } 108 109 static void 110 write_csr_ring_srv_arb_en(struct resource *csr_base_addr, u32 bank, u32 value) 111 { 112 WRITE_CSR_RING_SRV_ARB_EN_GEN4VF(csr_base_addr, bank, value); 113 } 114 115 static u32 116 get_src_sel_mask(void) 117 { 118 return ADF_BANK_INT_SRC_SEL_MASK_GEN4; 119 } 120 121 static u32 122 get_int_col_ctl_enable_mask(void) 123 { 124 return ADF_RING_CSR_INT_COL_CTL_ENABLE; 125 } 126 127 static u32 128 get_bank_irq_mask(u32 irq_mask) 129 { 130 return 0x1; 131 } 132 133 void 134 gen4vf_init_hw_csr_info(struct adf_hw_csr_info *csr_info) 135 { 136 struct adf_hw_csr_ops *csr_ops = &csr_info->csr_ops; 137 138 csr_info->csr_addr_offset = ADF_RING_CSR_ADDR_OFFSET_GEN4VF; 139 csr_info->ring_bundle_size = ADF_RING_BUNDLE_SIZE_GEN4; 140 csr_info->bank_int_flag_clear_mask = ADF_BANK_INT_FLAG_CLEAR_MASK_GEN4; 141 csr_info->num_rings_per_int_srcsel = ADF_RINGS_PER_INT_SRCSEL_GEN4; 142 csr_info->arb_enable_mask = 0x1; 143 csr_ops->build_csr_ring_base_addr = build_csr_ring_base_addr; 144 csr_ops->read_csr_ring_head = read_csr_ring_head; 145 csr_ops->write_csr_ring_head = write_csr_ring_head; 146 csr_ops->read_csr_ring_tail = read_csr_ring_tail; 147 csr_ops->write_csr_ring_tail = write_csr_ring_tail; 148 csr_ops->read_csr_e_stat = read_csr_e_stat; 149 csr_ops->write_csr_ring_config = write_csr_ring_config; 150 csr_ops->read_csr_ring_base = read_csr_ring_base; 151 csr_ops->write_csr_ring_base = write_csr_ring_base; 152 csr_ops->write_csr_int_flag = write_csr_int_flag; 153 csr_ops->write_csr_int_srcsel = write_csr_int_srcsel; 154 csr_ops->write_csr_int_col_en = write_csr_int_col_en; 155 csr_ops->write_csr_int_col_ctl = write_csr_int_col_ctl; 156 csr_ops->write_csr_int_flag_and_col = write_csr_int_flag_and_col; 157 csr_ops->read_csr_ring_srv_arb_en = read_csr_ring_srv_arb_en; 158 csr_ops->write_csr_ring_srv_arb_en = write_csr_ring_srv_arb_en; 159 csr_ops->get_src_sel_mask = get_src_sel_mask; 160 csr_ops->get_int_col_ctl_enable_mask = get_int_col_ctl_enable_mask; 161 csr_ops->get_bank_irq_mask = get_bank_irq_mask; 162 } 163