1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2021, Adrian Chadd <adrian@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* Driver for Qualcomm IPQ4018 clock and reset device */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/malloc.h> 36 #include <sys/module.h> 37 #include <sys/sglist.h> 38 #include <sys/random.h> 39 #include <sys/stdatomic.h> 40 #include <sys/mutex.h> 41 42 #include <machine/bus.h> 43 #include <machine/resource.h> 44 #include <sys/bus.h> 45 46 #include <dev/fdt/fdt_common.h> 47 #include <dev/ofw/ofw_bus.h> 48 #include <dev/ofw/ofw_bus_subr.h> 49 50 #include <dev/extres/hwreset/hwreset.h> 51 52 #include "clkdev_if.h" 53 #include "hwreset_if.h" 54 55 #include <dt-bindings/clock/qcom,gcc-ipq4019.h> 56 57 #include "qcom_gcc_ipq4018_var.h" 58 59 60 static int qcom_gcc_ipq4018_modevent(module_t, int, void *); 61 62 static int qcom_gcc_ipq4018_probe(device_t); 63 static int qcom_gcc_ipq4018_attach(device_t); 64 static int qcom_gcc_ipq4018_detach(device_t); 65 66 static int 67 qcom_gcc_ipq4018_modevent(module_t mod, int type, void *unused) 68 { 69 int error; 70 71 switch (type) { 72 case MOD_LOAD: 73 case MOD_QUIESCE: 74 case MOD_UNLOAD: 75 case MOD_SHUTDOWN: 76 error = 0; 77 break; 78 default: 79 error = EOPNOTSUPP; 80 break; 81 } 82 83 return (error); 84 } 85 86 static int 87 qcom_gcc_ipq4018_probe(device_t dev) 88 { 89 if (! ofw_bus_status_okay(dev)) 90 return (ENXIO); 91 92 if (ofw_bus_is_compatible(dev, "qcom,gcc-ipq4019") == 0) 93 return (ENXIO); 94 95 return (0); 96 } 97 98 static int 99 qcom_gcc_ipq4018_attach(device_t dev) 100 { 101 struct qcom_gcc_ipq4018_softc *sc; 102 103 sc = device_get_softc(dev); 104 105 /* Found a compatible device! */ 106 sc->dev = dev; 107 108 sc->reg_rid = 0; 109 sc->reg = bus_alloc_resource_anywhere(dev, SYS_RES_MEMORY, 110 &sc->reg_rid, 0x60000, RF_ACTIVE); 111 if (sc->reg == NULL) { 112 device_printf(dev, "Couldn't allocate memory resource!\n"); 113 return (ENXIO); 114 } 115 116 device_set_desc(dev, "Qualcomm IPQ4018 Clock/Reset Controller"); 117 118 mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); 119 120 /* 121 * Register as a reset provider. 122 */ 123 hwreset_register_ofw_provider(dev); 124 125 /* 126 * Setup and register as a clock provider. 127 */ 128 qcom_gcc_ipq4018_clock_setup(sc); 129 130 return (0); 131 } 132 133 static int 134 qcom_gcc_ipq4018_detach(device_t dev) 135 { 136 struct qcom_gcc_ipq4018_softc *sc; 137 138 sc = device_get_softc(dev); 139 140 /* 141 * TBD - deregistering reset/clock resources. 142 */ 143 144 if (sc->reg != NULL) { 145 bus_release_resource(sc->dev, SYS_RES_MEMORY, 146 sc->reg_rid, sc->reg); 147 } 148 return (0); 149 } 150 151 static device_method_t qcom_gcc_ipq4018_methods[] = { 152 /* Device methods. */ 153 DEVMETHOD(device_probe, qcom_gcc_ipq4018_probe), 154 DEVMETHOD(device_attach, qcom_gcc_ipq4018_attach), 155 DEVMETHOD(device_detach, qcom_gcc_ipq4018_detach), 156 157 /* Reset interface */ 158 DEVMETHOD(hwreset_assert, qcom_gcc_ipq4018_hwreset_assert), 159 DEVMETHOD(hwreset_is_asserted, qcom_gcc_ipq4018_hwreset_is_asserted), 160 161 /* Clock interface */ 162 DEVMETHOD(clkdev_read_4, qcom_gcc_ipq4018_clock_read), 163 DEVMETHOD(clkdev_write_4, qcom_gcc_ipq4018_clock_write), 164 DEVMETHOD(clkdev_modify_4, qcom_gcc_ipq4018_clock_modify), 165 DEVMETHOD(clkdev_device_lock, qcom_gcc_ipq4018_clock_lock), 166 DEVMETHOD(clkdev_device_unlock, qcom_gcc_ipq4018_clock_unlock), 167 168 DEVMETHOD_END 169 }; 170 171 static driver_t qcom_gcc_ipq4018_driver = { 172 "qcom_gcc", 173 qcom_gcc_ipq4018_methods, 174 sizeof(struct qcom_gcc_ipq4018_softc) 175 }; 176 177 EARLY_DRIVER_MODULE(qcom_gcc_ipq4018, simplebus, qcom_gcc_ipq4018_driver, 178 qcom_gcc_ipq4018_modevent, NULL, BUS_PASS_CPU + BUS_PASS_ORDER_EARLY); 179 EARLY_DRIVER_MODULE(qcom_gcc_ipq4018, ofwbus, qcom_gcc_ipq4018_driver, 180 qcom_gcc_ipq4018_modevent, NULL, BUS_PASS_CPU + BUS_PASS_ORDER_EARLY); 181 MODULE_VERSION(qcom_gcc_ipq4018, 1); 182