1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011-2013 Qlogic Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * File: qla_isr.c 32 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656. 33 */ 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD$"); 37 38 #include "qla_os.h" 39 #include "qla_reg.h" 40 #include "qla_hw.h" 41 #include "qla_def.h" 42 #include "qla_inline.h" 43 #include "qla_ver.h" 44 #include "qla_glbl.h" 45 #include "qla_dbg.h" 46 47 static void qla_replenish_normal_rx(qla_host_t *ha, qla_sds_t *sdsp); 48 static void qla_replenish_jumbo_rx(qla_host_t *ha, qla_sds_t *sdsp); 49 50 /* 51 * Name: qla_rx_intr 52 * Function: Handles normal ethernet frames received 53 */ 54 static void 55 qla_rx_intr(qla_host_t *ha, uint64_t data, uint32_t sds_idx, 56 struct lro_ctrl *lro) 57 { 58 uint32_t idx, length, status, ring; 59 qla_rx_buf_t *rxb; 60 struct mbuf *mp; 61 struct ifnet *ifp = ha->ifp; 62 qla_sds_t *sdsp; 63 struct ether_vlan_header *eh; 64 65 sdsp = &ha->hw.sds[sds_idx]; 66 67 ring = (uint32_t)Q8_STAT_DESC_TYPE(data); 68 idx = (uint32_t)Q8_STAT_DESC_HANDLE(data); 69 length = (uint32_t)Q8_STAT_DESC_TOTAL_LENGTH(data); 70 status = (uint32_t)Q8_STAT_DESC_STATUS(data); 71 72 if (ring == 0) { 73 if ((idx >= NUM_RX_DESCRIPTORS) || (length > MCLBYTES)) { 74 device_printf(ha->pci_dev, "%s: ring[%d] index[0x%08x]" 75 " len[0x%08x] invalid\n", 76 __func__, ring, idx, length); 77 return; 78 } 79 } else { 80 if ((idx >= NUM_RX_JUMBO_DESCRIPTORS)||(length > MJUM9BYTES)) { 81 device_printf(ha->pci_dev, "%s: ring[%d] index[0x%08x]" 82 " len[0x%08x] invalid\n", 83 __func__, ring, idx, length); 84 return; 85 } 86 } 87 88 if (ring == 0) 89 rxb = &ha->rx_buf[idx]; 90 else 91 rxb = &ha->rx_jbuf[idx]; 92 93 QL_ASSERT((rxb != NULL),\ 94 ("%s: [r, i, sds_idx]=[%d, 0x%x, %d] rxb != NULL\n",\ 95 __func__, ring, idx, sds_idx)); 96 97 mp = rxb->m_head; 98 99 QL_ASSERT((mp != NULL),\ 100 ("%s: [r,i,rxb, sds_idx]=[%d, 0x%x, %p, %d] mp != NULL\n",\ 101 __func__, ring, idx, rxb, sds_idx)); 102 103 bus_dmamap_sync(ha->rx_tag, rxb->map, BUS_DMASYNC_POSTREAD); 104 105 if (ring == 0) { 106 rxb->m_head = NULL; 107 rxb->next = sdsp->rxb_free; 108 sdsp->rxb_free = rxb; 109 sdsp->rx_free++; 110 } else { 111 rxb->m_head = NULL; 112 rxb->next = sdsp->rxjb_free; 113 sdsp->rxjb_free = rxb; 114 sdsp->rxj_free++; 115 } 116 117 mp->m_len = length; 118 mp->m_pkthdr.len = length; 119 mp->m_pkthdr.rcvif = ifp; 120 121 eh = mtod(mp, struct ether_vlan_header *); 122 123 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 124 uint32_t *data = (uint32_t *)eh; 125 126 mp->m_pkthdr.ether_vtag = ntohs(eh->evl_tag); 127 mp->m_flags |= M_VLANTAG; 128 129 *(data + 3) = *(data + 2); 130 *(data + 2) = *(data + 1); 131 *(data + 1) = *data; 132 133 m_adj(mp, ETHER_VLAN_ENCAP_LEN); 134 } 135 136 if (status == Q8_STAT_DESC_STATUS_CHKSUM_OK) { 137 mp->m_pkthdr.csum_flags = (CSUM_IP_CHECKED | CSUM_IP_VALID); 138 } else { 139 mp->m_pkthdr.csum_flags = 0; 140 } 141 142 if (lro->lro_cnt && (tcp_lro_rx(lro, mp, 0) == 0)) { 143 /* LRO packet has been successfully queued */ 144 } else { 145 (*ifp->if_input)(ifp, mp); 146 } 147 148 if (sdsp->rx_free > std_replenish) 149 qla_replenish_normal_rx(ha, sdsp); 150 151 if (sdsp->rxj_free > jumbo_replenish) 152 qla_replenish_jumbo_rx(ha, sdsp); 153 154 return; 155 } 156 157 static void 158 qla_replenish_jumbo_rx(qla_host_t *ha, qla_sds_t *sdsp) 159 { 160 qla_rx_buf_t *rxb; 161 int count = jumbo_replenish; 162 uint32_t rxj_next; 163 164 if (!mtx_trylock(&ha->rxj_lock)) 165 return; 166 167 rxj_next = ha->hw.rxj_next; 168 169 while (count--) { 170 rxb = sdsp->rxjb_free; 171 172 if (rxb == NULL) 173 break; 174 175 sdsp->rxjb_free = rxb->next; 176 sdsp->rxj_free--; 177 178 if (qla_get_mbuf(ha, rxb, NULL, RDS_RING_INDEX_JUMBO) == 0) { 179 qla_set_hw_rcv_desc(ha, RDS_RING_INDEX_JUMBO, 180 ha->hw.rxj_in, rxb->handle, rxb->paddr, 181 (rxb->m_head)->m_pkthdr.len); 182 ha->hw.rxj_in++; 183 if (ha->hw.rxj_in == NUM_RX_JUMBO_DESCRIPTORS) 184 ha->hw.rxj_in = 0; 185 ha->hw.rxj_next++; 186 if (ha->hw.rxj_next == NUM_RX_JUMBO_DESCRIPTORS) 187 ha->hw.rxj_next = 0; 188 } else { 189 device_printf(ha->pci_dev, 190 "%s: qla_get_mbuf [1,(%d),(%d)] failed\n", 191 __func__, ha->hw.rxj_in, rxb->handle); 192 193 rxb->m_head = NULL; 194 rxb->next = sdsp->rxjb_free; 195 sdsp->rxjb_free = rxb; 196 sdsp->rxj_free++; 197 198 break; 199 } 200 } 201 202 if (rxj_next != ha->hw.rxj_next) { 203 QL_UPDATE_RDS_PRODUCER_INDEX(ha, 1, ha->hw.rxj_next); 204 } 205 mtx_unlock(&ha->rxj_lock); 206 } 207 208 static void 209 qla_replenish_normal_rx(qla_host_t *ha, qla_sds_t *sdsp) 210 { 211 qla_rx_buf_t *rxb; 212 int count = std_replenish; 213 uint32_t rx_next; 214 215 if (!mtx_trylock(&ha->rx_lock)) 216 return; 217 218 rx_next = ha->hw.rx_next; 219 220 while (count--) { 221 rxb = sdsp->rxb_free; 222 223 if (rxb == NULL) 224 break; 225 226 sdsp->rxb_free = rxb->next; 227 sdsp->rx_free--; 228 229 if (qla_get_mbuf(ha, rxb, NULL, RDS_RING_INDEX_NORMAL) == 0) { 230 qla_set_hw_rcv_desc(ha, RDS_RING_INDEX_NORMAL, 231 ha->hw.rx_in, rxb->handle, rxb->paddr, 232 (rxb->m_head)->m_pkthdr.len); 233 ha->hw.rx_in++; 234 if (ha->hw.rx_in == NUM_RX_DESCRIPTORS) 235 ha->hw.rx_in = 0; 236 ha->hw.rx_next++; 237 if (ha->hw.rx_next == NUM_RX_DESCRIPTORS) 238 ha->hw.rx_next = 0; 239 } else { 240 device_printf(ha->pci_dev, 241 "%s: qla_get_mbuf [0,(%d),(%d)] failed\n", 242 __func__, ha->hw.rx_in, rxb->handle); 243 244 rxb->m_head = NULL; 245 rxb->next = sdsp->rxb_free; 246 sdsp->rxb_free = rxb; 247 sdsp->rx_free++; 248 249 break; 250 } 251 } 252 253 if (rx_next != ha->hw.rx_next) { 254 QL_UPDATE_RDS_PRODUCER_INDEX(ha, 0, ha->hw.rx_next); 255 } 256 mtx_unlock(&ha->rx_lock); 257 } 258 259 /* 260 * Name: qla_isr 261 * Function: Main Interrupt Service Routine 262 */ 263 static uint32_t 264 qla_rcv_isr(qla_host_t *ha, uint32_t sds_idx, uint32_t count) 265 { 266 device_t dev; 267 qla_hw_t *hw; 268 uint32_t comp_idx, desc_count; 269 q80_stat_desc_t *sdesc; 270 struct lro_ctrl *lro; 271 uint32_t ret = 0; 272 273 dev = ha->pci_dev; 274 hw = &ha->hw; 275 276 hw->sds[sds_idx].rcv_active = 1; 277 if (ha->flags.stop_rcv) { 278 hw->sds[sds_idx].rcv_active = 0; 279 return 0; 280 } 281 282 QL_DPRINT2((dev, "%s: [%d]enter\n", __func__, sds_idx)); 283 284 /* 285 * receive interrupts 286 */ 287 comp_idx = hw->sds[sds_idx].sdsr_next; 288 lro = &hw->sds[sds_idx].lro; 289 290 while (count--) { 291 sdesc = (q80_stat_desc_t *) 292 &hw->sds[sds_idx].sds_ring_base[comp_idx]; 293 294 if (Q8_STAT_DESC_OWNER((sdesc->data[0])) != 295 Q8_STAT_DESC_OWNER_HOST) { 296 QL_DPRINT2((dev, "%s: data %p sdsr_next 0x%08x\n", 297 __func__, (void *)sdesc->data[0], comp_idx)); 298 break; 299 } 300 301 desc_count = Q8_STAT_DESC_COUNT((sdesc->data[0])); 302 303 switch (Q8_STAT_DESC_OPCODE((sdesc->data[0]))) { 304 case Q8_STAT_DESC_OPCODE_RCV_PKT: 305 case Q8_STAT_DESC_OPCODE_SYN_OFFLOAD: 306 qla_rx_intr(ha, (sdesc->data[0]), sds_idx, lro); 307 308 break; 309 310 default: 311 device_printf(dev, "%s: default 0x%llx!\n", __func__, 312 (long long unsigned int)sdesc->data[0]); 313 break; 314 } 315 316 while (desc_count--) { 317 sdesc->data[0] = 318 Q8_STAT_DESC_SET_OWNER(Q8_STAT_DESC_OWNER_FW); 319 comp_idx = (comp_idx + 1) & (NUM_STATUS_DESCRIPTORS-1); 320 sdesc = (q80_stat_desc_t *) 321 &hw->sds[sds_idx].sds_ring_base[comp_idx]; 322 } 323 } 324 325 tcp_lro_flush_all(lro); 326 327 if (hw->sds[sds_idx].sdsr_next != comp_idx) { 328 QL_UPDATE_SDS_CONSUMER_INDEX(ha, sds_idx, comp_idx); 329 } 330 hw->sds[sds_idx].sdsr_next = comp_idx; 331 332 sdesc = (q80_stat_desc_t *)&hw->sds[sds_idx].sds_ring_base[comp_idx]; 333 if ((sds_idx == 0) && (Q8_STAT_DESC_OWNER((sdesc->data[0])) == 334 Q8_STAT_DESC_OWNER_HOST)) { 335 ret = -1; 336 } 337 338 hw->sds[sds_idx].rcv_active = 0; 339 return (ret); 340 } 341 342 void 343 qla_isr(void *arg) 344 { 345 qla_ivec_t *ivec = arg; 346 qla_host_t *ha; 347 uint32_t sds_idx; 348 uint32_t ret; 349 350 ha = ivec->ha; 351 sds_idx = ivec->irq_rid - 1; 352 353 if (sds_idx >= ha->hw.num_sds_rings) { 354 device_printf(ha->pci_dev, "%s: bogus sds_idx 0x%x\n", __func__, 355 sds_idx); 356 357 return; 358 } 359 360 if (sds_idx == 0) 361 taskqueue_enqueue(ha->tx_tq, &ha->tx_task); 362 363 ret = qla_rcv_isr(ha, sds_idx, rcv_pkt_thres); 364 365 if (sds_idx == 0) 366 taskqueue_enqueue(ha->tx_tq, &ha->tx_task); 367 368 if (ret) { 369 taskqueue_enqueue(ha->irq_vec[sds_idx].rcv_tq, 370 &ha->irq_vec[sds_idx].rcv_task); 371 } else { 372 QL_ENABLE_INTERRUPTS(ha, sds_idx); 373 } 374 } 375 376 void 377 qla_rcv(void *context, int pending) 378 { 379 qla_ivec_t *ivec = context; 380 qla_host_t *ha; 381 qla_hw_t *hw; 382 uint32_t sds_idx; 383 uint32_t ret; 384 struct ifnet *ifp; 385 386 ha = ivec->ha; 387 hw = &ha->hw; 388 sds_idx = ivec->irq_rid - 1; 389 ifp = ha->ifp; 390 391 do { 392 if (sds_idx == 0) { 393 if (qla_le32_to_host(*(hw->tx_cons)) != hw->txr_comp) { 394 taskqueue_enqueue(ha->tx_tq, &ha->tx_task); 395 } else if ((ifp->if_snd.ifq_head != NULL) && 396 QL_RUNNING(ifp)) { 397 taskqueue_enqueue(ha->tx_tq, &ha->tx_task); 398 } 399 } 400 ret = qla_rcv_isr(ha, sds_idx, rcv_pkt_thres_d); 401 } while (ret); 402 403 if (sds_idx == 0) 404 taskqueue_enqueue(ha->tx_tq, &ha->tx_task); 405 406 QL_ENABLE_INTERRUPTS(ha, sds_idx); 407 } 408