1 /*- 2 * Copyright (c) 2016 Andriy Voskoboinyk <avos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 #include "opt_wlan.h" 29 30 #include <sys/param.h> 31 #include <sys/lock.h> 32 #include <sys/mutex.h> 33 #include <sys/mbuf.h> 34 #include <sys/kernel.h> 35 #include <sys/socket.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #include <sys/queue.h> 39 #include <sys/taskqueue.h> 40 #include <sys/bus.h> 41 #include <sys/endian.h> 42 #include <sys/linker.h> 43 44 #include <net/if.h> 45 #include <net/ethernet.h> 46 #include <net/if_media.h> 47 48 #include <net80211/ieee80211_var.h> 49 #include <net80211/ieee80211_radiotap.h> 50 51 #include <dev/rtwn/if_rtwnreg.h> 52 #include <dev/rtwn/if_rtwnvar.h> 53 54 #include <dev/rtwn/if_rtwn_debug.h> 55 56 #include <dev/rtwn/rtl8812a/r12a.h> 57 #include <dev/rtwn/rtl8812a/r12a_priv.h> 58 #include <dev/rtwn/rtl8812a/r12a_reg.h> 59 #include <dev/rtwn/rtl8812a/r12a_var.h> 60 61 void 62 r12a_lc_calib(struct rtwn_softc *sc) 63 { 64 uint32_t chnlbw; 65 uint8_t txmode; 66 67 RTWN_DPRINTF(sc, RTWN_DEBUG_CALIB, 68 "%s: LC calibration started\n", __func__); 69 70 txmode = rtwn_read_1(sc, R12A_SINGLETONE_CONT_TX + 2); 71 72 if ((txmode & 0x07) != 0) { 73 /* Disable all continuous Tx. */ 74 /* 75 * Skipped because BB turns off continuous Tx until 76 * next packet comes in. 77 */ 78 } else { 79 /* Block all Tx queues. */ 80 rtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL); 81 } 82 83 /* Enter LCK mode. */ 84 rtwn_rf_setbits(sc, 0, R12A_RF_LCK, 0, R12A_RF_LCK_MODE); 85 86 /* Start calibration. */ 87 chnlbw = rtwn_rf_read(sc, 0, R92C_RF_CHNLBW); 88 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, chnlbw | R92C_RF_CHNLBW_LCSTART); 89 90 /* Give calibration the time to complete. */ 91 rtwn_delay(sc, 150000); /* 150 ms */ 92 93 /* Leave LCK mode. */ 94 rtwn_rf_setbits(sc, 0, R12A_RF_LCK, R12A_RF_LCK_MODE, 0); 95 96 /* Restore configuration. */ 97 if ((txmode & 0x07) != 0) { 98 /* Continuous Tx case. */ 99 /* 100 * Skipped because BB turns off continuous Tx until 101 * next packet comes in. 102 */ 103 } else { 104 /* Unblock all Tx queues. */ 105 rtwn_write_1(sc, R92C_TXPAUSE, 0); 106 } 107 108 /* Recover channel number. */ 109 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, chnlbw); 110 111 RTWN_DPRINTF(sc, RTWN_DEBUG_CALIB, 112 "%s: LC calibration finished\n", __func__); 113 } 114 115 #ifndef RTWN_WITHOUT_UCODE 116 int 117 r12a_iq_calib_fw_supported(struct rtwn_softc *sc) 118 { 119 if (sc->fwver == 0x19) 120 return (1); 121 122 return (0); 123 } 124 #endif 125 126 void 127 r12a_save_bb_afe_vals(struct rtwn_softc *sc, uint32_t vals[], 128 const uint16_t regs[], int size) 129 { 130 int i; 131 132 /* Select page C. */ 133 rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x80000000, 0); 134 135 for (i = 0; i < size; i++) 136 vals[i] = rtwn_bb_read(sc, regs[i]); 137 } 138 139 void 140 r12a_restore_bb_afe_vals(struct rtwn_softc *sc, uint32_t vals[], 141 const uint16_t regs[], int size) 142 { 143 int i; 144 145 /* Select page C. */ 146 rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x80000000, 0); 147 148 for (i = 0; i < size; i++) 149 rtwn_bb_write(sc, regs[i], vals[i]); 150 } 151 152 void 153 r12a_save_rf_vals(struct rtwn_softc *sc, uint32_t vals[], 154 const uint8_t regs[], int size) 155 { 156 int c, i; 157 158 /* Select page C. */ 159 rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x80000000, 0); 160 161 for (c = 0; c < sc->nrxchains; c++) 162 for (i = 0; i < size; i++) 163 vals[c * size + i] = rtwn_rf_read(sc, c, regs[i]); 164 } 165 166 void 167 r12a_restore_rf_vals(struct rtwn_softc *sc, uint32_t vals[], 168 const uint8_t regs[], int size) 169 { 170 int c, i; 171 172 /* Select page C. */ 173 rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x80000000, 0); 174 175 for (c = 0; c < sc->nrxchains; c++) 176 for (i = 0; i < size; i++) 177 rtwn_rf_write(sc, c, regs[i], vals[c * size + i]); 178 } 179 180 #ifdef RTWN_TODO 181 static void 182 r12a_iq_tx(struct rtwn_softc *sc) 183 { 184 /* TODO */ 185 } 186 187 static void 188 r12a_iq_config_mac(struct rtwn_softc *sc) 189 { 190 191 /* Select page C. */ 192 rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x80000000, 0); 193 rtwn_write_1(sc, R92C_TXPAUSE, 194 R92C_TX_QUEUE_AC | R92C_TX_QUEUE_MGT | R92C_TX_QUEUE_HIGH); 195 /* BCN_CTRL & BCN_CTRL1 */ 196 rtwn_setbits_1(sc, R92C_BCN_CTRL(0), R92C_BCN_CTRL_EN_BCN, 0); 197 rtwn_setbits_1(sc, R92C_BCN_CTRL(1), R92C_BCN_CTRL_EN_BCN, 0); 198 /* Rx ant off */ 199 rtwn_write_1(sc, R12A_OFDMCCK_EN, 0); 200 /* CCA off */ 201 rtwn_bb_setbits(sc, R12A_CCA_ON_SEC, 0x03, 0x0c); 202 /* CCK RX Path off */ 203 rtwn_write_1(sc, R12A_CCK_RX_PATH + 3, 0x0f); 204 } 205 #endif 206 207 void 208 r12a_iq_calib_sw(struct rtwn_softc *sc) 209 { 210 #define R12A_MAX_NRXCHAINS 2 211 uint32_t bb_vals[nitems(r12a_iq_bb_regs)]; 212 uint32_t afe_vals[nitems(r12a_iq_afe_regs)]; 213 uint32_t rf_vals[nitems(r12a_iq_rf_regs) * R12A_MAX_NRXCHAINS]; 214 uint32_t rfe[2]; 215 216 KASSERT(sc->nrxchains <= R12A_MAX_NRXCHAINS, 217 ("nrxchains > %d (%d)\n", R12A_MAX_NRXCHAINS, sc->nrxchains)); 218 219 /* Save registers. */ 220 r12a_save_bb_afe_vals(sc, bb_vals, r12a_iq_bb_regs, 221 nitems(r12a_iq_bb_regs)); 222 223 /* Select page C1. */ 224 rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0, 0x80000000); 225 rfe[0] = rtwn_bb_read(sc, R12A_RFE(0)); 226 rfe[1] = rtwn_bb_read(sc, R12A_RFE(1)); 227 228 r12a_save_bb_afe_vals(sc, afe_vals, r12a_iq_afe_regs, 229 nitems(r12a_iq_afe_regs)); 230 r12a_save_rf_vals(sc, rf_vals, r12a_iq_rf_regs, 231 nitems(r12a_iq_rf_regs)); 232 233 #ifdef RTWN_TODO 234 /* Configure MAC. */ 235 rtwn_iq_config_mac(sc); 236 rtwn_iq_tx(sc); 237 #endif 238 239 r12a_restore_rf_vals(sc, rf_vals, r12a_iq_rf_regs, 240 nitems(r12a_iq_rf_regs)); 241 r12a_restore_bb_afe_vals(sc, afe_vals, r12a_iq_afe_regs, 242 nitems(r12a_iq_afe_regs)); 243 244 /* Select page C1. */ 245 rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0, 0x80000000); 246 247 /* Chain 0. */ 248 rtwn_bb_write(sc, R12A_SLEEP_NAV(0), 0); 249 rtwn_bb_write(sc, R12A_PMPD(0), 0); 250 rtwn_bb_write(sc, 0xc88, 0); 251 rtwn_bb_write(sc, 0xc8c, 0x3c000000); 252 rtwn_bb_setbits(sc, 0xc90, 0, 0x00000080); 253 rtwn_bb_setbits(sc, 0xcc4, 0, 0x20040000); 254 rtwn_bb_setbits(sc, 0xcc8, 0, 0x20000000); 255 256 /* Chain 1. */ 257 rtwn_bb_write(sc, R12A_SLEEP_NAV(1), 0); 258 rtwn_bb_write(sc, R12A_PMPD(1), 0); 259 rtwn_bb_write(sc, 0xe88, 0); 260 rtwn_bb_write(sc, 0xe8c, 0x3c000000); 261 rtwn_bb_setbits(sc, 0xe90, 0, 0x00000080); 262 rtwn_bb_setbits(sc, 0xec4, 0, 0x20040000); 263 rtwn_bb_setbits(sc, 0xec8, 0, 0x20000000); 264 265 rtwn_bb_write(sc, R12A_RFE(0), rfe[0]); 266 rtwn_bb_write(sc, R12A_RFE(1), rfe[1]); 267 268 r12a_restore_bb_afe_vals(sc, bb_vals, r12a_iq_bb_regs, 269 nitems(r12a_iq_bb_regs)); 270 #undef R12A_MAX_NRXCHAINS 271 } 272 273 void 274 r12a_iq_calib(struct rtwn_softc *sc) 275 { 276 #ifndef RTWN_WITHOUT_UCODE 277 if ((sc->sc_flags & RTWN_FW_LOADED) && 278 rtwn_r12a_iq_calib_fw_supported(sc)) 279 r12a_iq_calib_fw(sc); 280 else 281 #endif 282 rtwn_r12a_iq_calib_sw(sc); 283 } 284