1 /* $FreeBSD$ */ 2 /*- 3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 4 * 5 * Copyright (c) 1996-2008, 4Front Technologies 6 * Copyright (C) 1992-2000 Don Kim (don.kim@esstech.com) 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 /*--------------------------------------------------------------------------- 33 * Copyright (C) 1997-1999, ESS Technology, Inc. 34 * This source code, its compiled object code, and its associated data sets 35 * are copyright (C) 1997-1999 ESS Technology, Inc. 36 *--------------------------------------------------------------------------- 37 * This header contains data structures and registers taken from the 38 * 4Front OSS Allegro BSD licensed driver (in the Attic/ directory). 39 * Files used for this header include: 40 * hardware.h 41 * kernel.h and hckernel.h 42 * srcmgr.h 43 *--------------------------------------------------------------------------- 44 */ 45 46 #ifndef _DEV_SOUND_PCI_ALLEGRO_REG_H 47 #define _DEV_SOUND_PCI_ALLEGRO_REG_H 48 49 /* Allegro PCI configuration registers */ 50 #define PCI_LEGACY_AUDIO_CTRL 0x40 51 #define SOUND_BLASTER_ENABLE 0x00000001 52 #define FM_SYNTHESIS_ENABLE 0x00000002 53 #define GAME_PORT_ENABLE 0x00000004 54 #define MPU401_IO_ENABLE 0x00000008 55 #define MPU401_IRQ_ENABLE 0x00000010 56 #define ALIAS_10BIT_IO 0x00000020 57 #define SB_DMA_MASK 0x000000C0 58 #define SB_DMA_0 0x00000040 59 #define SB_DMA_1 0x00000040 60 #define SB_DMA_R 0x00000080 61 #define SB_DMA_3 0x000000C0 62 #define SB_IRQ_MASK 0x00000700 63 #define SB_IRQ_5 0x00000000 64 #define SB_IRQ_7 0x00000100 65 #define SB_IRQ_9 0x00000200 66 #define SB_IRQ_10 0x00000300 67 #define MIDI_IRQ_MASK 0x00003800 68 #define SERIAL_IRQ_ENABLE 0x00004000 69 #define DISABLE_LEGACY 0x00008000 70 71 #define PCI_ALLEGRO_CONFIG 0x50 72 #define SB_ADDR_240 0x00000004 73 #define MPU_ADDR_MASK 0x00000018 74 #define MPU_ADDR_330 0x00000000 75 #define MPU_ADDR_300 0x00000008 76 #define MPU_ADDR_320 0x00000010 77 #define MPU_ADDR_340 0x00000018 78 #define USE_PCI_TIMING 0x00000040 79 #define POSTED_WRITE_ENABLE 0x00000080 80 #define DMA_POLICY_MASK 0x00000700 81 #define DMA_DDMA 0x00000000 82 #define DMA_TDMA 0x00000100 83 #define DMA_PCPCI 0x00000200 84 #define DMA_WBDMA16 0x00000400 85 #define DMA_WBDMA4 0x00000500 86 #define DMA_WBDMA2 0x00000600 87 #define DMA_WBDMA1 0x00000700 88 #define DMA_SAFE_GUARD 0x00000800 89 #define HI_PERF_GP_ENABLE 0x00001000 90 #define PIC_SNOOP_MODE_0 0x00002000 91 #define PIC_SNOOP_MODE_1 0x00004000 92 #define SOUNDBLASTER_IRQ_MASK 0x00008000 93 #define RING_IN_ENABLE 0x00010000 94 #define SPDIF_TEST_MODE 0x00020000 95 #define CLK_MULT_MODE_SELECT_2 0x00040000 96 #define EEPROM_WRITE_ENABLE 0x00080000 97 #define CODEC_DIR_IN 0x00100000 98 #define HV_BUTTON_FROM_GD 0x00200000 99 #define REDUCED_DEBOUNCE 0x00400000 100 #define HV_CTRL_ENABLE 0x00800000 101 #define SPDIF_ENABLE 0x01000000 102 #define CLK_DIV_SELECT 0x06000000 103 #define CLK_DIV_BY_48 0x00000000 104 #define CLK_DIV_BY_49 0x02000000 105 #define CLK_DIV_BY_50 0x04000000 106 #define CLK_DIV_RESERVED 0x06000000 107 #define PM_CTRL_ENABLE 0x08000000 108 #define CLK_MULT_MODE_SELECT 0x30000000 109 #define CLK_MULT_MODE_SHIFT 28 110 #define CLK_MULT_MODE_0 0x00000000 111 #define CLK_MULT_MODE_1 0x10000000 112 #define CLK_MULT_MODE_2 0x20000000 113 #define CLK_MULT_MODE_3 0x30000000 114 #define INT_CLK_SELECT 0x40000000 115 #define INT_CLK_MULT_RESET 0x80000000 116 117 /* M3 */ 118 #define INT_CLK_SRC_NOT_PCI 0x00100000 119 #define INT_CLK_MULT_ENABLE 0x80000000 120 121 #define PCI_ACPI_CONTROL 0x54 122 #define PCI_ACPI_D0 0x00000000 123 #define PCI_ACPI_D1 0xB4F70000 124 #define PCI_ACPI_D2 0xB4F7B4F7 125 126 #define PCI_USER_CONFIG 0x58 127 #define EXT_PCI_MASTER_ENABLE 0x00000001 128 #define SPDIF_OUT_SELECT 0x00000002 129 #define TEST_PIN_DIR_CTRL 0x00000004 130 #define AC97_CODEC_TEST 0x00000020 131 #define TRI_STATE_BUFFER 0x00000080 132 #define IN_CLK_12MHZ_SELECT 0x00000100 133 #define MULTI_FUNC_DISABLE 0x00000200 134 #define EXT_MASTER_PAIR_SEL 0x00000400 135 #define PCI_MASTER_SUPPORT 0x00000800 136 #define STOP_CLOCK_ENABLE 0x00001000 137 #define EAPD_DRIVE_ENABLE 0x00002000 138 #define REQ_TRI_STATE_ENABLE 0x00004000 139 #define REQ_LOW_ENABLE 0x00008000 140 #define MIDI_1_ENABLE 0x00010000 141 #define MIDI_2_ENABLE 0x00020000 142 #define SB_AUDIO_SYNC 0x00040000 143 #define HV_CTRL_TEST 0x00100000 144 #define SOUNDBLASTER_TEST 0x00400000 145 146 #define PCI_USER_CONFIG_C 0x5C 147 148 #define PCI_DDMA_CTRL 0x60 149 #define DDMA_ENABLE 0x00000001 150 151 152 /* Allegro registers */ 153 #define HOST_INT_CTRL 0x18 154 #define SB_INT_ENABLE 0x0001 155 #define MPU401_INT_ENABLE 0x0002 156 #define ASSP_INT_ENABLE 0x0010 157 #define RING_INT_ENABLE 0x0020 158 #define HV_INT_ENABLE 0x0040 159 #define CLKRUN_GEN_ENABLE 0x0100 160 #define HV_CTRL_TO_PME 0x0400 161 #define SOFTWARE_RESET_ENABLE 0x8000 162 163 #define HOST_INT_STATUS 0x1A 164 #define SB_INT_PENDING 0x01 165 #define MPU401_INT_PENDING 0x02 166 #define ASSP_INT_PENDING 0x10 167 #define RING_INT_PENDING 0x20 168 #define HV_INT_PENDING 0x40 169 170 #define HARDWARE_VOL_CTRL 0x1B 171 #define SHADOW_MIX_REG_VOICE 0x1C 172 #define HW_VOL_COUNTER_VOICE 0x1D 173 #define SHADOW_MIX_REG_MASTER 0x1E 174 #define HW_VOL_COUNTER_MASTER 0x1F 175 176 #define CODEC_COMMAND 0x30 177 #define CODEC_READ_B 0x80 178 179 #define CODEC_STATUS 0x30 180 #define CODEC_BUSY_B 0x01 181 182 #define CODEC_DATA 0x32 183 184 /* AC97 registers */ 185 #ifndef M3_MODEL 186 #define AC97_RESET 0x00 187 #endif 188 189 #define AC97_VOL_MUTE_B 0x8000 190 #define AC97_VOL_M 0x1F 191 #define AC97_LEFT_VOL_S 8 192 193 #define AC97_MASTER_VOL 0x02 194 #define AC97_LINE_LEVEL_VOL 0x04 195 #define AC97_MASTER_MONO_VOL 0x06 196 #define AC97_PC_BEEP_VOL 0x0A 197 #define AC97_PC_BEEP_VOL_M 0x0F 198 #define AC97_SROUND_MASTER_VOL 0x38 199 #define AC97_PC_BEEP_VOL_S 1 200 201 #ifndef M3_MODEL 202 #define AC97_PHONE_VOL 0x0C 203 #define AC97_MIC_VOL 0x0E 204 #endif 205 #define AC97_MIC_20DB_ENABLE 0x40 206 207 #ifndef M3_MODEL 208 #define AC97_LINEIN_VOL 0x10 209 #define AC97_CD_VOL 0x12 210 #define AC97_VIDEO_VOL 0x14 211 #define AC97_AUX_VOL 0x16 212 #endif 213 #define AC97_PCM_OUT_VOL 0x18 214 #ifndef M3_MODEL 215 #define AC97_RECORD_SELECT 0x1A 216 #endif 217 #define AC97_RECORD_MIC 0x00 218 #define AC97_RECORD_CD 0x01 219 #define AC97_RECORD_VIDEO 0x02 220 #define AC97_RECORD_AUX 0x03 221 #define AC97_RECORD_MONO_MUX 0x02 222 #define AC97_RECORD_DIGITAL 0x03 223 #define AC97_RECORD_LINE 0x04 224 #define AC97_RECORD_STEREO 0x05 225 #define AC97_RECORD_MONO 0x06 226 #define AC97_RECORD_PHONE 0x07 227 228 #ifndef M3_MODEL 229 #define AC97_RECORD_GAIN 0x1C 230 #endif 231 #define AC97_RECORD_VOL_M 0x0F 232 233 #ifndef M3_MODEL 234 #define AC97_GENERAL_PURPOSE 0x20 235 #endif 236 #define AC97_POWER_DOWN_CTRL 0x26 237 #define AC97_ADC_READY 0x0001 238 #define AC97_DAC_READY 0x0002 239 #define AC97_ANALOG_READY 0x0004 240 #define AC97_VREF_ON 0x0008 241 #define AC97_PR0 0x0100 242 #define AC97_PR1 0x0200 243 #define AC97_PR2 0x0400 244 #define AC97_PR3 0x0800 245 #define AC97_PR4 0x1000 246 247 #define AC97_RESERVED1 0x28 248 249 #define AC97_VENDOR_TEST 0x5A 250 251 #define AC97_CLOCK_DELAY 0x5C 252 #define AC97_LINEOUT_MUX_SEL 0x0001 253 #define AC97_MONO_MUX_SEL 0x0002 254 #define AC97_CLOCK_DELAY_SEL 0x1F 255 #define AC97_DAC_CDS_SHIFT 6 256 #define AC97_ADC_CDS_SHIFT 11 257 258 #define AC97_MULTI_CHANNEL_SEL 0x74 259 260 #ifndef M3_MODEL 261 #define AC97_VENDOR_ID1 0x7C 262 #define AC97_VENDOR_ID2 0x7E 263 #endif 264 265 #define RING_BUS_CTRL_A 0x36 266 #define RAC_PME_ENABLE 0x0100 267 #define RAC_SDFS_ENABLE 0x0200 268 #define LAC_PME_ENABLE 0x0400 269 #define LAC_SDFS_ENABLE 0x0800 270 #define SERIAL_AC_LINK_ENABLE 0x1000 271 #define IO_SRAM_ENABLE 0x2000 272 #define IIS_INPUT_ENABLE 0x8000 273 274 #define RING_BUS_CTRL_B 0x38 275 #define SECOND_CODEC_ID_MASK 0x0003 276 #define SPDIF_FUNC_ENABLE 0x0010 277 #define SECOND_AC_ENABLE 0x0020 278 #define SB_MODULE_INTF_ENABLE 0x0040 279 #define SSPE_ENABLE 0x0040 280 #define M3I_DOCK_ENABLE 0x0080 281 282 #define SDO_OUT_DEST_CTRL 0x3A 283 #define COMMAND_ADDR_OUT 0x0003 284 #define PCM_LR_OUT_LOCAL 0x0000 285 #define PCM_LR_OUT_REMOTE 0x0004 286 #define PCM_LR_OUT_MUTE 0x0008 287 #define PCM_LR_OUT_BOTH 0x000C 288 #define LINE1_DAC_OUT_LOCAL 0x0000 289 #define LINE1_DAC_OUT_REMOTE 0x0010 290 #define LINE1_DAC_OUT_MUTE 0x0020 291 #define LINE1_DAC_OUT_BOTH 0x0030 292 #define PCM_CLS_OUT_LOCAL 0x0000 293 #define PCM_CLS_OUT_REMOTE 0x0040 294 #define PCM_CLS_OUT_MUTE 0x0080 295 #define PCM_CLS_OUT_BOTH 0x00C0 296 #define PCM_RLF_OUT_LOCAL 0x0000 297 #define PCM_RLF_OUT_REMOTE 0x0100 298 #define PCM_RLF_OUT_MUTE 0x0200 299 #define PCM_RLF_OUT_BOTH 0x0300 300 #define LINE2_DAC_OUT_LOCAL 0x0000 301 #define LINE2_DAC_OUT_REMOTE 0x0400 302 #define LINE2_DAC_OUT_MUTE 0x0800 303 #define LINE2_DAC_OUT_BOTH 0x0C00 304 #define HANDSET_OUT_LOCAL 0x0000 305 #define HANDSET_OUT_REMOTE 0x1000 306 #define HANDSET_OUT_MUTE 0x2000 307 #define HANDSET_OUT_BOTH 0x3000 308 #define IO_CTRL_OUT_LOCAL 0x0000 309 #define IO_CTRL_OUT_REMOTE 0x4000 310 #define IO_CTRL_OUT_MUTE 0x8000 311 #define IO_CTRL_OUT_BOTH 0xC000 312 313 #define SDO_IN_DEST_CTRL 0x3C 314 #define STATUS_ADDR_IN 0x0003 315 #define PCM_LR_IN_LOCAL 0x0000 316 #define PCM_LR_IN_REMOTE 0x0004 317 #define PCM_LR_RESERVED 0x0008 318 #define PCM_LR_IN_BOTH 0x000C 319 #define LINE1_ADC_IN_LOCAL 0x0000 320 #define LINE1_ADC_IN_REMOTE 0x0010 321 #define LINE1_ADC_IN_MUTE 0x0020 322 #define MIC_ADC_IN_LOCAL 0x0000 323 #define MIC_ADC_IN_REMOTE 0x0040 324 #define MIC_ADC_IN_MUTE 0x0080 325 #define LINE2_DAC_IN_LOCAL 0x0000 326 #define LINE2_DAC_IN_REMOTE 0x0400 327 #define LINE2_DAC_IN_MUTE 0x0800 328 #define HANDSET_IN_LOCAL 0x0000 329 #define HANDSET_IN_REMOTE 0x1000 330 #define HANDSET_IN_MUTE 0x2000 331 #define IO_STATUS_IN_LOCAL 0x0000 332 #define IO_STATUS_IN_REMOTE 0x4000 333 334 #define SPDIF_IN_CTRL 0x3E 335 #define SPDIF_IN_ENABLE 0x0001 336 337 #define GPIO_DATA 0x60 338 #define GPIO_DATA_MASK 0x0FFF 339 #define GPIO_HV_STATUS 0x3000 340 #define GPIO_PME_STATUS 0x4000 341 342 #define GPIO_MASK 0x64 343 #define GPIO_DIRECTION 0x68 344 #define GPO_PRIMARY_AC97 0x0001 345 #define GPI_LINEOUT_SENSE 0x0004 346 #define GPO_SECONDARY_AC97 0x0008 347 #define GPI_VOL_DOWN 0x0010 348 #define GPI_VOL_UP 0x0020 349 #define GPI_IIS_CLK 0x0040 350 #define GPI_IIS_LRCLK 0x0080 351 #define GPI_IIS_DATA 0x0100 352 #define GPI_DOCKING_STATUS 0x0100 353 #define GPI_HEADPHONE_SENSE 0x0200 354 #define GPO_EXT_AMP_SHUTDOWN 0x1000 355 356 /* M3 */ 357 #define GPO_M3_EXT_AMP_SHUTDN 0x0002 358 359 #define ASSP_INDEX_PORT 0x80 360 #define ASSP_MEMORY_PORT 0x82 361 #define ASSP_DATA_PORT 0x84 362 363 #define MPU401_DATA_PORT 0x98 364 #define MPU401_STATUS_PORT 0x99 365 366 #define CLK_MULT_DATA_PORT 0x9C 367 368 #define ASSP_CONTROL_A 0xA2 369 #define ASSP_0_WS_ENABLE 0x01 370 #define ASSP_CTRL_A_RESERVED1 0x02 371 #define ASSP_CTRL_A_RESERVED2 0x04 372 #define ASSP_CLK_49MHZ_SELECT 0x08 373 #define FAST_PLU_ENABLE 0x10 374 #define ASSP_CTRL_A_RESERVED3 0x20 375 #define DSP_CLK_36MHZ_SELECT 0x40 376 377 #define ASSP_CONTROL_B 0xA4 378 #define RESET_ASSP 0x00 379 #define RUN_ASSP 0x01 380 #define ENABLE_ASSP_CLOCK 0x00 381 #define STOP_ASSP_CLOCK 0x10 382 #define RESET_TOGGLE 0x40 383 384 #define ASSP_CONTROL_C 0xA6 385 #define ASSP_HOST_INT_ENABLE 0x01 386 #define FM_ADDR_REMAP_DISABLE 0x02 387 #define HOST_WRITE_PORT_ENABLE 0x08 388 389 #define ASSP_HOST_INT_STATUS 0xAC 390 #define DSP2HOST_REQ_PIORECORD 0x01 391 #define DSP2HOST_REQ_I2SRATE 0x02 392 #define DSP2HOST_REQ_TIMER 0x04 393 394 /* 395 * DSP memory map 396 */ 397 398 #define REV_A_CODE_MEMORY_BEGIN 0x0000 399 #define REV_A_CODE_MEMORY_END 0x0FFF 400 #define REV_A_CODE_MEMORY_UNIT_LENGTH 0x0040 401 #define REV_A_CODE_MEMORY_LENGTH (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1) 402 403 #define REV_B_CODE_MEMORY_BEGIN 0x0000 404 #define REV_B_CODE_MEMORY_END 0x0BFF 405 #define REV_B_CODE_MEMORY_UNIT_LENGTH 0x0040 406 #define REV_B_CODE_MEMORY_LENGTH (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1) 407 408 #if (REV_A_CODE_MEMORY_LENGTH % REV_A_CODE_MEMORY_UNIT_LENGTH) 409 #error Assumption about code memory unit length failed. 410 #endif 411 #if (REV_B_CODE_MEMORY_LENGTH % REV_B_CODE_MEMORY_UNIT_LENGTH) 412 #error Assumption about code memory unit length failed. 413 #endif 414 415 #define REV_A_DATA_MEMORY_BEGIN 0x1000 416 #define REV_A_DATA_MEMORY_END 0x2FFF 417 #define REV_A_DATA_MEMORY_UNIT_LENGTH 0x0080 418 #define REV_A_DATA_MEMORY_LENGTH (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1) 419 420 #define REV_B_DATA_MEMORY_BEGIN 0x1000 421 /*#define REV_B_DATA_MEMORY_END 0x23FF */ 422 #define REV_B_DATA_MEMORY_END 0x2BFF 423 #define REV_B_DATA_MEMORY_UNIT_LENGTH 0x0080 424 #define REV_B_DATA_MEMORY_LENGTH (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1) 425 426 #if (REV_A_DATA_MEMORY_LENGTH % REV_A_DATA_MEMORY_UNIT_LENGTH) 427 #error Assumption about data memory unit length failed. 428 #endif 429 #if (REV_B_DATA_MEMORY_LENGTH % REV_B_DATA_MEMORY_UNIT_LENGTH) 430 #error Assumption about data memory unit length failed. 431 #endif 432 433 #define CODE_MEMORY_MAP_LENGTH (64 + 1) 434 #define DATA_MEMORY_MAP_LENGTH (64 + 1) 435 436 #if (CODE_MEMORY_MAP_LENGTH < ((REV_A_CODE_MEMORY_LENGTH / REV_A_CODE_MEMORY_UNIT_LENGTH) + 1)) 437 #error Code memory map length too short. 438 #endif 439 #if (DATA_MEMORY_MAP_LENGTH < ((REV_A_DATA_MEMORY_LENGTH / REV_A_DATA_MEMORY_UNIT_LENGTH) + 1)) 440 #error Data memory map length too short. 441 #endif 442 #if (CODE_MEMORY_MAP_LENGTH < ((REV_B_CODE_MEMORY_LENGTH / REV_B_CODE_MEMORY_UNIT_LENGTH) + 1)) 443 #error Code memory map length too short. 444 #endif 445 #if (DATA_MEMORY_MAP_LENGTH < ((REV_B_DATA_MEMORY_LENGTH / REV_B_DATA_MEMORY_UNIT_LENGTH) + 1)) 446 #error Data memory map length too short. 447 #endif 448 449 450 /* 451 * Kernel code memory definition 452 */ 453 454 #define KCODE_VECTORS_BEGIN 0x0000 455 #define KCODE_VECTORS_END 0x002F 456 #define KCODE_VECTORS_UNIT_LENGTH 0x0002 457 #define KCODE_VECTORS_LENGTH (KCODE_VECTORS_END - KCODE_VECTORS_BEGIN + 1) 458 459 460 /* 461 * Kernel data memory definition 462 */ 463 464 #define KDATA_BASE_ADDR 0x1000 465 #define KDATA_BASE_ADDR2 0x1080 466 467 #define KDATA_TASK0 (KDATA_BASE_ADDR + 0x0000) 468 #define KDATA_TASK1 (KDATA_BASE_ADDR + 0x0001) 469 #define KDATA_TASK2 (KDATA_BASE_ADDR + 0x0002) 470 #define KDATA_TASK3 (KDATA_BASE_ADDR + 0x0003) 471 #define KDATA_TASK4 (KDATA_BASE_ADDR + 0x0004) 472 #define KDATA_TASK5 (KDATA_BASE_ADDR + 0x0005) 473 #define KDATA_TASK6 (KDATA_BASE_ADDR + 0x0006) 474 #define KDATA_TASK7 (KDATA_BASE_ADDR + 0x0007) 475 #define KDATA_TASK_ENDMARK (KDATA_BASE_ADDR + 0x0008) 476 477 #define KDATA_CURRENT_TASK (KDATA_BASE_ADDR + 0x0009) 478 #define KDATA_TASK_SWITCH (KDATA_BASE_ADDR + 0x000A) 479 480 #define KDATA_INSTANCE0_POS3D (KDATA_BASE_ADDR + 0x000B) 481 #define KDATA_INSTANCE1_POS3D (KDATA_BASE_ADDR + 0x000C) 482 #define KDATA_INSTANCE2_POS3D (KDATA_BASE_ADDR + 0x000D) 483 #define KDATA_INSTANCE3_POS3D (KDATA_BASE_ADDR + 0x000E) 484 #define KDATA_INSTANCE4_POS3D (KDATA_BASE_ADDR + 0x000F) 485 #define KDATA_INSTANCE5_POS3D (KDATA_BASE_ADDR + 0x0010) 486 #define KDATA_INSTANCE6_POS3D (KDATA_BASE_ADDR + 0x0011) 487 #define KDATA_INSTANCE7_POS3D (KDATA_BASE_ADDR + 0x0012) 488 #define KDATA_INSTANCE8_POS3D (KDATA_BASE_ADDR + 0x0013) 489 #define KDATA_INSTANCE_POS3D_ENDMARK (KDATA_BASE_ADDR + 0x0014) 490 491 #define KDATA_INSTANCE0_SPKVIRT (KDATA_BASE_ADDR + 0x0015) 492 #define KDATA_INSTANCE_SPKVIRT_ENDMARK (KDATA_BASE_ADDR + 0x0016) 493 494 #define KDATA_INSTANCE0_SPDIF (KDATA_BASE_ADDR + 0x0017) 495 #define KDATA_INSTANCE_SPDIF_ENDMARK (KDATA_BASE_ADDR + 0x0018) 496 497 #define KDATA_INSTANCE0_MODEM (KDATA_BASE_ADDR + 0x0019) 498 #define KDATA_INSTANCE_MODEM_ENDMARK (KDATA_BASE_ADDR + 0x001A) 499 500 #define KDATA_INSTANCE0_SRC (KDATA_BASE_ADDR + 0x001B) 501 #define KDATA_INSTANCE1_SRC (KDATA_BASE_ADDR + 0x001C) 502 #define KDATA_INSTANCE_SRC_ENDMARK (KDATA_BASE_ADDR + 0x001D) 503 504 #define KDATA_INSTANCE0_MINISRC (KDATA_BASE_ADDR + 0x001E) 505 #define KDATA_INSTANCE1_MINISRC (KDATA_BASE_ADDR + 0x001F) 506 #define KDATA_INSTANCE2_MINISRC (KDATA_BASE_ADDR + 0x0020) 507 #define KDATA_INSTANCE3_MINISRC (KDATA_BASE_ADDR + 0x0021) 508 #define KDATA_INSTANCE_MINISRC_ENDMARK (KDATA_BASE_ADDR + 0x0022) 509 510 #define KDATA_INSTANCE0_CPYTHRU (KDATA_BASE_ADDR + 0x0023) 511 #define KDATA_INSTANCE1_CPYTHRU (KDATA_BASE_ADDR + 0x0024) 512 #define KDATA_INSTANCE_CPYTHRU_ENDMARK (KDATA_BASE_ADDR + 0x0025) 513 514 #define KDATA_CURRENT_DMA (KDATA_BASE_ADDR + 0x0026) 515 #define KDATA_DMA_SWITCH (KDATA_BASE_ADDR + 0x0027) 516 #define KDATA_DMA_ACTIVE (KDATA_BASE_ADDR + 0x0028) 517 518 #define KDATA_DMA_XFER0 (KDATA_BASE_ADDR + 0x0029) 519 #define KDATA_DMA_XFER1 (KDATA_BASE_ADDR + 0x002A) 520 #define KDATA_DMA_XFER2 (KDATA_BASE_ADDR + 0x002B) 521 #define KDATA_DMA_XFER3 (KDATA_BASE_ADDR + 0x002C) 522 #define KDATA_DMA_XFER4 (KDATA_BASE_ADDR + 0x002D) 523 #define KDATA_DMA_XFER5 (KDATA_BASE_ADDR + 0x002E) 524 #define KDATA_DMA_XFER6 (KDATA_BASE_ADDR + 0x002F) 525 #define KDATA_DMA_XFER7 (KDATA_BASE_ADDR + 0x0030) 526 #define KDATA_DMA_XFER8 (KDATA_BASE_ADDR + 0x0031) 527 #define KDATA_DMA_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0032) 528 529 #define KDATA_I2S_SAMPLE_COUNT (KDATA_BASE_ADDR + 0x0033) 530 #define KDATA_I2S_INT_METER (KDATA_BASE_ADDR + 0x0034) 531 #define KDATA_I2S_ACTIVE (KDATA_BASE_ADDR + 0x0035) 532 533 #define KDATA_TIMER_COUNT_RELOAD (KDATA_BASE_ADDR + 0x0036) 534 #define KDATA_TIMER_COUNT_CURRENT (KDATA_BASE_ADDR + 0x0037) 535 536 #define KDATA_HALT_SYNCH_CLIENT (KDATA_BASE_ADDR + 0x0038) 537 #define KDATA_HALT_SYNCH_DMA (KDATA_BASE_ADDR + 0x0039) 538 #define KDATA_HALT_ACKNOWLEDGE (KDATA_BASE_ADDR + 0x003A) 539 540 #define KDATA_ADC1_XFER0 (KDATA_BASE_ADDR + 0x003B) 541 #define KDATA_ADC1_XFER_ENDMARK (KDATA_BASE_ADDR + 0x003C) 542 #define KDATA_ADC1_LEFT_VOLUME (KDATA_BASE_ADDR + 0x003D) 543 #define KDATA_ADC1_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x003E) 544 #define KDATA_ADC1_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x003F) 545 #define KDATA_ADC1_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0040) 546 547 #define KDATA_ADC2_XFER0 (KDATA_BASE_ADDR + 0x0041) 548 #define KDATA_ADC2_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0042) 549 #define KDATA_ADC2_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0043) 550 #define KDATA_ADC2_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x0044) 551 #define KDATA_ADC2_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x0045) 552 #define KDATA_ADC2_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0046) 553 554 #define KDATA_CD_XFER0 (KDATA_BASE_ADDR + 0x0047) 555 #define KDATA_CD_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0048) 556 #define KDATA_CD_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0049) 557 #define KDATA_CD_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x004A) 558 #define KDATA_CD_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x004B) 559 #define KDATA_CD_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x004C) 560 561 #define KDATA_MIC_XFER0 (KDATA_BASE_ADDR + 0x004D) 562 #define KDATA_MIC_XFER_ENDMARK (KDATA_BASE_ADDR + 0x004E) 563 #define KDATA_MIC_VOLUME (KDATA_BASE_ADDR + 0x004F) 564 #define KDATA_MIC_SUR_VOL (KDATA_BASE_ADDR + 0x0050) 565 566 #define KDATA_I2S_XFER0 (KDATA_BASE_ADDR + 0x0051) 567 #define KDATA_I2S_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0052) 568 569 #define KDATA_CHI_XFER0 (KDATA_BASE_ADDR + 0x0053) 570 #define KDATA_CHI_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0054) 571 572 #define KDATA_SPDIF_XFER (KDATA_BASE_ADDR + 0x0055) 573 #define KDATA_SPDIF_CURRENT_FRAME (KDATA_BASE_ADDR + 0x0056) 574 #define KDATA_SPDIF_FRAME0 (KDATA_BASE_ADDR + 0x0057) 575 #define KDATA_SPDIF_FRAME1 (KDATA_BASE_ADDR + 0x0058) 576 #define KDATA_SPDIF_FRAME2 (KDATA_BASE_ADDR + 0x0059) 577 578 #define KDATA_SPDIF_REQUEST (KDATA_BASE_ADDR + 0x005A) 579 #define KDATA_SPDIF_TEMP (KDATA_BASE_ADDR + 0x005B) 580 581 /*AY SPDIF IN */ 582 #define KDATA_SPDIFIN_XFER0 (KDATA_BASE_ADDR + 0x005C) 583 #define KDATA_SPDIFIN_XFER_ENDMARK (KDATA_BASE_ADDR + 0x005D) 584 #define KDATA_SPDIFIN_INT_METER (KDATA_BASE_ADDR + 0x005E) 585 586 #define KDATA_DSP_RESET_COUNT (KDATA_BASE_ADDR + 0x005F) 587 #define KDATA_DEBUG_OUTPUT (KDATA_BASE_ADDR + 0x0060) 588 589 #define KDATA_KERNEL_ISR_LIST (KDATA_BASE_ADDR + 0x0061) 590 591 #define KDATA_KERNEL_ISR_CBSR1 (KDATA_BASE_ADDR + 0x0062) 592 #define KDATA_KERNEL_ISR_CBER1 (KDATA_BASE_ADDR + 0x0063) 593 #define KDATA_KERNEL_ISR_CBCR (KDATA_BASE_ADDR + 0x0064) 594 #define KDATA_KERNEL_ISR_AR0 (KDATA_BASE_ADDR + 0x0065) 595 #define KDATA_KERNEL_ISR_AR1 (KDATA_BASE_ADDR + 0x0066) 596 #define KDATA_KERNEL_ISR_AR2 (KDATA_BASE_ADDR + 0x0067) 597 #define KDATA_KERNEL_ISR_AR3 (KDATA_BASE_ADDR + 0x0068) 598 #define KDATA_KERNEL_ISR_AR4 (KDATA_BASE_ADDR + 0x0069) 599 #define KDATA_KERNEL_ISR_AR5 (KDATA_BASE_ADDR + 0x006A) 600 #define KDATA_KERNEL_ISR_BRCR (KDATA_BASE_ADDR + 0x006B) 601 #define KDATA_KERNEL_ISR_PASR (KDATA_BASE_ADDR + 0x006C) 602 #define KDATA_KERNEL_ISR_PAER (KDATA_BASE_ADDR + 0x006D) 603 604 #define KDATA_CLIENT_SCRATCH0 (KDATA_BASE_ADDR + 0x006E) 605 #define KDATA_CLIENT_SCRATCH1 (KDATA_BASE_ADDR + 0x006F) 606 #define KDATA_KERNEL_SCRATCH (KDATA_BASE_ADDR + 0x0070) 607 #define KDATA_KERNEL_ISR_SCRATCH (KDATA_BASE_ADDR + 0x0071) 608 609 #define KDATA_OUEUE_LEFT (KDATA_BASE_ADDR + 0x0072) 610 #define KDATA_QUEUE_RIGHT (KDATA_BASE_ADDR + 0x0073) 611 612 #define KDATA_ADC1_REQUEST (KDATA_BASE_ADDR + 0x0074) 613 #define KDATA_ADC2_REQUEST (KDATA_BASE_ADDR + 0x0075) 614 #define KDATA_CD_REQUEST (KDATA_BASE_ADDR + 0x0076) 615 #define KDATA_MIC_REQUEST (KDATA_BASE_ADDR + 0x0077) 616 617 #define KDATA_ADC1_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0078) 618 #define KDATA_ADC2_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0079) 619 #define KDATA_CD_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007A) 620 #define KDATA_MIC_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007B) 621 #define KDATA_MIC_SYNC_COUNTER (KDATA_BASE_ADDR + 0x007C) 622 623 /* 624 * second segment 625 */ 626 627 /* smart mixer buffer */ 628 629 #define KDATA_MIXER_WORD0 (KDATA_BASE_ADDR2 + 0x0000) 630 #define KDATA_MIXER_WORD1 (KDATA_BASE_ADDR2 + 0x0001) 631 #define KDATA_MIXER_WORD2 (KDATA_BASE_ADDR2 + 0x0002) 632 #define KDATA_MIXER_WORD3 (KDATA_BASE_ADDR2 + 0x0003) 633 #define KDATA_MIXER_WORD4 (KDATA_BASE_ADDR2 + 0x0004) 634 #define KDATA_MIXER_WORD5 (KDATA_BASE_ADDR2 + 0x0005) 635 #define KDATA_MIXER_WORD6 (KDATA_BASE_ADDR2 + 0x0006) 636 #define KDATA_MIXER_WORD7 (KDATA_BASE_ADDR2 + 0x0007) 637 #define KDATA_MIXER_WORD8 (KDATA_BASE_ADDR2 + 0x0008) 638 #define KDATA_MIXER_WORD9 (KDATA_BASE_ADDR2 + 0x0009) 639 #define KDATA_MIXER_WORDA (KDATA_BASE_ADDR2 + 0x000A) 640 #define KDATA_MIXER_WORDB (KDATA_BASE_ADDR2 + 0x000B) 641 #define KDATA_MIXER_WORDC (KDATA_BASE_ADDR2 + 0x000C) 642 #define KDATA_MIXER_WORDD (KDATA_BASE_ADDR2 + 0x000D) 643 #define KDATA_MIXER_WORDE (KDATA_BASE_ADDR2 + 0x000E) 644 #define KDATA_MIXER_WORDF (KDATA_BASE_ADDR2 + 0x000F) 645 646 #define KDATA_MIXER_XFER0 (KDATA_BASE_ADDR2 + 0x0010) 647 #define KDATA_MIXER_XFER1 (KDATA_BASE_ADDR2 + 0x0011) 648 #define KDATA_MIXER_XFER2 (KDATA_BASE_ADDR2 + 0x0012) 649 #define KDATA_MIXER_XFER3 (KDATA_BASE_ADDR2 + 0x0013) 650 #define KDATA_MIXER_XFER4 (KDATA_BASE_ADDR2 + 0x0014) 651 #define KDATA_MIXER_XFER5 (KDATA_BASE_ADDR2 + 0x0015) 652 #define KDATA_MIXER_XFER6 (KDATA_BASE_ADDR2 + 0x0016) 653 #define KDATA_MIXER_XFER7 (KDATA_BASE_ADDR2 + 0x0017) 654 #define KDATA_MIXER_XFER8 (KDATA_BASE_ADDR2 + 0x0018) 655 #define KDATA_MIXER_XFER9 (KDATA_BASE_ADDR2 + 0x0019) 656 #define KDATA_MIXER_XFER_ENDMARK (KDATA_BASE_ADDR2 + 0x001A) 657 658 #define KDATA_MIXER_TASK_NUMBER (KDATA_BASE_ADDR2 + 0x001B) 659 #define KDATA_CURRENT_MIXER (KDATA_BASE_ADDR2 + 0x001C) 660 #define KDATA_MIXER_ACTIVE (KDATA_BASE_ADDR2 + 0x001D) 661 #define KDATA_MIXER_BANK_STATUS (KDATA_BASE_ADDR2 + 0x001E) 662 #define KDATA_DAC_LEFT_VOLUME (KDATA_BASE_ADDR2 + 0x001F) 663 #define KDATA_DAC_RIGHT_VOLUME (KDATA_BASE_ADDR2 + 0x0020) 664 665 /* 666 * Client data memory definition 667 */ 668 669 #define CDATA_INSTANCE_READY 0x00 670 671 #define CDATA_HOST_SRC_ADDRL 0x01 672 #define CDATA_HOST_SRC_ADDRH 0x02 673 #define CDATA_HOST_SRC_END_PLUS_1L 0x03 674 #define CDATA_HOST_SRC_END_PLUS_1H 0x04 675 #define CDATA_HOST_SRC_CURRENTL 0x05 676 #define CDATA_HOST_SRC_CURRENTH 0x06 677 678 #define CDATA_IN_BUF_CONNECT 0x07 679 #define CDATA_OUT_BUF_CONNECT 0x08 680 681 #define CDATA_IN_BUF_BEGIN 0x09 682 #define CDATA_IN_BUF_END_PLUS_1 0x0A 683 #define CDATA_IN_BUF_HEAD 0x0B 684 #define CDATA_IN_BUF_TAIL 0x0C 685 686 #define CDATA_OUT_BUF_BEGIN 0x0D 687 #define CDATA_OUT_BUF_END_PLUS_1 0x0E 688 #define CDATA_OUT_BUF_HEAD 0x0F 689 #define CDATA_OUT_BUF_TAIL 0x10 690 691 #define CDATA_DMA_CONTROL 0x11 692 #define CDATA_RESERVED 0x12 693 694 #define CDATA_FREQUENCY 0x13 695 #define CDATA_LEFT_VOLUME 0x14 696 #define CDATA_RIGHT_VOLUME 0x15 697 #define CDATA_LEFT_SUR_VOL 0x16 698 #define CDATA_RIGHT_SUR_VOL 0x17 699 700 /* These are from Allegro hckernel.h */ 701 #define CDATA_HEADER_LEN 0x18 702 #define SRC3_DIRECTION_OFFSET CDATA_HEADER_LEN 703 #define SRC3_MODE_OFFSET CDATA_HEADER_LEN + 1 704 #define SRC3_WORD_LENGTH_OFFSET CDATA_HEADER_LEN + 2 705 #define SRC3_PARAMETER_OFFSET CDATA_HEADER_LEN + 3 706 #define SRC3_COEFF_ADDR_OFFSET CDATA_HEADER_LEN + 8 707 #define SRC3_FILTAP_ADDR_OFFSET CDATA_HEADER_LEN + 10 708 #define SRC3_TEMP_INBUF_ADDR_OFFSET CDATA_HEADER_LEN + 16 709 #define SRC3_TEMP_OUTBUF_ADDR_OFFSET CDATA_HEADER_LEN + 17 710 #define FOR_FUTURE_USE 10 /* for storing temporary variable in future */ 711 712 /* 713 * DMA control definition 714 */ 715 716 #define DMACONTROL_BLOCK_MASK 0x000F 717 #define DMAC_BLOCK0_SELECTOR 0x0000 718 #define DMAC_BLOCK1_SELECTOR 0x0001 719 #define DMAC_BLOCK2_SELECTOR 0x0002 720 #define DMAC_BLOCK3_SELECTOR 0x0003 721 #define DMAC_BLOCK4_SELECTOR 0x0004 722 #define DMAC_BLOCK5_SELECTOR 0x0005 723 #define DMAC_BLOCK6_SELECTOR 0x0006 724 #define DMAC_BLOCK7_SELECTOR 0x0007 725 #define DMAC_BLOCK8_SELECTOR 0x0008 726 #define DMAC_BLOCK9_SELECTOR 0x0009 727 #define DMAC_BLOCKA_SELECTOR 0x000A 728 #define DMAC_BLOCKB_SELECTOR 0x000B 729 #define DMAC_BLOCKC_SELECTOR 0x000C 730 #define DMAC_BLOCKD_SELECTOR 0x000D 731 #define DMAC_BLOCKE_SELECTOR 0x000E 732 #define DMAC_BLOCKF_SELECTOR 0x000F 733 #define DMACONTROL_PAGE_MASK 0x00F0 734 #define DMAC_PAGE0_SELECTOR 0x0030 735 #define DMAC_PAGE1_SELECTOR 0x0020 736 #define DMAC_PAGE2_SELECTOR 0x0010 737 #define DMAC_PAGE3_SELECTOR 0x0000 738 #define DMACONTROL_AUTOREPEAT 0x1000 739 #define DMACONTROL_STOPPED 0x2000 740 #define DMACONTROL_DIRECTION 0x0100 741 742 /* 743 * Kernel/client memory allocation 744 */ 745 746 #define NUM_UNITS_KERNEL_CODE 16 747 #define NUM_UNITS_KERNEL_DATA 2 748 749 #define NUM_UNITS_KERNEL_CODE_WITH_HSP 16 750 #ifdef M3_MODEL 751 #define NUM_UNITS_KERNEL_DATA_WITH_HSP 5 752 #else 753 #define NUM_UNITS_KERNEL_DATA_WITH_HSP 4 754 #endif 755 756 #define NUM_UNITS( BYTES, UNITLEN ) ((((BYTES+1)>>1) + (UNITLEN-1)) / UNITLEN) 757 758 /* 759 * DSP hardware 760 */ 761 762 #define DSP_PORT_TIMER_COUNT 0x06 763 #define DSP_PORT_MEMORY_INDEX 0x80 764 #define DSP_PORT_MEMORY_TYPE 0x82 765 #define DSP_PORT_MEMORY_DATA 0x84 766 #define DSP_PORT_CONTROL_REG_A 0xA2 767 #define DSP_PORT_CONTROL_REG_B 0xA4 768 #define DSP_PORT_CONTROL_REG_C 0xA6 769 770 #define MEMTYPE_INTERNAL_CODE 0x0002 771 #define MEMTYPE_INTERNAL_DATA 0x0003 772 #define MEMTYPE_MASK 0x0003 773 774 #define REGB_ENABLE_RESET 0x01 775 #define REGB_STOP_CLOCK 0x10 776 777 #define REGC_DISABLE_FM_MAPPING 0x02 778 779 #define DP_SHIFT_COUNT 7 780 781 #define DMA_BLOCK_LENGTH 32 782 783 /* These are from Allegro srcmgr.h */ 784 #define MINISRC_BIQUAD_STAGE 2 785 #define MINISRC_IN_BUFFER_SIZE ( 0x50 * 2 ) 786 #define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2) 787 #define MINISRC_TMP_BUFFER_SIZE ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 ) 788 #define MINISRC_BIQUAD_STAGE 2 789 /* M. SRC LPF coefficient could be changed in the DSP code */ 790 #define MINISRC_COEF_LOC 0X175 791 792 #endif /* !_DEV_SOUND_PCI_ALLEGRO_REG_H */ 793