1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2000 Orion Hodson <O.Hodson@cs.ucl.ac.uk> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * This driver exists largely as a result of other people's efforts. 31 * Much of register handling is based on NetBSD CMI8x38 audio driver 32 * by Takuya Shiozaki <AoiMoe@imou.to>. Chen-Li Tien 33 * <cltien@cmedia.com.tw> clarified points regarding the DMA related 34 * registers and the 8738 mixer devices. His Linux driver was also a 35 * useful reference point. 36 * 37 * TODO: MIDI 38 * 39 * SPDIF contributed by Gerhard Gonter <gonter@whisky.wu-wien.ac.at>. 40 * 41 * This card/code does not always manage to sample at 44100 - actual 42 * rate drifts slightly between recordings (usually 0-3%). No 43 * differences visible in register dumps between times that work and 44 * those that don't. 45 */ 46 47 #ifdef HAVE_KERNEL_OPTION_HEADERS 48 #include "opt_snd.h" 49 #endif 50 51 #include <dev/sound/pcm/sound.h> 52 #include <dev/sound/pci/cmireg.h> 53 #include <dev/sound/isa/sb.h> 54 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcivar.h> 57 58 #include <sys/sysctl.h> 59 #include <dev/sound/midi/mpu401.h> 60 61 #include "mixer_if.h" 62 #include "mpufoi_if.h" 63 64 /* Supported chip ID's */ 65 #define CMI8338A_PCI_ID 0x010013f6 66 #define CMI8338B_PCI_ID 0x010113f6 67 #define CMI8738_PCI_ID 0x011113f6 68 #define CMI8738B_PCI_ID 0x011213f6 69 #define CMI120_USB_ID 0x01030d8c 70 71 /* Buffer size max is 64k for permitted DMA boundaries */ 72 #define CMI_DEFAULT_BUFSZ 16384 73 74 /* Interrupts per length of buffer */ 75 #define CMI_INTR_PER_BUFFER 2 76 77 /* Clarify meaning of named defines in cmireg.h */ 78 #define CMPCI_REG_DMA0_MAX_SAMPLES CMPCI_REG_DMA0_BYTES 79 #define CMPCI_REG_DMA0_INTR_SAMPLES CMPCI_REG_DMA0_SAMPLES 80 #define CMPCI_REG_DMA1_MAX_SAMPLES CMPCI_REG_DMA1_BYTES 81 #define CMPCI_REG_DMA1_INTR_SAMPLES CMPCI_REG_DMA1_SAMPLES 82 83 /* Our indication of custom mixer control */ 84 #define CMPCI_NON_SB16_CONTROL 0xff 85 86 /* Debugging macro's */ 87 #undef DEB 88 #ifndef DEB 89 #define DEB(x) /* x */ 90 #endif /* DEB */ 91 92 #ifndef DEBMIX 93 #define DEBMIX(x) /* x */ 94 #endif /* DEBMIX */ 95 96 /* ------------------------------------------------------------------------- */ 97 /* Structures */ 98 99 struct sc_info; 100 101 struct sc_chinfo { 102 struct sc_info *parent; 103 struct pcm_channel *channel; 104 struct snd_dbuf *buffer; 105 u_int32_t fmt, spd, phys_buf, bps; 106 u_int32_t dma_active:1, dma_was_active:1; 107 int dir; 108 }; 109 110 struct sc_info { 111 device_t dev; 112 113 bus_space_tag_t st; 114 bus_space_handle_t sh; 115 bus_dma_tag_t parent_dmat; 116 struct resource *reg, *irq; 117 int regid, irqid; 118 void *ih; 119 struct mtx *lock; 120 121 int spdif_enabled; 122 unsigned int bufsz; 123 struct sc_chinfo pch, rch; 124 125 struct mpu401 *mpu; 126 mpu401_intr_t *mpu_intr; 127 struct resource *mpu_reg; 128 int mpu_regid; 129 bus_space_tag_t mpu_bt; 130 bus_space_handle_t mpu_bh; 131 }; 132 133 /* Channel caps */ 134 135 static u_int32_t cmi_fmt[] = { 136 SND_FORMAT(AFMT_U8, 1, 0), 137 SND_FORMAT(AFMT_U8, 2, 0), 138 SND_FORMAT(AFMT_S16_LE, 1, 0), 139 SND_FORMAT(AFMT_S16_LE, 2, 0), 140 0 141 }; 142 143 static struct pcmchan_caps cmi_caps = {5512, 48000, cmi_fmt, 0}; 144 145 /* ------------------------------------------------------------------------- */ 146 /* Register Utilities */ 147 148 static u_int32_t 149 cmi_rd(struct sc_info *sc, int regno, int size) 150 { 151 switch (size) { 152 case 1: 153 return bus_space_read_1(sc->st, sc->sh, regno); 154 case 2: 155 return bus_space_read_2(sc->st, sc->sh, regno); 156 case 4: 157 return bus_space_read_4(sc->st, sc->sh, regno); 158 default: 159 DEB(printf("cmi_rd: failed 0x%04x %d\n", regno, size)); 160 return 0xFFFFFFFF; 161 } 162 } 163 164 static void 165 cmi_wr(struct sc_info *sc, int regno, u_int32_t data, int size) 166 { 167 switch (size) { 168 case 1: 169 bus_space_write_1(sc->st, sc->sh, regno, data); 170 break; 171 case 2: 172 bus_space_write_2(sc->st, sc->sh, regno, data); 173 break; 174 case 4: 175 bus_space_write_4(sc->st, sc->sh, regno, data); 176 break; 177 } 178 } 179 180 static void 181 cmi_partial_wr4(struct sc_info *sc, 182 int reg, int shift, u_int32_t mask, u_int32_t val) 183 { 184 u_int32_t r; 185 186 r = cmi_rd(sc, reg, 4); 187 r &= ~(mask << shift); 188 r |= val << shift; 189 cmi_wr(sc, reg, r, 4); 190 } 191 192 static void 193 cmi_clr4(struct sc_info *sc, int reg, u_int32_t mask) 194 { 195 u_int32_t r; 196 197 r = cmi_rd(sc, reg, 4); 198 r &= ~mask; 199 cmi_wr(sc, reg, r, 4); 200 } 201 202 static void 203 cmi_set4(struct sc_info *sc, int reg, u_int32_t mask) 204 { 205 u_int32_t r; 206 207 r = cmi_rd(sc, reg, 4); 208 r |= mask; 209 cmi_wr(sc, reg, r, 4); 210 } 211 212 /* ------------------------------------------------------------------------- */ 213 /* Rate Mapping */ 214 215 static int cmi_rates[] = {5512, 8000, 11025, 16000, 216 22050, 32000, 44100, 48000}; 217 #define NUM_CMI_RATES (sizeof(cmi_rates)/sizeof(cmi_rates[0])) 218 219 /* cmpci_rate_to_regvalue returns sampling freq selector for FCR1 220 * register - reg order is 5k,11k,22k,44k,8k,16k,32k,48k */ 221 222 static u_int32_t 223 cmpci_rate_to_regvalue(int rate) 224 { 225 int i, r; 226 227 for(i = 0; i < NUM_CMI_RATES - 1; i++) { 228 if (rate < ((cmi_rates[i] + cmi_rates[i + 1]) / 2)) { 229 break; 230 } 231 } 232 233 DEB(printf("cmpci_rate_to_regvalue: %d -> %d\n", rate, cmi_rates[i])); 234 235 r = ((i >> 1) | (i << 2)) & 0x07; 236 return r; 237 } 238 239 static int 240 cmpci_regvalue_to_rate(u_int32_t r) 241 { 242 int i; 243 244 i = ((r << 1) | (r >> 2)) & 0x07; 245 DEB(printf("cmpci_regvalue_to_rate: %d -> %d\n", r, i)); 246 return cmi_rates[i]; 247 } 248 249 /* ------------------------------------------------------------------------- */ 250 /* ADC/DAC control - there are 2 dma channels on 8738, either can be 251 * playback or capture. We use ch0 for playback and ch1 for capture. */ 252 253 static void 254 cmi_dma_prog(struct sc_info *sc, struct sc_chinfo *ch, u_int32_t base) 255 { 256 u_int32_t s, i, sz; 257 258 ch->phys_buf = sndbuf_getbufaddr(ch->buffer); 259 260 cmi_wr(sc, base, ch->phys_buf, 4); 261 sz = (u_int32_t)sndbuf_getsize(ch->buffer); 262 263 s = sz / ch->bps - 1; 264 cmi_wr(sc, base + 4, s, 2); 265 266 i = sz / (ch->bps * CMI_INTR_PER_BUFFER) - 1; 267 cmi_wr(sc, base + 6, i, 2); 268 } 269 270 static void 271 cmi_ch0_start(struct sc_info *sc, struct sc_chinfo *ch) 272 { 273 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE); 274 275 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE); 276 cmi_set4(sc, CMPCI_REG_INTR_CTRL, 277 CMPCI_REG_CH0_INTR_ENABLE); 278 279 ch->dma_active = 1; 280 } 281 282 static u_int32_t 283 cmi_ch0_stop(struct sc_info *sc, struct sc_chinfo *ch) 284 { 285 u_int32_t r = ch->dma_active; 286 287 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE); 288 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE); 289 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET); 290 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET); 291 ch->dma_active = 0; 292 return r; 293 } 294 295 static void 296 cmi_ch1_start(struct sc_info *sc, struct sc_chinfo *ch) 297 { 298 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE); 299 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE); 300 /* Enable Interrupts */ 301 cmi_set4(sc, CMPCI_REG_INTR_CTRL, 302 CMPCI_REG_CH1_INTR_ENABLE); 303 DEB(printf("cmi_ch1_start: dma prog\n")); 304 ch->dma_active = 1; 305 } 306 307 static u_int32_t 308 cmi_ch1_stop(struct sc_info *sc, struct sc_chinfo *ch) 309 { 310 u_int32_t r = ch->dma_active; 311 312 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE); 313 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE); 314 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET); 315 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET); 316 ch->dma_active = 0; 317 return r; 318 } 319 320 static void 321 cmi_spdif_speed(struct sc_info *sc, int speed) { 322 u_int32_t fcr1, lcr, mcr; 323 324 if (speed >= 44100) { 325 fcr1 = CMPCI_REG_SPDIF0_ENABLE; 326 lcr = CMPCI_REG_XSPDIF_ENABLE; 327 mcr = (speed == 48000) ? 328 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K : 0; 329 } else { 330 fcr1 = mcr = lcr = 0; 331 } 332 333 cmi_partial_wr4(sc, CMPCI_REG_MISC, 0, 334 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K, mcr); 335 cmi_partial_wr4(sc, CMPCI_REG_FUNC_1, 0, 336 CMPCI_REG_SPDIF0_ENABLE, fcr1); 337 cmi_partial_wr4(sc, CMPCI_REG_LEGACY_CTRL, 0, 338 CMPCI_REG_XSPDIF_ENABLE, lcr); 339 } 340 341 /* ------------------------------------------------------------------------- */ 342 /* Channel Interface implementation */ 343 344 static void * 345 cmichan_init(kobj_t obj, void *devinfo, 346 struct snd_dbuf *b, struct pcm_channel *c, int dir) 347 { 348 struct sc_info *sc = devinfo; 349 struct sc_chinfo *ch = (dir == PCMDIR_PLAY) ? &sc->pch : &sc->rch; 350 351 ch->parent = sc; 352 ch->channel = c; 353 ch->bps = 1; 354 ch->fmt = SND_FORMAT(AFMT_U8, 1, 0); 355 ch->spd = DSP_DEFAULT_SPEED; 356 ch->buffer = b; 357 ch->dma_active = 0; 358 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0) { 359 DEB(printf("cmichan_init failed\n")); 360 return NULL; 361 } 362 363 ch->dir = dir; 364 snd_mtxlock(sc->lock); 365 if (ch->dir == PCMDIR_PLAY) { 366 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE); 367 } else { 368 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE); 369 } 370 snd_mtxunlock(sc->lock); 371 372 return ch; 373 } 374 375 static int 376 cmichan_setformat(kobj_t obj, void *data, u_int32_t format) 377 { 378 struct sc_chinfo *ch = data; 379 struct sc_info *sc = ch->parent; 380 u_int32_t f; 381 382 if (format & AFMT_S16_LE) { 383 f = CMPCI_REG_FORMAT_16BIT; 384 ch->bps = 2; 385 } else { 386 f = CMPCI_REG_FORMAT_8BIT; 387 ch->bps = 1; 388 } 389 390 if (AFMT_CHANNEL(format) > 1) { 391 f |= CMPCI_REG_FORMAT_STEREO; 392 ch->bps *= 2; 393 } else { 394 f |= CMPCI_REG_FORMAT_MONO; 395 } 396 397 snd_mtxlock(sc->lock); 398 if (ch->dir == PCMDIR_PLAY) { 399 cmi_partial_wr4(ch->parent, 400 CMPCI_REG_CHANNEL_FORMAT, 401 CMPCI_REG_CH0_FORMAT_SHIFT, 402 CMPCI_REG_CH0_FORMAT_MASK, 403 f); 404 } else { 405 cmi_partial_wr4(ch->parent, 406 CMPCI_REG_CHANNEL_FORMAT, 407 CMPCI_REG_CH1_FORMAT_SHIFT, 408 CMPCI_REG_CH1_FORMAT_MASK, 409 f); 410 } 411 snd_mtxunlock(sc->lock); 412 ch->fmt = format; 413 414 return 0; 415 } 416 417 static u_int32_t 418 cmichan_setspeed(kobj_t obj, void *data, u_int32_t speed) 419 { 420 struct sc_chinfo *ch = data; 421 struct sc_info *sc = ch->parent; 422 u_int32_t r, rsp __unused; 423 424 r = cmpci_rate_to_regvalue(speed); 425 snd_mtxlock(sc->lock); 426 if (ch->dir == PCMDIR_PLAY) { 427 if (speed < 44100) { 428 /* disable if req before rate change */ 429 cmi_spdif_speed(ch->parent, speed); 430 } 431 cmi_partial_wr4(ch->parent, 432 CMPCI_REG_FUNC_1, 433 CMPCI_REG_DAC_FS_SHIFT, 434 CMPCI_REG_DAC_FS_MASK, 435 r); 436 if (speed >= 44100 && ch->parent->spdif_enabled) { 437 /* enable if req after rate change */ 438 cmi_spdif_speed(ch->parent, speed); 439 } 440 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4); 441 rsp >>= CMPCI_REG_DAC_FS_SHIFT; 442 rsp &= CMPCI_REG_DAC_FS_MASK; 443 } else { 444 cmi_partial_wr4(ch->parent, 445 CMPCI_REG_FUNC_1, 446 CMPCI_REG_ADC_FS_SHIFT, 447 CMPCI_REG_ADC_FS_MASK, 448 r); 449 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4); 450 rsp >>= CMPCI_REG_ADC_FS_SHIFT; 451 rsp &= CMPCI_REG_ADC_FS_MASK; 452 } 453 snd_mtxunlock(sc->lock); 454 ch->spd = cmpci_regvalue_to_rate(r); 455 456 DEB(printf("cmichan_setspeed (%s) %d -> %d (%d)\n", 457 (ch->dir == PCMDIR_PLAY) ? "play" : "rec", 458 speed, ch->spd, cmpci_regvalue_to_rate(rsp))); 459 460 return ch->spd; 461 } 462 463 static u_int32_t 464 cmichan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 465 { 466 struct sc_chinfo *ch = data; 467 struct sc_info *sc = ch->parent; 468 469 /* user has requested interrupts every blocksize bytes */ 470 if (blocksize > sc->bufsz / CMI_INTR_PER_BUFFER) { 471 blocksize = sc->bufsz / CMI_INTR_PER_BUFFER; 472 } 473 sndbuf_resize(ch->buffer, CMI_INTR_PER_BUFFER, blocksize); 474 475 return blocksize; 476 } 477 478 static int 479 cmichan_trigger(kobj_t obj, void *data, int go) 480 { 481 struct sc_chinfo *ch = data; 482 struct sc_info *sc = ch->parent; 483 484 if (!PCMTRIG_COMMON(go)) 485 return 0; 486 487 snd_mtxlock(sc->lock); 488 if (ch->dir == PCMDIR_PLAY) { 489 switch(go) { 490 case PCMTRIG_START: 491 cmi_ch0_start(sc, ch); 492 break; 493 case PCMTRIG_STOP: 494 case PCMTRIG_ABORT: 495 cmi_ch0_stop(sc, ch); 496 break; 497 } 498 } else { 499 switch(go) { 500 case PCMTRIG_START: 501 cmi_ch1_start(sc, ch); 502 break; 503 case PCMTRIG_STOP: 504 case PCMTRIG_ABORT: 505 cmi_ch1_stop(sc, ch); 506 break; 507 } 508 } 509 snd_mtxunlock(sc->lock); 510 return 0; 511 } 512 513 static u_int32_t 514 cmichan_getptr(kobj_t obj, void *data) 515 { 516 struct sc_chinfo *ch = data; 517 struct sc_info *sc = ch->parent; 518 u_int32_t physptr, bufptr, sz; 519 520 snd_mtxlock(sc->lock); 521 if (ch->dir == PCMDIR_PLAY) { 522 physptr = cmi_rd(sc, CMPCI_REG_DMA0_BASE, 4); 523 } else { 524 physptr = cmi_rd(sc, CMPCI_REG_DMA1_BASE, 4); 525 } 526 snd_mtxunlock(sc->lock); 527 528 sz = sndbuf_getsize(ch->buffer); 529 bufptr = (physptr - ch->phys_buf + sz - ch->bps) % sz; 530 531 return bufptr; 532 } 533 534 static void 535 cmi_intr(void *data) 536 { 537 struct sc_info *sc = data; 538 u_int32_t intrstat; 539 u_int32_t toclear; 540 541 snd_mtxlock(sc->lock); 542 intrstat = cmi_rd(sc, CMPCI_REG_INTR_STATUS, 4); 543 if ((intrstat & CMPCI_REG_ANY_INTR) != 0) { 544 toclear = 0; 545 if (intrstat & CMPCI_REG_CH0_INTR) { 546 toclear |= CMPCI_REG_CH0_INTR_ENABLE; 547 //cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE); 548 } 549 550 if (intrstat & CMPCI_REG_CH1_INTR) { 551 toclear |= CMPCI_REG_CH1_INTR_ENABLE; 552 //cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE); 553 } 554 555 if (toclear) { 556 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, toclear); 557 snd_mtxunlock(sc->lock); 558 559 /* Signal interrupts to channel */ 560 if (intrstat & CMPCI_REG_CH0_INTR) { 561 chn_intr(sc->pch.channel); 562 } 563 564 if (intrstat & CMPCI_REG_CH1_INTR) { 565 chn_intr(sc->rch.channel); 566 } 567 568 snd_mtxlock(sc->lock); 569 cmi_set4(sc, CMPCI_REG_INTR_CTRL, toclear); 570 } 571 } 572 if(sc->mpu_intr) { 573 (sc->mpu_intr)(sc->mpu); 574 } 575 snd_mtxunlock(sc->lock); 576 return; 577 } 578 579 static struct pcmchan_caps * 580 cmichan_getcaps(kobj_t obj, void *data) 581 { 582 return &cmi_caps; 583 } 584 585 static kobj_method_t cmichan_methods[] = { 586 KOBJMETHOD(channel_init, cmichan_init), 587 KOBJMETHOD(channel_setformat, cmichan_setformat), 588 KOBJMETHOD(channel_setspeed, cmichan_setspeed), 589 KOBJMETHOD(channel_setblocksize, cmichan_setblocksize), 590 KOBJMETHOD(channel_trigger, cmichan_trigger), 591 KOBJMETHOD(channel_getptr, cmichan_getptr), 592 KOBJMETHOD(channel_getcaps, cmichan_getcaps), 593 KOBJMETHOD_END 594 }; 595 CHANNEL_DECLARE(cmichan); 596 597 /* ------------------------------------------------------------------------- */ 598 /* Mixer - sb16 with kinks */ 599 600 static void 601 cmimix_wr(struct sc_info *sc, u_int8_t port, u_int8_t val) 602 { 603 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1); 604 cmi_wr(sc, CMPCI_REG_SBDATA, val, 1); 605 } 606 607 static u_int8_t 608 cmimix_rd(struct sc_info *sc, u_int8_t port) 609 { 610 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1); 611 return (u_int8_t)cmi_rd(sc, CMPCI_REG_SBDATA, 1); 612 } 613 614 struct sb16props { 615 u_int8_t rreg; /* right reg chan register */ 616 u_int8_t stereo:1; /* (no explanation needed, honest) */ 617 u_int8_t rec:1; /* recording source */ 618 u_int8_t bits:3; /* num bits to represent maximum gain rep */ 619 u_int8_t oselect; /* output select mask */ 620 u_int8_t iselect; /* right input select mask */ 621 } static const cmt[SOUND_MIXER_NRDEVICES] = { 622 [SOUND_MIXER_SYNTH] = {CMPCI_SB16_MIXER_FM_R, 1, 1, 5, 623 CMPCI_SB16_SW_FM, CMPCI_SB16_MIXER_FM_SRC_R}, 624 [SOUND_MIXER_CD] = {CMPCI_SB16_MIXER_CDDA_R, 1, 1, 5, 625 CMPCI_SB16_SW_CD, CMPCI_SB16_MIXER_CD_SRC_R}, 626 [SOUND_MIXER_LINE] = {CMPCI_SB16_MIXER_LINE_R, 1, 1, 5, 627 CMPCI_SB16_SW_LINE, CMPCI_SB16_MIXER_LINE_SRC_R}, 628 [SOUND_MIXER_MIC] = {CMPCI_SB16_MIXER_MIC, 0, 1, 5, 629 CMPCI_SB16_SW_MIC, CMPCI_SB16_MIXER_MIC_SRC}, 630 [SOUND_MIXER_SPEAKER] = {CMPCI_SB16_MIXER_SPEAKER, 0, 0, 2, 0, 0}, 631 [SOUND_MIXER_PCM] = {CMPCI_SB16_MIXER_VOICE_R, 1, 0, 5, 0, 0}, 632 [SOUND_MIXER_VOLUME] = {CMPCI_SB16_MIXER_MASTER_R, 1, 0, 5, 0, 0}, 633 /* These controls are not implemented in CMI8738, but maybe at a 634 future date. They are not documented in C-Media documentation, 635 though appear in other drivers for future h/w (ALSA, Linux, NetBSD). 636 */ 637 [SOUND_MIXER_IGAIN] = {CMPCI_SB16_MIXER_INGAIN_R, 1, 0, 2, 0, 0}, 638 [SOUND_MIXER_OGAIN] = {CMPCI_SB16_MIXER_OUTGAIN_R, 1, 0, 2, 0, 0}, 639 [SOUND_MIXER_BASS] = {CMPCI_SB16_MIXER_BASS_R, 1, 0, 4, 0, 0}, 640 [SOUND_MIXER_TREBLE] = {CMPCI_SB16_MIXER_TREBLE_R, 1, 0, 4, 0, 0}, 641 /* The mic pre-amp is implemented with non-SB16 compatible 642 registers. */ 643 [SOUND_MIXER_MONITOR] = {CMPCI_NON_SB16_CONTROL, 0, 1, 4, 0}, 644 }; 645 646 #define MIXER_GAIN_REG_RTOL(r) (r - 1) 647 648 static int 649 cmimix_init(struct snd_mixer *m) 650 { 651 struct sc_info *sc = mix_getdevinfo(m); 652 u_int32_t i,v; 653 654 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) { 655 if (cmt[i].bits) v |= 1 << i; 656 } 657 mix_setdevs(m, v); 658 659 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) { 660 if (cmt[i].rec) v |= 1 << i; 661 } 662 mix_setrecdevs(m, v); 663 664 cmimix_wr(sc, CMPCI_SB16_MIXER_RESET, 0); 665 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, 0); 666 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, 0); 667 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX, 668 CMPCI_SB16_SW_CD | CMPCI_SB16_SW_MIC | CMPCI_SB16_SW_LINE); 669 return 0; 670 } 671 672 static int 673 cmimix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right) 674 { 675 struct sc_info *sc = mix_getdevinfo(m); 676 u_int32_t r, l, max; 677 u_int8_t v; 678 679 max = (1 << cmt[dev].bits) - 1; 680 681 if (cmt[dev].rreg == CMPCI_NON_SB16_CONTROL) { 682 /* For time being this can only be one thing (mic in 683 * mic/aux reg) */ 684 v = cmi_rd(sc, CMPCI_REG_AUX_MIC, 1) & 0xf0; 685 l = left * max / 100; 686 /* 3 bit gain with LSB MICGAIN off(1),on(1) -> 4 bit value */ 687 v |= ((l << 1) | (~l >> 3)) & 0x0f; 688 cmi_wr(sc, CMPCI_REG_AUX_MIC, v, 1); 689 return 0; 690 } 691 692 l = (left * max / 100) << (8 - cmt[dev].bits); 693 if (cmt[dev].stereo) { 694 r = (right * max / 100) << (8 - cmt[dev].bits); 695 cmimix_wr(sc, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l); 696 cmimix_wr(sc, cmt[dev].rreg, r); 697 DEBMIX(printf("Mixer stereo write dev %d reg 0x%02x "\ 698 "value 0x%02x:0x%02x\n", 699 dev, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l, r)); 700 } else { 701 r = l; 702 cmimix_wr(sc, cmt[dev].rreg, l); 703 DEBMIX(printf("Mixer mono write dev %d reg 0x%02x " \ 704 "value 0x%02x:0x%02x\n", 705 dev, cmt[dev].rreg, l, l)); 706 } 707 708 /* Zero gain does not mute channel from output, but this does... */ 709 v = cmimix_rd(sc, CMPCI_SB16_MIXER_OUTMIX); 710 if (l == 0 && r == 0) { 711 v &= ~cmt[dev].oselect; 712 } else { 713 v |= cmt[dev].oselect; 714 } 715 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX, v); 716 717 return 0; 718 } 719 720 static u_int32_t 721 cmimix_setrecsrc(struct snd_mixer *m, u_int32_t src) 722 { 723 struct sc_info *sc = mix_getdevinfo(m); 724 u_int32_t i, ml, sl; 725 726 ml = sl = 0; 727 for(i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 728 if ((1<<i) & src) { 729 if (cmt[i].stereo) { 730 sl |= cmt[i].iselect; 731 } else { 732 ml |= cmt[i].iselect; 733 } 734 } 735 } 736 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, sl|ml); 737 DEBMIX(printf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n", 738 CMPCI_SB16_MIXER_ADCMIX_R, sl|ml)); 739 ml = CMPCI_SB16_MIXER_SRC_R_TO_L(ml); 740 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, sl|ml); 741 DEBMIX(printf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n", 742 CMPCI_SB16_MIXER_ADCMIX_L, sl|ml)); 743 744 return src; 745 } 746 747 /* Optional SPDIF support. */ 748 749 static int 750 cmi_initsys(struct sc_info* sc) 751 { 752 /* XXX: an user should be able to set this with a control tool, 753 if not done before 7.0-RELEASE, this needs to be converted 754 to a device specific sysctl "dev.pcm.X.yyy" via 755 device_get_sysctl_*() as discussed on multimedia@ in msg-id 756 <861wujij2q.fsf@xps.des.no> */ 757 SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev), 758 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 759 OID_AUTO, "spdif_enabled", CTLFLAG_RW, 760 &sc->spdif_enabled, 0, 761 "enable SPDIF output at 44.1 kHz and above"); 762 763 return 0; 764 } 765 766 /* ------------------------------------------------------------------------- */ 767 static kobj_method_t cmi_mixer_methods[] = { 768 KOBJMETHOD(mixer_init, cmimix_init), 769 KOBJMETHOD(mixer_set, cmimix_set), 770 KOBJMETHOD(mixer_setrecsrc, cmimix_setrecsrc), 771 KOBJMETHOD_END 772 }; 773 MIXER_DECLARE(cmi_mixer); 774 775 /* 776 * mpu401 functions 777 */ 778 779 static unsigned char 780 cmi_mread(struct mpu401 *arg, void *sc, int reg) 781 { 782 unsigned int d; 783 784 d = bus_space_read_1(0,0, 0x330 + reg); 785 /* printf("cmi_mread: reg %x %x\n",reg, d); 786 */ 787 return d; 788 } 789 790 static void 791 cmi_mwrite(struct mpu401 *arg, void *sc, int reg, unsigned char b) 792 { 793 794 bus_space_write_1(0,0,0x330 + reg , b); 795 } 796 797 static int 798 cmi_muninit(struct mpu401 *arg, void *cookie) 799 { 800 struct sc_info *sc = cookie; 801 802 snd_mtxlock(sc->lock); 803 sc->mpu_intr = NULL; 804 sc->mpu = NULL; 805 snd_mtxunlock(sc->lock); 806 807 return 0; 808 } 809 810 static kobj_method_t cmi_mpu_methods[] = { 811 KOBJMETHOD(mpufoi_read, cmi_mread), 812 KOBJMETHOD(mpufoi_write, cmi_mwrite), 813 KOBJMETHOD(mpufoi_uninit, cmi_muninit), 814 KOBJMETHOD_END 815 }; 816 817 static DEFINE_CLASS(cmi_mpu, cmi_mpu_methods, 0); 818 819 static void 820 cmi_midiattach(struct sc_info *sc) { 821 /* 822 const struct { 823 int port,bits; 824 } *p, ports[] = { 825 {0x330,0}, 826 {0x320,1}, 827 {0x310,2}, 828 {0x300,3}, 829 {0,0} } ; 830 Notes, CMPCI_REG_VMPUSEL sets the io port for the mpu. Does 831 anyone know how to bus_space tag? 832 */ 833 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE); 834 cmi_clr4(sc, CMPCI_REG_LEGACY_CTRL, 835 CMPCI_REG_VMPUSEL_MASK << CMPCI_REG_VMPUSEL_SHIFT); 836 cmi_set4(sc, CMPCI_REG_LEGACY_CTRL, 837 0 << CMPCI_REG_VMPUSEL_SHIFT ); 838 cmi_set4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE); 839 sc->mpu = mpu401_init(&cmi_mpu_class, sc, cmi_intr, &sc->mpu_intr); 840 } 841 842 /* ------------------------------------------------------------------------- */ 843 /* Power and reset */ 844 845 static void 846 cmi_power(struct sc_info *sc, int state) 847 { 848 switch (state) { 849 case 0: /* full power */ 850 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN); 851 break; 852 default: 853 /* power off */ 854 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN); 855 break; 856 } 857 } 858 859 static int 860 cmi_init(struct sc_info *sc) 861 { 862 /* Effect reset */ 863 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET); 864 DELAY(100); 865 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET); 866 867 /* Disable interrupts and channels */ 868 cmi_clr4(sc, CMPCI_REG_FUNC_0, 869 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE); 870 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, 871 CMPCI_REG_CH0_INTR_ENABLE | CMPCI_REG_CH1_INTR_ENABLE); 872 873 /* Configure DMA channels, ch0 = play, ch1 = capture */ 874 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_DIR); 875 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_DIR); 876 877 /* Attempt to enable 4 Channel output */ 878 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_N4SPK3D); 879 880 /* Disable SPDIF1 - not compatible with config */ 881 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF1_ENABLE); 882 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF_LOOP); 883 884 return 0; 885 } 886 887 static void 888 cmi_uninit(struct sc_info *sc) 889 { 890 /* Disable interrupts and channels */ 891 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, 892 CMPCI_REG_CH0_INTR_ENABLE | 893 CMPCI_REG_CH1_INTR_ENABLE | 894 CMPCI_REG_TDMA_INTR_ENABLE); 895 cmi_clr4(sc, CMPCI_REG_FUNC_0, 896 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE); 897 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE); 898 899 if( sc->mpu ) 900 sc->mpu_intr = NULL; 901 } 902 903 /* ------------------------------------------------------------------------- */ 904 /* Bus and device registration */ 905 static int 906 cmi_probe(device_t dev) 907 { 908 switch(pci_get_devid(dev)) { 909 case CMI8338A_PCI_ID: 910 device_set_desc(dev, "CMedia CMI8338A"); 911 return BUS_PROBE_DEFAULT; 912 case CMI8338B_PCI_ID: 913 device_set_desc(dev, "CMedia CMI8338B"); 914 return BUS_PROBE_DEFAULT; 915 case CMI8738_PCI_ID: 916 device_set_desc(dev, "CMedia CMI8738"); 917 return BUS_PROBE_DEFAULT; 918 case CMI8738B_PCI_ID: 919 device_set_desc(dev, "CMedia CMI8738B"); 920 return BUS_PROBE_DEFAULT; 921 case CMI120_USB_ID: 922 device_set_desc(dev, "CMedia CMI120"); 923 return BUS_PROBE_DEFAULT; 924 default: 925 return ENXIO; 926 } 927 } 928 929 static int 930 cmi_attach(device_t dev) 931 { 932 struct sc_info *sc; 933 char status[SND_STATUSLEN]; 934 935 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 936 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "snd_cmi softc"); 937 pci_enable_busmaster(dev); 938 939 sc->dev = dev; 940 sc->regid = PCIR_BAR(0); 941 sc->reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->regid, 942 RF_ACTIVE); 943 if (!sc->reg) { 944 device_printf(dev, "cmi_attach: Cannot allocate bus resource\n"); 945 goto bad; 946 } 947 sc->st = rman_get_bustag(sc->reg); 948 sc->sh = rman_get_bushandle(sc->reg); 949 950 if (0) 951 cmi_midiattach(sc); 952 953 sc->irqid = 0; 954 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid, 955 RF_ACTIVE | RF_SHAREABLE); 956 if (!sc->irq || 957 snd_setup_intr(dev, sc->irq, INTR_MPSAFE, cmi_intr, sc, &sc->ih)) { 958 device_printf(dev, "cmi_attach: Unable to map interrupt\n"); 959 goto bad; 960 } 961 962 sc->bufsz = pcm_getbuffersize(dev, 4096, CMI_DEFAULT_BUFSZ, 65536); 963 964 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2, 965 /*boundary*/0, 966 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 967 /*highaddr*/BUS_SPACE_MAXADDR, 968 /*filter*/NULL, /*filterarg*/NULL, 969 /*maxsize*/sc->bufsz, /*nsegments*/1, 970 /*maxsegz*/0x3ffff, /*flags*/0, 971 /*lockfunc*/NULL, 972 /*lockfunc*/NULL, 973 &sc->parent_dmat) != 0) { 974 device_printf(dev, "cmi_attach: Unable to create dma tag\n"); 975 goto bad; 976 } 977 978 cmi_power(sc, 0); 979 if (cmi_init(sc)) 980 goto bad; 981 982 if (mixer_init(dev, &cmi_mixer_class, sc)) 983 goto bad; 984 985 if (pcm_register(dev, sc, 1, 1)) 986 goto bad; 987 988 cmi_initsys(sc); 989 990 pcm_addchan(dev, PCMDIR_PLAY, &cmichan_class, sc); 991 pcm_addchan(dev, PCMDIR_REC, &cmichan_class, sc); 992 993 snprintf(status, SND_STATUSLEN, "at io 0x%jx irq %jd %s", 994 rman_get_start(sc->reg), rman_get_start(sc->irq),PCM_KLDSTRING(snd_cmi)); 995 pcm_setstatus(dev, status); 996 997 DEB(printf("cmi_attach: succeeded\n")); 998 return 0; 999 1000 bad: 1001 if (sc->parent_dmat) 1002 bus_dma_tag_destroy(sc->parent_dmat); 1003 if (sc->ih) 1004 bus_teardown_intr(dev, sc->irq, sc->ih); 1005 if (sc->irq) 1006 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 1007 if (sc->reg) 1008 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg); 1009 if (sc->lock) 1010 snd_mtxfree(sc->lock); 1011 if (sc) 1012 free(sc, M_DEVBUF); 1013 1014 return ENXIO; 1015 } 1016 1017 static int 1018 cmi_detach(device_t dev) 1019 { 1020 struct sc_info *sc; 1021 int r; 1022 1023 r = pcm_unregister(dev); 1024 if (r) return r; 1025 1026 sc = pcm_getdevinfo(dev); 1027 cmi_uninit(sc); 1028 cmi_power(sc, 3); 1029 1030 bus_dma_tag_destroy(sc->parent_dmat); 1031 bus_teardown_intr(dev, sc->irq, sc->ih); 1032 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 1033 if(sc->mpu) 1034 mpu401_uninit(sc->mpu); 1035 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg); 1036 if (sc->mpu_reg) 1037 bus_release_resource(dev, SYS_RES_IOPORT, sc->mpu_regid, sc->mpu_reg); 1038 1039 snd_mtxfree(sc->lock); 1040 free(sc, M_DEVBUF); 1041 1042 return 0; 1043 } 1044 1045 static int 1046 cmi_suspend(device_t dev) 1047 { 1048 struct sc_info *sc = pcm_getdevinfo(dev); 1049 1050 snd_mtxlock(sc->lock); 1051 sc->pch.dma_was_active = cmi_ch0_stop(sc, &sc->pch); 1052 sc->rch.dma_was_active = cmi_ch1_stop(sc, &sc->rch); 1053 cmi_power(sc, 3); 1054 snd_mtxunlock(sc->lock); 1055 return 0; 1056 } 1057 1058 static int 1059 cmi_resume(device_t dev) 1060 { 1061 struct sc_info *sc = pcm_getdevinfo(dev); 1062 1063 snd_mtxlock(sc->lock); 1064 cmi_power(sc, 0); 1065 if (cmi_init(sc) != 0) { 1066 device_printf(dev, "unable to reinitialize the card\n"); 1067 snd_mtxunlock(sc->lock); 1068 return ENXIO; 1069 } 1070 1071 if (mixer_reinit(dev) == -1) { 1072 device_printf(dev, "unable to reinitialize the mixer\n"); 1073 snd_mtxunlock(sc->lock); 1074 return ENXIO; 1075 } 1076 1077 if (sc->pch.dma_was_active) { 1078 cmichan_setspeed(NULL, &sc->pch, sc->pch.spd); 1079 cmichan_setformat(NULL, &sc->pch, sc->pch.fmt); 1080 cmi_ch0_start(sc, &sc->pch); 1081 } 1082 1083 if (sc->rch.dma_was_active) { 1084 cmichan_setspeed(NULL, &sc->rch, sc->rch.spd); 1085 cmichan_setformat(NULL, &sc->rch, sc->rch.fmt); 1086 cmi_ch1_start(sc, &sc->rch); 1087 } 1088 snd_mtxunlock(sc->lock); 1089 return 0; 1090 } 1091 1092 static device_method_t cmi_methods[] = { 1093 DEVMETHOD(device_probe, cmi_probe), 1094 DEVMETHOD(device_attach, cmi_attach), 1095 DEVMETHOD(device_detach, cmi_detach), 1096 DEVMETHOD(device_resume, cmi_resume), 1097 DEVMETHOD(device_suspend, cmi_suspend), 1098 { 0, 0 } 1099 }; 1100 1101 static driver_t cmi_driver = { 1102 "pcm", 1103 cmi_methods, 1104 PCM_SOFTC_SIZE 1105 }; 1106 1107 DRIVER_MODULE(snd_cmi, pci, cmi_driver, 0, 0); 1108 MODULE_DEPEND(snd_cmi, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1109 MODULE_DEPEND(snd_cmi, midi, 1,1,1); 1110 MODULE_VERSION(snd_cmi, 1); 1111