1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2012-2016 Ruslan Bukin <br@bsdpad.com> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #define PCI_VENDOR_XILINX 0x10ee 30 #define PCI_DEVICE_XILINX_HDSPE 0x3fc6 /* AIO, MADI, AES, RayDAT */ 31 #define PCI_CLASS_REVISION 0x08 32 #define PCI_REVISION_AIO 212 33 #define PCI_REVISION_RAYDAT 211 34 35 #define HDSPE_AIO 0 36 #define HDSPE_RAYDAT 1 37 38 /* Hardware mixer */ 39 #define HDSPE_OUT_ENABLE_BASE 512 40 #define HDSPE_IN_ENABLE_BASE 768 41 #define HDSPE_MIXER_BASE 32768 42 #define HDSPE_MAX_GAIN 32768 43 44 /* Buffer */ 45 #define HDSPE_PAGE_ADDR_BUF_OUT 8192 46 #define HDSPE_PAGE_ADDR_BUF_IN (HDSPE_PAGE_ADDR_BUF_OUT + 64 * 16 * 4) 47 #define HDSPE_BUF_POSITION_MASK 0x000FFC0 48 49 /* Frequency */ 50 #define HDSPE_FREQ_0 (1 << 6) 51 #define HDSPE_FREQ_1 (1 << 7) 52 #define HDSPE_FREQ_DOUBLE (1 << 8) 53 #define HDSPE_FREQ_QUAD (1 << 31) 54 55 #define HDSPE_FREQ_32000 HDSPE_FREQ_0 56 #define HDSPE_FREQ_44100 HDSPE_FREQ_1 57 #define HDSPE_FREQ_48000 (HDSPE_FREQ_0 | HDSPE_FREQ_1) 58 #define HDSPE_FREQ_MASK (HDSPE_FREQ_0 | HDSPE_FREQ_1 | \ 59 HDSPE_FREQ_DOUBLE | HDSPE_FREQ_QUAD) 60 #define HDSPE_FREQ_MASK_DEFAULT HDSPE_FREQ_48000 61 #define HDSPE_FREQ_REG 256 62 #define HDSPE_FREQ_AIO 104857600000000ULL 63 64 #define HDSPE_SPEED_DEFAULT 48000 65 66 /* Latency */ 67 #define HDSPE_LAT_0 (1 << 1) 68 #define HDSPE_LAT_1 (1 << 2) 69 #define HDSPE_LAT_2 (1 << 3) 70 #define HDSPE_LAT_MASK (HDSPE_LAT_0 | HDSPE_LAT_1 | HDSPE_LAT_2) 71 #define HDSPE_LAT_BYTES_MAX (4096 * 4) 72 #define HDSPE_LAT_BYTES_MIN (32 * 4) 73 #define hdspe_encode_latency(x) (((x)<<1) & HDSPE_LAT_MASK) 74 75 /* Gain */ 76 #define HDSP_ADGain0 (1 << 25) 77 #define HDSP_ADGain1 (1 << 26) 78 #define HDSP_DAGain0 (1 << 27) 79 #define HDSP_DAGain1 (1 << 28) 80 #define HDSP_PhoneGain0 (1 << 29) 81 #define HDSP_PhoneGain1 (1 << 30) 82 83 #define HDSP_ADGainMask (HDSP_ADGain0 | HDSP_ADGain1) 84 #define HDSP_ADGainMinus10dBV (HDSP_ADGainMask) 85 #define HDSP_ADGainPlus4dBu (HDSP_ADGain0) 86 #define HDSP_ADGainLowGain 0 87 88 #define HDSP_DAGainMask (HDSP_DAGain0 | HDSP_DAGain1) 89 #define HDSP_DAGainHighGain (HDSP_DAGainMask) 90 #define HDSP_DAGainPlus4dBu (HDSP_DAGain0) 91 #define HDSP_DAGainMinus10dBV 0 92 93 #define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1) 94 #define HDSP_PhoneGain0dB HDSP_PhoneGainMask 95 #define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0) 96 #define HDSP_PhoneGainMinus12dB 0 97 98 /* Settings */ 99 #define HDSPE_SETTINGS_REG 0 100 #define HDSPE_CONTROL_REG 64 101 #define HDSPE_STATUS_REG 0 102 #define HDSPE_STATUS1_REG 64 103 #define HDSPE_STATUS2_REG 192 104 #define HDSPE_ENABLE (1 << 0) 105 106 /* Interrupts */ 107 #define HDSPE_AUDIO_IRQ_PENDING (1 << 0) 108 #define HDSPE_AUDIO_INT_ENABLE (1 << 5) 109 #define HDSPE_INTERRUPT_ACK 96 110 111 /* Channels */ 112 #define HDSPE_MAX_SLOTS 64 /* Mono channels */ 113 #define HDSPE_MAX_CHANS (HDSPE_MAX_SLOTS / 2) /* Stereo pairs */ 114 115 #define HDSPE_CHANBUF_SAMPLES (16 * 1024) 116 #define HDSPE_CHANBUF_SIZE (4 * HDSPE_CHANBUF_SAMPLES) 117 #define HDSPE_DMASEGSIZE (HDSPE_CHANBUF_SIZE * HDSPE_MAX_SLOTS) 118 119 struct hdspe_channel { 120 uint32_t left; 121 uint32_t right; 122 char *descr; 123 uint32_t play; 124 uint32_t rec; 125 }; 126 127 /* Clock sources */ 128 #define HDSPE_SETTING_MASTER (1 << 0) 129 #define HDSPE_SETTING_CLOCK_MASK 0x1f 130 131 #define HDSPE_STATUS1_CLOCK_SHIFT 28 132 #define HDSPE_STATUS1_CLOCK_MASK (0x0f << HDSPE_STATUS1_CLOCK_SHIFT) 133 #define HDSPE_STATUS1_CLOCK(n) (((n) << HDSPE_STATUS1_CLOCK_SHIFT) & \ 134 HDSPE_STATUS1_CLOCK_MASK) 135 136 struct hdspe_clock_source { 137 char *name; 138 uint32_t setting; 139 uint32_t status; 140 uint32_t lock_bit; 141 uint32_t sync_bit; 142 }; 143 144 static MALLOC_DEFINE(M_HDSPE, "hdspe", "hdspe audio"); 145 146 /* Channel registers */ 147 struct sc_chinfo { 148 struct snd_dbuf *buffer; 149 struct pcm_channel *channel; 150 struct sc_pcminfo *parent; 151 152 /* Channel information */ 153 uint32_t dir; 154 uint32_t format; 155 uint32_t lslot; 156 uint32_t rslot; 157 uint32_t lvol; 158 uint32_t rvol; 159 160 /* Buffer */ 161 uint32_t *data; 162 uint32_t size; 163 164 /* Flags */ 165 uint32_t run; 166 }; 167 168 /* PCM device private data */ 169 struct sc_pcminfo { 170 device_t dev; 171 uint32_t (*ih) (struct sc_pcminfo *scp); 172 uint32_t chnum; 173 struct sc_chinfo chan[HDSPE_MAX_CHANS]; 174 struct sc_info *sc; 175 struct hdspe_channel *hc; 176 }; 177 178 /* HDSPe device private data */ 179 struct sc_info { 180 device_t dev; 181 struct mtx *lock; 182 183 uint32_t ctrl_register; 184 uint32_t settings_register; 185 uint32_t type; 186 187 /* Control/Status register */ 188 struct resource *cs; 189 int csid; 190 bus_space_tag_t cst; 191 bus_space_handle_t csh; 192 193 struct resource *irq; 194 int irqid; 195 void *ih; 196 bus_dma_tag_t dmat; 197 198 /* Play/Record DMA buffers */ 199 uint32_t *pbuf; 200 uint32_t *rbuf; 201 uint32_t bufsize; 202 bus_dmamap_t pmap; 203 bus_dmamap_t rmap; 204 uint32_t period; 205 uint32_t speed; 206 }; 207 208 #define hdspe_read_1(sc, regno) \ 209 bus_space_read_1((sc)->cst, (sc)->csh, (regno)) 210 #define hdspe_read_2(sc, regno) \ 211 bus_space_read_2((sc)->cst, (sc)->csh, (regno)) 212 #define hdspe_read_4(sc, regno) \ 213 bus_space_read_4((sc)->cst, (sc)->csh, (regno)) 214 215 #define hdspe_write_1(sc, regno, data) \ 216 bus_space_write_1((sc)->cst, (sc)->csh, (regno), (data)) 217 #define hdspe_write_2(sc, regno, data) \ 218 bus_space_write_2((sc)->cst, (sc)->csh, (regno), (data)) 219 #define hdspe_write_4(sc, regno, data) \ 220 bus_space_write_4((sc)->cst, (sc)->csh, (regno), (data)) 221