1 /* $NetBSD: if_stge.c,v 1.32 2005/12/11 12:22:49 christos Exp $ */ 2 3 /*- 4 * SPDX-License-Identifier: BSD-2-Clause-NetBSD 5 * 6 * Copyright (c) 2001 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to The NetBSD Foundation 10 * by Jason R. Thorpe. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Device driver for the Sundance Tech. TC9021 10/100/1000 36 * Ethernet controller. 37 */ 38 39 #include <sys/cdefs.h> 40 __FBSDID("$FreeBSD$"); 41 42 #ifdef HAVE_KERNEL_OPTION_HEADERS 43 #include "opt_device_polling.h" 44 #endif 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/endian.h> 49 #include <sys/mbuf.h> 50 #include <sys/malloc.h> 51 #include <sys/kernel.h> 52 #include <sys/module.h> 53 #include <sys/socket.h> 54 #include <sys/sockio.h> 55 #include <sys/sysctl.h> 56 #include <sys/taskqueue.h> 57 58 #include <net/bpf.h> 59 #include <net/ethernet.h> 60 #include <net/if.h> 61 #include <net/if_var.h> 62 #include <net/if_dl.h> 63 #include <net/if_media.h> 64 #include <net/if_types.h> 65 #include <net/if_vlan_var.h> 66 67 #include <machine/bus.h> 68 #include <machine/resource.h> 69 #include <sys/bus.h> 70 #include <sys/rman.h> 71 72 #include <dev/mii/mii.h> 73 #include <dev/mii/mii_bitbang.h> 74 #include <dev/mii/miivar.h> 75 76 #include <dev/pci/pcireg.h> 77 #include <dev/pci/pcivar.h> 78 79 #include <dev/stge/if_stgereg.h> 80 81 #define STGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 82 83 MODULE_DEPEND(stge, pci, 1, 1, 1); 84 MODULE_DEPEND(stge, ether, 1, 1, 1); 85 MODULE_DEPEND(stge, miibus, 1, 1, 1); 86 87 /* "device miibus" required. See GENERIC if you get errors here. */ 88 #include "miibus_if.h" 89 90 /* 91 * Devices supported by this driver. 92 */ 93 static const struct stge_product { 94 uint16_t stge_vendorid; 95 uint16_t stge_deviceid; 96 const char *stge_name; 97 } stge_products[] = { 98 { VENDOR_SUNDANCETI, DEVICEID_SUNDANCETI_ST1023, 99 "Sundance ST-1023 Gigabit Ethernet" }, 100 101 { VENDOR_SUNDANCETI, DEVICEID_SUNDANCETI_ST2021, 102 "Sundance ST-2021 Gigabit Ethernet" }, 103 104 { VENDOR_TAMARACK, DEVICEID_TAMARACK_TC9021, 105 "Tamarack TC9021 Gigabit Ethernet" }, 106 107 { VENDOR_TAMARACK, DEVICEID_TAMARACK_TC9021_ALT, 108 "Tamarack TC9021 Gigabit Ethernet" }, 109 110 /* 111 * The Sundance sample boards use the Sundance vendor ID, 112 * but the Tamarack product ID. 113 */ 114 { VENDOR_SUNDANCETI, DEVICEID_TAMARACK_TC9021, 115 "Sundance TC9021 Gigabit Ethernet" }, 116 117 { VENDOR_SUNDANCETI, DEVICEID_TAMARACK_TC9021_ALT, 118 "Sundance TC9021 Gigabit Ethernet" }, 119 120 { VENDOR_DLINK, DEVICEID_DLINK_DL4000, 121 "D-Link DL-4000 Gigabit Ethernet" }, 122 123 { VENDOR_ANTARES, DEVICEID_ANTARES_TC9021, 124 "Antares Gigabit Ethernet" } 125 }; 126 127 static int stge_probe(device_t); 128 static int stge_attach(device_t); 129 static int stge_detach(device_t); 130 static int stge_shutdown(device_t); 131 static int stge_suspend(device_t); 132 static int stge_resume(device_t); 133 134 static int stge_encap(struct stge_softc *, struct mbuf **); 135 static void stge_start(if_t); 136 static void stge_start_locked(if_t); 137 static void stge_watchdog(struct stge_softc *); 138 static int stge_ioctl(if_t, u_long, caddr_t); 139 static void stge_init(void *); 140 static void stge_init_locked(struct stge_softc *); 141 static void stge_vlan_setup(struct stge_softc *); 142 static void stge_stop(struct stge_softc *); 143 static void stge_start_tx(struct stge_softc *); 144 static void stge_start_rx(struct stge_softc *); 145 static void stge_stop_tx(struct stge_softc *); 146 static void stge_stop_rx(struct stge_softc *); 147 148 static void stge_reset(struct stge_softc *, uint32_t); 149 static int stge_eeprom_wait(struct stge_softc *); 150 static void stge_read_eeprom(struct stge_softc *, int, uint16_t *); 151 static void stge_tick(void *); 152 static void stge_stats_update(struct stge_softc *); 153 static void stge_set_filter(struct stge_softc *); 154 static void stge_set_multi(struct stge_softc *); 155 156 static void stge_link_task(void *, int); 157 static void stge_intr(void *); 158 static __inline int stge_tx_error(struct stge_softc *); 159 static void stge_txeof(struct stge_softc *); 160 static int stge_rxeof(struct stge_softc *); 161 static __inline void stge_discard_rxbuf(struct stge_softc *, int); 162 static int stge_newbuf(struct stge_softc *, int); 163 #ifndef __NO_STRICT_ALIGNMENT 164 static __inline struct mbuf *stge_fixup_rx(struct stge_softc *, struct mbuf *); 165 #endif 166 167 static int stge_miibus_readreg(device_t, int, int); 168 static int stge_miibus_writereg(device_t, int, int, int); 169 static void stge_miibus_statchg(device_t); 170 static int stge_mediachange(if_t); 171 static void stge_mediastatus(if_t, struct ifmediareq *); 172 173 static void stge_dmamap_cb(void *, bus_dma_segment_t *, int, int); 174 static int stge_dma_alloc(struct stge_softc *); 175 static void stge_dma_free(struct stge_softc *); 176 static void stge_dma_wait(struct stge_softc *); 177 static void stge_init_tx_ring(struct stge_softc *); 178 static int stge_init_rx_ring(struct stge_softc *); 179 #ifdef DEVICE_POLLING 180 static int stge_poll(if_t, enum poll_cmd, int); 181 #endif 182 183 static void stge_setwol(struct stge_softc *); 184 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 185 static int sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS); 186 static int sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS); 187 188 /* 189 * MII bit-bang glue 190 */ 191 static uint32_t stge_mii_bitbang_read(device_t); 192 static void stge_mii_bitbang_write(device_t, uint32_t); 193 194 static const struct mii_bitbang_ops stge_mii_bitbang_ops = { 195 stge_mii_bitbang_read, 196 stge_mii_bitbang_write, 197 { 198 PC_MgmtData, /* MII_BIT_MDO */ 199 PC_MgmtData, /* MII_BIT_MDI */ 200 PC_MgmtClk, /* MII_BIT_MDC */ 201 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 202 0, /* MII_BIT_DIR_PHY_HOST */ 203 } 204 }; 205 206 static device_method_t stge_methods[] = { 207 /* Device interface */ 208 DEVMETHOD(device_probe, stge_probe), 209 DEVMETHOD(device_attach, stge_attach), 210 DEVMETHOD(device_detach, stge_detach), 211 DEVMETHOD(device_shutdown, stge_shutdown), 212 DEVMETHOD(device_suspend, stge_suspend), 213 DEVMETHOD(device_resume, stge_resume), 214 215 /* MII interface */ 216 DEVMETHOD(miibus_readreg, stge_miibus_readreg), 217 DEVMETHOD(miibus_writereg, stge_miibus_writereg), 218 DEVMETHOD(miibus_statchg, stge_miibus_statchg), 219 220 DEVMETHOD_END 221 }; 222 223 static driver_t stge_driver = { 224 "stge", 225 stge_methods, 226 sizeof(struct stge_softc) 227 }; 228 229 DRIVER_MODULE(stge, pci, stge_driver, 0, 0); 230 DRIVER_MODULE(miibus, stge, miibus_driver, 0, 0); 231 232 static struct resource_spec stge_res_spec_io[] = { 233 { SYS_RES_IOPORT, PCIR_BAR(0), RF_ACTIVE }, 234 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 235 { -1, 0, 0 } 236 }; 237 238 static struct resource_spec stge_res_spec_mem[] = { 239 { SYS_RES_MEMORY, PCIR_BAR(1), RF_ACTIVE }, 240 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 241 { -1, 0, 0 } 242 }; 243 244 /* 245 * stge_mii_bitbang_read: [mii bit-bang interface function] 246 * 247 * Read the MII serial port for the MII bit-bang module. 248 */ 249 static uint32_t 250 stge_mii_bitbang_read(device_t dev) 251 { 252 struct stge_softc *sc; 253 uint32_t val; 254 255 sc = device_get_softc(dev); 256 257 val = CSR_READ_1(sc, STGE_PhyCtrl); 258 CSR_BARRIER(sc, STGE_PhyCtrl, 1, 259 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 260 return (val); 261 } 262 263 /* 264 * stge_mii_bitbang_write: [mii big-bang interface function] 265 * 266 * Write the MII serial port for the MII bit-bang module. 267 */ 268 static void 269 stge_mii_bitbang_write(device_t dev, uint32_t val) 270 { 271 struct stge_softc *sc; 272 273 sc = device_get_softc(dev); 274 275 CSR_WRITE_1(sc, STGE_PhyCtrl, val); 276 CSR_BARRIER(sc, STGE_PhyCtrl, 1, 277 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 278 } 279 280 /* 281 * sc_miibus_readreg: [mii interface function] 282 * 283 * Read a PHY register on the MII of the TC9021. 284 */ 285 static int 286 stge_miibus_readreg(device_t dev, int phy, int reg) 287 { 288 struct stge_softc *sc; 289 int error, val; 290 291 sc = device_get_softc(dev); 292 293 if (reg == STGE_PhyCtrl) { 294 /* XXX allow ip1000phy read STGE_PhyCtrl register. */ 295 STGE_MII_LOCK(sc); 296 error = CSR_READ_1(sc, STGE_PhyCtrl); 297 STGE_MII_UNLOCK(sc); 298 return (error); 299 } 300 301 STGE_MII_LOCK(sc); 302 val = mii_bitbang_readreg(dev, &stge_mii_bitbang_ops, phy, reg); 303 STGE_MII_UNLOCK(sc); 304 return (val); 305 } 306 307 /* 308 * stge_miibus_writereg: [mii interface function] 309 * 310 * Write a PHY register on the MII of the TC9021. 311 */ 312 static int 313 stge_miibus_writereg(device_t dev, int phy, int reg, int val) 314 { 315 struct stge_softc *sc; 316 317 sc = device_get_softc(dev); 318 319 STGE_MII_LOCK(sc); 320 mii_bitbang_writereg(dev, &stge_mii_bitbang_ops, phy, reg, val); 321 STGE_MII_UNLOCK(sc); 322 return (0); 323 } 324 325 /* 326 * stge_miibus_statchg: [mii interface function] 327 * 328 * Callback from MII layer when media changes. 329 */ 330 static void 331 stge_miibus_statchg(device_t dev) 332 { 333 struct stge_softc *sc; 334 335 sc = device_get_softc(dev); 336 taskqueue_enqueue(taskqueue_swi, &sc->sc_link_task); 337 } 338 339 /* 340 * stge_mediastatus: [ifmedia interface function] 341 * 342 * Get the current interface media status. 343 */ 344 static void 345 stge_mediastatus(if_t ifp, struct ifmediareq *ifmr) 346 { 347 struct stge_softc *sc; 348 struct mii_data *mii; 349 350 sc = if_getsoftc(ifp); 351 mii = device_get_softc(sc->sc_miibus); 352 353 mii_pollstat(mii); 354 ifmr->ifm_status = mii->mii_media_status; 355 ifmr->ifm_active = mii->mii_media_active; 356 } 357 358 /* 359 * stge_mediachange: [ifmedia interface function] 360 * 361 * Set hardware to newly-selected media. 362 */ 363 static int 364 stge_mediachange(if_t ifp) 365 { 366 struct stge_softc *sc; 367 struct mii_data *mii; 368 369 sc = if_getsoftc(ifp); 370 mii = device_get_softc(sc->sc_miibus); 371 mii_mediachg(mii); 372 373 return (0); 374 } 375 376 static int 377 stge_eeprom_wait(struct stge_softc *sc) 378 { 379 int i; 380 381 for (i = 0; i < STGE_TIMEOUT; i++) { 382 DELAY(1000); 383 if ((CSR_READ_2(sc, STGE_EepromCtrl) & EC_EepromBusy) == 0) 384 return (0); 385 } 386 return (1); 387 } 388 389 /* 390 * stge_read_eeprom: 391 * 392 * Read data from the serial EEPROM. 393 */ 394 static void 395 stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data) 396 { 397 398 if (stge_eeprom_wait(sc)) 399 device_printf(sc->sc_dev, "EEPROM failed to come ready\n"); 400 401 CSR_WRITE_2(sc, STGE_EepromCtrl, 402 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR)); 403 if (stge_eeprom_wait(sc)) 404 device_printf(sc->sc_dev, "EEPROM read timed out\n"); 405 *data = CSR_READ_2(sc, STGE_EepromData); 406 } 407 408 static int 409 stge_probe(device_t dev) 410 { 411 const struct stge_product *sp; 412 int i; 413 uint16_t vendor, devid; 414 415 vendor = pci_get_vendor(dev); 416 devid = pci_get_device(dev); 417 sp = stge_products; 418 for (i = 0; i < nitems(stge_products); i++, sp++) { 419 if (vendor == sp->stge_vendorid && 420 devid == sp->stge_deviceid) { 421 device_set_desc(dev, sp->stge_name); 422 return (BUS_PROBE_DEFAULT); 423 } 424 } 425 426 return (ENXIO); 427 } 428 429 static int 430 stge_attach(device_t dev) 431 { 432 struct stge_softc *sc; 433 if_t ifp; 434 uint8_t enaddr[ETHER_ADDR_LEN]; 435 int error, flags, i; 436 uint16_t cmd; 437 uint32_t val; 438 439 error = 0; 440 sc = device_get_softc(dev); 441 sc->sc_dev = dev; 442 443 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 444 MTX_DEF); 445 mtx_init(&sc->sc_mii_mtx, "stge_mii_mutex", NULL, MTX_DEF); 446 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0); 447 TASK_INIT(&sc->sc_link_task, 0, stge_link_task, sc); 448 449 /* 450 * Map the device. 451 */ 452 pci_enable_busmaster(dev); 453 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 454 val = pci_read_config(dev, PCIR_BAR(1), 4); 455 if (PCI_BAR_IO(val)) 456 sc->sc_spec = stge_res_spec_mem; 457 else { 458 val = pci_read_config(dev, PCIR_BAR(0), 4); 459 if (!PCI_BAR_IO(val)) { 460 device_printf(sc->sc_dev, "couldn't locate IO BAR\n"); 461 error = ENXIO; 462 goto fail; 463 } 464 sc->sc_spec = stge_res_spec_io; 465 } 466 error = bus_alloc_resources(dev, sc->sc_spec, sc->sc_res); 467 if (error != 0) { 468 device_printf(dev, "couldn't allocate %s resources\n", 469 sc->sc_spec == stge_res_spec_mem ? "memory" : "I/O"); 470 goto fail; 471 } 472 sc->sc_rev = pci_get_revid(dev); 473 474 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 475 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 476 "rxint_nframe", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 477 &sc->sc_rxint_nframe, 0, sysctl_hw_stge_rxint_nframe, "I", 478 "stge rx interrupt nframe"); 479 480 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 481 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 482 "rxint_dmawait", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 483 &sc->sc_rxint_dmawait, 0, sysctl_hw_stge_rxint_dmawait, "I", 484 "stge rx interrupt dmawait"); 485 486 /* Pull in device tunables. */ 487 sc->sc_rxint_nframe = STGE_RXINT_NFRAME_DEFAULT; 488 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 489 "rxint_nframe", &sc->sc_rxint_nframe); 490 if (error == 0) { 491 if (sc->sc_rxint_nframe < STGE_RXINT_NFRAME_MIN || 492 sc->sc_rxint_nframe > STGE_RXINT_NFRAME_MAX) { 493 device_printf(dev, "rxint_nframe value out of range; " 494 "using default: %d\n", STGE_RXINT_NFRAME_DEFAULT); 495 sc->sc_rxint_nframe = STGE_RXINT_NFRAME_DEFAULT; 496 } 497 } 498 499 sc->sc_rxint_dmawait = STGE_RXINT_DMAWAIT_DEFAULT; 500 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 501 "rxint_dmawait", &sc->sc_rxint_dmawait); 502 if (error == 0) { 503 if (sc->sc_rxint_dmawait < STGE_RXINT_DMAWAIT_MIN || 504 sc->sc_rxint_dmawait > STGE_RXINT_DMAWAIT_MAX) { 505 device_printf(dev, "rxint_dmawait value out of range; " 506 "using default: %d\n", STGE_RXINT_DMAWAIT_DEFAULT); 507 sc->sc_rxint_dmawait = STGE_RXINT_DMAWAIT_DEFAULT; 508 } 509 } 510 511 if ((error = stge_dma_alloc(sc)) != 0) 512 goto fail; 513 514 /* 515 * Determine if we're copper or fiber. It affects how we 516 * reset the card. 517 */ 518 if (CSR_READ_4(sc, STGE_AsicCtrl) & AC_PhyMedia) 519 sc->sc_usefiber = 1; 520 else 521 sc->sc_usefiber = 0; 522 523 /* Load LED configuration from EEPROM. */ 524 stge_read_eeprom(sc, STGE_EEPROM_LEDMode, &sc->sc_led); 525 526 /* 527 * Reset the chip to a known state. 528 */ 529 STGE_LOCK(sc); 530 stge_reset(sc, STGE_RESET_FULL); 531 STGE_UNLOCK(sc); 532 533 /* 534 * Reading the station address from the EEPROM doesn't seem 535 * to work, at least on my sample boards. Instead, since 536 * the reset sequence does AutoInit, read it from the station 537 * address registers. For Sundance 1023 you can only read it 538 * from EEPROM. 539 */ 540 if (pci_get_device(dev) != DEVICEID_SUNDANCETI_ST1023) { 541 uint16_t v; 542 543 v = CSR_READ_2(sc, STGE_StationAddress0); 544 enaddr[0] = v & 0xff; 545 enaddr[1] = v >> 8; 546 v = CSR_READ_2(sc, STGE_StationAddress1); 547 enaddr[2] = v & 0xff; 548 enaddr[3] = v >> 8; 549 v = CSR_READ_2(sc, STGE_StationAddress2); 550 enaddr[4] = v & 0xff; 551 enaddr[5] = v >> 8; 552 sc->sc_stge1023 = 0; 553 } else { 554 uint16_t myaddr[ETHER_ADDR_LEN / 2]; 555 for (i = 0; i <ETHER_ADDR_LEN / 2; i++) { 556 stge_read_eeprom(sc, STGE_EEPROM_StationAddress0 + i, 557 &myaddr[i]); 558 myaddr[i] = le16toh(myaddr[i]); 559 } 560 bcopy(myaddr, enaddr, sizeof(enaddr)); 561 sc->sc_stge1023 = 1; 562 } 563 564 ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 565 if (ifp == NULL) { 566 device_printf(sc->sc_dev, "failed to if_alloc()\n"); 567 error = ENXIO; 568 goto fail; 569 } 570 571 if_setsoftc(ifp, sc); 572 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 573 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 574 if_setioctlfn(ifp, stge_ioctl); 575 if_setstartfn(ifp, stge_start); 576 if_setinitfn(ifp, stge_init); 577 if_setsendqlen(ifp, STGE_TX_RING_CNT - 1); 578 if_setsendqready(ifp); 579 /* Revision B3 and earlier chips have checksum bug. */ 580 if (sc->sc_rev >= 0x0c) { 581 if_sethwassist(ifp, STGE_CSUM_FEATURES); 582 if_setcapabilities(ifp, IFCAP_HWCSUM); 583 } else { 584 if_sethwassist(ifp, 0); 585 if_setcapabilities(ifp, 0); 586 } 587 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC, 0); 588 if_setcapenable(ifp, if_getcapabilities(ifp)); 589 590 /* 591 * Read some important bits from the PhyCtrl register. 592 */ 593 sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) & 594 (PC_PhyDuplexPolarity | PC_PhyLnkPolarity); 595 596 /* Set up MII bus. */ 597 flags = MIIF_DOPAUSE; 598 if (sc->sc_rev >= 0x40 && sc->sc_rev <= 0x4e) 599 flags |= MIIF_MACPRIV0; 600 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, stge_mediachange, 601 stge_mediastatus, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 602 flags); 603 if (error != 0) { 604 device_printf(sc->sc_dev, "attaching PHYs failed\n"); 605 goto fail; 606 } 607 608 ether_ifattach(ifp, enaddr); 609 610 /* VLAN capability setup */ 611 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING, 0); 612 if (sc->sc_rev >= 0x0c) 613 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM, 0); 614 if_setcapenable(ifp, if_getcapabilities(ifp)); 615 #ifdef DEVICE_POLLING 616 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0); 617 #endif 618 /* 619 * Tell the upper layer(s) we support long frames. 620 * Must appear after the call to ether_ifattach() because 621 * ether_ifattach() sets ifi_hdrlen to the default value. 622 */ 623 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 624 625 /* 626 * The manual recommends disabling early transmit, so we 627 * do. It's disabled anyway, if using IP checksumming, 628 * since the entire packet must be in the FIFO in order 629 * for the chip to perform the checksum. 630 */ 631 sc->sc_txthresh = 0x0fff; 632 633 /* 634 * Disable MWI if the PCI layer tells us to. 635 */ 636 sc->sc_DMACtrl = 0; 637 if ((cmd & PCIM_CMD_MWRICEN) == 0) 638 sc->sc_DMACtrl |= DMAC_MWIDisable; 639 640 /* 641 * Hookup IRQ 642 */ 643 error = bus_setup_intr(dev, sc->sc_res[1], INTR_TYPE_NET | INTR_MPSAFE, 644 NULL, stge_intr, sc, &sc->sc_ih); 645 if (error != 0) { 646 ether_ifdetach(ifp); 647 device_printf(sc->sc_dev, "couldn't set up IRQ\n"); 648 sc->sc_ifp = NULL; 649 goto fail; 650 } 651 652 fail: 653 if (error != 0) 654 stge_detach(dev); 655 656 return (error); 657 } 658 659 static int 660 stge_detach(device_t dev) 661 { 662 struct stge_softc *sc; 663 if_t ifp; 664 665 sc = device_get_softc(dev); 666 667 ifp = sc->sc_ifp; 668 #ifdef DEVICE_POLLING 669 if (ifp && if_getcapenable(ifp) & IFCAP_POLLING) 670 ether_poll_deregister(ifp); 671 #endif 672 if (device_is_attached(dev)) { 673 STGE_LOCK(sc); 674 /* XXX */ 675 sc->sc_detach = 1; 676 stge_stop(sc); 677 STGE_UNLOCK(sc); 678 callout_drain(&sc->sc_tick_ch); 679 taskqueue_drain(taskqueue_swi, &sc->sc_link_task); 680 ether_ifdetach(ifp); 681 } 682 683 if (sc->sc_miibus != NULL) { 684 device_delete_child(dev, sc->sc_miibus); 685 sc->sc_miibus = NULL; 686 } 687 bus_generic_detach(dev); 688 stge_dma_free(sc); 689 690 if (ifp != NULL) { 691 if_free(ifp); 692 sc->sc_ifp = NULL; 693 } 694 695 if (sc->sc_ih) { 696 bus_teardown_intr(dev, sc->sc_res[1], sc->sc_ih); 697 sc->sc_ih = NULL; 698 } 699 700 if (sc->sc_spec) 701 bus_release_resources(dev, sc->sc_spec, sc->sc_res); 702 703 mtx_destroy(&sc->sc_mii_mtx); 704 mtx_destroy(&sc->sc_mtx); 705 706 return (0); 707 } 708 709 struct stge_dmamap_arg { 710 bus_addr_t stge_busaddr; 711 }; 712 713 static void 714 stge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 715 { 716 struct stge_dmamap_arg *ctx; 717 718 if (error != 0) 719 return; 720 721 ctx = (struct stge_dmamap_arg *)arg; 722 ctx->stge_busaddr = segs[0].ds_addr; 723 } 724 725 static int 726 stge_dma_alloc(struct stge_softc *sc) 727 { 728 struct stge_dmamap_arg ctx; 729 struct stge_txdesc *txd; 730 struct stge_rxdesc *rxd; 731 int error, i; 732 733 /* create parent tag. */ 734 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev),/* parent */ 735 1, 0, /* algnmnt, boundary */ 736 STGE_DMA_MAXADDR, /* lowaddr */ 737 BUS_SPACE_MAXADDR, /* highaddr */ 738 NULL, NULL, /* filter, filterarg */ 739 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 740 0, /* nsegments */ 741 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 742 0, /* flags */ 743 NULL, NULL, /* lockfunc, lockarg */ 744 &sc->sc_cdata.stge_parent_tag); 745 if (error != 0) { 746 device_printf(sc->sc_dev, "failed to create parent DMA tag\n"); 747 goto fail; 748 } 749 /* create tag for Tx ring. */ 750 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */ 751 STGE_RING_ALIGN, 0, /* algnmnt, boundary */ 752 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 753 BUS_SPACE_MAXADDR, /* highaddr */ 754 NULL, NULL, /* filter, filterarg */ 755 STGE_TX_RING_SZ, /* maxsize */ 756 1, /* nsegments */ 757 STGE_TX_RING_SZ, /* maxsegsize */ 758 0, /* flags */ 759 NULL, NULL, /* lockfunc, lockarg */ 760 &sc->sc_cdata.stge_tx_ring_tag); 761 if (error != 0) { 762 device_printf(sc->sc_dev, 763 "failed to allocate Tx ring DMA tag\n"); 764 goto fail; 765 } 766 767 /* create tag for Rx ring. */ 768 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */ 769 STGE_RING_ALIGN, 0, /* algnmnt, boundary */ 770 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 771 BUS_SPACE_MAXADDR, /* highaddr */ 772 NULL, NULL, /* filter, filterarg */ 773 STGE_RX_RING_SZ, /* maxsize */ 774 1, /* nsegments */ 775 STGE_RX_RING_SZ, /* maxsegsize */ 776 0, /* flags */ 777 NULL, NULL, /* lockfunc, lockarg */ 778 &sc->sc_cdata.stge_rx_ring_tag); 779 if (error != 0) { 780 device_printf(sc->sc_dev, 781 "failed to allocate Rx ring DMA tag\n"); 782 goto fail; 783 } 784 785 /* create tag for Tx buffers. */ 786 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */ 787 1, 0, /* algnmnt, boundary */ 788 BUS_SPACE_MAXADDR, /* lowaddr */ 789 BUS_SPACE_MAXADDR, /* highaddr */ 790 NULL, NULL, /* filter, filterarg */ 791 MCLBYTES * STGE_MAXTXSEGS, /* maxsize */ 792 STGE_MAXTXSEGS, /* nsegments */ 793 MCLBYTES, /* maxsegsize */ 794 0, /* flags */ 795 NULL, NULL, /* lockfunc, lockarg */ 796 &sc->sc_cdata.stge_tx_tag); 797 if (error != 0) { 798 device_printf(sc->sc_dev, "failed to allocate Tx DMA tag\n"); 799 goto fail; 800 } 801 802 /* create tag for Rx buffers. */ 803 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */ 804 1, 0, /* algnmnt, boundary */ 805 BUS_SPACE_MAXADDR, /* lowaddr */ 806 BUS_SPACE_MAXADDR, /* highaddr */ 807 NULL, NULL, /* filter, filterarg */ 808 MCLBYTES, /* maxsize */ 809 1, /* nsegments */ 810 MCLBYTES, /* maxsegsize */ 811 0, /* flags */ 812 NULL, NULL, /* lockfunc, lockarg */ 813 &sc->sc_cdata.stge_rx_tag); 814 if (error != 0) { 815 device_printf(sc->sc_dev, "failed to allocate Rx DMA tag\n"); 816 goto fail; 817 } 818 819 /* allocate DMA'able memory and load the DMA map for Tx ring. */ 820 error = bus_dmamem_alloc(sc->sc_cdata.stge_tx_ring_tag, 821 (void **)&sc->sc_rdata.stge_tx_ring, BUS_DMA_NOWAIT | 822 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->sc_cdata.stge_tx_ring_map); 823 if (error != 0) { 824 device_printf(sc->sc_dev, 825 "failed to allocate DMA'able memory for Tx ring\n"); 826 goto fail; 827 } 828 829 ctx.stge_busaddr = 0; 830 error = bus_dmamap_load(sc->sc_cdata.stge_tx_ring_tag, 831 sc->sc_cdata.stge_tx_ring_map, sc->sc_rdata.stge_tx_ring, 832 STGE_TX_RING_SZ, stge_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 833 if (error != 0 || ctx.stge_busaddr == 0) { 834 device_printf(sc->sc_dev, 835 "failed to load DMA'able memory for Tx ring\n"); 836 goto fail; 837 } 838 sc->sc_rdata.stge_tx_ring_paddr = ctx.stge_busaddr; 839 840 /* allocate DMA'able memory and load the DMA map for Rx ring. */ 841 error = bus_dmamem_alloc(sc->sc_cdata.stge_rx_ring_tag, 842 (void **)&sc->sc_rdata.stge_rx_ring, BUS_DMA_NOWAIT | 843 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->sc_cdata.stge_rx_ring_map); 844 if (error != 0) { 845 device_printf(sc->sc_dev, 846 "failed to allocate DMA'able memory for Rx ring\n"); 847 goto fail; 848 } 849 850 ctx.stge_busaddr = 0; 851 error = bus_dmamap_load(sc->sc_cdata.stge_rx_ring_tag, 852 sc->sc_cdata.stge_rx_ring_map, sc->sc_rdata.stge_rx_ring, 853 STGE_RX_RING_SZ, stge_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 854 if (error != 0 || ctx.stge_busaddr == 0) { 855 device_printf(sc->sc_dev, 856 "failed to load DMA'able memory for Rx ring\n"); 857 goto fail; 858 } 859 sc->sc_rdata.stge_rx_ring_paddr = ctx.stge_busaddr; 860 861 /* create DMA maps for Tx buffers. */ 862 for (i = 0; i < STGE_TX_RING_CNT; i++) { 863 txd = &sc->sc_cdata.stge_txdesc[i]; 864 txd->tx_m = NULL; 865 txd->tx_dmamap = 0; 866 error = bus_dmamap_create(sc->sc_cdata.stge_tx_tag, 0, 867 &txd->tx_dmamap); 868 if (error != 0) { 869 device_printf(sc->sc_dev, 870 "failed to create Tx dmamap\n"); 871 goto fail; 872 } 873 } 874 /* create DMA maps for Rx buffers. */ 875 if ((error = bus_dmamap_create(sc->sc_cdata.stge_rx_tag, 0, 876 &sc->sc_cdata.stge_rx_sparemap)) != 0) { 877 device_printf(sc->sc_dev, "failed to create spare Rx dmamap\n"); 878 goto fail; 879 } 880 for (i = 0; i < STGE_RX_RING_CNT; i++) { 881 rxd = &sc->sc_cdata.stge_rxdesc[i]; 882 rxd->rx_m = NULL; 883 rxd->rx_dmamap = 0; 884 error = bus_dmamap_create(sc->sc_cdata.stge_rx_tag, 0, 885 &rxd->rx_dmamap); 886 if (error != 0) { 887 device_printf(sc->sc_dev, 888 "failed to create Rx dmamap\n"); 889 goto fail; 890 } 891 } 892 893 fail: 894 return (error); 895 } 896 897 static void 898 stge_dma_free(struct stge_softc *sc) 899 { 900 struct stge_txdesc *txd; 901 struct stge_rxdesc *rxd; 902 int i; 903 904 /* Tx ring */ 905 if (sc->sc_cdata.stge_tx_ring_tag) { 906 if (sc->sc_rdata.stge_tx_ring_paddr) 907 bus_dmamap_unload(sc->sc_cdata.stge_tx_ring_tag, 908 sc->sc_cdata.stge_tx_ring_map); 909 if (sc->sc_rdata.stge_tx_ring) 910 bus_dmamem_free(sc->sc_cdata.stge_tx_ring_tag, 911 sc->sc_rdata.stge_tx_ring, 912 sc->sc_cdata.stge_tx_ring_map); 913 sc->sc_rdata.stge_tx_ring = NULL; 914 sc->sc_rdata.stge_tx_ring_paddr = 0; 915 bus_dma_tag_destroy(sc->sc_cdata.stge_tx_ring_tag); 916 sc->sc_cdata.stge_tx_ring_tag = NULL; 917 } 918 /* Rx ring */ 919 if (sc->sc_cdata.stge_rx_ring_tag) { 920 if (sc->sc_rdata.stge_rx_ring_paddr) 921 bus_dmamap_unload(sc->sc_cdata.stge_rx_ring_tag, 922 sc->sc_cdata.stge_rx_ring_map); 923 if (sc->sc_rdata.stge_rx_ring) 924 bus_dmamem_free(sc->sc_cdata.stge_rx_ring_tag, 925 sc->sc_rdata.stge_rx_ring, 926 sc->sc_cdata.stge_rx_ring_map); 927 sc->sc_rdata.stge_rx_ring = NULL; 928 sc->sc_rdata.stge_rx_ring_paddr = 0; 929 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_ring_tag); 930 sc->sc_cdata.stge_rx_ring_tag = NULL; 931 } 932 /* Tx buffers */ 933 if (sc->sc_cdata.stge_tx_tag) { 934 for (i = 0; i < STGE_TX_RING_CNT; i++) { 935 txd = &sc->sc_cdata.stge_txdesc[i]; 936 if (txd->tx_dmamap) { 937 bus_dmamap_destroy(sc->sc_cdata.stge_tx_tag, 938 txd->tx_dmamap); 939 txd->tx_dmamap = 0; 940 } 941 } 942 bus_dma_tag_destroy(sc->sc_cdata.stge_tx_tag); 943 sc->sc_cdata.stge_tx_tag = NULL; 944 } 945 /* Rx buffers */ 946 if (sc->sc_cdata.stge_rx_tag) { 947 for (i = 0; i < STGE_RX_RING_CNT; i++) { 948 rxd = &sc->sc_cdata.stge_rxdesc[i]; 949 if (rxd->rx_dmamap) { 950 bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag, 951 rxd->rx_dmamap); 952 rxd->rx_dmamap = 0; 953 } 954 } 955 if (sc->sc_cdata.stge_rx_sparemap) { 956 bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag, 957 sc->sc_cdata.stge_rx_sparemap); 958 sc->sc_cdata.stge_rx_sparemap = 0; 959 } 960 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_tag); 961 sc->sc_cdata.stge_rx_tag = NULL; 962 } 963 964 if (sc->sc_cdata.stge_parent_tag) { 965 bus_dma_tag_destroy(sc->sc_cdata.stge_parent_tag); 966 sc->sc_cdata.stge_parent_tag = NULL; 967 } 968 } 969 970 /* 971 * stge_shutdown: 972 * 973 * Make sure the interface is stopped at reboot time. 974 */ 975 static int 976 stge_shutdown(device_t dev) 977 { 978 979 return (stge_suspend(dev)); 980 } 981 982 static void 983 stge_setwol(struct stge_softc *sc) 984 { 985 if_t ifp; 986 uint8_t v; 987 988 STGE_LOCK_ASSERT(sc); 989 990 ifp = sc->sc_ifp; 991 v = CSR_READ_1(sc, STGE_WakeEvent); 992 /* Disable all WOL bits. */ 993 v &= ~(WE_WakePktEnable | WE_MagicPktEnable | WE_LinkEventEnable | 994 WE_WakeOnLanEnable); 995 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 996 v |= WE_MagicPktEnable | WE_WakeOnLanEnable; 997 CSR_WRITE_1(sc, STGE_WakeEvent, v); 998 /* Reset Tx and prevent transmission. */ 999 CSR_WRITE_4(sc, STGE_AsicCtrl, 1000 CSR_READ_4(sc, STGE_AsicCtrl) | AC_TxReset); 1001 /* 1002 * TC9021 automatically reset link speed to 100Mbps when it's put 1003 * into sleep so there is no need to try to resetting link speed. 1004 */ 1005 } 1006 1007 static int 1008 stge_suspend(device_t dev) 1009 { 1010 struct stge_softc *sc; 1011 1012 sc = device_get_softc(dev); 1013 1014 STGE_LOCK(sc); 1015 stge_stop(sc); 1016 sc->sc_suspended = 1; 1017 stge_setwol(sc); 1018 STGE_UNLOCK(sc); 1019 1020 return (0); 1021 } 1022 1023 static int 1024 stge_resume(device_t dev) 1025 { 1026 struct stge_softc *sc; 1027 if_t ifp; 1028 uint8_t v; 1029 1030 sc = device_get_softc(dev); 1031 1032 STGE_LOCK(sc); 1033 /* 1034 * Clear WOL bits, so special frames wouldn't interfere 1035 * normal Rx operation anymore. 1036 */ 1037 v = CSR_READ_1(sc, STGE_WakeEvent); 1038 v &= ~(WE_WakePktEnable | WE_MagicPktEnable | WE_LinkEventEnable | 1039 WE_WakeOnLanEnable); 1040 CSR_WRITE_1(sc, STGE_WakeEvent, v); 1041 ifp = sc->sc_ifp; 1042 if (if_getflags(ifp) & IFF_UP) 1043 stge_init_locked(sc); 1044 1045 sc->sc_suspended = 0; 1046 STGE_UNLOCK(sc); 1047 1048 return (0); 1049 } 1050 1051 static void 1052 stge_dma_wait(struct stge_softc *sc) 1053 { 1054 int i; 1055 1056 for (i = 0; i < STGE_TIMEOUT; i++) { 1057 DELAY(2); 1058 if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0) 1059 break; 1060 } 1061 1062 if (i == STGE_TIMEOUT) 1063 device_printf(sc->sc_dev, "DMA wait timed out\n"); 1064 } 1065 1066 static int 1067 stge_encap(struct stge_softc *sc, struct mbuf **m_head) 1068 { 1069 struct stge_txdesc *txd; 1070 struct stge_tfd *tfd; 1071 struct mbuf *m; 1072 bus_dma_segment_t txsegs[STGE_MAXTXSEGS]; 1073 int error, i, nsegs, si; 1074 uint64_t csum_flags, tfc; 1075 1076 STGE_LOCK_ASSERT(sc); 1077 1078 if ((txd = STAILQ_FIRST(&sc->sc_cdata.stge_txfreeq)) == NULL) 1079 return (ENOBUFS); 1080 1081 error = bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_tx_tag, 1082 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1083 if (error == EFBIG) { 1084 m = m_collapse(*m_head, M_NOWAIT, STGE_MAXTXSEGS); 1085 if (m == NULL) { 1086 m_freem(*m_head); 1087 *m_head = NULL; 1088 return (ENOMEM); 1089 } 1090 *m_head = m; 1091 error = bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_tx_tag, 1092 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1093 if (error != 0) { 1094 m_freem(*m_head); 1095 *m_head = NULL; 1096 return (error); 1097 } 1098 } else if (error != 0) 1099 return (error); 1100 if (nsegs == 0) { 1101 m_freem(*m_head); 1102 *m_head = NULL; 1103 return (EIO); 1104 } 1105 1106 m = *m_head; 1107 csum_flags = 0; 1108 if ((m->m_pkthdr.csum_flags & STGE_CSUM_FEATURES) != 0) { 1109 if (m->m_pkthdr.csum_flags & CSUM_IP) 1110 csum_flags |= TFD_IPChecksumEnable; 1111 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1112 csum_flags |= TFD_TCPChecksumEnable; 1113 else if (m->m_pkthdr.csum_flags & CSUM_UDP) 1114 csum_flags |= TFD_UDPChecksumEnable; 1115 } 1116 1117 si = sc->sc_cdata.stge_tx_prod; 1118 tfd = &sc->sc_rdata.stge_tx_ring[si]; 1119 for (i = 0; i < nsegs; i++) 1120 tfd->tfd_frags[i].frag_word0 = 1121 htole64(FRAG_ADDR(txsegs[i].ds_addr) | 1122 FRAG_LEN(txsegs[i].ds_len)); 1123 sc->sc_cdata.stge_tx_cnt++; 1124 1125 tfc = TFD_FrameId(si) | TFD_WordAlign(TFD_WordAlign_disable) | 1126 TFD_FragCount(nsegs) | csum_flags; 1127 if (sc->sc_cdata.stge_tx_cnt >= STGE_TX_HIWAT) 1128 tfc |= TFD_TxDMAIndicate; 1129 1130 /* Update producer index. */ 1131 sc->sc_cdata.stge_tx_prod = (si + 1) % STGE_TX_RING_CNT; 1132 1133 /* Check if we have a VLAN tag to insert. */ 1134 if (m->m_flags & M_VLANTAG) 1135 tfc |= (TFD_VLANTagInsert | TFD_VID(m->m_pkthdr.ether_vtag)); 1136 tfd->tfd_control = htole64(tfc); 1137 1138 /* Update Tx Queue. */ 1139 STAILQ_REMOVE_HEAD(&sc->sc_cdata.stge_txfreeq, tx_q); 1140 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txbusyq, txd, tx_q); 1141 txd->tx_m = m; 1142 1143 /* Sync descriptors. */ 1144 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap, 1145 BUS_DMASYNC_PREWRITE); 1146 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag, 1147 sc->sc_cdata.stge_tx_ring_map, 1148 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1149 1150 return (0); 1151 } 1152 1153 /* 1154 * stge_start: [ifnet interface function] 1155 * 1156 * Start packet transmission on the interface. 1157 */ 1158 static void 1159 stge_start(if_t ifp) 1160 { 1161 struct stge_softc *sc; 1162 1163 sc = if_getsoftc(ifp); 1164 STGE_LOCK(sc); 1165 stge_start_locked(ifp); 1166 STGE_UNLOCK(sc); 1167 } 1168 1169 static void 1170 stge_start_locked(if_t ifp) 1171 { 1172 struct stge_softc *sc; 1173 struct mbuf *m_head; 1174 int enq; 1175 1176 sc = if_getsoftc(ifp); 1177 1178 STGE_LOCK_ASSERT(sc); 1179 1180 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) != 1181 IFF_DRV_RUNNING || sc->sc_link == 0) 1182 return; 1183 1184 for (enq = 0; !if_sendq_empty(ifp); ) { 1185 if (sc->sc_cdata.stge_tx_cnt >= STGE_TX_HIWAT) { 1186 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1187 break; 1188 } 1189 1190 m_head = if_dequeue(ifp); 1191 if (m_head == NULL) 1192 break; 1193 /* 1194 * Pack the data into the transmit ring. If we 1195 * don't have room, set the OACTIVE flag and wait 1196 * for the NIC to drain the ring. 1197 */ 1198 if (stge_encap(sc, &m_head)) { 1199 if (m_head == NULL) 1200 break; 1201 if_sendq_prepend(ifp, m_head); 1202 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1203 break; 1204 } 1205 1206 enq++; 1207 /* 1208 * If there's a BPF listener, bounce a copy of this frame 1209 * to him. 1210 */ 1211 ETHER_BPF_MTAP(ifp, m_head); 1212 } 1213 1214 if (enq > 0) { 1215 /* Transmit */ 1216 CSR_WRITE_4(sc, STGE_DMACtrl, DMAC_TxDMAPollNow); 1217 1218 /* Set a timeout in case the chip goes out to lunch. */ 1219 sc->sc_watchdog_timer = 5; 1220 } 1221 } 1222 1223 /* 1224 * stge_watchdog: 1225 * 1226 * Watchdog timer handler. 1227 */ 1228 static void 1229 stge_watchdog(struct stge_softc *sc) 1230 { 1231 if_t ifp; 1232 1233 STGE_LOCK_ASSERT(sc); 1234 1235 if (sc->sc_watchdog_timer == 0 || --sc->sc_watchdog_timer) 1236 return; 1237 1238 ifp = sc->sc_ifp; 1239 if_printf(sc->sc_ifp, "device timeout\n"); 1240 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1241 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1242 stge_init_locked(sc); 1243 if (!if_sendq_empty(ifp)) 1244 stge_start_locked(ifp); 1245 } 1246 1247 /* 1248 * stge_ioctl: [ifnet interface function] 1249 * 1250 * Handle control requests from the operator. 1251 */ 1252 static int 1253 stge_ioctl(if_t ifp, u_long cmd, caddr_t data) 1254 { 1255 struct stge_softc *sc; 1256 struct ifreq *ifr; 1257 struct mii_data *mii; 1258 int error, mask; 1259 1260 sc = if_getsoftc(ifp); 1261 ifr = (struct ifreq *)data; 1262 error = 0; 1263 switch (cmd) { 1264 case SIOCSIFMTU: 1265 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > STGE_JUMBO_MTU) 1266 error = EINVAL; 1267 else if (if_getmtu(ifp) != ifr->ifr_mtu) { 1268 if_setmtu(ifp, ifr->ifr_mtu); 1269 STGE_LOCK(sc); 1270 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1271 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1272 stge_init_locked(sc); 1273 } 1274 STGE_UNLOCK(sc); 1275 } 1276 break; 1277 case SIOCSIFFLAGS: 1278 STGE_LOCK(sc); 1279 if ((if_getflags(ifp) & IFF_UP) != 0) { 1280 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1281 if (((if_getflags(ifp) ^ sc->sc_if_flags) 1282 & IFF_PROMISC) != 0) 1283 stge_set_filter(sc); 1284 } else { 1285 if (sc->sc_detach == 0) 1286 stge_init_locked(sc); 1287 } 1288 } else { 1289 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1290 stge_stop(sc); 1291 } 1292 sc->sc_if_flags = if_getflags(ifp); 1293 STGE_UNLOCK(sc); 1294 break; 1295 case SIOCADDMULTI: 1296 case SIOCDELMULTI: 1297 STGE_LOCK(sc); 1298 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1299 stge_set_multi(sc); 1300 STGE_UNLOCK(sc); 1301 break; 1302 case SIOCSIFMEDIA: 1303 case SIOCGIFMEDIA: 1304 mii = device_get_softc(sc->sc_miibus); 1305 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1306 break; 1307 case SIOCSIFCAP: 1308 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 1309 #ifdef DEVICE_POLLING 1310 if ((mask & IFCAP_POLLING) != 0) { 1311 if ((ifr->ifr_reqcap & IFCAP_POLLING) != 0) { 1312 error = ether_poll_register(stge_poll, ifp); 1313 if (error != 0) 1314 break; 1315 STGE_LOCK(sc); 1316 CSR_WRITE_2(sc, STGE_IntEnable, 0); 1317 if_setcapenablebit(ifp, IFCAP_POLLING, 0); 1318 STGE_UNLOCK(sc); 1319 } else { 1320 error = ether_poll_deregister(ifp); 1321 if (error != 0) 1322 break; 1323 STGE_LOCK(sc); 1324 CSR_WRITE_2(sc, STGE_IntEnable, 1325 sc->sc_IntEnable); 1326 if_setcapenablebit(ifp, 0, IFCAP_POLLING); 1327 STGE_UNLOCK(sc); 1328 } 1329 } 1330 #endif 1331 if ((mask & IFCAP_HWCSUM) != 0) { 1332 if_togglecapenable(ifp, IFCAP_HWCSUM); 1333 if ((IFCAP_HWCSUM & if_getcapenable(ifp)) != 0 && 1334 (IFCAP_HWCSUM & if_getcapabilities(ifp)) != 0) 1335 if_sethwassist(ifp, STGE_CSUM_FEATURES); 1336 else 1337 if_sethwassist(ifp, 0); 1338 } 1339 if ((mask & IFCAP_WOL) != 0 && 1340 (if_getcapabilities(ifp) & IFCAP_WOL) != 0) { 1341 if ((mask & IFCAP_WOL_MAGIC) != 0) 1342 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 1343 } 1344 if ((mask & IFCAP_VLAN_HWTAGGING) != 0) { 1345 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 1346 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1347 STGE_LOCK(sc); 1348 stge_vlan_setup(sc); 1349 STGE_UNLOCK(sc); 1350 } 1351 } 1352 VLAN_CAPABILITIES(ifp); 1353 break; 1354 default: 1355 error = ether_ioctl(ifp, cmd, data); 1356 break; 1357 } 1358 1359 return (error); 1360 } 1361 1362 static void 1363 stge_link_task(void *arg, int pending) 1364 { 1365 struct stge_softc *sc; 1366 struct mii_data *mii; 1367 uint32_t v, ac; 1368 int i; 1369 1370 sc = (struct stge_softc *)arg; 1371 STGE_LOCK(sc); 1372 1373 mii = device_get_softc(sc->sc_miibus); 1374 if (mii->mii_media_status & IFM_ACTIVE) { 1375 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1376 sc->sc_link = 1; 1377 } else 1378 sc->sc_link = 0; 1379 1380 sc->sc_MACCtrl = 0; 1381 if (((mii->mii_media_active & IFM_GMASK) & IFM_FDX) != 0) 1382 sc->sc_MACCtrl |= MC_DuplexSelect; 1383 if (((mii->mii_media_active & IFM_GMASK) & IFM_ETH_RXPAUSE) != 0) 1384 sc->sc_MACCtrl |= MC_RxFlowControlEnable; 1385 if (((mii->mii_media_active & IFM_GMASK) & IFM_ETH_TXPAUSE) != 0) 1386 sc->sc_MACCtrl |= MC_TxFlowControlEnable; 1387 /* 1388 * Update STGE_MACCtrl register depending on link status. 1389 * (duplex, flow control etc) 1390 */ 1391 v = ac = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 1392 v &= ~(MC_DuplexSelect|MC_RxFlowControlEnable|MC_TxFlowControlEnable); 1393 v |= sc->sc_MACCtrl; 1394 CSR_WRITE_4(sc, STGE_MACCtrl, v); 1395 if (((ac ^ sc->sc_MACCtrl) & MC_DuplexSelect) != 0) { 1396 /* Duplex setting changed, reset Tx/Rx functions. */ 1397 ac = CSR_READ_4(sc, STGE_AsicCtrl); 1398 ac |= AC_TxReset | AC_RxReset; 1399 CSR_WRITE_4(sc, STGE_AsicCtrl, ac); 1400 for (i = 0; i < STGE_TIMEOUT; i++) { 1401 DELAY(100); 1402 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0) 1403 break; 1404 } 1405 if (i == STGE_TIMEOUT) 1406 device_printf(sc->sc_dev, "reset failed to complete\n"); 1407 } 1408 STGE_UNLOCK(sc); 1409 } 1410 1411 static __inline int 1412 stge_tx_error(struct stge_softc *sc) 1413 { 1414 uint32_t txstat; 1415 int error; 1416 1417 for (error = 0;;) { 1418 txstat = CSR_READ_4(sc, STGE_TxStatus); 1419 if ((txstat & TS_TxComplete) == 0) 1420 break; 1421 /* Tx underrun */ 1422 if ((txstat & TS_TxUnderrun) != 0) { 1423 /* 1424 * XXX 1425 * There should be a more better way to recover 1426 * from Tx underrun instead of a full reset. 1427 */ 1428 if (sc->sc_nerr++ < STGE_MAXERR) 1429 device_printf(sc->sc_dev, "Tx underrun, " 1430 "resetting...\n"); 1431 if (sc->sc_nerr == STGE_MAXERR) 1432 device_printf(sc->sc_dev, "too many errors; " 1433 "not reporting any more\n"); 1434 error = -1; 1435 break; 1436 } 1437 /* Maximum/Late collisions, Re-enable Tx MAC. */ 1438 if ((txstat & (TS_MaxCollisions|TS_LateCollision)) != 0) 1439 CSR_WRITE_4(sc, STGE_MACCtrl, 1440 (CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK) | 1441 MC_TxEnable); 1442 } 1443 1444 return (error); 1445 } 1446 1447 /* 1448 * stge_intr: 1449 * 1450 * Interrupt service routine. 1451 */ 1452 static void 1453 stge_intr(void *arg) 1454 { 1455 struct stge_softc *sc; 1456 if_t ifp; 1457 int reinit; 1458 uint16_t status; 1459 1460 sc = (struct stge_softc *)arg; 1461 ifp = sc->sc_ifp; 1462 1463 STGE_LOCK(sc); 1464 1465 #ifdef DEVICE_POLLING 1466 if ((if_getcapenable(ifp) & IFCAP_POLLING) != 0) 1467 goto done_locked; 1468 #endif 1469 status = CSR_READ_2(sc, STGE_IntStatus); 1470 if (sc->sc_suspended || (status & IS_InterruptStatus) == 0) 1471 goto done_locked; 1472 1473 /* Disable interrupts. */ 1474 for (reinit = 0;;) { 1475 status = CSR_READ_2(sc, STGE_IntStatusAck); 1476 status &= sc->sc_IntEnable; 1477 if (status == 0) 1478 break; 1479 /* Host interface errors. */ 1480 if ((status & IS_HostError) != 0) { 1481 device_printf(sc->sc_dev, 1482 "Host interface error, resetting...\n"); 1483 reinit = 1; 1484 goto force_init; 1485 } 1486 1487 /* Receive interrupts. */ 1488 if ((status & IS_RxDMAComplete) != 0) { 1489 stge_rxeof(sc); 1490 if ((status & IS_RFDListEnd) != 0) 1491 CSR_WRITE_4(sc, STGE_DMACtrl, 1492 DMAC_RxDMAPollNow); 1493 } 1494 1495 /* Transmit interrupts. */ 1496 if ((status & (IS_TxDMAComplete | IS_TxComplete)) != 0) 1497 stge_txeof(sc); 1498 1499 /* Transmission errors.*/ 1500 if ((status & IS_TxComplete) != 0) { 1501 if ((reinit = stge_tx_error(sc)) != 0) 1502 break; 1503 } 1504 } 1505 1506 force_init: 1507 if (reinit != 0) { 1508 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1509 stge_init_locked(sc); 1510 } 1511 1512 /* Re-enable interrupts. */ 1513 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable); 1514 1515 /* Try to get more packets going. */ 1516 if (!if_sendq_empty(ifp)) 1517 stge_start_locked(ifp); 1518 1519 done_locked: 1520 STGE_UNLOCK(sc); 1521 } 1522 1523 /* 1524 * stge_txeof: 1525 * 1526 * Helper; handle transmit interrupts. 1527 */ 1528 static void 1529 stge_txeof(struct stge_softc *sc) 1530 { 1531 if_t ifp; 1532 struct stge_txdesc *txd; 1533 uint64_t control; 1534 int cons; 1535 1536 STGE_LOCK_ASSERT(sc); 1537 1538 ifp = sc->sc_ifp; 1539 1540 txd = STAILQ_FIRST(&sc->sc_cdata.stge_txbusyq); 1541 if (txd == NULL) 1542 return; 1543 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag, 1544 sc->sc_cdata.stge_tx_ring_map, BUS_DMASYNC_POSTREAD); 1545 1546 /* 1547 * Go through our Tx list and free mbufs for those 1548 * frames which have been transmitted. 1549 */ 1550 for (cons = sc->sc_cdata.stge_tx_cons;; 1551 cons = (cons + 1) % STGE_TX_RING_CNT) { 1552 if (sc->sc_cdata.stge_tx_cnt <= 0) 1553 break; 1554 control = le64toh(sc->sc_rdata.stge_tx_ring[cons].tfd_control); 1555 if ((control & TFD_TFDDone) == 0) 1556 break; 1557 sc->sc_cdata.stge_tx_cnt--; 1558 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1559 1560 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap, 1561 BUS_DMASYNC_POSTWRITE); 1562 bus_dmamap_unload(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap); 1563 1564 /* Output counter is updated with statistics register */ 1565 m_freem(txd->tx_m); 1566 txd->tx_m = NULL; 1567 STAILQ_REMOVE_HEAD(&sc->sc_cdata.stge_txbusyq, tx_q); 1568 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txfreeq, txd, tx_q); 1569 txd = STAILQ_FIRST(&sc->sc_cdata.stge_txbusyq); 1570 } 1571 sc->sc_cdata.stge_tx_cons = cons; 1572 if (sc->sc_cdata.stge_tx_cnt == 0) 1573 sc->sc_watchdog_timer = 0; 1574 1575 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag, 1576 sc->sc_cdata.stge_tx_ring_map, 1577 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1578 } 1579 1580 static __inline void 1581 stge_discard_rxbuf(struct stge_softc *sc, int idx) 1582 { 1583 struct stge_rfd *rfd; 1584 1585 rfd = &sc->sc_rdata.stge_rx_ring[idx]; 1586 rfd->rfd_status = 0; 1587 } 1588 1589 #ifndef __NO_STRICT_ALIGNMENT 1590 /* 1591 * It seems that TC9021's DMA engine has alignment restrictions in 1592 * DMA scatter operations. The first DMA segment has no address 1593 * alignment restrictins but the rest should be aligned on 4(?) bytes 1594 * boundary. Otherwise it would corrupt random memory. Since we don't 1595 * know which one is used for the first segment in advance we simply 1596 * don't align at all. 1597 * To avoid copying over an entire frame to align, we allocate a new 1598 * mbuf and copy ethernet header to the new mbuf. The new mbuf is 1599 * prepended into the existing mbuf chain. 1600 */ 1601 static __inline struct mbuf * 1602 stge_fixup_rx(struct stge_softc *sc, struct mbuf *m) 1603 { 1604 struct mbuf *n; 1605 1606 n = NULL; 1607 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 1608 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 1609 m->m_data += ETHER_HDR_LEN; 1610 n = m; 1611 } else { 1612 MGETHDR(n, M_NOWAIT, MT_DATA); 1613 if (n != NULL) { 1614 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 1615 m->m_data += ETHER_HDR_LEN; 1616 m->m_len -= ETHER_HDR_LEN; 1617 n->m_len = ETHER_HDR_LEN; 1618 M_MOVE_PKTHDR(n, m); 1619 n->m_next = m; 1620 } else 1621 m_freem(m); 1622 } 1623 1624 return (n); 1625 } 1626 #endif 1627 1628 /* 1629 * stge_rxeof: 1630 * 1631 * Helper; handle receive interrupts. 1632 */ 1633 static int 1634 stge_rxeof(struct stge_softc *sc) 1635 { 1636 if_t ifp; 1637 struct stge_rxdesc *rxd; 1638 struct mbuf *mp, *m; 1639 uint64_t status64; 1640 uint32_t status; 1641 int cons, prog, rx_npkts; 1642 1643 STGE_LOCK_ASSERT(sc); 1644 1645 rx_npkts = 0; 1646 ifp = sc->sc_ifp; 1647 1648 bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag, 1649 sc->sc_cdata.stge_rx_ring_map, BUS_DMASYNC_POSTREAD); 1650 1651 prog = 0; 1652 for (cons = sc->sc_cdata.stge_rx_cons; prog < STGE_RX_RING_CNT; 1653 prog++, cons = (cons + 1) % STGE_RX_RING_CNT) { 1654 status64 = le64toh(sc->sc_rdata.stge_rx_ring[cons].rfd_status); 1655 status = RFD_RxStatus(status64); 1656 if ((status & RFD_RFDDone) == 0) 1657 break; 1658 #ifdef DEVICE_POLLING 1659 if (if_getcapenable(ifp) & IFCAP_POLLING) { 1660 if (sc->sc_cdata.stge_rxcycles <= 0) 1661 break; 1662 sc->sc_cdata.stge_rxcycles--; 1663 } 1664 #endif 1665 prog++; 1666 rxd = &sc->sc_cdata.stge_rxdesc[cons]; 1667 mp = rxd->rx_m; 1668 1669 /* 1670 * If the packet had an error, drop it. Note we count 1671 * the error later in the periodic stats update. 1672 */ 1673 if ((status & RFD_FrameEnd) != 0 && (status & 1674 (RFD_RxFIFOOverrun | RFD_RxRuntFrame | 1675 RFD_RxAlignmentError | RFD_RxFCSError | 1676 RFD_RxLengthError)) != 0) { 1677 stge_discard_rxbuf(sc, cons); 1678 if (sc->sc_cdata.stge_rxhead != NULL) { 1679 m_freem(sc->sc_cdata.stge_rxhead); 1680 STGE_RXCHAIN_RESET(sc); 1681 } 1682 continue; 1683 } 1684 /* 1685 * Add a new receive buffer to the ring. 1686 */ 1687 if (stge_newbuf(sc, cons) != 0) { 1688 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1689 stge_discard_rxbuf(sc, cons); 1690 if (sc->sc_cdata.stge_rxhead != NULL) { 1691 m_freem(sc->sc_cdata.stge_rxhead); 1692 STGE_RXCHAIN_RESET(sc); 1693 } 1694 continue; 1695 } 1696 1697 if ((status & RFD_FrameEnd) != 0) 1698 mp->m_len = RFD_RxDMAFrameLen(status) - 1699 sc->sc_cdata.stge_rxlen; 1700 sc->sc_cdata.stge_rxlen += mp->m_len; 1701 1702 /* Chain mbufs. */ 1703 if (sc->sc_cdata.stge_rxhead == NULL) { 1704 sc->sc_cdata.stge_rxhead = mp; 1705 sc->sc_cdata.stge_rxtail = mp; 1706 } else { 1707 mp->m_flags &= ~M_PKTHDR; 1708 sc->sc_cdata.stge_rxtail->m_next = mp; 1709 sc->sc_cdata.stge_rxtail = mp; 1710 } 1711 1712 if ((status & RFD_FrameEnd) != 0) { 1713 m = sc->sc_cdata.stge_rxhead; 1714 m->m_pkthdr.rcvif = ifp; 1715 m->m_pkthdr.len = sc->sc_cdata.stge_rxlen; 1716 1717 if (m->m_pkthdr.len > sc->sc_if_framesize) { 1718 m_freem(m); 1719 STGE_RXCHAIN_RESET(sc); 1720 continue; 1721 } 1722 /* 1723 * Set the incoming checksum information for 1724 * the packet. 1725 */ 1726 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) { 1727 if ((status & RFD_IPDetected) != 0) { 1728 m->m_pkthdr.csum_flags |= 1729 CSUM_IP_CHECKED; 1730 if ((status & RFD_IPError) == 0) 1731 m->m_pkthdr.csum_flags |= 1732 CSUM_IP_VALID; 1733 } 1734 if (((status & RFD_TCPDetected) != 0 && 1735 (status & RFD_TCPError) == 0) || 1736 ((status & RFD_UDPDetected) != 0 && 1737 (status & RFD_UDPError) == 0)) { 1738 m->m_pkthdr.csum_flags |= 1739 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 1740 m->m_pkthdr.csum_data = 0xffff; 1741 } 1742 } 1743 1744 #ifndef __NO_STRICT_ALIGNMENT 1745 if (sc->sc_if_framesize > (MCLBYTES - ETHER_ALIGN)) { 1746 if ((m = stge_fixup_rx(sc, m)) == NULL) { 1747 STGE_RXCHAIN_RESET(sc); 1748 continue; 1749 } 1750 } 1751 #endif 1752 /* Check for VLAN tagged packets. */ 1753 if ((status & RFD_VLANDetected) != 0 && 1754 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 1755 m->m_pkthdr.ether_vtag = RFD_TCI(status64); 1756 m->m_flags |= M_VLANTAG; 1757 } 1758 1759 STGE_UNLOCK(sc); 1760 /* Pass it on. */ 1761 if_input(ifp, m); 1762 STGE_LOCK(sc); 1763 rx_npkts++; 1764 1765 STGE_RXCHAIN_RESET(sc); 1766 } 1767 } 1768 1769 if (prog > 0) { 1770 /* Update the consumer index. */ 1771 sc->sc_cdata.stge_rx_cons = cons; 1772 bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag, 1773 sc->sc_cdata.stge_rx_ring_map, 1774 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1775 } 1776 return (rx_npkts); 1777 } 1778 1779 #ifdef DEVICE_POLLING 1780 static int 1781 stge_poll(if_t ifp, enum poll_cmd cmd, int count) 1782 { 1783 struct stge_softc *sc; 1784 uint16_t status; 1785 int rx_npkts; 1786 1787 rx_npkts = 0; 1788 sc = if_getsoftc(ifp); 1789 STGE_LOCK(sc); 1790 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 1791 STGE_UNLOCK(sc); 1792 return (rx_npkts); 1793 } 1794 1795 sc->sc_cdata.stge_rxcycles = count; 1796 rx_npkts = stge_rxeof(sc); 1797 stge_txeof(sc); 1798 1799 if (cmd == POLL_AND_CHECK_STATUS) { 1800 status = CSR_READ_2(sc, STGE_IntStatus); 1801 status &= sc->sc_IntEnable; 1802 if (status != 0) { 1803 if ((status & IS_HostError) != 0) { 1804 device_printf(sc->sc_dev, 1805 "Host interface error, resetting...\n"); 1806 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1807 stge_init_locked(sc); 1808 } 1809 if ((status & IS_TxComplete) != 0) { 1810 if (stge_tx_error(sc) != 0) { 1811 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1812 stge_init_locked(sc); 1813 } 1814 } 1815 } 1816 } 1817 1818 if (!if_sendq_empty(ifp)) 1819 stge_start_locked(ifp); 1820 1821 STGE_UNLOCK(sc); 1822 return (rx_npkts); 1823 } 1824 #endif /* DEVICE_POLLING */ 1825 1826 /* 1827 * stge_tick: 1828 * 1829 * One second timer, used to tick the MII. 1830 */ 1831 static void 1832 stge_tick(void *arg) 1833 { 1834 struct stge_softc *sc; 1835 struct mii_data *mii; 1836 1837 sc = (struct stge_softc *)arg; 1838 1839 STGE_LOCK_ASSERT(sc); 1840 1841 mii = device_get_softc(sc->sc_miibus); 1842 mii_tick(mii); 1843 1844 /* Update statistics counters. */ 1845 stge_stats_update(sc); 1846 1847 /* 1848 * Relcaim any pending Tx descriptors to release mbufs in a 1849 * timely manner as we don't generate Tx completion interrupts 1850 * for every frame. This limits the delay to a maximum of one 1851 * second. 1852 */ 1853 if (sc->sc_cdata.stge_tx_cnt != 0) 1854 stge_txeof(sc); 1855 1856 stge_watchdog(sc); 1857 1858 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1859 } 1860 1861 /* 1862 * stge_stats_update: 1863 * 1864 * Read the TC9021 statistics counters. 1865 */ 1866 static void 1867 stge_stats_update(struct stge_softc *sc) 1868 { 1869 if_t ifp; 1870 1871 STGE_LOCK_ASSERT(sc); 1872 1873 ifp = sc->sc_ifp; 1874 1875 CSR_READ_4(sc,STGE_OctetRcvOk); 1876 1877 if_inc_counter(ifp, IFCOUNTER_IPACKETS, CSR_READ_4(sc, STGE_FramesRcvdOk)); 1878 1879 if_inc_counter(ifp, IFCOUNTER_IERRORS, CSR_READ_2(sc, STGE_FramesLostRxErrors)); 1880 1881 CSR_READ_4(sc, STGE_OctetXmtdOk); 1882 1883 if_inc_counter(ifp, IFCOUNTER_OPACKETS, CSR_READ_4(sc, STGE_FramesXmtdOk)); 1884 1885 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1886 CSR_READ_4(sc, STGE_LateCollisions) + 1887 CSR_READ_4(sc, STGE_MultiColFrames) + 1888 CSR_READ_4(sc, STGE_SingleColFrames)); 1889 1890 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1891 CSR_READ_2(sc, STGE_FramesAbortXSColls) + 1892 CSR_READ_2(sc, STGE_FramesWEXDeferal)); 1893 } 1894 1895 /* 1896 * stge_reset: 1897 * 1898 * Perform a soft reset on the TC9021. 1899 */ 1900 static void 1901 stge_reset(struct stge_softc *sc, uint32_t how) 1902 { 1903 uint32_t ac; 1904 uint8_t v; 1905 int i, dv; 1906 1907 STGE_LOCK_ASSERT(sc); 1908 1909 dv = 5000; 1910 ac = CSR_READ_4(sc, STGE_AsicCtrl); 1911 switch (how) { 1912 case STGE_RESET_TX: 1913 ac |= AC_TxReset | AC_FIFO; 1914 dv = 100; 1915 break; 1916 case STGE_RESET_RX: 1917 ac |= AC_RxReset | AC_FIFO; 1918 dv = 100; 1919 break; 1920 case STGE_RESET_FULL: 1921 default: 1922 /* 1923 * Only assert RstOut if we're fiber. We need GMII clocks 1924 * to be present in order for the reset to complete on fiber 1925 * cards. 1926 */ 1927 ac |= AC_GlobalReset | AC_RxReset | AC_TxReset | 1928 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit | 1929 (sc->sc_usefiber ? AC_RstOut : 0); 1930 break; 1931 } 1932 1933 CSR_WRITE_4(sc, STGE_AsicCtrl, ac); 1934 1935 /* Account for reset problem at 10Mbps. */ 1936 DELAY(dv); 1937 1938 for (i = 0; i < STGE_TIMEOUT; i++) { 1939 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0) 1940 break; 1941 DELAY(dv); 1942 } 1943 1944 if (i == STGE_TIMEOUT) 1945 device_printf(sc->sc_dev, "reset failed to complete\n"); 1946 1947 /* Set LED, from Linux IPG driver. */ 1948 ac = CSR_READ_4(sc, STGE_AsicCtrl); 1949 ac &= ~(AC_LEDMode | AC_LEDSpeed | AC_LEDModeBit1); 1950 if ((sc->sc_led & 0x01) != 0) 1951 ac |= AC_LEDMode; 1952 if ((sc->sc_led & 0x03) != 0) 1953 ac |= AC_LEDModeBit1; 1954 if ((sc->sc_led & 0x08) != 0) 1955 ac |= AC_LEDSpeed; 1956 CSR_WRITE_4(sc, STGE_AsicCtrl, ac); 1957 1958 /* Set PHY, from Linux IPG driver */ 1959 v = CSR_READ_1(sc, STGE_PhySet); 1960 v &= ~(PS_MemLenb9b | PS_MemLen | PS_NonCompdet); 1961 v |= ((sc->sc_led & 0x70) >> 4); 1962 CSR_WRITE_1(sc, STGE_PhySet, v); 1963 } 1964 1965 /* 1966 * stge_init: [ ifnet interface function ] 1967 * 1968 * Initialize the interface. 1969 */ 1970 static void 1971 stge_init(void *xsc) 1972 { 1973 struct stge_softc *sc; 1974 1975 sc = (struct stge_softc *)xsc; 1976 STGE_LOCK(sc); 1977 stge_init_locked(sc); 1978 STGE_UNLOCK(sc); 1979 } 1980 1981 static void 1982 stge_init_locked(struct stge_softc *sc) 1983 { 1984 if_t ifp; 1985 struct mii_data *mii; 1986 uint16_t eaddr[3]; 1987 uint32_t v; 1988 int error; 1989 1990 STGE_LOCK_ASSERT(sc); 1991 1992 ifp = sc->sc_ifp; 1993 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1994 return; 1995 mii = device_get_softc(sc->sc_miibus); 1996 1997 /* 1998 * Cancel any pending I/O. 1999 */ 2000 stge_stop(sc); 2001 2002 /* 2003 * Reset the chip to a known state. 2004 */ 2005 stge_reset(sc, STGE_RESET_FULL); 2006 2007 /* Init descriptors. */ 2008 error = stge_init_rx_ring(sc); 2009 if (error != 0) { 2010 device_printf(sc->sc_dev, 2011 "initialization failed: no memory for rx buffers\n"); 2012 stge_stop(sc); 2013 goto out; 2014 } 2015 stge_init_tx_ring(sc); 2016 2017 /* Set the station address. */ 2018 bcopy(if_getlladdr(ifp), eaddr, ETHER_ADDR_LEN); 2019 CSR_WRITE_2(sc, STGE_StationAddress0, htole16(eaddr[0])); 2020 CSR_WRITE_2(sc, STGE_StationAddress1, htole16(eaddr[1])); 2021 CSR_WRITE_2(sc, STGE_StationAddress2, htole16(eaddr[2])); 2022 2023 /* 2024 * Set the statistics masks. Disable all the RMON stats, 2025 * and disable selected stats in the non-RMON stats registers. 2026 */ 2027 CSR_WRITE_4(sc, STGE_RMONStatisticsMask, 0xffffffff); 2028 CSR_WRITE_4(sc, STGE_StatisticsMask, 2029 (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) | 2030 (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) | 2031 (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) | 2032 (1U << 21)); 2033 2034 /* Set up the receive filter. */ 2035 stge_set_filter(sc); 2036 /* Program multicast filter. */ 2037 stge_set_multi(sc); 2038 2039 /* 2040 * Give the transmit and receive ring to the chip. 2041 */ 2042 CSR_WRITE_4(sc, STGE_TFDListPtrHi, 2043 STGE_ADDR_HI(STGE_TX_RING_ADDR(sc, 0))); 2044 CSR_WRITE_4(sc, STGE_TFDListPtrLo, 2045 STGE_ADDR_LO(STGE_TX_RING_ADDR(sc, 0))); 2046 2047 CSR_WRITE_4(sc, STGE_RFDListPtrHi, 2048 STGE_ADDR_HI(STGE_RX_RING_ADDR(sc, 0))); 2049 CSR_WRITE_4(sc, STGE_RFDListPtrLo, 2050 STGE_ADDR_LO(STGE_RX_RING_ADDR(sc, 0))); 2051 2052 /* 2053 * Initialize the Tx auto-poll period. It's OK to make this number 2054 * large (255 is the max, but we use 127) -- we explicitly kick the 2055 * transmit engine when there's actually a packet. 2056 */ 2057 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127); 2058 2059 /* ..and the Rx auto-poll period. */ 2060 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1); 2061 2062 /* Initialize the Tx start threshold. */ 2063 CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh); 2064 2065 /* Rx DMA thresholds, from Linux */ 2066 CSR_WRITE_1(sc, STGE_RxDMABurstThresh, 0x30); 2067 CSR_WRITE_1(sc, STGE_RxDMAUrgentThresh, 0x30); 2068 2069 /* Rx early threhold, from Linux */ 2070 CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff); 2071 2072 /* Tx DMA thresholds, from Linux */ 2073 CSR_WRITE_1(sc, STGE_TxDMABurstThresh, 0x30); 2074 CSR_WRITE_1(sc, STGE_TxDMAUrgentThresh, 0x04); 2075 2076 /* 2077 * Initialize the Rx DMA interrupt control register. We 2078 * request an interrupt after every incoming packet, but 2079 * defer it for sc_rxint_dmawait us. When the number of 2080 * interrupts pending reaches STGE_RXINT_NFRAME, we stop 2081 * deferring the interrupt, and signal it immediately. 2082 */ 2083 CSR_WRITE_4(sc, STGE_RxDMAIntCtrl, 2084 RDIC_RxFrameCount(sc->sc_rxint_nframe) | 2085 RDIC_RxDMAWaitTime(STGE_RXINT_USECS2TICK(sc->sc_rxint_dmawait))); 2086 2087 /* 2088 * Initialize the interrupt mask. 2089 */ 2090 sc->sc_IntEnable = IS_HostError | IS_TxComplete | 2091 IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd; 2092 #ifdef DEVICE_POLLING 2093 /* Disable interrupts if we are polling. */ 2094 if ((if_getcapenable(ifp) & IFCAP_POLLING) != 0) 2095 CSR_WRITE_2(sc, STGE_IntEnable, 0); 2096 else 2097 #endif 2098 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable); 2099 2100 /* 2101 * Configure the DMA engine. 2102 * XXX Should auto-tune TxBurstLimit. 2103 */ 2104 CSR_WRITE_4(sc, STGE_DMACtrl, sc->sc_DMACtrl | DMAC_TxBurstLimit(3)); 2105 2106 /* 2107 * Send a PAUSE frame when we reach 29,696 bytes in the Rx 2108 * FIFO, and send an un-PAUSE frame when we reach 3056 bytes 2109 * in the Rx FIFO. 2110 */ 2111 CSR_WRITE_2(sc, STGE_FlowOnTresh, 29696 / 16); 2112 CSR_WRITE_2(sc, STGE_FlowOffThresh, 3056 / 16); 2113 2114 /* 2115 * Set the maximum frame size. 2116 */ 2117 sc->sc_if_framesize = if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN; 2118 CSR_WRITE_2(sc, STGE_MaxFrameSize, sc->sc_if_framesize); 2119 2120 /* 2121 * Initialize MacCtrl -- do it before setting the media, 2122 * as setting the media will actually program the register. 2123 * 2124 * Note: We have to poke the IFS value before poking 2125 * anything else. 2126 */ 2127 /* Tx/Rx MAC should be disabled before programming IFS.*/ 2128 CSR_WRITE_4(sc, STGE_MACCtrl, MC_IFSSelect(MC_IFS96bit)); 2129 2130 stge_vlan_setup(sc); 2131 2132 if (sc->sc_rev >= 6) { /* >= B.2 */ 2133 /* Multi-frag frame bug work-around. */ 2134 CSR_WRITE_2(sc, STGE_DebugCtrl, 2135 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0200); 2136 2137 /* Tx Poll Now bug work-around. */ 2138 CSR_WRITE_2(sc, STGE_DebugCtrl, 2139 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0010); 2140 /* Tx Poll Now bug work-around. */ 2141 CSR_WRITE_2(sc, STGE_DebugCtrl, 2142 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0020); 2143 } 2144 2145 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2146 v |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable; 2147 CSR_WRITE_4(sc, STGE_MACCtrl, v); 2148 /* 2149 * It seems that transmitting frames without checking the state of 2150 * Rx/Tx MAC wedge the hardware. 2151 */ 2152 stge_start_tx(sc); 2153 stge_start_rx(sc); 2154 2155 sc->sc_link = 0; 2156 /* 2157 * Set the current media. 2158 */ 2159 mii_mediachg(mii); 2160 2161 /* 2162 * Start the one second MII clock. 2163 */ 2164 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 2165 2166 /* 2167 * ...all done! 2168 */ 2169 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 2170 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2171 2172 out: 2173 if (error != 0) 2174 device_printf(sc->sc_dev, "interface not running\n"); 2175 } 2176 2177 static void 2178 stge_vlan_setup(struct stge_softc *sc) 2179 { 2180 if_t ifp; 2181 uint32_t v; 2182 2183 ifp = sc->sc_ifp; 2184 /* 2185 * The NIC always copy a VLAN tag regardless of STGE_MACCtrl 2186 * MC_AutoVLANuntagging bit. 2187 * MC_AutoVLANtagging bit selects which VLAN source to use 2188 * between STGE_VLANTag and TFC. However TFC TFD_VLANTagInsert 2189 * bit has priority over MC_AutoVLANtagging bit. So we always 2190 * use TFC instead of STGE_VLANTag register. 2191 */ 2192 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2193 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 2194 v |= MC_AutoVLANuntagging; 2195 else 2196 v &= ~MC_AutoVLANuntagging; 2197 CSR_WRITE_4(sc, STGE_MACCtrl, v); 2198 } 2199 2200 /* 2201 * Stop transmission on the interface. 2202 */ 2203 static void 2204 stge_stop(struct stge_softc *sc) 2205 { 2206 if_t ifp; 2207 struct stge_txdesc *txd; 2208 struct stge_rxdesc *rxd; 2209 uint32_t v; 2210 int i; 2211 2212 STGE_LOCK_ASSERT(sc); 2213 /* 2214 * Stop the one second clock. 2215 */ 2216 callout_stop(&sc->sc_tick_ch); 2217 sc->sc_watchdog_timer = 0; 2218 2219 /* 2220 * Disable interrupts. 2221 */ 2222 CSR_WRITE_2(sc, STGE_IntEnable, 0); 2223 2224 /* 2225 * Stop receiver, transmitter, and stats update. 2226 */ 2227 stge_stop_rx(sc); 2228 stge_stop_tx(sc); 2229 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2230 v |= MC_StatisticsDisable; 2231 CSR_WRITE_4(sc, STGE_MACCtrl, v); 2232 2233 /* 2234 * Stop the transmit and receive DMA. 2235 */ 2236 stge_dma_wait(sc); 2237 CSR_WRITE_4(sc, STGE_TFDListPtrHi, 0); 2238 CSR_WRITE_4(sc, STGE_TFDListPtrLo, 0); 2239 CSR_WRITE_4(sc, STGE_RFDListPtrHi, 0); 2240 CSR_WRITE_4(sc, STGE_RFDListPtrLo, 0); 2241 2242 /* 2243 * Free RX and TX mbufs still in the queues. 2244 */ 2245 for (i = 0; i < STGE_RX_RING_CNT; i++) { 2246 rxd = &sc->sc_cdata.stge_rxdesc[i]; 2247 if (rxd->rx_m != NULL) { 2248 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, 2249 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2250 bus_dmamap_unload(sc->sc_cdata.stge_rx_tag, 2251 rxd->rx_dmamap); 2252 m_freem(rxd->rx_m); 2253 rxd->rx_m = NULL; 2254 } 2255 } 2256 for (i = 0; i < STGE_TX_RING_CNT; i++) { 2257 txd = &sc->sc_cdata.stge_txdesc[i]; 2258 if (txd->tx_m != NULL) { 2259 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, 2260 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2261 bus_dmamap_unload(sc->sc_cdata.stge_tx_tag, 2262 txd->tx_dmamap); 2263 m_freem(txd->tx_m); 2264 txd->tx_m = NULL; 2265 } 2266 } 2267 2268 /* 2269 * Mark the interface down and cancel the watchdog timer. 2270 */ 2271 ifp = sc->sc_ifp; 2272 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 2273 sc->sc_link = 0; 2274 } 2275 2276 static void 2277 stge_start_tx(struct stge_softc *sc) 2278 { 2279 uint32_t v; 2280 int i; 2281 2282 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2283 if ((v & MC_TxEnabled) != 0) 2284 return; 2285 v |= MC_TxEnable; 2286 CSR_WRITE_4(sc, STGE_MACCtrl, v); 2287 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127); 2288 for (i = STGE_TIMEOUT; i > 0; i--) { 2289 DELAY(10); 2290 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2291 if ((v & MC_TxEnabled) != 0) 2292 break; 2293 } 2294 if (i == 0) 2295 device_printf(sc->sc_dev, "Starting Tx MAC timed out\n"); 2296 } 2297 2298 static void 2299 stge_start_rx(struct stge_softc *sc) 2300 { 2301 uint32_t v; 2302 int i; 2303 2304 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2305 if ((v & MC_RxEnabled) != 0) 2306 return; 2307 v |= MC_RxEnable; 2308 CSR_WRITE_4(sc, STGE_MACCtrl, v); 2309 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1); 2310 for (i = STGE_TIMEOUT; i > 0; i--) { 2311 DELAY(10); 2312 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2313 if ((v & MC_RxEnabled) != 0) 2314 break; 2315 } 2316 if (i == 0) 2317 device_printf(sc->sc_dev, "Starting Rx MAC timed out\n"); 2318 } 2319 2320 static void 2321 stge_stop_tx(struct stge_softc *sc) 2322 { 2323 uint32_t v; 2324 int i; 2325 2326 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2327 if ((v & MC_TxEnabled) == 0) 2328 return; 2329 v |= MC_TxDisable; 2330 CSR_WRITE_4(sc, STGE_MACCtrl, v); 2331 for (i = STGE_TIMEOUT; i > 0; i--) { 2332 DELAY(10); 2333 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2334 if ((v & MC_TxEnabled) == 0) 2335 break; 2336 } 2337 if (i == 0) 2338 device_printf(sc->sc_dev, "Stopping Tx MAC timed out\n"); 2339 } 2340 2341 static void 2342 stge_stop_rx(struct stge_softc *sc) 2343 { 2344 uint32_t v; 2345 int i; 2346 2347 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2348 if ((v & MC_RxEnabled) == 0) 2349 return; 2350 v |= MC_RxDisable; 2351 CSR_WRITE_4(sc, STGE_MACCtrl, v); 2352 for (i = STGE_TIMEOUT; i > 0; i--) { 2353 DELAY(10); 2354 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2355 if ((v & MC_RxEnabled) == 0) 2356 break; 2357 } 2358 if (i == 0) 2359 device_printf(sc->sc_dev, "Stopping Rx MAC timed out\n"); 2360 } 2361 2362 static void 2363 stge_init_tx_ring(struct stge_softc *sc) 2364 { 2365 struct stge_ring_data *rd; 2366 struct stge_txdesc *txd; 2367 bus_addr_t addr; 2368 int i; 2369 2370 STAILQ_INIT(&sc->sc_cdata.stge_txfreeq); 2371 STAILQ_INIT(&sc->sc_cdata.stge_txbusyq); 2372 2373 sc->sc_cdata.stge_tx_prod = 0; 2374 sc->sc_cdata.stge_tx_cons = 0; 2375 sc->sc_cdata.stge_tx_cnt = 0; 2376 2377 rd = &sc->sc_rdata; 2378 bzero(rd->stge_tx_ring, STGE_TX_RING_SZ); 2379 for (i = 0; i < STGE_TX_RING_CNT; i++) { 2380 if (i == (STGE_TX_RING_CNT - 1)) 2381 addr = STGE_TX_RING_ADDR(sc, 0); 2382 else 2383 addr = STGE_TX_RING_ADDR(sc, i + 1); 2384 rd->stge_tx_ring[i].tfd_next = htole64(addr); 2385 rd->stge_tx_ring[i].tfd_control = htole64(TFD_TFDDone); 2386 txd = &sc->sc_cdata.stge_txdesc[i]; 2387 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txfreeq, txd, tx_q); 2388 } 2389 2390 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag, 2391 sc->sc_cdata.stge_tx_ring_map, 2392 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2393 2394 } 2395 2396 static int 2397 stge_init_rx_ring(struct stge_softc *sc) 2398 { 2399 struct stge_ring_data *rd; 2400 bus_addr_t addr; 2401 int i; 2402 2403 sc->sc_cdata.stge_rx_cons = 0; 2404 STGE_RXCHAIN_RESET(sc); 2405 2406 rd = &sc->sc_rdata; 2407 bzero(rd->stge_rx_ring, STGE_RX_RING_SZ); 2408 for (i = 0; i < STGE_RX_RING_CNT; i++) { 2409 if (stge_newbuf(sc, i) != 0) 2410 return (ENOBUFS); 2411 if (i == (STGE_RX_RING_CNT - 1)) 2412 addr = STGE_RX_RING_ADDR(sc, 0); 2413 else 2414 addr = STGE_RX_RING_ADDR(sc, i + 1); 2415 rd->stge_rx_ring[i].rfd_next = htole64(addr); 2416 rd->stge_rx_ring[i].rfd_status = 0; 2417 } 2418 2419 bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag, 2420 sc->sc_cdata.stge_rx_ring_map, 2421 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2422 2423 return (0); 2424 } 2425 2426 /* 2427 * stge_newbuf: 2428 * 2429 * Add a receive buffer to the indicated descriptor. 2430 */ 2431 static int 2432 stge_newbuf(struct stge_softc *sc, int idx) 2433 { 2434 struct stge_rxdesc *rxd; 2435 struct stge_rfd *rfd; 2436 struct mbuf *m; 2437 bus_dma_segment_t segs[1]; 2438 bus_dmamap_t map; 2439 int nsegs; 2440 2441 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 2442 if (m == NULL) 2443 return (ENOBUFS); 2444 m->m_len = m->m_pkthdr.len = MCLBYTES; 2445 /* 2446 * The hardware requires 4bytes aligned DMA address when JUMBO 2447 * frame is used. 2448 */ 2449 if (sc->sc_if_framesize <= (MCLBYTES - ETHER_ALIGN)) 2450 m_adj(m, ETHER_ALIGN); 2451 2452 if (bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_rx_tag, 2453 sc->sc_cdata.stge_rx_sparemap, m, segs, &nsegs, 0) != 0) { 2454 m_freem(m); 2455 return (ENOBUFS); 2456 } 2457 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2458 2459 rxd = &sc->sc_cdata.stge_rxdesc[idx]; 2460 if (rxd->rx_m != NULL) { 2461 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap, 2462 BUS_DMASYNC_POSTREAD); 2463 bus_dmamap_unload(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap); 2464 } 2465 map = rxd->rx_dmamap; 2466 rxd->rx_dmamap = sc->sc_cdata.stge_rx_sparemap; 2467 sc->sc_cdata.stge_rx_sparemap = map; 2468 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap, 2469 BUS_DMASYNC_PREREAD); 2470 rxd->rx_m = m; 2471 2472 rfd = &sc->sc_rdata.stge_rx_ring[idx]; 2473 rfd->rfd_frag.frag_word0 = 2474 htole64(FRAG_ADDR(segs[0].ds_addr) | FRAG_LEN(segs[0].ds_len)); 2475 rfd->rfd_status = 0; 2476 2477 return (0); 2478 } 2479 2480 /* 2481 * stge_set_filter: 2482 * 2483 * Set up the receive filter. 2484 */ 2485 static void 2486 stge_set_filter(struct stge_softc *sc) 2487 { 2488 if_t ifp; 2489 uint16_t mode; 2490 2491 STGE_LOCK_ASSERT(sc); 2492 2493 ifp = sc->sc_ifp; 2494 2495 mode = CSR_READ_2(sc, STGE_ReceiveMode); 2496 mode |= RM_ReceiveUnicast; 2497 if ((if_getflags(ifp) & IFF_BROADCAST) != 0) 2498 mode |= RM_ReceiveBroadcast; 2499 else 2500 mode &= ~RM_ReceiveBroadcast; 2501 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 2502 mode |= RM_ReceiveAllFrames; 2503 else 2504 mode &= ~RM_ReceiveAllFrames; 2505 2506 CSR_WRITE_2(sc, STGE_ReceiveMode, mode); 2507 } 2508 2509 static u_int 2510 stge_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 2511 { 2512 uint32_t crc, *mchash = arg; 2513 2514 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 2515 /* Just want the 6 least significant bits. */ 2516 crc &= 0x3f; 2517 /* Set the corresponding bit in the hash table. */ 2518 mchash[crc >> 5] |= 1 << (crc & 0x1f); 2519 2520 return (1); 2521 } 2522 2523 static void 2524 stge_set_multi(struct stge_softc *sc) 2525 { 2526 if_t ifp; 2527 uint32_t mchash[2]; 2528 uint16_t mode; 2529 int count; 2530 2531 STGE_LOCK_ASSERT(sc); 2532 2533 ifp = sc->sc_ifp; 2534 2535 mode = CSR_READ_2(sc, STGE_ReceiveMode); 2536 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 2537 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 2538 mode |= RM_ReceiveAllFrames; 2539 else if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) 2540 mode |= RM_ReceiveMulticast; 2541 CSR_WRITE_2(sc, STGE_ReceiveMode, mode); 2542 return; 2543 } 2544 2545 /* clear existing filters. */ 2546 CSR_WRITE_4(sc, STGE_HashTable0, 0); 2547 CSR_WRITE_4(sc, STGE_HashTable1, 0); 2548 2549 /* 2550 * Set up the multicast address filter by passing all multicast 2551 * addresses through a CRC generator, and then using the low-order 2552 * 6 bits as an index into the 64 bit multicast hash table. The 2553 * high order bits select the register, while the rest of the bits 2554 * select the bit within the register. 2555 */ 2556 bzero(mchash, sizeof(mchash)); 2557 count = if_foreach_llmaddr(ifp, stge_hash_maddr, mchash); 2558 2559 mode &= ~(RM_ReceiveMulticast | RM_ReceiveAllFrames); 2560 if (count > 0) 2561 mode |= RM_ReceiveMulticastHash; 2562 else 2563 mode &= ~RM_ReceiveMulticastHash; 2564 2565 CSR_WRITE_4(sc, STGE_HashTable0, mchash[0]); 2566 CSR_WRITE_4(sc, STGE_HashTable1, mchash[1]); 2567 CSR_WRITE_2(sc, STGE_ReceiveMode, mode); 2568 } 2569 2570 static int 2571 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2572 { 2573 int error, value; 2574 2575 if (!arg1) 2576 return (EINVAL); 2577 value = *(int *)arg1; 2578 error = sysctl_handle_int(oidp, &value, 0, req); 2579 if (error || !req->newptr) 2580 return (error); 2581 if (value < low || value > high) 2582 return (EINVAL); 2583 *(int *)arg1 = value; 2584 2585 return (0); 2586 } 2587 2588 static int 2589 sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS) 2590 { 2591 return (sysctl_int_range(oidp, arg1, arg2, req, 2592 STGE_RXINT_NFRAME_MIN, STGE_RXINT_NFRAME_MAX)); 2593 } 2594 2595 static int 2596 sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS) 2597 { 2598 return (sysctl_int_range(oidp, arg1, arg2, req, 2599 STGE_RXINT_DMAWAIT_MIN, STGE_RXINT_DMAWAIT_MAX)); 2600 } 2601