160727d8bSWarner Losh /*- 2d02c2331SBill Paul * Copyright (c) 1997, 1998, 1999 3d02c2331SBill Paul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4d02c2331SBill Paul * 5d02c2331SBill Paul * Redistribution and use in source and binary forms, with or without 6d02c2331SBill Paul * modification, are permitted provided that the following conditions 7d02c2331SBill Paul * are met: 8d02c2331SBill Paul * 1. Redistributions of source code must retain the above copyright 9d02c2331SBill Paul * notice, this list of conditions and the following disclaimer. 10d02c2331SBill Paul * 2. Redistributions in binary form must reproduce the above copyright 11d02c2331SBill Paul * notice, this list of conditions and the following disclaimer in the 12d02c2331SBill Paul * documentation and/or other materials provided with the distribution. 13d02c2331SBill Paul * 3. All advertising materials mentioning features or use of this software 14d02c2331SBill Paul * must display the following acknowledgement: 15d02c2331SBill Paul * This product includes software developed by Bill Paul. 16d02c2331SBill Paul * 4. Neither the name of the author nor the names of any co-contributors 17d02c2331SBill Paul * may be used to endorse or promote products derived from this software 18d02c2331SBill Paul * without specific prior written permission. 19d02c2331SBill Paul * 20d02c2331SBill Paul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21d02c2331SBill Paul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22d02c2331SBill Paul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23d02c2331SBill Paul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24d02c2331SBill Paul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25d02c2331SBill Paul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26d02c2331SBill Paul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27d02c2331SBill Paul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28d02c2331SBill Paul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29d02c2331SBill Paul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30d02c2331SBill Paul * THE POSSIBILITY OF SUCH DAMAGE. 31d02c2331SBill Paul * 32c3aac50fSPeter Wemm * $FreeBSD$ 33d02c2331SBill Paul */ 34d02c2331SBill Paul 35d02c2331SBill Paul /* 36d02c2331SBill Paul * Tigon register offsets. These are memory mapped registers 37d02c2331SBill Paul * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 38d02c2331SBill Paul * Each register must be accessed using 32 bit operations. 39d02c2331SBill Paul * 40d02c2331SBill Paul * All reegisters are accessed through a 16K shared memory block. 41d02c2331SBill Paul * The first group of registers are actually copies of the PCI 42d02c2331SBill Paul * configuration space registers. 43d02c2331SBill Paul */ 44d02c2331SBill Paul 45d02c2331SBill Paul #define TI_PCI_ID 0x000 /* PCI device/vendor ID */ 46d02c2331SBill Paul #define TI_PCI_CMDSTAT 0x004 47d02c2331SBill Paul #define TI_PCI_CLASSCODE 0x008 48d02c2331SBill Paul #define TI_PCI_BIST 0x00C 49d02c2331SBill Paul #define TI_PCI_LOMEM 0x010 /* Shared memory base address */ 50d02c2331SBill Paul #define TI_PCI_SUBSYS 0x02C 51d02c2331SBill Paul #define TI_PCI_ROMBASE 0x030 52d02c2331SBill Paul #define TI_PCI_INT 0x03C 53d02c2331SBill Paul 54d02c2331SBill Paul #ifndef PCIM_CMD_MWIEN 55d02c2331SBill Paul #define PCIM_CMD_MWIEN 0x0010 56d02c2331SBill Paul #endif 57d02c2331SBill Paul 58d02c2331SBill Paul /* 59d02c2331SBill Paul * Alteon AceNIC PCI vendor/device ID. 60d02c2331SBill Paul */ 61d02c2331SBill Paul #define ALT_VENDORID 0x12AE 62d02c2331SBill Paul #define ALT_DEVICEID_ACENIC 0x0001 63e87631b9SBill Paul #define ALT_DEVICEID_ACENIC_COPPER 0x0002 64d02c2331SBill Paul 65d02c2331SBill Paul /* 66d02c2331SBill Paul * 3Com 3c985 PCI vendor/device ID. 67d02c2331SBill Paul */ 68d02c2331SBill Paul #define TC_VENDORID 0x10B7 69d02c2331SBill Paul #define TC_DEVICEID_3C985 0x0001 70d02c2331SBill Paul 71d02c2331SBill Paul /* 72d02c2331SBill Paul * Netgear GA620 PCI vendor/device ID. 73d02c2331SBill Paul */ 74d02c2331SBill Paul #define NG_VENDORID 0x1385 75d02c2331SBill Paul #define NG_DEVICEID_GA620 0x620A 766f069b49SBill Paul #define NG_DEVICEID_GA620T 0x630A 77d02c2331SBill Paul 78d02c2331SBill Paul /* 79d02c2331SBill Paul * SGI device/vendor ID. 80d02c2331SBill Paul */ 81d02c2331SBill Paul #define SGI_VENDORID 0x10A9 82d02c2331SBill Paul #define SGI_DEVICEID_TIGON 0x0009 83d02c2331SBill Paul 84d02c2331SBill Paul /* 85b822a5eaSBill Paul * DEC vendor ID, Farallon device ID. Apparently, Farallon used 86b822a5eaSBill Paul * the DEC vendor ID in their cards by mistake. 87b822a5eaSBill Paul */ 88b822a5eaSBill Paul #define DEC_VENDORID 0x1011 89b822a5eaSBill Paul #define DEC_DEVICEID_FARALLON_PN9000SX 0x001a 90b822a5eaSBill Paul 91b822a5eaSBill Paul /* 92d02c2331SBill Paul * Tigon configuration and control registers. 93d02c2331SBill Paul */ 94d02c2331SBill Paul #define TI_MISC_HOST_CTL 0x040 95d02c2331SBill Paul #define TI_MISC_LOCAL_CTL 0x044 96d02c2331SBill Paul #define TI_SEM_AB 0x048 /* Tigon 2 only */ 97d02c2331SBill Paul #define TI_MISC_CONF 0x050 /* Tigon 2 only */ 98d02c2331SBill Paul #define TI_TIMER_BITS 0x054 99d02c2331SBill Paul #define TI_TIMERREF 0x058 100d02c2331SBill Paul #define TI_PCI_STATE 0x05C 101d02c2331SBill Paul #define TI_MAIN_EVENT_A 0x060 102d02c2331SBill Paul #define TI_MAILBOX_EVENT_A 0x064 103d02c2331SBill Paul #define TI_WINBASE 0x068 104d02c2331SBill Paul #define TI_WINDATA 0x06C 105d02c2331SBill Paul #define TI_MAIN_EVENT_B 0x070 /* Tigon 2 only */ 106d02c2331SBill Paul #define TI_MAILBOX_EVENT_B 0x074 /* Tigon 2 only */ 107d02c2331SBill Paul #define TI_TIMERREF_B 0x078 /* Tigon 2 only */ 108d02c2331SBill Paul #define TI_SERIAL 0x07C 109d02c2331SBill Paul 110d02c2331SBill Paul /* 111d02c2331SBill Paul * Misc host control bits. 112d02c2331SBill Paul */ 113d02c2331SBill Paul #define TI_MHC_INTSTATE 0x00000001 114d02c2331SBill Paul #define TI_MHC_CLEARINT 0x00000002 115d02c2331SBill Paul #define TI_MHC_RESET 0x00000008 116d02c2331SBill Paul #define TI_MHC_BYTE_SWAP_ENB 0x00000010 117d02c2331SBill Paul #define TI_MHC_WORD_SWAP_ENB 0x00000020 118d02c2331SBill Paul #define TI_MHC_MASK_INTS 0x00000040 119d02c2331SBill Paul #define TI_MHC_CHIP_REV_MASK 0xF0000000 120d02c2331SBill Paul 121d02c2331SBill Paul #define TI_MHC_BIGENDIAN_INIT \ 122d02c2331SBill Paul (TI_MHC_BYTE_SWAP_ENB|TI_MHC_WORD_SWAP_ENB|TI_MHC_CLEARINT) 123d02c2331SBill Paul 124d02c2331SBill Paul #define TI_MHC_LITTLEENDIAN_INIT \ 125d02c2331SBill Paul (TI_MHC_WORD_SWAP_ENB|TI_MHC_CLEARINT) 126d02c2331SBill Paul 127d02c2331SBill Paul /* 128d02c2331SBill Paul * Tigon chip rev values. Rev 4 is the Tigon 1. Rev 6 is the Tigon 2. 129d02c2331SBill Paul * Rev 5 is also the Tigon 2, but is a broken version which was never 130d02c2331SBill Paul * used in any actual hardware, so we ignore it. 131d02c2331SBill Paul */ 132d02c2331SBill Paul #define TI_REV_TIGON_I 0x40000000 133d02c2331SBill Paul #define TI_REV_TIGON_II 0x60000000 134d02c2331SBill Paul 135d02c2331SBill Paul /* 136d02c2331SBill Paul * Firmware revision that we want. 137d02c2331SBill Paul */ 138d02c2331SBill Paul #define TI_FIRMWARE_MAJOR 0xc 139e87631b9SBill Paul #define TI_FIRMWARE_MINOR 0x4 14098cb733cSKenneth D. Merry #define TI_FIRMWARE_FIX 0xb 141d02c2331SBill Paul 142d02c2331SBill Paul /* 143453130d9SPedro F. Giffuni * Miscellaneous Local Control register. 144d02c2331SBill Paul */ 145d02c2331SBill Paul #define TI_MLC_EE_WRITE_ENB 0x00000010 146d02c2331SBill Paul #define TI_MLC_SRAM_BANK_SIZE 0x00000300 /* Tigon 2 only */ 147d02c2331SBill Paul #define TI_MLC_LOCALADDR_21 0x00004000 148d02c2331SBill Paul #define TI_MLC_LOCALADDR_22 0x00008000 149d02c2331SBill Paul #define TI_MLC_SBUS_WRITEERR 0x00080000 150d02c2331SBill Paul #define TI_MLC_EE_CLK 0x00100000 151d02c2331SBill Paul #define TI_MLC_EE_TXEN 0x00200000 152d02c2331SBill Paul #define TI_MLC_EE_DOUT 0x00400000 153d02c2331SBill Paul #define TI_MLC_EE_DIN 0x00800000 154d02c2331SBill Paul 1556263665fSBill Paul /* Possible memory sizes. */ 1566263665fSBill Paul #define TI_MLC_SRAM_BANK_DISA 0x00000000 1576263665fSBill Paul #define TI_MLC_SRAM_BANK_1024K 0x00000100 1586263665fSBill Paul #define TI_MLC_SRAM_BANK_512K 0x00000200 1596263665fSBill Paul #define TI_MLC_SRAM_BANK_256K 0x00000300 1606263665fSBill Paul 161d02c2331SBill Paul /* 162d02c2331SBill Paul * Offset of MAC address inside EEPROM. 163d02c2331SBill Paul */ 164d02c2331SBill Paul #define TI_EE_MAC_OFFSET 0x8c 165d02c2331SBill Paul 166d02c2331SBill Paul #define TI_DMA_ASSIST 0x11C 167d02c2331SBill Paul #define TI_CPU_STATE 0x140 168d02c2331SBill Paul #define TI_CPU_PROGRAM_COUNTER 0x144 169d02c2331SBill Paul #define TI_SRAM_ADDR 0x154 170d02c2331SBill Paul #define TI_SRAM_DATA 0x158 171d02c2331SBill Paul #define TI_GEN_0 0x180 172d02c2331SBill Paul #define TI_GEN_X 0x1FC 173d02c2331SBill Paul #define TI_MAC_TX_STATE 0x200 174d02c2331SBill Paul #define TI_MAC_RX_STATE 0x220 175d02c2331SBill Paul #define TI_CPU_CTL_B 0x240 /* Tigon 2 only */ 176d02c2331SBill Paul #define TI_CPU_PROGRAM_COUNTER_B 0x244 /* Tigon 2 only */ 177d02c2331SBill Paul #define TI_SRAM_ADDR_B 0x254 /* Tigon 2 only */ 178d02c2331SBill Paul #define TI_SRAM_DATA_B 0x258 /* Tigon 2 only */ 179d02c2331SBill Paul #define TI_GEN_B_0 0x280 /* Tigon 2 only */ 180d02c2331SBill Paul #define TI_GEN_B_X 0x2FC /* Tigon 2 only */ 181d02c2331SBill Paul 182d02c2331SBill Paul /* 183d02c2331SBill Paul * Misc config register. 184d02c2331SBill Paul */ 185d02c2331SBill Paul #define TI_MCR_SRAM_SYNCHRONOUS 0x00100000 /* Tigon 2 only */ 186d02c2331SBill Paul 187d02c2331SBill Paul /* 188d02c2331SBill Paul * PCI state register. 189d02c2331SBill Paul */ 190d02c2331SBill Paul #define TI_PCISTATE_FORCE_RESET 0x00000001 191d02c2331SBill Paul #define TI_PCISTATE_PROVIDE_LEN 0x00000002 192d02c2331SBill Paul #define TI_PCISTATE_READ_MAXDMA 0x0000001C 193d02c2331SBill Paul #define TI_PCISTATE_WRITE_MAXDMA 0x000000E0 194d02c2331SBill Paul #define TI_PCISTATE_MINDMA 0x0000FF00 195d02c2331SBill Paul #define TI_PCISTATE_FIFO_RETRY_ENB 0x00010000 196d02c2331SBill Paul #define TI_PCISTATE_USE_MEM_RD_MULT 0x00020000 197d02c2331SBill Paul #define TI_PCISTATE_NO_SWAP_READ_DMA 0x00040000 198d02c2331SBill Paul #define TI_PCISTATE_NO_SWAP_WRITE_DMA 0x00080000 199d02c2331SBill Paul #define TI_PCISTATE_66MHZ_BUS 0x00080000 /* Tigon 2 only */ 200d02c2331SBill Paul #define TI_PCISTATE_32BIT_BUS 0x00100000 /* Tigon 2 only */ 201d02c2331SBill Paul #define TI_PCISTATE_ENB_BYTE_ENABLES 0x00800000 /* Tigon 2 only */ 202d02c2331SBill Paul #define TI_PCISTATE_READ_CMD 0x0F000000 203d02c2331SBill Paul #define TI_PCISTATE_WRITE_CMD 0xF0000000 204d02c2331SBill Paul 205d02c2331SBill Paul #define TI_PCI_READMAX_4 0x04 206d02c2331SBill Paul #define TI_PCI_READMAX_16 0x08 207d02c2331SBill Paul #define TI_PCI_READMAX_32 0x0C 208d02c2331SBill Paul #define TI_PCI_READMAX_64 0x10 209d02c2331SBill Paul #define TI_PCI_READMAX_128 0x14 210d02c2331SBill Paul #define TI_PCI_READMAX_256 0x18 211d02c2331SBill Paul #define TI_PCI_READMAX_1024 0x1C 212d02c2331SBill Paul 213d02c2331SBill Paul #define TI_PCI_WRITEMAX_4 0x20 214d02c2331SBill Paul #define TI_PCI_WRITEMAX_16 0x40 215d02c2331SBill Paul #define TI_PCI_WRITEMAX_32 0x60 216d02c2331SBill Paul #define TI_PCI_WRITEMAX_64 0x80 217d02c2331SBill Paul #define TI_PCI_WRITEMAX_128 0xA0 218d02c2331SBill Paul #define TI_PCI_WRITEMAX_256 0xC0 219d02c2331SBill Paul #define TI_PCI_WRITEMAX_1024 0xE0 220d02c2331SBill Paul 221d02c2331SBill Paul #define TI_PCI_READ_CMD 0x06000000 222d02c2331SBill Paul #define TI_PCI_WRITE_CMD 0x70000000 223d02c2331SBill Paul 224d02c2331SBill Paul /* 225d02c2331SBill Paul * DMA state register. 226d02c2331SBill Paul */ 227d02c2331SBill Paul #define TI_DMASTATE_ENABLE 0x00000001 228d02c2331SBill Paul #define TI_DMASTATE_PAUSE 0x00000002 229d02c2331SBill Paul 230d02c2331SBill Paul /* 231d02c2331SBill Paul * CPU state register. 232d02c2331SBill Paul */ 233d02c2331SBill Paul #define TI_CPUSTATE_RESET 0x00000001 234d02c2331SBill Paul #define TI_CPUSTATE_STEP 0x00000002 235d02c2331SBill Paul #define TI_CPUSTATE_ROMFAIL 0x00000010 236d02c2331SBill Paul #define TI_CPUSTATE_HALT 0x00010000 237d02c2331SBill Paul /* 238d02c2331SBill Paul * MAC TX state register 239d02c2331SBill Paul */ 240d02c2331SBill Paul #define TI_TXSTATE_RESET 0x00000001 241d02c2331SBill Paul #define TI_TXSTATE_ENB 0x00000002 242d02c2331SBill Paul #define TI_TXSTATE_STOP 0x00000004 243d02c2331SBill Paul 244d02c2331SBill Paul /* 245d02c2331SBill Paul * MAC RX state register 246d02c2331SBill Paul */ 247d02c2331SBill Paul #define TI_RXSTATE_RESET 0x00000001 248d02c2331SBill Paul #define TI_RXSTATE_ENB 0x00000002 249d02c2331SBill Paul #define TI_RXSTATE_STOP 0x00000004 250d02c2331SBill Paul 251d02c2331SBill Paul /* 252d02c2331SBill Paul * Tigon 2 mailbox registers. The mailbox area consists of 256 bytes 253d02c2331SBill Paul * split into 64 bit registers. Only the lower 32 bits of each mailbox 254d02c2331SBill Paul * are used. 255d02c2331SBill Paul */ 256d02c2331SBill Paul #define TI_MB_HOSTINTR_HI 0x500 257d02c2331SBill Paul #define TI_MB_HOSTINTR_LO 0x504 258d02c2331SBill Paul #define TI_MB_HOSTINTR TI_MB_HOSTINTR_LO 259d02c2331SBill Paul #define TI_MB_CMDPROD_IDX_HI 0x508 260d02c2331SBill Paul #define TI_MB_CMDPROD_IDX_LO 0x50C 261d02c2331SBill Paul #define TI_MB_CMDPROD_IDX TI_MB_CMDPROD_IDX_LO 262d02c2331SBill Paul #define TI_MB_SENDPROD_IDX_HI 0x510 263d02c2331SBill Paul #define TI_MB_SENDPROD_IDX_LO 0x514 264d02c2331SBill Paul #define TI_MB_SENDPROD_IDX TI_MB_SENDPROD_IDX_LO 265d02c2331SBill Paul #define TI_MB_STDRXPROD_IDX_HI 0x518 /* Tigon 2 only */ 266d02c2331SBill Paul #define TI_MB_STDRXPROD_IDX_LO 0x51C /* Tigon 2 only */ 267d02c2331SBill Paul #define TI_MB_STDRXPROD_IDX TI_MB_STDRXPROD_IDX_LO 268d02c2331SBill Paul #define TI_MB_JUMBORXPROD_IDX_HI 0x520 /* Tigon 2 only */ 269d02c2331SBill Paul #define TI_MB_JUMBORXPROD_IDX_LO 0x524 /* Tigon 2 only */ 270d02c2331SBill Paul #define TI_MB_JUMBORXPROD_IDX TI_MB_JUMBORXPROD_IDX_LO 271d02c2331SBill Paul #define TI_MB_MINIRXPROD_IDX_HI 0x528 /* Tigon 2 only */ 272d02c2331SBill Paul #define TI_MB_MINIRXPROD_IDX_LO 0x52C /* Tigon 2 only */ 273d02c2331SBill Paul #define TI_MB_MINIRXPROD_IDX TI_MB_MINIRXPROD_IDX_LO 274d02c2331SBill Paul #define TI_MB_RSVD 0x530 275d02c2331SBill Paul 276d02c2331SBill Paul /* 277d02c2331SBill Paul * Tigon 2 general communication registers. These are 64 and 32 bit 278d02c2331SBill Paul * registers which are only valid after the firmware has been 279d02c2331SBill Paul * loaded and started. They actually exist in NIC memory but are 280d02c2331SBill Paul * mapped into the host memory via the shared memory region. 281d02c2331SBill Paul * 282d02c2331SBill Paul * The NIC internally maps these registers starting at address 0, 283d02c2331SBill Paul * so to determine the NIC address of any of these registers, we 284d02c2331SBill Paul * subtract 0x600 (the address of the first register). 285d02c2331SBill Paul */ 286d02c2331SBill Paul 287d02c2331SBill Paul #define TI_GCR_BASE 0x600 288d02c2331SBill Paul #define TI_GCR_MACADDR 0x600 289d02c2331SBill Paul #define TI_GCR_PAR0 0x600 290d02c2331SBill Paul #define TI_GCR_PAR1 0x604 291d02c2331SBill Paul #define TI_GCR_GENINFO_HI 0x608 292d02c2331SBill Paul #define TI_GCR_GENINFO_LO 0x60C 293d02c2331SBill Paul #define TI_GCR_MCASTADDR 0x610 /* obsolete */ 294d02c2331SBill Paul #define TI_GCR_MAR0 0x610 /* obsolete */ 295d02c2331SBill Paul #define TI_GCR_MAR1 0x614 /* obsolete */ 296d02c2331SBill Paul #define TI_GCR_OPMODE 0x618 297d02c2331SBill Paul #define TI_GCR_DMA_READCFG 0x61C 298d02c2331SBill Paul #define TI_GCR_DMA_WRITECFG 0x620 299d02c2331SBill Paul #define TI_GCR_TX_BUFFER_RATIO 0x624 300d02c2331SBill Paul #define TI_GCR_EVENTCONS_IDX 0x628 301d02c2331SBill Paul #define TI_GCR_CMDCONS_IDX 0x62C 302d02c2331SBill Paul #define TI_GCR_TUNEPARMS 0x630 303d02c2331SBill Paul #define TI_GCR_RX_COAL_TICKS 0x630 304d02c2331SBill Paul #define TI_GCR_TX_COAL_TICKS 0x634 305d02c2331SBill Paul #define TI_GCR_STAT_TICKS 0x638 306d02c2331SBill Paul #define TI_GCR_TX_MAX_COAL_BD 0x63C 307d02c2331SBill Paul #define TI_GCR_RX_MAX_COAL_BD 0x640 308d02c2331SBill Paul #define TI_GCR_NIC_TRACING 0x644 309d02c2331SBill Paul #define TI_GCR_GLINK 0x648 310d02c2331SBill Paul #define TI_GCR_LINK 0x64C 311d02c2331SBill Paul #define TI_GCR_NICTRACE_PTR 0x650 312d02c2331SBill Paul #define TI_GCR_NICTRACE_START 0x654 313d02c2331SBill Paul #define TI_GCR_NICTRACE_LEN 0x658 314d02c2331SBill Paul #define TI_GCR_IFINDEX 0x65C 315d02c2331SBill Paul #define TI_GCR_IFMTU 0x660 316d02c2331SBill Paul #define TI_GCR_MASK_INTRS 0x664 317d02c2331SBill Paul #define TI_GCR_GLINK_STAT 0x668 318d02c2331SBill Paul #define TI_GCR_LINK_STAT 0x66C 319d02c2331SBill Paul #define TI_GCR_RXRETURNCONS_IDX 0x680 320d02c2331SBill Paul #define TI_GCR_CMDRING 0x700 321d02c2331SBill Paul 322d54c9057SPyun YongHyeon #define TI_GCR_NIC_ADDR(x) (x - TI_GCR_BASE) 323d02c2331SBill Paul 324d02c2331SBill Paul /* 325d02c2331SBill Paul * Local memory window. The local memory window is a 2K shared 326d02c2331SBill Paul * memory region which can be used to access the NIC's internal 327d02c2331SBill Paul * SRAM. The window can be mapped to a given 2K region using 328d02c2331SBill Paul * the TI_WINDOW_BASE register. 329d02c2331SBill Paul */ 330d02c2331SBill Paul #define TI_WINDOW 0x800 331d02c2331SBill Paul #define TI_WINLEN 0x800 332d02c2331SBill Paul 333d02c2331SBill Paul #define TI_TICKS_PER_SEC 1000000 334d02c2331SBill Paul 335d02c2331SBill Paul /* 336d02c2331SBill Paul * Operation mode register. 337d02c2331SBill Paul */ 338d02c2331SBill Paul #define TI_OPMODE_BYTESWAP_BD 0x00000002 339d02c2331SBill Paul #define TI_OPMODE_WORDSWAP_BD 0x00000004 340453130d9SPedro F. Giffuni #define TI_OPMODE_WARN_ENB 0x00000008 /* not yet implemented */ 341d02c2331SBill Paul #define TI_OPMODE_BYTESWAP_DATA 0x00000010 342d02c2331SBill Paul #define TI_OPMODE_1_DMA_ACTIVE 0x00000040 343d02c2331SBill Paul #define TI_OPMODE_SBUS 0x00000100 344d02c2331SBill Paul #define TI_OPMODE_DONT_FRAG_JUMBO 0x00000200 345d02c2331SBill Paul #define TI_OPMODE_INCLUDE_CRC 0x00000400 346d02c2331SBill Paul #define TI_OPMODE_RX_BADFRAMES 0x00000800 347d02c2331SBill Paul #define TI_OPMODE_NO_EVENT_INTRS 0x00001000 348d02c2331SBill Paul #define TI_OPMODE_NO_TX_INTRS 0x00002000 349d02c2331SBill Paul #define TI_OPMODE_NO_RX_INTRS 0x00004000 350453130d9SPedro F. Giffuni #define TI_OPMODE_FATAL_ENB 0x40000000 /* not yet implemented */ 35198cb733cSKenneth D. Merry #define TI_OPMODE_JUMBO_HDRSPLIT 0x00008000 352d02c2331SBill Paul 353d02c2331SBill Paul /* 354d02c2331SBill Paul * DMA configuration thresholds. 355d02c2331SBill Paul */ 356d02c2331SBill Paul #define TI_DMA_STATE_THRESH_16W 0x00000100 357d02c2331SBill Paul #define TI_DMA_STATE_THRESH_8W 0x00000080 358d02c2331SBill Paul #define TI_DMA_STATE_THRESH_4W 0x00000040 359d02c2331SBill Paul #define TI_DMA_STATE_THRESH_2W 0x00000020 360d02c2331SBill Paul #define TI_DMA_STATE_THRESH_1W 0x00000010 361d02c2331SBill Paul 362d02c2331SBill Paul #define TI_DMA_STATE_FORCE_32_BIT 0x00000008 363d02c2331SBill Paul 364d02c2331SBill Paul /* 365d02c2331SBill Paul * Gigabit link status bits. 366d02c2331SBill Paul */ 367d02c2331SBill Paul #define TI_GLNK_SENSE_NO_BEG 0x00002000 368d02c2331SBill Paul #define TI_GLNK_LOOPBACK 0x00004000 369d02c2331SBill Paul #define TI_GLNK_PREF 0x00008000 370d02c2331SBill Paul #define TI_GLNK_1000MB 0x00040000 371d02c2331SBill Paul #define TI_GLNK_FULL_DUPLEX 0x00080000 372d02c2331SBill Paul #define TI_GLNK_TX_FLOWCTL_Y 0x00200000 /* Tigon 2 only */ 373d02c2331SBill Paul #define TI_GLNK_RX_FLOWCTL_Y 0x00800000 374d02c2331SBill Paul #define TI_GLNK_AUTONEGENB 0x20000000 375d02c2331SBill Paul #define TI_GLNK_ENB 0x40000000 376d02c2331SBill Paul 377d02c2331SBill Paul /* 378d02c2331SBill Paul * Link status bits. 379d02c2331SBill Paul */ 380d02c2331SBill Paul #define TI_LNK_LOOPBACK 0x00004000 381d02c2331SBill Paul #define TI_LNK_PREF 0x00008000 382d02c2331SBill Paul #define TI_LNK_10MB 0x00010000 383d02c2331SBill Paul #define TI_LNK_100MB 0x00020000 384d02c2331SBill Paul #define TI_LNK_1000MB 0x00040000 385d02c2331SBill Paul #define TI_LNK_FULL_DUPLEX 0x00080000 386d02c2331SBill Paul #define TI_LNK_HALF_DUPLEX 0x00100000 387d02c2331SBill Paul #define TI_LNK_TX_FLOWCTL_Y 0x00200000 /* Tigon 2 only */ 388d02c2331SBill Paul #define TI_LNK_RX_FLOWCTL_Y 0x00800000 389d02c2331SBill Paul #define TI_LNK_AUTONEGENB 0x20000000 390d02c2331SBill Paul #define TI_LNK_ENB 0x40000000 391d02c2331SBill Paul 392d02c2331SBill Paul /* 393d02c2331SBill Paul * Ring size constants. 394d02c2331SBill Paul */ 395d02c2331SBill Paul #define TI_EVENT_RING_CNT 256 396d02c2331SBill Paul #define TI_CMD_RING_CNT 64 397d02c2331SBill Paul #define TI_STD_RX_RING_CNT 512 398d02c2331SBill Paul #define TI_JUMBO_RX_RING_CNT 256 399d02c2331SBill Paul #define TI_MINI_RX_RING_CNT 1024 400d02c2331SBill Paul #define TI_RETURN_RING_CNT 2048 401d02c2331SBill Paul 402ff3ced12SPyun YongHyeon #define TI_MAXTXSEGS 32 403b7c2632dSPyun YongHyeon #define TI_RING_ALIGN 32 404b7c2632dSPyun YongHyeon #define TI_JUMBO_RING_ALIGN 64 4056239708bSScott Long 406d02c2331SBill Paul /* 407d02c2331SBill Paul * Possible TX ring sizes. 408d02c2331SBill Paul */ 409d02c2331SBill Paul #define TI_TX_RING_CNT_128 128 410d02c2331SBill Paul #define TI_TX_RING_BASE_128 0x3800 411d02c2331SBill Paul 412d02c2331SBill Paul #define TI_TX_RING_CNT_256 256 413d02c2331SBill Paul #define TI_TX_RING_BASE_256 0x3000 414d02c2331SBill Paul 415d02c2331SBill Paul #define TI_TX_RING_CNT_512 512 416d02c2331SBill Paul #define TI_TX_RING_BASE_512 0x2000 417d02c2331SBill Paul 418d02c2331SBill Paul #define TI_TX_RING_CNT TI_TX_RING_CNT_512 419d02c2331SBill Paul #define TI_TX_RING_BASE TI_TX_RING_BASE_512 420d02c2331SBill Paul 421d02c2331SBill Paul /* 422d02c2331SBill Paul * The Tigon can have up to 8MB of external SRAM, however the Tigon 1 423d02c2331SBill Paul * is limited to 2MB total, and in general I think most adapters have 424d02c2331SBill Paul * around 1MB. We use this value for zeroing the NIC's SRAM, so to 425d02c2331SBill Paul * be safe we use the largest possible value (zeroing memory that 426d02c2331SBill Paul * isn't there doesn't hurt anything). 427d02c2331SBill Paul */ 428d02c2331SBill Paul #define TI_MEM_MAX 0x7FFFFF 429d02c2331SBill Paul 430d02c2331SBill Paul /* 43198cb733cSKenneth D. Merry * Maximum register address on the Tigon. 43298cb733cSKenneth D. Merry */ 43398cb733cSKenneth D. Merry #define TI_REG_MAX 0x3fff 43498cb733cSKenneth D. Merry 43598cb733cSKenneth D. Merry /* 43698cb733cSKenneth D. Merry * These values were taken from Alteon's tg.h. 43798cb733cSKenneth D. Merry */ 43898cb733cSKenneth D. Merry #define TI_BEG_SRAM 0x0 /* host thinks it's here */ 43998cb733cSKenneth D. Merry #define TI_BEG_SCRATCH 0xc00000 /* beg of scratch pad area */ 44098cb733cSKenneth D. Merry #define TI_END_SRAM_II 0x800000 /* end of SRAM, for 2 MB stuffed */ 44198cb733cSKenneth D. Merry #define TI_END_SCRATCH_II 0xc04000 /* end of scratch pad CPU A (16KB) */ 44298cb733cSKenneth D. Merry #define TI_END_SCRATCH_B 0xc02000 /* end of scratch pad CPU B (8KB) */ 44398cb733cSKenneth D. Merry #define TI_BEG_SCRATCH_B_DEBUG 0xd00000 /* beg of scratch pad for ioctl */ 44498cb733cSKenneth D. Merry #define TI_END_SCRATCH_B_DEBUG 0xd02000 /* end of scratch pad for ioctl */ 44598cb733cSKenneth D. Merry #define TI_SCRATCH_DEBUG_OFF 0x100000 /* offset for ioctl usage */ 44698cb733cSKenneth D. Merry #define TI_END_SRAM_I 0x200000 /* end of SRAM, for 2 MB stuffed */ 44798cb733cSKenneth D. Merry #define TI_END_SCRATCH_I 0xc00800 /* end of scratch pad area (2KB) */ 44898cb733cSKenneth D. Merry #define TI_BEG_PROM 0x40000000 /* beg of PROM, special access */ 44998cb733cSKenneth D. Merry #define TI_BEG_FLASH 0x80000000 /* beg of EEPROM, special access */ 45098cb733cSKenneth D. Merry #define TI_END_FLASH 0x80100000 /* end of EEPROM for 1 MB stuff */ 45198cb733cSKenneth D. Merry #define TI_BEG_SER_EEPROM 0xa0000000 /* beg of Serial EEPROM (fake out) */ 45298cb733cSKenneth D. Merry #define TI_END_SER_EEPROM 0xa0002000 /* end of Serial EEPROM (fake out) */ 45398cb733cSKenneth D. Merry #define TI_BEG_REGS 0xc0000000 /* beg of register area */ 45498cb733cSKenneth D. Merry #define TI_END_REGS 0xc0000400 /* end of register area */ 45598cb733cSKenneth D. Merry #define TI_END_WRITE_REGS 0xc0000180 /* can't write GPRs currently */ 45698cb733cSKenneth D. Merry #define TI_BEG_REGS2 0xc0000200 /* beg of second writeable reg area */ 45798cb733cSKenneth D. Merry /* the EEPROM is byte addressable in a pretty odd way */ 45898cb733cSKenneth D. Merry #define EEPROM_BYTE_LOC 0xff000000 45998cb733cSKenneth D. Merry 46098cb733cSKenneth D. Merry /* 46198cb733cSKenneth D. Merry * From Alteon's tg.h. 46298cb733cSKenneth D. Merry */ 46398cb733cSKenneth D. Merry #define TI_PROCESSOR_A 0 46498cb733cSKenneth D. Merry #define TI_PROCESSOR_B 1 46598cb733cSKenneth D. Merry #define TI_CPU_A TG_PROCESSOR_A 46698cb733cSKenneth D. Merry #define TI_CPU_B TG_PROCESSOR_B 46798cb733cSKenneth D. Merry 46898cb733cSKenneth D. Merry /* 46998cb733cSKenneth D. Merry * Following macro can be used to access to any of the CPU registers 47098cb733cSKenneth D. Merry * It will adjust the address appropriately. 47198cb733cSKenneth D. Merry * Parameters: 47298cb733cSKenneth D. Merry * reg - The register to access, e.g TI_CPU_CONTROL 47398cb733cSKenneth D. Merry * cpu - cpu, i.e PROCESSOR_A or PROCESSOR_B (or TI_CPU_A or TI_CPU_B) 47498cb733cSKenneth D. Merry */ 47598cb733cSKenneth D. Merry #define CPU_REG(reg, cpu) ((reg) + (cpu) * 0x100) 47698cb733cSKenneth D. Merry 47798cb733cSKenneth D. Merry /* 478d02c2331SBill Paul * Even on the alpha, pci addresses are 32-bit quantities 479d02c2331SBill Paul */ 480d02c2331SBill Paul 481d02c2331SBill Paul typedef struct { 4825ddfea8cSPyun YongHyeon uint32_t ti_addr_hi; 4835ddfea8cSPyun YongHyeon uint32_t ti_addr_lo; 484d02c2331SBill Paul } ti_hostaddr; 4856239708bSScott Long 486d02c2331SBill Paul #define TI_HOSTADDR(x) x.ti_addr_lo 4876239708bSScott Long 4886239708bSScott Long static __inline void 4896239708bSScott Long ti_hostaddr64(ti_hostaddr *x, bus_addr_t addr) 4906239708bSScott Long { 4916239708bSScott Long uint64_t baddr; 4926239708bSScott Long 4936239708bSScott Long baddr = (uint64_t)addr; 4946239708bSScott Long x->ti_addr_lo = baddr & 0xffffffff; 4956239708bSScott Long x->ti_addr_hi = baddr >> 32; 4966239708bSScott Long } 497d02c2331SBill Paul 498d02c2331SBill Paul /* 499d02c2331SBill Paul * Ring control block structure. The rules for the max_len field 500d02c2331SBill Paul * are as follows: 501d02c2331SBill Paul * 502d02c2331SBill Paul * For the send ring, max_len indicates the number of entries in the 503d02c2331SBill Paul * ring (128, 256 or 512). 504d02c2331SBill Paul * 505d02c2331SBill Paul * For the standard receive ring, max_len indicates the threshold 506d02c2331SBill Paul * used to decide when a frame should be put in the jumbo receive ring 507d02c2331SBill Paul * instead of the standard one. 508d02c2331SBill Paul * 509d02c2331SBill Paul * For the mini ring, max_len indicates the size of the buffers in the 510d02c2331SBill Paul * ring. This is the value used to decide when a frame is small enough 511d02c2331SBill Paul * to be placed in the mini ring. 512d02c2331SBill Paul * 513d02c2331SBill Paul * For the return receive ring, max_len indicates the number of entries 514d02c2331SBill Paul * in the ring. It can be one of 2048, 1024 or 0 (which is the same as 515d02c2331SBill Paul * 2048 for backwards compatibility). The value 1024 can only be used 516d02c2331SBill Paul * if the mini ring is disabled. 517d02c2331SBill Paul */ 518d02c2331SBill Paul struct ti_rcb { 519d02c2331SBill Paul ti_hostaddr ti_hostaddr; 520d02c2331SBill Paul #if BYTE_ORDER == BIG_ENDIAN 5215ddfea8cSPyun YongHyeon uint16_t ti_max_len; 5225ddfea8cSPyun YongHyeon uint16_t ti_flags; 523d02c2331SBill Paul #else 5245ddfea8cSPyun YongHyeon uint16_t ti_flags; 5255ddfea8cSPyun YongHyeon uint16_t ti_max_len; 526d02c2331SBill Paul #endif 5275ddfea8cSPyun YongHyeon uint32_t ti_unused; 528d02c2331SBill Paul }; 529d02c2331SBill Paul 530d02c2331SBill Paul #define TI_RCB_FLAG_TCP_UDP_CKSUM 0x00000001 531d02c2331SBill Paul #define TI_RCB_FLAG_IP_CKSUM 0x00000002 532d02c2331SBill Paul #define TI_RCB_FLAG_NO_PHDR_CKSUM 0x00000008 533d02c2331SBill Paul #define TI_RCB_FLAG_VLAN_ASSIST 0x00000010 534d02c2331SBill Paul #define TI_RCB_FLAG_COAL_UPD_ONLY 0x00000020 535d02c2331SBill Paul #define TI_RCB_FLAG_HOST_RING 0x00000040 536d02c2331SBill Paul #define TI_RCB_FLAG_IEEE_SNAP_CKSUM 0x00000080 537d02c2331SBill Paul #define TI_RCB_FLAG_USE_EXT_RX_BD 0x00000100 538d02c2331SBill Paul #define TI_RCB_FLAG_RING_DISABLED 0x00000200 539d02c2331SBill Paul 540d02c2331SBill Paul struct ti_producer { 5415ddfea8cSPyun YongHyeon uint32_t ti_idx; 5425ddfea8cSPyun YongHyeon uint32_t ti_unused; 543d02c2331SBill Paul }; 544d02c2331SBill Paul 545d02c2331SBill Paul /* 546d02c2331SBill Paul * Tigon general information block. This resides in host memory 547d02c2331SBill Paul * and contains the status counters, ring control blocks and 548d02c2331SBill Paul * producer pointers. 549d02c2331SBill Paul */ 550d02c2331SBill Paul 551d02c2331SBill Paul struct ti_gib { 552d02c2331SBill Paul struct ti_stats ti_stats; 553d02c2331SBill Paul struct ti_rcb ti_ev_rcb; 554d02c2331SBill Paul struct ti_rcb ti_cmd_rcb; 555d02c2331SBill Paul struct ti_rcb ti_tx_rcb; 556d02c2331SBill Paul struct ti_rcb ti_std_rx_rcb; 557d02c2331SBill Paul struct ti_rcb ti_jumbo_rx_rcb; 558d02c2331SBill Paul struct ti_rcb ti_mini_rx_rcb; 559d02c2331SBill Paul struct ti_rcb ti_return_rcb; 560d02c2331SBill Paul ti_hostaddr ti_ev_prodidx_ptr; 561d02c2331SBill Paul ti_hostaddr ti_return_prodidx_ptr; 562d02c2331SBill Paul ti_hostaddr ti_tx_considx_ptr; 563d02c2331SBill Paul ti_hostaddr ti_refresh_stats_ptr; 564d02c2331SBill Paul }; 565d02c2331SBill Paul 566d02c2331SBill Paul /* 567d02c2331SBill Paul * Buffer descriptor structures. There are basically three types 568d02c2331SBill Paul * of structures: normal receive descriptors, extended receive 569d02c2331SBill Paul * descriptors and transmit descriptors. The extended receive 570d02c2331SBill Paul * descriptors are optionally used only for the jumbo receive ring. 571d02c2331SBill Paul */ 572d02c2331SBill Paul 573d02c2331SBill Paul struct ti_rx_desc { 574d02c2331SBill Paul ti_hostaddr ti_addr; 575d02c2331SBill Paul #if BYTE_ORDER == BIG_ENDIAN 5765ddfea8cSPyun YongHyeon uint16_t ti_idx; 5775ddfea8cSPyun YongHyeon uint16_t ti_len; 578d02c2331SBill Paul #else 5795ddfea8cSPyun YongHyeon uint16_t ti_len; 5805ddfea8cSPyun YongHyeon uint16_t ti_idx; 581d02c2331SBill Paul #endif 582d02c2331SBill Paul #if BYTE_ORDER == BIG_ENDIAN 5835ddfea8cSPyun YongHyeon uint16_t ti_type; 5845ddfea8cSPyun YongHyeon uint16_t ti_flags; 585d02c2331SBill Paul #else 5865ddfea8cSPyun YongHyeon uint16_t ti_flags; 5875ddfea8cSPyun YongHyeon uint16_t ti_type; 588d02c2331SBill Paul #endif 589d02c2331SBill Paul #if BYTE_ORDER == BIG_ENDIAN 5905ddfea8cSPyun YongHyeon uint16_t ti_ip_cksum; 5915ddfea8cSPyun YongHyeon uint16_t ti_tcp_udp_cksum; 592d02c2331SBill Paul #else 5935ddfea8cSPyun YongHyeon uint16_t ti_tcp_udp_cksum; 5945ddfea8cSPyun YongHyeon uint16_t ti_ip_cksum; 595d02c2331SBill Paul #endif 596d02c2331SBill Paul #if BYTE_ORDER == BIG_ENDIAN 5975ddfea8cSPyun YongHyeon uint16_t ti_error_flags; 5985ddfea8cSPyun YongHyeon uint16_t ti_vlan_tag; 599d02c2331SBill Paul #else 6005ddfea8cSPyun YongHyeon uint16_t ti_vlan_tag; 6015ddfea8cSPyun YongHyeon uint16_t ti_error_flags; 602d02c2331SBill Paul #endif 6035ddfea8cSPyun YongHyeon uint32_t ti_rsvd; 6045ddfea8cSPyun YongHyeon uint32_t ti_opaque; 605d02c2331SBill Paul }; 606d02c2331SBill Paul 607b7c2632dSPyun YongHyeon #define TI_STD_RX_RING_SZ (sizeof(struct ti_rx_desc) * TI_STD_RX_RING_CNT) 608b7c2632dSPyun YongHyeon #define TI_MINI_RX_RING_SZ (sizeof(struct ti_rx_desc) * TI_MINI_RX_RING_CNT) 609b7c2632dSPyun YongHyeon #define TI_RX_RETURN_RING_SZ (sizeof(struct ti_rx_desc) * TI_RETURN_RING_CNT) 610b7c2632dSPyun YongHyeon 611d02c2331SBill Paul struct ti_rx_desc_ext { 612d02c2331SBill Paul ti_hostaddr ti_addr1; 613d02c2331SBill Paul ti_hostaddr ti_addr2; 614d02c2331SBill Paul ti_hostaddr ti_addr3; 615d02c2331SBill Paul #if BYTE_ORDER == BIG_ENDIAN 6165ddfea8cSPyun YongHyeon uint16_t ti_len1; 6175ddfea8cSPyun YongHyeon uint16_t ti_len2; 618d02c2331SBill Paul #else 6195ddfea8cSPyun YongHyeon uint16_t ti_len2; 6205ddfea8cSPyun YongHyeon uint16_t ti_len1; 621d02c2331SBill Paul #endif 622d02c2331SBill Paul #if BYTE_ORDER == BIG_ENDIAN 6235ddfea8cSPyun YongHyeon uint16_t ti_len3; 6245ddfea8cSPyun YongHyeon uint16_t ti_rsvd0; 625d02c2331SBill Paul #else 6265ddfea8cSPyun YongHyeon uint16_t ti_rsvd0; 6275ddfea8cSPyun YongHyeon uint16_t ti_len3; 628d02c2331SBill Paul #endif 629d02c2331SBill Paul ti_hostaddr ti_addr0; 630d02c2331SBill Paul #if BYTE_ORDER == BIG_ENDIAN 6315ddfea8cSPyun YongHyeon uint16_t ti_idx; 6325ddfea8cSPyun YongHyeon uint16_t ti_len0; 633d02c2331SBill Paul #else 6345ddfea8cSPyun YongHyeon uint16_t ti_len0; 6355ddfea8cSPyun YongHyeon uint16_t ti_idx; 636d02c2331SBill Paul #endif 637d02c2331SBill Paul #if BYTE_ORDER == BIG_ENDIAN 6385ddfea8cSPyun YongHyeon uint16_t ti_type; 6395ddfea8cSPyun YongHyeon uint16_t ti_flags; 640d02c2331SBill Paul #else 6415ddfea8cSPyun YongHyeon uint16_t ti_flags; 6425ddfea8cSPyun YongHyeon uint16_t ti_type; 643d02c2331SBill Paul #endif 644d02c2331SBill Paul #if BYTE_ORDER == BIG_ENDIAN 6455ddfea8cSPyun YongHyeon uint16_t ti_ip_cksum; 6465ddfea8cSPyun YongHyeon uint16_t ti_tcp_udp_cksum; 647d02c2331SBill Paul #else 6485ddfea8cSPyun YongHyeon uint16_t ti_tcp_udp_cksum; 6495ddfea8cSPyun YongHyeon uint16_t ti_ip_cksum; 650d02c2331SBill Paul #endif 651d02c2331SBill Paul #if BYTE_ORDER == BIG_ENDIAN 6525ddfea8cSPyun YongHyeon uint16_t ti_error_flags; 6535ddfea8cSPyun YongHyeon uint16_t ti_vlan_tag; 654d02c2331SBill Paul #else 6555ddfea8cSPyun YongHyeon uint16_t ti_vlan_tag; 6565ddfea8cSPyun YongHyeon uint16_t ti_error_flags; 657d02c2331SBill Paul #endif 6585ddfea8cSPyun YongHyeon uint32_t ti_rsvd1; 6595ddfea8cSPyun YongHyeon uint32_t ti_opaque; 660d02c2331SBill Paul }; 661d02c2331SBill Paul 662b7c2632dSPyun YongHyeon #ifdef TI_SF_BUF_JUMBO 663b7c2632dSPyun YongHyeon #define TI_JUMBO_RX_RING_SZ \ 664b7c2632dSPyun YongHyeon (sizeof(struct ti_rx_desc_ext) * TI_JUMBO_RX_RING_CNT) 665b7c2632dSPyun YongHyeon #else 666b7c2632dSPyun YongHyeon #define TI_JUMBO_RX_RING_SZ \ 667b7c2632dSPyun YongHyeon (sizeof(struct ti_rx_desc) * TI_JUMBO_RX_RING_CNT) 668b7c2632dSPyun YongHyeon #endif 669b7c2632dSPyun YongHyeon 670d02c2331SBill Paul /* 671d02c2331SBill Paul * Transmit descriptors are, mercifully, very small. 672d02c2331SBill Paul */ 673d02c2331SBill Paul struct ti_tx_desc { 674d02c2331SBill Paul ti_hostaddr ti_addr; 675d02c2331SBill Paul #if BYTE_ORDER == BIG_ENDIAN 6765ddfea8cSPyun YongHyeon uint16_t ti_len; 6775ddfea8cSPyun YongHyeon uint16_t ti_flags; 678d02c2331SBill Paul #else 6795ddfea8cSPyun YongHyeon uint16_t ti_flags; 6805ddfea8cSPyun YongHyeon uint16_t ti_len; 681d02c2331SBill Paul #endif 682d02c2331SBill Paul #if BYTE_ORDER == BIG_ENDIAN 6835ddfea8cSPyun YongHyeon uint16_t ti_rsvd; 6845ddfea8cSPyun YongHyeon uint16_t ti_vlan_tag; 685d02c2331SBill Paul #else 6865ddfea8cSPyun YongHyeon uint16_t ti_vlan_tag; 6875ddfea8cSPyun YongHyeon uint16_t ti_rsvd; 688d02c2331SBill Paul #endif 689d02c2331SBill Paul }; 690d02c2331SBill Paul 691b7c2632dSPyun YongHyeon #define TI_TX_RING_SZ (sizeof(struct ti_tx_desc) * TI_TX_RING_CNT) 692b7c2632dSPyun YongHyeon 693d02c2331SBill Paul /* 694d02c2331SBill Paul * NOTE! On the Alpha, we have an alignment constraint. 695d02c2331SBill Paul * The first thing in the packet is a 14-byte Ethernet header. 696d02c2331SBill Paul * This means that the packet is misaligned. To compensate, 697d02c2331SBill Paul * we actually offset the data 2 bytes into the cluster. This 698ccb7a62eSJohn Baldwin * aligns the packet after the Ethernet header at a 32-bit 699d02c2331SBill Paul * boundary. 700d02c2331SBill Paul */ 701d02c2331SBill Paul 702d02c2331SBill Paul #define TI_FRAMELEN 1518 703571a80b2SBill Paul #define TI_JUMBO_FRAMELEN 9018 704d02c2331SBill Paul #define TI_JUMBO_MTU (TI_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 705d02c2331SBill Paul #define TI_PAGE_SIZE PAGE_SIZE 706d02c2331SBill Paul #define TI_MIN_FRAMELEN 60 707d02c2331SBill Paul 708d02c2331SBill Paul /* 709d02c2331SBill Paul * Buffer descriptor error flags. 710d02c2331SBill Paul */ 711d02c2331SBill Paul #define TI_BDERR_CRC 0x0001 712d02c2331SBill Paul #define TI_BDERR_COLLDETECT 0x0002 713d02c2331SBill Paul #define TI_BDERR_LINKLOST 0x0004 714d02c2331SBill Paul #define TI_BDERR_DECODE 0x0008 715d02c2331SBill Paul #define TI_BDERR_ODD_NIBBLES 0x0010 716d02c2331SBill Paul #define TI_BDERR_MAC_ABRT 0x0020 717d02c2331SBill Paul #define TI_BDERR_RUNT 0x0040 718d02c2331SBill Paul #define TI_BDERR_TRUNC 0x0080 719d02c2331SBill Paul #define TI_BDERR_GIANT 0x0100 720d02c2331SBill Paul 721d02c2331SBill Paul /* 722d02c2331SBill Paul * Buffer descriptor flags. 723d02c2331SBill Paul */ 724d02c2331SBill Paul #define TI_BDFLAG_TCP_UDP_CKSUM 0x0001 725d02c2331SBill Paul #define TI_BDFLAG_IP_CKSUM 0x0002 726d02c2331SBill Paul #define TI_BDFLAG_END 0x0004 727d02c2331SBill Paul #define TI_BDFLAG_MORE 0x0008 728d02c2331SBill Paul #define TI_BDFLAG_JUMBO_RING 0x0010 729d02c2331SBill Paul #define TI_BDFLAG_UCAST_PKT 0x0020 730d02c2331SBill Paul #define TI_BDFLAG_MCAST_PKT 0x0040 731d02c2331SBill Paul #define TI_BDFLAG_BCAST_PKT 0x0060 732d02c2331SBill Paul #define TI_BDFLAG_IP_FRAG 0x0080 733d02c2331SBill Paul #define TI_BDFLAG_IP_FRAG_END 0x0100 734d02c2331SBill Paul #define TI_BDFLAG_VLAN_TAG 0x0200 735d02c2331SBill Paul #define TI_BDFLAG_ERROR 0x0400 736d02c2331SBill Paul #define TI_BDFLAG_COAL_NOW 0x0800 737d02c2331SBill Paul #define TI_BDFLAG_MINI_RING 0x1000 738d02c2331SBill Paul 739d02c2331SBill Paul /* 740d02c2331SBill Paul * Descriptor type flags. I think these only have meaning for 741d02c2331SBill Paul * the Tigon 1. I had to extract them from the sample driver source 742d02c2331SBill Paul * since they aren't in the manual. 743d02c2331SBill Paul */ 744d02c2331SBill Paul #define TI_BDTYPE_TYPE_NULL 0x0000 745d02c2331SBill Paul #define TI_BDTYPE_SEND_BD 0x0001 746d02c2331SBill Paul #define TI_BDTYPE_RECV_BD 0x0002 747d02c2331SBill Paul #define TI_BDTYPE_RECV_JUMBO_BD 0x0003 748d02c2331SBill Paul #define TI_BDTYPE_RECV_BD_LAST 0x0004 749d02c2331SBill Paul #define TI_BDTYPE_SEND_DATA 0x0005 750d02c2331SBill Paul #define TI_BDTYPE_SEND_DATA_LAST 0x0006 751d02c2331SBill Paul #define TI_BDTYPE_RECV_DATA 0x0007 752d02c2331SBill Paul #define TI_BDTYPE_RECV_DATA_LAST 0x000b 753d02c2331SBill Paul #define TI_BDTYPE_EVENT_RUPT 0x000c 754d02c2331SBill Paul #define TI_BDTYPE_EVENT_NO_RUPT 0x000d 755d02c2331SBill Paul #define TI_BDTYPE_ODD_START 0x000e 756d02c2331SBill Paul #define TI_BDTYPE_UPDATE_STATS 0x000f 757d02c2331SBill Paul #define TI_BDTYPE_SEND_DUMMY_DMA 0x0010 758d02c2331SBill Paul #define TI_BDTYPE_EVENT_PROD 0x0011 759d02c2331SBill Paul #define TI_BDTYPE_TX_CONS 0x0012 760d02c2331SBill Paul #define TI_BDTYPE_RX_PROD 0x0013 761d02c2331SBill Paul #define TI_BDTYPE_REFRESH_STATS 0x0014 762d02c2331SBill Paul #define TI_BDTYPE_SEND_DATA_LAST_VLAN 0x0015 763d02c2331SBill Paul #define TI_BDTYPE_SEND_DATA_COAL 0x0016 764d02c2331SBill Paul #define TI_BDTYPE_SEND_DATA_LAST_COAL 0x0017 765d02c2331SBill Paul #define TI_BDTYPE_SEND_DATA_LAST_VLAN_COAL 0x0018 766d02c2331SBill Paul #define TI_BDTYPE_TX_CONS_NO_INTR 0x0019 767d02c2331SBill Paul 768d02c2331SBill Paul /* 769d02c2331SBill Paul * Tigon command structure. 770d02c2331SBill Paul */ 771d02c2331SBill Paul struct ti_cmd_desc { 7725ddfea8cSPyun YongHyeon uint32_t ti_cmdx; 773d02c2331SBill Paul }; 774d02c2331SBill Paul 775d54c9057SPyun YongHyeon #define TI_CMD_CMD(cmd) (((((cmd)->ti_cmdx)) >> 24) & 0xff) 776d54c9057SPyun YongHyeon #define TI_CMD_CODE(cmd) (((((cmd)->ti_cmdx)) >> 12) & 0xfff) 777d54c9057SPyun YongHyeon #define TI_CMD_IDX(cmd) ((((cmd)->ti_cmdx)) & 0xfff) 778d54c9057SPyun YongHyeon 779d02c2331SBill Paul #define TI_CMD_HOST_STATE 0x01 780d02c2331SBill Paul #define TI_CMD_CODE_STACK_UP 0x01 781d02c2331SBill Paul #define TI_CMD_CODE_STACK_DOWN 0x02 782d02c2331SBill Paul 783d02c2331SBill Paul /* 784d02c2331SBill Paul * This command enables software address filtering. It's a workaround 785d02c2331SBill Paul * for a bug in the Tigon 1 and not implemented for the Tigon 2. 786d02c2331SBill Paul */ 787d02c2331SBill Paul #define TI_CMD_FDR_FILTERING 0x02 788d02c2331SBill Paul #define TI_CMD_CODE_FILT_ENB 0x01 789d02c2331SBill Paul #define TI_CMD_CODE_FILT_DIS 0x02 790d02c2331SBill Paul 791d02c2331SBill Paul #define TI_CMD_SET_RX_PROD_IDX 0x03 /* obsolete */ 792d02c2331SBill Paul #define TI_CMD_UPDATE_GENCOM 0x04 793d02c2331SBill Paul #define TI_CMD_RESET_JUMBO_RING 0x05 794d02c2331SBill Paul #define TI_CMD_SET_PARTIAL_RX_CNT 0x06 795d02c2331SBill Paul #define TI_CMD_ADD_MCAST_ADDR 0x08 /* obsolete */ 796d02c2331SBill Paul #define TI_CMD_DEL_MCAST_ADDR 0x09 /* obsolete */ 797d02c2331SBill Paul 798d02c2331SBill Paul #define TI_CMD_SET_PROMISC_MODE 0x0A 799d02c2331SBill Paul #define TI_CMD_CODE_PROMISC_ENB 0x01 800d02c2331SBill Paul #define TI_CMD_CODE_PROMISC_DIS 0x02 801d02c2331SBill Paul 802d02c2331SBill Paul #define TI_CMD_LINK_NEGOTIATION 0x0B 803d02c2331SBill Paul #define TI_CMD_CODE_NEGOTIATE_BOTH 0x00 804d02c2331SBill Paul #define TI_CMD_CODE_NEGOTIATE_GIGABIT 0x01 805d02c2331SBill Paul #define TI_CMD_CODE_NEGOTIATE_10_100 0x02 806d02c2331SBill Paul 807d02c2331SBill Paul #define TI_CMD_SET_MAC_ADDR 0x0C 808d02c2331SBill Paul #define TI_CMD_CLR_PROFILE 0x0D 809d02c2331SBill Paul 810d02c2331SBill Paul #define TI_CMD_SET_ALLMULTI 0x0E 811d02c2331SBill Paul #define TI_CMD_CODE_ALLMULTI_ENB 0x01 812d02c2331SBill Paul #define TI_CMD_CODE_ALLMULTI_DIS 0x02 813d02c2331SBill Paul 814d02c2331SBill Paul #define TI_CMD_CLR_STATS 0x0F 815d02c2331SBill Paul #define TI_CMD_SET_RX_JUMBO_PROD_IDX 0x10 /* obsolete */ 816d02c2331SBill Paul #define TI_CMD_RFRSH_STATS 0x11 817d02c2331SBill Paul 818d02c2331SBill Paul #define TI_CMD_EXT_ADD_MCAST 0x12 819d02c2331SBill Paul #define TI_CMD_EXT_DEL_MCAST 0x13 820d02c2331SBill Paul 821d02c2331SBill Paul /* 822d02c2331SBill Paul * Utility macros to make issuing commands a little simpler. Assumes 823d02c2331SBill Paul * that 'sc' and 'cmd' are in local scope. 824d02c2331SBill Paul */ 825d54c9057SPyun YongHyeon #define TI_DO_CMD(x, y, z) do { \ 826d54c9057SPyun YongHyeon cmd.ti_cmdx = (((x) << 24) | ((y) << 12) | ((z))); \ 827d54c9057SPyun YongHyeon ti_cmd(sc, &cmd); \ 828d54c9057SPyun YongHyeon } while(0) 829d02c2331SBill Paul 830d54c9057SPyun YongHyeon #define TI_DO_CMD_EXT(x, y, z, v, w) do { \ 831d54c9057SPyun YongHyeon cmd.ti_cmdx = (((x) << 24) | ((y) << 12) | ((z))); \ 832d54c9057SPyun YongHyeon ti_cmd_ext(sc, &cmd, (v), (w)); \ 833d54c9057SPyun YongHyeon } while(0) 834d02c2331SBill Paul 835d02c2331SBill Paul /* 836d02c2331SBill Paul * Other utility macros. 837d02c2331SBill Paul */ 838d54c9057SPyun YongHyeon #define TI_INC(x, y) (x) = ((x) + 1) % y 839d02c2331SBill Paul 840d54c9057SPyun YongHyeon #define TI_UPDATE_JUMBOPROD(x, y) do { \ 841d54c9057SPyun YongHyeon if ((x)->ti_hwrev == TI_HWREV_TIGON) \ 842d54c9057SPyun YongHyeon TI_DO_CMD(TI_CMD_SET_RX_JUMBO_PROD_IDX, 0, (y)); \ 843d54c9057SPyun YongHyeon else \ 844d54c9057SPyun YongHyeon CSR_WRITE_4((x), TI_MB_JUMBORXPROD_IDX, (y)); \ 845d54c9057SPyun YongHyeon } while(0) 846d02c2331SBill Paul 847d02c2331SBill Paul #define TI_UPDATE_MINIPROD(x, y) \ 848d54c9057SPyun YongHyeon CSR_WRITE_4((x), TI_MB_MINIRXPROD_IDX, (y)) 849d02c2331SBill Paul 850d54c9057SPyun YongHyeon #define TI_UPDATE_STDPROD(x, y) do { \ 851d54c9057SPyun YongHyeon if ((x)->ti_hwrev == TI_HWREV_TIGON) \ 852d54c9057SPyun YongHyeon TI_DO_CMD(TI_CMD_SET_RX_PROD_IDX, 0, (y)); \ 853d54c9057SPyun YongHyeon else \ 854d54c9057SPyun YongHyeon CSR_WRITE_4((x), TI_MB_STDRXPROD_IDX, (y)); \ 855d54c9057SPyun YongHyeon } while(0) 856d02c2331SBill Paul 857d02c2331SBill Paul /* 858d02c2331SBill Paul * Tigon event structure. 859d02c2331SBill Paul */ 860d02c2331SBill Paul struct ti_event_desc { 8615ddfea8cSPyun YongHyeon uint32_t ti_eventx; 8625ddfea8cSPyun YongHyeon uint32_t ti_rsvd; 863d02c2331SBill Paul }; 864b7c2632dSPyun YongHyeon #define TI_EVENT_RING_SZ (sizeof(struct ti_event_desc) * TI_EVENT_RING_CNT) 865d02c2331SBill Paul 866d54c9057SPyun YongHyeon #define TI_EVENT_EVENT(e) (((((e)->ti_eventx)) >> 24) & 0xff) 867d54c9057SPyun YongHyeon #define TI_EVENT_CODE(e) (((((e)->ti_eventx)) >> 12) & 0xfff) 868d54c9057SPyun YongHyeon #define TI_EVENT_IDX(e) (((((e)->ti_eventx))) & 0xfff) 869d54c9057SPyun YongHyeon 870d02c2331SBill Paul /* 871d02c2331SBill Paul * Tigon events. 872d02c2331SBill Paul */ 873d02c2331SBill Paul #define TI_EV_FIRMWARE_UP 0x01 874d02c2331SBill Paul #define TI_EV_STATS_UPDATED 0x04 875d02c2331SBill Paul 876d02c2331SBill Paul #define TI_EV_LINKSTAT_CHANGED 0x06 877d02c2331SBill Paul #define TI_EV_CODE_GIG_LINK_UP 0x01 878d02c2331SBill Paul #define TI_EV_CODE_LINK_DOWN 0x02 879d02c2331SBill Paul #define TI_EV_CODE_LINK_UP 0x03 880d02c2331SBill Paul 881d02c2331SBill Paul #define TI_EV_ERROR 0x07 882d02c2331SBill Paul #define TI_EV_CODE_ERR_INVAL_CMD 0x01 883d02c2331SBill Paul #define TI_EV_CODE_ERR_UNIMP_CMD 0x02 884d02c2331SBill Paul #define TI_EV_CODE_ERR_BADCFG 0x03 885d02c2331SBill Paul 886d02c2331SBill Paul #define TI_EV_MCAST_UPDATED 0x08 887d02c2331SBill Paul #define TI_EV_CODE_MCAST_ADD 0x01 888d02c2331SBill Paul #define TI_EV_CODE_MCAST_DEL 0x02 889d02c2331SBill Paul 890d02c2331SBill Paul #define TI_EV_RESET_JUMBO_RING 0x09 891d02c2331SBill Paul /* 892d02c2331SBill Paul * Register access macros. The Tigon always uses memory mapped register 893d02c2331SBill Paul * accesses and all registers must be accessed with 32 bit operations. 894d02c2331SBill Paul */ 895d02c2331SBill Paul 896d02c2331SBill Paul #define CSR_WRITE_4(sc, reg, val) \ 897d54c9057SPyun YongHyeon bus_space_write_4((sc)->ti_btag, (sc)->ti_bhandle, (reg), (val)) 898d02c2331SBill Paul 899d02c2331SBill Paul #define CSR_READ_4(sc, reg) \ 900d54c9057SPyun YongHyeon bus_space_read_4((sc)->ti_btag, (sc)->ti_bhandle, (reg)) 901d02c2331SBill Paul 902d02c2331SBill Paul #define TI_SETBIT(sc, reg, x) \ 903d54c9057SPyun YongHyeon CSR_WRITE_4((sc), (reg), (CSR_READ_4((sc), (reg)) | (x))) 904d02c2331SBill Paul #define TI_CLRBIT(sc, reg, x) \ 905d54c9057SPyun YongHyeon CSR_WRITE_4((sc), (reg), (CSR_READ_4((sc), (reg)) & ~(x))) 906d02c2331SBill Paul 907ff3ced12SPyun YongHyeon struct ti_txdesc { 908ff3ced12SPyun YongHyeon struct mbuf *tx_m; 909ff3ced12SPyun YongHyeon bus_dmamap_t tx_dmamap; 910ff3ced12SPyun YongHyeon STAILQ_ENTRY(ti_txdesc) tx_q; 911ff3ced12SPyun YongHyeon }; 912ff3ced12SPyun YongHyeon 913ff3ced12SPyun YongHyeon STAILQ_HEAD(ti_txdq, ti_txdesc); 914ff3ced12SPyun YongHyeon 915b7c2632dSPyun YongHyeon struct ti_status { 916d02c2331SBill Paul /* 917d02c2331SBill Paul * Make sure producer structures are aligned on 32-byte cache 918b7c2632dSPyun YongHyeon * line boundaries. We can create separate DMA area for each 919b7c2632dSPyun YongHyeon * producer/consumer area but it wouldn't get much benefit 920b7c2632dSPyun YongHyeon * since driver use a global driver lock. 921d02c2331SBill Paul */ 922d02c2331SBill Paul struct ti_producer ti_ev_prodidx_r; 9235ddfea8cSPyun YongHyeon uint32_t ti_pad0[6]; 924d02c2331SBill Paul struct ti_producer ti_return_prodidx_r; 9255ddfea8cSPyun YongHyeon uint32_t ti_pad1[6]; 926d02c2331SBill Paul struct ti_producer ti_tx_considx_r; 9275ddfea8cSPyun YongHyeon uint32_t ti_pad2[6]; 928d02c2331SBill Paul }; 929d02c2331SBill Paul 930b7c2632dSPyun YongHyeon /* 931b7c2632dSPyun YongHyeon * Ring structures. Most of these reside in host memory and we tell 932b7c2632dSPyun YongHyeon * the NIC where they are via the ring control blocks. The exceptions 933b7c2632dSPyun YongHyeon * are the tx and command rings, which live in NIC memory and which 934b7c2632dSPyun YongHyeon * we access via the shared memory window. 935b7c2632dSPyun YongHyeon */ 936b7c2632dSPyun YongHyeon struct ti_ring_data { 937b7c2632dSPyun YongHyeon struct ti_gib *ti_info; 938b7c2632dSPyun YongHyeon bus_addr_t ti_info_paddr; 939b7c2632dSPyun YongHyeon struct ti_status *ti_status; 940b7c2632dSPyun YongHyeon bus_addr_t ti_status_paddr; 941b7c2632dSPyun YongHyeon struct ti_rx_desc *ti_rx_std_ring; 942b7c2632dSPyun YongHyeon bus_addr_t ti_rx_std_ring_paddr; 943b7c2632dSPyun YongHyeon #ifdef TI_SF_BUF_JUMBO 944b7c2632dSPyun YongHyeon struct ti_rx_desc_ext *ti_rx_jumbo_ring; 945b7c2632dSPyun YongHyeon #else 946b7c2632dSPyun YongHyeon struct ti_rx_desc *ti_rx_jumbo_ring; 947b7c2632dSPyun YongHyeon #endif 948b7c2632dSPyun YongHyeon bus_addr_t ti_rx_jumbo_ring_paddr; 949b7c2632dSPyun YongHyeon struct ti_rx_desc *ti_rx_mini_ring; 950b7c2632dSPyun YongHyeon bus_addr_t ti_rx_mini_ring_paddr; 951b7c2632dSPyun YongHyeon struct ti_rx_desc *ti_rx_return_ring; 952b7c2632dSPyun YongHyeon bus_addr_t ti_rx_return_ring_paddr; 953b7c2632dSPyun YongHyeon struct ti_event_desc *ti_event_ring; 954b7c2632dSPyun YongHyeon bus_addr_t ti_event_ring_paddr; 955b7c2632dSPyun YongHyeon struct ti_tx_desc *ti_tx_ring; 956b7c2632dSPyun YongHyeon bus_addr_t ti_tx_ring_paddr; 957b7c2632dSPyun YongHyeon }; 958d54c9057SPyun YongHyeon 959d02c2331SBill Paul /* 960d02c2331SBill Paul * Mbuf pointers. We need these to keep track of the virtual addresses 961d02c2331SBill Paul * of our mbuf chains since we can only convert from physical to virtual, 962d02c2331SBill Paul * not the other way around. 963d02c2331SBill Paul */ 964d02c2331SBill Paul struct ti_chain_data { 965b7c2632dSPyun YongHyeon bus_dma_tag_t ti_parent_tag; 966b7c2632dSPyun YongHyeon bus_dma_tag_t ti_gib_tag; 967b7c2632dSPyun YongHyeon bus_dmamap_t ti_gib_map; 968b7c2632dSPyun YongHyeon bus_dma_tag_t ti_event_ring_tag; 969b7c2632dSPyun YongHyeon bus_dmamap_t ti_event_ring_map; 970b7c2632dSPyun YongHyeon bus_dma_tag_t ti_status_tag; 971b7c2632dSPyun YongHyeon bus_dmamap_t ti_status_map; 972b7c2632dSPyun YongHyeon bus_dma_tag_t ti_tx_ring_tag; 973b7c2632dSPyun YongHyeon bus_dmamap_t ti_tx_ring_map; 974b7c2632dSPyun YongHyeon bus_dma_tag_t ti_tx_tag; 975ff3ced12SPyun YongHyeon struct ti_txdesc ti_txdesc[TI_TX_RING_CNT]; 976ff3ced12SPyun YongHyeon struct ti_txdq ti_txfreeq; 977ff3ced12SPyun YongHyeon struct ti_txdq ti_txbusyq; 978b7c2632dSPyun YongHyeon bus_dma_tag_t ti_rx_return_ring_tag; 979b7c2632dSPyun YongHyeon bus_dmamap_t ti_rx_return_ring_map; 980b7c2632dSPyun YongHyeon bus_dma_tag_t ti_rx_std_ring_tag; 981b7c2632dSPyun YongHyeon bus_dmamap_t ti_rx_std_ring_map; 982b7c2632dSPyun YongHyeon bus_dma_tag_t ti_rx_std_tag; 983d02c2331SBill Paul struct mbuf *ti_rx_std_chain[TI_STD_RX_RING_CNT]; 9846239708bSScott Long bus_dmamap_t ti_rx_std_maps[TI_STD_RX_RING_CNT]; 98510a4360cSPyun YongHyeon bus_dmamap_t ti_rx_std_sparemap; 986b7c2632dSPyun YongHyeon bus_dma_tag_t ti_rx_jumbo_ring_tag; 987b7c2632dSPyun YongHyeon bus_dmamap_t ti_rx_jumbo_ring_map; 988b7c2632dSPyun YongHyeon bus_dma_tag_t ti_rx_jumbo_tag; 989d02c2331SBill Paul struct mbuf *ti_rx_jumbo_chain[TI_JUMBO_RX_RING_CNT]; 9906239708bSScott Long bus_dmamap_t ti_rx_jumbo_maps[TI_JUMBO_RX_RING_CNT]; 99110a4360cSPyun YongHyeon bus_dmamap_t ti_rx_jumbo_sparemap; 992b7c2632dSPyun YongHyeon bus_dma_tag_t ti_rx_mini_ring_tag; 993b7c2632dSPyun YongHyeon bus_dmamap_t ti_rx_mini_ring_map; 994b7c2632dSPyun YongHyeon bus_dma_tag_t ti_rx_mini_tag; 995d02c2331SBill Paul struct mbuf *ti_rx_mini_chain[TI_MINI_RX_RING_CNT]; 9966239708bSScott Long bus_dmamap_t ti_rx_mini_maps[TI_MINI_RX_RING_CNT]; 99710a4360cSPyun YongHyeon bus_dmamap_t ti_rx_mini_sparemap; 998d02c2331SBill Paul }; 999d02c2331SBill Paul 1000d02c2331SBill Paul struct ti_type { 10015ddfea8cSPyun YongHyeon uint16_t ti_vid; 10025ddfea8cSPyun YongHyeon uint16_t ti_did; 1003a1d090d4SMarius Strobl const char *ti_name; 1004d02c2331SBill Paul }; 1005d02c2331SBill Paul 1006d02c2331SBill Paul #define TI_HWREV_TIGON 0x01 1007d02c2331SBill Paul #define TI_HWREV_TIGON_II 0x02 1008d02c2331SBill Paul #define TI_TIMEOUT 1000 1009d02c2331SBill Paul #define TI_TXCONS_UNSET 0xFFFF /* impossible value */ 1010d02c2331SBill Paul 1011d02c2331SBill Paul struct ti_mc_entry { 1012d02c2331SBill Paul struct ether_addr mc_addr; 1013e3975643SJake Burkholder SLIST_ENTRY(ti_mc_entry) mc_entries; 1014d02c2331SBill Paul }; 1015d02c2331SBill Paul 101698cb733cSKenneth D. Merry typedef enum { 101798cb733cSKenneth D. Merry TI_FLAG_NONE = 0x00, 101898cb733cSKenneth D. Merry TI_FLAG_DEBUGING = 0x01, 101998cb733cSKenneth D. Merry TI_FLAG_WAIT_FOR_LINK = 0x02 102098cb733cSKenneth D. Merry } ti_flag_vals; 102198cb733cSKenneth D. Merry 1022d02c2331SBill Paul struct ti_softc { 10236239708bSScott Long device_t ti_dev; 1024fc74a9f9SBrooks Davis struct ifnet *ti_ifp; 1025d02c2331SBill Paul bus_space_handle_t ti_bhandle; 1026d02c2331SBill Paul bus_space_tag_t ti_btag; 102789ca84e6SBill Paul void *ti_intrhand; 102889ca84e6SBill Paul struct resource *ti_irq; 102989ca84e6SBill Paul struct resource *ti_res; 1030d02c2331SBill Paul struct ifmedia ifmedia; /* media info */ 10315ddfea8cSPyun YongHyeon uint8_t ti_hwrev; /* Tigon rev (1 or 2) */ 10325ddfea8cSPyun YongHyeon uint8_t ti_copper; /* 1000baseTX card */ 10335ddfea8cSPyun YongHyeon uint8_t ti_linkstat; /* Link state */ 103498cb733cSKenneth D. Merry int ti_hdrsplit; /* enable header splitting */ 1035b7c2632dSPyun YongHyeon int ti_dac; 1036b7c2632dSPyun YongHyeon struct ti_ring_data ti_rdata; /* rings */ 1037d02c2331SBill Paul struct ti_chain_data ti_cdata; /* mbufs */ 1038b7c2632dSPyun YongHyeon #define ti_ev_prodidx ti_rdata.ti_status->ti_ev_prodidx_r 1039b7c2632dSPyun YongHyeon #define ti_return_prodidx ti_rdata.ti_status->ti_return_prodidx_r 1040b7c2632dSPyun YongHyeon #define ti_tx_considx ti_rdata.ti_status->ti_tx_considx_r 1041ff3ced12SPyun YongHyeon int ti_tx_saved_prodidx; 1042ff3ced12SPyun YongHyeon int ti_tx_saved_considx; 1043ff3ced12SPyun YongHyeon int ti_rx_saved_considx; 1044ff3ced12SPyun YongHyeon int ti_ev_saved_considx; 1045ff3ced12SPyun YongHyeon int ti_cmd_saved_prodidx; 1046ff3ced12SPyun YongHyeon int ti_std; /* current std ring head */ 1047ff3ced12SPyun YongHyeon int ti_mini; /* current mini ring head */ 1048ff3ced12SPyun YongHyeon int ti_jumbo; /* current jumo ring head */ 1049e3975643SJake Burkholder SLIST_HEAD(__ti_mchead, ti_mc_entry) ti_mc_listhead; 10505ddfea8cSPyun YongHyeon uint32_t ti_stat_ticks; 10515ddfea8cSPyun YongHyeon uint32_t ti_rx_coal_ticks; 10525ddfea8cSPyun YongHyeon uint32_t ti_tx_coal_ticks; 10535ddfea8cSPyun YongHyeon uint32_t ti_rx_max_coal_bds; 10545ddfea8cSPyun YongHyeon uint32_t ti_tx_max_coal_bds; 10555ddfea8cSPyun YongHyeon uint32_t ti_tx_buf_ratio; 1056d02c2331SBill Paul int ti_if_flags; 105727434230SBill Paul int ti_txcnt; 1058d1ce9105SBill Paul struct mtx ti_mtx; 10597cf545d0SJohn Baldwin struct callout ti_watchdog; 10607cf545d0SJohn Baldwin int ti_timer; 106198cb733cSKenneth D. Merry ti_flag_vals ti_flags; 10629b81d5e3SPyun YongHyeon uint8_t *ti_membuf; 10639b81d5e3SPyun YongHyeon uint8_t *ti_membuf2; 106489c9c53dSPoul-Henning Kamp struct cdev *dev; 1065d02c2331SBill Paul }; 1066d02c2331SBill Paul 10679ed346baSBosko Milekic #define TI_LOCK(_sc) mtx_lock(&(_sc)->ti_mtx) 10689ed346baSBosko Milekic #define TI_UNLOCK(_sc) mtx_unlock(&(_sc)->ti_mtx) 10695120abbfSSam Leffler #define TI_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->ti_mtx, MA_OWNED) 1070d1ce9105SBill Paul 1071d02c2331SBill Paul /* 1072d02c2331SBill Paul * Microchip Technology 24Cxx EEPROM control bytes 1073d02c2331SBill Paul */ 1074d02c2331SBill Paul #define EEPROM_CTL_READ 0xA1 /* 0101 0001 */ 1075d02c2331SBill Paul #define EEPROM_CTL_WRITE 0xA0 /* 0101 0000 */ 1076d02c2331SBill Paul 1077d02c2331SBill Paul /* 1078d02c2331SBill Paul * Note that EEPROM_START leaves transmission enabled. 1079d02c2331SBill Paul */ 1080d54c9057SPyun YongHyeon #define EEPROM_START do { \ 1081d02c2331SBill Paul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock pin high */\ 1082d02c2331SBill Paul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Set DATA bit to 1 */ \ 1083d02c2331SBill Paul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Enable xmit to write bit */\ 1084d02c2331SBill Paul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Pull DATA bit to 0 again */\ 1085d54c9057SPyun YongHyeon TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock low again */ \ 1086d54c9057SPyun YongHyeon } while(0) 1087d02c2331SBill Paul 1088d02c2331SBill Paul /* 1089d02c2331SBill Paul * EEPROM_STOP ends access to the EEPROM and clears the ETXEN bit so 1090d02c2331SBill Paul * that no further data can be written to the EEPROM I/O pin. 1091d02c2331SBill Paul */ 1092d54c9057SPyun YongHyeon #define EEPROM_STOP do { \ 1093d02c2331SBill Paul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Disable xmit */ \ 1094d02c2331SBill Paul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Pull DATA to 0 */ \ 1095d02c2331SBill Paul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock high */ \ 1096d02c2331SBill Paul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Enable xmit */ \ 1097d02c2331SBill Paul TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Toggle DATA to 1 */ \ 1098d02c2331SBill Paul TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Disable xmit. */ \ 1099d54c9057SPyun YongHyeon TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock low again */ \ 1100d54c9057SPyun YongHyeon } while(0) 1101