1 /*- 2 * Copyright (c) 2012 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * This software was developed by Oleksandr Rybalko under sponsorship 6 * from the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_ddb.h" 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/conf.h> 39 #include <sys/kdb.h> 40 #include <machine/bus.h> 41 #include <machine/fdt.h> 42 43 #include <dev/uart/uart.h> 44 #include <dev/uart/uart_cpu.h> 45 #include <dev/uart/uart_cpu_fdt.h> 46 #include <dev/uart/uart_bus.h> 47 #include <dev/uart/uart_dev_imx.h> 48 #include "uart_if.h" 49 50 #include <arm/freescale/imx/imx_ccmvar.h> 51 52 /* 53 * The hardare FIFOs are 32 bytes. We want an interrupt when there are 24 bytes 54 * available to read or space for 24 more bytes to write. While 8 bytes of 55 * slack before over/underrun might seem excessive, the hardware can run at 56 * 5mbps, which means 2uS per char, so at full speed 8 bytes provides only 16uS 57 * to get into the interrupt handler and service the fifo. 58 */ 59 #define IMX_FIFOSZ 32 60 #define IMX_RXFIFO_LEVEL 24 61 #define IMX_TXFIFO_LEVEL 24 62 63 /* 64 * Low-level UART interface. 65 */ 66 static int imx_uart_probe(struct uart_bas *bas); 67 static void imx_uart_init(struct uart_bas *bas, int, int, int, int); 68 static void imx_uart_term(struct uart_bas *bas); 69 static void imx_uart_putc(struct uart_bas *bas, int); 70 static int imx_uart_rxready(struct uart_bas *bas); 71 static int imx_uart_getc(struct uart_bas *bas, struct mtx *); 72 73 static struct uart_ops uart_imx_uart_ops = { 74 .probe = imx_uart_probe, 75 .init = imx_uart_init, 76 .term = imx_uart_term, 77 .putc = imx_uart_putc, 78 .rxready = imx_uart_rxready, 79 .getc = imx_uart_getc, 80 }; 81 82 #if 0 /* Handy when debugging. */ 83 static void 84 dumpregs(struct uart_bas *bas, const char * msg) 85 { 86 87 if (!bootverbose) 88 return; 89 printf("%s bsh 0x%08lx UCR1 0x%08x UCR2 0x%08x " 90 "UCR3 0x%08x UCR4 0x%08x USR1 0x%08x USR2 0x%08x\n", 91 msg, bas->bsh, 92 GETREG(bas, REG(UCR1)), GETREG(bas, REG(UCR2)), 93 GETREG(bas, REG(UCR3)), GETREG(bas, REG(UCR4)), 94 GETREG(bas, REG(USR1)), GETREG(bas, REG(USR2))); 95 } 96 #endif 97 98 static int 99 imx_uart_probe(struct uart_bas *bas) 100 { 101 102 return (0); 103 } 104 105 static u_int 106 imx_uart_getbaud(struct uart_bas *bas) 107 { 108 uint32_t rate, ubir, ubmr; 109 u_int baud, blo, bhi, i; 110 static const u_int predivs[] = {6, 5, 4, 3, 2, 1, 7, 1}; 111 static const u_int std_rates[] = { 112 9600, 14400, 19200, 38400, 57600, 115200, 230400, 460800, 921600 113 }; 114 115 /* 116 * Get the baud rate the hardware is programmed for, then search the 117 * table of standard baud rates for a number that's within 3% of the 118 * actual rate the hardware is programmed for. It's more comforting to 119 * see that your console is running at 115200 than 114942. Note that 120 * here we cannot make a simplifying assumption that the predivider and 121 * numerator are 1 (like we do when setting the baud rate), because we 122 * don't know what u-boot might have set up. 123 */ 124 i = (GETREG(bas, REG(UFCR)) & IMXUART_UFCR_RFDIV_MASK) >> 125 IMXUART_UFCR_RFDIV_SHIFT; 126 rate = imx_ccm_uart_hz() / predivs[i]; 127 ubir = GETREG(bas, REG(UBIR)) + 1; 128 ubmr = GETREG(bas, REG(UBMR)) + 1; 129 baud = ((rate / 16 ) * ubir) / ubmr; 130 131 blo = (baud * 100) / 103; 132 bhi = (baud * 100) / 97; 133 for (i = 0; i < nitems(std_rates); i++) { 134 rate = std_rates[i]; 135 if (rate >= blo && rate <= bhi) { 136 baud = rate; 137 break; 138 } 139 } 140 141 return (baud); 142 } 143 144 static void 145 imx_uart_init(struct uart_bas *bas, int baudrate, int databits, 146 int stopbits, int parity) 147 { 148 uint32_t baseclk, reg; 149 150 /* Enable the device and the RX/TX channels. */ 151 SET(bas, REG(UCR1), FLD(UCR1, UARTEN)); 152 SET(bas, REG(UCR2), FLD(UCR2, RXEN) | FLD(UCR2, TXEN)); 153 154 if (databits == 7) 155 DIS(bas, UCR2, WS); 156 else 157 ENA(bas, UCR2, WS); 158 159 if (stopbits == 2) 160 ENA(bas, UCR2, STPB); 161 else 162 DIS(bas, UCR2, STPB); 163 164 switch (parity) { 165 case UART_PARITY_ODD: 166 DIS(bas, UCR2, PROE); 167 ENA(bas, UCR2, PREN); 168 break; 169 case UART_PARITY_EVEN: 170 ENA(bas, UCR2, PROE); 171 ENA(bas, UCR2, PREN); 172 break; 173 case UART_PARITY_MARK: 174 case UART_PARITY_SPACE: 175 /* FALLTHROUGH: Hardware doesn't support mark/space. */ 176 case UART_PARITY_NONE: 177 default: 178 DIS(bas, UCR2, PREN); 179 break; 180 } 181 182 /* 183 * The hardware has an extremely flexible baud clock: it allows setting 184 * both the numerator and denominator of the divider, as well as a 185 * separate pre-divider. We simplify the problem of coming up with a 186 * workable pair of numbers by assuming a pre-divider and numerator of 187 * one because our base clock is so fast we can reach virtually any 188 * reasonable speed with a simple divisor. The numerator value actually 189 * includes the 16x over-sampling (so a value of 16 means divide by 1); 190 * the register value is the numerator-1, so we have a hard-coded 15. 191 * Note that a quirk of the hardware requires that both UBIR and UBMR be 192 * set back to back in order for the change to take effect. 193 */ 194 if (baudrate > 0) { 195 baseclk = imx_ccm_uart_hz(); 196 reg = GETREG(bas, REG(UFCR)); 197 reg = (reg & ~IMXUART_UFCR_RFDIV_MASK) | IMXUART_UFCR_RFDIV_DIV1; 198 SETREG(bas, REG(UFCR), reg); 199 SETREG(bas, REG(UBIR), 15); 200 SETREG(bas, REG(UBMR), (baseclk / baudrate) - 1); 201 } 202 203 /* 204 * Program the tx lowater and rx hiwater levels at which fifo-service 205 * interrupts are signaled. The tx value is interpetted as "when there 206 * are only this many bytes remaining" (not "this many free"). 207 */ 208 reg = GETREG(bas, REG(UFCR)); 209 reg &= ~(IMXUART_UFCR_TXTL_MASK | IMXUART_UFCR_RXTL_MASK); 210 reg |= (IMX_FIFOSZ - IMX_TXFIFO_LEVEL) << IMXUART_UFCR_TXTL_SHIFT; 211 reg |= IMX_RXFIFO_LEVEL << IMXUART_UFCR_RXTL_SHIFT; 212 SETREG(bas, REG(UFCR), reg); 213 } 214 215 static void 216 imx_uart_term(struct uart_bas *bas) 217 { 218 219 } 220 221 static void 222 imx_uart_putc(struct uart_bas *bas, int c) 223 { 224 225 while (!(IS(bas, USR1, TRDY))) 226 ; 227 SETREG(bas, REG(UTXD), c); 228 } 229 230 static int 231 imx_uart_rxready(struct uart_bas *bas) 232 { 233 234 return ((IS(bas, USR2, RDR)) ? 1 : 0); 235 } 236 237 static int 238 imx_uart_getc(struct uart_bas *bas, struct mtx *hwmtx) 239 { 240 int c; 241 242 uart_lock(hwmtx); 243 while (!(IS(bas, USR2, RDR))) 244 ; 245 246 c = GETREG(bas, REG(URXD)); 247 uart_unlock(hwmtx); 248 #if defined(KDB) 249 if (c & FLD(URXD, BRK)) { 250 if (kdb_break()) 251 return (0); 252 } 253 #endif 254 return (c & 0xff); 255 } 256 257 /* 258 * High-level UART interface. 259 */ 260 struct imx_uart_softc { 261 struct uart_softc base; 262 }; 263 264 static int imx_uart_bus_attach(struct uart_softc *); 265 static int imx_uart_bus_detach(struct uart_softc *); 266 static int imx_uart_bus_flush(struct uart_softc *, int); 267 static int imx_uart_bus_getsig(struct uart_softc *); 268 static int imx_uart_bus_ioctl(struct uart_softc *, int, intptr_t); 269 static int imx_uart_bus_ipend(struct uart_softc *); 270 static int imx_uart_bus_param(struct uart_softc *, int, int, int, int); 271 static int imx_uart_bus_probe(struct uart_softc *); 272 static int imx_uart_bus_receive(struct uart_softc *); 273 static int imx_uart_bus_setsig(struct uart_softc *, int); 274 static int imx_uart_bus_transmit(struct uart_softc *); 275 static void imx_uart_bus_grab(struct uart_softc *); 276 static void imx_uart_bus_ungrab(struct uart_softc *); 277 278 static kobj_method_t imx_uart_methods[] = { 279 KOBJMETHOD(uart_attach, imx_uart_bus_attach), 280 KOBJMETHOD(uart_detach, imx_uart_bus_detach), 281 KOBJMETHOD(uart_flush, imx_uart_bus_flush), 282 KOBJMETHOD(uart_getsig, imx_uart_bus_getsig), 283 KOBJMETHOD(uart_ioctl, imx_uart_bus_ioctl), 284 KOBJMETHOD(uart_ipend, imx_uart_bus_ipend), 285 KOBJMETHOD(uart_param, imx_uart_bus_param), 286 KOBJMETHOD(uart_probe, imx_uart_bus_probe), 287 KOBJMETHOD(uart_receive, imx_uart_bus_receive), 288 KOBJMETHOD(uart_setsig, imx_uart_bus_setsig), 289 KOBJMETHOD(uart_transmit, imx_uart_bus_transmit), 290 KOBJMETHOD(uart_grab, imx_uart_bus_grab), 291 KOBJMETHOD(uart_ungrab, imx_uart_bus_ungrab), 292 { 0, 0 } 293 }; 294 295 static struct uart_class uart_imx_class = { 296 "imx", 297 imx_uart_methods, 298 sizeof(struct imx_uart_softc), 299 .uc_ops = &uart_imx_uart_ops, 300 .uc_range = 0x100, 301 .uc_rclk = 24000000, /* TODO: get value from CCM */ 302 .uc_rshift = 0 303 }; 304 305 static struct ofw_compat_data compat_data[] = { 306 {"fsl,imx6q-uart", (uintptr_t)&uart_imx_class}, 307 {"fsl,imx53-uart", (uintptr_t)&uart_imx_class}, 308 {"fsl,imx51-uart", (uintptr_t)&uart_imx_class}, 309 {"fsl,imx31-uart", (uintptr_t)&uart_imx_class}, 310 {"fsl,imx27-uart", (uintptr_t)&uart_imx_class}, 311 {"fsl,imx25-uart", (uintptr_t)&uart_imx_class}, 312 {"fsl,imx21-uart", (uintptr_t)&uart_imx_class}, 313 {NULL, (uintptr_t)NULL}, 314 }; 315 UART_FDT_CLASS_AND_DEVICE(compat_data); 316 317 #define SIGCHG(c, i, s, d) \ 318 if (c) { \ 319 i |= (i & s) ? s : s | d; \ 320 } else { \ 321 i = (i & s) ? (i & ~s) | d : i; \ 322 } 323 324 static int 325 imx_uart_bus_attach(struct uart_softc *sc) 326 { 327 struct uart_bas *bas; 328 struct uart_devinfo *di; 329 330 bas = &sc->sc_bas; 331 if (sc->sc_sysdev != NULL) { 332 di = sc->sc_sysdev; 333 imx_uart_init(bas, di->baudrate, di->databits, di->stopbits, 334 di->parity); 335 } else { 336 imx_uart_init(bas, 115200, 8, 1, 0); 337 } 338 339 (void)imx_uart_bus_getsig(sc); 340 341 /* Clear all pending interrupts. */ 342 SETREG(bas, REG(USR1), 0xffff); 343 SETREG(bas, REG(USR2), 0xffff); 344 345 DIS(bas, UCR4, DREN); 346 ENA(bas, UCR1, RRDYEN); 347 DIS(bas, UCR1, IDEN); 348 DIS(bas, UCR3, RXDSEN); 349 ENA(bas, UCR2, ATEN); 350 DIS(bas, UCR1, TXMPTYEN); 351 DIS(bas, UCR1, TRDYEN); 352 DIS(bas, UCR4, TCEN); 353 DIS(bas, UCR4, OREN); 354 ENA(bas, UCR4, BKEN); 355 DIS(bas, UCR4, WKEN); 356 DIS(bas, UCR1, ADEN); 357 DIS(bas, UCR3, ACIEN); 358 DIS(bas, UCR2, ESCI); 359 DIS(bas, UCR4, ENIRI); 360 DIS(bas, UCR3, AIRINTEN); 361 DIS(bas, UCR3, AWAKEN); 362 DIS(bas, UCR3, FRAERREN); 363 DIS(bas, UCR3, PARERREN); 364 DIS(bas, UCR1, RTSDEN); 365 DIS(bas, UCR2, RTSEN); 366 DIS(bas, UCR3, DTREN); 367 DIS(bas, UCR3, RI); 368 DIS(bas, UCR3, DCD); 369 DIS(bas, UCR3, DTRDEN); 370 ENA(bas, UCR2, IRTS); 371 ENA(bas, UCR3, RXDMUXSEL); 372 373 return (0); 374 } 375 376 static int 377 imx_uart_bus_detach(struct uart_softc *sc) 378 { 379 380 SETREG(&sc->sc_bas, REG(UCR4), 0); 381 382 return (0); 383 } 384 385 static int 386 imx_uart_bus_flush(struct uart_softc *sc, int what) 387 { 388 389 /* TODO */ 390 return (0); 391 } 392 393 static int 394 imx_uart_bus_getsig(struct uart_softc *sc) 395 { 396 uint32_t new, old, sig; 397 uint8_t bes; 398 399 do { 400 old = sc->sc_hwsig; 401 sig = old; 402 uart_lock(sc->sc_hwmtx); 403 bes = GETREG(&sc->sc_bas, REG(USR2)); 404 uart_unlock(sc->sc_hwmtx); 405 /* XXX: chip can show delta */ 406 SIGCHG(bes & FLD(USR2, DCDIN), sig, SER_DCD, SER_DDCD); 407 new = sig & ~SER_MASK_DELTA; 408 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 409 410 return (sig); 411 } 412 413 static int 414 imx_uart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 415 { 416 struct uart_bas *bas; 417 int error; 418 419 bas = &sc->sc_bas; 420 error = 0; 421 uart_lock(sc->sc_hwmtx); 422 switch (request) { 423 case UART_IOCTL_BREAK: 424 /* TODO */ 425 break; 426 case UART_IOCTL_BAUD: 427 *(u_int*)data = imx_uart_getbaud(bas); 428 break; 429 default: 430 error = EINVAL; 431 break; 432 } 433 uart_unlock(sc->sc_hwmtx); 434 435 return (error); 436 } 437 438 static int 439 imx_uart_bus_ipend(struct uart_softc *sc) 440 { 441 struct uart_bas *bas; 442 int ipend; 443 uint32_t usr1, usr2; 444 uint32_t ucr1, ucr2, ucr4; 445 446 bas = &sc->sc_bas; 447 ipend = 0; 448 449 uart_lock(sc->sc_hwmtx); 450 451 /* Read pending interrupts */ 452 usr1 = GETREG(bas, REG(USR1)); 453 usr2 = GETREG(bas, REG(USR2)); 454 /* ACK interrupts */ 455 SETREG(bas, REG(USR1), usr1); 456 SETREG(bas, REG(USR2), usr2); 457 458 ucr1 = GETREG(bas, REG(UCR1)); 459 ucr2 = GETREG(bas, REG(UCR2)); 460 ucr4 = GETREG(bas, REG(UCR4)); 461 462 /* If we have reached tx low-water, we can tx some more now. */ 463 if ((usr1 & FLD(USR1, TRDY)) && (ucr1 & FLD(UCR1, TRDYEN))) { 464 DIS(bas, UCR1, TRDYEN); 465 ipend |= SER_INT_TXIDLE; 466 } 467 468 /* 469 * If we have reached the rx high-water, or if there are bytes in the rx 470 * fifo and no new data has arrived for 8 character periods (aging 471 * timer), we have input data to process. 472 */ 473 if (((usr1 & FLD(USR1, RRDY)) && (ucr1 & FLD(UCR1, RRDYEN))) || 474 ((usr1 & FLD(USR1, AGTIM)) && (ucr2 & FLD(UCR2, ATEN)))) { 475 DIS(bas, UCR1, RRDYEN); 476 DIS(bas, UCR2, ATEN); 477 ipend |= SER_INT_RXREADY; 478 } 479 480 /* A break can come in at any time, it never gets disabled. */ 481 if ((usr2 & FLD(USR2, BRCD)) && (ucr4 & FLD(UCR4, BKEN))) 482 ipend |= SER_INT_BREAK; 483 484 uart_unlock(sc->sc_hwmtx); 485 486 return (ipend); 487 } 488 489 static int 490 imx_uart_bus_param(struct uart_softc *sc, int baudrate, int databits, 491 int stopbits, int parity) 492 { 493 494 uart_lock(sc->sc_hwmtx); 495 imx_uart_init(&sc->sc_bas, baudrate, databits, stopbits, parity); 496 uart_unlock(sc->sc_hwmtx); 497 return (0); 498 } 499 500 static int 501 imx_uart_bus_probe(struct uart_softc *sc) 502 { 503 int error; 504 505 error = imx_uart_probe(&sc->sc_bas); 506 if (error) 507 return (error); 508 509 /* 510 * On input we can read up to the full fifo size at once. On output, we 511 * want to write only as much as the programmed tx low water level, 512 * because that's all we can be certain we have room for in the fifo 513 * when we get a tx-ready interrupt. 514 */ 515 sc->sc_rxfifosz = IMX_FIFOSZ; 516 sc->sc_txfifosz = IMX_TXFIFO_LEVEL; 517 518 device_set_desc(sc->sc_dev, "Freescale i.MX UART"); 519 return (0); 520 } 521 522 static int 523 imx_uart_bus_receive(struct uart_softc *sc) 524 { 525 struct uart_bas *bas; 526 int xc, out; 527 528 bas = &sc->sc_bas; 529 uart_lock(sc->sc_hwmtx); 530 531 /* 532 * Empty the rx fifo. We get the RRDY interrupt when IMX_RXFIFO_LEVEL 533 * (the rx high-water level) is reached, but we set sc_rxfifosz to the 534 * full hardware fifo size, so we can safely process however much is 535 * there, not just the highwater size. 536 */ 537 while (IS(bas, USR2, RDR)) { 538 if (uart_rx_full(sc)) { 539 /* No space left in input buffer */ 540 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 541 break; 542 } 543 xc = GETREG(bas, REG(URXD)); 544 out = xc & 0x000000ff; 545 if (xc & FLD(URXD, FRMERR)) 546 out |= UART_STAT_FRAMERR; 547 if (xc & FLD(URXD, PRERR)) 548 out |= UART_STAT_PARERR; 549 if (xc & FLD(URXD, OVRRUN)) 550 out |= UART_STAT_OVERRUN; 551 if (xc & FLD(URXD, BRK)) 552 out |= UART_STAT_BREAK; 553 554 uart_rx_put(sc, out); 555 } 556 ENA(bas, UCR1, RRDYEN); 557 ENA(bas, UCR2, ATEN); 558 559 uart_unlock(sc->sc_hwmtx); 560 return (0); 561 } 562 563 static int 564 imx_uart_bus_setsig(struct uart_softc *sc, int sig) 565 { 566 567 return (0); 568 } 569 570 static int 571 imx_uart_bus_transmit(struct uart_softc *sc) 572 { 573 struct uart_bas *bas = &sc->sc_bas; 574 int i; 575 576 bas = &sc->sc_bas; 577 uart_lock(sc->sc_hwmtx); 578 579 /* 580 * Fill the tx fifo. The uart core puts at most IMX_TXFIFO_LEVEL bytes 581 * into the txbuf (because that's what sc_txfifosz is set to), and 582 * because we got the TRDY (low-water reached) interrupt we know at 583 * least that much space is available in the fifo. 584 */ 585 for (i = 0; i < sc->sc_txdatasz; i++) { 586 SETREG(bas, REG(UTXD), sc->sc_txbuf[i] & 0xff); 587 } 588 sc->sc_txbusy = 1; 589 ENA(bas, UCR1, TRDYEN); 590 591 uart_unlock(sc->sc_hwmtx); 592 593 return (0); 594 } 595 596 static void 597 imx_uart_bus_grab(struct uart_softc *sc) 598 { 599 struct uart_bas *bas = &sc->sc_bas; 600 601 bas = &sc->sc_bas; 602 uart_lock(sc->sc_hwmtx); 603 DIS(bas, UCR1, RRDYEN); 604 DIS(bas, UCR2, ATEN); 605 uart_unlock(sc->sc_hwmtx); 606 } 607 608 static void 609 imx_uart_bus_ungrab(struct uart_softc *sc) 610 { 611 struct uart_bas *bas = &sc->sc_bas; 612 613 bas = &sc->sc_bas; 614 uart_lock(sc->sc_hwmtx); 615 ENA(bas, UCR1, RRDYEN); 616 ENA(bas, UCR2, ATEN); 617 uart_unlock(sc->sc_hwmtx); 618 } 619