1 /* $FreeBSD$ */ 2 /*- 3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 4 * 5 * Copyright (c) 2009 Hans Petter Selasky. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * This file contains the driver for the AVR32 series USB Device 31 * Controller 32 */ 33 34 /* 35 * NOTE: When the chip detects BUS-reset it will also reset the 36 * endpoints, Function-address and more. 37 */ 38 #ifdef USB_GLOBAL_INCLUDE_FILE 39 #include USB_GLOBAL_INCLUDE_FILE 40 #else 41 #include <sys/stdint.h> 42 #include <sys/stddef.h> 43 #include <sys/param.h> 44 #include <sys/queue.h> 45 #include <sys/types.h> 46 #include <sys/systm.h> 47 #include <sys/kernel.h> 48 #include <sys/bus.h> 49 #include <sys/module.h> 50 #include <sys/lock.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/sysctl.h> 54 #include <sys/sx.h> 55 #include <sys/unistd.h> 56 #include <sys/callout.h> 57 #include <sys/malloc.h> 58 #include <sys/priv.h> 59 60 #include <dev/usb/usb.h> 61 #include <dev/usb/usbdi.h> 62 63 #define USB_DEBUG_VAR avr32dci_debug 64 65 #include <dev/usb/usb_core.h> 66 #include <dev/usb/usb_debug.h> 67 #include <dev/usb/usb_busdma.h> 68 #include <dev/usb/usb_process.h> 69 #include <dev/usb/usb_transfer.h> 70 #include <dev/usb/usb_device.h> 71 #include <dev/usb/usb_hub.h> 72 #include <dev/usb/usb_util.h> 73 74 #include <dev/usb/usb_controller.h> 75 #include <dev/usb/usb_bus.h> 76 #endif /* USB_GLOBAL_INCLUDE_FILE */ 77 78 #include <dev/usb/controller/avr32dci.h> 79 80 #define AVR32_BUS2SC(bus) \ 81 ((struct avr32dci_softc *)(((uint8_t *)(bus)) - \ 82 ((uint8_t *)&(((struct avr32dci_softc *)0)->sc_bus)))) 83 84 #define AVR32_PC2SC(pc) \ 85 AVR32_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 86 87 #ifdef USB_DEBUG 88 static int avr32dci_debug = 0; 89 90 static SYSCTL_NODE(_hw_usb, OID_AUTO, avr32dci, 91 CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 92 "USB AVR32 DCI"); 93 SYSCTL_INT(_hw_usb_avr32dci, OID_AUTO, debug, CTLFLAG_RWTUN, 94 &avr32dci_debug, 0, "AVR32 DCI debug level"); 95 #endif 96 97 #define AVR32_INTR_ENDPT 1 98 99 /* prototypes */ 100 101 static const struct usb_bus_methods avr32dci_bus_methods; 102 static const struct usb_pipe_methods avr32dci_device_non_isoc_methods; 103 static const struct usb_pipe_methods avr32dci_device_isoc_fs_methods; 104 105 static avr32dci_cmd_t avr32dci_setup_rx; 106 static avr32dci_cmd_t avr32dci_data_rx; 107 static avr32dci_cmd_t avr32dci_data_tx; 108 static avr32dci_cmd_t avr32dci_data_tx_sync; 109 static void avr32dci_device_done(struct usb_xfer *, usb_error_t); 110 static void avr32dci_do_poll(struct usb_bus *); 111 static void avr32dci_standard_done(struct usb_xfer *); 112 static void avr32dci_root_intr(struct avr32dci_softc *sc); 113 114 /* 115 * Here is a list of what the chip supports: 116 */ 117 static const struct usb_hw_ep_profile 118 avr32dci_ep_profile[4] = { 119 [0] = { 120 .max_in_frame_size = 64, 121 .max_out_frame_size = 64, 122 .is_simplex = 1, 123 .support_control = 1, 124 }, 125 126 [1] = { 127 .max_in_frame_size = 512, 128 .max_out_frame_size = 512, 129 .is_simplex = 1, 130 .support_bulk = 1, 131 .support_interrupt = 1, 132 .support_isochronous = 1, 133 .support_in = 1, 134 .support_out = 1, 135 }, 136 137 [2] = { 138 .max_in_frame_size = 64, 139 .max_out_frame_size = 64, 140 .is_simplex = 1, 141 .support_bulk = 1, 142 .support_interrupt = 1, 143 .support_in = 1, 144 .support_out = 1, 145 }, 146 147 [3] = { 148 .max_in_frame_size = 1024, 149 .max_out_frame_size = 1024, 150 .is_simplex = 1, 151 .support_bulk = 1, 152 .support_interrupt = 1, 153 .support_isochronous = 1, 154 .support_in = 1, 155 .support_out = 1, 156 }, 157 }; 158 159 static void 160 avr32dci_get_hw_ep_profile(struct usb_device *udev, 161 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 162 { 163 if (ep_addr == 0) 164 *ppf = avr32dci_ep_profile; 165 else if (ep_addr < 3) 166 *ppf = avr32dci_ep_profile + 1; 167 else if (ep_addr < 5) 168 *ppf = avr32dci_ep_profile + 2; 169 else if (ep_addr < 7) 170 *ppf = avr32dci_ep_profile + 3; 171 else 172 *ppf = NULL; 173 } 174 175 static void 176 avr32dci_mod_ctrl(struct avr32dci_softc *sc, uint32_t set, uint32_t clear) 177 { 178 uint32_t temp; 179 180 temp = AVR32_READ_4(sc, AVR32_CTRL); 181 temp |= set; 182 temp &= ~clear; 183 AVR32_WRITE_4(sc, AVR32_CTRL, temp); 184 } 185 186 static void 187 avr32dci_mod_ien(struct avr32dci_softc *sc, uint32_t set, uint32_t clear) 188 { 189 uint32_t temp; 190 191 temp = AVR32_READ_4(sc, AVR32_IEN); 192 temp |= set; 193 temp &= ~clear; 194 AVR32_WRITE_4(sc, AVR32_IEN, temp); 195 } 196 197 static void 198 avr32dci_clocks_on(struct avr32dci_softc *sc) 199 { 200 if (sc->sc_flags.clocks_off && 201 sc->sc_flags.port_powered) { 202 DPRINTFN(5, "\n"); 203 204 /* turn on clocks */ 205 (sc->sc_clocks_on) (&sc->sc_bus); 206 207 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_EN_USBA, 0); 208 209 sc->sc_flags.clocks_off = 0; 210 } 211 } 212 213 static void 214 avr32dci_clocks_off(struct avr32dci_softc *sc) 215 { 216 if (!sc->sc_flags.clocks_off) { 217 DPRINTFN(5, "\n"); 218 219 avr32dci_mod_ctrl(sc, 0, AVR32_CTRL_DEV_EN_USBA); 220 221 /* turn clocks off */ 222 (sc->sc_clocks_off) (&sc->sc_bus); 223 224 sc->sc_flags.clocks_off = 1; 225 } 226 } 227 228 static void 229 avr32dci_pull_up(struct avr32dci_softc *sc) 230 { 231 /* pullup D+, if possible */ 232 233 if (!sc->sc_flags.d_pulled_up && 234 sc->sc_flags.port_powered) { 235 sc->sc_flags.d_pulled_up = 1; 236 avr32dci_mod_ctrl(sc, 0, AVR32_CTRL_DEV_DETACH); 237 } 238 } 239 240 static void 241 avr32dci_pull_down(struct avr32dci_softc *sc) 242 { 243 /* pulldown D+, if possible */ 244 245 if (sc->sc_flags.d_pulled_up) { 246 sc->sc_flags.d_pulled_up = 0; 247 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_DETACH, 0); 248 } 249 } 250 251 static void 252 avr32dci_wakeup_peer(struct avr32dci_softc *sc) 253 { 254 if (!sc->sc_flags.status_suspend) { 255 return; 256 } 257 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_REWAKEUP, 0); 258 259 /* wait 8 milliseconds */ 260 /* Wait for reset to complete. */ 261 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 262 263 /* hardware should have cleared RMWKUP bit */ 264 } 265 266 static void 267 avr32dci_set_address(struct avr32dci_softc *sc, uint8_t addr) 268 { 269 DPRINTFN(5, "addr=%d\n", addr); 270 271 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_FADDR_EN | addr, 0); 272 } 273 274 static uint8_t 275 avr32dci_setup_rx(struct avr32dci_td *td) 276 { 277 struct avr32dci_softc *sc; 278 struct usb_device_request req; 279 uint16_t count; 280 uint32_t temp; 281 282 /* get pointer to softc */ 283 sc = AVR32_PC2SC(td->pc); 284 285 /* check endpoint status */ 286 temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no)); 287 288 DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp); 289 290 if (!(temp & AVR32_EPTSTA_RX_SETUP)) { 291 goto not_complete; 292 } 293 /* clear did stall */ 294 td->did_stall = 0; 295 /* get the packet byte count */ 296 count = AVR32_EPTSTA_BYTE_COUNT(temp); 297 298 /* verify data length */ 299 if (count != td->remainder) { 300 DPRINTFN(0, "Invalid SETUP packet " 301 "length, %d bytes\n", count); 302 goto not_complete; 303 } 304 if (count != sizeof(req)) { 305 DPRINTFN(0, "Unsupported SETUP packet " 306 "length, %d bytes\n", count); 307 goto not_complete; 308 } 309 /* receive data */ 310 memcpy(&req, sc->physdata, sizeof(req)); 311 312 /* copy data into real buffer */ 313 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 314 315 td->offset = sizeof(req); 316 td->remainder = 0; 317 318 /* sneak peek the set address */ 319 if ((req.bmRequestType == UT_WRITE_DEVICE) && 320 (req.bRequest == UR_SET_ADDRESS)) { 321 sc->sc_dv_addr = req.wValue[0] & 0x7F; 322 /* must write address before ZLP */ 323 avr32dci_mod_ctrl(sc, 0, AVR32_CTRL_DEV_FADDR_EN | 324 AVR32_CTRL_DEV_ADDR); 325 avr32dci_mod_ctrl(sc, sc->sc_dv_addr, 0); 326 } else { 327 sc->sc_dv_addr = 0xFF; 328 } 329 330 /* clear SETUP packet interrupt */ 331 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_RX_SETUP); 332 return (0); /* complete */ 333 334 not_complete: 335 if (temp & AVR32_EPTSTA_RX_SETUP) { 336 /* clear SETUP packet interrupt */ 337 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_RX_SETUP); 338 } 339 /* abort any ongoing transfer */ 340 if (!td->did_stall) { 341 DPRINTFN(5, "stalling\n"); 342 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(td->ep_no), 343 AVR32_EPTSTA_FRCESTALL); 344 td->did_stall = 1; 345 } 346 return (1); /* not complete */ 347 } 348 349 static uint8_t 350 avr32dci_data_rx(struct avr32dci_td *td) 351 { 352 struct avr32dci_softc *sc; 353 struct usb_page_search buf_res; 354 uint16_t count; 355 uint32_t temp; 356 uint8_t to; 357 uint8_t got_short; 358 359 to = 4; /* don't loop forever! */ 360 got_short = 0; 361 362 /* get pointer to softc */ 363 sc = AVR32_PC2SC(td->pc); 364 365 repeat: 366 /* check if any of the FIFO banks have data */ 367 /* check endpoint status */ 368 temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no)); 369 370 DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp); 371 372 if (temp & AVR32_EPTSTA_RX_SETUP) { 373 if (td->remainder == 0) { 374 /* 375 * We are actually complete and have 376 * received the next SETUP 377 */ 378 DPRINTFN(5, "faking complete\n"); 379 return (0); /* complete */ 380 } 381 /* 382 * USB Host Aborted the transfer. 383 */ 384 td->error = 1; 385 return (0); /* complete */ 386 } 387 /* check status */ 388 if (!(temp & AVR32_EPTSTA_RX_BK_RDY)) { 389 /* no data */ 390 goto not_complete; 391 } 392 /* get the packet byte count */ 393 count = AVR32_EPTSTA_BYTE_COUNT(temp); 394 395 /* verify the packet byte count */ 396 if (count != td->max_packet_size) { 397 if (count < td->max_packet_size) { 398 /* we have a short packet */ 399 td->short_pkt = 1; 400 got_short = 1; 401 } else { 402 /* invalid USB packet */ 403 td->error = 1; 404 return (0); /* we are complete */ 405 } 406 } 407 /* verify the packet byte count */ 408 if (count > td->remainder) { 409 /* invalid USB packet */ 410 td->error = 1; 411 return (0); /* we are complete */ 412 } 413 while (count > 0) { 414 usbd_get_page(td->pc, td->offset, &buf_res); 415 416 /* get correct length */ 417 if (buf_res.length > count) { 418 buf_res.length = count; 419 } 420 /* receive data */ 421 memcpy(buf_res.buffer, sc->physdata + 422 (AVR32_EPTSTA_CURRENT_BANK(temp) << td->bank_shift) + 423 (td->ep_no << 16) + (td->offset % td->max_packet_size), buf_res.length); 424 /* update counters */ 425 count -= buf_res.length; 426 td->offset += buf_res.length; 427 td->remainder -= buf_res.length; 428 } 429 430 /* clear OUT packet interrupt */ 431 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_RX_BK_RDY); 432 433 /* check if we are complete */ 434 if ((td->remainder == 0) || got_short) { 435 if (td->short_pkt) { 436 /* we are complete */ 437 return (0); 438 } 439 /* else need to receive a zero length packet */ 440 } 441 if (--to) { 442 goto repeat; 443 } 444 not_complete: 445 return (1); /* not complete */ 446 } 447 448 static uint8_t 449 avr32dci_data_tx(struct avr32dci_td *td) 450 { 451 struct avr32dci_softc *sc; 452 struct usb_page_search buf_res; 453 uint16_t count; 454 uint8_t to; 455 uint32_t temp; 456 457 to = 4; /* don't loop forever! */ 458 459 /* get pointer to softc */ 460 sc = AVR32_PC2SC(td->pc); 461 462 repeat: 463 464 /* check endpoint status */ 465 temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no)); 466 467 DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp); 468 469 if (temp & AVR32_EPTSTA_RX_SETUP) { 470 /* 471 * The current transfer was aborted 472 * by the USB Host 473 */ 474 td->error = 1; 475 return (0); /* complete */ 476 } 477 if (temp & AVR32_EPTSTA_TX_PK_RDY) { 478 /* cannot write any data - all banks are busy */ 479 goto not_complete; 480 } 481 count = td->max_packet_size; 482 if (td->remainder < count) { 483 /* we have a short packet */ 484 td->short_pkt = 1; 485 count = td->remainder; 486 } 487 while (count > 0) { 488 usbd_get_page(td->pc, td->offset, &buf_res); 489 490 /* get correct length */ 491 if (buf_res.length > count) { 492 buf_res.length = count; 493 } 494 /* transmit data */ 495 memcpy(sc->physdata + 496 (AVR32_EPTSTA_CURRENT_BANK(temp) << td->bank_shift) + 497 (td->ep_no << 16) + (td->offset % td->max_packet_size), 498 buf_res.buffer, buf_res.length); 499 /* update counters */ 500 count -= buf_res.length; 501 td->offset += buf_res.length; 502 td->remainder -= buf_res.length; 503 } 504 505 /* allocate FIFO bank */ 506 AVR32_WRITE_4(sc, AVR32_EPTCTL(td->ep_no), AVR32_EPTCTL_TX_PK_RDY); 507 508 /* check remainder */ 509 if (td->remainder == 0) { 510 if (td->short_pkt) { 511 return (0); /* complete */ 512 } 513 /* else we need to transmit a short packet */ 514 } 515 if (--to) { 516 goto repeat; 517 } 518 not_complete: 519 return (1); /* not complete */ 520 } 521 522 static uint8_t 523 avr32dci_data_tx_sync(struct avr32dci_td *td) 524 { 525 struct avr32dci_softc *sc; 526 uint32_t temp; 527 528 /* get pointer to softc */ 529 sc = AVR32_PC2SC(td->pc); 530 531 /* check endpoint status */ 532 temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no)); 533 534 DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp); 535 536 if (temp & AVR32_EPTSTA_RX_SETUP) { 537 DPRINTFN(5, "faking complete\n"); 538 /* Race condition */ 539 return (0); /* complete */ 540 } 541 /* 542 * The control endpoint has only got one bank, so if that bank 543 * is free the packet has been transferred! 544 */ 545 if (AVR32_EPTSTA_BUSY_BANK_STA(temp) != 0) { 546 /* cannot write any data - a bank is busy */ 547 goto not_complete; 548 } 549 if (sc->sc_dv_addr != 0xFF) { 550 /* set new address */ 551 avr32dci_set_address(sc, sc->sc_dv_addr); 552 } 553 return (0); /* complete */ 554 555 not_complete: 556 return (1); /* not complete */ 557 } 558 559 static uint8_t 560 avr32dci_xfer_do_fifo(struct usb_xfer *xfer) 561 { 562 struct avr32dci_td *td; 563 564 DPRINTFN(9, "\n"); 565 566 td = xfer->td_transfer_cache; 567 while (1) { 568 if ((td->func) (td)) { 569 /* operation in progress */ 570 break; 571 } 572 if (((void *)td) == xfer->td_transfer_last) { 573 goto done; 574 } 575 if (td->error) { 576 goto done; 577 } else if (td->remainder > 0) { 578 /* 579 * We had a short transfer. If there is no alternate 580 * next, stop processing ! 581 */ 582 if (!td->alt_next) { 583 goto done; 584 } 585 } 586 /* 587 * Fetch the next transfer descriptor and transfer 588 * some flags to the next transfer descriptor 589 */ 590 td = td->obj_next; 591 xfer->td_transfer_cache = td; 592 } 593 return (1); /* not complete */ 594 595 done: 596 /* compute all actual lengths */ 597 598 avr32dci_standard_done(xfer); 599 return (0); /* complete */ 600 } 601 602 static void 603 avr32dci_interrupt_poll(struct avr32dci_softc *sc) 604 { 605 struct usb_xfer *xfer; 606 607 repeat: 608 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 609 if (!avr32dci_xfer_do_fifo(xfer)) { 610 /* queue has been modified */ 611 goto repeat; 612 } 613 } 614 } 615 616 void 617 avr32dci_vbus_interrupt(struct avr32dci_softc *sc, uint8_t is_on) 618 { 619 DPRINTFN(5, "vbus = %u\n", is_on); 620 621 if (is_on) { 622 if (!sc->sc_flags.status_vbus) { 623 sc->sc_flags.status_vbus = 1; 624 625 /* complete root HUB interrupt endpoint */ 626 627 avr32dci_root_intr(sc); 628 } 629 } else { 630 if (sc->sc_flags.status_vbus) { 631 sc->sc_flags.status_vbus = 0; 632 sc->sc_flags.status_bus_reset = 0; 633 sc->sc_flags.status_suspend = 0; 634 sc->sc_flags.change_suspend = 0; 635 sc->sc_flags.change_connect = 1; 636 637 /* complete root HUB interrupt endpoint */ 638 639 avr32dci_root_intr(sc); 640 } 641 } 642 } 643 644 void 645 avr32dci_interrupt(struct avr32dci_softc *sc) 646 { 647 uint32_t status; 648 649 USB_BUS_LOCK(&sc->sc_bus); 650 651 /* read interrupt status */ 652 status = AVR32_READ_4(sc, AVR32_INTSTA); 653 654 /* clear all set interrupts */ 655 AVR32_WRITE_4(sc, AVR32_CLRINT, status); 656 657 DPRINTFN(14, "INTSTA=0x%08x\n", status); 658 659 /* check for any bus state change interrupts */ 660 if (status & AVR32_INT_ENDRESET) { 661 DPRINTFN(5, "end of reset\n"); 662 663 /* set correct state */ 664 sc->sc_flags.status_bus_reset = 1; 665 sc->sc_flags.status_suspend = 0; 666 sc->sc_flags.change_suspend = 0; 667 sc->sc_flags.change_connect = 1; 668 669 /* disable resume interrupt */ 670 avr32dci_mod_ien(sc, AVR32_INT_DET_SUSPD | 671 AVR32_INT_ENDRESET, AVR32_INT_WAKE_UP); 672 673 /* complete root HUB interrupt endpoint */ 674 avr32dci_root_intr(sc); 675 } 676 /* 677 * If resume and suspend is set at the same time we interpret 678 * that like RESUME. Resume is set when there is at least 3 679 * milliseconds of inactivity on the USB BUS. 680 */ 681 if (status & AVR32_INT_WAKE_UP) { 682 DPRINTFN(5, "resume interrupt\n"); 683 684 if (sc->sc_flags.status_suspend) { 685 /* update status bits */ 686 sc->sc_flags.status_suspend = 0; 687 sc->sc_flags.change_suspend = 1; 688 689 /* disable resume interrupt */ 690 avr32dci_mod_ien(sc, AVR32_INT_DET_SUSPD | 691 AVR32_INT_ENDRESET, AVR32_INT_WAKE_UP); 692 693 /* complete root HUB interrupt endpoint */ 694 avr32dci_root_intr(sc); 695 } 696 } else if (status & AVR32_INT_DET_SUSPD) { 697 DPRINTFN(5, "suspend interrupt\n"); 698 699 if (!sc->sc_flags.status_suspend) { 700 /* update status bits */ 701 sc->sc_flags.status_suspend = 1; 702 sc->sc_flags.change_suspend = 1; 703 704 /* disable suspend interrupt */ 705 avr32dci_mod_ien(sc, AVR32_INT_WAKE_UP | 706 AVR32_INT_ENDRESET, AVR32_INT_DET_SUSPD); 707 708 /* complete root HUB interrupt endpoint */ 709 avr32dci_root_intr(sc); 710 } 711 } 712 /* check for any endpoint interrupts */ 713 if (status & -AVR32_INT_EPT_INT(0)) { 714 DPRINTFN(5, "real endpoint interrupt\n"); 715 716 avr32dci_interrupt_poll(sc); 717 } 718 USB_BUS_UNLOCK(&sc->sc_bus); 719 } 720 721 static void 722 avr32dci_setup_standard_chain_sub(struct avr32dci_std_temp *temp) 723 { 724 struct avr32dci_td *td; 725 726 /* get current Transfer Descriptor */ 727 td = temp->td_next; 728 temp->td = td; 729 730 /* prepare for next TD */ 731 temp->td_next = td->obj_next; 732 733 /* fill out the Transfer Descriptor */ 734 td->func = temp->func; 735 td->pc = temp->pc; 736 td->offset = temp->offset; 737 td->remainder = temp->len; 738 td->error = 0; 739 td->did_stall = temp->did_stall; 740 td->short_pkt = temp->short_pkt; 741 td->alt_next = temp->setup_alt_next; 742 } 743 744 static void 745 avr32dci_setup_standard_chain(struct usb_xfer *xfer) 746 { 747 struct avr32dci_std_temp temp; 748 struct avr32dci_softc *sc; 749 struct avr32dci_td *td; 750 uint32_t x; 751 uint8_t ep_no; 752 uint8_t need_sync; 753 754 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 755 xfer->address, UE_GET_ADDR(xfer->endpointno), 756 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 757 758 temp.max_frame_size = xfer->max_frame_size; 759 760 td = xfer->td_start[0]; 761 xfer->td_transfer_first = td; 762 xfer->td_transfer_cache = td; 763 764 /* setup temp */ 765 766 temp.pc = NULL; 767 temp.td = NULL; 768 temp.td_next = xfer->td_start[0]; 769 temp.offset = 0; 770 temp.setup_alt_next = xfer->flags_int.short_frames_ok || 771 xfer->flags_int.isochronous_xfr; 772 temp.did_stall = !xfer->flags_int.control_stall; 773 774 sc = AVR32_BUS2SC(xfer->xroot->bus); 775 ep_no = (xfer->endpointno & UE_ADDR); 776 777 /* check if we should prepend a setup message */ 778 779 if (xfer->flags_int.control_xfr) { 780 if (xfer->flags_int.control_hdr) { 781 temp.func = &avr32dci_setup_rx; 782 temp.len = xfer->frlengths[0]; 783 temp.pc = xfer->frbuffers + 0; 784 temp.short_pkt = temp.len ? 1 : 0; 785 /* check for last frame */ 786 if (xfer->nframes == 1) { 787 /* no STATUS stage yet, SETUP is last */ 788 if (xfer->flags_int.control_act) 789 temp.setup_alt_next = 0; 790 } 791 avr32dci_setup_standard_chain_sub(&temp); 792 } 793 x = 1; 794 } else { 795 x = 0; 796 } 797 798 if (x != xfer->nframes) { 799 if (xfer->endpointno & UE_DIR_IN) { 800 temp.func = &avr32dci_data_tx; 801 need_sync = 1; 802 } else { 803 temp.func = &avr32dci_data_rx; 804 need_sync = 0; 805 } 806 807 /* setup "pc" pointer */ 808 temp.pc = xfer->frbuffers + x; 809 } else { 810 need_sync = 0; 811 } 812 while (x != xfer->nframes) { 813 /* DATA0 / DATA1 message */ 814 815 temp.len = xfer->frlengths[x]; 816 817 x++; 818 819 if (x == xfer->nframes) { 820 if (xfer->flags_int.control_xfr) { 821 if (xfer->flags_int.control_act) { 822 temp.setup_alt_next = 0; 823 } 824 } else { 825 temp.setup_alt_next = 0; 826 } 827 } 828 if (temp.len == 0) { 829 /* make sure that we send an USB packet */ 830 831 temp.short_pkt = 0; 832 833 } else { 834 /* regular data transfer */ 835 836 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 837 } 838 839 avr32dci_setup_standard_chain_sub(&temp); 840 841 if (xfer->flags_int.isochronous_xfr) { 842 temp.offset += temp.len; 843 } else { 844 /* get next Page Cache pointer */ 845 temp.pc = xfer->frbuffers + x; 846 } 847 } 848 849 if (xfer->flags_int.control_xfr) { 850 /* always setup a valid "pc" pointer for status and sync */ 851 temp.pc = xfer->frbuffers + 0; 852 temp.len = 0; 853 temp.short_pkt = 0; 854 temp.setup_alt_next = 0; 855 856 /* check if we need to sync */ 857 if (need_sync) { 858 /* we need a SYNC point after TX */ 859 temp.func = &avr32dci_data_tx_sync; 860 avr32dci_setup_standard_chain_sub(&temp); 861 } 862 /* check if we should append a status stage */ 863 if (!xfer->flags_int.control_act) { 864 /* 865 * Send a DATA1 message and invert the current 866 * endpoint direction. 867 */ 868 if (xfer->endpointno & UE_DIR_IN) { 869 temp.func = &avr32dci_data_rx; 870 need_sync = 0; 871 } else { 872 temp.func = &avr32dci_data_tx; 873 need_sync = 1; 874 } 875 876 avr32dci_setup_standard_chain_sub(&temp); 877 if (need_sync) { 878 /* we need a SYNC point after TX */ 879 temp.func = &avr32dci_data_tx_sync; 880 avr32dci_setup_standard_chain_sub(&temp); 881 } 882 } 883 } 884 /* must have at least one frame! */ 885 td = temp.td; 886 xfer->td_transfer_last = td; 887 } 888 889 static void 890 avr32dci_timeout(void *arg) 891 { 892 struct usb_xfer *xfer = arg; 893 894 DPRINTF("xfer=%p\n", xfer); 895 896 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 897 898 /* transfer is transferred */ 899 avr32dci_device_done(xfer, USB_ERR_TIMEOUT); 900 } 901 902 static void 903 avr32dci_start_standard_chain(struct usb_xfer *xfer) 904 { 905 DPRINTFN(9, "\n"); 906 907 /* poll one time - will turn on interrupts */ 908 if (avr32dci_xfer_do_fifo(xfer)) { 909 uint8_t ep_no = xfer->endpointno & UE_ADDR; 910 struct avr32dci_softc *sc = AVR32_BUS2SC(xfer->xroot->bus); 911 912 avr32dci_mod_ien(sc, AVR32_INT_EPT_INT(ep_no), 0); 913 914 /* put transfer on interrupt queue */ 915 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 916 917 /* start timeout, if any */ 918 if (xfer->timeout != 0) { 919 usbd_transfer_timeout_ms(xfer, 920 &avr32dci_timeout, xfer->timeout); 921 } 922 } 923 } 924 925 static void 926 avr32dci_root_intr(struct avr32dci_softc *sc) 927 { 928 DPRINTFN(9, "\n"); 929 930 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 931 932 /* set port bit */ 933 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 934 935 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 936 sizeof(sc->sc_hub_idata)); 937 } 938 939 static usb_error_t 940 avr32dci_standard_done_sub(struct usb_xfer *xfer) 941 { 942 struct avr32dci_td *td; 943 uint32_t len; 944 uint8_t error; 945 946 DPRINTFN(9, "\n"); 947 948 td = xfer->td_transfer_cache; 949 950 do { 951 len = td->remainder; 952 953 if (xfer->aframes != xfer->nframes) { 954 /* 955 * Verify the length and subtract 956 * the remainder from "frlengths[]": 957 */ 958 if (len > xfer->frlengths[xfer->aframes]) { 959 td->error = 1; 960 } else { 961 xfer->frlengths[xfer->aframes] -= len; 962 } 963 } 964 /* Check for transfer error */ 965 if (td->error) { 966 /* the transfer is finished */ 967 error = 1; 968 td = NULL; 969 break; 970 } 971 /* Check for short transfer */ 972 if (len > 0) { 973 if (xfer->flags_int.short_frames_ok || 974 xfer->flags_int.isochronous_xfr) { 975 /* follow alt next */ 976 if (td->alt_next) { 977 td = td->obj_next; 978 } else { 979 td = NULL; 980 } 981 } else { 982 /* the transfer is finished */ 983 td = NULL; 984 } 985 error = 0; 986 break; 987 } 988 td = td->obj_next; 989 990 /* this USB frame is complete */ 991 error = 0; 992 break; 993 994 } while (0); 995 996 /* update transfer cache */ 997 998 xfer->td_transfer_cache = td; 999 1000 return (error ? 1001 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1002 } 1003 1004 static void 1005 avr32dci_standard_done(struct usb_xfer *xfer) 1006 { 1007 usb_error_t err = 0; 1008 1009 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 1010 xfer, xfer->endpoint); 1011 1012 /* reset scanner */ 1013 1014 xfer->td_transfer_cache = xfer->td_transfer_first; 1015 1016 if (xfer->flags_int.control_xfr) { 1017 if (xfer->flags_int.control_hdr) { 1018 err = avr32dci_standard_done_sub(xfer); 1019 } 1020 xfer->aframes = 1; 1021 1022 if (xfer->td_transfer_cache == NULL) { 1023 goto done; 1024 } 1025 } 1026 while (xfer->aframes != xfer->nframes) { 1027 err = avr32dci_standard_done_sub(xfer); 1028 xfer->aframes++; 1029 1030 if (xfer->td_transfer_cache == NULL) { 1031 goto done; 1032 } 1033 } 1034 1035 if (xfer->flags_int.control_xfr && 1036 !xfer->flags_int.control_act) { 1037 err = avr32dci_standard_done_sub(xfer); 1038 } 1039 done: 1040 avr32dci_device_done(xfer, err); 1041 } 1042 1043 /*------------------------------------------------------------------------* 1044 * avr32dci_device_done 1045 * 1046 * NOTE: this function can be called more than one time on the 1047 * same USB transfer! 1048 *------------------------------------------------------------------------*/ 1049 static void 1050 avr32dci_device_done(struct usb_xfer *xfer, usb_error_t error) 1051 { 1052 struct avr32dci_softc *sc = AVR32_BUS2SC(xfer->xroot->bus); 1053 uint8_t ep_no; 1054 1055 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1056 1057 DPRINTFN(9, "xfer=%p, pipe=%p, error=%d\n", 1058 xfer, xfer->endpoint, error); 1059 1060 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 1061 ep_no = (xfer->endpointno & UE_ADDR); 1062 1063 /* disable endpoint interrupt */ 1064 avr32dci_mod_ien(sc, 0, AVR32_INT_EPT_INT(ep_no)); 1065 1066 DPRINTFN(15, "disabled interrupts!\n"); 1067 } 1068 /* dequeue transfer and start next transfer */ 1069 usbd_transfer_done(xfer, error); 1070 } 1071 1072 static void 1073 avr32dci_xfer_stall(struct usb_xfer *xfer) 1074 { 1075 avr32dci_device_done(xfer, USB_ERR_STALLED); 1076 } 1077 1078 static void 1079 avr32dci_set_stall(struct usb_device *udev, 1080 struct usb_endpoint *pipe, uint8_t *did_stall) 1081 { 1082 struct avr32dci_softc *sc; 1083 uint8_t ep_no; 1084 1085 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1086 1087 DPRINTFN(5, "pipe=%p\n", pipe); 1088 1089 sc = AVR32_BUS2SC(udev->bus); 1090 /* get endpoint number */ 1091 ep_no = (pipe->edesc->bEndpointAddress & UE_ADDR); 1092 /* set stall */ 1093 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(ep_no), AVR32_EPTSTA_FRCESTALL); 1094 } 1095 1096 static void 1097 avr32dci_clear_stall_sub(struct avr32dci_softc *sc, uint8_t ep_no, 1098 uint8_t ep_type, uint8_t ep_dir) 1099 { 1100 const struct usb_hw_ep_profile *pf; 1101 uint32_t temp; 1102 uint32_t epsize; 1103 uint8_t n; 1104 1105 if (ep_type == UE_CONTROL) { 1106 /* clearing stall is not needed */ 1107 return; 1108 } 1109 /* set endpoint reset */ 1110 AVR32_WRITE_4(sc, AVR32_EPTRST, AVR32_EPTRST_MASK(ep_no)); 1111 1112 /* set stall */ 1113 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(ep_no), AVR32_EPTSTA_FRCESTALL); 1114 1115 /* reset data toggle */ 1116 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(ep_no), AVR32_EPTSTA_TOGGLESQ); 1117 1118 /* clear stall */ 1119 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(ep_no), AVR32_EPTSTA_FRCESTALL); 1120 1121 if (ep_type == UE_BULK) { 1122 temp = AVR32_EPTCFG_TYPE_BULK; 1123 } else if (ep_type == UE_INTERRUPT) { 1124 temp = AVR32_EPTCFG_TYPE_INTR; 1125 } else { 1126 temp = AVR32_EPTCFG_TYPE_ISOC | 1127 AVR32_EPTCFG_NB_TRANS(1); 1128 } 1129 if (ep_dir & UE_DIR_IN) { 1130 temp |= AVR32_EPTCFG_EPDIR_IN; 1131 } 1132 avr32dci_get_hw_ep_profile(NULL, &pf, ep_no); 1133 1134 /* compute endpoint size (use maximum) */ 1135 epsize = pf->max_in_frame_size | pf->max_out_frame_size; 1136 n = 0; 1137 while ((epsize /= 2)) 1138 n++; 1139 temp |= AVR32_EPTCFG_EPSIZE(n); 1140 1141 /* use the maximum number of banks supported */ 1142 if (ep_no < 1) 1143 temp |= AVR32_EPTCFG_NBANK(1); 1144 else if (ep_no < 3) 1145 temp |= AVR32_EPTCFG_NBANK(2); 1146 else 1147 temp |= AVR32_EPTCFG_NBANK(3); 1148 1149 AVR32_WRITE_4(sc, AVR32_EPTCFG(ep_no), temp); 1150 1151 temp = AVR32_READ_4(sc, AVR32_EPTCFG(ep_no)); 1152 1153 if (!(temp & AVR32_EPTCFG_EPT_MAPD)) { 1154 device_printf(sc->sc_bus.bdev, "Chip rejected configuration\n"); 1155 } else { 1156 AVR32_WRITE_4(sc, AVR32_EPTCTLENB(ep_no), 1157 AVR32_EPTCTL_EPT_ENABL); 1158 } 1159 } 1160 1161 static void 1162 avr32dci_clear_stall(struct usb_device *udev, struct usb_endpoint *pipe) 1163 { 1164 struct avr32dci_softc *sc; 1165 struct usb_endpoint_descriptor *ed; 1166 1167 DPRINTFN(5, "pipe=%p\n", pipe); 1168 1169 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1170 1171 /* check mode */ 1172 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 1173 /* not supported */ 1174 return; 1175 } 1176 /* get softc */ 1177 sc = AVR32_BUS2SC(udev->bus); 1178 1179 /* get endpoint descriptor */ 1180 ed = pipe->edesc; 1181 1182 /* reset endpoint */ 1183 avr32dci_clear_stall_sub(sc, 1184 (ed->bEndpointAddress & UE_ADDR), 1185 (ed->bmAttributes & UE_XFERTYPE), 1186 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1187 } 1188 1189 usb_error_t 1190 avr32dci_init(struct avr32dci_softc *sc) 1191 { 1192 uint8_t n; 1193 1194 DPRINTF("start\n"); 1195 1196 /* set up the bus structure */ 1197 sc->sc_bus.usbrev = USB_REV_1_1; 1198 sc->sc_bus.methods = &avr32dci_bus_methods; 1199 1200 USB_BUS_LOCK(&sc->sc_bus); 1201 1202 /* make sure USB is enabled */ 1203 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_EN_USBA, 0); 1204 1205 /* turn on clocks */ 1206 (sc->sc_clocks_on) (&sc->sc_bus); 1207 1208 /* make sure device is re-enumerated */ 1209 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_DETACH, 0); 1210 1211 /* wait a little for things to stabilise */ 1212 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 20); 1213 1214 /* disable interrupts */ 1215 avr32dci_mod_ien(sc, 0, 0xFFFFFFFF); 1216 1217 /* enable interrupts */ 1218 avr32dci_mod_ien(sc, AVR32_INT_DET_SUSPD | 1219 AVR32_INT_ENDRESET, 0); 1220 1221 /* reset all endpoints */ 1222 AVR32_WRITE_4(sc, AVR32_EPTRST, (1 << AVR32_EP_MAX) - 1); 1223 1224 /* disable all endpoints */ 1225 for (n = 0; n != AVR32_EP_MAX; n++) { 1226 /* disable endpoint */ 1227 AVR32_WRITE_4(sc, AVR32_EPTCTLDIS(n), AVR32_EPTCTL_EPT_ENABL); 1228 } 1229 1230 /* turn off clocks */ 1231 1232 avr32dci_clocks_off(sc); 1233 1234 USB_BUS_UNLOCK(&sc->sc_bus); 1235 1236 /* catch any lost interrupts */ 1237 1238 avr32dci_do_poll(&sc->sc_bus); 1239 1240 return (0); /* success */ 1241 } 1242 1243 void 1244 avr32dci_uninit(struct avr32dci_softc *sc) 1245 { 1246 uint8_t n; 1247 1248 USB_BUS_LOCK(&sc->sc_bus); 1249 1250 /* turn on clocks */ 1251 (sc->sc_clocks_on) (&sc->sc_bus); 1252 1253 /* disable interrupts */ 1254 avr32dci_mod_ien(sc, 0, 0xFFFFFFFF); 1255 1256 /* reset all endpoints */ 1257 AVR32_WRITE_4(sc, AVR32_EPTRST, (1 << AVR32_EP_MAX) - 1); 1258 1259 /* disable all endpoints */ 1260 for (n = 0; n != AVR32_EP_MAX; n++) { 1261 /* disable endpoint */ 1262 AVR32_WRITE_4(sc, AVR32_EPTCTLDIS(n), AVR32_EPTCTL_EPT_ENABL); 1263 } 1264 1265 sc->sc_flags.port_powered = 0; 1266 sc->sc_flags.status_vbus = 0; 1267 sc->sc_flags.status_bus_reset = 0; 1268 sc->sc_flags.status_suspend = 0; 1269 sc->sc_flags.change_suspend = 0; 1270 sc->sc_flags.change_connect = 1; 1271 1272 avr32dci_pull_down(sc); 1273 avr32dci_clocks_off(sc); 1274 1275 USB_BUS_UNLOCK(&sc->sc_bus); 1276 } 1277 1278 static void 1279 avr32dci_suspend(struct avr32dci_softc *sc) 1280 { 1281 /* TODO */ 1282 } 1283 1284 static void 1285 avr32dci_resume(struct avr32dci_softc *sc) 1286 { 1287 /* TODO */ 1288 } 1289 1290 static void 1291 avr32dci_do_poll(struct usb_bus *bus) 1292 { 1293 struct avr32dci_softc *sc = AVR32_BUS2SC(bus); 1294 1295 USB_BUS_LOCK(&sc->sc_bus); 1296 avr32dci_interrupt_poll(sc); 1297 USB_BUS_UNLOCK(&sc->sc_bus); 1298 } 1299 1300 /*------------------------------------------------------------------------* 1301 * avr32dci bulk support 1302 * avr32dci control support 1303 * avr32dci interrupt support 1304 *------------------------------------------------------------------------*/ 1305 static void 1306 avr32dci_device_non_isoc_open(struct usb_xfer *xfer) 1307 { 1308 return; 1309 } 1310 1311 static void 1312 avr32dci_device_non_isoc_close(struct usb_xfer *xfer) 1313 { 1314 avr32dci_device_done(xfer, USB_ERR_CANCELLED); 1315 } 1316 1317 static void 1318 avr32dci_device_non_isoc_enter(struct usb_xfer *xfer) 1319 { 1320 return; 1321 } 1322 1323 static void 1324 avr32dci_device_non_isoc_start(struct usb_xfer *xfer) 1325 { 1326 /* setup TDs */ 1327 avr32dci_setup_standard_chain(xfer); 1328 avr32dci_start_standard_chain(xfer); 1329 } 1330 1331 static const struct usb_pipe_methods avr32dci_device_non_isoc_methods = 1332 { 1333 .open = avr32dci_device_non_isoc_open, 1334 .close = avr32dci_device_non_isoc_close, 1335 .enter = avr32dci_device_non_isoc_enter, 1336 .start = avr32dci_device_non_isoc_start, 1337 }; 1338 1339 /*------------------------------------------------------------------------* 1340 * avr32dci full speed isochronous support 1341 *------------------------------------------------------------------------*/ 1342 static void 1343 avr32dci_device_isoc_fs_open(struct usb_xfer *xfer) 1344 { 1345 return; 1346 } 1347 1348 static void 1349 avr32dci_device_isoc_fs_close(struct usb_xfer *xfer) 1350 { 1351 avr32dci_device_done(xfer, USB_ERR_CANCELLED); 1352 } 1353 1354 static void 1355 avr32dci_device_isoc_fs_enter(struct usb_xfer *xfer) 1356 { 1357 struct avr32dci_softc *sc = AVR32_BUS2SC(xfer->xroot->bus); 1358 uint32_t temp; 1359 uint32_t nframes; 1360 uint8_t ep_no; 1361 1362 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 1363 xfer, xfer->endpoint->isoc_next, xfer->nframes); 1364 1365 /* get the current frame index */ 1366 ep_no = xfer->endpointno & UE_ADDR; 1367 nframes = (AVR32_READ_4(sc, AVR32_FNUM) / 8); 1368 1369 nframes &= AVR32_FRAME_MASK; 1370 1371 /* 1372 * check if the frame index is within the window where the frames 1373 * will be inserted 1374 */ 1375 temp = (nframes - xfer->endpoint->isoc_next) & AVR32_FRAME_MASK; 1376 1377 if ((xfer->endpoint->is_synced == 0) || 1378 (temp < xfer->nframes)) { 1379 /* 1380 * If there is data underflow or the pipe queue is 1381 * empty we schedule the transfer a few frames ahead 1382 * of the current frame position. Else two isochronous 1383 * transfers might overlap. 1384 */ 1385 xfer->endpoint->isoc_next = (nframes + 3) & AVR32_FRAME_MASK; 1386 xfer->endpoint->is_synced = 1; 1387 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 1388 } 1389 /* 1390 * compute how many milliseconds the insertion is ahead of the 1391 * current frame position: 1392 */ 1393 temp = (xfer->endpoint->isoc_next - nframes) & AVR32_FRAME_MASK; 1394 1395 /* 1396 * pre-compute when the isochronous transfer will be finished: 1397 */ 1398 xfer->isoc_time_complete = 1399 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp + 1400 xfer->nframes; 1401 1402 /* compute frame number for next insertion */ 1403 xfer->endpoint->isoc_next += xfer->nframes; 1404 1405 /* setup TDs */ 1406 avr32dci_setup_standard_chain(xfer); 1407 } 1408 1409 static void 1410 avr32dci_device_isoc_fs_start(struct usb_xfer *xfer) 1411 { 1412 /* start TD chain */ 1413 avr32dci_start_standard_chain(xfer); 1414 } 1415 1416 static const struct usb_pipe_methods avr32dci_device_isoc_fs_methods = 1417 { 1418 .open = avr32dci_device_isoc_fs_open, 1419 .close = avr32dci_device_isoc_fs_close, 1420 .enter = avr32dci_device_isoc_fs_enter, 1421 .start = avr32dci_device_isoc_fs_start, 1422 }; 1423 1424 /*------------------------------------------------------------------------* 1425 * avr32dci root control support 1426 *------------------------------------------------------------------------* 1427 * Simulate a hardware HUB by handling all the necessary requests. 1428 *------------------------------------------------------------------------*/ 1429 1430 static const struct usb_device_descriptor avr32dci_devd = { 1431 .bLength = sizeof(struct usb_device_descriptor), 1432 .bDescriptorType = UDESC_DEVICE, 1433 .bcdUSB = {0x00, 0x02}, 1434 .bDeviceClass = UDCLASS_HUB, 1435 .bDeviceSubClass = UDSUBCLASS_HUB, 1436 .bDeviceProtocol = UDPROTO_HSHUBSTT, 1437 .bMaxPacketSize = 64, 1438 .bcdDevice = {0x00, 0x01}, 1439 .iManufacturer = 1, 1440 .iProduct = 2, 1441 .bNumConfigurations = 1, 1442 }; 1443 1444 static const struct usb_device_qualifier avr32dci_odevd = { 1445 .bLength = sizeof(struct usb_device_qualifier), 1446 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 1447 .bcdUSB = {0x00, 0x02}, 1448 .bDeviceClass = UDCLASS_HUB, 1449 .bDeviceSubClass = UDSUBCLASS_HUB, 1450 .bDeviceProtocol = UDPROTO_FSHUB, 1451 .bMaxPacketSize0 = 0, 1452 .bNumConfigurations = 0, 1453 }; 1454 1455 static const struct avr32dci_config_desc avr32dci_confd = { 1456 .confd = { 1457 .bLength = sizeof(struct usb_config_descriptor), 1458 .bDescriptorType = UDESC_CONFIG, 1459 .wTotalLength[0] = sizeof(avr32dci_confd), 1460 .bNumInterface = 1, 1461 .bConfigurationValue = 1, 1462 .iConfiguration = 0, 1463 .bmAttributes = UC_SELF_POWERED, 1464 .bMaxPower = 0, 1465 }, 1466 .ifcd = { 1467 .bLength = sizeof(struct usb_interface_descriptor), 1468 .bDescriptorType = UDESC_INTERFACE, 1469 .bNumEndpoints = 1, 1470 .bInterfaceClass = UICLASS_HUB, 1471 .bInterfaceSubClass = UISUBCLASS_HUB, 1472 .bInterfaceProtocol = 0, 1473 }, 1474 .endpd = { 1475 .bLength = sizeof(struct usb_endpoint_descriptor), 1476 .bDescriptorType = UDESC_ENDPOINT, 1477 .bEndpointAddress = (UE_DIR_IN | AVR32_INTR_ENDPT), 1478 .bmAttributes = UE_INTERRUPT, 1479 .wMaxPacketSize[0] = 8, 1480 .bInterval = 255, 1481 }, 1482 }; 1483 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 1484 1485 static const struct usb_hub_descriptor_min avr32dci_hubd = { 1486 .bDescLength = sizeof(avr32dci_hubd), 1487 .bDescriptorType = UDESC_HUB, 1488 .bNbrPorts = 1, 1489 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 1490 .bPwrOn2PwrGood = 50, 1491 .bHubContrCurrent = 0, 1492 .DeviceRemovable = {0}, /* port is removable */ 1493 }; 1494 1495 #define STRING_VENDOR \ 1496 "A\0V\0R\0003\0002" 1497 1498 #define STRING_PRODUCT \ 1499 "D\0C\0I\0 \0R\0o\0o\0t\0 \0H\0U\0B" 1500 1501 USB_MAKE_STRING_DESC(STRING_VENDOR, avr32dci_vendor); 1502 USB_MAKE_STRING_DESC(STRING_PRODUCT, avr32dci_product); 1503 1504 static usb_error_t 1505 avr32dci_roothub_exec(struct usb_device *udev, 1506 struct usb_device_request *req, const void **pptr, uint16_t *plength) 1507 { 1508 struct avr32dci_softc *sc = AVR32_BUS2SC(udev->bus); 1509 const void *ptr; 1510 uint16_t len; 1511 uint16_t value; 1512 uint16_t index; 1513 uint32_t temp; 1514 usb_error_t err; 1515 1516 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1517 1518 /* buffer reset */ 1519 ptr = (const void *)&sc->sc_hub_temp; 1520 len = 0; 1521 err = 0; 1522 1523 value = UGETW(req->wValue); 1524 index = UGETW(req->wIndex); 1525 1526 /* demultiplex the control request */ 1527 1528 switch (req->bmRequestType) { 1529 case UT_READ_DEVICE: 1530 switch (req->bRequest) { 1531 case UR_GET_DESCRIPTOR: 1532 goto tr_handle_get_descriptor; 1533 case UR_GET_CONFIG: 1534 goto tr_handle_get_config; 1535 case UR_GET_STATUS: 1536 goto tr_handle_get_status; 1537 default: 1538 goto tr_stalled; 1539 } 1540 break; 1541 1542 case UT_WRITE_DEVICE: 1543 switch (req->bRequest) { 1544 case UR_SET_ADDRESS: 1545 goto tr_handle_set_address; 1546 case UR_SET_CONFIG: 1547 goto tr_handle_set_config; 1548 case UR_CLEAR_FEATURE: 1549 goto tr_valid; /* nop */ 1550 case UR_SET_DESCRIPTOR: 1551 goto tr_valid; /* nop */ 1552 case UR_SET_FEATURE: 1553 default: 1554 goto tr_stalled; 1555 } 1556 break; 1557 1558 case UT_WRITE_ENDPOINT: 1559 switch (req->bRequest) { 1560 case UR_CLEAR_FEATURE: 1561 switch (UGETW(req->wValue)) { 1562 case UF_ENDPOINT_HALT: 1563 goto tr_handle_clear_halt; 1564 case UF_DEVICE_REMOTE_WAKEUP: 1565 goto tr_handle_clear_wakeup; 1566 default: 1567 goto tr_stalled; 1568 } 1569 break; 1570 case UR_SET_FEATURE: 1571 switch (UGETW(req->wValue)) { 1572 case UF_ENDPOINT_HALT: 1573 goto tr_handle_set_halt; 1574 case UF_DEVICE_REMOTE_WAKEUP: 1575 goto tr_handle_set_wakeup; 1576 default: 1577 goto tr_stalled; 1578 } 1579 break; 1580 case UR_SYNCH_FRAME: 1581 goto tr_valid; /* nop */ 1582 default: 1583 goto tr_stalled; 1584 } 1585 break; 1586 1587 case UT_READ_ENDPOINT: 1588 switch (req->bRequest) { 1589 case UR_GET_STATUS: 1590 goto tr_handle_get_ep_status; 1591 default: 1592 goto tr_stalled; 1593 } 1594 break; 1595 1596 case UT_WRITE_INTERFACE: 1597 switch (req->bRequest) { 1598 case UR_SET_INTERFACE: 1599 goto tr_handle_set_interface; 1600 case UR_CLEAR_FEATURE: 1601 goto tr_valid; /* nop */ 1602 case UR_SET_FEATURE: 1603 default: 1604 goto tr_stalled; 1605 } 1606 break; 1607 1608 case UT_READ_INTERFACE: 1609 switch (req->bRequest) { 1610 case UR_GET_INTERFACE: 1611 goto tr_handle_get_interface; 1612 case UR_GET_STATUS: 1613 goto tr_handle_get_iface_status; 1614 default: 1615 goto tr_stalled; 1616 } 1617 break; 1618 1619 case UT_WRITE_CLASS_INTERFACE: 1620 case UT_WRITE_VENDOR_INTERFACE: 1621 /* XXX forward */ 1622 break; 1623 1624 case UT_READ_CLASS_INTERFACE: 1625 case UT_READ_VENDOR_INTERFACE: 1626 /* XXX forward */ 1627 break; 1628 1629 case UT_WRITE_CLASS_DEVICE: 1630 switch (req->bRequest) { 1631 case UR_CLEAR_FEATURE: 1632 goto tr_valid; 1633 case UR_SET_DESCRIPTOR: 1634 case UR_SET_FEATURE: 1635 break; 1636 default: 1637 goto tr_stalled; 1638 } 1639 break; 1640 1641 case UT_WRITE_CLASS_OTHER: 1642 switch (req->bRequest) { 1643 case UR_CLEAR_FEATURE: 1644 goto tr_handle_clear_port_feature; 1645 case UR_SET_FEATURE: 1646 goto tr_handle_set_port_feature; 1647 case UR_CLEAR_TT_BUFFER: 1648 case UR_RESET_TT: 1649 case UR_STOP_TT: 1650 goto tr_valid; 1651 1652 default: 1653 goto tr_stalled; 1654 } 1655 break; 1656 1657 case UT_READ_CLASS_OTHER: 1658 switch (req->bRequest) { 1659 case UR_GET_TT_STATE: 1660 goto tr_handle_get_tt_state; 1661 case UR_GET_STATUS: 1662 goto tr_handle_get_port_status; 1663 default: 1664 goto tr_stalled; 1665 } 1666 break; 1667 1668 case UT_READ_CLASS_DEVICE: 1669 switch (req->bRequest) { 1670 case UR_GET_DESCRIPTOR: 1671 goto tr_handle_get_class_descriptor; 1672 case UR_GET_STATUS: 1673 goto tr_handle_get_class_status; 1674 1675 default: 1676 goto tr_stalled; 1677 } 1678 break; 1679 default: 1680 goto tr_stalled; 1681 } 1682 goto tr_valid; 1683 1684 tr_handle_get_descriptor: 1685 switch (value >> 8) { 1686 case UDESC_DEVICE: 1687 if (value & 0xff) { 1688 goto tr_stalled; 1689 } 1690 len = sizeof(avr32dci_devd); 1691 ptr = (const void *)&avr32dci_devd; 1692 goto tr_valid; 1693 case UDESC_CONFIG: 1694 if (value & 0xff) { 1695 goto tr_stalled; 1696 } 1697 len = sizeof(avr32dci_confd); 1698 ptr = (const void *)&avr32dci_confd; 1699 goto tr_valid; 1700 case UDESC_STRING: 1701 switch (value & 0xff) { 1702 case 0: /* Language table */ 1703 len = sizeof(usb_string_lang_en); 1704 ptr = (const void *)&usb_string_lang_en; 1705 goto tr_valid; 1706 1707 case 1: /* Vendor */ 1708 len = sizeof(avr32dci_vendor); 1709 ptr = (const void *)&avr32dci_vendor; 1710 goto tr_valid; 1711 1712 case 2: /* Product */ 1713 len = sizeof(avr32dci_product); 1714 ptr = (const void *)&avr32dci_product; 1715 goto tr_valid; 1716 default: 1717 break; 1718 } 1719 break; 1720 default: 1721 goto tr_stalled; 1722 } 1723 goto tr_stalled; 1724 1725 tr_handle_get_config: 1726 len = 1; 1727 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 1728 goto tr_valid; 1729 1730 tr_handle_get_status: 1731 len = 2; 1732 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 1733 goto tr_valid; 1734 1735 tr_handle_set_address: 1736 if (value & 0xFF00) { 1737 goto tr_stalled; 1738 } 1739 sc->sc_rt_addr = value; 1740 goto tr_valid; 1741 1742 tr_handle_set_config: 1743 if (value >= 2) { 1744 goto tr_stalled; 1745 } 1746 sc->sc_conf = value; 1747 goto tr_valid; 1748 1749 tr_handle_get_interface: 1750 len = 1; 1751 sc->sc_hub_temp.wValue[0] = 0; 1752 goto tr_valid; 1753 1754 tr_handle_get_tt_state: 1755 tr_handle_get_class_status: 1756 tr_handle_get_iface_status: 1757 tr_handle_get_ep_status: 1758 len = 2; 1759 USETW(sc->sc_hub_temp.wValue, 0); 1760 goto tr_valid; 1761 1762 tr_handle_set_halt: 1763 tr_handle_set_interface: 1764 tr_handle_set_wakeup: 1765 tr_handle_clear_wakeup: 1766 tr_handle_clear_halt: 1767 goto tr_valid; 1768 1769 tr_handle_clear_port_feature: 1770 if (index != 1) { 1771 goto tr_stalled; 1772 } 1773 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 1774 1775 switch (value) { 1776 case UHF_PORT_SUSPEND: 1777 avr32dci_wakeup_peer(sc); 1778 break; 1779 1780 case UHF_PORT_ENABLE: 1781 sc->sc_flags.port_enabled = 0; 1782 break; 1783 1784 case UHF_PORT_TEST: 1785 case UHF_PORT_INDICATOR: 1786 case UHF_C_PORT_ENABLE: 1787 case UHF_C_PORT_OVER_CURRENT: 1788 case UHF_C_PORT_RESET: 1789 /* nops */ 1790 break; 1791 case UHF_PORT_POWER: 1792 sc->sc_flags.port_powered = 0; 1793 avr32dci_pull_down(sc); 1794 avr32dci_clocks_off(sc); 1795 break; 1796 case UHF_C_PORT_CONNECTION: 1797 /* clear connect change flag */ 1798 sc->sc_flags.change_connect = 0; 1799 1800 if (!sc->sc_flags.status_bus_reset) { 1801 /* we are not connected */ 1802 break; 1803 } 1804 /* configure the control endpoint */ 1805 /* set endpoint reset */ 1806 AVR32_WRITE_4(sc, AVR32_EPTRST, AVR32_EPTRST_MASK(0)); 1807 1808 /* set stall */ 1809 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(0), AVR32_EPTSTA_FRCESTALL); 1810 1811 /* reset data toggle */ 1812 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(0), AVR32_EPTSTA_TOGGLESQ); 1813 1814 /* clear stall */ 1815 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(0), AVR32_EPTSTA_FRCESTALL); 1816 1817 /* configure */ 1818 AVR32_WRITE_4(sc, AVR32_EPTCFG(0), AVR32_EPTCFG_TYPE_CTRL | 1819 AVR32_EPTCFG_NBANK(1) | AVR32_EPTCFG_EPSIZE(6)); 1820 1821 temp = AVR32_READ_4(sc, AVR32_EPTCFG(0)); 1822 1823 if (!(temp & AVR32_EPTCFG_EPT_MAPD)) { 1824 device_printf(sc->sc_bus.bdev, 1825 "Chip rejected configuration\n"); 1826 } else { 1827 AVR32_WRITE_4(sc, AVR32_EPTCTLENB(0), 1828 AVR32_EPTCTL_EPT_ENABL); 1829 } 1830 break; 1831 case UHF_C_PORT_SUSPEND: 1832 sc->sc_flags.change_suspend = 0; 1833 break; 1834 default: 1835 err = USB_ERR_IOERROR; 1836 goto done; 1837 } 1838 goto tr_valid; 1839 1840 tr_handle_set_port_feature: 1841 if (index != 1) { 1842 goto tr_stalled; 1843 } 1844 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 1845 1846 switch (value) { 1847 case UHF_PORT_ENABLE: 1848 sc->sc_flags.port_enabled = 1; 1849 break; 1850 case UHF_PORT_SUSPEND: 1851 case UHF_PORT_RESET: 1852 case UHF_PORT_TEST: 1853 case UHF_PORT_INDICATOR: 1854 /* nops */ 1855 break; 1856 case UHF_PORT_POWER: 1857 sc->sc_flags.port_powered = 1; 1858 break; 1859 default: 1860 err = USB_ERR_IOERROR; 1861 goto done; 1862 } 1863 goto tr_valid; 1864 1865 tr_handle_get_port_status: 1866 1867 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 1868 1869 if (index != 1) { 1870 goto tr_stalled; 1871 } 1872 if (sc->sc_flags.status_vbus) { 1873 avr32dci_clocks_on(sc); 1874 avr32dci_pull_up(sc); 1875 } else { 1876 avr32dci_pull_down(sc); 1877 avr32dci_clocks_off(sc); 1878 } 1879 1880 /* Select Device Side Mode */ 1881 1882 value = UPS_PORT_MODE_DEVICE; 1883 1884 /* Check for High Speed */ 1885 if (AVR32_READ_4(sc, AVR32_INTSTA) & AVR32_INT_SPEED) 1886 value |= UPS_HIGH_SPEED; 1887 1888 if (sc->sc_flags.port_powered) { 1889 value |= UPS_PORT_POWER; 1890 } 1891 if (sc->sc_flags.port_enabled) { 1892 value |= UPS_PORT_ENABLED; 1893 } 1894 if (sc->sc_flags.status_vbus && 1895 sc->sc_flags.status_bus_reset) { 1896 value |= UPS_CURRENT_CONNECT_STATUS; 1897 } 1898 if (sc->sc_flags.status_suspend) { 1899 value |= UPS_SUSPEND; 1900 } 1901 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 1902 1903 value = 0; 1904 1905 if (sc->sc_flags.change_connect) { 1906 value |= UPS_C_CONNECT_STATUS; 1907 } 1908 if (sc->sc_flags.change_suspend) { 1909 value |= UPS_C_SUSPEND; 1910 } 1911 USETW(sc->sc_hub_temp.ps.wPortChange, value); 1912 len = sizeof(sc->sc_hub_temp.ps); 1913 goto tr_valid; 1914 1915 tr_handle_get_class_descriptor: 1916 if (value & 0xFF) { 1917 goto tr_stalled; 1918 } 1919 ptr = (const void *)&avr32dci_hubd; 1920 len = sizeof(avr32dci_hubd); 1921 goto tr_valid; 1922 1923 tr_stalled: 1924 err = USB_ERR_STALLED; 1925 tr_valid: 1926 done: 1927 *plength = len; 1928 *pptr = ptr; 1929 return (err); 1930 } 1931 1932 static void 1933 avr32dci_xfer_setup(struct usb_setup_params *parm) 1934 { 1935 const struct usb_hw_ep_profile *pf; 1936 struct avr32dci_softc *sc; 1937 struct usb_xfer *xfer; 1938 void *last_obj; 1939 uint32_t ntd; 1940 uint32_t n; 1941 uint8_t ep_no; 1942 1943 sc = AVR32_BUS2SC(parm->udev->bus); 1944 xfer = parm->curr_xfer; 1945 1946 /* 1947 * NOTE: This driver does not use any of the parameters that 1948 * are computed from the following values. Just set some 1949 * reasonable dummies: 1950 */ 1951 parm->hc_max_packet_size = 0x400; 1952 parm->hc_max_packet_count = 1; 1953 parm->hc_max_frame_size = 0x400; 1954 1955 usbd_transfer_setup_sub(parm); 1956 1957 /* 1958 * compute maximum number of TDs 1959 */ 1960 if ((xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) { 1961 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 1962 + 1 /* SYNC 2 */ ; 1963 } else { 1964 ntd = xfer->nframes + 1 /* SYNC */ ; 1965 } 1966 1967 /* 1968 * check if "usbd_transfer_setup_sub" set an error 1969 */ 1970 if (parm->err) 1971 return; 1972 1973 /* 1974 * allocate transfer descriptors 1975 */ 1976 last_obj = NULL; 1977 1978 /* 1979 * get profile stuff 1980 */ 1981 ep_no = xfer->endpointno & UE_ADDR; 1982 avr32dci_get_hw_ep_profile(parm->udev, &pf, ep_no); 1983 1984 if (pf == NULL) { 1985 /* should not happen */ 1986 parm->err = USB_ERR_INVAL; 1987 return; 1988 } 1989 /* align data */ 1990 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 1991 1992 for (n = 0; n != ntd; n++) { 1993 struct avr32dci_td *td; 1994 1995 if (parm->buf) { 1996 uint32_t temp; 1997 1998 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 1999 2000 /* init TD */ 2001 td->max_packet_size = xfer->max_packet_size; 2002 td->ep_no = ep_no; 2003 temp = pf->max_in_frame_size | pf->max_out_frame_size; 2004 td->bank_shift = 0; 2005 while ((temp /= 2)) 2006 td->bank_shift++; 2007 if (pf->support_multi_buffer) { 2008 td->support_multi_buffer = 1; 2009 } 2010 td->obj_next = last_obj; 2011 2012 last_obj = td; 2013 } 2014 parm->size[0] += sizeof(*td); 2015 } 2016 2017 xfer->td_start[0] = last_obj; 2018 } 2019 2020 static void 2021 avr32dci_xfer_unsetup(struct usb_xfer *xfer) 2022 { 2023 return; 2024 } 2025 2026 static void 2027 avr32dci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 2028 struct usb_endpoint *pipe) 2029 { 2030 struct avr32dci_softc *sc = AVR32_BUS2SC(udev->bus); 2031 2032 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", 2033 pipe, udev->address, 2034 edesc->bEndpointAddress, udev->flags.usb_mode, 2035 sc->sc_rt_addr, udev->device_index); 2036 2037 if (udev->device_index != sc->sc_rt_addr) { 2038 if ((udev->speed != USB_SPEED_FULL) && 2039 (udev->speed != USB_SPEED_HIGH)) { 2040 /* not supported */ 2041 return; 2042 } 2043 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) 2044 pipe->methods = &avr32dci_device_isoc_fs_methods; 2045 else 2046 pipe->methods = &avr32dci_device_non_isoc_methods; 2047 } 2048 } 2049 2050 static void 2051 avr32dci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 2052 { 2053 struct avr32dci_softc *sc = AVR32_BUS2SC(bus); 2054 2055 switch (state) { 2056 case USB_HW_POWER_SUSPEND: 2057 avr32dci_suspend(sc); 2058 break; 2059 case USB_HW_POWER_SHUTDOWN: 2060 avr32dci_uninit(sc); 2061 break; 2062 case USB_HW_POWER_RESUME: 2063 avr32dci_resume(sc); 2064 break; 2065 default: 2066 break; 2067 } 2068 } 2069 2070 static const struct usb_bus_methods avr32dci_bus_methods = 2071 { 2072 .endpoint_init = &avr32dci_ep_init, 2073 .xfer_setup = &avr32dci_xfer_setup, 2074 .xfer_unsetup = &avr32dci_xfer_unsetup, 2075 .get_hw_ep_profile = &avr32dci_get_hw_ep_profile, 2076 .xfer_stall = &avr32dci_xfer_stall, 2077 .set_stall = &avr32dci_set_stall, 2078 .clear_stall = &avr32dci_clear_stall, 2079 .roothub_exec = &avr32dci_roothub_exec, 2080 .xfer_poll = &avr32dci_do_poll, 2081 .set_hw_power_sleep = &avr32dci_set_hw_power_sleep, 2082 }; 2083