1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013-2014 Kevin Lo 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 /* 33 * ASIX Electronics AX88178A/AX88179 USB 2.0/3.0 gigabit ethernet driver. 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/bus.h> 39 #include <sys/condvar.h> 40 #include <sys/endian.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/module.h> 44 #include <sys/mutex.h> 45 #include <sys/socket.h> 46 #include <sys/sysctl.h> 47 #include <sys/unistd.h> 48 49 #include <net/if.h> 50 #include <net/if_var.h> 51 52 #include <dev/usb/usb.h> 53 #include <dev/usb/usbdi.h> 54 #include <dev/usb/usbdi_util.h> 55 #include "usbdevs.h" 56 57 #define USB_DEBUG_VAR axge_debug 58 #include <dev/usb/usb_debug.h> 59 #include <dev/usb/usb_process.h> 60 61 #include <dev/usb/net/usb_ethernet.h> 62 #include <dev/usb/net/if_axgereg.h> 63 64 /* 65 * Various supported device vendors/products. 66 */ 67 68 static const STRUCT_USB_HOST_ID axge_devs[] = { 69 #define AXGE_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 70 AXGE_DEV(ASIX, AX88178A), 71 AXGE_DEV(ASIX, AX88179), 72 AXGE_DEV(DLINK, DUB1312), 73 AXGE_DEV(LENOVO, GIGALAN), 74 AXGE_DEV(SITECOMEU, LN032), 75 #undef AXGE_DEV 76 }; 77 78 static const struct { 79 uint8_t ctrl; 80 uint8_t timer_l; 81 uint8_t timer_h; 82 uint8_t size; 83 uint8_t ifg; 84 } __packed axge_bulk_size[] = { 85 { 7, 0x4f, 0x00, 0x12, 0xff }, 86 { 7, 0x20, 0x03, 0x16, 0xff }, 87 { 7, 0xae, 0x07, 0x18, 0xff }, 88 { 7, 0xcc, 0x4c, 0x18, 0x08 } 89 }; 90 91 /* prototypes */ 92 93 static device_probe_t axge_probe; 94 static device_attach_t axge_attach; 95 static device_detach_t axge_detach; 96 97 static usb_callback_t axge_bulk_read_callback; 98 static usb_callback_t axge_bulk_write_callback; 99 100 static miibus_readreg_t axge_miibus_readreg; 101 static miibus_writereg_t axge_miibus_writereg; 102 static miibus_statchg_t axge_miibus_statchg; 103 104 static uether_fn_t axge_attach_post; 105 static uether_fn_t axge_init; 106 static uether_fn_t axge_stop; 107 static uether_fn_t axge_start; 108 static uether_fn_t axge_tick; 109 static uether_fn_t axge_rxfilter; 110 111 static int axge_read_mem(struct axge_softc *, uint8_t, uint16_t, 112 uint16_t, void *, int); 113 static void axge_write_mem(struct axge_softc *, uint8_t, uint16_t, 114 uint16_t, void *, int); 115 static uint8_t axge_read_cmd_1(struct axge_softc *, uint8_t, uint16_t); 116 static uint16_t axge_read_cmd_2(struct axge_softc *, uint8_t, uint16_t, 117 uint16_t); 118 static void axge_write_cmd_1(struct axge_softc *, uint8_t, uint16_t, 119 uint8_t); 120 static void axge_write_cmd_2(struct axge_softc *, uint8_t, uint16_t, 121 uint16_t, uint16_t); 122 static void axge_chip_init(struct axge_softc *); 123 static void axge_reset(struct axge_softc *); 124 125 static int axge_attach_post_sub(struct usb_ether *); 126 static int axge_ifmedia_upd(struct ifnet *); 127 static void axge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 128 static int axge_ioctl(struct ifnet *, u_long, caddr_t); 129 static void axge_rx_frame(struct usb_ether *, struct usb_page_cache *, int); 130 static void axge_rxeof(struct usb_ether *, struct usb_page_cache *, 131 unsigned int, unsigned int, uint32_t); 132 static void axge_csum_cfg(struct usb_ether *); 133 134 #define AXGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 135 136 #ifdef USB_DEBUG 137 static int axge_debug = 0; 138 139 static SYSCTL_NODE(_hw_usb, OID_AUTO, axge, CTLFLAG_RW, 0, "USB axge"); 140 SYSCTL_INT(_hw_usb_axge, OID_AUTO, debug, CTLFLAG_RWTUN, &axge_debug, 0, 141 "Debug level"); 142 #endif 143 144 static const struct usb_config axge_config[AXGE_N_TRANSFER] = { 145 [AXGE_BULK_DT_WR] = { 146 .type = UE_BULK, 147 .endpoint = UE_ADDR_ANY, 148 .direction = UE_DIR_OUT, 149 .frames = AXGE_N_FRAMES, 150 .bufsize = AXGE_N_FRAMES * MCLBYTES, 151 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 152 .callback = axge_bulk_write_callback, 153 .timeout = 10000, /* 10 seconds */ 154 }, 155 [AXGE_BULK_DT_RD] = { 156 .type = UE_BULK, 157 .endpoint = UE_ADDR_ANY, 158 .direction = UE_DIR_IN, 159 .bufsize = 65536, 160 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 161 .callback = axge_bulk_read_callback, 162 .timeout = 0, /* no timeout */ 163 }, 164 }; 165 166 static device_method_t axge_methods[] = { 167 /* Device interface. */ 168 DEVMETHOD(device_probe, axge_probe), 169 DEVMETHOD(device_attach, axge_attach), 170 DEVMETHOD(device_detach, axge_detach), 171 172 /* MII interface. */ 173 DEVMETHOD(miibus_readreg, axge_miibus_readreg), 174 DEVMETHOD(miibus_writereg, axge_miibus_writereg), 175 DEVMETHOD(miibus_statchg, axge_miibus_statchg), 176 177 DEVMETHOD_END 178 }; 179 180 static driver_t axge_driver = { 181 .name = "axge", 182 .methods = axge_methods, 183 .size = sizeof(struct axge_softc), 184 }; 185 186 static devclass_t axge_devclass; 187 188 DRIVER_MODULE(axge, uhub, axge_driver, axge_devclass, NULL, NULL); 189 DRIVER_MODULE(miibus, axge, miibus_driver, miibus_devclass, NULL, NULL); 190 MODULE_DEPEND(axge, uether, 1, 1, 1); 191 MODULE_DEPEND(axge, usb, 1, 1, 1); 192 MODULE_DEPEND(axge, ether, 1, 1, 1); 193 MODULE_DEPEND(axge, miibus, 1, 1, 1); 194 MODULE_VERSION(axge, 1); 195 USB_PNP_HOST_INFO(axge_devs); 196 197 static const struct usb_ether_methods axge_ue_methods = { 198 .ue_attach_post = axge_attach_post, 199 .ue_attach_post_sub = axge_attach_post_sub, 200 .ue_start = axge_start, 201 .ue_init = axge_init, 202 .ue_stop = axge_stop, 203 .ue_tick = axge_tick, 204 .ue_setmulti = axge_rxfilter, 205 .ue_setpromisc = axge_rxfilter, 206 .ue_mii_upd = axge_ifmedia_upd, 207 .ue_mii_sts = axge_ifmedia_sts, 208 }; 209 210 static int 211 axge_read_mem(struct axge_softc *sc, uint8_t cmd, uint16_t index, 212 uint16_t val, void *buf, int len) 213 { 214 struct usb_device_request req; 215 216 AXGE_LOCK_ASSERT(sc, MA_OWNED); 217 218 req.bmRequestType = UT_READ_VENDOR_DEVICE; 219 req.bRequest = cmd; 220 USETW(req.wValue, val); 221 USETW(req.wIndex, index); 222 USETW(req.wLength, len); 223 224 return (uether_do_request(&sc->sc_ue, &req, buf, 1000)); 225 } 226 227 static void 228 axge_write_mem(struct axge_softc *sc, uint8_t cmd, uint16_t index, 229 uint16_t val, void *buf, int len) 230 { 231 struct usb_device_request req; 232 233 AXGE_LOCK_ASSERT(sc, MA_OWNED); 234 235 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 236 req.bRequest = cmd; 237 USETW(req.wValue, val); 238 USETW(req.wIndex, index); 239 USETW(req.wLength, len); 240 241 if (uether_do_request(&sc->sc_ue, &req, buf, 1000)) { 242 /* Error ignored. */ 243 } 244 } 245 246 static uint8_t 247 axge_read_cmd_1(struct axge_softc *sc, uint8_t cmd, uint16_t reg) 248 { 249 uint8_t val; 250 251 axge_read_mem(sc, cmd, 1, reg, &val, 1); 252 return (val); 253 } 254 255 static uint16_t 256 axge_read_cmd_2(struct axge_softc *sc, uint8_t cmd, uint16_t index, 257 uint16_t reg) 258 { 259 uint8_t val[2]; 260 261 axge_read_mem(sc, cmd, index, reg, &val, 2); 262 return (UGETW(val)); 263 } 264 265 static void 266 axge_write_cmd_1(struct axge_softc *sc, uint8_t cmd, uint16_t reg, uint8_t val) 267 { 268 axge_write_mem(sc, cmd, 1, reg, &val, 1); 269 } 270 271 static void 272 axge_write_cmd_2(struct axge_softc *sc, uint8_t cmd, uint16_t index, 273 uint16_t reg, uint16_t val) 274 { 275 uint8_t temp[2]; 276 277 USETW(temp, val); 278 axge_write_mem(sc, cmd, index, reg, &temp, 2); 279 } 280 281 static int 282 axge_miibus_readreg(device_t dev, int phy, int reg) 283 { 284 struct axge_softc *sc; 285 uint16_t val; 286 int locked; 287 288 sc = device_get_softc(dev); 289 locked = mtx_owned(&sc->sc_mtx); 290 if (!locked) 291 AXGE_LOCK(sc); 292 293 val = axge_read_cmd_2(sc, AXGE_ACCESS_PHY, reg, phy); 294 295 if (!locked) 296 AXGE_UNLOCK(sc); 297 298 return (val); 299 } 300 301 static int 302 axge_miibus_writereg(device_t dev, int phy, int reg, int val) 303 { 304 struct axge_softc *sc; 305 int locked; 306 307 sc = device_get_softc(dev); 308 locked = mtx_owned(&sc->sc_mtx); 309 if (!locked) 310 AXGE_LOCK(sc); 311 312 axge_write_cmd_2(sc, AXGE_ACCESS_PHY, reg, phy, val); 313 314 if (!locked) 315 AXGE_UNLOCK(sc); 316 317 return (0); 318 } 319 320 static void 321 axge_miibus_statchg(device_t dev) 322 { 323 struct axge_softc *sc; 324 struct mii_data *mii; 325 struct ifnet *ifp; 326 uint8_t link_status, tmp[5]; 327 uint16_t val; 328 int locked; 329 330 sc = device_get_softc(dev); 331 mii = GET_MII(sc); 332 locked = mtx_owned(&sc->sc_mtx); 333 if (!locked) 334 AXGE_LOCK(sc); 335 336 ifp = uether_getifp(&sc->sc_ue); 337 if (mii == NULL || ifp == NULL || 338 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 339 goto done; 340 341 sc->sc_flags &= ~AXGE_FLAG_LINK; 342 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 343 (IFM_ACTIVE | IFM_AVALID)) { 344 switch (IFM_SUBTYPE(mii->mii_media_active)) { 345 case IFM_10_T: 346 case IFM_100_TX: 347 case IFM_1000_T: 348 sc->sc_flags |= AXGE_FLAG_LINK; 349 break; 350 default: 351 break; 352 } 353 } 354 355 /* Lost link, do nothing. */ 356 if ((sc->sc_flags & AXGE_FLAG_LINK) == 0) 357 goto done; 358 359 link_status = axge_read_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PLSR); 360 361 val = 0; 362 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 363 val |= MSR_FD; 364 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 365 val |= MSR_TFC; 366 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 367 val |= MSR_RFC; 368 } 369 val |= MSR_RE; 370 switch (IFM_SUBTYPE(mii->mii_media_active)) { 371 case IFM_1000_T: 372 val |= MSR_GM | MSR_EN_125MHZ; 373 if (link_status & PLSR_USB_SS) 374 memcpy(tmp, &axge_bulk_size[0], 5); 375 else if (link_status & PLSR_USB_HS) 376 memcpy(tmp, &axge_bulk_size[1], 5); 377 else 378 memcpy(tmp, &axge_bulk_size[3], 5); 379 break; 380 case IFM_100_TX: 381 val |= MSR_PS; 382 if (link_status & (PLSR_USB_SS | PLSR_USB_HS)) 383 memcpy(tmp, &axge_bulk_size[2], 5); 384 else 385 memcpy(tmp, &axge_bulk_size[3], 5); 386 break; 387 case IFM_10_T: 388 memcpy(tmp, &axge_bulk_size[3], 5); 389 break; 390 } 391 /* Rx bulk configuration. */ 392 axge_write_mem(sc, AXGE_ACCESS_MAC, 5, AXGE_RX_BULKIN_QCTRL, tmp, 5); 393 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR, val); 394 done: 395 if (!locked) 396 AXGE_UNLOCK(sc); 397 } 398 399 static void 400 axge_chip_init(struct axge_softc *sc) 401 { 402 /* Power up ethernet PHY. */ 403 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR, 0); 404 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR, EPPRCR_IPRL); 405 uether_pause(&sc->sc_ue, hz / 4); 406 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CLK_SELECT, 407 AXGE_CLK_SELECT_ACS | AXGE_CLK_SELECT_BCS); 408 uether_pause(&sc->sc_ue, hz / 10); 409 } 410 411 static void 412 axge_reset(struct axge_softc *sc) 413 { 414 struct usb_config_descriptor *cd; 415 usb_error_t err; 416 417 cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev); 418 419 err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx, 420 cd->bConfigurationValue); 421 if (err) 422 DPRINTF("reset failed (ignored)\n"); 423 424 /* Wait a little while for the chip to get its brains in order. */ 425 uether_pause(&sc->sc_ue, hz / 100); 426 427 /* Reinitialize controller to achieve full reset. */ 428 axge_chip_init(sc); 429 } 430 431 static void 432 axge_attach_post(struct usb_ether *ue) 433 { 434 struct axge_softc *sc; 435 436 sc = uether_getsc(ue); 437 438 /* Initialize controller and get station address. */ 439 axge_chip_init(sc); 440 axge_read_mem(sc, AXGE_ACCESS_MAC, ETHER_ADDR_LEN, AXGE_NIDR, 441 ue->ue_eaddr, ETHER_ADDR_LEN); 442 } 443 444 static int 445 axge_attach_post_sub(struct usb_ether *ue) 446 { 447 struct axge_softc *sc; 448 struct ifnet *ifp; 449 int error; 450 451 sc = uether_getsc(ue); 452 ifp = ue->ue_ifp; 453 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 454 ifp->if_start = uether_start; 455 ifp->if_ioctl = axge_ioctl; 456 ifp->if_init = uether_init; 457 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 458 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 459 IFQ_SET_READY(&ifp->if_snd); 460 461 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_TXCSUM | IFCAP_RXCSUM; 462 ifp->if_hwassist = AXGE_CSUM_FEATURES; 463 ifp->if_capenable = ifp->if_capabilities; 464 465 mtx_lock(&Giant); 466 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp, 467 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts, 468 BMSR_DEFCAPMASK, AXGE_PHY_ADDR, MII_OFFSET_ANY, MIIF_DOPAUSE); 469 mtx_unlock(&Giant); 470 471 return (error); 472 } 473 474 /* 475 * Set media options. 476 */ 477 static int 478 axge_ifmedia_upd(struct ifnet *ifp) 479 { 480 struct axge_softc *sc; 481 struct mii_data *mii; 482 struct mii_softc *miisc; 483 int error; 484 485 sc = ifp->if_softc; 486 mii = GET_MII(sc); 487 AXGE_LOCK_ASSERT(sc, MA_OWNED); 488 489 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 490 PHY_RESET(miisc); 491 error = mii_mediachg(mii); 492 493 return (error); 494 } 495 496 /* 497 * Report current media status. 498 */ 499 static void 500 axge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 501 { 502 struct axge_softc *sc; 503 struct mii_data *mii; 504 505 sc = ifp->if_softc; 506 mii = GET_MII(sc); 507 AXGE_LOCK(sc); 508 mii_pollstat(mii); 509 ifmr->ifm_active = mii->mii_media_active; 510 ifmr->ifm_status = mii->mii_media_status; 511 AXGE_UNLOCK(sc); 512 } 513 514 /* 515 * Probe for a AX88179 chip. 516 */ 517 static int 518 axge_probe(device_t dev) 519 { 520 struct usb_attach_arg *uaa; 521 522 uaa = device_get_ivars(dev); 523 if (uaa->usb_mode != USB_MODE_HOST) 524 return (ENXIO); 525 if (uaa->info.bConfigIndex != AXGE_CONFIG_IDX) 526 return (ENXIO); 527 if (uaa->info.bIfaceIndex != AXGE_IFACE_IDX) 528 return (ENXIO); 529 530 return (usbd_lookup_id_by_uaa(axge_devs, sizeof(axge_devs), uaa)); 531 } 532 533 /* 534 * Attach the interface. Allocate softc structures, do ifmedia 535 * setup and ethernet/BPF attach. 536 */ 537 static int 538 axge_attach(device_t dev) 539 { 540 struct usb_attach_arg *uaa; 541 struct axge_softc *sc; 542 struct usb_ether *ue; 543 uint8_t iface_index; 544 int error; 545 546 uaa = device_get_ivars(dev); 547 sc = device_get_softc(dev); 548 ue = &sc->sc_ue; 549 550 device_set_usb_desc(dev); 551 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 552 553 iface_index = AXGE_IFACE_IDX; 554 error = usbd_transfer_setup(uaa->device, &iface_index, 555 sc->sc_xfer, axge_config, AXGE_N_TRANSFER, sc, &sc->sc_mtx); 556 if (error) { 557 device_printf(dev, "allocating USB transfers failed\n"); 558 mtx_destroy(&sc->sc_mtx); 559 return (ENXIO); 560 } 561 562 ue->ue_sc = sc; 563 ue->ue_dev = dev; 564 ue->ue_udev = uaa->device; 565 ue->ue_mtx = &sc->sc_mtx; 566 ue->ue_methods = &axge_ue_methods; 567 568 error = uether_ifattach(ue); 569 if (error) { 570 device_printf(dev, "could not attach interface\n"); 571 goto detach; 572 } 573 return (0); /* success */ 574 575 detach: 576 axge_detach(dev); 577 return (ENXIO); /* failure */ 578 } 579 580 static int 581 axge_detach(device_t dev) 582 { 583 struct axge_softc *sc; 584 struct usb_ether *ue; 585 uint16_t val; 586 587 sc = device_get_softc(dev); 588 ue = &sc->sc_ue; 589 if (device_is_attached(dev)) { 590 591 /* wait for any post attach or other command to complete */ 592 usb_proc_drain(&ue->ue_tq); 593 594 AXGE_LOCK(sc); 595 /* 596 * XXX 597 * ether_ifdetach(9) should be called first. 598 */ 599 axge_stop(ue); 600 /* Force bulk-in to return a zero-length USB packet. */ 601 val = axge_read_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR); 602 val |= EPPRCR_BZ | EPPRCR_IPRL; 603 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR, val); 604 /* Change clock. */ 605 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CLK_SELECT, 0); 606 /* Disable MAC. */ 607 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, 0); 608 AXGE_UNLOCK(sc); 609 } 610 usbd_transfer_unsetup(sc->sc_xfer, AXGE_N_TRANSFER); 611 uether_ifdetach(ue); 612 mtx_destroy(&sc->sc_mtx); 613 614 return (0); 615 } 616 617 static void 618 axge_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 619 { 620 struct axge_softc *sc; 621 struct usb_ether *ue; 622 struct usb_page_cache *pc; 623 int actlen; 624 625 sc = usbd_xfer_softc(xfer); 626 ue = &sc->sc_ue; 627 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 628 629 switch (USB_GET_STATE(xfer)) { 630 case USB_ST_TRANSFERRED: 631 pc = usbd_xfer_get_frame(xfer, 0); 632 axge_rx_frame(ue, pc, actlen); 633 634 /* FALLTHROUGH */ 635 case USB_ST_SETUP: 636 tr_setup: 637 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 638 usbd_transfer_submit(xfer); 639 uether_rxflush(ue); 640 break; 641 642 default: 643 if (error != USB_ERR_CANCELLED) { 644 usbd_xfer_set_stall(xfer); 645 goto tr_setup; 646 } 647 break; 648 } 649 } 650 651 static void 652 axge_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 653 { 654 struct axge_softc *sc; 655 struct ifnet *ifp; 656 struct usb_page_cache *pc; 657 struct mbuf *m; 658 struct axge_frame_txhdr txhdr; 659 int nframes, pos; 660 661 sc = usbd_xfer_softc(xfer); 662 ifp = uether_getifp(&sc->sc_ue); 663 664 switch (USB_GET_STATE(xfer)) { 665 case USB_ST_TRANSFERRED: 666 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 667 /* FALLTHROUGH */ 668 case USB_ST_SETUP: 669 tr_setup: 670 if ((sc->sc_flags & AXGE_FLAG_LINK) == 0 || 671 (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) { 672 /* 673 * Don't send anything if there is no link or 674 * controller is busy. 675 */ 676 return; 677 } 678 679 for (nframes = 0; nframes < AXGE_N_FRAMES && 680 !IFQ_DRV_IS_EMPTY(&ifp->if_snd); nframes++) { 681 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 682 if (m == NULL) 683 break; 684 usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES, 685 nframes); 686 pc = usbd_xfer_get_frame(xfer, nframes); 687 txhdr.mss = 0; 688 txhdr.len = htole32(AXGE_TXBYTES(m->m_pkthdr.len)); 689 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0 && 690 (m->m_pkthdr.csum_flags & AXGE_CSUM_FEATURES) == 0) 691 txhdr.len |= htole32(AXGE_CSUM_DISABLE); 692 693 pos = 0; 694 usbd_copy_in(pc, pos, &txhdr, sizeof(txhdr)); 695 pos += sizeof(txhdr); 696 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len); 697 pos += m->m_pkthdr.len; 698 699 /* 700 * if there's a BPF listener, bounce a copy 701 * of this frame to him: 702 */ 703 BPF_MTAP(ifp, m); 704 705 m_freem(m); 706 707 /* Set frame length. */ 708 usbd_xfer_set_frame_len(xfer, nframes, pos); 709 } 710 if (nframes != 0) { 711 /* 712 * XXX 713 * Update TX packet counter here. This is not 714 * correct way but it seems that there is no way 715 * to know how many packets are sent at the end 716 * of transfer because controller combines 717 * multiple writes into single one if there is 718 * room in TX buffer of controller. 719 */ 720 if_inc_counter(ifp, IFCOUNTER_OPACKETS, nframes); 721 usbd_xfer_set_frames(xfer, nframes); 722 usbd_transfer_submit(xfer); 723 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 724 } 725 return; 726 /* NOTREACHED */ 727 default: 728 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 729 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 730 731 if (error != USB_ERR_CANCELLED) { 732 usbd_xfer_set_stall(xfer); 733 goto tr_setup; 734 } 735 return; 736 737 } 738 } 739 740 static void 741 axge_tick(struct usb_ether *ue) 742 { 743 struct axge_softc *sc; 744 struct mii_data *mii; 745 746 sc = uether_getsc(ue); 747 mii = GET_MII(sc); 748 AXGE_LOCK_ASSERT(sc, MA_OWNED); 749 750 mii_tick(mii); 751 } 752 753 static void 754 axge_rxfilter(struct usb_ether *ue) 755 { 756 struct axge_softc *sc; 757 struct ifnet *ifp; 758 struct ifmultiaddr *ifma; 759 uint32_t h; 760 uint16_t rxmode; 761 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 762 763 sc = uether_getsc(ue); 764 ifp = uether_getifp(ue); 765 h = 0; 766 AXGE_LOCK_ASSERT(sc, MA_OWNED); 767 768 /* 769 * Configure RX settings. 770 * Don't set RCR_IPE(IP header alignment on 32bit boundary) to disable 771 * inserting extra padding bytes. This wastes ethernet to USB host 772 * bandwidth as well as complicating RX handling logic. Current USB 773 * framework requires copying RX frames to mbufs so there is no need 774 * to worry about alignment. 775 */ 776 rxmode = RCR_DROP_CRCERR | RCR_START; 777 if (ifp->if_flags & IFF_BROADCAST) 778 rxmode |= RCR_ACPT_BCAST; 779 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 780 if (ifp->if_flags & IFF_PROMISC) 781 rxmode |= RCR_PROMISC; 782 rxmode |= RCR_ACPT_ALL_MCAST; 783 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, rxmode); 784 return; 785 } 786 787 rxmode |= RCR_ACPT_MCAST; 788 if_maddr_rlock(ifp); 789 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 790 if (ifma->ifma_addr->sa_family != AF_LINK) 791 continue; 792 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 793 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 794 hashtbl[h / 8] |= 1 << (h % 8); 795 } 796 if_maddr_runlock(ifp); 797 798 axge_write_mem(sc, AXGE_ACCESS_MAC, 8, AXGE_MFA, (void *)&hashtbl, 8); 799 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, rxmode); 800 } 801 802 static void 803 axge_start(struct usb_ether *ue) 804 { 805 struct axge_softc *sc; 806 807 sc = uether_getsc(ue); 808 /* 809 * Start the USB transfers, if not already started. 810 */ 811 usbd_transfer_start(sc->sc_xfer[AXGE_BULK_DT_RD]); 812 usbd_transfer_start(sc->sc_xfer[AXGE_BULK_DT_WR]); 813 } 814 815 static void 816 axge_init(struct usb_ether *ue) 817 { 818 struct axge_softc *sc; 819 struct ifnet *ifp; 820 821 sc = uether_getsc(ue); 822 ifp = uether_getifp(ue); 823 AXGE_LOCK_ASSERT(sc, MA_OWNED); 824 825 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 826 return; 827 828 /* 829 * Cancel pending I/O and free all RX/TX buffers. 830 */ 831 axge_stop(ue); 832 833 axge_reset(sc); 834 835 /* Set MAC address. */ 836 axge_write_mem(sc, AXGE_ACCESS_MAC, ETHER_ADDR_LEN, AXGE_NIDR, 837 IF_LLADDR(ifp), ETHER_ADDR_LEN); 838 839 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PWLLR, 0x34); 840 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PWLHR, 0x52); 841 842 /* Configure TX/RX checksum offloading. */ 843 axge_csum_cfg(ue); 844 845 /* Configure RX filters. */ 846 axge_rxfilter(ue); 847 848 /* 849 * XXX 850 * Controller supports wakeup on link change detection, 851 * magic packet and wakeup frame recpetion. But it seems 852 * there is no framework for USB ethernet suspend/wakeup. 853 * Disable all wakeup functions. 854 */ 855 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_MMSR, 0); 856 (void)axge_read_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_MMSR); 857 858 /* Configure default medium type. */ 859 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR, MSR_GM | MSR_FD | 860 MSR_RFC | MSR_TFC | MSR_RE); 861 862 usbd_xfer_set_stall(sc->sc_xfer[AXGE_BULK_DT_WR]); 863 864 ifp->if_drv_flags |= IFF_DRV_RUNNING; 865 /* Switch to selected media. */ 866 axge_ifmedia_upd(ifp); 867 } 868 869 static void 870 axge_stop(struct usb_ether *ue) 871 { 872 struct axge_softc *sc; 873 struct ifnet *ifp; 874 uint16_t val; 875 876 sc = uether_getsc(ue); 877 ifp = uether_getifp(ue); 878 879 AXGE_LOCK_ASSERT(sc, MA_OWNED); 880 881 val = axge_read_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR); 882 val &= ~MSR_RE; 883 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR, val); 884 885 if (ifp != NULL) 886 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 887 sc->sc_flags &= ~AXGE_FLAG_LINK; 888 889 /* 890 * Stop all the transfers, if not already stopped: 891 */ 892 usbd_transfer_stop(sc->sc_xfer[AXGE_BULK_DT_WR]); 893 usbd_transfer_stop(sc->sc_xfer[AXGE_BULK_DT_RD]); 894 } 895 896 static int 897 axge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 898 { 899 struct usb_ether *ue; 900 struct axge_softc *sc; 901 struct ifreq *ifr; 902 int error, mask, reinit; 903 904 ue = ifp->if_softc; 905 sc = uether_getsc(ue); 906 ifr = (struct ifreq *)data; 907 error = 0; 908 reinit = 0; 909 if (cmd == SIOCSIFCAP) { 910 AXGE_LOCK(sc); 911 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 912 if ((mask & IFCAP_TXCSUM) != 0 && 913 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 914 ifp->if_capenable ^= IFCAP_TXCSUM; 915 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 916 ifp->if_hwassist |= AXGE_CSUM_FEATURES; 917 else 918 ifp->if_hwassist &= ~AXGE_CSUM_FEATURES; 919 reinit++; 920 } 921 if ((mask & IFCAP_RXCSUM) != 0 && 922 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 923 ifp->if_capenable ^= IFCAP_RXCSUM; 924 reinit++; 925 } 926 if (reinit > 0 && ifp->if_drv_flags & IFF_DRV_RUNNING) 927 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 928 else 929 reinit = 0; 930 AXGE_UNLOCK(sc); 931 if (reinit > 0) 932 uether_init(ue); 933 } else 934 error = uether_ioctl(ifp, cmd, data); 935 936 return (error); 937 } 938 939 static void 940 axge_rx_frame(struct usb_ether *ue, struct usb_page_cache *pc, int actlen) 941 { 942 struct axge_frame_rxhdr pkt_hdr; 943 uint32_t rxhdr; 944 uint32_t pos; 945 uint32_t pkt_cnt, pkt_end; 946 uint32_t hdr_off; 947 uint32_t pktlen; 948 949 /* verify we have enough data */ 950 if (actlen < (int)sizeof(rxhdr)) 951 return; 952 953 pos = 0; 954 955 usbd_copy_out(pc, actlen - sizeof(rxhdr), &rxhdr, sizeof(rxhdr)); 956 rxhdr = le32toh(rxhdr); 957 958 pkt_cnt = rxhdr & 0xFFFF; 959 hdr_off = pkt_end = (rxhdr >> 16) & 0xFFFF; 960 961 /* 962 * <----------------------- actlen ------------------------> 963 * [frame #0]...[frame #N][pkt_hdr #0]...[pkt_hdr #N][rxhdr] 964 * Each RX frame would be aligned on 8 bytes boundary. If 965 * RCR_IPE bit is set in AXGE_RCR register, there would be 2 966 * padding bytes and 6 dummy bytes(as the padding also should 967 * be aligned on 8 bytes boundary) for each RX frame to align 968 * IP header on 32bits boundary. Driver don't set RCR_IPE bit 969 * of AXGE_RCR register, so there should be no padding bytes 970 * which simplifies RX logic a lot. 971 */ 972 while (pkt_cnt--) { 973 /* verify the header offset */ 974 if ((int)(hdr_off + sizeof(pkt_hdr)) > actlen) { 975 DPRINTF("End of packet headers\n"); 976 break; 977 } 978 usbd_copy_out(pc, hdr_off, &pkt_hdr, sizeof(pkt_hdr)); 979 pkt_hdr.status = le32toh(pkt_hdr.status); 980 pktlen = AXGE_RXBYTES(pkt_hdr.status); 981 if (pos + pktlen > pkt_end) { 982 DPRINTF("Data position reached end\n"); 983 break; 984 } 985 986 if (AXGE_RX_ERR(pkt_hdr.status) != 0) { 987 DPRINTF("Dropped a packet\n"); 988 if_inc_counter(ue->ue_ifp, IFCOUNTER_IERRORS, 1); 989 } else 990 axge_rxeof(ue, pc, pos, pktlen, pkt_hdr.status); 991 pos += (pktlen + 7) & ~7; 992 hdr_off += sizeof(pkt_hdr); 993 } 994 } 995 996 static void 997 axge_rxeof(struct usb_ether *ue, struct usb_page_cache *pc, unsigned int offset, 998 unsigned int len, uint32_t status) 999 { 1000 struct ifnet *ifp; 1001 struct mbuf *m; 1002 1003 ifp = ue->ue_ifp; 1004 if (len < ETHER_HDR_LEN || len > MCLBYTES - ETHER_ALIGN) { 1005 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1006 return; 1007 } 1008 1009 if (len > MHLEN - ETHER_ALIGN) 1010 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1011 else 1012 m = m_gethdr(M_NOWAIT, MT_DATA); 1013 if (m == NULL) { 1014 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1015 return; 1016 } 1017 m->m_pkthdr.rcvif = ifp; 1018 m->m_len = m->m_pkthdr.len = len; 1019 m->m_data += ETHER_ALIGN; 1020 1021 usbd_copy_out(pc, offset, mtod(m, uint8_t *), len); 1022 1023 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) { 1024 if ((status & AXGE_RX_L3_CSUM_ERR) == 0 && 1025 (status & AXGE_RX_L3_TYPE_MASK) == AXGE_RX_L3_TYPE_IPV4) 1026 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 1027 CSUM_IP_VALID; 1028 if ((status & AXGE_RX_L4_CSUM_ERR) == 0 && 1029 ((status & AXGE_RX_L4_TYPE_MASK) == AXGE_RX_L4_TYPE_UDP || 1030 (status & AXGE_RX_L4_TYPE_MASK) == AXGE_RX_L4_TYPE_TCP)) { 1031 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 1032 CSUM_PSEUDO_HDR; 1033 m->m_pkthdr.csum_data = 0xffff; 1034 } 1035 } 1036 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1037 1038 _IF_ENQUEUE(&ue->ue_rxq, m); 1039 } 1040 1041 static void 1042 axge_csum_cfg(struct usb_ether *ue) 1043 { 1044 struct axge_softc *sc; 1045 struct ifnet *ifp; 1046 uint8_t csum; 1047 1048 sc = uether_getsc(ue); 1049 AXGE_LOCK_ASSERT(sc, MA_OWNED); 1050 ifp = uether_getifp(ue); 1051 1052 csum = 0; 1053 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1054 csum |= CTCR_IP | CTCR_TCP | CTCR_UDP; 1055 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CTCR, csum); 1056 1057 csum = 0; 1058 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1059 csum |= CRCR_IP | CRCR_TCP | CRCR_UDP; 1060 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CRCR, csum); 1061 } 1062