1 /*- 2 * SPDX-License-Identifier: Beerware 3 * 4 * ---------------------------------------------------------------------------- 5 * "THE BEER-WARE LICENSE" (Revision 42): 6 * <phk@FreeBSD.org> wrote this file. As long as you retain this notice you 7 * can do whatever you want with this stuff. If we meet some day, and you think 8 * this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp 9 * ---------------------------------------------------------------------------- 10 * 11 * 12 * The AMD Elan sc520 is a system-on-chip gadget which is used in embedded 13 * kind of things, see www.soekris.com for instance, and it has a few quirks 14 * we need to deal with. 15 * Unfortunately we cannot identify the gadget by CPUID output because it 16 * depends on strapping options and only the stepping field may be useful 17 * and those are undocumented from AMDs side. 18 * 19 * So instead we recognize the on-chip host-PCI bridge and call back from 20 * sys/i386/pci/pci_bus.c to here if we find it. 21 * 22 * #ifdef CPU_ELAN_PPS 23 * The Elan has three general purpose counters, and when two of these 24 * are used just right they can hardware timestamp external events with 25 * approx 125 nsec resolution and +/- 125 nsec precision. 26 * 27 * Connect the signal to TMR1IN and a GPIO pin, and configure the GPIO pin 28 * with a 'P' in sysctl machdep.elan_gpio_config. 29 * 30 * The rising edge of the signal will start timer 1 counting up from 31 * zero, and when the timecounter polls for PPS, both counter 1 & 2 is 32 * read, as well as the GPIO bit. If a rising edge has happened, the 33 * contents of timer 1 which is how long time ago the edge happened, 34 * is subtracted from timer 2 to give us a "true time stamp". 35 * 36 * Echoing the PPS signal on any GPIO pin is supported (set it to 'e' 37 * or 'E' (inverted) in the sysctl) The echo signal should only be 38 * used as a visual indication, not for calibration since it suffers 39 * from 1/hz (or more) jitter which the timestamps are compensated for. 40 * #endif CPU_ELAN_PPS 41 */ 42 43 #include <sys/cdefs.h> 44 __FBSDID("$FreeBSD$"); 45 46 #include "opt_cpu.h" 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/conf.h> 51 #include <sys/eventhandler.h> 52 #include <sys/sysctl.h> 53 #include <sys/syslog.h> 54 #include <sys/timetc.h> 55 #include <sys/proc.h> 56 #include <sys/uio.h> 57 #include <sys/lock.h> 58 #include <sys/mutex.h> 59 #include <sys/malloc.h> 60 #include <sys/sysctl.h> 61 #include <sys/timepps.h> 62 #include <sys/watchdog.h> 63 64 #include <dev/led/led.h> 65 #include <machine/md_var.h> 66 #include <machine/elan_mmcr.h> 67 #include <machine/pc/bios.h> 68 69 #include <vm/vm.h> 70 #include <vm/pmap.h> 71 72 static char gpio_config[33]; 73 74 static volatile uint16_t *mmcrptr; 75 volatile struct elan_mmcr *elan_mmcr; 76 77 #ifdef CPU_ELAN_PPS 78 static struct pps_state elan_pps; 79 static volatile uint16_t *pps_ap[3]; 80 static u_int pps_a, pps_d; 81 static u_int echo_a, echo_d; 82 #endif /* CPU_ELAN_PPS */ 83 84 #ifdef CPU_SOEKRIS 85 86 static struct bios_oem bios_soekris = { 87 { 0xf0000, 0xf1000 }, 88 { 89 { "Soekris", 0, 8 }, /* Soekris Engineering. */ 90 { "net4", 0, 8 }, /* net45xx */ 91 { "comBIOS", 0, 54 }, /* comBIOS ver. 1.26a 20040819 ... */ 92 { NULL, 0, 0 }, 93 } 94 }; 95 96 #endif 97 98 static u_int led_cookie[32]; 99 static struct cdev *led_dev[32]; 100 101 static void 102 gpio_led(void *cookie, int state) 103 { 104 u_int u, v; 105 106 u = *(int *)cookie; 107 v = u & 0xffff; 108 u >>= 16; 109 if (!state) 110 v ^= 0xc; 111 mmcrptr[v / 2] = u; 112 } 113 114 static int 115 sysctl_machdep_elan_gpio_config(SYSCTL_HANDLER_ARGS) 116 { 117 u_int u, v; 118 int i, np, ne; 119 int error; 120 char buf[32]; 121 char tmp[10]; 122 123 error = SYSCTL_OUT(req, gpio_config, 33); 124 if (error != 0 || req->newptr == NULL) 125 return (error); 126 if (req->newlen != 32) 127 return (EINVAL); 128 error = SYSCTL_IN(req, buf, 32); 129 if (error != 0) 130 return (error); 131 /* Disallow any disabled pins and count pps and echo */ 132 np = ne = 0; 133 for (i = 0; i < 32; i++) { 134 if (gpio_config[i] == '-' && buf[i] == '.') 135 buf[i] = gpio_config[i]; 136 if (gpio_config[i] == '-' && buf[i] != '-') 137 return (EPERM); 138 if (buf[i] == 'P') { 139 np++; 140 if (np > 1) 141 return (EINVAL); 142 } 143 if (buf[i] == 'e' || buf[i] == 'E') { 144 ne++; 145 if (ne > 1) 146 return (EINVAL); 147 } 148 if (buf[i] != 'L' && buf[i] != 'l' 149 #ifdef CPU_ELAN_PPS 150 && buf[i] != 'P' && buf[i] != 'E' && buf[i] != 'e' 151 #endif /* CPU_ELAN_PPS */ 152 && buf[i] != '.' && buf[i] != '-') 153 return (EINVAL); 154 } 155 #ifdef CPU_ELAN_PPS 156 if (np == 0) 157 pps_a = pps_d = 0; 158 if (ne == 0) 159 echo_a = echo_d = 0; 160 #endif 161 for (i = 0; i < 32; i++) { 162 u = 1 << (i & 0xf); 163 if (i >= 16) 164 v = 2; 165 else 166 v = 0; 167 #ifdef CPU_SOEKRIS 168 if (i == 9) 169 ; 170 else 171 #endif 172 if (buf[i] != 'l' && buf[i] != 'L' && led_dev[i] != NULL) { 173 led_destroy(led_dev[i]); 174 led_dev[i] = NULL; 175 mmcrptr[(0xc2a + v) / 2] &= ~u; 176 } 177 switch (buf[i]) { 178 #ifdef CPU_ELAN_PPS 179 case 'P': 180 pps_d = u; 181 pps_a = 0xc30 + v; 182 pps_ap[0] = &mmcrptr[pps_a / 2]; 183 pps_ap[1] = &elan_mmcr->GPTMR2CNT; 184 pps_ap[2] = &elan_mmcr->GPTMR1CNT; 185 mmcrptr[(0xc2a + v) / 2] &= ~u; 186 gpio_config[i] = buf[i]; 187 break; 188 case 'e': 189 case 'E': 190 echo_d = u; 191 if (buf[i] == 'E') 192 echo_a = 0xc34 + v; 193 else 194 echo_a = 0xc38 + v; 195 mmcrptr[(0xc2a + v) / 2] |= u; 196 gpio_config[i] = buf[i]; 197 break; 198 #endif /* CPU_ELAN_PPS */ 199 case 'l': 200 case 'L': 201 if (buf[i] == 'L') 202 led_cookie[i] = (0xc34 + v) | (u << 16); 203 else 204 led_cookie[i] = (0xc38 + v) | (u << 16); 205 if (led_dev[i]) 206 break; 207 sprintf(tmp, "gpio%d", i); 208 mmcrptr[(0xc2a + v) / 2] |= u; 209 gpio_config[i] = buf[i]; 210 led_dev[i] = 211 led_create(gpio_led, &led_cookie[i], tmp); 212 break; 213 case '.': 214 gpio_config[i] = buf[i]; 215 break; 216 case '-': 217 default: 218 break; 219 } 220 } 221 return (0); 222 } 223 224 SYSCTL_OID(_machdep, OID_AUTO, elan_gpio_config, CTLTYPE_STRING | CTLFLAG_RW, 225 NULL, 0, sysctl_machdep_elan_gpio_config, "A", "Elan CPU GPIO pin config"); 226 227 #ifdef CPU_ELAN_PPS 228 static void 229 elan_poll_pps(struct timecounter *tc) 230 { 231 static int state; 232 int i; 233 uint16_t u, x, y, z; 234 register_t saveintr; 235 236 /* 237 * Grab the HW state as quickly and compactly as we can. Disable 238 * interrupts to avoid measuring our interrupt service time on 239 * hw with quality clock sources. 240 */ 241 saveintr = intr_disable(); 242 x = *pps_ap[0]; /* state, must be first, see below */ 243 y = *pps_ap[1]; /* timer2 */ 244 z = *pps_ap[2]; /* timer1 */ 245 intr_restore(saveintr); 246 247 /* 248 * Order is important here. We need to check the state of the GPIO 249 * pin first, in order to avoid reading timer 1 right before the 250 * state change. Technically pps_a may be zero in which case we 251 * harmlessly read the REVID register and the contents of pps_d is 252 * of no concern. 253 */ 254 255 i = x & pps_d; 256 257 /* If state did not change or we don't have a GPIO pin, return */ 258 if (i == state || pps_a == 0) 259 return; 260 261 state = i; 262 263 /* If the state is "low", flip the echo GPIO and return. */ 264 if (!i) { 265 if (echo_a) 266 mmcrptr[(echo_a ^ 0xc) / 2] = echo_d; 267 return; 268 } 269 270 /* 271 * Subtract timer1 from timer2 to compensate for time from the 272 * edge until we read the counters. 273 */ 274 u = y - z; 275 276 pps_capture(&elan_pps); 277 elan_pps.capcount = u; 278 pps_event(&elan_pps, PPS_CAPTUREASSERT); 279 280 /* Twiddle echo bit */ 281 if (echo_a) 282 mmcrptr[echo_a / 2] = echo_d; 283 } 284 #endif /* CPU_ELAN_PPS */ 285 286 static unsigned 287 elan_get_timecount(struct timecounter *tc) 288 { 289 290 /* Read timer2, end of story */ 291 return (elan_mmcr->GPTMR2CNT); 292 } 293 294 /* 295 * The Elan CPU can be run from a number of clock frequencies, this 296 * allows you to override the default 33.3 MHZ. 297 */ 298 #ifndef CPU_ELAN_XTAL 299 #define CPU_ELAN_XTAL 33333333 300 #endif 301 302 static struct timecounter elan_timecounter = { 303 elan_get_timecount, 304 NULL, 305 0xffff, 306 CPU_ELAN_XTAL / 4, 307 "ELAN", 308 1000 309 }; 310 311 static int 312 sysctl_machdep_elan_freq(SYSCTL_HANDLER_ARGS) 313 { 314 u_int f; 315 int error; 316 317 f = elan_timecounter.tc_frequency * 4; 318 error = sysctl_handle_int(oidp, &f, 0, req); 319 if (error == 0 && req->newptr != NULL) 320 elan_timecounter.tc_frequency = (f + 3) / 4; 321 return (error); 322 } 323 324 SYSCTL_PROC(_machdep, OID_AUTO, elan_freq, CTLTYPE_UINT | CTLFLAG_RW, 325 0, sizeof (u_int), sysctl_machdep_elan_freq, "IU", ""); 326 327 /* 328 * Positively identifying the Elan can only be done through the PCI id of 329 * the host-bridge, this function is called from i386/pci/pci_bus.c. 330 */ 331 void 332 init_AMD_Elan_sc520(void) 333 { 334 u_int new; 335 int i; 336 337 mmcrptr = pmap_mapdev(0xfffef000, 0x1000); 338 elan_mmcr = (volatile struct elan_mmcr *)mmcrptr; 339 340 /*- 341 * The i8254 is driven with a nonstandard frequency which is 342 * derived thusly: 343 * f = 32768 * 45 * 25 / 31 = 1189161.29... 344 * We use the sysctl to get the i8254 (timecounter etc) into whack. 345 */ 346 347 new = 1189161; 348 i = kernel_sysctlbyname(&thread0, "machdep.i8254_freq", 349 NULL, 0, &new, sizeof new, NULL, 0); 350 if (bootverbose || 1) 351 printf("sysctl machdep.i8254_freq=%d returns %d\n", new, i); 352 353 /* Start GP timer #2 and use it as timecounter, hz permitting */ 354 elan_mmcr->GPTMR2MAXCMPA = 0; 355 elan_mmcr->GPTMR2CTL = 0xc001; 356 357 #ifdef CPU_ELAN_PPS 358 /* Set up GP timer #1 as pps counter */ 359 elan_mmcr->CSPFS &= ~0x10; 360 elan_mmcr->GPTMR1CTL = 0x8000 | 0x4000 | 0x10 | 0x1; 361 elan_mmcr->GPTMR1MAXCMPA = 0x0; 362 elan_mmcr->GPTMR1MAXCMPB = 0x0; 363 elan_pps.ppscap |= PPS_CAPTUREASSERT; 364 pps_init(&elan_pps); 365 #endif 366 tc_init(&elan_timecounter); 367 } 368 369 static void 370 elan_watchdog(void *foo __unused, u_int spec, int *error) 371 { 372 u_int u, v, w; 373 static u_int cur; 374 375 u = spec & WD_INTERVAL; 376 if (u > 0 && u <= 35) { 377 u = imax(u - 5, 24); 378 v = 2 << (u - 24); 379 v |= 0xc000; 380 381 /* 382 * There is a bug in some silicon which prevents us from 383 * writing to the WDTMRCTL register if the GP echo mode is 384 * enabled. GP echo mode on the other hand is desirable 385 * for other reasons. Save and restore the GP echo mode 386 * around our hardware tom-foolery. 387 */ 388 w = elan_mmcr->GPECHO; 389 elan_mmcr->GPECHO = 0; 390 if (v != cur) { 391 /* Clear the ENB bit */ 392 elan_mmcr->WDTMRCTL = 0x3333; 393 elan_mmcr->WDTMRCTL = 0xcccc; 394 elan_mmcr->WDTMRCTL = 0; 395 396 /* Set new value */ 397 elan_mmcr->WDTMRCTL = 0x3333; 398 elan_mmcr->WDTMRCTL = 0xcccc; 399 elan_mmcr->WDTMRCTL = v; 400 cur = v; 401 } else { 402 /* Just reset timer */ 403 elan_mmcr->WDTMRCTL = 0xaaaa; 404 elan_mmcr->WDTMRCTL = 0x5555; 405 } 406 elan_mmcr->GPECHO = w; 407 *error = 0; 408 } else { 409 w = elan_mmcr->GPECHO; 410 elan_mmcr->GPECHO = 0; 411 elan_mmcr->WDTMRCTL = 0x3333; 412 elan_mmcr->WDTMRCTL = 0xcccc; 413 elan_mmcr->WDTMRCTL = 0x4080; 414 elan_mmcr->WDTMRCTL = w; /* XXX What does this statement do? */ 415 elan_mmcr->GPECHO = w; 416 cur = 0; 417 } 418 } 419 420 static int 421 elan_mmap(struct cdev *dev, vm_ooffset_t offset, vm_paddr_t *paddr, 422 int nprot, vm_memattr_t *memattr) 423 { 424 425 if (offset >= 0x1000) 426 return (-1); 427 *paddr = 0xfffef000; 428 return (0); 429 } 430 static int 431 elan_ioctl(struct cdev *dev, u_long cmd, caddr_t arg, int flag, struct thread *tdr) 432 { 433 int error; 434 435 error = ENOIOCTL; 436 437 #ifdef CPU_ELAN_PPS 438 if (pps_a != 0) 439 error = pps_ioctl(cmd, arg, &elan_pps); 440 /* 441 * We only want to incur the overhead of the PPS polling if we 442 * are actually asked to timestamp. 443 */ 444 if (elan_pps.ppsparam.mode & PPS_CAPTUREASSERT) { 445 elan_timecounter.tc_poll_pps = elan_poll_pps; 446 } else { 447 elan_timecounter.tc_poll_pps = NULL; 448 } 449 if (error != ENOIOCTL) 450 return (error); 451 #endif 452 453 return(error); 454 } 455 456 static struct cdevsw elan_cdevsw = { 457 .d_version = D_VERSION, 458 .d_flags = D_NEEDGIANT, 459 .d_ioctl = elan_ioctl, 460 .d_mmap = elan_mmap, 461 .d_name = "elan", 462 }; 463 464 static void 465 elan_drvinit(void) 466 { 467 468 #ifdef CPU_SOEKRIS 469 #define BIOS_OEM_MAXLEN 72 470 static u_char bios_oem[BIOS_OEM_MAXLEN] = "\0"; 471 #endif /* CPU_SOEKRIS */ 472 473 /* If no elan found, just return */ 474 if (mmcrptr == NULL) 475 return; 476 477 printf("Elan-mmcr driver: MMCR at %p.%s\n", 478 mmcrptr, 479 #ifdef CPU_ELAN_PPS 480 " PPS support." 481 #else 482 "" 483 #endif 484 ); 485 486 make_dev(&elan_cdevsw, 0, 487 UID_ROOT, GID_WHEEL, 0600, "elan-mmcr"); 488 489 #ifdef CPU_SOEKRIS 490 if ( bios_oem_strings(&bios_soekris, bios_oem, BIOS_OEM_MAXLEN) > 0 ) 491 printf("Elan-mmcr %s\n", bios_oem); 492 493 /* Create the error LED on GPIO9 */ 494 led_cookie[9] = 0x02000c34; 495 led_dev[9] = led_create(gpio_led, &led_cookie[9], "error"); 496 497 /* Disable the unavailable GPIO pins */ 498 strcpy(gpio_config, "-----....--..--------..---------"); 499 #else /* !CPU_SOEKRIS */ 500 /* We don't know which pins are available so enable them all */ 501 strcpy(gpio_config, "................................"); 502 #endif /* CPU_SOEKRIS */ 503 504 EVENTHANDLER_REGISTER(watchdog_list, elan_watchdog, NULL, 0); 505 } 506 507 SYSINIT(elan, SI_SUB_PSEUDO, SI_ORDER_MIDDLE, elan_drvinit, NULL); 508 509