1 /*- 2 * Copyright (c) 2014-2017, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/sockio.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/mutex.h> 44 #include <sys/module.h> 45 #include <sys/kobj.h> 46 #include <sys/rman.h> 47 #include <sys/sbuf.h> 48 #include <sys/smp.h> 49 #include <sys/socket.h> 50 #include <sys/sysctl.h> 51 #include <sys/syslog.h> 52 #include <sys/taskqueue.h> 53 #include <sys/limits.h> 54 55 56 #include <net/if.h> 57 #include <net/if_var.h> 58 #include <net/if_types.h> 59 #include <net/if_media.h> 60 #include <net/bpf.h> 61 #include <net/ethernet.h> 62 #include <net/mp_ring.h> 63 #include <net/vnet.h> 64 65 #include <netinet/in.h> 66 #include <netinet/in_pcb.h> 67 #include <netinet/tcp_lro.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/if_ether.h> 70 #include <netinet/ip.h> 71 #include <netinet/ip6.h> 72 #include <netinet/tcp.h> 73 #include <netinet/ip_var.h> 74 #include <netinet6/ip6_var.h> 75 76 #include <machine/bus.h> 77 #include <machine/in_cksum.h> 78 79 #include <vm/vm.h> 80 #include <vm/pmap.h> 81 82 #include <dev/led/led.h> 83 #include <dev/pci/pcireg.h> 84 #include <dev/pci/pcivar.h> 85 #include <dev/pci/pci_private.h> 86 87 #include <net/iflib.h> 88 89 #include "ifdi_if.h" 90 91 #if defined(__i386__) || defined(__amd64__) 92 #include <sys/memdesc.h> 93 #include <machine/bus.h> 94 #include <machine/md_var.h> 95 #include <machine/specialreg.h> 96 #include <x86/include/busdma_impl.h> 97 #include <x86/iommu/busdma_dmar.h> 98 #endif 99 100 #include <sys/bitstring.h> 101 /* 102 * enable accounting of every mbuf as it comes in to and goes out of 103 * iflib's software descriptor references 104 */ 105 #define MEMORY_LOGGING 0 106 /* 107 * Enable mbuf vectors for compressing long mbuf chains 108 */ 109 110 /* 111 * NB: 112 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 113 * we prefetch needs to be determined by the time spent in m_free vis a vis 114 * the cost of a prefetch. This will of course vary based on the workload: 115 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 116 * is quite expensive, thus suggesting very little prefetch. 117 * - small packet forwarding which is just returning a single mbuf to 118 * UMA will typically be very fast vis a vis the cost of a memory 119 * access. 120 */ 121 122 123 /* 124 * File organization: 125 * - private structures 126 * - iflib private utility functions 127 * - ifnet functions 128 * - vlan registry and other exported functions 129 * - iflib public core functions 130 * 131 * 132 */ 133 static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 134 135 struct iflib_txq; 136 typedef struct iflib_txq *iflib_txq_t; 137 struct iflib_rxq; 138 typedef struct iflib_rxq *iflib_rxq_t; 139 struct iflib_fl; 140 typedef struct iflib_fl *iflib_fl_t; 141 142 struct iflib_ctx; 143 144 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 145 146 typedef struct iflib_filter_info { 147 driver_filter_t *ifi_filter; 148 void *ifi_filter_arg; 149 struct grouptask *ifi_task; 150 void *ifi_ctx; 151 } *iflib_filter_info_t; 152 153 struct iflib_ctx { 154 KOBJ_FIELDS; 155 /* 156 * Pointer to hardware driver's softc 157 */ 158 void *ifc_softc; 159 device_t ifc_dev; 160 if_t ifc_ifp; 161 162 cpuset_t ifc_cpus; 163 if_shared_ctx_t ifc_sctx; 164 struct if_softc_ctx ifc_softc_ctx; 165 166 struct mtx ifc_mtx; 167 168 uint16_t ifc_nhwtxqs; 169 uint16_t ifc_nhwrxqs; 170 171 iflib_txq_t ifc_txqs; 172 iflib_rxq_t ifc_rxqs; 173 uint32_t ifc_if_flags; 174 uint32_t ifc_flags; 175 uint32_t ifc_max_fl_buf_size; 176 int ifc_in_detach; 177 178 int ifc_link_state; 179 int ifc_link_irq; 180 int ifc_watchdog_events; 181 struct cdev *ifc_led_dev; 182 struct resource *ifc_msix_mem; 183 184 struct if_irq ifc_legacy_irq; 185 struct grouptask ifc_admin_task; 186 struct grouptask ifc_vflr_task; 187 struct iflib_filter_info ifc_filter_info; 188 struct ifmedia ifc_media; 189 190 struct sysctl_oid *ifc_sysctl_node; 191 uint16_t ifc_sysctl_ntxqs; 192 uint16_t ifc_sysctl_nrxqs; 193 uint16_t ifc_sysctl_qs_eq_override; 194 uint16_t ifc_sysctl_rx_budget; 195 196 qidx_t ifc_sysctl_ntxds[8]; 197 qidx_t ifc_sysctl_nrxds[8]; 198 struct if_txrx ifc_txrx; 199 #define isc_txd_encap ifc_txrx.ift_txd_encap 200 #define isc_txd_flush ifc_txrx.ift_txd_flush 201 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 202 #define isc_rxd_available ifc_txrx.ift_rxd_available 203 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 204 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 205 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 206 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 208 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 209 eventhandler_tag ifc_vlan_attach_event; 210 eventhandler_tag ifc_vlan_detach_event; 211 uint8_t ifc_mac[ETHER_ADDR_LEN]; 212 char ifc_mtx_name[16]; 213 }; 214 215 216 void * 217 iflib_get_softc(if_ctx_t ctx) 218 { 219 220 return (ctx->ifc_softc); 221 } 222 223 device_t 224 iflib_get_dev(if_ctx_t ctx) 225 { 226 227 return (ctx->ifc_dev); 228 } 229 230 if_t 231 iflib_get_ifp(if_ctx_t ctx) 232 { 233 234 return (ctx->ifc_ifp); 235 } 236 237 struct ifmedia * 238 iflib_get_media(if_ctx_t ctx) 239 { 240 241 return (&ctx->ifc_media); 242 } 243 244 void 245 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 246 { 247 248 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN); 249 } 250 251 if_softc_ctx_t 252 iflib_get_softc_ctx(if_ctx_t ctx) 253 { 254 255 return (&ctx->ifc_softc_ctx); 256 } 257 258 if_shared_ctx_t 259 iflib_get_sctx(if_ctx_t ctx) 260 { 261 262 return (ctx->ifc_sctx); 263 } 264 265 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 266 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 267 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 268 269 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 270 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 271 272 #define RX_SW_DESC_MAP_CREATED (1 << 0) 273 #define TX_SW_DESC_MAP_CREATED (1 << 1) 274 #define RX_SW_DESC_INUSE (1 << 3) 275 #define TX_SW_DESC_MAPPED (1 << 4) 276 277 #define M_TOOBIG M_PROTO1 278 279 typedef struct iflib_sw_rx_desc_array { 280 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 281 struct mbuf **ifsd_m; /* pkthdr mbufs */ 282 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 283 uint8_t *ifsd_flags; 284 } iflib_rxsd_array_t; 285 286 typedef struct iflib_sw_tx_desc_array { 287 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 288 struct mbuf **ifsd_m; /* pkthdr mbufs */ 289 uint8_t *ifsd_flags; 290 } if_txsd_vec_t; 291 292 293 /* magic number that should be high enough for any hardware */ 294 #define IFLIB_MAX_TX_SEGS 128 295 /* bnxt supports 64 with hardware LRO enabled */ 296 #define IFLIB_MAX_RX_SEGS 64 297 #define IFLIB_RX_COPY_THRESH 128 298 #define IFLIB_MAX_RX_REFRESH 32 299 /* The minimum descriptors per second before we start coalescing */ 300 #define IFLIB_MIN_DESC_SEC 16384 301 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 302 #define IFLIB_QUEUE_IDLE 0 303 #define IFLIB_QUEUE_HUNG 1 304 #define IFLIB_QUEUE_WORKING 2 305 /* maximum number of txqs that can share an rx interrupt */ 306 #define IFLIB_MAX_TX_SHARED_INTR 4 307 308 /* this should really scale with ring size - this is a fairly arbitrary value */ 309 #define TX_BATCH_SIZE 32 310 311 #define IFLIB_RESTART_BUDGET 8 312 313 #define IFC_LEGACY 0x001 314 #define IFC_QFLUSH 0x002 315 #define IFC_MULTISEG 0x004 316 #define IFC_DMAR 0x008 317 #define IFC_SC_ALLOCATED 0x010 318 #define IFC_INIT_DONE 0x020 319 #define IFC_PREFETCH 0x040 320 #define IFC_DO_RESET 0x080 321 #define IFC_CHECK_HUNG 0x100 322 323 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 324 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 325 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 326 struct iflib_txq { 327 qidx_t ift_in_use; 328 qidx_t ift_cidx; 329 qidx_t ift_cidx_processed; 330 qidx_t ift_pidx; 331 uint8_t ift_gen; 332 uint8_t ift_br_offset; 333 uint16_t ift_npending; 334 uint16_t ift_db_pending; 335 uint16_t ift_rs_pending; 336 /* implicit pad */ 337 uint8_t ift_txd_size[8]; 338 uint64_t ift_processed; 339 uint64_t ift_cleaned; 340 uint64_t ift_cleaned_prev; 341 #if MEMORY_LOGGING 342 uint64_t ift_enqueued; 343 uint64_t ift_dequeued; 344 #endif 345 uint64_t ift_no_tx_dma_setup; 346 uint64_t ift_no_desc_avail; 347 uint64_t ift_mbuf_defrag_failed; 348 uint64_t ift_mbuf_defrag; 349 uint64_t ift_map_failed; 350 uint64_t ift_txd_encap_efbig; 351 uint64_t ift_pullups; 352 353 struct mtx ift_mtx; 354 struct mtx ift_db_mtx; 355 356 /* constant values */ 357 if_ctx_t ift_ctx; 358 struct ifmp_ring *ift_br; 359 struct grouptask ift_task; 360 qidx_t ift_size; 361 uint16_t ift_id; 362 struct callout ift_timer; 363 364 if_txsd_vec_t ift_sds; 365 uint8_t ift_qstatus; 366 uint8_t ift_closed; 367 uint8_t ift_update_freq; 368 struct iflib_filter_info ift_filter_info; 369 bus_dma_tag_t ift_desc_tag; 370 bus_dma_tag_t ift_tso_desc_tag; 371 iflib_dma_info_t ift_ifdi; 372 #define MTX_NAME_LEN 16 373 char ift_mtx_name[MTX_NAME_LEN]; 374 char ift_db_mtx_name[MTX_NAME_LEN]; 375 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 376 #ifdef IFLIB_DIAGNOSTICS 377 uint64_t ift_cpu_exec_count[256]; 378 #endif 379 } __aligned(CACHE_LINE_SIZE); 380 381 struct iflib_fl { 382 qidx_t ifl_cidx; 383 qidx_t ifl_pidx; 384 qidx_t ifl_credits; 385 uint8_t ifl_gen; 386 uint8_t ifl_rxd_size; 387 #if MEMORY_LOGGING 388 uint64_t ifl_m_enqueued; 389 uint64_t ifl_m_dequeued; 390 uint64_t ifl_cl_enqueued; 391 uint64_t ifl_cl_dequeued; 392 #endif 393 /* implicit pad */ 394 395 bitstr_t *ifl_rx_bitmap; 396 qidx_t ifl_fragidx; 397 /* constant */ 398 qidx_t ifl_size; 399 uint16_t ifl_buf_size; 400 uint16_t ifl_cltype; 401 uma_zone_t ifl_zone; 402 iflib_rxsd_array_t ifl_sds; 403 iflib_rxq_t ifl_rxq; 404 uint8_t ifl_id; 405 bus_dma_tag_t ifl_desc_tag; 406 iflib_dma_info_t ifl_ifdi; 407 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 408 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 409 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 410 } __aligned(CACHE_LINE_SIZE); 411 412 static inline qidx_t 413 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 414 { 415 qidx_t used; 416 417 if (pidx > cidx) 418 used = pidx - cidx; 419 else if (pidx < cidx) 420 used = size - cidx + pidx; 421 else if (gen == 0 && pidx == cidx) 422 used = 0; 423 else if (gen == 1 && pidx == cidx) 424 used = size; 425 else 426 panic("bad state"); 427 428 return (used); 429 } 430 431 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 432 433 #define IDXDIFF(head, tail, wrap) \ 434 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 435 436 struct iflib_rxq { 437 /* If there is a separate completion queue - 438 * these are the cq cidx and pidx. Otherwise 439 * these are unused. 440 */ 441 qidx_t ifr_size; 442 qidx_t ifr_cq_cidx; 443 qidx_t ifr_cq_pidx; 444 uint8_t ifr_cq_gen; 445 uint8_t ifr_fl_offset; 446 447 if_ctx_t ifr_ctx; 448 iflib_fl_t ifr_fl; 449 uint64_t ifr_rx_irq; 450 uint16_t ifr_id; 451 uint8_t ifr_lro_enabled; 452 uint8_t ifr_nfl; 453 uint8_t ifr_ntxqirq; 454 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 455 struct lro_ctrl ifr_lc; 456 struct grouptask ifr_task; 457 struct iflib_filter_info ifr_filter_info; 458 iflib_dma_info_t ifr_ifdi; 459 460 /* dynamically allocate if any drivers need a value substantially larger than this */ 461 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 462 #ifdef IFLIB_DIAGNOSTICS 463 uint64_t ifr_cpu_exec_count[256]; 464 #endif 465 } __aligned(CACHE_LINE_SIZE); 466 467 typedef struct if_rxsd { 468 caddr_t *ifsd_cl; 469 struct mbuf **ifsd_m; 470 iflib_fl_t ifsd_fl; 471 qidx_t ifsd_cidx; 472 } *if_rxsd_t; 473 474 /* multiple of word size */ 475 #ifdef __LP64__ 476 #define PKT_INFO_SIZE 6 477 #define RXD_INFO_SIZE 5 478 #define PKT_TYPE uint64_t 479 #else 480 #define PKT_INFO_SIZE 11 481 #define RXD_INFO_SIZE 8 482 #define PKT_TYPE uint32_t 483 #endif 484 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 485 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 486 487 typedef struct if_pkt_info_pad { 488 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 489 } *if_pkt_info_pad_t; 490 typedef struct if_rxd_info_pad { 491 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 492 } *if_rxd_info_pad_t; 493 494 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 495 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 496 497 498 static inline void 499 pkt_info_zero(if_pkt_info_t pi) 500 { 501 if_pkt_info_pad_t pi_pad; 502 503 pi_pad = (if_pkt_info_pad_t)pi; 504 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 505 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 506 #ifndef __LP64__ 507 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 508 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 509 #endif 510 } 511 512 static inline void 513 rxd_info_zero(if_rxd_info_t ri) 514 { 515 if_rxd_info_pad_t ri_pad; 516 int i; 517 518 ri_pad = (if_rxd_info_pad_t)ri; 519 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 520 ri_pad->rxd_val[i] = 0; 521 ri_pad->rxd_val[i+1] = 0; 522 ri_pad->rxd_val[i+2] = 0; 523 ri_pad->rxd_val[i+3] = 0; 524 } 525 #ifdef __LP64__ 526 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 527 #endif 528 } 529 530 /* 531 * Only allow a single packet to take up most 1/nth of the tx ring 532 */ 533 #define MAX_SINGLE_PACKET_FRACTION 12 534 #define IF_BAD_DMA (bus_addr_t)-1 535 536 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 537 538 #define CTX_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_mtx, _name, "iflib ctx lock", MTX_DEF) 539 540 #define CTX_LOCK(ctx) mtx_lock(&(ctx)->ifc_mtx) 541 #define CTX_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_mtx) 542 #define CTX_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_mtx) 543 544 545 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 546 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 547 548 549 /* Our boot-time initialization hook */ 550 static int iflib_module_event_handler(module_t, int, void *); 551 552 static moduledata_t iflib_moduledata = { 553 "iflib", 554 iflib_module_event_handler, 555 NULL 556 }; 557 558 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 559 MODULE_VERSION(iflib, 1); 560 561 MODULE_DEPEND(iflib, pci, 1, 1, 1); 562 MODULE_DEPEND(iflib, ether, 1, 1, 1); 563 564 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 565 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 566 567 #ifndef IFLIB_DEBUG_COUNTERS 568 #ifdef INVARIANTS 569 #define IFLIB_DEBUG_COUNTERS 1 570 #else 571 #define IFLIB_DEBUG_COUNTERS 0 572 #endif /* !INVARIANTS */ 573 #endif 574 575 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 576 "iflib driver parameters"); 577 578 /* 579 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 580 */ 581 static int iflib_min_tx_latency = 0; 582 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 583 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 584 static int iflib_no_tx_batch = 0; 585 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 586 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 587 588 589 #if IFLIB_DEBUG_COUNTERS 590 591 static int iflib_tx_seen; 592 static int iflib_tx_sent; 593 static int iflib_tx_encap; 594 static int iflib_rx_allocs; 595 static int iflib_fl_refills; 596 static int iflib_fl_refills_large; 597 static int iflib_tx_frees; 598 599 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 600 &iflib_tx_seen, 0, "# tx mbufs seen"); 601 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 602 &iflib_tx_sent, 0, "# tx mbufs sent"); 603 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 604 &iflib_tx_encap, 0, "# tx mbufs encapped"); 605 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 606 &iflib_tx_frees, 0, "# tx frees"); 607 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 608 &iflib_rx_allocs, 0, "# rx allocations"); 609 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 610 &iflib_fl_refills, 0, "# refills"); 611 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 612 &iflib_fl_refills_large, 0, "# large refills"); 613 614 615 static int iflib_txq_drain_flushing; 616 static int iflib_txq_drain_oactive; 617 static int iflib_txq_drain_notready; 618 static int iflib_txq_drain_encapfail; 619 620 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 621 &iflib_txq_drain_flushing, 0, "# drain flushes"); 622 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 623 &iflib_txq_drain_oactive, 0, "# drain oactives"); 624 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 625 &iflib_txq_drain_notready, 0, "# drain notready"); 626 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_encapfail, CTLFLAG_RD, 627 &iflib_txq_drain_encapfail, 0, "# drain encap fails"); 628 629 630 static int iflib_encap_load_mbuf_fail; 631 static int iflib_encap_pad_mbuf_fail; 632 static int iflib_encap_txq_avail_fail; 633 static int iflib_encap_txd_encap_fail; 634 635 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 636 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 637 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 638 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 639 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 640 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 641 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 642 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 643 644 static int iflib_task_fn_rxs; 645 static int iflib_rx_intr_enables; 646 static int iflib_fast_intrs; 647 static int iflib_intr_link; 648 static int iflib_intr_msix; 649 static int iflib_rx_unavail; 650 static int iflib_rx_ctx_inactive; 651 static int iflib_rx_zero_len; 652 static int iflib_rx_if_input; 653 static int iflib_rx_mbuf_null; 654 static int iflib_rxd_flush; 655 656 static int iflib_verbose_debug; 657 658 SYSCTL_INT(_net_iflib, OID_AUTO, intr_link, CTLFLAG_RD, 659 &iflib_intr_link, 0, "# intr link calls"); 660 SYSCTL_INT(_net_iflib, OID_AUTO, intr_msix, CTLFLAG_RD, 661 &iflib_intr_msix, 0, "# intr msix calls"); 662 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 663 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 664 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 665 &iflib_rx_intr_enables, 0, "# rx intr enables"); 666 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 667 &iflib_fast_intrs, 0, "# fast_intr calls"); 668 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 669 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 670 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 671 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 672 SYSCTL_INT(_net_iflib, OID_AUTO, rx_zero_len, CTLFLAG_RD, 673 &iflib_rx_zero_len, 0, "# times rxeof saw zero len mbuf"); 674 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 675 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 676 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD, 677 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf"); 678 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 679 &iflib_rxd_flush, 0, "# times rxd_flush called"); 680 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 681 &iflib_verbose_debug, 0, "enable verbose debugging"); 682 683 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 684 static void 685 iflib_debug_reset(void) 686 { 687 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 688 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 689 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 690 iflib_txq_drain_notready = iflib_txq_drain_encapfail = 691 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 692 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 693 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 694 iflib_intr_link = iflib_intr_msix = iflib_rx_unavail = 695 iflib_rx_ctx_inactive = iflib_rx_zero_len = iflib_rx_if_input = 696 iflib_rx_mbuf_null = iflib_rxd_flush = 0; 697 } 698 699 #else 700 #define DBG_COUNTER_INC(name) 701 static void iflib_debug_reset(void) {} 702 #endif 703 704 705 706 #define IFLIB_DEBUG 0 707 708 static void iflib_tx_structures_free(if_ctx_t ctx); 709 static void iflib_rx_structures_free(if_ctx_t ctx); 710 static int iflib_queues_alloc(if_ctx_t ctx); 711 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 712 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 713 static int iflib_qset_structures_setup(if_ctx_t ctx); 714 static int iflib_msix_init(if_ctx_t ctx); 715 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, char *str); 716 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 717 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 718 static int iflib_register(if_ctx_t); 719 static void iflib_init_locked(if_ctx_t ctx); 720 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 721 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 722 static void iflib_ifmp_purge(iflib_txq_t txq); 723 static void _iflib_pre_assert(if_softc_ctx_t scctx); 724 static void iflib_stop(if_ctx_t ctx); 725 static void iflib_if_init_locked(if_ctx_t ctx); 726 #ifndef __NO_STRICT_ALIGNMENT 727 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 728 #endif 729 730 #ifdef DEV_NETMAP 731 #include <sys/selinfo.h> 732 #include <net/netmap.h> 733 #include <dev/netmap/netmap_kern.h> 734 735 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 736 737 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init); 738 739 /* 740 * device-specific sysctl variables: 741 * 742 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 743 * During regular operations the CRC is stripped, but on some 744 * hardware reception of frames not multiple of 64 is slower, 745 * so using crcstrip=0 helps in benchmarks. 746 * 747 * iflib_rx_miss, iflib_rx_miss_bufs: 748 * count packets that might be missed due to lost interrupts. 749 */ 750 SYSCTL_DECL(_dev_netmap); 751 /* 752 * The xl driver by default strips CRCs and we do not override it. 753 */ 754 755 int iflib_crcstrip = 1; 756 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 757 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames"); 758 759 int iflib_rx_miss, iflib_rx_miss_bufs; 760 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 761 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr"); 762 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 763 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs"); 764 765 /* 766 * Register/unregister. We are already under netmap lock. 767 * Only called on the first register or the last unregister. 768 */ 769 static int 770 iflib_netmap_register(struct netmap_adapter *na, int onoff) 771 { 772 struct ifnet *ifp = na->ifp; 773 if_ctx_t ctx = ifp->if_softc; 774 int status; 775 776 CTX_LOCK(ctx); 777 IFDI_INTR_DISABLE(ctx); 778 779 /* Tell the stack that the interface is no longer active */ 780 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 781 782 if (!CTX_IS_VF(ctx)) 783 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 784 785 /* enable or disable flags and callbacks in na and ifp */ 786 if (onoff) { 787 nm_set_native_flags(na); 788 } else { 789 nm_clear_native_flags(na); 790 } 791 iflib_stop(ctx); 792 iflib_init_locked(ctx); 793 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 794 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 795 if (status) 796 nm_clear_native_flags(na); 797 CTX_UNLOCK(ctx); 798 return (status); 799 } 800 801 static int 802 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init) 803 { 804 struct netmap_adapter *na = kring->na; 805 u_int const lim = kring->nkr_num_slots - 1; 806 u_int head = kring->rhead; 807 struct netmap_ring *ring = kring->ring; 808 bus_dmamap_t *map; 809 struct if_rxd_update iru; 810 if_ctx_t ctx = rxq->ifr_ctx; 811 iflib_fl_t fl = &rxq->ifr_fl[0]; 812 uint32_t refill_pidx, nic_i; 813 814 if (nm_i == head && __predict_true(!init)) 815 return 0; 816 iru_init(&iru, rxq, 0 /* flid */); 817 map = fl->ifl_sds.ifsd_map; 818 refill_pidx = netmap_idx_k2n(kring, nm_i); 819 /* 820 * IMPORTANT: we must leave one free slot in the ring, 821 * so move head back by one unit 822 */ 823 head = nm_prev(head, lim); 824 while (nm_i != head) { 825 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) { 826 struct netmap_slot *slot = &ring->slot[nm_i]; 827 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]); 828 uint32_t nic_i_dma = refill_pidx; 829 nic_i = netmap_idx_k2n(kring, nm_i); 830 831 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH); 832 833 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 834 return netmap_ring_reinit(kring); 835 836 fl->ifl_vm_addrs[tmp_pidx] = addr; 837 if (__predict_false(init) && map) { 838 netmap_load_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); 839 } else if (map && (slot->flags & NS_BUF_CHANGED)) { 840 /* buffer has changed, reload map */ 841 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); 842 } 843 slot->flags &= ~NS_BUF_CHANGED; 844 845 nm_i = nm_next(nm_i, lim); 846 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim); 847 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1) 848 continue; 849 850 iru.iru_pidx = refill_pidx; 851 iru.iru_count = tmp_pidx+1; 852 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 853 854 refill_pidx = nic_i; 855 if (map == NULL) 856 continue; 857 858 for (int n = 0; n < iru.iru_count; n++) { 859 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, map[nic_i_dma], 860 BUS_DMASYNC_PREREAD); 861 /* XXX - change this to not use the netmap func*/ 862 nic_i_dma = nm_next(nic_i_dma, lim); 863 } 864 } 865 } 866 kring->nr_hwcur = head; 867 868 if (map) 869 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 870 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 871 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 872 return (0); 873 } 874 875 /* 876 * Reconcile kernel and user view of the transmit ring. 877 * 878 * All information is in the kring. 879 * Userspace wants to send packets up to the one before kring->rhead, 880 * kernel knows kring->nr_hwcur is the first unsent packet. 881 * 882 * Here we push packets out (as many as possible), and possibly 883 * reclaim buffers from previously completed transmission. 884 * 885 * The caller (netmap) guarantees that there is only one instance 886 * running at any time. Any interference with other driver 887 * methods should be handled by the individual drivers. 888 */ 889 static int 890 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 891 { 892 struct netmap_adapter *na = kring->na; 893 struct ifnet *ifp = na->ifp; 894 struct netmap_ring *ring = kring->ring; 895 u_int nm_i; /* index into the netmap ring */ 896 u_int nic_i; /* index into the NIC ring */ 897 u_int n; 898 u_int const lim = kring->nkr_num_slots - 1; 899 u_int const head = kring->rhead; 900 struct if_pkt_info pi; 901 902 /* 903 * interrupts on every tx packet are expensive so request 904 * them every half ring, or where NS_REPORT is set 905 */ 906 u_int report_frequency = kring->nkr_num_slots >> 1; 907 /* device-specific */ 908 if_ctx_t ctx = ifp->if_softc; 909 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 910 911 if (txq->ift_sds.ifsd_map) 912 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 913 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 914 915 916 /* 917 * First part: process new packets to send. 918 * nm_i is the current index in the netmap ring, 919 * nic_i is the corresponding index in the NIC ring. 920 * 921 * If we have packets to send (nm_i != head) 922 * iterate over the netmap ring, fetch length and update 923 * the corresponding slot in the NIC ring. Some drivers also 924 * need to update the buffer's physical address in the NIC slot 925 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 926 * 927 * The netmap_reload_map() calls is especially expensive, 928 * even when (as in this case) the tag is 0, so do only 929 * when the buffer has actually changed. 930 * 931 * If possible do not set the report/intr bit on all slots, 932 * but only a few times per ring or when NS_REPORT is set. 933 * 934 * Finally, on 10G and faster drivers, it might be useful 935 * to prefetch the next slot and txr entry. 936 */ 937 938 nm_i = netmap_idx_n2k(kring, kring->nr_hwcur); 939 pkt_info_zero(&pi); 940 pi.ipi_segs = txq->ift_segs; 941 pi.ipi_qsidx = kring->ring_id; 942 if (nm_i != head) { /* we have new packets to send */ 943 nic_i = netmap_idx_k2n(kring, nm_i); 944 945 __builtin_prefetch(&ring->slot[nm_i]); 946 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 947 if (txq->ift_sds.ifsd_map) 948 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 949 950 for (n = 0; nm_i != head; n++) { 951 struct netmap_slot *slot = &ring->slot[nm_i]; 952 u_int len = slot->len; 953 uint64_t paddr; 954 void *addr = PNMB(na, slot, &paddr); 955 int flags = (slot->flags & NS_REPORT || 956 nic_i == 0 || nic_i == report_frequency) ? 957 IPI_TX_INTR : 0; 958 959 /* device-specific */ 960 pi.ipi_len = len; 961 pi.ipi_segs[0].ds_addr = paddr; 962 pi.ipi_segs[0].ds_len = len; 963 pi.ipi_nsegs = 1; 964 pi.ipi_ndescs = 0; 965 pi.ipi_pidx = nic_i; 966 pi.ipi_flags = flags; 967 968 /* Fill the slot in the NIC ring. */ 969 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 970 971 /* prefetch for next round */ 972 __builtin_prefetch(&ring->slot[nm_i + 1]); 973 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 974 if (txq->ift_sds.ifsd_map) { 975 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 976 977 NM_CHECK_ADDR_LEN(na, addr, len); 978 979 if (slot->flags & NS_BUF_CHANGED) { 980 /* buffer has changed, reload map */ 981 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr); 982 } 983 /* make sure changes to the buffer are synced */ 984 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i], 985 BUS_DMASYNC_PREWRITE); 986 } 987 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 988 nm_i = nm_next(nm_i, lim); 989 nic_i = nm_next(nic_i, lim); 990 } 991 kring->nr_hwcur = head; 992 993 /* synchronize the NIC ring */ 994 if (txq->ift_sds.ifsd_map) 995 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 996 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 997 998 /* (re)start the tx unit up to slot nic_i (excluded) */ 999 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1000 } 1001 1002 /* 1003 * Second part: reclaim buffers for completed transmissions. 1004 */ 1005 if (iflib_tx_credits_update(ctx, txq)) { 1006 /* some tx completed, increment avail */ 1007 nic_i = txq->ift_cidx_processed; 1008 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1009 } 1010 return (0); 1011 } 1012 1013 /* 1014 * Reconcile kernel and user view of the receive ring. 1015 * Same as for the txsync, this routine must be efficient. 1016 * The caller guarantees a single invocations, but races against 1017 * the rest of the driver should be handled here. 1018 * 1019 * On call, kring->rhead is the first packet that userspace wants 1020 * to keep, and kring->rcur is the wakeup point. 1021 * The kernel has previously reported packets up to kring->rtail. 1022 * 1023 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1024 * of whether or not we received an interrupt. 1025 */ 1026 static int 1027 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1028 { 1029 struct netmap_adapter *na = kring->na; 1030 struct netmap_ring *ring = kring->ring; 1031 uint32_t nm_i; /* index into the netmap ring */ 1032 uint32_t nic_i; /* index into the NIC ring */ 1033 u_int i, n; 1034 u_int const lim = kring->nkr_num_slots - 1; 1035 u_int const head = netmap_idx_n2k(kring, kring->rhead); 1036 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1037 struct if_rxd_info ri; 1038 1039 struct ifnet *ifp = na->ifp; 1040 if_ctx_t ctx = ifp->if_softc; 1041 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1042 iflib_fl_t fl = rxq->ifr_fl; 1043 if (head > lim) 1044 return netmap_ring_reinit(kring); 1045 1046 /* XXX check sync modes */ 1047 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 1048 if (fl->ifl_sds.ifsd_map == NULL) 1049 continue; 1050 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map, 1051 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1052 } 1053 /* 1054 * First part: import newly received packets. 1055 * 1056 * nm_i is the index of the next free slot in the netmap ring, 1057 * nic_i is the index of the next received packet in the NIC ring, 1058 * and they may differ in case if_init() has been called while 1059 * in netmap mode. For the receive ring we have 1060 * 1061 * nic_i = rxr->next_check; 1062 * nm_i = kring->nr_hwtail (previous) 1063 * and 1064 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1065 * 1066 * rxr->next_check is set to 0 on a ring reinit 1067 */ 1068 if (netmap_no_pendintr || force_update) { 1069 int crclen = iflib_crcstrip ? 0 : 4; 1070 int error, avail; 1071 uint16_t slot_flags = kring->nkr_slot_flags; 1072 1073 for (i = 0; i < rxq->ifr_nfl; i++) { 1074 fl = &rxq->ifr_fl[i]; 1075 nic_i = fl->ifl_cidx; 1076 nm_i = netmap_idx_n2k(kring, nic_i); 1077 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX); 1078 for (n = 0; avail > 0; n++, avail--) { 1079 rxd_info_zero(&ri); 1080 ri.iri_frags = rxq->ifr_frags; 1081 ri.iri_qsidx = kring->ring_id; 1082 ri.iri_ifp = ctx->ifc_ifp; 1083 ri.iri_cidx = nic_i; 1084 1085 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1086 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1087 ring->slot[nm_i].flags = slot_flags; 1088 if (fl->ifl_sds.ifsd_map) 1089 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, 1090 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1091 nm_i = nm_next(nm_i, lim); 1092 nic_i = nm_next(nic_i, lim); 1093 } 1094 if (n) { /* update the state variables */ 1095 if (netmap_no_pendintr && !force_update) { 1096 /* diagnostics */ 1097 iflib_rx_miss ++; 1098 iflib_rx_miss_bufs += n; 1099 } 1100 fl->ifl_cidx = nic_i; 1101 kring->nr_hwtail = netmap_idx_k2n(kring, nm_i); 1102 } 1103 kring->nr_kflags &= ~NKR_PENDINTR; 1104 } 1105 } 1106 /* 1107 * Second part: skip past packets that userspace has released. 1108 * (kring->nr_hwcur to head excluded), 1109 * and make the buffers available for reception. 1110 * As usual nm_i is the index in the netmap ring, 1111 * nic_i is the index in the NIC ring, and 1112 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1113 */ 1114 /* XXX not sure how this will work with multiple free lists */ 1115 nm_i = netmap_idx_n2k(kring, kring->nr_hwcur); 1116 1117 return (netmap_fl_refill(rxq, kring, nm_i, false)); 1118 } 1119 1120 static void 1121 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1122 { 1123 struct ifnet *ifp = na->ifp; 1124 if_ctx_t ctx = ifp->if_softc; 1125 1126 CTX_LOCK(ctx); 1127 if (onoff) { 1128 IFDI_INTR_ENABLE(ctx); 1129 } else { 1130 IFDI_INTR_DISABLE(ctx); 1131 } 1132 CTX_UNLOCK(ctx); 1133 } 1134 1135 1136 static int 1137 iflib_netmap_attach(if_ctx_t ctx) 1138 { 1139 struct netmap_adapter na; 1140 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1141 1142 bzero(&na, sizeof(na)); 1143 1144 na.ifp = ctx->ifc_ifp; 1145 na.na_flags = NAF_BDG_MAYSLEEP; 1146 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1147 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1148 1149 na.num_tx_desc = scctx->isc_ntxd[0]; 1150 na.num_rx_desc = scctx->isc_nrxd[0]; 1151 na.nm_txsync = iflib_netmap_txsync; 1152 na.nm_rxsync = iflib_netmap_rxsync; 1153 na.nm_register = iflib_netmap_register; 1154 na.nm_intr = iflib_netmap_intr; 1155 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1156 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1157 return (netmap_attach(&na)); 1158 } 1159 1160 static void 1161 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1162 { 1163 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1164 struct netmap_slot *slot; 1165 1166 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1167 if (slot == NULL) 1168 return; 1169 if (txq->ift_sds.ifsd_map == NULL) 1170 return; 1171 1172 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1173 1174 /* 1175 * In netmap mode, set the map for the packet buffer. 1176 * NOTE: Some drivers (not this one) also need to set 1177 * the physical buffer address in the NIC ring. 1178 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1179 * netmap slot index, si 1180 */ 1181 int si = netmap_idx_n2k(&na->tx_rings[txq->ift_id], i); 1182 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si)); 1183 } 1184 } 1185 1186 static void 1187 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1188 { 1189 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1190 struct netmap_kring *kring = &na->rx_rings[rxq->ifr_id]; 1191 struct netmap_slot *slot; 1192 uint32_t nm_i; 1193 1194 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1195 if (slot == NULL) 1196 return; 1197 nm_i = netmap_idx_n2k(kring, 0); 1198 netmap_fl_refill(rxq, kring, nm_i, true); 1199 } 1200 1201 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1202 1203 #else 1204 #define iflib_netmap_txq_init(ctx, txq) 1205 #define iflib_netmap_rxq_init(ctx, rxq) 1206 #define iflib_netmap_detach(ifp) 1207 1208 #define iflib_netmap_attach(ctx) (0) 1209 #define netmap_rx_irq(ifp, qid, budget) (0) 1210 #define netmap_tx_irq(ifp, qid) do {} while (0) 1211 1212 #endif 1213 1214 #if defined(__i386__) || defined(__amd64__) 1215 static __inline void 1216 prefetch(void *x) 1217 { 1218 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1219 } 1220 static __inline void 1221 prefetch2cachelines(void *x) 1222 { 1223 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1224 #if (CACHE_LINE_SIZE < 128) 1225 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1226 #endif 1227 } 1228 #else 1229 #define prefetch(x) 1230 #define prefetch2cachelines(x) 1231 #endif 1232 1233 static void 1234 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1235 { 1236 iflib_fl_t fl; 1237 1238 fl = &rxq->ifr_fl[flid]; 1239 iru->iru_paddrs = fl->ifl_bus_addrs; 1240 iru->iru_vaddrs = &fl->ifl_vm_addrs[0]; 1241 iru->iru_idxs = fl->ifl_rxd_idxs; 1242 iru->iru_qsidx = rxq->ifr_id; 1243 iru->iru_buf_size = fl->ifl_buf_size; 1244 iru->iru_flidx = fl->ifl_id; 1245 } 1246 1247 static void 1248 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1249 { 1250 if (err) 1251 return; 1252 *(bus_addr_t *) arg = segs[0].ds_addr; 1253 } 1254 1255 int 1256 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1257 { 1258 int err; 1259 if_shared_ctx_t sctx = ctx->ifc_sctx; 1260 device_t dev = ctx->ifc_dev; 1261 1262 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1263 1264 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1265 sctx->isc_q_align, 0, /* alignment, bounds */ 1266 BUS_SPACE_MAXADDR, /* lowaddr */ 1267 BUS_SPACE_MAXADDR, /* highaddr */ 1268 NULL, NULL, /* filter, filterarg */ 1269 size, /* maxsize */ 1270 1, /* nsegments */ 1271 size, /* maxsegsize */ 1272 BUS_DMA_ALLOCNOW, /* flags */ 1273 NULL, /* lockfunc */ 1274 NULL, /* lockarg */ 1275 &dma->idi_tag); 1276 if (err) { 1277 device_printf(dev, 1278 "%s: bus_dma_tag_create failed: %d\n", 1279 __func__, err); 1280 goto fail_0; 1281 } 1282 1283 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1284 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1285 if (err) { 1286 device_printf(dev, 1287 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1288 __func__, (uintmax_t)size, err); 1289 goto fail_1; 1290 } 1291 1292 dma->idi_paddr = IF_BAD_DMA; 1293 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1294 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1295 if (err || dma->idi_paddr == IF_BAD_DMA) { 1296 device_printf(dev, 1297 "%s: bus_dmamap_load failed: %d\n", 1298 __func__, err); 1299 goto fail_2; 1300 } 1301 1302 dma->idi_size = size; 1303 return (0); 1304 1305 fail_2: 1306 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1307 fail_1: 1308 bus_dma_tag_destroy(dma->idi_tag); 1309 fail_0: 1310 dma->idi_tag = NULL; 1311 1312 return (err); 1313 } 1314 1315 int 1316 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1317 { 1318 int i, err; 1319 iflib_dma_info_t *dmaiter; 1320 1321 dmaiter = dmalist; 1322 for (i = 0; i < count; i++, dmaiter++) { 1323 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1324 break; 1325 } 1326 if (err) 1327 iflib_dma_free_multi(dmalist, i); 1328 return (err); 1329 } 1330 1331 void 1332 iflib_dma_free(iflib_dma_info_t dma) 1333 { 1334 if (dma->idi_tag == NULL) 1335 return; 1336 if (dma->idi_paddr != IF_BAD_DMA) { 1337 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1338 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1339 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1340 dma->idi_paddr = IF_BAD_DMA; 1341 } 1342 if (dma->idi_vaddr != NULL) { 1343 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1344 dma->idi_vaddr = NULL; 1345 } 1346 bus_dma_tag_destroy(dma->idi_tag); 1347 dma->idi_tag = NULL; 1348 } 1349 1350 void 1351 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1352 { 1353 int i; 1354 iflib_dma_info_t *dmaiter = dmalist; 1355 1356 for (i = 0; i < count; i++, dmaiter++) 1357 iflib_dma_free(*dmaiter); 1358 } 1359 1360 #ifdef EARLY_AP_STARTUP 1361 static const int iflib_started = 1; 1362 #else 1363 /* 1364 * We used to abuse the smp_started flag to decide if the queues have been 1365 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1366 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1367 * is set. Run a SYSINIT() strictly after that to just set a usable 1368 * completion flag. 1369 */ 1370 1371 static int iflib_started; 1372 1373 static void 1374 iflib_record_started(void *arg) 1375 { 1376 iflib_started = 1; 1377 } 1378 1379 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1380 iflib_record_started, NULL); 1381 #endif 1382 1383 static int 1384 iflib_fast_intr(void *arg) 1385 { 1386 iflib_filter_info_t info = arg; 1387 struct grouptask *gtask = info->ifi_task; 1388 if (!iflib_started) 1389 return (FILTER_HANDLED); 1390 1391 DBG_COUNTER_INC(fast_intrs); 1392 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1393 return (FILTER_HANDLED); 1394 1395 GROUPTASK_ENQUEUE(gtask); 1396 return (FILTER_HANDLED); 1397 } 1398 1399 static int 1400 iflib_fast_intr_rxtx(void *arg) 1401 { 1402 iflib_filter_info_t info = arg; 1403 struct grouptask *gtask = info->ifi_task; 1404 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1405 if_ctx_t ctx; 1406 int i, cidx; 1407 1408 if (!iflib_started) 1409 return (FILTER_HANDLED); 1410 1411 DBG_COUNTER_INC(fast_intrs); 1412 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1413 return (FILTER_HANDLED); 1414 1415 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1416 qidx_t txqid = rxq->ifr_txqid[i]; 1417 1418 ctx = rxq->ifr_ctx; 1419 1420 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) { 1421 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1422 continue; 1423 } 1424 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 1425 } 1426 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1427 cidx = rxq->ifr_cq_cidx; 1428 else 1429 cidx = rxq->ifr_fl[0].ifl_cidx; 1430 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1431 GROUPTASK_ENQUEUE(gtask); 1432 else 1433 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1434 return (FILTER_HANDLED); 1435 } 1436 1437 1438 static int 1439 iflib_fast_intr_ctx(void *arg) 1440 { 1441 iflib_filter_info_t info = arg; 1442 struct grouptask *gtask = info->ifi_task; 1443 1444 if (!iflib_started) 1445 return (FILTER_HANDLED); 1446 1447 DBG_COUNTER_INC(fast_intrs); 1448 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1449 return (FILTER_HANDLED); 1450 1451 GROUPTASK_ENQUEUE(gtask); 1452 return (FILTER_HANDLED); 1453 } 1454 1455 static int 1456 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1457 driver_filter_t filter, driver_intr_t handler, void *arg, 1458 char *name) 1459 { 1460 int rc, flags; 1461 struct resource *res; 1462 void *tag = NULL; 1463 device_t dev = ctx->ifc_dev; 1464 1465 flags = RF_ACTIVE; 1466 if (ctx->ifc_flags & IFC_LEGACY) 1467 flags |= RF_SHAREABLE; 1468 MPASS(rid < 512); 1469 irq->ii_rid = rid; 1470 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags); 1471 if (res == NULL) { 1472 device_printf(dev, 1473 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1474 return (ENOMEM); 1475 } 1476 irq->ii_res = res; 1477 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1478 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1479 filter, handler, arg, &tag); 1480 if (rc != 0) { 1481 device_printf(dev, 1482 "failed to setup interrupt for rid %d, name %s: %d\n", 1483 rid, name ? name : "unknown", rc); 1484 return (rc); 1485 } else if (name) 1486 bus_describe_intr(dev, res, tag, "%s", name); 1487 1488 irq->ii_tag = tag; 1489 return (0); 1490 } 1491 1492 1493 /********************************************************************* 1494 * 1495 * Allocate memory for tx_buffer structures. The tx_buffer stores all 1496 * the information needed to transmit a packet on the wire. This is 1497 * called only once at attach, setup is done every reset. 1498 * 1499 **********************************************************************/ 1500 1501 static int 1502 iflib_txsd_alloc(iflib_txq_t txq) 1503 { 1504 if_ctx_t ctx = txq->ift_ctx; 1505 if_shared_ctx_t sctx = ctx->ifc_sctx; 1506 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1507 device_t dev = ctx->ifc_dev; 1508 int err, nsegments, ntsosegments; 1509 1510 nsegments = scctx->isc_tx_nsegments; 1511 ntsosegments = scctx->isc_tx_tso_segments_max; 1512 MPASS(scctx->isc_ntxd[0] > 0); 1513 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1514 MPASS(nsegments > 0); 1515 MPASS(ntsosegments > 0); 1516 /* 1517 * Setup DMA descriptor areas. 1518 */ 1519 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1520 1, 0, /* alignment, bounds */ 1521 BUS_SPACE_MAXADDR, /* lowaddr */ 1522 BUS_SPACE_MAXADDR, /* highaddr */ 1523 NULL, NULL, /* filter, filterarg */ 1524 sctx->isc_tx_maxsize, /* maxsize */ 1525 nsegments, /* nsegments */ 1526 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1527 0, /* flags */ 1528 NULL, /* lockfunc */ 1529 NULL, /* lockfuncarg */ 1530 &txq->ift_desc_tag))) { 1531 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1532 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1533 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1534 goto fail; 1535 } 1536 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1537 1, 0, /* alignment, bounds */ 1538 BUS_SPACE_MAXADDR, /* lowaddr */ 1539 BUS_SPACE_MAXADDR, /* highaddr */ 1540 NULL, NULL, /* filter, filterarg */ 1541 scctx->isc_tx_tso_size_max, /* maxsize */ 1542 ntsosegments, /* nsegments */ 1543 scctx->isc_tx_tso_segsize_max, /* maxsegsize */ 1544 0, /* flags */ 1545 NULL, /* lockfunc */ 1546 NULL, /* lockfuncarg */ 1547 &txq->ift_tso_desc_tag))) { 1548 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err); 1549 1550 goto fail; 1551 } 1552 if (!(txq->ift_sds.ifsd_flags = 1553 (uint8_t *) malloc(sizeof(uint8_t) * 1554 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1555 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1556 err = ENOMEM; 1557 goto fail; 1558 } 1559 if (!(txq->ift_sds.ifsd_m = 1560 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1561 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1562 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1563 err = ENOMEM; 1564 goto fail; 1565 } 1566 1567 /* Create the descriptor buffer dma maps */ 1568 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1569 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1570 return (0); 1571 1572 if (!(txq->ift_sds.ifsd_map = 1573 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1574 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1575 err = ENOMEM; 1576 goto fail; 1577 } 1578 1579 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1580 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]); 1581 if (err != 0) { 1582 device_printf(dev, "Unable to create TX DMA map\n"); 1583 goto fail; 1584 } 1585 } 1586 #endif 1587 return (0); 1588 fail: 1589 /* We free all, it handles case where we are in the middle */ 1590 iflib_tx_structures_free(ctx); 1591 return (err); 1592 } 1593 1594 static void 1595 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1596 { 1597 bus_dmamap_t map; 1598 1599 map = NULL; 1600 if (txq->ift_sds.ifsd_map != NULL) 1601 map = txq->ift_sds.ifsd_map[i]; 1602 if (map != NULL) { 1603 bus_dmamap_unload(txq->ift_desc_tag, map); 1604 bus_dmamap_destroy(txq->ift_desc_tag, map); 1605 txq->ift_sds.ifsd_map[i] = NULL; 1606 } 1607 } 1608 1609 static void 1610 iflib_txq_destroy(iflib_txq_t txq) 1611 { 1612 if_ctx_t ctx = txq->ift_ctx; 1613 1614 for (int i = 0; i < txq->ift_size; i++) 1615 iflib_txsd_destroy(ctx, txq, i); 1616 if (txq->ift_sds.ifsd_map != NULL) { 1617 free(txq->ift_sds.ifsd_map, M_IFLIB); 1618 txq->ift_sds.ifsd_map = NULL; 1619 } 1620 if (txq->ift_sds.ifsd_m != NULL) { 1621 free(txq->ift_sds.ifsd_m, M_IFLIB); 1622 txq->ift_sds.ifsd_m = NULL; 1623 } 1624 if (txq->ift_sds.ifsd_flags != NULL) { 1625 free(txq->ift_sds.ifsd_flags, M_IFLIB); 1626 txq->ift_sds.ifsd_flags = NULL; 1627 } 1628 if (txq->ift_desc_tag != NULL) { 1629 bus_dma_tag_destroy(txq->ift_desc_tag); 1630 txq->ift_desc_tag = NULL; 1631 } 1632 if (txq->ift_tso_desc_tag != NULL) { 1633 bus_dma_tag_destroy(txq->ift_tso_desc_tag); 1634 txq->ift_tso_desc_tag = NULL; 1635 } 1636 } 1637 1638 static void 1639 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1640 { 1641 struct mbuf **mp; 1642 1643 mp = &txq->ift_sds.ifsd_m[i]; 1644 if (*mp == NULL) 1645 return; 1646 1647 if (txq->ift_sds.ifsd_map != NULL) { 1648 bus_dmamap_sync(txq->ift_desc_tag, 1649 txq->ift_sds.ifsd_map[i], 1650 BUS_DMASYNC_POSTWRITE); 1651 bus_dmamap_unload(txq->ift_desc_tag, 1652 txq->ift_sds.ifsd_map[i]); 1653 } 1654 m_free(*mp); 1655 DBG_COUNTER_INC(tx_frees); 1656 *mp = NULL; 1657 } 1658 1659 static int 1660 iflib_txq_setup(iflib_txq_t txq) 1661 { 1662 if_ctx_t ctx = txq->ift_ctx; 1663 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1664 iflib_dma_info_t di; 1665 int i; 1666 1667 /* Set number of descriptors available */ 1668 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1669 /* XXX make configurable */ 1670 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1671 1672 /* Reset indices */ 1673 txq->ift_cidx_processed = 0; 1674 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1675 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1676 1677 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1678 bzero((void *)di->idi_vaddr, di->idi_size); 1679 1680 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1681 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1682 bus_dmamap_sync(di->idi_tag, di->idi_map, 1683 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1684 return (0); 1685 } 1686 1687 /********************************************************************* 1688 * 1689 * Allocate memory for rx_buffer structures. Since we use one 1690 * rx_buffer per received packet, the maximum number of rx_buffer's 1691 * that we'll need is equal to the number of receive descriptors 1692 * that we've allocated. 1693 * 1694 **********************************************************************/ 1695 static int 1696 iflib_rxsd_alloc(iflib_rxq_t rxq) 1697 { 1698 if_ctx_t ctx = rxq->ifr_ctx; 1699 if_shared_ctx_t sctx = ctx->ifc_sctx; 1700 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1701 device_t dev = ctx->ifc_dev; 1702 iflib_fl_t fl; 1703 int err; 1704 1705 MPASS(scctx->isc_nrxd[0] > 0); 1706 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1707 1708 fl = rxq->ifr_fl; 1709 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1710 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1711 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1712 1, 0, /* alignment, bounds */ 1713 BUS_SPACE_MAXADDR, /* lowaddr */ 1714 BUS_SPACE_MAXADDR, /* highaddr */ 1715 NULL, NULL, /* filter, filterarg */ 1716 sctx->isc_rx_maxsize, /* maxsize */ 1717 sctx->isc_rx_nsegments, /* nsegments */ 1718 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1719 0, /* flags */ 1720 NULL, /* lockfunc */ 1721 NULL, /* lockarg */ 1722 &fl->ifl_desc_tag); 1723 if (err) { 1724 device_printf(dev, "%s: bus_dma_tag_create failed %d\n", 1725 __func__, err); 1726 goto fail; 1727 } 1728 if (!(fl->ifl_sds.ifsd_flags = 1729 (uint8_t *) malloc(sizeof(uint8_t) * 1730 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1731 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1732 err = ENOMEM; 1733 goto fail; 1734 } 1735 if (!(fl->ifl_sds.ifsd_m = 1736 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1737 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1738 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1739 err = ENOMEM; 1740 goto fail; 1741 } 1742 if (!(fl->ifl_sds.ifsd_cl = 1743 (caddr_t *) malloc(sizeof(caddr_t) * 1744 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1745 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1746 err = ENOMEM; 1747 goto fail; 1748 } 1749 1750 /* Create the descriptor buffer dma maps */ 1751 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1752 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1753 continue; 1754 1755 if (!(fl->ifl_sds.ifsd_map = 1756 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1757 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1758 err = ENOMEM; 1759 goto fail; 1760 } 1761 1762 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1763 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]); 1764 if (err != 0) { 1765 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1766 goto fail; 1767 } 1768 } 1769 #endif 1770 } 1771 return (0); 1772 1773 fail: 1774 iflib_rx_structures_free(ctx); 1775 return (err); 1776 } 1777 1778 1779 /* 1780 * Internal service routines 1781 */ 1782 1783 struct rxq_refill_cb_arg { 1784 int error; 1785 bus_dma_segment_t seg; 1786 int nseg; 1787 }; 1788 1789 static void 1790 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1791 { 1792 struct rxq_refill_cb_arg *cb_arg = arg; 1793 1794 cb_arg->error = error; 1795 cb_arg->seg = segs[0]; 1796 cb_arg->nseg = nseg; 1797 } 1798 1799 1800 #ifdef ACPI_DMAR 1801 #define IS_DMAR(ctx) (ctx->ifc_flags & IFC_DMAR) 1802 #else 1803 #define IS_DMAR(ctx) (0) 1804 #endif 1805 1806 /** 1807 * rxq_refill - refill an rxq free-buffer list 1808 * @ctx: the iflib context 1809 * @rxq: the free-list to refill 1810 * @n: the number of new buffers to allocate 1811 * 1812 * (Re)populate an rxq free-buffer list with up to @n new packet buffers. 1813 * The caller must assure that @n does not exceed the queue's capacity. 1814 */ 1815 static void 1816 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1817 { 1818 struct mbuf *m; 1819 int idx, frag_idx = fl->ifl_fragidx; 1820 int pidx = fl->ifl_pidx; 1821 caddr_t cl, *sd_cl; 1822 struct mbuf **sd_m; 1823 uint8_t *sd_flags; 1824 struct if_rxd_update iru; 1825 bus_dmamap_t *sd_map; 1826 int n, i = 0; 1827 uint64_t bus_addr; 1828 int err; 1829 qidx_t credits; 1830 1831 sd_m = fl->ifl_sds.ifsd_m; 1832 sd_map = fl->ifl_sds.ifsd_map; 1833 sd_cl = fl->ifl_sds.ifsd_cl; 1834 sd_flags = fl->ifl_sds.ifsd_flags; 1835 idx = pidx; 1836 credits = fl->ifl_credits; 1837 1838 n = count; 1839 MPASS(n > 0); 1840 MPASS(credits + n <= fl->ifl_size); 1841 1842 if (pidx < fl->ifl_cidx) 1843 MPASS(pidx + n <= fl->ifl_cidx); 1844 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1845 MPASS(fl->ifl_gen == 0); 1846 if (pidx > fl->ifl_cidx) 1847 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1848 1849 DBG_COUNTER_INC(fl_refills); 1850 if (n > 8) 1851 DBG_COUNTER_INC(fl_refills_large); 1852 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1853 while (n--) { 1854 /* 1855 * We allocate an uninitialized mbuf + cluster, mbuf is 1856 * initialized after rx. 1857 * 1858 * If the cluster is still set then we know a minimum sized packet was received 1859 */ 1860 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, &frag_idx); 1861 if ((frag_idx < 0) || (frag_idx >= fl->ifl_size)) 1862 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 1863 if ((cl = sd_cl[frag_idx]) == NULL) { 1864 if ((cl = sd_cl[frag_idx] = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1865 break; 1866 #if MEMORY_LOGGING 1867 fl->ifl_cl_enqueued++; 1868 #endif 1869 } 1870 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 1871 break; 1872 } 1873 #if MEMORY_LOGGING 1874 fl->ifl_m_enqueued++; 1875 #endif 1876 1877 DBG_COUNTER_INC(rx_allocs); 1878 #if defined(__i386__) || defined(__amd64__) 1879 if (!IS_DMAR(ctx)) { 1880 bus_addr = pmap_kextract((vm_offset_t)cl); 1881 } else 1882 #endif 1883 { 1884 struct rxq_refill_cb_arg cb_arg; 1885 iflib_rxq_t q; 1886 1887 cb_arg.error = 0; 1888 q = fl->ifl_rxq; 1889 MPASS(sd_map != NULL); 1890 MPASS(sd_map[frag_idx] != NULL); 1891 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[frag_idx], 1892 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0); 1893 bus_dmamap_sync(fl->ifl_desc_tag, sd_map[frag_idx], 1894 BUS_DMASYNC_PREREAD); 1895 1896 if (err != 0 || cb_arg.error) { 1897 /* 1898 * !zone_pack ? 1899 */ 1900 if (fl->ifl_zone == zone_pack) 1901 uma_zfree(fl->ifl_zone, cl); 1902 m_free(m); 1903 n = 0; 1904 goto done; 1905 } 1906 bus_addr = cb_arg.seg.ds_addr; 1907 } 1908 bit_set(fl->ifl_rx_bitmap, frag_idx); 1909 sd_flags[frag_idx] |= RX_SW_DESC_INUSE; 1910 1911 MPASS(sd_m[frag_idx] == NULL); 1912 sd_cl[frag_idx] = cl; 1913 sd_m[frag_idx] = m; 1914 fl->ifl_rxd_idxs[i] = frag_idx; 1915 fl->ifl_bus_addrs[i] = bus_addr; 1916 fl->ifl_vm_addrs[i] = cl; 1917 credits++; 1918 i++; 1919 MPASS(credits <= fl->ifl_size); 1920 if (++idx == fl->ifl_size) { 1921 fl->ifl_gen = 1; 1922 idx = 0; 1923 } 1924 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 1925 iru.iru_pidx = pidx; 1926 iru.iru_count = i; 1927 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1928 i = 0; 1929 pidx = idx; 1930 fl->ifl_pidx = idx; 1931 fl->ifl_credits = credits; 1932 } 1933 1934 } 1935 done: 1936 if (i) { 1937 iru.iru_pidx = pidx; 1938 iru.iru_count = i; 1939 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1940 fl->ifl_pidx = idx; 1941 fl->ifl_credits = credits; 1942 } 1943 DBG_COUNTER_INC(rxd_flush); 1944 if (fl->ifl_pidx == 0) 1945 pidx = fl->ifl_size - 1; 1946 else 1947 pidx = fl->ifl_pidx - 1; 1948 1949 if (sd_map) 1950 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1951 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1952 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 1953 fl->ifl_fragidx = frag_idx; 1954 } 1955 1956 static __inline void 1957 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 1958 { 1959 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 1960 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 1961 #ifdef INVARIANTS 1962 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 1963 #endif 1964 1965 MPASS(fl->ifl_credits <= fl->ifl_size); 1966 MPASS(reclaimable == delta); 1967 1968 if (reclaimable > 0) 1969 _iflib_fl_refill(ctx, fl, min(max, reclaimable)); 1970 } 1971 1972 static void 1973 iflib_fl_bufs_free(iflib_fl_t fl) 1974 { 1975 iflib_dma_info_t idi = fl->ifl_ifdi; 1976 uint32_t i; 1977 1978 for (i = 0; i < fl->ifl_size; i++) { 1979 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 1980 uint8_t *sd_flags = &fl->ifl_sds.ifsd_flags[i]; 1981 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 1982 1983 if (*sd_flags & RX_SW_DESC_INUSE) { 1984 if (fl->ifl_sds.ifsd_map != NULL) { 1985 bus_dmamap_t sd_map = fl->ifl_sds.ifsd_map[i]; 1986 bus_dmamap_unload(fl->ifl_desc_tag, sd_map); 1987 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map); 1988 } 1989 if (*sd_m != NULL) { 1990 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 1991 uma_zfree(zone_mbuf, *sd_m); 1992 } 1993 if (*sd_cl != NULL) 1994 uma_zfree(fl->ifl_zone, *sd_cl); 1995 *sd_flags = 0; 1996 } else { 1997 MPASS(*sd_cl == NULL); 1998 MPASS(*sd_m == NULL); 1999 } 2000 #if MEMORY_LOGGING 2001 fl->ifl_m_dequeued++; 2002 fl->ifl_cl_dequeued++; 2003 #endif 2004 *sd_cl = NULL; 2005 *sd_m = NULL; 2006 } 2007 #ifdef INVARIANTS 2008 for (i = 0; i < fl->ifl_size; i++) { 2009 MPASS(fl->ifl_sds.ifsd_flags[i] == 0); 2010 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2011 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2012 } 2013 #endif 2014 /* 2015 * Reset free list values 2016 */ 2017 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2018 bzero(idi->idi_vaddr, idi->idi_size); 2019 } 2020 2021 /********************************************************************* 2022 * 2023 * Initialize a receive ring and its buffers. 2024 * 2025 **********************************************************************/ 2026 static int 2027 iflib_fl_setup(iflib_fl_t fl) 2028 { 2029 iflib_rxq_t rxq = fl->ifl_rxq; 2030 if_ctx_t ctx = rxq->ifr_ctx; 2031 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2032 2033 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2034 /* 2035 ** Free current RX buffer structs and their mbufs 2036 */ 2037 iflib_fl_bufs_free(fl); 2038 /* Now replenish the mbufs */ 2039 MPASS(fl->ifl_credits == 0); 2040 /* 2041 * XXX don't set the max_frame_size to larger 2042 * than the hardware can handle 2043 */ 2044 if (sctx->isc_max_frame_size <= 2048) 2045 fl->ifl_buf_size = MCLBYTES; 2046 #ifndef CONTIGMALLOC_WORKS 2047 else 2048 fl->ifl_buf_size = MJUMPAGESIZE; 2049 #else 2050 else if (sctx->isc_max_frame_size <= 4096) 2051 fl->ifl_buf_size = MJUMPAGESIZE; 2052 else if (sctx->isc_max_frame_size <= 9216) 2053 fl->ifl_buf_size = MJUM9BYTES; 2054 else 2055 fl->ifl_buf_size = MJUM16BYTES; 2056 #endif 2057 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2058 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2059 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2060 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2061 2062 2063 /* avoid pre-allocating zillions of clusters to an idle card 2064 * potentially speeding up attach 2065 */ 2066 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2067 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2068 if (min(128, fl->ifl_size) != fl->ifl_credits) 2069 return (ENOBUFS); 2070 /* 2071 * handle failure 2072 */ 2073 MPASS(rxq != NULL); 2074 MPASS(fl->ifl_ifdi != NULL); 2075 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2076 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2077 return (0); 2078 } 2079 2080 /********************************************************************* 2081 * 2082 * Free receive ring data structures 2083 * 2084 **********************************************************************/ 2085 static void 2086 iflib_rx_sds_free(iflib_rxq_t rxq) 2087 { 2088 iflib_fl_t fl; 2089 int i; 2090 2091 if (rxq->ifr_fl != NULL) { 2092 for (i = 0; i < rxq->ifr_nfl; i++) { 2093 fl = &rxq->ifr_fl[i]; 2094 if (fl->ifl_desc_tag != NULL) { 2095 bus_dma_tag_destroy(fl->ifl_desc_tag); 2096 fl->ifl_desc_tag = NULL; 2097 } 2098 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2099 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2100 /* XXX destroy maps first */ 2101 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2102 fl->ifl_sds.ifsd_m = NULL; 2103 fl->ifl_sds.ifsd_cl = NULL; 2104 fl->ifl_sds.ifsd_map = NULL; 2105 } 2106 free(rxq->ifr_fl, M_IFLIB); 2107 rxq->ifr_fl = NULL; 2108 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2109 } 2110 } 2111 2112 /* 2113 * MI independent logic 2114 * 2115 */ 2116 static void 2117 iflib_timer(void *arg) 2118 { 2119 iflib_txq_t txq = arg; 2120 if_ctx_t ctx = txq->ift_ctx; 2121 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2122 2123 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2124 return; 2125 /* 2126 ** Check on the state of the TX queue(s), this 2127 ** can be done without the lock because its RO 2128 ** and the HUNG state will be static if set. 2129 */ 2130 IFDI_TIMER(ctx, txq->ift_id); 2131 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2132 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2133 (sctx->isc_pause_frames == 0))) 2134 goto hung; 2135 2136 if (ifmp_ring_is_stalled(txq->ift_br)) 2137 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2138 txq->ift_cleaned_prev = txq->ift_cleaned; 2139 /* handle any laggards */ 2140 if (txq->ift_db_pending) 2141 GROUPTASK_ENQUEUE(&txq->ift_task); 2142 2143 sctx->isc_pause_frames = 0; 2144 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2145 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); 2146 return; 2147 hung: 2148 CTX_LOCK(ctx); 2149 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2150 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n", 2151 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2152 2153 IFDI_WATCHDOG_RESET(ctx); 2154 ctx->ifc_watchdog_events++; 2155 2156 ctx->ifc_flags |= IFC_DO_RESET; 2157 iflib_admin_intr_deferred(ctx); 2158 CTX_UNLOCK(ctx); 2159 } 2160 2161 static void 2162 iflib_init_locked(if_ctx_t ctx) 2163 { 2164 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2165 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2166 if_t ifp = ctx->ifc_ifp; 2167 iflib_fl_t fl; 2168 iflib_txq_t txq; 2169 iflib_rxq_t rxq; 2170 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2171 2172 2173 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2174 IFDI_INTR_DISABLE(ctx); 2175 2176 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2177 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2178 /* Set hardware offload abilities */ 2179 if_clearhwassist(ifp); 2180 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2181 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2182 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2183 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2184 if (if_getcapenable(ifp) & IFCAP_TSO4) 2185 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2186 if (if_getcapenable(ifp) & IFCAP_TSO6) 2187 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2188 2189 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2190 CALLOUT_LOCK(txq); 2191 callout_stop(&txq->ift_timer); 2192 CALLOUT_UNLOCK(txq); 2193 iflib_netmap_txq_init(ctx, txq); 2194 } 2195 #ifdef INVARIANTS 2196 i = if_getdrvflags(ifp); 2197 #endif 2198 IFDI_INIT(ctx); 2199 MPASS(if_getdrvflags(ifp) == i); 2200 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2201 /* XXX this should really be done on a per-queue basis */ 2202 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2203 MPASS(rxq->ifr_id == i); 2204 iflib_netmap_rxq_init(ctx, rxq); 2205 continue; 2206 } 2207 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2208 if (iflib_fl_setup(fl)) { 2209 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n"); 2210 goto done; 2211 } 2212 } 2213 } 2214 done: 2215 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2216 IFDI_INTR_ENABLE(ctx); 2217 txq = ctx->ifc_txqs; 2218 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2219 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2220 txq->ift_timer.c_cpu); 2221 } 2222 2223 static int 2224 iflib_media_change(if_t ifp) 2225 { 2226 if_ctx_t ctx = if_getsoftc(ifp); 2227 int err; 2228 2229 CTX_LOCK(ctx); 2230 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2231 iflib_init_locked(ctx); 2232 CTX_UNLOCK(ctx); 2233 return (err); 2234 } 2235 2236 static void 2237 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2238 { 2239 if_ctx_t ctx = if_getsoftc(ifp); 2240 2241 CTX_LOCK(ctx); 2242 IFDI_UPDATE_ADMIN_STATUS(ctx); 2243 IFDI_MEDIA_STATUS(ctx, ifmr); 2244 CTX_UNLOCK(ctx); 2245 } 2246 2247 static void 2248 iflib_stop(if_ctx_t ctx) 2249 { 2250 iflib_txq_t txq = ctx->ifc_txqs; 2251 iflib_rxq_t rxq = ctx->ifc_rxqs; 2252 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2253 iflib_dma_info_t di; 2254 iflib_fl_t fl; 2255 int i, j; 2256 2257 /* Tell the stack that the interface is no longer active */ 2258 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2259 2260 IFDI_INTR_DISABLE(ctx); 2261 DELAY(1000); 2262 IFDI_STOP(ctx); 2263 DELAY(1000); 2264 2265 iflib_debug_reset(); 2266 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2267 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2268 /* make sure all transmitters have completed before proceeding XXX */ 2269 2270 /* clean any enqueued buffers */ 2271 iflib_ifmp_purge(txq); 2272 /* Free any existing tx buffers. */ 2273 for (j = 0; j < txq->ift_size; j++) { 2274 iflib_txsd_free(ctx, txq, j); 2275 } 2276 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2277 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2278 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2279 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2280 txq->ift_pullups = 0; 2281 ifmp_ring_reset_stats(txq->ift_br); 2282 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwtxqs; j++, di++) 2283 bzero((void *)di->idi_vaddr, di->idi_size); 2284 } 2285 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2286 /* make sure all transmitters have completed before proceeding XXX */ 2287 2288 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwrxqs; j++, di++) 2289 bzero((void *)di->idi_vaddr, di->idi_size); 2290 /* also resets the free lists pidx/cidx */ 2291 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2292 iflib_fl_bufs_free(fl); 2293 } 2294 } 2295 2296 static inline caddr_t 2297 calc_next_rxd(iflib_fl_t fl, int cidx) 2298 { 2299 qidx_t size; 2300 int nrxd; 2301 caddr_t start, end, cur, next; 2302 2303 nrxd = fl->ifl_size; 2304 size = fl->ifl_rxd_size; 2305 start = fl->ifl_ifdi->idi_vaddr; 2306 2307 if (__predict_false(size == 0)) 2308 return (start); 2309 cur = start + size*cidx; 2310 end = start + size*nrxd; 2311 next = CACHE_PTR_NEXT(cur); 2312 return (next < end ? next : start); 2313 } 2314 2315 static inline void 2316 prefetch_pkts(iflib_fl_t fl, int cidx) 2317 { 2318 int nextptr; 2319 int nrxd = fl->ifl_size; 2320 caddr_t next_rxd; 2321 2322 2323 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2324 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2325 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2326 next_rxd = calc_next_rxd(fl, cidx); 2327 prefetch(next_rxd); 2328 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2329 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2330 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2331 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2332 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2333 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2334 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2335 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2336 } 2337 2338 static void 2339 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd) 2340 { 2341 int flid, cidx; 2342 bus_dmamap_t map; 2343 iflib_fl_t fl; 2344 iflib_dma_info_t di; 2345 int next; 2346 2347 map = NULL; 2348 flid = irf->irf_flid; 2349 cidx = irf->irf_idx; 2350 fl = &rxq->ifr_fl[flid]; 2351 sd->ifsd_fl = fl; 2352 sd->ifsd_cidx = cidx; 2353 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx]; 2354 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2355 fl->ifl_credits--; 2356 #if MEMORY_LOGGING 2357 fl->ifl_m_dequeued++; 2358 #endif 2359 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2360 prefetch_pkts(fl, cidx); 2361 if (fl->ifl_sds.ifsd_map != NULL) { 2362 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2363 prefetch(&fl->ifl_sds.ifsd_map[next]); 2364 map = fl->ifl_sds.ifsd_map[cidx]; 2365 di = fl->ifl_ifdi; 2366 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2367 prefetch(&fl->ifl_sds.ifsd_flags[next]); 2368 bus_dmamap_sync(di->idi_tag, di->idi_map, 2369 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2370 2371 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2372 MPASS(fl->ifl_cidx == cidx); 2373 if (unload) 2374 bus_dmamap_unload(fl->ifl_desc_tag, map); 2375 } 2376 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2377 if (__predict_false(fl->ifl_cidx == 0)) 2378 fl->ifl_gen = 0; 2379 if (map != NULL) 2380 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2381 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2382 bit_clear(fl->ifl_rx_bitmap, cidx); 2383 } 2384 2385 static struct mbuf * 2386 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd) 2387 { 2388 int i, padlen , flags; 2389 struct mbuf *m, *mh, *mt; 2390 caddr_t cl; 2391 2392 i = 0; 2393 mh = NULL; 2394 do { 2395 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd); 2396 2397 MPASS(*sd->ifsd_cl != NULL); 2398 MPASS(*sd->ifsd_m != NULL); 2399 2400 /* Don't include zero-length frags */ 2401 if (ri->iri_frags[i].irf_len == 0) { 2402 /* XXX we can save the cluster here, but not the mbuf */ 2403 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0); 2404 m_free(*sd->ifsd_m); 2405 *sd->ifsd_m = NULL; 2406 continue; 2407 } 2408 m = *sd->ifsd_m; 2409 *sd->ifsd_m = NULL; 2410 if (mh == NULL) { 2411 flags = M_PKTHDR|M_EXT; 2412 mh = mt = m; 2413 padlen = ri->iri_pad; 2414 } else { 2415 flags = M_EXT; 2416 mt->m_next = m; 2417 mt = m; 2418 /* assuming padding is only on the first fragment */ 2419 padlen = 0; 2420 } 2421 cl = *sd->ifsd_cl; 2422 *sd->ifsd_cl = NULL; 2423 2424 /* Can these two be made one ? */ 2425 m_init(m, M_NOWAIT, MT_DATA, flags); 2426 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2427 /* 2428 * These must follow m_init and m_cljset 2429 */ 2430 m->m_data += padlen; 2431 ri->iri_len -= padlen; 2432 m->m_len = ri->iri_frags[i].irf_len; 2433 } while (++i < ri->iri_nfrags); 2434 2435 return (mh); 2436 } 2437 2438 /* 2439 * Process one software descriptor 2440 */ 2441 static struct mbuf * 2442 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2443 { 2444 struct if_rxsd sd; 2445 struct mbuf *m; 2446 2447 /* should I merge this back in now that the two paths are basically duplicated? */ 2448 if (ri->iri_nfrags == 1 && 2449 ri->iri_frags[0].irf_len <= IFLIB_RX_COPY_THRESH) { 2450 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd); 2451 m = *sd.ifsd_m; 2452 *sd.ifsd_m = NULL; 2453 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2454 #ifndef __NO_STRICT_ALIGNMENT 2455 if (!IP_ALIGNED(m)) 2456 m->m_data += 2; 2457 #endif 2458 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2459 m->m_len = ri->iri_frags[0].irf_len; 2460 } else { 2461 m = assemble_segments(rxq, ri, &sd); 2462 } 2463 m->m_pkthdr.len = ri->iri_len; 2464 m->m_pkthdr.rcvif = ri->iri_ifp; 2465 m->m_flags |= ri->iri_flags; 2466 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2467 m->m_pkthdr.flowid = ri->iri_flowid; 2468 M_HASHTYPE_SET(m, ri->iri_rsstype); 2469 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2470 m->m_pkthdr.csum_data = ri->iri_csum_data; 2471 return (m); 2472 } 2473 2474 #if defined(INET6) || defined(INET) 2475 static void 2476 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2477 { 2478 CURVNET_SET(lc->ifp->if_vnet); 2479 #if defined(INET6) 2480 *v6 = VNET(ip6_forwarding); 2481 #endif 2482 #if defined(INET) 2483 *v4 = VNET(ipforwarding); 2484 #endif 2485 CURVNET_RESTORE(); 2486 } 2487 2488 /* 2489 * Returns true if it's possible this packet could be LROed. 2490 * if it returns false, it is guaranteed that tcp_lro_rx() 2491 * would not return zero. 2492 */ 2493 static bool 2494 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2495 { 2496 struct ether_header *eh; 2497 uint16_t eh_type; 2498 2499 eh = mtod(m, struct ether_header *); 2500 eh_type = ntohs(eh->ether_type); 2501 switch (eh_type) { 2502 #if defined(INET6) 2503 case ETHERTYPE_IPV6: 2504 return !v6_forwarding; 2505 #endif 2506 #if defined (INET) 2507 case ETHERTYPE_IP: 2508 return !v4_forwarding; 2509 #endif 2510 } 2511 2512 return false; 2513 } 2514 #else 2515 static void 2516 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2517 { 2518 } 2519 #endif 2520 2521 static bool 2522 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2523 { 2524 if_ctx_t ctx = rxq->ifr_ctx; 2525 if_shared_ctx_t sctx = ctx->ifc_sctx; 2526 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2527 int avail, i; 2528 qidx_t *cidxp; 2529 struct if_rxd_info ri; 2530 int err, budget_left, rx_bytes, rx_pkts; 2531 iflib_fl_t fl; 2532 struct ifnet *ifp; 2533 int lro_enabled; 2534 bool lro_possible = false; 2535 bool v4_forwarding, v6_forwarding; 2536 2537 /* 2538 * XXX early demux data packets so that if_input processing only handles 2539 * acks in interrupt context 2540 */ 2541 struct mbuf *m, *mh, *mt, *mf; 2542 2543 ifp = ctx->ifc_ifp; 2544 mh = mt = NULL; 2545 MPASS(budget > 0); 2546 rx_pkts = rx_bytes = 0; 2547 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2548 cidxp = &rxq->ifr_cq_cidx; 2549 else 2550 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2551 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2552 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2553 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2554 DBG_COUNTER_INC(rx_unavail); 2555 return (false); 2556 } 2557 2558 for (budget_left = budget; (budget_left > 0) && (avail > 0); budget_left--, avail--) { 2559 if (__predict_false(!CTX_ACTIVE(ctx))) { 2560 DBG_COUNTER_INC(rx_ctx_inactive); 2561 break; 2562 } 2563 /* 2564 * Reset client set fields to their default values 2565 */ 2566 rxd_info_zero(&ri); 2567 ri.iri_qsidx = rxq->ifr_id; 2568 ri.iri_cidx = *cidxp; 2569 ri.iri_ifp = ifp; 2570 ri.iri_frags = rxq->ifr_frags; 2571 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2572 2573 if (err) 2574 goto err; 2575 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2576 *cidxp = ri.iri_cidx; 2577 /* Update our consumer index */ 2578 /* XXX NB: shurd - check if this is still safe */ 2579 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) { 2580 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2581 rxq->ifr_cq_gen = 0; 2582 } 2583 /* was this only a completion queue message? */ 2584 if (__predict_false(ri.iri_nfrags == 0)) 2585 continue; 2586 } 2587 MPASS(ri.iri_nfrags != 0); 2588 MPASS(ri.iri_len != 0); 2589 2590 /* will advance the cidx on the corresponding free lists */ 2591 m = iflib_rxd_pkt_get(rxq, &ri); 2592 if (avail == 0 && budget_left) 2593 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2594 2595 if (__predict_false(m == NULL)) { 2596 DBG_COUNTER_INC(rx_mbuf_null); 2597 continue; 2598 } 2599 /* imm_pkt: -- cxgb */ 2600 if (mh == NULL) 2601 mh = mt = m; 2602 else { 2603 mt->m_nextpkt = m; 2604 mt = m; 2605 } 2606 } 2607 /* make sure that we can refill faster than drain */ 2608 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2609 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2610 2611 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2612 if (lro_enabled) 2613 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2614 mt = mf = NULL; 2615 while (mh != NULL) { 2616 m = mh; 2617 mh = mh->m_nextpkt; 2618 m->m_nextpkt = NULL; 2619 #ifndef __NO_STRICT_ALIGNMENT 2620 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2621 continue; 2622 #endif 2623 rx_bytes += m->m_pkthdr.len; 2624 rx_pkts++; 2625 #if defined(INET6) || defined(INET) 2626 if (lro_enabled) { 2627 if (!lro_possible) { 2628 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2629 if (lro_possible && mf != NULL) { 2630 ifp->if_input(ifp, mf); 2631 DBG_COUNTER_INC(rx_if_input); 2632 mt = mf = NULL; 2633 } 2634 } 2635 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2636 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2637 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2638 continue; 2639 } 2640 } 2641 #endif 2642 if (lro_possible) { 2643 ifp->if_input(ifp, m); 2644 DBG_COUNTER_INC(rx_if_input); 2645 continue; 2646 } 2647 2648 if (mf == NULL) 2649 mf = m; 2650 if (mt != NULL) 2651 mt->m_nextpkt = m; 2652 mt = m; 2653 } 2654 if (mf != NULL) { 2655 ifp->if_input(ifp, mf); 2656 DBG_COUNTER_INC(rx_if_input); 2657 } 2658 2659 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2660 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2661 2662 /* 2663 * Flush any outstanding LRO work 2664 */ 2665 #if defined(INET6) || defined(INET) 2666 tcp_lro_flush_all(&rxq->ifr_lc); 2667 #endif 2668 if (avail) 2669 return true; 2670 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); 2671 err: 2672 CTX_LOCK(ctx); 2673 ctx->ifc_flags |= IFC_DO_RESET; 2674 iflib_admin_intr_deferred(ctx); 2675 CTX_UNLOCK(ctx); 2676 return (false); 2677 } 2678 2679 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2680 static inline qidx_t 2681 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2682 { 2683 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2684 qidx_t minthresh = txq->ift_size / 8; 2685 if (in_use > 4*minthresh) 2686 return (notify_count); 2687 if (in_use > 2*minthresh) 2688 return (notify_count >> 1); 2689 if (in_use > minthresh) 2690 return (notify_count >> 3); 2691 return (0); 2692 } 2693 2694 static inline qidx_t 2695 txq_max_rs_deferred(iflib_txq_t txq) 2696 { 2697 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2698 qidx_t minthresh = txq->ift_size / 8; 2699 if (txq->ift_in_use > 4*minthresh) 2700 return (notify_count); 2701 if (txq->ift_in_use > 2*minthresh) 2702 return (notify_count >> 1); 2703 if (txq->ift_in_use > minthresh) 2704 return (notify_count >> 2); 2705 return (2); 2706 } 2707 2708 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2709 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2710 2711 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2712 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2713 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2714 2715 /* forward compatibility for cxgb */ 2716 #define FIRST_QSET(ctx) 0 2717 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2718 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2719 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2720 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2721 2722 /* XXX we should be setting this to something other than zero */ 2723 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2724 #define MAX_TX_DESC(ctx) ((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max) 2725 2726 static inline bool 2727 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2728 { 2729 qidx_t dbval, max; 2730 bool rang; 2731 2732 rang = false; 2733 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2734 if (ring || txq->ift_db_pending >= max) { 2735 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2736 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2737 txq->ift_db_pending = txq->ift_npending = 0; 2738 rang = true; 2739 } 2740 return (rang); 2741 } 2742 2743 #ifdef PKT_DEBUG 2744 static void 2745 print_pkt(if_pkt_info_t pi) 2746 { 2747 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2748 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2749 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2750 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2751 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2752 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2753 } 2754 #endif 2755 2756 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2757 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2758 2759 static int 2760 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2761 { 2762 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2763 struct ether_vlan_header *eh; 2764 struct mbuf *m, *n; 2765 2766 n = m = *mp; 2767 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 2768 M_WRITABLE(m) == 0) { 2769 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 2770 return (ENOMEM); 2771 } else { 2772 m_freem(*mp); 2773 n = *mp = m; 2774 } 2775 } 2776 2777 /* 2778 * Determine where frame payload starts. 2779 * Jump over vlan headers if already present, 2780 * helpful for QinQ too. 2781 */ 2782 if (__predict_false(m->m_len < sizeof(*eh))) { 2783 txq->ift_pullups++; 2784 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 2785 return (ENOMEM); 2786 } 2787 eh = mtod(m, struct ether_vlan_header *); 2788 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2789 pi->ipi_etype = ntohs(eh->evl_proto); 2790 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2791 } else { 2792 pi->ipi_etype = ntohs(eh->evl_encap_proto); 2793 pi->ipi_ehdrlen = ETHER_HDR_LEN; 2794 } 2795 2796 switch (pi->ipi_etype) { 2797 #ifdef INET 2798 case ETHERTYPE_IP: 2799 { 2800 struct ip *ip = NULL; 2801 struct tcphdr *th = NULL; 2802 int minthlen; 2803 2804 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 2805 if (__predict_false(m->m_len < minthlen)) { 2806 /* 2807 * if this code bloat is causing too much of a hit 2808 * move it to a separate function and mark it noinline 2809 */ 2810 if (m->m_len == pi->ipi_ehdrlen) { 2811 n = m->m_next; 2812 MPASS(n); 2813 if (n->m_len >= sizeof(*ip)) { 2814 ip = (struct ip *)n->m_data; 2815 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2816 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2817 } else { 2818 txq->ift_pullups++; 2819 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2820 return (ENOMEM); 2821 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2822 } 2823 } else { 2824 txq->ift_pullups++; 2825 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2826 return (ENOMEM); 2827 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2828 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2829 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2830 } 2831 } else { 2832 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2833 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2834 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2835 } 2836 pi->ipi_ip_hlen = ip->ip_hl << 2; 2837 pi->ipi_ipproto = ip->ip_p; 2838 pi->ipi_flags |= IPI_TX_IPV4; 2839 2840 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 2841 ip->ip_sum = 0; 2842 2843 if (IS_TSO4(pi)) { 2844 if (pi->ipi_ipproto == IPPROTO_TCP) { 2845 if (__predict_false(th == NULL)) { 2846 txq->ift_pullups++; 2847 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 2848 return (ENOMEM); 2849 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 2850 } 2851 pi->ipi_tcp_hflags = th->th_flags; 2852 pi->ipi_tcp_hlen = th->th_off << 2; 2853 pi->ipi_tcp_seq = th->th_seq; 2854 } 2855 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 2856 return (ENXIO); 2857 th->th_sum = in_pseudo(ip->ip_src.s_addr, 2858 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2859 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2860 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 2861 ip->ip_sum = 0; 2862 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 2863 } 2864 } 2865 break; 2866 } 2867 #endif 2868 #ifdef INET6 2869 case ETHERTYPE_IPV6: 2870 { 2871 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 2872 struct tcphdr *th; 2873 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 2874 2875 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 2876 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 2877 return (ENOMEM); 2878 } 2879 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 2880 2881 /* XXX-BZ this will go badly in case of ext hdrs. */ 2882 pi->ipi_ipproto = ip6->ip6_nxt; 2883 pi->ipi_flags |= IPI_TX_IPV6; 2884 2885 if (IS_TSO6(pi)) { 2886 if (pi->ipi_ipproto == IPPROTO_TCP) { 2887 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 2888 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 2889 return (ENOMEM); 2890 } 2891 pi->ipi_tcp_hflags = th->th_flags; 2892 pi->ipi_tcp_hlen = th->th_off << 2; 2893 } 2894 2895 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 2896 return (ENXIO); 2897 /* 2898 * The corresponding flag is set by the stack in the IPv4 2899 * TSO case, but not in IPv6 (at least in FreeBSD 10.2). 2900 * So, set it here because the rest of the flow requires it. 2901 */ 2902 pi->ipi_csum_flags |= CSUM_TCP_IPV6; 2903 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 2904 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2905 } 2906 break; 2907 } 2908 #endif 2909 default: 2910 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 2911 pi->ipi_ip_hlen = 0; 2912 break; 2913 } 2914 *mp = m; 2915 2916 return (0); 2917 } 2918 2919 static __noinline struct mbuf * 2920 collapse_pkthdr(struct mbuf *m0) 2921 { 2922 struct mbuf *m, *m_next, *tmp; 2923 2924 m = m0; 2925 m_next = m->m_next; 2926 while (m_next != NULL && m_next->m_len == 0) { 2927 m = m_next; 2928 m->m_next = NULL; 2929 m_free(m); 2930 m_next = m_next->m_next; 2931 } 2932 m = m0; 2933 m->m_next = m_next; 2934 if ((m_next->m_flags & M_EXT) == 0) { 2935 m = m_defrag(m, M_NOWAIT); 2936 } else { 2937 tmp = m_next->m_next; 2938 memcpy(m_next, m, MPKTHSIZE); 2939 m = m_next; 2940 m->m_next = tmp; 2941 } 2942 return (m); 2943 } 2944 2945 /* 2946 * If dodgy hardware rejects the scatter gather chain we've handed it 2947 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 2948 * m_defrag'd mbufs 2949 */ 2950 static __noinline struct mbuf * 2951 iflib_remove_mbuf(iflib_txq_t txq) 2952 { 2953 int ntxd, i, pidx; 2954 struct mbuf *m, *mh, **ifsd_m; 2955 2956 pidx = txq->ift_pidx; 2957 ifsd_m = txq->ift_sds.ifsd_m; 2958 ntxd = txq->ift_size; 2959 mh = m = ifsd_m[pidx]; 2960 ifsd_m[pidx] = NULL; 2961 #if MEMORY_LOGGING 2962 txq->ift_dequeued++; 2963 #endif 2964 i = 1; 2965 2966 while (m) { 2967 ifsd_m[(pidx + i) & (ntxd -1)] = NULL; 2968 #if MEMORY_LOGGING 2969 txq->ift_dequeued++; 2970 #endif 2971 m = m->m_next; 2972 i++; 2973 } 2974 return (mh); 2975 } 2976 2977 static int 2978 iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map, 2979 struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs, 2980 int max_segs, int flags) 2981 { 2982 if_ctx_t ctx; 2983 if_shared_ctx_t sctx; 2984 if_softc_ctx_t scctx; 2985 int i, next, pidx, err, ntxd, count; 2986 struct mbuf *m, *tmp, **ifsd_m; 2987 2988 m = *m0; 2989 2990 /* 2991 * Please don't ever do this 2992 */ 2993 if (__predict_false(m->m_len == 0)) 2994 *m0 = m = collapse_pkthdr(m); 2995 2996 ctx = txq->ift_ctx; 2997 sctx = ctx->ifc_sctx; 2998 scctx = &ctx->ifc_softc_ctx; 2999 ifsd_m = txq->ift_sds.ifsd_m; 3000 ntxd = txq->ift_size; 3001 pidx = txq->ift_pidx; 3002 if (map != NULL) { 3003 uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags; 3004 3005 err = bus_dmamap_load_mbuf_sg(tag, map, 3006 *m0, segs, nsegs, BUS_DMA_NOWAIT); 3007 if (err) 3008 return (err); 3009 ifsd_flags[pidx] |= TX_SW_DESC_MAPPED; 3010 count = 0; 3011 m = *m0; 3012 do { 3013 if (__predict_false(m->m_len <= 0)) { 3014 tmp = m; 3015 m = m->m_next; 3016 tmp->m_next = NULL; 3017 m_free(tmp); 3018 continue; 3019 } 3020 m = m->m_next; 3021 count++; 3022 } while (m != NULL); 3023 if (count > *nsegs) { 3024 ifsd_m[pidx] = *m0; 3025 ifsd_m[pidx]->m_flags |= M_TOOBIG; 3026 return (0); 3027 } 3028 m = *m0; 3029 count = 0; 3030 do { 3031 next = (pidx + count) & (ntxd-1); 3032 MPASS(ifsd_m[next] == NULL); 3033 ifsd_m[next] = m; 3034 count++; 3035 tmp = m; 3036 m = m->m_next; 3037 } while (m != NULL); 3038 } else { 3039 int buflen, sgsize, maxsegsz, max_sgsize; 3040 vm_offset_t vaddr; 3041 vm_paddr_t curaddr; 3042 3043 count = i = 0; 3044 m = *m0; 3045 if (m->m_pkthdr.csum_flags & CSUM_TSO) 3046 maxsegsz = scctx->isc_tx_tso_segsize_max; 3047 else 3048 maxsegsz = sctx->isc_tx_maxsegsize; 3049 3050 do { 3051 if (__predict_false(m->m_len <= 0)) { 3052 tmp = m; 3053 m = m->m_next; 3054 tmp->m_next = NULL; 3055 m_free(tmp); 3056 continue; 3057 } 3058 buflen = m->m_len; 3059 vaddr = (vm_offset_t)m->m_data; 3060 /* 3061 * see if we can't be smarter about physically 3062 * contiguous mappings 3063 */ 3064 next = (pidx + count) & (ntxd-1); 3065 MPASS(ifsd_m[next] == NULL); 3066 #if MEMORY_LOGGING 3067 txq->ift_enqueued++; 3068 #endif 3069 ifsd_m[next] = m; 3070 while (buflen > 0) { 3071 if (i >= max_segs) 3072 goto err; 3073 max_sgsize = MIN(buflen, maxsegsz); 3074 curaddr = pmap_kextract(vaddr); 3075 sgsize = PAGE_SIZE - (curaddr & PAGE_MASK); 3076 sgsize = MIN(sgsize, max_sgsize); 3077 segs[i].ds_addr = curaddr; 3078 segs[i].ds_len = sgsize; 3079 vaddr += sgsize; 3080 buflen -= sgsize; 3081 i++; 3082 } 3083 count++; 3084 tmp = m; 3085 m = m->m_next; 3086 } while (m != NULL); 3087 *nsegs = i; 3088 } 3089 return (0); 3090 err: 3091 *m0 = iflib_remove_mbuf(txq); 3092 return (EFBIG); 3093 } 3094 3095 static inline caddr_t 3096 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3097 { 3098 qidx_t size; 3099 int ntxd; 3100 caddr_t start, end, cur, next; 3101 3102 ntxd = txq->ift_size; 3103 size = txq->ift_txd_size[qid]; 3104 start = txq->ift_ifdi[qid].idi_vaddr; 3105 3106 if (__predict_false(size == 0)) 3107 return (start); 3108 cur = start + size*cidx; 3109 end = start + size*ntxd; 3110 next = CACHE_PTR_NEXT(cur); 3111 return (next < end ? next : start); 3112 } 3113 3114 /* 3115 * Pad an mbuf to ensure a minimum ethernet frame size. 3116 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3117 */ 3118 static __noinline int 3119 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3120 { 3121 /* 3122 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3123 * and ARP message is the smallest common payload I can think of 3124 */ 3125 static char pad[18]; /* just zeros */ 3126 int n; 3127 struct mbuf *new_head; 3128 3129 if (!M_WRITABLE(*m_head)) { 3130 new_head = m_dup(*m_head, M_NOWAIT); 3131 if (new_head == NULL) { 3132 m_freem(*m_head); 3133 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3134 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3135 return ENOMEM; 3136 } 3137 m_freem(*m_head); 3138 *m_head = new_head; 3139 } 3140 3141 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3142 n > 0; n -= sizeof(pad)) 3143 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3144 break; 3145 3146 if (n > 0) { 3147 m_freem(*m_head); 3148 device_printf(dev, "cannot pad short frame\n"); 3149 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3150 return (ENOBUFS); 3151 } 3152 3153 return 0; 3154 } 3155 3156 static int 3157 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3158 { 3159 if_ctx_t ctx; 3160 if_shared_ctx_t sctx; 3161 if_softc_ctx_t scctx; 3162 bus_dma_segment_t *segs; 3163 struct mbuf *m_head; 3164 void *next_txd; 3165 bus_dmamap_t map; 3166 struct if_pkt_info pi; 3167 int remap = 0; 3168 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3169 bus_dma_tag_t desc_tag; 3170 3171 segs = txq->ift_segs; 3172 ctx = txq->ift_ctx; 3173 sctx = ctx->ifc_sctx; 3174 scctx = &ctx->ifc_softc_ctx; 3175 segs = txq->ift_segs; 3176 ntxd = txq->ift_size; 3177 m_head = *m_headp; 3178 map = NULL; 3179 3180 /* 3181 * If we're doing TSO the next descriptor to clean may be quite far ahead 3182 */ 3183 cidx = txq->ift_cidx; 3184 pidx = txq->ift_pidx; 3185 if (ctx->ifc_flags & IFC_PREFETCH) { 3186 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3187 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3188 next_txd = calc_next_txd(txq, cidx, 0); 3189 prefetch(next_txd); 3190 } 3191 3192 /* prefetch the next cache line of mbuf pointers and flags */ 3193 prefetch(&txq->ift_sds.ifsd_m[next]); 3194 if (txq->ift_sds.ifsd_map != NULL) { 3195 prefetch(&txq->ift_sds.ifsd_map[next]); 3196 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3197 prefetch(&txq->ift_sds.ifsd_flags[next]); 3198 } 3199 } else if (txq->ift_sds.ifsd_map != NULL) 3200 map = txq->ift_sds.ifsd_map[pidx]; 3201 3202 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3203 desc_tag = txq->ift_tso_desc_tag; 3204 max_segs = scctx->isc_tx_tso_segments_max; 3205 } else { 3206 desc_tag = txq->ift_desc_tag; 3207 max_segs = scctx->isc_tx_nsegments; 3208 } 3209 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3210 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3211 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3212 if (err) 3213 return err; 3214 } 3215 m_head = *m_headp; 3216 3217 pkt_info_zero(&pi); 3218 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3219 pi.ipi_pidx = pidx; 3220 pi.ipi_qsidx = txq->ift_id; 3221 pi.ipi_len = m_head->m_pkthdr.len; 3222 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3223 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0; 3224 3225 /* deliberate bitwise OR to make one condition */ 3226 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3227 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) 3228 return (err); 3229 m_head = *m_headp; 3230 } 3231 3232 retry: 3233 err = iflib_busdma_load_mbuf_sg(txq, desc_tag, map, m_headp, segs, &nsegs, max_segs, BUS_DMA_NOWAIT); 3234 defrag: 3235 if (__predict_false(err)) { 3236 switch (err) { 3237 case EFBIG: 3238 /* try collapse once and defrag once */ 3239 if (remap == 0) 3240 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3241 if (remap == 1) 3242 m_head = m_defrag(*m_headp, M_NOWAIT); 3243 remap++; 3244 if (__predict_false(m_head == NULL)) 3245 goto defrag_failed; 3246 txq->ift_mbuf_defrag++; 3247 *m_headp = m_head; 3248 goto retry; 3249 break; 3250 case ENOMEM: 3251 txq->ift_no_tx_dma_setup++; 3252 break; 3253 default: 3254 txq->ift_no_tx_dma_setup++; 3255 m_freem(*m_headp); 3256 DBG_COUNTER_INC(tx_frees); 3257 *m_headp = NULL; 3258 break; 3259 } 3260 txq->ift_map_failed++; 3261 DBG_COUNTER_INC(encap_load_mbuf_fail); 3262 return (err); 3263 } 3264 3265 /* 3266 * XXX assumes a 1 to 1 relationship between segments and 3267 * descriptors - this does not hold true on all drivers, e.g. 3268 * cxgb 3269 */ 3270 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3271 txq->ift_no_desc_avail++; 3272 if (map != NULL) 3273 bus_dmamap_unload(desc_tag, map); 3274 DBG_COUNTER_INC(encap_txq_avail_fail); 3275 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3276 GROUPTASK_ENQUEUE(&txq->ift_task); 3277 return (ENOBUFS); 3278 } 3279 /* 3280 * On Intel cards we can greatly reduce the number of TX interrupts 3281 * we see by only setting report status on every Nth descriptor. 3282 * However, this also means that the driver will need to keep track 3283 * of the descriptors that RS was set on to check them for the DD bit. 3284 */ 3285 txq->ift_rs_pending += nsegs + 1; 3286 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3287 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs - 1) <= MAX_TX_DESC(ctx)) { 3288 pi.ipi_flags |= IPI_TX_INTR; 3289 txq->ift_rs_pending = 0; 3290 } 3291 3292 pi.ipi_segs = segs; 3293 pi.ipi_nsegs = nsegs; 3294 3295 MPASS(pidx >= 0 && pidx < txq->ift_size); 3296 #ifdef PKT_DEBUG 3297 print_pkt(&pi); 3298 #endif 3299 if (map != NULL) 3300 bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE); 3301 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3302 if (map != NULL) 3303 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3304 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3305 DBG_COUNTER_INC(tx_encap); 3306 MPASS(pi.ipi_new_pidx < txq->ift_size); 3307 3308 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3309 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3310 ndesc += txq->ift_size; 3311 txq->ift_gen = 1; 3312 } 3313 /* 3314 * drivers can need as many as 3315 * two sentinels 3316 */ 3317 MPASS(ndesc <= pi.ipi_nsegs + 2); 3318 MPASS(pi.ipi_new_pidx != pidx); 3319 MPASS(ndesc > 0); 3320 txq->ift_in_use += ndesc; 3321 3322 /* 3323 * We update the last software descriptor again here because there may 3324 * be a sentinel and/or there may be more mbufs than segments 3325 */ 3326 txq->ift_pidx = pi.ipi_new_pidx; 3327 txq->ift_npending += pi.ipi_ndescs; 3328 } else if (__predict_false(err == EFBIG && remap < 2)) { 3329 *m_headp = m_head = iflib_remove_mbuf(txq); 3330 remap = 1; 3331 txq->ift_txd_encap_efbig++; 3332 goto defrag; 3333 } else 3334 DBG_COUNTER_INC(encap_txd_encap_fail); 3335 return (err); 3336 3337 defrag_failed: 3338 txq->ift_mbuf_defrag_failed++; 3339 txq->ift_map_failed++; 3340 m_freem(*m_headp); 3341 DBG_COUNTER_INC(tx_frees); 3342 *m_headp = NULL; 3343 return (ENOMEM); 3344 } 3345 3346 static void 3347 iflib_tx_desc_free(iflib_txq_t txq, int n) 3348 { 3349 int hasmap; 3350 uint32_t qsize, cidx, mask, gen; 3351 struct mbuf *m, **ifsd_m; 3352 uint8_t *ifsd_flags; 3353 bus_dmamap_t *ifsd_map; 3354 bool do_prefetch; 3355 3356 cidx = txq->ift_cidx; 3357 gen = txq->ift_gen; 3358 qsize = txq->ift_size; 3359 mask = qsize-1; 3360 hasmap = txq->ift_sds.ifsd_map != NULL; 3361 ifsd_flags = txq->ift_sds.ifsd_flags; 3362 ifsd_m = txq->ift_sds.ifsd_m; 3363 ifsd_map = txq->ift_sds.ifsd_map; 3364 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3365 3366 while (n--) { 3367 if (do_prefetch) { 3368 prefetch(ifsd_m[(cidx + 3) & mask]); 3369 prefetch(ifsd_m[(cidx + 4) & mask]); 3370 } 3371 if (ifsd_m[cidx] != NULL) { 3372 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3373 prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]); 3374 if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) { 3375 /* 3376 * does it matter if it's not the TSO tag? If so we'll 3377 * have to add the type to flags 3378 */ 3379 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]); 3380 ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED; 3381 } 3382 if ((m = ifsd_m[cidx]) != NULL) { 3383 /* XXX we don't support any drivers that batch packets yet */ 3384 MPASS(m->m_nextpkt == NULL); 3385 /* if the number of clusters exceeds the number of segments 3386 * there won't be space on the ring to save a pointer to each 3387 * cluster so we simply free the list here 3388 */ 3389 if (m->m_flags & M_TOOBIG) { 3390 m_freem(m); 3391 } else { 3392 m_free(m); 3393 } 3394 ifsd_m[cidx] = NULL; 3395 #if MEMORY_LOGGING 3396 txq->ift_dequeued++; 3397 #endif 3398 DBG_COUNTER_INC(tx_frees); 3399 } 3400 } 3401 if (__predict_false(++cidx == qsize)) { 3402 cidx = 0; 3403 gen = 0; 3404 } 3405 } 3406 txq->ift_cidx = cidx; 3407 txq->ift_gen = gen; 3408 } 3409 3410 static __inline int 3411 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3412 { 3413 int reclaim; 3414 if_ctx_t ctx = txq->ift_ctx; 3415 3416 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3417 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3418 3419 /* 3420 * Need a rate-limiting check so that this isn't called every time 3421 */ 3422 iflib_tx_credits_update(ctx, txq); 3423 reclaim = DESC_RECLAIMABLE(txq); 3424 3425 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3426 #ifdef INVARIANTS 3427 if (iflib_verbose_debug) { 3428 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3429 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3430 reclaim, thresh); 3431 3432 } 3433 #endif 3434 return (0); 3435 } 3436 iflib_tx_desc_free(txq, reclaim); 3437 txq->ift_cleaned += reclaim; 3438 txq->ift_in_use -= reclaim; 3439 3440 return (reclaim); 3441 } 3442 3443 static struct mbuf ** 3444 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3445 { 3446 int next, size; 3447 struct mbuf **items; 3448 3449 size = r->size; 3450 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3451 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3452 3453 prefetch(items[(cidx + offset) & (size-1)]); 3454 if (remaining > 1) { 3455 prefetch2cachelines(&items[next]); 3456 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3457 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3458 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3459 } 3460 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3461 } 3462 3463 static void 3464 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3465 { 3466 3467 ifmp_ring_check_drainage(txq->ift_br, budget); 3468 } 3469 3470 static uint32_t 3471 iflib_txq_can_drain(struct ifmp_ring *r) 3472 { 3473 iflib_txq_t txq = r->cookie; 3474 if_ctx_t ctx = txq->ift_ctx; 3475 3476 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) || 3477 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)); 3478 } 3479 3480 static uint32_t 3481 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3482 { 3483 iflib_txq_t txq = r->cookie; 3484 if_ctx_t ctx = txq->ift_ctx; 3485 struct ifnet *ifp = ctx->ifc_ifp; 3486 struct mbuf **mp, *m; 3487 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail; 3488 int reclaimed, err, in_use_prev, desc_used; 3489 bool do_prefetch, ring, rang; 3490 3491 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3492 !LINK_ACTIVE(ctx))) { 3493 DBG_COUNTER_INC(txq_drain_notready); 3494 return (0); 3495 } 3496 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3497 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3498 avail = IDXDIFF(pidx, cidx, r->size); 3499 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3500 DBG_COUNTER_INC(txq_drain_flushing); 3501 for (i = 0; i < avail; i++) { 3502 m_free(r->items[(cidx + i) & (r->size-1)]); 3503 r->items[(cidx + i) & (r->size-1)] = NULL; 3504 } 3505 return (avail); 3506 } 3507 3508 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3509 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3510 CALLOUT_LOCK(txq); 3511 callout_stop(&txq->ift_timer); 3512 CALLOUT_UNLOCK(txq); 3513 DBG_COUNTER_INC(txq_drain_oactive); 3514 return (0); 3515 } 3516 if (reclaimed) 3517 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3518 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3519 count = MIN(avail, TX_BATCH_SIZE); 3520 #ifdef INVARIANTS 3521 if (iflib_verbose_debug) 3522 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3523 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3524 #endif 3525 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3526 avail = TXQ_AVAIL(txq); 3527 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) { 3528 int pidx_prev, rem = do_prefetch ? count - i : 0; 3529 3530 mp = _ring_peek_one(r, cidx, i, rem); 3531 MPASS(mp != NULL && *mp != NULL); 3532 if (__predict_false(*mp == (struct mbuf *)txq)) { 3533 consumed++; 3534 reclaimed++; 3535 continue; 3536 } 3537 in_use_prev = txq->ift_in_use; 3538 pidx_prev = txq->ift_pidx; 3539 err = iflib_encap(txq, mp); 3540 if (__predict_false(err)) { 3541 DBG_COUNTER_INC(txq_drain_encapfail); 3542 /* no room - bail out */ 3543 if (err == ENOBUFS) 3544 break; 3545 consumed++; 3546 DBG_COUNTER_INC(txq_drain_encapfail); 3547 /* we can't send this packet - skip it */ 3548 continue; 3549 } 3550 consumed++; 3551 pkt_sent++; 3552 m = *mp; 3553 DBG_COUNTER_INC(tx_sent); 3554 bytes_sent += m->m_pkthdr.len; 3555 mcast_sent += !!(m->m_flags & M_MCAST); 3556 avail = TXQ_AVAIL(txq); 3557 3558 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3559 desc_used += (txq->ift_in_use - in_use_prev); 3560 ETHER_BPF_MTAP(ifp, m); 3561 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3562 break; 3563 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3564 } 3565 3566 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3567 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3568 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3569 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3570 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3571 if (mcast_sent) 3572 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3573 #ifdef INVARIANTS 3574 if (iflib_verbose_debug) 3575 printf("consumed=%d\n", consumed); 3576 #endif 3577 return (consumed); 3578 } 3579 3580 static uint32_t 3581 iflib_txq_drain_always(struct ifmp_ring *r) 3582 { 3583 return (1); 3584 } 3585 3586 static uint32_t 3587 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3588 { 3589 int i, avail; 3590 struct mbuf **mp; 3591 iflib_txq_t txq; 3592 3593 txq = r->cookie; 3594 3595 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3596 CALLOUT_LOCK(txq); 3597 callout_stop(&txq->ift_timer); 3598 CALLOUT_UNLOCK(txq); 3599 3600 avail = IDXDIFF(pidx, cidx, r->size); 3601 for (i = 0; i < avail; i++) { 3602 mp = _ring_peek_one(r, cidx, i, avail - i); 3603 if (__predict_false(*mp == (struct mbuf *)txq)) 3604 continue; 3605 m_freem(*mp); 3606 } 3607 MPASS(ifmp_ring_is_stalled(r) == 0); 3608 return (avail); 3609 } 3610 3611 static void 3612 iflib_ifmp_purge(iflib_txq_t txq) 3613 { 3614 struct ifmp_ring *r; 3615 3616 r = txq->ift_br; 3617 r->drain = iflib_txq_drain_free; 3618 r->can_drain = iflib_txq_drain_always; 3619 3620 ifmp_ring_check_drainage(r, r->size); 3621 3622 r->drain = iflib_txq_drain; 3623 r->can_drain = iflib_txq_can_drain; 3624 } 3625 3626 static void 3627 _task_fn_tx(void *context) 3628 { 3629 iflib_txq_t txq = context; 3630 if_ctx_t ctx = txq->ift_ctx; 3631 struct ifnet *ifp = ctx->ifc_ifp; 3632 int rc; 3633 3634 #ifdef IFLIB_DIAGNOSTICS 3635 txq->ift_cpu_exec_count[curcpu]++; 3636 #endif 3637 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3638 return; 3639 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 3640 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3641 netmap_tx_irq(ifp, txq->ift_id); 3642 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3643 return; 3644 } 3645 if (txq->ift_db_pending) 3646 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE); 3647 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3648 if (ctx->ifc_flags & IFC_LEGACY) 3649 IFDI_INTR_ENABLE(ctx); 3650 else { 3651 rc = IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3652 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3653 } 3654 } 3655 3656 static void 3657 _task_fn_rx(void *context) 3658 { 3659 iflib_rxq_t rxq = context; 3660 if_ctx_t ctx = rxq->ifr_ctx; 3661 bool more; 3662 int rc; 3663 uint16_t budget; 3664 3665 #ifdef IFLIB_DIAGNOSTICS 3666 rxq->ifr_cpu_exec_count[curcpu]++; 3667 #endif 3668 DBG_COUNTER_INC(task_fn_rxs); 3669 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3670 return; 3671 more = true; 3672 #ifdef DEV_NETMAP 3673 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) { 3674 u_int work = 0; 3675 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) { 3676 more = false; 3677 } 3678 } 3679 #endif 3680 budget = ctx->ifc_sysctl_rx_budget; 3681 if (budget == 0) 3682 budget = 16; /* XXX */ 3683 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) { 3684 if (ctx->ifc_flags & IFC_LEGACY) 3685 IFDI_INTR_ENABLE(ctx); 3686 else { 3687 DBG_COUNTER_INC(rx_intr_enables); 3688 rc = IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3689 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3690 } 3691 } 3692 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3693 return; 3694 if (more) 3695 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3696 } 3697 3698 static void 3699 _task_fn_admin(void *context) 3700 { 3701 if_ctx_t ctx = context; 3702 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3703 iflib_txq_t txq; 3704 int i; 3705 3706 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) { 3707 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3708 return; 3709 } 3710 } 3711 3712 CTX_LOCK(ctx); 3713 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3714 CALLOUT_LOCK(txq); 3715 callout_stop(&txq->ift_timer); 3716 CALLOUT_UNLOCK(txq); 3717 } 3718 IFDI_UPDATE_ADMIN_STATUS(ctx); 3719 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3720 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); 3721 IFDI_LINK_INTR_ENABLE(ctx); 3722 if (ctx->ifc_flags & IFC_DO_RESET) { 3723 ctx->ifc_flags &= ~IFC_DO_RESET; 3724 iflib_if_init_locked(ctx); 3725 } 3726 CTX_UNLOCK(ctx); 3727 3728 if (LINK_ACTIVE(ctx) == 0) 3729 return; 3730 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3731 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3732 } 3733 3734 3735 static void 3736 _task_fn_iov(void *context) 3737 { 3738 if_ctx_t ctx = context; 3739 3740 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3741 return; 3742 3743 CTX_LOCK(ctx); 3744 IFDI_VFLR_HANDLE(ctx); 3745 CTX_UNLOCK(ctx); 3746 } 3747 3748 static int 3749 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3750 { 3751 int err; 3752 if_int_delay_info_t info; 3753 if_ctx_t ctx; 3754 3755 info = (if_int_delay_info_t)arg1; 3756 ctx = info->iidi_ctx; 3757 info->iidi_req = req; 3758 info->iidi_oidp = oidp; 3759 CTX_LOCK(ctx); 3760 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3761 CTX_UNLOCK(ctx); 3762 return (err); 3763 } 3764 3765 /********************************************************************* 3766 * 3767 * IFNET FUNCTIONS 3768 * 3769 **********************************************************************/ 3770 3771 static void 3772 iflib_if_init_locked(if_ctx_t ctx) 3773 { 3774 iflib_stop(ctx); 3775 iflib_init_locked(ctx); 3776 } 3777 3778 3779 static void 3780 iflib_if_init(void *arg) 3781 { 3782 if_ctx_t ctx = arg; 3783 3784 CTX_LOCK(ctx); 3785 iflib_if_init_locked(ctx); 3786 CTX_UNLOCK(ctx); 3787 } 3788 3789 static int 3790 iflib_if_transmit(if_t ifp, struct mbuf *m) 3791 { 3792 if_ctx_t ctx = if_getsoftc(ifp); 3793 3794 iflib_txq_t txq; 3795 int err, qidx; 3796 3797 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3798 DBG_COUNTER_INC(tx_frees); 3799 m_freem(m); 3800 return (ENOBUFS); 3801 } 3802 3803 MPASS(m->m_nextpkt == NULL); 3804 qidx = 0; 3805 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m)) 3806 qidx = QIDX(ctx, m); 3807 /* 3808 * XXX calculate buf_ring based on flowid (divvy up bits?) 3809 */ 3810 txq = &ctx->ifc_txqs[qidx]; 3811 3812 #ifdef DRIVER_BACKPRESSURE 3813 if (txq->ift_closed) { 3814 while (m != NULL) { 3815 next = m->m_nextpkt; 3816 m->m_nextpkt = NULL; 3817 m_freem(m); 3818 m = next; 3819 } 3820 return (ENOBUFS); 3821 } 3822 #endif 3823 #ifdef notyet 3824 qidx = count = 0; 3825 mp = marr; 3826 next = m; 3827 do { 3828 count++; 3829 next = next->m_nextpkt; 3830 } while (next != NULL); 3831 3832 if (count > nitems(marr)) 3833 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3834 /* XXX check nextpkt */ 3835 m_freem(m); 3836 /* XXX simplify for now */ 3837 DBG_COUNTER_INC(tx_frees); 3838 return (ENOBUFS); 3839 } 3840 for (next = m, i = 0; next != NULL; i++) { 3841 mp[i] = next; 3842 next = next->m_nextpkt; 3843 mp[i]->m_nextpkt = NULL; 3844 } 3845 #endif 3846 DBG_COUNTER_INC(tx_seen); 3847 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE); 3848 3849 GROUPTASK_ENQUEUE(&txq->ift_task); 3850 if (err) { 3851 /* support forthcoming later */ 3852 #ifdef DRIVER_BACKPRESSURE 3853 txq->ift_closed = TRUE; 3854 #endif 3855 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3856 m_freem(m); 3857 } 3858 3859 return (err); 3860 } 3861 3862 static void 3863 iflib_if_qflush(if_t ifp) 3864 { 3865 if_ctx_t ctx = if_getsoftc(ifp); 3866 iflib_txq_t txq = ctx->ifc_txqs; 3867 int i; 3868 3869 CTX_LOCK(ctx); 3870 ctx->ifc_flags |= IFC_QFLUSH; 3871 CTX_UNLOCK(ctx); 3872 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 3873 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 3874 iflib_txq_check_drain(txq, 0); 3875 CTX_LOCK(ctx); 3876 ctx->ifc_flags &= ~IFC_QFLUSH; 3877 CTX_UNLOCK(ctx); 3878 3879 if_qflush(ifp); 3880 } 3881 3882 3883 #define IFCAP_FLAGS (IFCAP_TXCSUM_IPV6 | IFCAP_RXCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 3884 IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 3885 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO) 3886 3887 static int 3888 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 3889 { 3890 if_ctx_t ctx = if_getsoftc(ifp); 3891 struct ifreq *ifr = (struct ifreq *)data; 3892 #if defined(INET) || defined(INET6) 3893 struct ifaddr *ifa = (struct ifaddr *)data; 3894 #endif 3895 bool avoid_reset = FALSE; 3896 int err = 0, reinit = 0, bits; 3897 3898 switch (command) { 3899 case SIOCSIFADDR: 3900 #ifdef INET 3901 if (ifa->ifa_addr->sa_family == AF_INET) 3902 avoid_reset = TRUE; 3903 #endif 3904 #ifdef INET6 3905 if (ifa->ifa_addr->sa_family == AF_INET6) 3906 avoid_reset = TRUE; 3907 #endif 3908 /* 3909 ** Calling init results in link renegotiation, 3910 ** so we avoid doing it when possible. 3911 */ 3912 if (avoid_reset) { 3913 if_setflagbits(ifp, IFF_UP,0); 3914 if (!(if_getdrvflags(ifp)& IFF_DRV_RUNNING)) 3915 reinit = 1; 3916 #ifdef INET 3917 if (!(if_getflags(ifp) & IFF_NOARP)) 3918 arp_ifinit(ifp, ifa); 3919 #endif 3920 } else 3921 err = ether_ioctl(ifp, command, data); 3922 break; 3923 case SIOCSIFMTU: 3924 CTX_LOCK(ctx); 3925 if (ifr->ifr_mtu == if_getmtu(ifp)) { 3926 CTX_UNLOCK(ctx); 3927 break; 3928 } 3929 bits = if_getdrvflags(ifp); 3930 /* stop the driver and free any clusters before proceeding */ 3931 iflib_stop(ctx); 3932 3933 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 3934 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 3935 ctx->ifc_flags |= IFC_MULTISEG; 3936 else 3937 ctx->ifc_flags &= ~IFC_MULTISEG; 3938 err = if_setmtu(ifp, ifr->ifr_mtu); 3939 } 3940 iflib_init_locked(ctx); 3941 if_setdrvflags(ifp, bits); 3942 CTX_UNLOCK(ctx); 3943 break; 3944 case SIOCSIFFLAGS: 3945 CTX_LOCK(ctx); 3946 if (if_getflags(ifp) & IFF_UP) { 3947 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3948 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 3949 (IFF_PROMISC | IFF_ALLMULTI)) { 3950 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 3951 } 3952 } else 3953 reinit = 1; 3954 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3955 iflib_stop(ctx); 3956 } 3957 ctx->ifc_if_flags = if_getflags(ifp); 3958 CTX_UNLOCK(ctx); 3959 break; 3960 case SIOCADDMULTI: 3961 case SIOCDELMULTI: 3962 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3963 CTX_LOCK(ctx); 3964 IFDI_INTR_DISABLE(ctx); 3965 IFDI_MULTI_SET(ctx); 3966 IFDI_INTR_ENABLE(ctx); 3967 CTX_UNLOCK(ctx); 3968 } 3969 break; 3970 case SIOCSIFMEDIA: 3971 CTX_LOCK(ctx); 3972 IFDI_MEDIA_SET(ctx); 3973 CTX_UNLOCK(ctx); 3974 /* falls thru */ 3975 case SIOCGIFMEDIA: 3976 case SIOCGIFXMEDIA: 3977 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command); 3978 break; 3979 case SIOCGI2C: 3980 { 3981 struct ifi2creq i2c; 3982 3983 err = copyin(ifr->ifr_data, &i2c, sizeof(i2c)); 3984 if (err != 0) 3985 break; 3986 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 3987 err = EINVAL; 3988 break; 3989 } 3990 if (i2c.len > sizeof(i2c.data)) { 3991 err = EINVAL; 3992 break; 3993 } 3994 3995 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 3996 err = copyout(&i2c, ifr->ifr_data, sizeof(i2c)); 3997 break; 3998 } 3999 case SIOCSIFCAP: 4000 { 4001 int mask, setmask; 4002 4003 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 4004 setmask = 0; 4005 #ifdef TCP_OFFLOAD 4006 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4007 #endif 4008 setmask |= (mask & IFCAP_FLAGS); 4009 4010 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) 4011 setmask |= (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4012 if ((mask & IFCAP_WOL) && 4013 (if_getcapabilities(ifp) & IFCAP_WOL) != 0) 4014 setmask |= (mask & (IFCAP_WOL_MCAST|IFCAP_WOL_MAGIC)); 4015 if_vlancap(ifp); 4016 /* 4017 * want to ensure that traffic has stopped before we change any of the flags 4018 */ 4019 if (setmask) { 4020 CTX_LOCK(ctx); 4021 bits = if_getdrvflags(ifp); 4022 if (bits & IFF_DRV_RUNNING) 4023 iflib_stop(ctx); 4024 if_togglecapenable(ifp, setmask); 4025 if (bits & IFF_DRV_RUNNING) 4026 iflib_init_locked(ctx); 4027 if_setdrvflags(ifp, bits); 4028 CTX_UNLOCK(ctx); 4029 } 4030 break; 4031 } 4032 case SIOCGPRIVATE_0: 4033 case SIOCSDRVSPEC: 4034 case SIOCGDRVSPEC: 4035 CTX_LOCK(ctx); 4036 err = IFDI_PRIV_IOCTL(ctx, command, data); 4037 CTX_UNLOCK(ctx); 4038 break; 4039 default: 4040 err = ether_ioctl(ifp, command, data); 4041 break; 4042 } 4043 if (reinit) 4044 iflib_if_init(ctx); 4045 return (err); 4046 } 4047 4048 static uint64_t 4049 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4050 { 4051 if_ctx_t ctx = if_getsoftc(ifp); 4052 4053 return (IFDI_GET_COUNTER(ctx, cnt)); 4054 } 4055 4056 /********************************************************************* 4057 * 4058 * OTHER FUNCTIONS EXPORTED TO THE STACK 4059 * 4060 **********************************************************************/ 4061 4062 static void 4063 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4064 { 4065 if_ctx_t ctx = if_getsoftc(ifp); 4066 4067 if ((void *)ctx != arg) 4068 return; 4069 4070 if ((vtag == 0) || (vtag > 4095)) 4071 return; 4072 4073 CTX_LOCK(ctx); 4074 IFDI_VLAN_REGISTER(ctx, vtag); 4075 /* Re-init to load the changes */ 4076 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4077 iflib_if_init_locked(ctx); 4078 CTX_UNLOCK(ctx); 4079 } 4080 4081 static void 4082 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4083 { 4084 if_ctx_t ctx = if_getsoftc(ifp); 4085 4086 if ((void *)ctx != arg) 4087 return; 4088 4089 if ((vtag == 0) || (vtag > 4095)) 4090 return; 4091 4092 CTX_LOCK(ctx); 4093 IFDI_VLAN_UNREGISTER(ctx, vtag); 4094 /* Re-init to load the changes */ 4095 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4096 iflib_if_init_locked(ctx); 4097 CTX_UNLOCK(ctx); 4098 } 4099 4100 static void 4101 iflib_led_func(void *arg, int onoff) 4102 { 4103 if_ctx_t ctx = arg; 4104 4105 CTX_LOCK(ctx); 4106 IFDI_LED_FUNC(ctx, onoff); 4107 CTX_UNLOCK(ctx); 4108 } 4109 4110 /********************************************************************* 4111 * 4112 * BUS FUNCTION DEFINITIONS 4113 * 4114 **********************************************************************/ 4115 4116 int 4117 iflib_device_probe(device_t dev) 4118 { 4119 pci_vendor_info_t *ent; 4120 4121 uint16_t pci_vendor_id, pci_device_id; 4122 uint16_t pci_subvendor_id, pci_subdevice_id; 4123 uint16_t pci_rev_id; 4124 if_shared_ctx_t sctx; 4125 4126 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4127 return (ENOTSUP); 4128 4129 pci_vendor_id = pci_get_vendor(dev); 4130 pci_device_id = pci_get_device(dev); 4131 pci_subvendor_id = pci_get_subvendor(dev); 4132 pci_subdevice_id = pci_get_subdevice(dev); 4133 pci_rev_id = pci_get_revid(dev); 4134 if (sctx->isc_parse_devinfo != NULL) 4135 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4136 4137 ent = sctx->isc_vendor_info; 4138 while (ent->pvi_vendor_id != 0) { 4139 if (pci_vendor_id != ent->pvi_vendor_id) { 4140 ent++; 4141 continue; 4142 } 4143 if ((pci_device_id == ent->pvi_device_id) && 4144 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4145 (ent->pvi_subvendor_id == 0)) && 4146 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4147 (ent->pvi_subdevice_id == 0)) && 4148 ((pci_rev_id == ent->pvi_rev_id) || 4149 (ent->pvi_rev_id == 0))) { 4150 4151 device_set_desc_copy(dev, ent->pvi_name); 4152 /* this needs to be changed to zero if the bus probing code 4153 * ever stops re-probing on best match because the sctx 4154 * may have its values over written by register calls 4155 * in subsequent probes 4156 */ 4157 return (BUS_PROBE_DEFAULT); 4158 } 4159 ent++; 4160 } 4161 return (ENXIO); 4162 } 4163 4164 int 4165 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4166 { 4167 int err, rid, msix, msix_bar; 4168 if_ctx_t ctx; 4169 if_t ifp; 4170 if_softc_ctx_t scctx; 4171 int i; 4172 uint16_t main_txq; 4173 uint16_t main_rxq; 4174 4175 4176 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4177 4178 if (sc == NULL) { 4179 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4180 device_set_softc(dev, ctx); 4181 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4182 } 4183 4184 ctx->ifc_sctx = sctx; 4185 ctx->ifc_dev = dev; 4186 ctx->ifc_softc = sc; 4187 4188 if ((err = iflib_register(ctx)) != 0) { 4189 device_printf(dev, "iflib_register failed %d\n", err); 4190 return (err); 4191 } 4192 iflib_add_device_sysctl_pre(ctx); 4193 4194 scctx = &ctx->ifc_softc_ctx; 4195 ifp = ctx->ifc_ifp; 4196 4197 /* 4198 * XXX sanity check that ntxd & nrxd are a power of 2 4199 */ 4200 if (ctx->ifc_sysctl_ntxqs != 0) 4201 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4202 if (ctx->ifc_sysctl_nrxqs != 0) 4203 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4204 4205 for (i = 0; i < sctx->isc_ntxqs; i++) { 4206 if (ctx->ifc_sysctl_ntxds[i] != 0) 4207 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4208 else 4209 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4210 } 4211 4212 for (i = 0; i < sctx->isc_nrxqs; i++) { 4213 if (ctx->ifc_sysctl_nrxds[i] != 0) 4214 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4215 else 4216 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4217 } 4218 4219 for (i = 0; i < sctx->isc_nrxqs; i++) { 4220 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4221 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4222 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4223 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4224 } 4225 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4226 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4227 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4228 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4229 } 4230 } 4231 4232 for (i = 0; i < sctx->isc_ntxqs; i++) { 4233 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4234 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4235 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4236 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4237 } 4238 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4239 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4240 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4241 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4242 } 4243 } 4244 4245 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4246 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4247 return (err); 4248 } 4249 _iflib_pre_assert(scctx); 4250 ctx->ifc_txrx = *scctx->isc_txrx; 4251 4252 #ifdef INVARIANTS 4253 MPASS(scctx->isc_capenable); 4254 if (scctx->isc_capenable & IFCAP_TXCSUM) 4255 MPASS(scctx->isc_tx_csum_flags); 4256 #endif 4257 4258 if_setcapabilities(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4259 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4260 4261 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4262 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4263 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4264 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4265 4266 #ifdef ACPI_DMAR 4267 if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL) 4268 ctx->ifc_flags |= IFC_DMAR; 4269 #elif !(defined(__i386__) || defined(__amd64__)) 4270 /* set unconditionally for !x86 */ 4271 ctx->ifc_flags |= IFC_DMAR; 4272 #endif 4273 4274 msix_bar = scctx->isc_msix_bar; 4275 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4276 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4277 4278 /* XXX change for per-queue sizes */ 4279 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n", 4280 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4281 for (i = 0; i < sctx->isc_nrxqs; i++) { 4282 if (!powerof2(scctx->isc_nrxd[i])) { 4283 /* round down instead? */ 4284 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4285 err = EINVAL; 4286 goto fail; 4287 } 4288 } 4289 for (i = 0; i < sctx->isc_ntxqs; i++) { 4290 if (!powerof2(scctx->isc_ntxd[i])) { 4291 device_printf(dev, 4292 "# tx descriptors must be a power of 2"); 4293 err = EINVAL; 4294 goto fail; 4295 } 4296 } 4297 4298 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4299 MAX_SINGLE_PACKET_FRACTION) 4300 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4301 MAX_SINGLE_PACKET_FRACTION); 4302 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4303 MAX_SINGLE_PACKET_FRACTION) 4304 scctx->isc_tx_tso_segments_max = max(1, 4305 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4306 4307 /* 4308 * Protect the stack against modern hardware 4309 */ 4310 if (scctx->isc_tx_tso_size_max > FREEBSD_TSO_SIZE_MAX) 4311 scctx->isc_tx_tso_size_max = FREEBSD_TSO_SIZE_MAX; 4312 4313 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4314 ifp->if_hw_tsomaxsegcount = scctx->isc_tx_tso_segments_max; 4315 ifp->if_hw_tsomax = scctx->isc_tx_tso_size_max; 4316 ifp->if_hw_tsomaxsegsize = scctx->isc_tx_tso_segsize_max; 4317 if (scctx->isc_rss_table_size == 0) 4318 scctx->isc_rss_table_size = 64; 4319 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4320 4321 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4322 /* XXX format name */ 4323 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin"); 4324 4325 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4326 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4327 device_printf(dev, "Unable to fetch CPU list\n"); 4328 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4329 } 4330 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4331 4332 /* 4333 ** Now setup MSI or MSI/X, should 4334 ** return us the number of supported 4335 ** vectors. (Will be 1 for MSI) 4336 */ 4337 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4338 msix = scctx->isc_vectors; 4339 } else if (scctx->isc_msix_bar != 0) 4340 /* 4341 * The simple fact that isc_msix_bar is not 0 does not mean we 4342 * we have a good value there that is known to work. 4343 */ 4344 msix = iflib_msix_init(ctx); 4345 else { 4346 scctx->isc_vectors = 1; 4347 scctx->isc_ntxqsets = 1; 4348 scctx->isc_nrxqsets = 1; 4349 scctx->isc_intr = IFLIB_INTR_LEGACY; 4350 msix = 0; 4351 } 4352 /* Get memory for the station queues */ 4353 if ((err = iflib_queues_alloc(ctx))) { 4354 device_printf(dev, "Unable to allocate queue memory\n"); 4355 goto fail; 4356 } 4357 4358 if ((err = iflib_qset_structures_setup(ctx))) { 4359 device_printf(dev, "qset structure setup failed %d\n", err); 4360 goto fail_queues; 4361 } 4362 4363 /* 4364 * Group taskqueues aren't properly set up until SMP is started, 4365 * so we disable interrupts until we can handle them post 4366 * SI_SUB_SMP. 4367 * 4368 * XXX: disabling interrupts doesn't actually work, at least for 4369 * the non-MSI case. When they occur before SI_SUB_SMP completes, 4370 * we do null handling and depend on this not causing too large an 4371 * interrupt storm. 4372 */ 4373 IFDI_INTR_DISABLE(ctx); 4374 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) { 4375 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err); 4376 goto fail_intr_free; 4377 } 4378 if (msix <= 1) { 4379 rid = 0; 4380 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4381 MPASS(msix == 1); 4382 rid = 1; 4383 } 4384 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4385 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4386 goto fail_intr_free; 4387 } 4388 } 4389 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4390 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4391 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4392 goto fail_detach; 4393 } 4394 if ((err = iflib_netmap_attach(ctx))) { 4395 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4396 goto fail_detach; 4397 } 4398 *ctxp = ctx; 4399 4400 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4401 iflib_add_device_sysctl_post(ctx); 4402 ctx->ifc_flags |= IFC_INIT_DONE; 4403 return (0); 4404 fail_detach: 4405 ether_ifdetach(ctx->ifc_ifp); 4406 fail_intr_free: 4407 if (scctx->isc_intr == IFLIB_INTR_MSIX || scctx->isc_intr == IFLIB_INTR_MSI) 4408 pci_release_msi(ctx->ifc_dev); 4409 fail_queues: 4410 /* XXX free queues */ 4411 fail: 4412 IFDI_DETACH(ctx); 4413 return (err); 4414 } 4415 4416 int 4417 iflib_device_attach(device_t dev) 4418 { 4419 if_ctx_t ctx; 4420 if_shared_ctx_t sctx; 4421 4422 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4423 return (ENOTSUP); 4424 4425 pci_enable_busmaster(dev); 4426 4427 return (iflib_device_register(dev, NULL, sctx, &ctx)); 4428 } 4429 4430 int 4431 iflib_device_deregister(if_ctx_t ctx) 4432 { 4433 if_t ifp = ctx->ifc_ifp; 4434 iflib_txq_t txq; 4435 iflib_rxq_t rxq; 4436 device_t dev = ctx->ifc_dev; 4437 int i, j; 4438 struct taskqgroup *tqg; 4439 iflib_fl_t fl; 4440 4441 /* Make sure VLANS are not using driver */ 4442 if (if_vlantrunkinuse(ifp)) { 4443 device_printf(dev,"Vlan in use, detach first\n"); 4444 return (EBUSY); 4445 } 4446 4447 CTX_LOCK(ctx); 4448 ctx->ifc_in_detach = 1; 4449 iflib_stop(ctx); 4450 CTX_UNLOCK(ctx); 4451 4452 /* Unregister VLAN events */ 4453 if (ctx->ifc_vlan_attach_event != NULL) 4454 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4455 if (ctx->ifc_vlan_detach_event != NULL) 4456 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4457 4458 iflib_netmap_detach(ifp); 4459 ether_ifdetach(ifp); 4460 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4461 CTX_LOCK_DESTROY(ctx); 4462 if (ctx->ifc_led_dev != NULL) 4463 led_destroy(ctx->ifc_led_dev); 4464 /* XXX drain any dependent tasks */ 4465 tqg = qgroup_if_io_tqg; 4466 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4467 callout_drain(&txq->ift_timer); 4468 if (txq->ift_task.gt_uniq != NULL) 4469 taskqgroup_detach(tqg, &txq->ift_task); 4470 } 4471 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4472 if (rxq->ifr_task.gt_uniq != NULL) 4473 taskqgroup_detach(tqg, &rxq->ifr_task); 4474 4475 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4476 free(fl->ifl_rx_bitmap, M_IFLIB); 4477 4478 } 4479 tqg = qgroup_if_config_tqg; 4480 if (ctx->ifc_admin_task.gt_uniq != NULL) 4481 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4482 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4483 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4484 4485 IFDI_DETACH(ctx); 4486 device_set_softc(ctx->ifc_dev, NULL); 4487 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 4488 pci_release_msi(dev); 4489 } 4490 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 4491 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 4492 } 4493 if (ctx->ifc_msix_mem != NULL) { 4494 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 4495 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem); 4496 ctx->ifc_msix_mem = NULL; 4497 } 4498 4499 bus_generic_detach(dev); 4500 if_free(ifp); 4501 4502 iflib_tx_structures_free(ctx); 4503 iflib_rx_structures_free(ctx); 4504 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4505 free(ctx->ifc_softc, M_IFLIB); 4506 free(ctx, M_IFLIB); 4507 return (0); 4508 } 4509 4510 4511 int 4512 iflib_device_detach(device_t dev) 4513 { 4514 if_ctx_t ctx = device_get_softc(dev); 4515 4516 return (iflib_device_deregister(ctx)); 4517 } 4518 4519 int 4520 iflib_device_suspend(device_t dev) 4521 { 4522 if_ctx_t ctx = device_get_softc(dev); 4523 4524 CTX_LOCK(ctx); 4525 IFDI_SUSPEND(ctx); 4526 CTX_UNLOCK(ctx); 4527 4528 return bus_generic_suspend(dev); 4529 } 4530 int 4531 iflib_device_shutdown(device_t dev) 4532 { 4533 if_ctx_t ctx = device_get_softc(dev); 4534 4535 CTX_LOCK(ctx); 4536 IFDI_SHUTDOWN(ctx); 4537 CTX_UNLOCK(ctx); 4538 4539 return bus_generic_suspend(dev); 4540 } 4541 4542 4543 int 4544 iflib_device_resume(device_t dev) 4545 { 4546 if_ctx_t ctx = device_get_softc(dev); 4547 iflib_txq_t txq = ctx->ifc_txqs; 4548 4549 CTX_LOCK(ctx); 4550 IFDI_RESUME(ctx); 4551 iflib_init_locked(ctx); 4552 CTX_UNLOCK(ctx); 4553 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 4554 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4555 4556 return (bus_generic_resume(dev)); 4557 } 4558 4559 int 4560 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 4561 { 4562 int error; 4563 if_ctx_t ctx = device_get_softc(dev); 4564 4565 CTX_LOCK(ctx); 4566 error = IFDI_IOV_INIT(ctx, num_vfs, params); 4567 CTX_UNLOCK(ctx); 4568 4569 return (error); 4570 } 4571 4572 void 4573 iflib_device_iov_uninit(device_t dev) 4574 { 4575 if_ctx_t ctx = device_get_softc(dev); 4576 4577 CTX_LOCK(ctx); 4578 IFDI_IOV_UNINIT(ctx); 4579 CTX_UNLOCK(ctx); 4580 } 4581 4582 int 4583 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 4584 { 4585 int error; 4586 if_ctx_t ctx = device_get_softc(dev); 4587 4588 CTX_LOCK(ctx); 4589 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 4590 CTX_UNLOCK(ctx); 4591 4592 return (error); 4593 } 4594 4595 /********************************************************************* 4596 * 4597 * MODULE FUNCTION DEFINITIONS 4598 * 4599 **********************************************************************/ 4600 4601 /* 4602 * - Start a fast taskqueue thread for each core 4603 * - Start a taskqueue for control operations 4604 */ 4605 static int 4606 iflib_module_init(void) 4607 { 4608 return (0); 4609 } 4610 4611 static int 4612 iflib_module_event_handler(module_t mod, int what, void *arg) 4613 { 4614 int err; 4615 4616 switch (what) { 4617 case MOD_LOAD: 4618 if ((err = iflib_module_init()) != 0) 4619 return (err); 4620 break; 4621 case MOD_UNLOAD: 4622 return (EBUSY); 4623 default: 4624 return (EOPNOTSUPP); 4625 } 4626 4627 return (0); 4628 } 4629 4630 /********************************************************************* 4631 * 4632 * PUBLIC FUNCTION DEFINITIONS 4633 * ordered as in iflib.h 4634 * 4635 **********************************************************************/ 4636 4637 4638 static void 4639 _iflib_assert(if_shared_ctx_t sctx) 4640 { 4641 MPASS(sctx->isc_tx_maxsize); 4642 MPASS(sctx->isc_tx_maxsegsize); 4643 4644 MPASS(sctx->isc_rx_maxsize); 4645 MPASS(sctx->isc_rx_nsegments); 4646 MPASS(sctx->isc_rx_maxsegsize); 4647 4648 MPASS(sctx->isc_nrxd_min[0]); 4649 MPASS(sctx->isc_nrxd_max[0]); 4650 MPASS(sctx->isc_nrxd_default[0]); 4651 MPASS(sctx->isc_ntxd_min[0]); 4652 MPASS(sctx->isc_ntxd_max[0]); 4653 MPASS(sctx->isc_ntxd_default[0]); 4654 } 4655 4656 static void 4657 _iflib_pre_assert(if_softc_ctx_t scctx) 4658 { 4659 4660 MPASS(scctx->isc_txrx->ift_txd_encap); 4661 MPASS(scctx->isc_txrx->ift_txd_flush); 4662 MPASS(scctx->isc_txrx->ift_txd_credits_update); 4663 MPASS(scctx->isc_txrx->ift_rxd_available); 4664 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 4665 MPASS(scctx->isc_txrx->ift_rxd_refill); 4666 MPASS(scctx->isc_txrx->ift_rxd_flush); 4667 } 4668 4669 static int 4670 iflib_register(if_ctx_t ctx) 4671 { 4672 if_shared_ctx_t sctx = ctx->ifc_sctx; 4673 driver_t *driver = sctx->isc_driver; 4674 device_t dev = ctx->ifc_dev; 4675 if_t ifp; 4676 4677 _iflib_assert(sctx); 4678 4679 CTX_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 4680 4681 ifp = ctx->ifc_ifp = if_gethandle(IFT_ETHER); 4682 if (ifp == NULL) { 4683 device_printf(dev, "can not allocate ifnet structure\n"); 4684 return (ENOMEM); 4685 } 4686 4687 /* 4688 * Initialize our context's device specific methods 4689 */ 4690 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 4691 kobj_class_compile((kobj_class_t) driver); 4692 driver->refs++; 4693 4694 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 4695 if_setsoftc(ifp, ctx); 4696 if_setdev(ifp, dev); 4697 if_setinitfn(ifp, iflib_if_init); 4698 if_setioctlfn(ifp, iflib_if_ioctl); 4699 if_settransmitfn(ifp, iflib_if_transmit); 4700 if_setqflushfn(ifp, iflib_if_qflush); 4701 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 4702 4703 ctx->ifc_vlan_attach_event = 4704 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 4705 EVENTHANDLER_PRI_FIRST); 4706 ctx->ifc_vlan_detach_event = 4707 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 4708 EVENTHANDLER_PRI_FIRST); 4709 4710 ifmedia_init(&ctx->ifc_media, IFM_IMASK, 4711 iflib_media_change, iflib_media_status); 4712 4713 return (0); 4714 } 4715 4716 4717 static int 4718 iflib_queues_alloc(if_ctx_t ctx) 4719 { 4720 if_shared_ctx_t sctx = ctx->ifc_sctx; 4721 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4722 device_t dev = ctx->ifc_dev; 4723 int nrxqsets = scctx->isc_nrxqsets; 4724 int ntxqsets = scctx->isc_ntxqsets; 4725 iflib_txq_t txq; 4726 iflib_rxq_t rxq; 4727 iflib_fl_t fl = NULL; 4728 int i, j, cpu, err, txconf, rxconf; 4729 iflib_dma_info_t ifdip; 4730 uint32_t *rxqsizes = scctx->isc_rxqsizes; 4731 uint32_t *txqsizes = scctx->isc_txqsizes; 4732 uint8_t nrxqs = sctx->isc_nrxqs; 4733 uint8_t ntxqs = sctx->isc_ntxqs; 4734 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 4735 caddr_t *vaddrs; 4736 uint64_t *paddrs; 4737 struct ifmp_ring **brscp; 4738 4739 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 4740 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 4741 4742 brscp = NULL; 4743 txq = NULL; 4744 rxq = NULL; 4745 4746 /* Allocate the TX ring struct memory */ 4747 if (!(txq = 4748 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 4749 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 4750 device_printf(dev, "Unable to allocate TX ring memory\n"); 4751 err = ENOMEM; 4752 goto fail; 4753 } 4754 4755 /* Now allocate the RX */ 4756 if (!(rxq = 4757 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 4758 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 4759 device_printf(dev, "Unable to allocate RX ring memory\n"); 4760 err = ENOMEM; 4761 goto rx_fail; 4762 } 4763 4764 ctx->ifc_txqs = txq; 4765 ctx->ifc_rxqs = rxq; 4766 4767 /* 4768 * XXX handle allocation failure 4769 */ 4770 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 4771 /* Set up some basics */ 4772 4773 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 4774 device_printf(dev, "failed to allocate iflib_dma_info\n"); 4775 err = ENOMEM; 4776 goto err_tx_desc; 4777 } 4778 txq->ift_ifdi = ifdip; 4779 for (j = 0; j < ntxqs; j++, ifdip++) { 4780 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 4781 device_printf(dev, "Unable to allocate Descriptor memory\n"); 4782 err = ENOMEM; 4783 goto err_tx_desc; 4784 } 4785 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 4786 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 4787 } 4788 txq->ift_ctx = ctx; 4789 txq->ift_id = i; 4790 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 4791 txq->ift_br_offset = 1; 4792 } else { 4793 txq->ift_br_offset = 0; 4794 } 4795 /* XXX fix this */ 4796 txq->ift_timer.c_cpu = cpu; 4797 4798 if (iflib_txsd_alloc(txq)) { 4799 device_printf(dev, "Critical Failure setting up TX buffers\n"); 4800 err = ENOMEM; 4801 goto err_tx_desc; 4802 } 4803 4804 /* Initialize the TX lock */ 4805 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout", 4806 device_get_nameunit(dev), txq->ift_id); 4807 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 4808 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 4809 4810 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db", 4811 device_get_nameunit(dev), txq->ift_id); 4812 4813 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 4814 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 4815 if (err) { 4816 /* XXX free any allocated rings */ 4817 device_printf(dev, "Unable to allocate buf_ring\n"); 4818 goto err_tx_desc; 4819 } 4820 } 4821 4822 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 4823 /* Set up some basics */ 4824 4825 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 4826 device_printf(dev, "failed to allocate iflib_dma_info\n"); 4827 err = ENOMEM; 4828 goto err_tx_desc; 4829 } 4830 4831 rxq->ifr_ifdi = ifdip; 4832 /* XXX this needs to be changed if #rx queues != #tx queues */ 4833 rxq->ifr_ntxqirq = 1; 4834 rxq->ifr_txqid[0] = i; 4835 for (j = 0; j < nrxqs; j++, ifdip++) { 4836 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 4837 device_printf(dev, "Unable to allocate Descriptor memory\n"); 4838 err = ENOMEM; 4839 goto err_tx_desc; 4840 } 4841 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 4842 } 4843 rxq->ifr_ctx = ctx; 4844 rxq->ifr_id = i; 4845 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 4846 rxq->ifr_fl_offset = 1; 4847 } else { 4848 rxq->ifr_fl_offset = 0; 4849 } 4850 rxq->ifr_nfl = nfree_lists; 4851 if (!(fl = 4852 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 4853 device_printf(dev, "Unable to allocate free list memory\n"); 4854 err = ENOMEM; 4855 goto err_tx_desc; 4856 } 4857 rxq->ifr_fl = fl; 4858 for (j = 0; j < nfree_lists; j++) { 4859 fl[j].ifl_rxq = rxq; 4860 fl[j].ifl_id = j; 4861 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 4862 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 4863 } 4864 /* Allocate receive buffers for the ring*/ 4865 if (iflib_rxsd_alloc(rxq)) { 4866 device_printf(dev, 4867 "Critical Failure setting up receive buffers\n"); 4868 err = ENOMEM; 4869 goto err_rx_desc; 4870 } 4871 4872 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4873 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, M_WAITOK|M_ZERO); 4874 } 4875 4876 /* TXQs */ 4877 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 4878 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 4879 for (i = 0; i < ntxqsets; i++) { 4880 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 4881 4882 for (j = 0; j < ntxqs; j++, di++) { 4883 vaddrs[i*ntxqs + j] = di->idi_vaddr; 4884 paddrs[i*ntxqs + j] = di->idi_paddr; 4885 } 4886 } 4887 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 4888 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 4889 iflib_tx_structures_free(ctx); 4890 free(vaddrs, M_IFLIB); 4891 free(paddrs, M_IFLIB); 4892 goto err_rx_desc; 4893 } 4894 free(vaddrs, M_IFLIB); 4895 free(paddrs, M_IFLIB); 4896 4897 /* RXQs */ 4898 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 4899 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 4900 for (i = 0; i < nrxqsets; i++) { 4901 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 4902 4903 for (j = 0; j < nrxqs; j++, di++) { 4904 vaddrs[i*nrxqs + j] = di->idi_vaddr; 4905 paddrs[i*nrxqs + j] = di->idi_paddr; 4906 } 4907 } 4908 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 4909 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 4910 iflib_tx_structures_free(ctx); 4911 free(vaddrs, M_IFLIB); 4912 free(paddrs, M_IFLIB); 4913 goto err_rx_desc; 4914 } 4915 free(vaddrs, M_IFLIB); 4916 free(paddrs, M_IFLIB); 4917 4918 return (0); 4919 4920 /* XXX handle allocation failure changes */ 4921 err_rx_desc: 4922 err_tx_desc: 4923 if (ctx->ifc_rxqs != NULL) 4924 free(ctx->ifc_rxqs, M_IFLIB); 4925 ctx->ifc_rxqs = NULL; 4926 if (ctx->ifc_txqs != NULL) 4927 free(ctx->ifc_txqs, M_IFLIB); 4928 ctx->ifc_txqs = NULL; 4929 rx_fail: 4930 if (brscp != NULL) 4931 free(brscp, M_IFLIB); 4932 if (rxq != NULL) 4933 free(rxq, M_IFLIB); 4934 if (txq != NULL) 4935 free(txq, M_IFLIB); 4936 fail: 4937 return (err); 4938 } 4939 4940 static int 4941 iflib_tx_structures_setup(if_ctx_t ctx) 4942 { 4943 iflib_txq_t txq = ctx->ifc_txqs; 4944 int i; 4945 4946 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4947 iflib_txq_setup(txq); 4948 4949 return (0); 4950 } 4951 4952 static void 4953 iflib_tx_structures_free(if_ctx_t ctx) 4954 { 4955 iflib_txq_t txq = ctx->ifc_txqs; 4956 int i, j; 4957 4958 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 4959 iflib_txq_destroy(txq); 4960 for (j = 0; j < ctx->ifc_nhwtxqs; j++) 4961 iflib_dma_free(&txq->ift_ifdi[j]); 4962 } 4963 free(ctx->ifc_txqs, M_IFLIB); 4964 ctx->ifc_txqs = NULL; 4965 IFDI_QUEUES_FREE(ctx); 4966 } 4967 4968 /********************************************************************* 4969 * 4970 * Initialize all receive rings. 4971 * 4972 **********************************************************************/ 4973 static int 4974 iflib_rx_structures_setup(if_ctx_t ctx) 4975 { 4976 iflib_rxq_t rxq = ctx->ifc_rxqs; 4977 int q; 4978 #if defined(INET6) || defined(INET) 4979 int i, err; 4980 #endif 4981 4982 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 4983 #if defined(INET6) || defined(INET) 4984 tcp_lro_free(&rxq->ifr_lc); 4985 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 4986 TCP_LRO_ENTRIES, min(1024, 4987 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) { 4988 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n"); 4989 goto fail; 4990 } 4991 rxq->ifr_lro_enabled = TRUE; 4992 #endif 4993 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 4994 } 4995 return (0); 4996 #if defined(INET6) || defined(INET) 4997 fail: 4998 /* 4999 * Free RX software descriptors allocated so far, we will only handle 5000 * the rings that completed, the failing case will have 5001 * cleaned up for itself. 'q' failed, so its the terminus. 5002 */ 5003 rxq = ctx->ifc_rxqs; 5004 for (i = 0; i < q; ++i, rxq++) { 5005 iflib_rx_sds_free(rxq); 5006 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 5007 } 5008 return (err); 5009 #endif 5010 } 5011 5012 /********************************************************************* 5013 * 5014 * Free all receive rings. 5015 * 5016 **********************************************************************/ 5017 static void 5018 iflib_rx_structures_free(if_ctx_t ctx) 5019 { 5020 iflib_rxq_t rxq = ctx->ifc_rxqs; 5021 5022 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5023 iflib_rx_sds_free(rxq); 5024 } 5025 } 5026 5027 static int 5028 iflib_qset_structures_setup(if_ctx_t ctx) 5029 { 5030 int err; 5031 5032 if ((err = iflib_tx_structures_setup(ctx)) != 0) 5033 return (err); 5034 5035 if ((err = iflib_rx_structures_setup(ctx)) != 0) { 5036 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5037 iflib_tx_structures_free(ctx); 5038 iflib_rx_structures_free(ctx); 5039 } 5040 return (err); 5041 } 5042 5043 int 5044 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5045 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, char *name) 5046 { 5047 5048 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5049 } 5050 5051 #ifdef SMP 5052 static int 5053 find_nth(if_ctx_t ctx, int qid) 5054 { 5055 cpuset_t cpus; 5056 int i, cpuid, eqid, count; 5057 5058 CPU_COPY(&ctx->ifc_cpus, &cpus); 5059 count = CPU_COUNT(&cpus); 5060 eqid = qid % count; 5061 /* clear up to the qid'th bit */ 5062 for (i = 0; i < eqid; i++) { 5063 cpuid = CPU_FFS(&cpus); 5064 MPASS(cpuid != 0); 5065 CPU_CLR(cpuid-1, &cpus); 5066 } 5067 cpuid = CPU_FFS(&cpus); 5068 MPASS(cpuid != 0); 5069 return (cpuid-1); 5070 } 5071 5072 #ifdef SCHED_ULE 5073 extern struct cpu_group *cpu_top; /* CPU topology */ 5074 5075 static int 5076 find_child_with_core(int cpu, struct cpu_group *grp) 5077 { 5078 int i; 5079 5080 if (grp->cg_children == 0) 5081 return -1; 5082 5083 MPASS(grp->cg_child); 5084 for (i = 0; i < grp->cg_children; i++) { 5085 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5086 return i; 5087 } 5088 5089 return -1; 5090 } 5091 5092 /* 5093 * Find the nth thread on the specified core 5094 */ 5095 static int 5096 find_thread(int cpu, int thread_num) 5097 { 5098 struct cpu_group *grp; 5099 int i; 5100 cpuset_t cs; 5101 5102 grp = cpu_top; 5103 if (grp == NULL) 5104 return cpu; 5105 i = 0; 5106 while ((i = find_child_with_core(cpu, grp)) != -1) { 5107 /* If the child only has one cpu, don't descend */ 5108 if (grp->cg_child[i].cg_count <= 1) 5109 break; 5110 grp = &grp->cg_child[i]; 5111 } 5112 5113 /* If they don't share at least an L2 cache, use the same CPU */ 5114 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5115 return cpu; 5116 5117 /* Now pick one */ 5118 CPU_COPY(&grp->cg_mask, &cs); 5119 for (i = thread_num % grp->cg_count; i > 0; i--) { 5120 MPASS(CPU_FFS(&cs)); 5121 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5122 } 5123 MPASS(CPU_FFS(&cs)); 5124 return CPU_FFS(&cs) - 1; 5125 } 5126 #else 5127 static int 5128 find_thread(int cpu, int thread_num __unused) 5129 { 5130 return cpu; 5131 } 5132 #endif 5133 5134 static int 5135 get_thread_num(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5136 { 5137 switch (type) { 5138 case IFLIB_INTR_TX: 5139 /* TX queues get threads on the same core as the corresponding RX queue */ 5140 /* XXX handle multiple RX threads per core and more than two threads per core */ 5141 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5142 case IFLIB_INTR_RX: 5143 case IFLIB_INTR_RXTX: 5144 /* RX queues get the first thread on their core */ 5145 return qid / CPU_COUNT(&ctx->ifc_cpus); 5146 default: 5147 return -1; 5148 } 5149 } 5150 #else 5151 #define get_thread_num(ctx, type, qid) CPU_FIRST() 5152 #define find_thread(cpuid, tid) CPU_FIRST() 5153 #define find_nth(ctx, gid) CPU_FIRST() 5154 #endif 5155 5156 /* Just to avoid copy/paste */ 5157 static inline int 5158 iflib_irq_set_affinity(if_ctx_t ctx, int irq, iflib_intr_type_t type, int qid, 5159 struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, char *name) 5160 { 5161 int cpuid; 5162 int err, tid; 5163 5164 cpuid = find_nth(ctx, qid); 5165 tid = get_thread_num(ctx, type, qid); 5166 MPASS(tid >= 0); 5167 cpuid = find_thread(cpuid, tid); 5168 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, irq, name); 5169 if (err) { 5170 device_printf(ctx->ifc_dev, "taskqgroup_attach_cpu failed %d\n", err); 5171 return (err); 5172 } 5173 #ifdef notyet 5174 if (cpuid > ctx->ifc_cpuid_highest) 5175 ctx->ifc_cpuid_highest = cpuid; 5176 #endif 5177 return 0; 5178 } 5179 5180 int 5181 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 5182 iflib_intr_type_t type, driver_filter_t *filter, 5183 void *filter_arg, int qid, char *name) 5184 { 5185 struct grouptask *gtask; 5186 struct taskqgroup *tqg; 5187 iflib_filter_info_t info; 5188 gtask_fn_t *fn; 5189 int tqrid, err; 5190 driver_filter_t *intr_fast; 5191 void *q; 5192 5193 info = &ctx->ifc_filter_info; 5194 tqrid = rid; 5195 5196 switch (type) { 5197 /* XXX merge tx/rx for netmap? */ 5198 case IFLIB_INTR_TX: 5199 q = &ctx->ifc_txqs[qid]; 5200 info = &ctx->ifc_txqs[qid].ift_filter_info; 5201 gtask = &ctx->ifc_txqs[qid].ift_task; 5202 tqg = qgroup_if_io_tqg; 5203 fn = _task_fn_tx; 5204 intr_fast = iflib_fast_intr; 5205 GROUPTASK_INIT(gtask, 0, fn, q); 5206 break; 5207 case IFLIB_INTR_RX: 5208 q = &ctx->ifc_rxqs[qid]; 5209 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5210 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5211 tqg = qgroup_if_io_tqg; 5212 fn = _task_fn_rx; 5213 intr_fast = iflib_fast_intr; 5214 GROUPTASK_INIT(gtask, 0, fn, q); 5215 break; 5216 case IFLIB_INTR_RXTX: 5217 q = &ctx->ifc_rxqs[qid]; 5218 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5219 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5220 tqg = qgroup_if_io_tqg; 5221 fn = _task_fn_rx; 5222 intr_fast = iflib_fast_intr_rxtx; 5223 GROUPTASK_INIT(gtask, 0, fn, q); 5224 break; 5225 case IFLIB_INTR_ADMIN: 5226 q = ctx; 5227 tqrid = -1; 5228 info = &ctx->ifc_filter_info; 5229 gtask = &ctx->ifc_admin_task; 5230 tqg = qgroup_if_config_tqg; 5231 fn = _task_fn_admin; 5232 intr_fast = iflib_fast_intr_ctx; 5233 break; 5234 default: 5235 panic("unknown net intr type"); 5236 } 5237 5238 info->ifi_filter = filter; 5239 info->ifi_filter_arg = filter_arg; 5240 info->ifi_task = gtask; 5241 info->ifi_ctx = q; 5242 5243 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 5244 if (err != 0) { 5245 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err); 5246 return (err); 5247 } 5248 if (type == IFLIB_INTR_ADMIN) 5249 return (0); 5250 5251 if (tqrid != -1) { 5252 err = iflib_irq_set_affinity(ctx, rman_get_start(irq->ii_res), type, qid, gtask, tqg, q, name); 5253 if (err) 5254 return (err); 5255 } else { 5256 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); 5257 } 5258 5259 return (0); 5260 } 5261 5262 void 5263 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, char *name) 5264 { 5265 struct grouptask *gtask; 5266 struct taskqgroup *tqg; 5267 gtask_fn_t *fn; 5268 void *q; 5269 int irq_num = -1; 5270 int err; 5271 5272 switch (type) { 5273 case IFLIB_INTR_TX: 5274 q = &ctx->ifc_txqs[qid]; 5275 gtask = &ctx->ifc_txqs[qid].ift_task; 5276 tqg = qgroup_if_io_tqg; 5277 fn = _task_fn_tx; 5278 if (irq != NULL) 5279 irq_num = rman_get_start(irq->ii_res); 5280 break; 5281 case IFLIB_INTR_RX: 5282 q = &ctx->ifc_rxqs[qid]; 5283 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5284 tqg = qgroup_if_io_tqg; 5285 fn = _task_fn_rx; 5286 if (irq != NULL) 5287 irq_num = rman_get_start(irq->ii_res); 5288 break; 5289 case IFLIB_INTR_IOV: 5290 q = ctx; 5291 gtask = &ctx->ifc_vflr_task; 5292 tqg = qgroup_if_config_tqg; 5293 fn = _task_fn_iov; 5294 break; 5295 default: 5296 panic("unknown net intr type"); 5297 } 5298 GROUPTASK_INIT(gtask, 0, fn, q); 5299 if (irq_num != -1) { 5300 err = iflib_irq_set_affinity(ctx, irq_num, type, qid, gtask, tqg, q, name); 5301 if (err) 5302 taskqgroup_attach(tqg, gtask, q, irq_num, name); 5303 } 5304 else { 5305 taskqgroup_attach(tqg, gtask, q, irq_num, name); 5306 } 5307 } 5308 5309 void 5310 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 5311 { 5312 if (irq->ii_tag) 5313 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 5314 5315 if (irq->ii_res) 5316 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res); 5317 } 5318 5319 static int 5320 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, char *name) 5321 { 5322 iflib_txq_t txq = ctx->ifc_txqs; 5323 iflib_rxq_t rxq = ctx->ifc_rxqs; 5324 if_irq_t irq = &ctx->ifc_legacy_irq; 5325 iflib_filter_info_t info; 5326 struct grouptask *gtask; 5327 struct taskqgroup *tqg; 5328 gtask_fn_t *fn; 5329 int tqrid; 5330 void *q; 5331 int err; 5332 5333 q = &ctx->ifc_rxqs[0]; 5334 info = &rxq[0].ifr_filter_info; 5335 gtask = &rxq[0].ifr_task; 5336 tqg = qgroup_if_io_tqg; 5337 tqrid = irq->ii_rid = *rid; 5338 fn = _task_fn_rx; 5339 5340 ctx->ifc_flags |= IFC_LEGACY; 5341 info->ifi_filter = filter; 5342 info->ifi_filter_arg = filter_arg; 5343 info->ifi_task = gtask; 5344 info->ifi_ctx = ctx; 5345 5346 /* We allocate a single interrupt resource */ 5347 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0) 5348 return (err); 5349 GROUPTASK_INIT(gtask, 0, fn, q); 5350 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); 5351 5352 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 5353 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, rman_get_start(irq->ii_res), "tx"); 5354 return (0); 5355 } 5356 5357 void 5358 iflib_led_create(if_ctx_t ctx) 5359 { 5360 5361 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 5362 device_get_nameunit(ctx->ifc_dev)); 5363 } 5364 5365 void 5366 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 5367 { 5368 5369 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 5370 } 5371 5372 void 5373 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 5374 { 5375 5376 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 5377 } 5378 5379 void 5380 iflib_admin_intr_deferred(if_ctx_t ctx) 5381 { 5382 #ifdef INVARIANTS 5383 struct grouptask *gtask; 5384 5385 gtask = &ctx->ifc_admin_task; 5386 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL); 5387 #endif 5388 5389 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 5390 } 5391 5392 void 5393 iflib_iov_intr_deferred(if_ctx_t ctx) 5394 { 5395 5396 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 5397 } 5398 5399 void 5400 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name) 5401 { 5402 5403 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name); 5404 } 5405 5406 void 5407 iflib_config_gtask_init(if_ctx_t ctx, struct grouptask *gtask, gtask_fn_t *fn, 5408 char *name) 5409 { 5410 5411 GROUPTASK_INIT(gtask, 0, fn, ctx); 5412 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name); 5413 } 5414 5415 void 5416 iflib_config_gtask_deinit(struct grouptask *gtask) 5417 { 5418 5419 taskqgroup_detach(qgroup_if_config_tqg, gtask); 5420 } 5421 5422 void 5423 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 5424 { 5425 if_t ifp = ctx->ifc_ifp; 5426 iflib_txq_t txq = ctx->ifc_txqs; 5427 5428 if_setbaudrate(ifp, baudrate); 5429 if (baudrate >= IF_Gbps(10)) 5430 ctx->ifc_flags |= IFC_PREFETCH; 5431 5432 /* If link down, disable watchdog */ 5433 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 5434 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 5435 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 5436 } 5437 ctx->ifc_link_state = link_state; 5438 if_link_state_change(ifp, link_state); 5439 } 5440 5441 static int 5442 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 5443 { 5444 int credits; 5445 #ifdef INVARIANTS 5446 int credits_pre = txq->ift_cidx_processed; 5447 #endif 5448 5449 if (ctx->isc_txd_credits_update == NULL) 5450 return (0); 5451 5452 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 5453 return (0); 5454 5455 txq->ift_processed += credits; 5456 txq->ift_cidx_processed += credits; 5457 5458 MPASS(credits_pre + credits == txq->ift_cidx_processed); 5459 if (txq->ift_cidx_processed >= txq->ift_size) 5460 txq->ift_cidx_processed -= txq->ift_size; 5461 return (credits); 5462 } 5463 5464 static int 5465 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 5466 { 5467 5468 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 5469 budget)); 5470 } 5471 5472 void 5473 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 5474 const char *description, if_int_delay_info_t info, 5475 int offset, int value) 5476 { 5477 info->iidi_ctx = ctx; 5478 info->iidi_offset = offset; 5479 info->iidi_value = value; 5480 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 5481 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 5482 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 5483 info, 0, iflib_sysctl_int_delay, "I", description); 5484 } 5485 5486 struct mtx * 5487 iflib_ctx_lock_get(if_ctx_t ctx) 5488 { 5489 5490 return (&ctx->ifc_mtx); 5491 } 5492 5493 static int 5494 iflib_msix_init(if_ctx_t ctx) 5495 { 5496 device_t dev = ctx->ifc_dev; 5497 if_shared_ctx_t sctx = ctx->ifc_sctx; 5498 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5499 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs; 5500 int iflib_num_tx_queues, iflib_num_rx_queues; 5501 int err, admincnt, bar; 5502 5503 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 5504 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 5505 5506 device_printf(dev, "msix_init qsets capped at %d\n", imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 5507 5508 bar = ctx->ifc_softc_ctx.isc_msix_bar; 5509 admincnt = sctx->isc_admin_intrcnt; 5510 /* Override by global tuneable */ 5511 { 5512 int i; 5513 size_t len = sizeof(i); 5514 err = kernel_sysctlbyname(curthread, "hw.pci.enable_msix", &i, &len, NULL, 0, NULL, 0); 5515 if (err == 0) { 5516 if (i == 0) 5517 goto msi; 5518 } 5519 else { 5520 device_printf(dev, "unable to read hw.pci.enable_msix."); 5521 } 5522 } 5523 /* Override by tuneable */ 5524 if (scctx->isc_disable_msix) 5525 goto msi; 5526 5527 /* 5528 ** When used in a virtualized environment 5529 ** PCI BUSMASTER capability may not be set 5530 ** so explicity set it here and rewrite 5531 ** the ENABLE in the MSIX control register 5532 ** at this point to cause the host to 5533 ** successfully initialize us. 5534 */ 5535 { 5536 int msix_ctrl, rid; 5537 5538 pci_enable_busmaster(dev); 5539 rid = 0; 5540 if (pci_find_cap(dev, PCIY_MSIX, &rid) == 0 && rid != 0) { 5541 rid += PCIR_MSIX_CTRL; 5542 msix_ctrl = pci_read_config(dev, rid, 2); 5543 msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 5544 pci_write_config(dev, rid, msix_ctrl, 2); 5545 } else { 5546 device_printf(dev, "PCIY_MSIX capability not found; " 5547 "or rid %d == 0.\n", rid); 5548 goto msi; 5549 } 5550 } 5551 5552 /* 5553 * bar == -1 => "trust me I know what I'm doing" 5554 * Some drivers are for hardware that is so shoddily 5555 * documented that no one knows which bars are which 5556 * so the developer has to map all bars. This hack 5557 * allows shoddy garbage to use msix in this framework. 5558 */ 5559 if (bar != -1) { 5560 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 5561 SYS_RES_MEMORY, &bar, RF_ACTIVE); 5562 if (ctx->ifc_msix_mem == NULL) { 5563 /* May not be enabled */ 5564 device_printf(dev, "Unable to map MSIX table \n"); 5565 goto msi; 5566 } 5567 } 5568 /* First try MSI/X */ 5569 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */ 5570 device_printf(dev, "System has MSIX disabled \n"); 5571 bus_release_resource(dev, SYS_RES_MEMORY, 5572 bar, ctx->ifc_msix_mem); 5573 ctx->ifc_msix_mem = NULL; 5574 goto msi; 5575 } 5576 #if IFLIB_DEBUG 5577 /* use only 1 qset in debug mode */ 5578 queuemsgs = min(msgs - admincnt, 1); 5579 #else 5580 queuemsgs = msgs - admincnt; 5581 #endif 5582 #ifdef RSS 5583 queues = imin(queuemsgs, rss_getnumbuckets()); 5584 #else 5585 queues = queuemsgs; 5586 #endif 5587 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 5588 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n", 5589 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 5590 #ifdef RSS 5591 /* If we're doing RSS, clamp at the number of RSS buckets */ 5592 if (queues > rss_getnumbuckets()) 5593 queues = rss_getnumbuckets(); 5594 #endif 5595 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 5596 rx_queues = iflib_num_rx_queues; 5597 else 5598 rx_queues = queues; 5599 5600 if (rx_queues > scctx->isc_nrxqsets) 5601 rx_queues = scctx->isc_nrxqsets; 5602 5603 /* 5604 * We want this to be all logical CPUs by default 5605 */ 5606 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 5607 tx_queues = iflib_num_tx_queues; 5608 else 5609 tx_queues = mp_ncpus; 5610 5611 if (tx_queues > scctx->isc_ntxqsets) 5612 tx_queues = scctx->isc_ntxqsets; 5613 5614 if (ctx->ifc_sysctl_qs_eq_override == 0) { 5615 #ifdef INVARIANTS 5616 if (tx_queues != rx_queues) 5617 device_printf(dev, "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 5618 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 5619 #endif 5620 tx_queues = min(rx_queues, tx_queues); 5621 rx_queues = min(rx_queues, tx_queues); 5622 } 5623 5624 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues); 5625 5626 vectors = rx_queues + admincnt; 5627 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 5628 device_printf(dev, 5629 "Using MSIX interrupts with %d vectors\n", vectors); 5630 scctx->isc_vectors = vectors; 5631 scctx->isc_nrxqsets = rx_queues; 5632 scctx->isc_ntxqsets = tx_queues; 5633 scctx->isc_intr = IFLIB_INTR_MSIX; 5634 5635 return (vectors); 5636 } else { 5637 device_printf(dev, "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err); 5638 } 5639 msi: 5640 vectors = pci_msi_count(dev); 5641 scctx->isc_nrxqsets = 1; 5642 scctx->isc_ntxqsets = 1; 5643 scctx->isc_vectors = vectors; 5644 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 5645 device_printf(dev,"Using an MSI interrupt\n"); 5646 scctx->isc_intr = IFLIB_INTR_MSI; 5647 } else { 5648 device_printf(dev,"Using a Legacy interrupt\n"); 5649 scctx->isc_intr = IFLIB_INTR_LEGACY; 5650 } 5651 5652 return (vectors); 5653 } 5654 5655 char * ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 5656 5657 static int 5658 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 5659 { 5660 int rc; 5661 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 5662 struct sbuf *sb; 5663 char *ring_state = "UNKNOWN"; 5664 5665 /* XXX needed ? */ 5666 rc = sysctl_wire_old_buffer(req, 0); 5667 MPASS(rc == 0); 5668 if (rc != 0) 5669 return (rc); 5670 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 5671 MPASS(sb != NULL); 5672 if (sb == NULL) 5673 return (ENOMEM); 5674 if (state[3] <= 3) 5675 ring_state = ring_states[state[3]]; 5676 5677 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 5678 state[0], state[1], state[2], ring_state); 5679 rc = sbuf_finish(sb); 5680 sbuf_delete(sb); 5681 return(rc); 5682 } 5683 5684 enum iflib_ndesc_handler { 5685 IFLIB_NTXD_HANDLER, 5686 IFLIB_NRXD_HANDLER, 5687 }; 5688 5689 static int 5690 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 5691 { 5692 if_ctx_t ctx = (void *)arg1; 5693 enum iflib_ndesc_handler type = arg2; 5694 char buf[256] = {0}; 5695 qidx_t *ndesc; 5696 char *p, *next; 5697 int nqs, rc, i; 5698 5699 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER); 5700 5701 nqs = 8; 5702 switch(type) { 5703 case IFLIB_NTXD_HANDLER: 5704 ndesc = ctx->ifc_sysctl_ntxds; 5705 if (ctx->ifc_sctx) 5706 nqs = ctx->ifc_sctx->isc_ntxqs; 5707 break; 5708 case IFLIB_NRXD_HANDLER: 5709 ndesc = ctx->ifc_sysctl_nrxds; 5710 if (ctx->ifc_sctx) 5711 nqs = ctx->ifc_sctx->isc_nrxqs; 5712 break; 5713 } 5714 if (nqs == 0) 5715 nqs = 8; 5716 5717 for (i=0; i<8; i++) { 5718 if (i >= nqs) 5719 break; 5720 if (i) 5721 strcat(buf, ","); 5722 sprintf(strchr(buf, 0), "%d", ndesc[i]); 5723 } 5724 5725 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 5726 if (rc || req->newptr == NULL) 5727 return rc; 5728 5729 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 5730 i++, p = strsep(&next, " ,")) { 5731 ndesc[i] = strtoul(p, NULL, 10); 5732 } 5733 5734 return(rc); 5735 } 5736 5737 #define NAME_BUFLEN 32 5738 static void 5739 iflib_add_device_sysctl_pre(if_ctx_t ctx) 5740 { 5741 device_t dev = iflib_get_dev(ctx); 5742 struct sysctl_oid_list *child, *oid_list; 5743 struct sysctl_ctx_list *ctx_list; 5744 struct sysctl_oid *node; 5745 5746 ctx_list = device_get_sysctl_ctx(dev); 5747 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 5748 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 5749 CTLFLAG_RD, NULL, "IFLIB fields"); 5750 oid_list = SYSCTL_CHILDREN(node); 5751 5752 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 5753 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0, 5754 "driver version"); 5755 5756 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 5757 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 5758 "# of txqs to use, 0 => use default #"); 5759 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 5760 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 5761 "# of rxqs to use, 0 => use default #"); 5762 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 5763 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 5764 "permit #txq != #rxq"); 5765 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 5766 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 5767 "disable MSIX (default 0)"); 5768 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 5769 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 5770 "set the rx budget"); 5771 5772 /* XXX change for per-queue sizes */ 5773 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 5774 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 5775 mp_ndesc_handler, "A", 5776 "list of # of tx descriptors to use, 0 = use default #"); 5777 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 5778 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 5779 mp_ndesc_handler, "A", 5780 "list of # of rx descriptors to use, 0 = use default #"); 5781 } 5782 5783 static void 5784 iflib_add_device_sysctl_post(if_ctx_t ctx) 5785 { 5786 if_shared_ctx_t sctx = ctx->ifc_sctx; 5787 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5788 device_t dev = iflib_get_dev(ctx); 5789 struct sysctl_oid_list *child; 5790 struct sysctl_ctx_list *ctx_list; 5791 iflib_fl_t fl; 5792 iflib_txq_t txq; 5793 iflib_rxq_t rxq; 5794 int i, j; 5795 char namebuf[NAME_BUFLEN]; 5796 char *qfmt; 5797 struct sysctl_oid *queue_node, *fl_node, *node; 5798 struct sysctl_oid_list *queue_list, *fl_list; 5799 ctx_list = device_get_sysctl_ctx(dev); 5800 5801 node = ctx->ifc_sysctl_node; 5802 child = SYSCTL_CHILDREN(node); 5803 5804 if (scctx->isc_ntxqsets > 100) 5805 qfmt = "txq%03d"; 5806 else if (scctx->isc_ntxqsets > 10) 5807 qfmt = "txq%02d"; 5808 else 5809 qfmt = "txq%d"; 5810 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 5811 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 5812 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 5813 CTLFLAG_RD, NULL, "Queue Name"); 5814 queue_list = SYSCTL_CHILDREN(queue_node); 5815 #if MEMORY_LOGGING 5816 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 5817 CTLFLAG_RD, 5818 &txq->ift_dequeued, "total mbufs freed"); 5819 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 5820 CTLFLAG_RD, 5821 &txq->ift_enqueued, "total mbufs enqueued"); 5822 #endif 5823 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 5824 CTLFLAG_RD, 5825 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 5826 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 5827 CTLFLAG_RD, 5828 &txq->ift_pullups, "# of times m_pullup was called"); 5829 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 5830 CTLFLAG_RD, 5831 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 5832 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 5833 CTLFLAG_RD, 5834 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 5835 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 5836 CTLFLAG_RD, 5837 &txq->ift_map_failed, "# of times dma map failed"); 5838 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 5839 CTLFLAG_RD, 5840 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 5841 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 5842 CTLFLAG_RD, 5843 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 5844 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 5845 CTLFLAG_RD, 5846 &txq->ift_pidx, 1, "Producer Index"); 5847 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 5848 CTLFLAG_RD, 5849 &txq->ift_cidx, 1, "Consumer Index"); 5850 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 5851 CTLFLAG_RD, 5852 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 5853 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 5854 CTLFLAG_RD, 5855 &txq->ift_in_use, 1, "descriptors in use"); 5856 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 5857 CTLFLAG_RD, 5858 &txq->ift_processed, "descriptors procesed for clean"); 5859 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 5860 CTLFLAG_RD, 5861 &txq->ift_cleaned, "total cleaned"); 5862 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 5863 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), 5864 0, mp_ring_state_handler, "A", "soft ring state"); 5865 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 5866 CTLFLAG_RD, &txq->ift_br->enqueues, 5867 "# of enqueues to the mp_ring for this queue"); 5868 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 5869 CTLFLAG_RD, &txq->ift_br->drops, 5870 "# of drops in the mp_ring for this queue"); 5871 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 5872 CTLFLAG_RD, &txq->ift_br->starts, 5873 "# of normal consumer starts in the mp_ring for this queue"); 5874 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 5875 CTLFLAG_RD, &txq->ift_br->stalls, 5876 "# of consumer stalls in the mp_ring for this queue"); 5877 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 5878 CTLFLAG_RD, &txq->ift_br->restarts, 5879 "# of consumer restarts in the mp_ring for this queue"); 5880 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 5881 CTLFLAG_RD, &txq->ift_br->abdications, 5882 "# of consumer abdications in the mp_ring for this queue"); 5883 } 5884 5885 if (scctx->isc_nrxqsets > 100) 5886 qfmt = "rxq%03d"; 5887 else if (scctx->isc_nrxqsets > 10) 5888 qfmt = "rxq%02d"; 5889 else 5890 qfmt = "rxq%d"; 5891 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 5892 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 5893 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 5894 CTLFLAG_RD, NULL, "Queue Name"); 5895 queue_list = SYSCTL_CHILDREN(queue_node); 5896 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5897 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx", 5898 CTLFLAG_RD, 5899 &rxq->ifr_cq_pidx, 1, "Producer Index"); 5900 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 5901 CTLFLAG_RD, 5902 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 5903 } 5904 5905 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 5906 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 5907 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 5908 CTLFLAG_RD, NULL, "freelist Name"); 5909 fl_list = SYSCTL_CHILDREN(fl_node); 5910 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 5911 CTLFLAG_RD, 5912 &fl->ifl_pidx, 1, "Producer Index"); 5913 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 5914 CTLFLAG_RD, 5915 &fl->ifl_cidx, 1, "Consumer Index"); 5916 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 5917 CTLFLAG_RD, 5918 &fl->ifl_credits, 1, "credits available"); 5919 #if MEMORY_LOGGING 5920 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 5921 CTLFLAG_RD, 5922 &fl->ifl_m_enqueued, "mbufs allocated"); 5923 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 5924 CTLFLAG_RD, 5925 &fl->ifl_m_dequeued, "mbufs freed"); 5926 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 5927 CTLFLAG_RD, 5928 &fl->ifl_cl_enqueued, "clusters allocated"); 5929 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 5930 CTLFLAG_RD, 5931 &fl->ifl_cl_dequeued, "clusters freed"); 5932 #endif 5933 5934 } 5935 } 5936 5937 } 5938 5939 #ifndef __NO_STRICT_ALIGNMENT 5940 static struct mbuf * 5941 iflib_fixup_rx(struct mbuf *m) 5942 { 5943 struct mbuf *n; 5944 5945 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 5946 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 5947 m->m_data += ETHER_HDR_LEN; 5948 n = m; 5949 } else { 5950 MGETHDR(n, M_NOWAIT, MT_DATA); 5951 if (n == NULL) { 5952 m_freem(m); 5953 return (NULL); 5954 } 5955 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 5956 m->m_data += ETHER_HDR_LEN; 5957 m->m_len -= ETHER_HDR_LEN; 5958 n->m_len = ETHER_HDR_LEN; 5959 M_MOVE_PKTHDR(n, m); 5960 n->m_next = m; 5961 } 5962 return (n); 5963 } 5964 #endif 5965