1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright 2002 by Peter Grehan. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Mac-io ATA controller 35 */ 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/module.h> 40 #include <sys/bus.h> 41 #include <sys/malloc.h> 42 #include <sys/sema.h> 43 #include <sys/taskqueue.h> 44 #include <vm/uma.h> 45 #include <machine/stdarg.h> 46 #include <machine/resource.h> 47 #include <machine/bus.h> 48 #include <sys/rman.h> 49 #include <sys/ata.h> 50 #include <dev/ata/ata-all.h> 51 #include <ata_if.h> 52 53 #include <dev/ofw/ofw_bus.h> 54 55 #include "ata_dbdma.h" 56 57 /* 58 * Offset to control registers from base 59 */ 60 #define ATA_MACIO_ALTOFFSET 0x160 61 62 /* 63 * Define the gap between registers 64 */ 65 #define ATA_MACIO_REGGAP 16 66 67 /* 68 * Whether or not to bind to the DBDMA IRQ 69 */ 70 #define USE_DBDMA_IRQ 0 71 72 /* 73 * Timing register 74 */ 75 #define ATA_MACIO_TIMINGREG 0x200 76 77 #define ATA_TIME_TO_TICK(rev,time) howmany(time, (rev == 4) ? 15 : 30) 78 #define PIO_REC_OFFSET 4 79 #define PIO_REC_MIN 1 80 #define PIO_ACT_MIN 1 81 #define DMA_REC_OFFSET 1 82 #define DMA_REC_MIN 1 83 #define DMA_ACT_MIN 1 84 85 struct ide_timings { 86 int cycle; /* minimum cycle time [ns] */ 87 int active; /* minimum command active time [ns] */ 88 }; 89 90 static const struct ide_timings pio_timings[5] = { 91 { 600, 180 }, /* PIO 0 */ 92 { 390, 150 }, /* PIO 1 */ 93 { 240, 105 }, /* PIO 2 */ 94 { 180, 90 }, /* PIO 3 */ 95 { 120, 75 } /* PIO 4 */ 96 }; 97 98 static const struct ide_timings dma_timings[3] = { 99 { 480, 240 }, /* WDMA 0 */ 100 { 165, 90 }, /* WDMA 1 */ 101 { 120, 75 } /* WDMA 2 */ 102 }; 103 104 static const struct ide_timings udma_timings[5] = { 105 { 120, 180 }, /* UDMA 0 */ 106 { 90, 150 }, /* UDMA 1 */ 107 { 60, 120 }, /* UDMA 2 */ 108 { 45, 90 }, /* UDMA 3 */ 109 { 30, 90 } /* UDMA 4 */ 110 }; 111 112 /* 113 * Define the macio ata bus attachment. 114 */ 115 static int ata_macio_probe(device_t dev); 116 static int ata_macio_setmode(device_t dev, int target, int mode); 117 static int ata_macio_attach(device_t dev); 118 static int ata_macio_begin_transaction(struct ata_request *request); 119 static int ata_macio_suspend(device_t dev); 120 static int ata_macio_resume(device_t dev); 121 122 static device_method_t ata_macio_methods[] = { 123 /* Device interface */ 124 DEVMETHOD(device_probe, ata_macio_probe), 125 DEVMETHOD(device_attach, ata_macio_attach), 126 DEVMETHOD(device_suspend, ata_macio_suspend), 127 DEVMETHOD(device_resume, ata_macio_resume), 128 129 /* ATA interface */ 130 DEVMETHOD(ata_setmode, ata_macio_setmode), 131 DEVMETHOD_END 132 }; 133 134 struct ata_macio_softc { 135 struct ata_dbdma_channel sc_ch; 136 137 int rev; 138 int max_mode; 139 struct resource *sc_mem; 140 141 uint32_t udmaconf[2]; 142 uint32_t wdmaconf[2]; 143 uint32_t pioconf[2]; 144 }; 145 146 static driver_t ata_macio_driver = { 147 "ata", 148 ata_macio_methods, 149 sizeof(struct ata_macio_softc), 150 }; 151 152 DRIVER_MODULE(ata, macio, ata_macio_driver, ata_devclass, NULL, NULL); 153 MODULE_DEPEND(ata, ata, 1, 1, 1); 154 155 static int 156 ata_macio_probe(device_t dev) 157 { 158 const char *type = ofw_bus_get_type(dev); 159 const char *name = ofw_bus_get_name(dev); 160 struct ata_macio_softc *sc; 161 162 if (strcmp(type, "ata") != 0 && 163 strcmp(type, "ide") != 0) 164 return (ENXIO); 165 166 sc = device_get_softc(dev); 167 bzero(sc, sizeof(struct ata_macio_softc)); 168 169 if (strcmp(name,"ata-4") == 0) { 170 device_set_desc(dev,"Apple MacIO Ultra ATA Controller"); 171 sc->rev = 4; 172 sc->max_mode = ATA_UDMA4; 173 } else { 174 device_set_desc(dev,"Apple MacIO ATA Controller"); 175 sc->rev = 3; 176 sc->max_mode = ATA_WDMA2; 177 } 178 179 return (ata_probe(dev)); 180 } 181 182 static int 183 ata_macio_attach(device_t dev) 184 { 185 struct ata_macio_softc *sc = device_get_softc(dev); 186 uint32_t timingreg; 187 struct ata_channel *ch; 188 int rid, i; 189 190 /* 191 * Allocate resources 192 */ 193 194 rid = 0; 195 ch = &sc->sc_ch.sc_ch; 196 sc->sc_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 197 RF_ACTIVE); 198 if (sc->sc_mem == NULL) { 199 device_printf(dev, "could not allocate memory\n"); 200 return (ENXIO); 201 } 202 203 /* 204 * Set up the resource vectors 205 */ 206 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 207 ch->r_io[i].res = sc->sc_mem; 208 ch->r_io[i].offset = i * ATA_MACIO_REGGAP; 209 } 210 ch->r_io[ATA_CONTROL].res = sc->sc_mem; 211 ch->r_io[ATA_CONTROL].offset = ATA_MACIO_ALTOFFSET; 212 ata_default_registers(dev); 213 214 ch->unit = 0; 215 ch->flags |= ATA_USE_16BIT | ATA_NO_ATAPI_DMA; 216 ata_generic_hw(dev); 217 218 #if USE_DBDMA_IRQ 219 int dbdma_irq_rid = 1; 220 struct resource *dbdma_irq; 221 void *cookie; 222 #endif 223 224 /* Init DMA engine */ 225 226 sc->sc_ch.dbdma_rid = 1; 227 sc->sc_ch.dbdma_regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 228 &sc->sc_ch.dbdma_rid, RF_ACTIVE); 229 230 ata_dbdma_dmainit(dev); 231 232 /* Configure initial timings */ 233 timingreg = bus_read_4(sc->sc_mem, ATA_MACIO_TIMINGREG); 234 if (sc->rev == 4) { 235 sc->udmaconf[0] = sc->udmaconf[1] = timingreg & 0x1ff00000; 236 sc->wdmaconf[0] = sc->wdmaconf[1] = timingreg & 0x001ffc00; 237 sc->pioconf[0] = sc->pioconf[1] = timingreg & 0x000003ff; 238 } else { 239 sc->udmaconf[0] = sc->udmaconf[1] = 0; 240 sc->wdmaconf[0] = sc->wdmaconf[1] = timingreg & 0xfffff800; 241 sc->pioconf[0] = sc->pioconf[1] = timingreg & 0x000007ff; 242 } 243 244 #if USE_DBDMA_IRQ 245 /* Bind to DBDMA interrupt as well */ 246 247 if ((dbdma_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 248 &dbdma_irq_rid, RF_SHAREABLE | RF_ACTIVE)) != NULL) { 249 bus_setup_intr(dev, dbdma_irq, ATA_INTR_FLAGS, NULL, 250 (driver_intr_t *)ata_interrupt, sc,&cookie); 251 } 252 #endif 253 254 /* Set begin_transaction */ 255 sc->sc_ch.sc_ch.hw.begin_transaction = ata_macio_begin_transaction; 256 257 return ata_attach(dev); 258 } 259 260 static int 261 ata_macio_setmode(device_t dev, int target, int mode) 262 { 263 struct ata_macio_softc *sc = device_get_softc(dev); 264 265 int min_cycle = 0, min_active = 0; 266 int cycle_tick = 0, act_tick = 0, inact_tick = 0, half_tick; 267 268 mode = min(mode, sc->max_mode); 269 270 if ((mode & ATA_DMA_MASK) == ATA_UDMA0) { 271 min_cycle = udma_timings[mode & ATA_MODE_MASK].cycle; 272 min_active = udma_timings[mode & ATA_MODE_MASK].active; 273 274 cycle_tick = ATA_TIME_TO_TICK(sc->rev,min_cycle); 275 act_tick = ATA_TIME_TO_TICK(sc->rev,min_active); 276 277 /* mask: 0x1ff00000 */ 278 sc->udmaconf[target] = 279 (cycle_tick << 21) | (act_tick << 25) | 0x100000; 280 } else if ((mode & ATA_DMA_MASK) == ATA_WDMA0) { 281 min_cycle = dma_timings[mode & ATA_MODE_MASK].cycle; 282 min_active = dma_timings[mode & ATA_MODE_MASK].active; 283 284 cycle_tick = ATA_TIME_TO_TICK(sc->rev,min_cycle); 285 act_tick = ATA_TIME_TO_TICK(sc->rev,min_active); 286 287 if (sc->rev == 4) { 288 inact_tick = cycle_tick - act_tick; 289 /* mask: 0x001ffc00 */ 290 sc->wdmaconf[target] = 291 (act_tick << 10) | (inact_tick << 15); 292 } else { 293 inact_tick = cycle_tick - act_tick - DMA_REC_OFFSET; 294 if (inact_tick < DMA_REC_MIN) 295 inact_tick = DMA_REC_MIN; 296 half_tick = 0; /* XXX */ 297 298 /* mask: 0xfffff800 */ 299 sc->wdmaconf[target] = (half_tick << 21) 300 | (inact_tick << 16) | (act_tick << 11); 301 } 302 } else { 303 min_cycle = 304 pio_timings[(mode & ATA_MODE_MASK) - ATA_PIO0].cycle; 305 min_active = 306 pio_timings[(mode & ATA_MODE_MASK) - ATA_PIO0].active; 307 308 cycle_tick = ATA_TIME_TO_TICK(sc->rev,min_cycle); 309 act_tick = ATA_TIME_TO_TICK(sc->rev,min_active); 310 311 if (sc->rev == 4) { 312 inact_tick = cycle_tick - act_tick; 313 314 /* mask: 0x000003ff */ 315 sc->pioconf[target] = 316 (inact_tick << 5) | act_tick; 317 } else { 318 if (act_tick < PIO_ACT_MIN) 319 act_tick = PIO_ACT_MIN; 320 321 inact_tick = cycle_tick - act_tick - PIO_REC_OFFSET; 322 if (inact_tick < PIO_REC_MIN) 323 inact_tick = PIO_REC_MIN; 324 325 /* mask: 0x000007ff */ 326 sc->pioconf[target] = 327 (inact_tick << 5) | act_tick; 328 } 329 } 330 331 return (mode); 332 } 333 334 static int 335 ata_macio_begin_transaction(struct ata_request *request) 336 { 337 struct ata_macio_softc *sc = device_get_softc(request->parent); 338 339 bus_write_4(sc->sc_mem, ATA_MACIO_TIMINGREG, 340 sc->udmaconf[request->unit] | sc->wdmaconf[request->unit] 341 | sc->pioconf[request->unit]); 342 343 return ata_begin_transaction(request); 344 } 345 346 static int 347 ata_macio_suspend(device_t dev) 348 { 349 struct ata_dbdma_channel *ch = device_get_softc(dev); 350 int error; 351 352 if (!ch->sc_ch.attached) 353 return (0); 354 355 error = ata_suspend(dev); 356 dbdma_save_state(ch->dbdma); 357 358 return (error); 359 } 360 361 static int 362 ata_macio_resume(device_t dev) 363 { 364 struct ata_dbdma_channel *ch = device_get_softc(dev); 365 int error; 366 367 if (!ch->sc_ch.attached) 368 return (0); 369 370 dbdma_restore_state(ch->dbdma); 371 error = ata_resume(dev); 372 373 return (error); 374 } 375