1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright 2019 Justin Hibbits 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_platform.h" 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/module.h> 36 #include <sys/bus.h> 37 #include <sys/conf.h> 38 #include <sys/endian.h> 39 #include <sys/kernel.h> 40 #include <sys/lock.h> 41 #include <sys/malloc.h> 42 #include <sys/mutex.h> 43 #include <sys/smp.h> 44 45 #include <vm/vm.h> 46 #include <vm/pmap.h> 47 48 #include <machine/bus.h> 49 #include <machine/intr_machdep.h> 50 #include <machine/md_var.h> 51 52 #include <dev/ofw/ofw_bus.h> 53 #include <dev/ofw/ofw_bus_subr.h> 54 55 #ifdef POWERNV 56 #include <powerpc/powernv/opal.h> 57 #endif 58 59 #include "pic_if.h" 60 61 #define XIVE_PRIORITY 7 /* Random non-zero number */ 62 #define MAX_XIVE_IRQS (1<<24) /* 24-bit XIRR field */ 63 64 /* Registers */ 65 #define XIVE_TM_QW1_OS 0x010 /* Guest OS registers */ 66 #define XIVE_TM_QW2_HV_POOL 0x020 /* Hypervisor pool registers */ 67 #define XIVE_TM_QW3_HV 0x030 /* Hypervisor registers */ 68 69 #define XIVE_TM_NSR 0x00 70 #define XIVE_TM_CPPR 0x01 71 #define XIVE_TM_IPB 0x02 72 #define XIVE_TM_LSMFB 0x03 73 #define XIVE_TM_ACK_CNT 0x04 74 #define XIVE_TM_INC 0x05 75 #define XIVE_TM_AGE 0x06 76 #define XIVE_TM_PIPR 0x07 77 78 #define TM_WORD0 0x0 79 #define TM_WORD2 0x8 80 #define TM_QW2W2_VP 0x80000000 81 82 #define XIVE_TM_SPC_ACK 0x800 83 #define TM_QW3NSR_HE_SHIFT 14 84 #define TM_QW3_NSR_HE_NONE 0 85 #define TM_QW3_NSR_HE_POOL 1 86 #define TM_QW3_NSR_HE_PHYS 2 87 #define TM_QW3_NSR_HE_LSI 3 88 #define XIVE_TM_SPC_PULL_POOL_CTX 0x828 89 90 #define XIVE_IRQ_LOAD_EOI 0x000 91 #define XIVE_IRQ_STORE_EOI 0x400 92 #define XIVE_IRQ_PQ_00 0xc00 93 #define XIVE_IRQ_PQ_01 0xd00 94 95 #define XIVE_IRQ_VAL_P 0x02 96 #define XIVE_IRQ_VAL_Q 0x01 97 98 struct xive_softc; 99 struct xive_irq; 100 101 extern void (*powernv_smp_ap_extra_init)(void); 102 103 /* Private support */ 104 static void xive_setup_cpu(void); 105 static void xive_smp_cpu_startup(void); 106 static void xive_init_irq(struct xive_irq *irqd, u_int irq); 107 static struct xive_irq *xive_configure_irq(u_int irq); 108 static int xive_provision_page(struct xive_softc *sc); 109 110 111 /* Interfaces */ 112 static int xive_probe(device_t); 113 static int xive_attach(device_t); 114 static int xics_probe(device_t); 115 static int xics_attach(device_t); 116 117 static void xive_bind(device_t, u_int, cpuset_t, void **); 118 static void xive_dispatch(device_t, struct trapframe *); 119 static void xive_enable(device_t, u_int, u_int, void **); 120 static void xive_eoi(device_t, u_int, void *); 121 static void xive_ipi(device_t, u_int); 122 static void xive_mask(device_t, u_int, void *); 123 static void xive_unmask(device_t, u_int, void *); 124 static void xive_translate_code(device_t dev, u_int irq, int code, 125 enum intr_trigger *trig, enum intr_polarity *pol); 126 127 static device_method_t xive_methods[] = { 128 /* Device interface */ 129 DEVMETHOD(device_probe, xive_probe), 130 DEVMETHOD(device_attach, xive_attach), 131 132 /* PIC interface */ 133 DEVMETHOD(pic_bind, xive_bind), 134 DEVMETHOD(pic_dispatch, xive_dispatch), 135 DEVMETHOD(pic_enable, xive_enable), 136 DEVMETHOD(pic_eoi, xive_eoi), 137 DEVMETHOD(pic_ipi, xive_ipi), 138 DEVMETHOD(pic_mask, xive_mask), 139 DEVMETHOD(pic_unmask, xive_unmask), 140 DEVMETHOD(pic_translate_code, xive_translate_code), 141 142 DEVMETHOD_END 143 }; 144 145 static device_method_t xics_methods[] = { 146 /* Device interface */ 147 DEVMETHOD(device_probe, xics_probe), 148 DEVMETHOD(device_attach, xics_attach), 149 150 DEVMETHOD_END 151 }; 152 153 struct xive_softc { 154 struct mtx sc_mtx; 155 struct resource *sc_mem; 156 vm_size_t sc_prov_page_size; 157 uint32_t sc_offset; 158 }; 159 160 struct xive_queue { 161 uint32_t *q_page; 162 uint32_t *q_eoi_page; 163 uint32_t q_toggle; 164 uint32_t q_size; 165 uint32_t q_index; 166 uint32_t q_mask; 167 }; 168 169 struct xive_irq { 170 uint32_t girq; 171 uint32_t lirq; 172 uint64_t vp; 173 uint64_t flags; 174 #define OPAL_XIVE_IRQ_EOI_VIA_FW 0x00000020 175 #define OPAL_XIVE_IRQ_MASK_VIA_FW 0x00000010 176 #define OPAL_XIVE_IRQ_SHIFT_BUG 0x00000008 177 #define OPAL_XIVE_IRQ_LSI 0x00000004 178 #define OPAL_XIVE_IRQ_STORE_EOI 0x00000002 179 #define OPAL_XIVE_IRQ_TRIGGER_PAGE 0x00000001 180 uint8_t prio; 181 vm_offset_t eoi_page; 182 vm_offset_t trig_page; 183 vm_size_t esb_size; 184 int chip; 185 }; 186 187 struct xive_cpu { 188 uint64_t vp; 189 uint64_t flags; 190 struct xive_irq ipi_data; 191 struct xive_queue queue; /* We only use a single queue for now. */ 192 uint64_t cam; 193 uint32_t chip; 194 }; 195 196 static driver_t xive_driver = { 197 "xive", 198 xive_methods, 199 sizeof(struct xive_softc) 200 }; 201 202 static driver_t xics_driver = { 203 "xivevc", 204 xics_methods, 205 0 206 }; 207 208 static devclass_t xive_devclass; 209 static devclass_t xics_devclass; 210 211 EARLY_DRIVER_MODULE(xive, ofwbus, xive_driver, xive_devclass, 0, 0, 212 BUS_PASS_INTERRUPT-1); 213 EARLY_DRIVER_MODULE(xivevc, ofwbus, xics_driver, xics_devclass, 0, 0, 214 BUS_PASS_INTERRUPT); 215 216 MALLOC_DEFINE(M_XIVE, "xive", "XIVE Memory"); 217 218 DPCPU_DEFINE_STATIC(struct xive_cpu, xive_cpu_data); 219 220 static int xive_ipi_vector = -1; 221 222 /* 223 * XIVE Exploitation mode driver. 224 * 225 * The XIVE, present in the POWER9 CPU, can run in two modes: XICS emulation 226 * mode, and "Exploitation mode". XICS emulation mode is compatible with the 227 * POWER8 and earlier XICS interrupt controller, using OPAL calls to emulate 228 * hypervisor calls and memory accesses. Exploitation mode gives us raw access 229 * to the XIVE MMIO, improving performance significantly. 230 * 231 * The XIVE controller is a very bizarre interrupt controller. It uses queues 232 * in memory to pass interrupts around, and maps itself into 512GB of physical 233 * device address space, giving each interrupt in the system one or more pages 234 * of address space. An IRQ is tied to a virtual processor, which could be a 235 * physical CPU thread, or a guest CPU thread (LPAR running on a physical 236 * thread). Thus, the controller can route interrupts directly to guest OSes 237 * bypassing processing by the hypervisor, thereby improving performance of the 238 * guest OS. 239 * 240 * An IRQ, in addition to being tied to a virtual processor, has one or two 241 * page mappings: an EOI page, and an optional trigger page. The trigger page 242 * could be the same as the EOI page. Level-sensitive interrupts (LSIs) don't 243 * have a trigger page, as they're external interrupts controlled by physical 244 * lines. MSIs and IPIs have trigger pages. An IPI is really just another IRQ 245 * in the XIVE, which is triggered by software. 246 * 247 * An interesting behavior of the XIVE controller is that oftentimes the 248 * contents of an address location don't actually matter, but the direction of 249 * the action is the signifier (read vs write), and the address is significant. 250 * Hence, masking and unmasking an interrupt is done by reading different 251 * addresses in the EOI page, and triggering an interrupt consists of writing to 252 * the trigger page. 253 * 254 * Additionally, the MMIO region mapped is CPU-sensitive, just like the 255 * per-processor register space (private access) in OpenPIC. In order for a CPU 256 * to receive interrupts it must itself configure its CPPR (Current Processor 257 * Priority Register), it cannot be set by any other processor. This 258 * necessitates the xive_smp_cpu_startup() function. 259 * 260 * Queues are pages of memory, sized powers-of-two, that are shared with the 261 * XIVE. The XIVE writes into the queue with an alternating polarity bit, which 262 * flips when the queue wraps. 263 */ 264 265 /* 266 * Offset-based read/write interfaces. 267 */ 268 static uint16_t 269 xive_read_2(struct xive_softc *sc, bus_size_t offset) 270 { 271 272 return (bus_read_2(sc->sc_mem, sc->sc_offset + offset)); 273 } 274 275 static void 276 xive_write_1(struct xive_softc *sc, bus_size_t offset, uint8_t val) 277 { 278 279 bus_write_1(sc->sc_mem, sc->sc_offset + offset, val); 280 } 281 282 /* EOI and Trigger page access interfaces. */ 283 static uint64_t 284 xive_read_mmap8(vm_offset_t addr) 285 { 286 return (*(volatile uint64_t *)addr); 287 } 288 289 static void 290 xive_write_mmap8(vm_offset_t addr, uint64_t val) 291 { 292 *(uint64_t *)(addr) = val; 293 } 294 295 296 /* Device interfaces. */ 297 static int 298 xive_probe(device_t dev) 299 { 300 301 if (!ofw_bus_is_compatible(dev, "ibm,opal-xive-pe")) 302 return (ENXIO); 303 304 device_set_desc(dev, "External Interrupt Virtualization Engine"); 305 306 /* Make sure we always win against the xicp driver. */ 307 return (BUS_PROBE_DEFAULT); 308 } 309 310 static int 311 xics_probe(device_t dev) 312 { 313 314 if (!ofw_bus_is_compatible(dev, "ibm,opal-xive-vc")) 315 return (ENXIO); 316 317 device_set_desc(dev, "External Interrupt Virtualization Engine Root"); 318 return (BUS_PROBE_DEFAULT); 319 } 320 321 static int 322 xive_attach(device_t dev) 323 { 324 struct xive_softc *sc = device_get_softc(dev); 325 struct xive_cpu *xive_cpud; 326 phandle_t phandle = ofw_bus_get_node(dev); 327 int64_t vp_block; 328 int error; 329 int rid; 330 int i, order; 331 uint64_t vp_id; 332 int64_t ipi_irq; 333 334 opal_call(OPAL_XIVE_RESET, OPAL_XIVE_XICS_MODE_EXP); 335 336 error = OF_getencprop(phandle, "ibm,xive-provision-page-size", 337 (pcell_t *)&sc->sc_prov_page_size, sizeof(sc->sc_prov_page_size)); 338 339 rid = 1; /* Get the Hypervisor-level register set. */ 340 sc->sc_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 341 &rid, RF_ACTIVE); 342 sc->sc_offset = XIVE_TM_QW3_HV; 343 344 mtx_init(&sc->sc_mtx, "XIVE", NULL, MTX_DEF); 345 346 order = fls(mp_maxid + (mp_maxid - 1)) - 1; 347 348 do { 349 vp_block = opal_call(OPAL_XIVE_ALLOCATE_VP_BLOCK, order); 350 if (vp_block == OPAL_BUSY) 351 DELAY(10); 352 else if (vp_block == OPAL_XIVE_PROVISIONING) 353 xive_provision_page(sc); 354 else 355 break; 356 } while (1); 357 358 if (vp_block < 0) { 359 device_printf(dev, 360 "Unable to allocate VP block. Opal error %d\n", 361 (int)vp_block); 362 bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->sc_mem); 363 return (ENXIO); 364 } 365 366 /* 367 * Set up the VPs. Try to do as much as we can in attach, to lessen 368 * what's needed at AP spawn time. 369 */ 370 CPU_FOREACH(i) { 371 vp_id = pcpu_find(i)->pc_hwref; 372 373 xive_cpud = DPCPU_ID_PTR(i, xive_cpu_data); 374 xive_cpud->vp = vp_id + vp_block; 375 opal_call(OPAL_XIVE_GET_VP_INFO, xive_cpud->vp, NULL, 376 vtophys(&xive_cpud->cam), NULL, vtophys(&xive_cpud->chip)); 377 378 /* Allocate the queue page and populate the queue state data. */ 379 xive_cpud->queue.q_page = contigmalloc(PAGE_SIZE, M_XIVE, 380 M_ZERO | M_WAITOK, 0, BUS_SPACE_MAXADDR, PAGE_SIZE, 0); 381 xive_cpud->queue.q_size = 1 << PAGE_SHIFT; 382 xive_cpud->queue.q_mask = 383 ((xive_cpud->queue.q_size / sizeof(int)) - 1); 384 xive_cpud->queue.q_toggle = 0; 385 xive_cpud->queue.q_index = 0; 386 do { 387 error = opal_call(OPAL_XIVE_SET_VP_INFO, xive_cpud->vp, 388 OPAL_XIVE_VP_ENABLED, 0); 389 } while (error == OPAL_BUSY); 390 error = opal_call(OPAL_XIVE_SET_QUEUE_INFO, vp_id, 391 XIVE_PRIORITY, vtophys(xive_cpud->queue.q_page), PAGE_SHIFT, 392 OPAL_XIVE_EQ_ALWAYS_NOTIFY | OPAL_XIVE_EQ_ENABLED); 393 394 do { 395 ipi_irq = opal_call(OPAL_XIVE_ALLOCATE_IRQ, 396 xive_cpud->chip); 397 } while (ipi_irq == OPAL_BUSY); 398 399 if (ipi_irq < 0) 400 device_printf(root_pic, 401 "Failed allocating IPI. OPAL error %d\n", 402 (int)ipi_irq); 403 else { 404 xive_init_irq(&xive_cpud->ipi_data, ipi_irq); 405 xive_cpud->ipi_data.vp = vp_id; 406 xive_cpud->ipi_data.lirq = MAX_XIVE_IRQS; 407 opal_call(OPAL_XIVE_SET_IRQ_CONFIG, ipi_irq, 408 xive_cpud->ipi_data.vp, XIVE_PRIORITY, 409 MAX_XIVE_IRQS); 410 } 411 } 412 413 powerpc_register_pic(dev, OF_xref_from_node(phandle), MAX_XIVE_IRQS, 414 1 /* Number of IPIs */, FALSE); 415 root_pic = dev; 416 417 xive_setup_cpu(); 418 powernv_smp_ap_extra_init = xive_smp_cpu_startup; 419 420 return (0); 421 } 422 423 static int 424 xics_attach(device_t dev) 425 { 426 phandle_t phandle = ofw_bus_get_node(dev); 427 428 /* The XIVE (root PIC) will handle all our interrupts */ 429 powerpc_register_pic(root_pic, OF_xref_from_node(phandle), 430 MAX_XIVE_IRQS, 1 /* Number of IPIs */, FALSE); 431 432 return (0); 433 } 434 435 /* 436 * PIC I/F methods. 437 */ 438 439 static void 440 xive_bind(device_t dev, u_int irq, cpuset_t cpumask, void **priv) 441 { 442 struct xive_irq *irqd; 443 int cpu; 444 int ncpus, i, error; 445 446 if (*priv == NULL) 447 *priv = xive_configure_irq(irq); 448 449 irqd = *priv; 450 451 /* 452 * This doesn't appear to actually support affinity groups, so pick a 453 * random CPU. 454 */ 455 ncpus = 0; 456 CPU_FOREACH(cpu) 457 if (CPU_ISSET(cpu, &cpumask)) ncpus++; 458 459 i = mftb() % ncpus; 460 ncpus = 0; 461 CPU_FOREACH(cpu) { 462 if (!CPU_ISSET(cpu, &cpumask)) 463 continue; 464 if (ncpus == i) 465 break; 466 ncpus++; 467 } 468 469 opal_call(OPAL_XIVE_SYNC); 470 471 irqd->vp = pcpu_find(cpu)->pc_hwref; 472 error = opal_call(OPAL_XIVE_SET_IRQ_CONFIG, irq, irqd->vp, 473 XIVE_PRIORITY, irqd->lirq); 474 475 if (error < 0) 476 panic("Cannot bind interrupt %d to CPU %d", irq, cpu); 477 478 xive_eoi(dev, irq, irqd); 479 } 480 481 /* Read the next entry in the queue page and update the index. */ 482 static int 483 xive_read_eq(struct xive_queue *q) 484 { 485 uint32_t i = be32toh(q->q_page[q->q_index]); 486 487 /* Check validity, using current queue polarity. */ 488 if ((i >> 31) == q->q_toggle) 489 return (0); 490 491 q->q_index = (q->q_index + 1) & q->q_mask; 492 493 if (q->q_index == 0) 494 q->q_toggle ^= 1; 495 496 return (i & 0x7fffffff); 497 } 498 499 static void 500 xive_dispatch(device_t dev, struct trapframe *tf) 501 { 502 struct xive_softc *sc; 503 struct xive_cpu *xive_cpud; 504 uint32_t vector; 505 uint16_t ack; 506 uint8_t cppr, he; 507 508 sc = device_get_softc(dev); 509 510 for (;;) { 511 ack = xive_read_2(sc, XIVE_TM_SPC_ACK); 512 cppr = (ack & 0xff); 513 514 he = ack >> TM_QW3NSR_HE_SHIFT; 515 516 if (he == TM_QW3_NSR_HE_NONE) 517 break; 518 switch (he) { 519 case TM_QW3_NSR_HE_NONE: 520 goto end; 521 case TM_QW3_NSR_HE_POOL: 522 case TM_QW3_NSR_HE_LSI: 523 device_printf(dev, 524 "Unexpected interrupt he type: %d\n", he); 525 goto end; 526 case TM_QW3_NSR_HE_PHYS: 527 break; 528 } 529 530 xive_cpud = DPCPU_PTR(xive_cpu_data); 531 xive_write_1(sc, XIVE_TM_CPPR, cppr); 532 533 for (;;) { 534 vector = xive_read_eq(&xive_cpud->queue); 535 536 if (vector == 0) 537 break; 538 539 if (vector == MAX_XIVE_IRQS) 540 vector = xive_ipi_vector; 541 542 powerpc_dispatch_intr(vector, tf); 543 } 544 } 545 end: 546 xive_write_1(sc, XIVE_TM_CPPR, 0xff); 547 } 548 549 static void 550 xive_enable(device_t dev, u_int irq, u_int vector, void **priv) 551 { 552 struct xive_irq *irqd; 553 cell_t status, cpu; 554 555 if (irq == MAX_XIVE_IRQS) { 556 if (xive_ipi_vector == -1) 557 xive_ipi_vector = vector; 558 return; 559 } 560 if (*priv == NULL) 561 *priv = xive_configure_irq(irq); 562 563 irqd = *priv; 564 565 /* Bind to this CPU to start */ 566 cpu = PCPU_GET(hwref); 567 irqd->lirq = vector; 568 569 for (;;) { 570 status = opal_call(OPAL_XIVE_SET_IRQ_CONFIG, irq, cpu, 571 XIVE_PRIORITY, vector); 572 if (status != OPAL_BUSY) 573 break; 574 DELAY(10); 575 } 576 577 if (status != 0) 578 panic("OPAL_SET_XIVE IRQ %d -> cpu %d failed: %d", irq, 579 cpu, status); 580 581 xive_unmask(dev, irq, *priv); 582 } 583 584 static void 585 xive_eoi(device_t dev, u_int irq, void *priv) 586 { 587 struct xive_irq *rirq; 588 struct xive_cpu *cpud; 589 uint8_t eoi_val; 590 591 if (irq == MAX_XIVE_IRQS) { 592 cpud = DPCPU_PTR(xive_cpu_data); 593 rirq = &cpud->ipi_data; 594 } else 595 rirq = priv; 596 597 if (rirq->flags & OPAL_XIVE_IRQ_EOI_VIA_FW) 598 opal_call(OPAL_INT_EOI, irq); 599 else if (rirq->flags & OPAL_XIVE_IRQ_STORE_EOI) 600 xive_write_mmap8(rirq->eoi_page + XIVE_IRQ_STORE_EOI, 0); 601 else if (rirq->flags & OPAL_XIVE_IRQ_LSI) 602 xive_read_mmap8(rirq->eoi_page + XIVE_IRQ_LOAD_EOI); 603 else { 604 eoi_val = xive_read_mmap8(rirq->eoi_page + XIVE_IRQ_PQ_00); 605 if ((eoi_val & XIVE_IRQ_VAL_Q) && rirq->trig_page != 0) 606 xive_write_mmap8(rirq->trig_page, 0); 607 } 608 } 609 610 static void 611 xive_ipi(device_t dev, u_int cpu) 612 { 613 struct xive_cpu *xive_cpud; 614 615 xive_cpud = DPCPU_ID_PTR(cpu, xive_cpu_data); 616 617 if (xive_cpud->ipi_data.trig_page == 0) 618 return; 619 xive_write_mmap8(xive_cpud->ipi_data.trig_page, 0); 620 } 621 622 static void 623 xive_mask(device_t dev, u_int irq, void *priv) 624 { 625 struct xive_irq *rirq; 626 627 /* Never mask IPIs */ 628 if (irq == MAX_XIVE_IRQS) 629 return; 630 631 rirq = priv; 632 633 if (!(rirq->flags & OPAL_XIVE_IRQ_LSI)) 634 return; 635 xive_read_mmap8(rirq->eoi_page + XIVE_IRQ_PQ_01); 636 } 637 638 static void 639 xive_unmask(device_t dev, u_int irq, void *priv) 640 { 641 struct xive_irq *rirq; 642 643 rirq = priv; 644 645 xive_read_mmap8(rirq->eoi_page + XIVE_IRQ_PQ_00); 646 } 647 648 static void 649 xive_translate_code(device_t dev, u_int irq, int code, 650 enum intr_trigger *trig, enum intr_polarity *pol) 651 { 652 switch (code) { 653 case 0: 654 /* L to H edge */ 655 *trig = INTR_TRIGGER_EDGE; 656 *pol = INTR_POLARITY_HIGH; 657 break; 658 case 1: 659 /* Active L level */ 660 *trig = INTR_TRIGGER_LEVEL; 661 *pol = INTR_POLARITY_LOW; 662 break; 663 default: 664 *trig = INTR_TRIGGER_CONFORM; 665 *pol = INTR_POLARITY_CONFORM; 666 } 667 } 668 669 /* Private functions. */ 670 /* 671 * Setup the current CPU. Called by the BSP at driver attachment, and by each 672 * AP at wakeup (via xive_smp_cpu_startup()). 673 */ 674 static void 675 xive_setup_cpu(void) 676 { 677 struct xive_softc *sc; 678 struct xive_cpu *cpup; 679 uint32_t val; 680 681 cpup = DPCPU_PTR(xive_cpu_data); 682 683 sc = device_get_softc(root_pic); 684 685 val = bus_read_4(sc->sc_mem, XIVE_TM_QW2_HV_POOL + TM_WORD2); 686 if (val & TM_QW2W2_VP) 687 bus_read_8(sc->sc_mem, XIVE_TM_SPC_PULL_POOL_CTX); 688 689 bus_write_4(sc->sc_mem, XIVE_TM_QW2_HV_POOL + TM_WORD0, 0xff); 690 bus_write_4(sc->sc_mem, XIVE_TM_QW2_HV_POOL + TM_WORD2, 691 TM_QW2W2_VP | cpup->cam); 692 693 xive_unmask(root_pic, cpup->ipi_data.girq, &cpup->ipi_data); 694 xive_write_1(sc, XIVE_TM_CPPR, 0xff); 695 } 696 697 /* Populate an IRQ structure, mapping the EOI and trigger pages. */ 698 static void 699 xive_init_irq(struct xive_irq *irqd, u_int irq) 700 { 701 uint64_t eoi_phys, trig_phys; 702 uint32_t esb_shift; 703 704 opal_call(OPAL_XIVE_GET_IRQ_INFO, irq, 705 vtophys(&irqd->flags), vtophys(&eoi_phys), 706 vtophys(&trig_phys), vtophys(&esb_shift), 707 vtophys(&irqd->chip)); 708 709 irqd->girq = irq; 710 irqd->esb_size = 1 << esb_shift; 711 irqd->eoi_page = (vm_offset_t)pmap_mapdev(eoi_phys, irqd->esb_size); 712 713 if (eoi_phys == trig_phys) 714 irqd->trig_page = irqd->eoi_page; 715 else if (trig_phys != 0) 716 irqd->trig_page = (vm_offset_t)pmap_mapdev(trig_phys, 717 irqd->esb_size); 718 else 719 irqd->trig_page = 0; 720 721 opal_call(OPAL_XIVE_GET_IRQ_CONFIG, irq, vtophys(&irqd->vp), 722 vtophys(&irqd->prio), vtophys(&irqd->lirq)); 723 } 724 725 /* Allocate an IRQ struct before populating it. */ 726 static struct xive_irq * 727 xive_configure_irq(u_int irq) 728 { 729 struct xive_irq *irqd; 730 731 irqd = malloc(sizeof(struct xive_irq), M_XIVE, M_WAITOK); 732 733 xive_init_irq(irqd, irq); 734 735 return (irqd); 736 } 737 738 /* 739 * Part of the OPAL API. OPAL_XIVE_ALLOCATE_VP_BLOCK might require more pages, 740 * provisioned through this call. 741 */ 742 static int 743 xive_provision_page(struct xive_softc *sc) 744 { 745 void *prov_page; 746 int error; 747 748 do { 749 prov_page = contigmalloc(sc->sc_prov_page_size, M_XIVE, 0, 750 0, BUS_SPACE_MAXADDR, 751 sc->sc_prov_page_size, sc->sc_prov_page_size); 752 753 error = opal_call(OPAL_XIVE_DONATE_PAGE, -1, 754 vtophys(prov_page)); 755 } while (error == OPAL_XIVE_PROVISIONING); 756 757 return (0); 758 } 759 760 /* The XIVE_TM_CPPR register must be set by each thread */ 761 static void 762 xive_smp_cpu_startup(void) 763 { 764 765 xive_setup_cpu(); 766 } 767