1 /*- 2 * Copyright (c) 2014 Andrew Turner 3 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com> 4 * All rights reserved. 5 * 6 * Portions of this software were developed by SRI International and the 7 * University of Cambridge Computer Laboratory under DARPA/AFRL contract 8 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. 9 * 10 * Portions of this software were developed by the University of Cambridge 11 * Computer Laboratory as part of the CTSRD Project, with support from the 12 * UK Higher Education Innovation Fund (HEIF). 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 36 #include "opt_platform.h" 37 38 #include <sys/param.h> 39 #include <vm/vm.h> 40 #include <vm/pmap.h> 41 42 #include <machine/bus.h> 43 44 uint8_t generic_bs_r_1(void *, bus_space_handle_t, bus_size_t); 45 uint16_t generic_bs_r_2(void *, bus_space_handle_t, bus_size_t); 46 uint32_t generic_bs_r_4(void *, bus_space_handle_t, bus_size_t); 47 uint64_t generic_bs_r_8(void *, bus_space_handle_t, bus_size_t); 48 49 void generic_bs_rm_1(void *, bus_space_handle_t, bus_size_t, uint8_t *, 50 bus_size_t); 51 void generic_bs_rm_2(void *, bus_space_handle_t, bus_size_t, uint16_t *, 52 bus_size_t); 53 void generic_bs_rm_4(void *, bus_space_handle_t, bus_size_t, uint32_t *, 54 bus_size_t); 55 void generic_bs_rm_8(void *, bus_space_handle_t, bus_size_t, uint64_t *, 56 bus_size_t); 57 58 void generic_bs_rr_1(void *, bus_space_handle_t, bus_size_t, uint8_t *, 59 bus_size_t); 60 void generic_bs_rr_2(void *, bus_space_handle_t, bus_size_t, uint16_t *, 61 bus_size_t); 62 void generic_bs_rr_4(void *, bus_space_handle_t, bus_size_t, uint32_t *, 63 bus_size_t); 64 void generic_bs_rr_8(void *, bus_space_handle_t, bus_size_t, uint64_t *, 65 bus_size_t); 66 67 void generic_bs_w_1(void *, bus_space_handle_t, bus_size_t, uint8_t); 68 void generic_bs_w_2(void *, bus_space_handle_t, bus_size_t, uint16_t); 69 void generic_bs_w_4(void *, bus_space_handle_t, bus_size_t, uint32_t); 70 void generic_bs_w_8(void *, bus_space_handle_t, bus_size_t, uint64_t); 71 72 void generic_bs_wm_1(void *, bus_space_handle_t, bus_size_t, const uint8_t *, 73 bus_size_t); 74 void generic_bs_wm_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *, 75 bus_size_t); 76 void generic_bs_wm_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *, 77 bus_size_t); 78 void generic_bs_wm_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *, 79 bus_size_t); 80 81 void generic_bs_wr_1(void *, bus_space_handle_t, bus_size_t, const uint8_t *, 82 bus_size_t); 83 void generic_bs_wr_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *, 84 bus_size_t); 85 void generic_bs_wr_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *, 86 bus_size_t); 87 void generic_bs_wr_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *, 88 bus_size_t); 89 90 static int 91 generic_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int flags, 92 bus_space_handle_t *bshp) 93 { 94 void *va; 95 96 va = pmap_mapdev(bpa, size); 97 if (va == NULL) 98 return (ENOMEM); 99 *bshp = (bus_space_handle_t)va; 100 return (0); 101 } 102 103 static void 104 generic_bs_unmap(void *t, bus_space_handle_t bsh, bus_size_t size) 105 { 106 107 pmap_unmapdev((void *)bsh, size); 108 } 109 110 static void 111 generic_bs_barrier(void *t, bus_space_handle_t bsh, bus_size_t offset, 112 bus_size_t size, int flags) 113 { 114 } 115 116 static int 117 generic_bs_subregion(void *t, bus_space_handle_t bsh, bus_size_t offset, 118 bus_size_t size, bus_space_handle_t *nbshp) 119 { 120 121 *nbshp = bsh + offset; 122 return (0); 123 } 124 125 struct bus_space memmap_bus = { 126 /* cookie */ 127 .bs_cookie = NULL, 128 129 /* mapping/unmapping */ 130 .bs_map = generic_bs_map, 131 .bs_unmap = generic_bs_unmap, 132 .bs_subregion = generic_bs_subregion, 133 134 /* allocation/deallocation */ 135 .bs_alloc = NULL, 136 .bs_free = NULL, 137 138 /* barrier */ 139 .bs_barrier = generic_bs_barrier, 140 141 /* read single */ 142 .bs_r_1 = generic_bs_r_1, 143 .bs_r_2 = generic_bs_r_2, 144 .bs_r_4 = generic_bs_r_4, 145 .bs_r_8 = generic_bs_r_8, 146 147 /* read multiple */ 148 .bs_rm_1 = NULL, 149 .bs_rm_2 = NULL, 150 .bs_rm_4 = NULL, 151 .bs_rm_8 = NULL, 152 153 /* write single */ 154 .bs_w_1 = generic_bs_w_1, 155 .bs_w_2 = generic_bs_w_2, 156 .bs_w_4 = generic_bs_w_4, 157 .bs_w_8 = generic_bs_w_8, 158 159 /* write multiple */ 160 .bs_wm_1 = NULL, 161 .bs_wm_2 = NULL, 162 .bs_wm_4 = NULL, 163 .bs_wm_8 = NULL, 164 165 /* write region */ 166 .bs_wr_1 = NULL, 167 .bs_wr_2 = NULL, 168 .bs_wr_4 = NULL, 169 .bs_wr_8 = NULL, 170 171 /* set multiple */ 172 .bs_sm_1 = NULL, 173 .bs_sm_2 = NULL, 174 .bs_sm_4 = NULL, 175 .bs_sm_8 = NULL, 176 177 /* set region */ 178 .bs_sr_1 = NULL, 179 .bs_sr_2 = NULL, 180 .bs_sr_4 = NULL, 181 .bs_sr_8 = NULL, 182 183 /* copy */ 184 .bs_c_1 = NULL, 185 .bs_c_2 = NULL, 186 .bs_c_4 = NULL, 187 .bs_c_8 = NULL, 188 189 /* read single stream */ 190 .bs_r_1_s = NULL, 191 .bs_r_2_s = NULL, 192 .bs_r_4_s = NULL, 193 .bs_r_8_s = NULL, 194 195 /* read multiple stream */ 196 .bs_rm_1_s = NULL, 197 .bs_rm_2_s = NULL, 198 .bs_rm_4_s = NULL, 199 .bs_rm_8_s = NULL, 200 201 /* read region stream */ 202 .bs_rr_1_s = NULL, 203 .bs_rr_2_s = NULL, 204 .bs_rr_4_s = NULL, 205 .bs_rr_8_s = NULL, 206 207 /* write single stream */ 208 .bs_w_1_s = NULL, 209 .bs_w_2_s = NULL, 210 .bs_w_4_s = NULL, 211 .bs_w_8_s = NULL, 212 213 /* write multiple stream */ 214 .bs_wm_1_s = NULL, 215 .bs_wm_2_s = NULL, 216 .bs_wm_4_s = NULL, 217 .bs_wm_8_s = NULL, 218 219 /* write region stream */ 220 .bs_wr_1_s = NULL, 221 .bs_wr_2_s = NULL, 222 .bs_wr_4_s = NULL, 223 .bs_wr_8_s = NULL, 224 }; 225 226 #ifdef FDT 227 bus_space_tag_t fdtbus_bs_tag = &memmap_bus; 228 #endif 229