1 /*- 2 * Copyright (c) 2015-2017 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * Portions of this software were developed by SRI International and the 6 * University of Cambridge Computer Laboratory under DARPA/AFRL contract 7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Portions of this software were developed by the University of Cambridge 10 * Computer Laboratory as part of the CTSRD Project, with support from the 11 * UK Higher Education Innovation Fund (HEIF). 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 /* 36 * RISC-V Timer 37 */ 38 39 #include "opt_platform.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/bus.h> 44 #include <sys/kernel.h> 45 #include <sys/module.h> 46 #include <sys/rman.h> 47 #include <sys/timeet.h> 48 #include <sys/timetc.h> 49 #include <sys/vdso.h> 50 #include <sys/watchdog.h> 51 52 #include <machine/cpufunc.h> 53 #include <machine/intr.h> 54 #include <machine/md_var.h> 55 #include <machine/sbi.h> 56 57 #include <dev/ofw/ofw_bus.h> 58 #include <dev/ofw/openfirm.h> 59 60 struct riscv_timer_softc { 61 struct resource *irq_res; 62 void *ih; 63 uint32_t clkfreq; 64 struct eventtimer et; 65 }; 66 static struct riscv_timer_softc *riscv_timer_sc = NULL; 67 68 static timecounter_get_t riscv_timer_tc_get_timecount; 69 static timecounter_fill_vdso_timehands_t riscv_timer_tc_fill_vdso_timehands; 70 71 static struct timecounter riscv_timer_timecount = { 72 .tc_name = "RISC-V Timecounter", 73 .tc_get_timecount = riscv_timer_tc_get_timecount, 74 .tc_poll_pps = NULL, 75 .tc_counter_mask = ~0u, 76 .tc_frequency = 0, 77 .tc_quality = 1000, 78 .tc_fill_vdso_timehands = riscv_timer_tc_fill_vdso_timehands, 79 }; 80 81 static inline uint64_t 82 get_timecount(void) 83 { 84 85 return (rdtime()); 86 } 87 88 static inline void 89 set_timecmp(uint64_t timecmp) 90 { 91 92 if (has_sstc) 93 csr_write(stimecmp, timecmp); 94 else 95 sbi_set_timer(timecmp); 96 } 97 98 static u_int 99 riscv_timer_tc_get_timecount(struct timecounter *tc __unused) 100 { 101 102 return (get_timecount()); 103 } 104 105 static uint32_t 106 riscv_timer_tc_fill_vdso_timehands(struct vdso_timehands *vdso_th, 107 struct timecounter *tc) 108 { 109 vdso_th->th_algo = VDSO_TH_ALGO_RISCV_RDTIME; 110 bzero(vdso_th->th_res, sizeof(vdso_th->th_res)); 111 return (1); 112 } 113 114 static int 115 riscv_timer_et_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 116 { 117 uint64_t counts; 118 119 if (first != 0) { 120 counts = ((uint32_t)et->et_frequency * first) >> 32; 121 set_timecmp(get_timecount() + counts); 122 123 return (0); 124 } 125 126 return (EINVAL); 127 } 128 129 static int 130 riscv_timer_et_stop(struct eventtimer *et) 131 { 132 133 /* Disable timer interrupts. */ 134 csr_clear(sie, SIE_STIE); 135 136 return (0); 137 } 138 139 static int 140 riscv_timer_intr(void *arg) 141 { 142 struct riscv_timer_softc *sc; 143 144 sc = (struct riscv_timer_softc *)arg; 145 146 csr_clear(sip, SIP_STIP); 147 148 if (sc->et.et_active) 149 sc->et.et_event_cb(&sc->et, sc->et.et_arg); 150 151 return (FILTER_HANDLED); 152 } 153 154 static int 155 riscv_timer_get_timebase(device_t dev, uint32_t *freq) 156 { 157 phandle_t node; 158 int len; 159 160 node = OF_finddevice("/cpus"); 161 if (node == -1) { 162 if (bootverbose) 163 device_printf(dev, "Can't find cpus node.\n"); 164 return (ENXIO); 165 } 166 167 len = OF_getproplen(node, "timebase-frequency"); 168 if (len != 4) { 169 if (bootverbose) 170 device_printf(dev, 171 "Can't find timebase-frequency property.\n"); 172 return (ENXIO); 173 } 174 175 OF_getencprop(node, "timebase-frequency", freq, len); 176 177 return (0); 178 } 179 180 static int 181 riscv_timer_probe(device_t dev) 182 { 183 184 device_set_desc(dev, "RISC-V Timer"); 185 186 return (BUS_PROBE_DEFAULT); 187 } 188 189 static int 190 riscv_timer_attach(device_t dev) 191 { 192 struct riscv_timer_softc *sc; 193 int irq, rid, error; 194 phandle_t iparent; 195 pcell_t cell; 196 197 sc = device_get_softc(dev); 198 if (riscv_timer_sc != NULL) 199 return (ENXIO); 200 201 if (device_get_unit(dev) != 0) 202 return (ENXIO); 203 204 if (riscv_timer_get_timebase(dev, &sc->clkfreq) != 0) { 205 device_printf(dev, "No clock frequency specified\n"); 206 return (ENXIO); 207 } 208 209 riscv_timer_sc = sc; 210 211 iparent = OF_xref_from_node(ofw_bus_get_node(intr_irq_root_dev)); 212 cell = IRQ_TIMER_SUPERVISOR; 213 irq = ofw_bus_map_intr(dev, iparent, 1, &cell); 214 error = bus_set_resource(dev, SYS_RES_IRQ, 0, irq, 1); 215 if (error != 0) { 216 device_printf(dev, "Unable to register IRQ resource\n"); 217 return (ENXIO); 218 } 219 220 rid = 0; 221 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 222 RF_ACTIVE); 223 if (sc->irq_res == NULL) { 224 device_printf(dev, "Unable to alloc IRQ resource\n"); 225 return (ENXIO); 226 } 227 228 /* Setup IRQs handler */ 229 error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_CLK, 230 riscv_timer_intr, NULL, sc, &sc->ih); 231 if (error != 0) { 232 device_printf(dev, "Unable to setup IRQ resource\n"); 233 return (ENXIO); 234 } 235 236 riscv_timer_timecount.tc_frequency = sc->clkfreq; 237 riscv_timer_timecount.tc_priv = sc; 238 tc_init(&riscv_timer_timecount); 239 240 sc->et.et_name = "RISC-V Eventtimer"; 241 sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU; 242 sc->et.et_quality = 1000; 243 244 sc->et.et_frequency = sc->clkfreq; 245 sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency; 246 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency; 247 sc->et.et_start = riscv_timer_et_start; 248 sc->et.et_stop = riscv_timer_et_stop; 249 sc->et.et_priv = sc; 250 et_register(&sc->et); 251 252 set_cputicker(get_timecount, sc->clkfreq, false); 253 254 return (0); 255 } 256 257 static device_method_t riscv_timer_methods[] = { 258 DEVMETHOD(device_probe, riscv_timer_probe), 259 DEVMETHOD(device_attach, riscv_timer_attach), 260 { 0, 0 } 261 }; 262 263 static driver_t riscv_timer_driver = { 264 "timer", 265 riscv_timer_methods, 266 sizeof(struct riscv_timer_softc), 267 }; 268 269 EARLY_DRIVER_MODULE(timer, nexus, riscv_timer_driver, 0, 0, 270 BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE); 271 272 void 273 DELAY(int usec) 274 { 275 int64_t counts, counts_per_usec; 276 uint64_t first, last; 277 278 /* 279 * Check the timers are setup, if not just 280 * use a for loop for the meantime 281 */ 282 if (riscv_timer_sc == NULL) { 283 for (; usec > 0; usec--) 284 for (counts = 200; counts > 0; counts--) 285 /* 286 * Prevent the compiler from optimizing 287 * out the loop 288 */ 289 cpufunc_nullop(); 290 return; 291 } 292 TSENTER(); 293 294 /* Get the number of times to count */ 295 counts_per_usec = ((riscv_timer_timecount.tc_frequency / 1000000) + 1); 296 297 /* 298 * Clamp the timeout at a maximum value (about 32 seconds with 299 * a 66MHz clock). *Nobody* should be delay()ing for anywhere 300 * near that length of time and if they are, they should be hung 301 * out to dry. 302 */ 303 if (usec >= (0x80000000U / counts_per_usec)) 304 counts = (0x80000000U / counts_per_usec) - 1; 305 else 306 counts = usec * counts_per_usec; 307 308 first = get_timecount(); 309 310 while (counts > 0) { 311 last = get_timecount(); 312 counts -= (int64_t)(last - first); 313 first = last; 314 } 315 TSEXIT(); 316 } 317