1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2003-2008, Joseph Koshy 5 * Copyright (c) 2007 The FreeBSD Foundation 6 * All rights reserved. 7 * 8 * Portions of this software were developed by A. Joseph Koshy under 9 * sponsorship from the FreeBSD Foundation and Google, Inc. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 #ifndef _SYS_PMC_H_ 36 #define _SYS_PMC_H_ 37 38 #include <dev/hwpmc/pmc_events.h> 39 #include <sys/proc.h> 40 #include <sys/counter.h> 41 #include <machine/pmc_mdep.h> 42 #include <machine/profile.h> 43 #ifdef _KERNEL 44 #include <sys/epoch.h> 45 #include <ck_queue.h> 46 #endif 47 48 #define PMC_MODULE_NAME "hwpmc" 49 #define PMC_NAME_MAX 64 /* HW counter name size */ 50 #define PMC_CLASS_MAX 8 /* max #classes of PMCs per-system */ 51 52 /* 53 * Kernel<->userland API version number [MMmmpppp] 54 * 55 * Major numbers are to be incremented when an incompatible change to 56 * the ABI occurs that older clients will not be able to handle. 57 * 58 * Minor numbers are incremented when a backwards compatible change 59 * occurs that allows older correct programs to run unchanged. For 60 * example, when support for a new PMC type is added. 61 * 62 * The patch version is incremented for every bug fix. 63 */ 64 #define PMC_VERSION_MAJOR 0x09 65 #define PMC_VERSION_MINOR 0x03 66 #define PMC_VERSION_PATCH 0x0000 67 68 #define PMC_VERSION (PMC_VERSION_MAJOR << 24 | \ 69 PMC_VERSION_MINOR << 16 | PMC_VERSION_PATCH) 70 71 #define PMC_CPUID_LEN 64 72 /* cpu model name for pmu lookup */ 73 extern char pmc_cpuid[PMC_CPUID_LEN]; 74 75 /* 76 * Kinds of CPUs known. 77 * 78 * We keep track of CPU variants that need to be distinguished in 79 * some way for PMC operations. CPU names are grouped by manufacturer 80 * and numbered sparsely in order to minimize changes to the ABI involved 81 * when new CPUs are added. 82 */ 83 84 #define __PMC_CPUS() \ 85 __PMC_CPU(AMD_K7, 0x00, "AMD K7") \ 86 __PMC_CPU(AMD_K8, 0x01, "AMD K8") \ 87 __PMC_CPU(INTEL_P5, 0x80, "Intel Pentium") \ 88 __PMC_CPU(INTEL_P6, 0x81, "Intel Pentium Pro") \ 89 __PMC_CPU(INTEL_CL, 0x82, "Intel Celeron") \ 90 __PMC_CPU(INTEL_PII, 0x83, "Intel Pentium II") \ 91 __PMC_CPU(INTEL_PIII, 0x84, "Intel Pentium III") \ 92 __PMC_CPU(INTEL_PM, 0x85, "Intel Pentium M") \ 93 __PMC_CPU(INTEL_PIV, 0x86, "Intel Pentium IV") \ 94 __PMC_CPU(INTEL_CORE, 0x87, "Intel Core Solo/Duo") \ 95 __PMC_CPU(INTEL_CORE2, 0x88, "Intel Core2") \ 96 __PMC_CPU(INTEL_CORE2EXTREME, 0x89, "Intel Core2 Extreme") \ 97 __PMC_CPU(INTEL_ATOM, 0x8A, "Intel Atom") \ 98 __PMC_CPU(INTEL_COREI7, 0x8B, "Intel Core i7") \ 99 __PMC_CPU(INTEL_WESTMERE, 0x8C, "Intel Westmere") \ 100 __PMC_CPU(INTEL_SANDYBRIDGE, 0x8D, "Intel Sandy Bridge") \ 101 __PMC_CPU(INTEL_IVYBRIDGE, 0x8E, "Intel Ivy Bridge") \ 102 __PMC_CPU(INTEL_SANDYBRIDGE_XEON, 0x8F, "Intel Sandy Bridge Xeon") \ 103 __PMC_CPU(INTEL_IVYBRIDGE_XEON, 0x90, "Intel Ivy Bridge Xeon") \ 104 __PMC_CPU(INTEL_HASWELL, 0x91, "Intel Haswell") \ 105 __PMC_CPU(INTEL_ATOM_SILVERMONT, 0x92, "Intel Atom Silvermont") \ 106 __PMC_CPU(INTEL_NEHALEM_EX, 0x93, "Intel Nehalem Xeon 7500") \ 107 __PMC_CPU(INTEL_WESTMERE_EX, 0x94, "Intel Westmere Xeon E7") \ 108 __PMC_CPU(INTEL_HASWELL_XEON, 0x95, "Intel Haswell Xeon E5 v3") \ 109 __PMC_CPU(INTEL_BROADWELL, 0x96, "Intel Broadwell") \ 110 __PMC_CPU(INTEL_BROADWELL_XEON, 0x97, "Intel Broadwell Xeon") \ 111 __PMC_CPU(INTEL_SKYLAKE, 0x98, "Intel Skylake") \ 112 __PMC_CPU(INTEL_SKYLAKE_XEON, 0x99, "Intel Skylake Xeon") \ 113 __PMC_CPU(INTEL_XSCALE, 0x100, "Intel XScale") \ 114 __PMC_CPU(MIPS_24K, 0x200, "MIPS 24K") \ 115 __PMC_CPU(MIPS_OCTEON, 0x201, "Cavium Octeon") \ 116 __PMC_CPU(MIPS_74K, 0x202, "MIPS 74K") \ 117 __PMC_CPU(MIPS_BERI, 0x203, "BERI") \ 118 __PMC_CPU(PPC_7450, 0x300, "PowerPC MPC7450") \ 119 __PMC_CPU(PPC_E500, 0x340, "PowerPC e500 Core") \ 120 __PMC_CPU(PPC_970, 0x380, "IBM PowerPC 970") \ 121 __PMC_CPU(GENERIC, 0x400, "Generic") \ 122 __PMC_CPU(ARMV7_CORTEX_A5, 0x500, "ARMv7 Cortex A5") \ 123 __PMC_CPU(ARMV7_CORTEX_A7, 0x501, "ARMv7 Cortex A7") \ 124 __PMC_CPU(ARMV7_CORTEX_A8, 0x502, "ARMv7 Cortex A8") \ 125 __PMC_CPU(ARMV7_CORTEX_A9, 0x503, "ARMv7 Cortex A9") \ 126 __PMC_CPU(ARMV7_CORTEX_A15, 0x504, "ARMv7 Cortex A15") \ 127 __PMC_CPU(ARMV7_CORTEX_A17, 0x505, "ARMv7 Cortex A17") \ 128 __PMC_CPU(ARMV8_CORTEX_A53, 0x600, "ARMv8 Cortex A53") \ 129 __PMC_CPU(ARMV8_CORTEX_A57, 0x601, "ARMv8 Cortex A57") 130 131 enum pmc_cputype { 132 #undef __PMC_CPU 133 #define __PMC_CPU(S,V,D) PMC_CPU_##S = V, 134 __PMC_CPUS() 135 }; 136 137 #define PMC_CPU_FIRST PMC_CPU_AMD_K7 138 #define PMC_CPU_LAST PMC_CPU_GENERIC 139 140 /* 141 * Classes of PMCs 142 */ 143 144 #define __PMC_CLASSES() \ 145 __PMC_CLASS(TSC, 0x00, "CPU Timestamp counter") \ 146 __PMC_CLASS(K7, 0x01, "AMD K7 performance counters") \ 147 __PMC_CLASS(K8, 0x02, "AMD K8 performance counters") \ 148 __PMC_CLASS(P5, 0x03, "Intel Pentium counters") \ 149 __PMC_CLASS(P6, 0x04, "Intel Pentium Pro counters") \ 150 __PMC_CLASS(P4, 0x05, "Intel Pentium-IV counters") \ 151 __PMC_CLASS(IAF, 0x06, "Intel Core2/Atom, fixed function") \ 152 __PMC_CLASS(IAP, 0x07, "Intel Core...Atom, programmable") \ 153 __PMC_CLASS(UCF, 0x08, "Intel Uncore fixed function") \ 154 __PMC_CLASS(UCP, 0x09, "Intel Uncore programmable") \ 155 __PMC_CLASS(XSCALE, 0x0A, "Intel XScale counters") \ 156 __PMC_CLASS(MIPS24K, 0x0B, "MIPS 24K") \ 157 __PMC_CLASS(OCTEON, 0x0C, "Cavium Octeon") \ 158 __PMC_CLASS(PPC7450, 0x0D, "Motorola MPC7450 class") \ 159 __PMC_CLASS(PPC970, 0x0E, "IBM PowerPC 970 class") \ 160 __PMC_CLASS(SOFT, 0x0F, "Software events") \ 161 __PMC_CLASS(ARMV7, 0x10, "ARMv7") \ 162 __PMC_CLASS(ARMV8, 0x11, "ARMv8") \ 163 __PMC_CLASS(MIPS74K, 0x12, "MIPS 74K") \ 164 __PMC_CLASS(E500, 0x13, "Freescale e500 class") \ 165 __PMC_CLASS(BERI, 0x14, "MIPS BERI") 166 167 enum pmc_class { 168 #undef __PMC_CLASS 169 #define __PMC_CLASS(S,V,D) PMC_CLASS_##S = V, 170 __PMC_CLASSES() 171 }; 172 173 #define PMC_CLASS_FIRST PMC_CLASS_TSC 174 #define PMC_CLASS_LAST PMC_CLASS_E500 175 176 /* 177 * A PMC can be in the following states: 178 * 179 * Hardware states: 180 * DISABLED -- administratively prohibited from being used. 181 * FREE -- HW available for use 182 * Software states: 183 * ALLOCATED -- allocated 184 * STOPPED -- allocated, but not counting events 185 * RUNNING -- allocated, and in operation; 'pm_runcount' 186 * holds the number of CPUs using this PMC at 187 * a given instant 188 * DELETED -- being destroyed 189 */ 190 191 #define __PMC_HWSTATES() \ 192 __PMC_STATE(DISABLED) \ 193 __PMC_STATE(FREE) 194 195 #define __PMC_SWSTATES() \ 196 __PMC_STATE(ALLOCATED) \ 197 __PMC_STATE(STOPPED) \ 198 __PMC_STATE(RUNNING) \ 199 __PMC_STATE(DELETED) 200 201 #define __PMC_STATES() \ 202 __PMC_HWSTATES() \ 203 __PMC_SWSTATES() 204 205 enum pmc_state { 206 #undef __PMC_STATE 207 #define __PMC_STATE(S) PMC_STATE_##S, 208 __PMC_STATES() 209 __PMC_STATE(MAX) 210 }; 211 212 #define PMC_STATE_FIRST PMC_STATE_DISABLED 213 #define PMC_STATE_LAST PMC_STATE_DELETED 214 215 /* 216 * An allocated PMC may used as a 'global' counter or as a 217 * 'thread-private' one. Each such mode of use can be in either 218 * statistical sampling mode or in counting mode. Thus a PMC in use 219 * 220 * SS i.e., SYSTEM STATISTICAL -- system-wide statistical profiling 221 * SC i.e., SYSTEM COUNTER -- system-wide counting mode 222 * TS i.e., THREAD STATISTICAL -- thread virtual, statistical profiling 223 * TC i.e., THREAD COUNTER -- thread virtual, counting mode 224 * 225 * Statistical profiling modes rely on the PMC periodically delivering 226 * a interrupt to the CPU (when the configured number of events have 227 * been measured), so the PMC must have the ability to generate 228 * interrupts. 229 * 230 * In counting modes, the PMC counts its configured events, with the 231 * value of the PMC being read whenever needed by its owner process. 232 * 233 * The thread specific modes "virtualize" the PMCs -- the PMCs appear 234 * to be thread private and count events only when the profiled thread 235 * actually executes on the CPU. 236 * 237 * The system-wide "global" modes keep the PMCs running all the time 238 * and are used to measure the behaviour of the whole system. 239 */ 240 241 #define __PMC_MODES() \ 242 __PMC_MODE(SS, 0) \ 243 __PMC_MODE(SC, 1) \ 244 __PMC_MODE(TS, 2) \ 245 __PMC_MODE(TC, 3) 246 247 enum pmc_mode { 248 #undef __PMC_MODE 249 #define __PMC_MODE(M,N) PMC_MODE_##M = N, 250 __PMC_MODES() 251 }; 252 253 #define PMC_MODE_FIRST PMC_MODE_SS 254 #define PMC_MODE_LAST PMC_MODE_TC 255 256 #define PMC_IS_COUNTING_MODE(mode) \ 257 ((mode) == PMC_MODE_SC || (mode) == PMC_MODE_TC) 258 #define PMC_IS_SYSTEM_MODE(mode) \ 259 ((mode) == PMC_MODE_SS || (mode) == PMC_MODE_SC) 260 #define PMC_IS_SAMPLING_MODE(mode) \ 261 ((mode) == PMC_MODE_SS || (mode) == PMC_MODE_TS) 262 #define PMC_IS_VIRTUAL_MODE(mode) \ 263 ((mode) == PMC_MODE_TS || (mode) == PMC_MODE_TC) 264 265 /* 266 * PMC row disposition 267 */ 268 269 #define __PMC_DISPOSITIONS(N) \ 270 __PMC_DISP(STANDALONE) /* global/disabled counters */ \ 271 __PMC_DISP(FREE) /* free/available */ \ 272 __PMC_DISP(THREAD) /* thread-virtual PMCs */ \ 273 __PMC_DISP(UNKNOWN) /* sentinel */ 274 275 enum pmc_disp { 276 #undef __PMC_DISP 277 #define __PMC_DISP(D) PMC_DISP_##D , 278 __PMC_DISPOSITIONS() 279 }; 280 281 #define PMC_DISP_FIRST PMC_DISP_STANDALONE 282 #define PMC_DISP_LAST PMC_DISP_THREAD 283 284 /* 285 * Counter capabilities 286 * 287 * __PMC_CAPS(NAME, VALUE, DESCRIPTION) 288 */ 289 290 #define __PMC_CAPS() \ 291 __PMC_CAP(INTERRUPT, 0, "generate interrupts") \ 292 __PMC_CAP(USER, 1, "count user-mode events") \ 293 __PMC_CAP(SYSTEM, 2, "count system-mode events") \ 294 __PMC_CAP(EDGE, 3, "do edge detection of events") \ 295 __PMC_CAP(THRESHOLD, 4, "ignore events below a threshold") \ 296 __PMC_CAP(READ, 5, "read PMC counter") \ 297 __PMC_CAP(WRITE, 6, "reprogram PMC counter") \ 298 __PMC_CAP(INVERT, 7, "invert comparison sense") \ 299 __PMC_CAP(QUALIFIER, 8, "further qualify monitored events") \ 300 __PMC_CAP(PRECISE, 9, "perform precise sampling") \ 301 __PMC_CAP(TAGGING, 10, "tag upstream events") \ 302 __PMC_CAP(CASCADE, 11, "cascade counters") 303 304 enum pmc_caps 305 { 306 #undef __PMC_CAP 307 #define __PMC_CAP(NAME, VALUE, DESCR) PMC_CAP_##NAME = (1 << VALUE) , 308 __PMC_CAPS() 309 }; 310 311 #define PMC_CAP_FIRST PMC_CAP_INTERRUPT 312 #define PMC_CAP_LAST PMC_CAP_CASCADE 313 314 /* 315 * PMC Event Numbers 316 * 317 * These are generated from the definitions in "dev/hwpmc/pmc_events.h". 318 */ 319 320 enum pmc_event { 321 #undef __PMC_EV 322 #undef __PMC_EV_BLOCK 323 #define __PMC_EV_BLOCK(C,V) PMC_EV_ ## C ## __BLOCK_START = (V) - 1 , 324 #define __PMC_EV(C,N) PMC_EV_ ## C ## _ ## N , 325 __PMC_EVENTS() 326 }; 327 328 /* 329 * PMC SYSCALL INTERFACE 330 */ 331 332 /* 333 * "PMC_OPS" -- these are the commands recognized by the kernel 334 * module, and are used when performing a system call from userland. 335 */ 336 #define __PMC_OPS() \ 337 __PMC_OP(CONFIGURELOG, "Set log file") \ 338 __PMC_OP(FLUSHLOG, "Flush log file") \ 339 __PMC_OP(GETCPUINFO, "Get system CPU information") \ 340 __PMC_OP(GETDRIVERSTATS, "Get driver statistics") \ 341 __PMC_OP(GETMODULEVERSION, "Get module version") \ 342 __PMC_OP(GETPMCINFO, "Get per-cpu PMC information") \ 343 __PMC_OP(PMCADMIN, "Set PMC state") \ 344 __PMC_OP(PMCALLOCATE, "Allocate and configure a PMC") \ 345 __PMC_OP(PMCATTACH, "Attach a PMC to a process") \ 346 __PMC_OP(PMCDETACH, "Detach a PMC from a process") \ 347 __PMC_OP(PMCGETMSR, "Get a PMC's hardware address") \ 348 __PMC_OP(PMCRELEASE, "Release a PMC") \ 349 __PMC_OP(PMCRW, "Read/Set a PMC") \ 350 __PMC_OP(PMCSETCOUNT, "Set initial count/sampling rate") \ 351 __PMC_OP(PMCSTART, "Start a PMC") \ 352 __PMC_OP(PMCSTOP, "Stop a PMC") \ 353 __PMC_OP(WRITELOG, "Write a cookie to the log file") \ 354 __PMC_OP(CLOSELOG, "Close log file") \ 355 __PMC_OP(GETDYNEVENTINFO, "Get dynamic events list") 356 357 358 enum pmc_ops { 359 #undef __PMC_OP 360 #define __PMC_OP(N, D) PMC_OP_##N, 361 __PMC_OPS() 362 }; 363 364 365 /* 366 * Flags used in operations on PMCs. 367 */ 368 369 #define PMC_F_UNUSED1 0x00000001 /* unused */ 370 #define PMC_F_DESCENDANTS 0x00000002 /*OP ALLOCATE track descendants */ 371 #define PMC_F_LOG_PROCCSW 0x00000004 /*OP ALLOCATE track ctx switches */ 372 #define PMC_F_LOG_PROCEXIT 0x00000008 /*OP ALLOCATE log proc exits */ 373 #define PMC_F_NEWVALUE 0x00000010 /*OP RW write new value */ 374 #define PMC_F_OLDVALUE 0x00000020 /*OP RW get old value */ 375 376 /* V2 API */ 377 #define PMC_F_CALLCHAIN 0x00000080 /*OP ALLOCATE capture callchains */ 378 #define PMC_F_USERCALLCHAIN 0x00000100 /*OP ALLOCATE use userspace stack */ 379 380 /* internal flags */ 381 #define PMC_F_ATTACHED_TO_OWNER 0x00010000 /*attached to owner*/ 382 #define PMC_F_NEEDS_LOGFILE 0x00020000 /*needs log file */ 383 #define PMC_F_ATTACH_DONE 0x00040000 /*attached at least once */ 384 385 #define PMC_CALLCHAIN_DEPTH_MAX 512 386 387 #define PMC_CC_F_USERSPACE 0x01 /*userspace callchain*/ 388 389 /* 390 * Cookies used to denote allocated PMCs, and the values of PMCs. 391 */ 392 393 typedef uint32_t pmc_id_t; 394 typedef uint64_t pmc_value_t; 395 396 #define PMC_ID_INVALID (~ (pmc_id_t) 0) 397 398 /* 399 * PMC IDs have the following format: 400 * 401 * +-----------------------+-------+-----------+ 402 * | CPU | PMC MODE | CLASS | ROW INDEX | 403 * +-----------------------+-------+-----------+ 404 * 405 * where CPU is 12 bits, MODE 8, CLASS 4, and ROW INDEX 8 Field 'CPU' 406 * is set to the requested CPU for system-wide PMCs or PMC_CPU_ANY for 407 * process-mode PMCs. Field 'PMC MODE' is the allocated PMC mode. 408 * Field 'PMC CLASS' is the class of the PMC. Field 'ROW INDEX' is the 409 * row index for the PMC. 410 * 411 * The 'ROW INDEX' ranges over 0..NWPMCS where NHWPMCS is the total 412 * number of hardware PMCs on this cpu. 413 */ 414 415 416 #define PMC_ID_TO_ROWINDEX(ID) ((ID) & 0xFF) 417 #define PMC_ID_TO_CLASS(ID) (((ID) & 0xF00) >> 8) 418 #define PMC_ID_TO_MODE(ID) (((ID) & 0xFF000) >> 12) 419 #define PMC_ID_TO_CPU(ID) (((ID) & 0xFFF00000) >> 20) 420 #define PMC_ID_MAKE_ID(CPU,MODE,CLASS,ROWINDEX) \ 421 ((((CPU) & 0xFFF) << 20) | (((MODE) & 0xFF) << 12) | \ 422 (((CLASS) & 0xF) << 8) | ((ROWINDEX) & 0xFF)) 423 424 /* 425 * Data structures for system calls supported by the pmc driver. 426 */ 427 428 /* 429 * OP PMCALLOCATE 430 * 431 * Allocate a PMC on the named CPU. 432 */ 433 434 #define PMC_CPU_ANY ~0 435 436 struct pmc_op_pmcallocate { 437 uint32_t pm_caps; /* PMC_CAP_* */ 438 uint32_t pm_cpu; /* CPU number or PMC_CPU_ANY */ 439 enum pmc_class pm_class; /* class of PMC desired */ 440 enum pmc_event pm_ev; /* [enum pmc_event] desired */ 441 uint32_t pm_flags; /* additional modifiers PMC_F_* */ 442 enum pmc_mode pm_mode; /* desired mode */ 443 pmc_id_t pm_pmcid; /* [return] process pmc id */ 444 pmc_value_t pm_count; /* initial/sample count */ 445 446 union pmc_md_op_pmcallocate pm_md; /* MD layer extensions */ 447 }; 448 449 /* 450 * OP PMCADMIN 451 * 452 * Set the administrative state (i.e., whether enabled or disabled) of 453 * a PMC 'pm_pmc' on CPU 'pm_cpu'. Note that 'pm_pmc' specifies an 454 * absolute PMC number and need not have been first allocated by the 455 * calling process. 456 */ 457 458 struct pmc_op_pmcadmin { 459 int pm_cpu; /* CPU# */ 460 uint32_t pm_flags; /* flags */ 461 int pm_pmc; /* PMC# */ 462 enum pmc_state pm_state; /* desired state */ 463 }; 464 465 /* 466 * OP PMCATTACH / OP PMCDETACH 467 * 468 * Attach/detach a PMC and a process. 469 */ 470 471 struct pmc_op_pmcattach { 472 pmc_id_t pm_pmc; /* PMC to attach to */ 473 pid_t pm_pid; /* target process */ 474 }; 475 476 /* 477 * OP PMCSETCOUNT 478 * 479 * Set the sampling rate (i.e., the reload count) for statistical counters. 480 * 'pm_pmcid' need to have been previously allocated using PMCALLOCATE. 481 */ 482 483 struct pmc_op_pmcsetcount { 484 pmc_value_t pm_count; /* initial/sample count */ 485 pmc_id_t pm_pmcid; /* PMC id to set */ 486 }; 487 488 489 /* 490 * OP PMCRW 491 * 492 * Read the value of a PMC named by 'pm_pmcid'. 'pm_pmcid' needs 493 * to have been previously allocated using PMCALLOCATE. 494 */ 495 496 497 struct pmc_op_pmcrw { 498 uint32_t pm_flags; /* PMC_F_{OLD,NEW}VALUE*/ 499 pmc_id_t pm_pmcid; /* pmc id */ 500 pmc_value_t pm_value; /* new&returned value */ 501 }; 502 503 504 /* 505 * OP GETPMCINFO 506 * 507 * retrieve PMC state for a named CPU. The caller is expected to 508 * allocate 'npmc' * 'struct pmc_info' bytes of space for the return 509 * values. 510 */ 511 512 struct pmc_info { 513 char pm_name[PMC_NAME_MAX]; /* pmc name */ 514 enum pmc_class pm_class; /* enum pmc_class */ 515 int pm_enabled; /* whether enabled */ 516 enum pmc_disp pm_rowdisp; /* FREE, THREAD or STANDLONE */ 517 pid_t pm_ownerpid; /* owner, or -1 */ 518 enum pmc_mode pm_mode; /* current mode [enum pmc_mode] */ 519 enum pmc_event pm_event; /* current event */ 520 uint32_t pm_flags; /* current flags */ 521 pmc_value_t pm_reloadcount; /* sampling counters only */ 522 }; 523 524 struct pmc_op_getpmcinfo { 525 int32_t pm_cpu; /* 0 <= cpu < mp_maxid */ 526 struct pmc_info pm_pmcs[]; /* space for 'npmc' structures */ 527 }; 528 529 530 /* 531 * OP GETCPUINFO 532 * 533 * Retrieve system CPU information. 534 */ 535 536 537 struct pmc_classinfo { 538 enum pmc_class pm_class; /* class id */ 539 uint32_t pm_caps; /* counter capabilities */ 540 uint32_t pm_width; /* width of the PMC */ 541 uint32_t pm_num; /* number of PMCs in class */ 542 }; 543 544 struct pmc_op_getcpuinfo { 545 enum pmc_cputype pm_cputype; /* what kind of CPU */ 546 uint32_t pm_ncpu; /* max CPU number */ 547 uint32_t pm_npmc; /* #PMCs per CPU */ 548 uint32_t pm_nclass; /* #classes of PMCs */ 549 struct pmc_classinfo pm_classes[PMC_CLASS_MAX]; 550 }; 551 552 /* 553 * OP CONFIGURELOG 554 * 555 * Configure a log file for writing system-wide statistics to. 556 */ 557 558 struct pmc_op_configurelog { 559 int pm_flags; 560 int pm_logfd; /* logfile fd (or -1) */ 561 }; 562 563 /* 564 * OP GETDRIVERSTATS 565 * 566 * Retrieve pmc(4) driver-wide statistics. 567 */ 568 #ifdef _KERNEL 569 struct pmc_driverstats { 570 counter_u64_t pm_intr_ignored; /* #interrupts ignored */ 571 counter_u64_t pm_intr_processed; /* #interrupts processed */ 572 counter_u64_t pm_intr_bufferfull; /* #interrupts with ENOSPC */ 573 counter_u64_t pm_syscalls; /* #syscalls */ 574 counter_u64_t pm_syscall_errors; /* #syscalls with errors */ 575 counter_u64_t pm_buffer_requests; /* #buffer requests */ 576 counter_u64_t pm_buffer_requests_failed; /* #failed buffer requests */ 577 counter_u64_t pm_log_sweeps; /* #sample buffer processing 578 passes */ 579 counter_u64_t pm_merges; /* merged k+u */ 580 counter_u64_t pm_overwrites; /* UR overwrites */ 581 }; 582 #endif 583 584 struct pmc_op_getdriverstats { 585 unsigned int pm_intr_ignored; /* #interrupts ignored */ 586 unsigned int pm_intr_processed; /* #interrupts processed */ 587 unsigned int pm_intr_bufferfull; /* #interrupts with ENOSPC */ 588 unsigned int pm_syscalls; /* #syscalls */ 589 unsigned int pm_syscall_errors; /* #syscalls with errors */ 590 unsigned int pm_buffer_requests; /* #buffer requests */ 591 unsigned int pm_buffer_requests_failed; /* #failed buffer requests */ 592 unsigned int pm_log_sweeps; /* #sample buffer processing 593 passes */ 594 }; 595 596 /* 597 * OP RELEASE / OP START / OP STOP 598 * 599 * Simple operations on a PMC id. 600 */ 601 602 struct pmc_op_simple { 603 pmc_id_t pm_pmcid; 604 }; 605 606 /* 607 * OP WRITELOG 608 * 609 * Flush the current log buffer and write 4 bytes of user data to it. 610 */ 611 612 struct pmc_op_writelog { 613 uint32_t pm_userdata; 614 }; 615 616 /* 617 * OP GETMSR 618 * 619 * Retrieve the machine specific address associated with the allocated 620 * PMC. This number can be used subsequently with a read-performance-counter 621 * instruction. 622 */ 623 624 struct pmc_op_getmsr { 625 uint32_t pm_msr; /* machine specific address */ 626 pmc_id_t pm_pmcid; /* allocated pmc id */ 627 }; 628 629 /* 630 * OP GETDYNEVENTINFO 631 * 632 * Retrieve a PMC dynamic class events list. 633 */ 634 635 struct pmc_dyn_event_descr { 636 char pm_ev_name[PMC_NAME_MAX]; 637 enum pmc_event pm_ev_code; 638 }; 639 640 struct pmc_op_getdyneventinfo { 641 enum pmc_class pm_class; 642 unsigned int pm_nevent; 643 struct pmc_dyn_event_descr pm_events[PMC_EV_DYN_COUNT]; 644 }; 645 646 #ifdef _KERNEL 647 648 #include <sys/malloc.h> 649 #include <sys/sysctl.h> 650 #include <sys/_cpuset.h> 651 652 #include <machine/frame.h> 653 654 #define PMC_HASH_SIZE 1024 655 #define PMC_MTXPOOL_SIZE 2048 656 #define PMC_LOG_BUFFER_SIZE 256 657 #define PMC_NLOGBUFFERS_PCPU 32 658 #define PMC_NSAMPLES 256 659 #define PMC_CALLCHAIN_DEPTH 128 660 #define PMC_THREADLIST_MAX 128 661 662 #define PMC_SYSCTL_NAME_PREFIX "kern." PMC_MODULE_NAME "." 663 664 /* 665 * Locking keys 666 * 667 * (b) - pmc_bufferlist_mtx (spin lock) 668 * (k) - pmc_kthread_mtx (sleep lock) 669 * (o) - po->po_mtx (spin lock) 670 * (g) - global_epoch_preempt (epoch) 671 * (p) - pmc_sx (sx) 672 */ 673 674 /* 675 * PMC commands 676 */ 677 678 struct pmc_syscall_args { 679 register_t pmop_code; /* one of PMC_OP_* */ 680 void *pmop_data; /* syscall parameter */ 681 }; 682 683 /* 684 * Interface to processor specific s1tuff 685 */ 686 687 /* 688 * struct pmc_descr 689 * 690 * Machine independent (i.e., the common parts) of a human readable 691 * PMC description. 692 */ 693 694 struct pmc_descr { 695 char pd_name[PMC_NAME_MAX]; /* name */ 696 uint32_t pd_caps; /* capabilities */ 697 enum pmc_class pd_class; /* class of the PMC */ 698 uint32_t pd_width; /* width in bits */ 699 }; 700 701 /* 702 * struct pmc_target 703 * 704 * This structure records all the target processes associated with a 705 * PMC. 706 */ 707 708 struct pmc_target { 709 LIST_ENTRY(pmc_target) pt_next; 710 struct pmc_process *pt_process; /* target descriptor */ 711 }; 712 713 /* 714 * struct pmc 715 * 716 * Describes each allocated PMC. 717 * 718 * Each PMC has precisely one owner, namely the process that allocated 719 * the PMC. 720 * 721 * A PMC may be attached to multiple target processes. The 722 * 'pm_targets' field links all the target processes being monitored 723 * by this PMC. 724 * 725 * The 'pm_savedvalue' field is protected by a mutex. 726 * 727 * On a multi-cpu machine, multiple target threads associated with a 728 * process-virtual PMC could be concurrently executing on different 729 * CPUs. The 'pm_runcount' field is atomically incremented every time 730 * the PMC gets scheduled on a CPU and atomically decremented when it 731 * get descheduled. Deletion of a PMC is only permitted when this 732 * field is '0'. 733 * 734 */ 735 struct pmc_pcpu_state { 736 uint8_t pps_stalled; 737 uint8_t pps_cpustate; 738 } __aligned(CACHE_LINE_SIZE); 739 struct pmc { 740 LIST_HEAD(,pmc_target) pm_targets; /* list of target processes */ 741 LIST_ENTRY(pmc) pm_next; /* owner's list */ 742 743 /* 744 * System-wide PMCs are allocated on a CPU and are not moved 745 * around. For system-wide PMCs we record the CPU the PMC was 746 * allocated on in the 'CPU' field of the pmc ID. 747 * 748 * Virtual PMCs run on whichever CPU is currently executing 749 * their targets' threads. For these PMCs we need to save 750 * their current PMC counter values when they are taken off 751 * CPU. 752 */ 753 754 union { 755 pmc_value_t pm_savedvalue; /* Virtual PMCS */ 756 } pm_gv; 757 758 /* 759 * For sampling mode PMCs, we keep track of the PMC's "reload 760 * count", which is the counter value to be loaded in when 761 * arming the PMC for the next counting session. For counting 762 * modes on PMCs that are read-only (e.g., the x86 TSC), we 763 * keep track of the initial value at the start of 764 * counting-mode operation. 765 */ 766 767 union { 768 pmc_value_t pm_reloadcount; /* sampling PMC modes */ 769 pmc_value_t pm_initial; /* counting PMC modes */ 770 } pm_sc; 771 772 struct pmc_pcpu_state *pm_pcpu_state; 773 volatile cpuset_t pm_cpustate; /* CPUs where PMC should be active */ 774 uint32_t pm_caps; /* PMC capabilities */ 775 enum pmc_event pm_event; /* event being measured */ 776 uint32_t pm_flags; /* additional flags PMC_F_... */ 777 struct pmc_owner *pm_owner; /* owner thread state */ 778 counter_u64_t pm_runcount; /* #cpus currently on */ 779 enum pmc_state pm_state; /* current PMC state */ 780 uint32_t pm_overflowcnt; /* count overflow interrupts */ 781 782 /* 783 * The PMC ID field encodes the row-index for the PMC, its 784 * mode, class and the CPU# associated with the PMC. 785 */ 786 787 pmc_id_t pm_id; /* allocated PMC id */ 788 enum pmc_class pm_class; 789 790 /* md extensions */ 791 union pmc_md_pmc pm_md; 792 }; 793 794 /* 795 * Accessor macros for 'struct pmc' 796 */ 797 798 #define PMC_TO_MODE(P) PMC_ID_TO_MODE((P)->pm_id) 799 #define PMC_TO_CLASS(P) PMC_ID_TO_CLASS((P)->pm_id) 800 #define PMC_TO_ROWINDEX(P) PMC_ID_TO_ROWINDEX((P)->pm_id) 801 #define PMC_TO_CPU(P) PMC_ID_TO_CPU((P)->pm_id) 802 803 /* 804 * struct pmc_threadpmcstate 805 * 806 * Record per-PMC, per-thread state. 807 */ 808 struct pmc_threadpmcstate { 809 pmc_value_t pt_pmcval; /* per-thread reload count */ 810 }; 811 812 /* 813 * struct pmc_thread 814 * 815 * Record a 'target' thread being profiled. 816 */ 817 struct pmc_thread { 818 LIST_ENTRY(pmc_thread) pt_next; /* linked list */ 819 struct thread *pt_td; /* target thread */ 820 struct pmc_threadpmcstate pt_pmcs[]; /* per-PMC state */ 821 }; 822 823 /* 824 * struct pmc_process 825 * 826 * Record a 'target' process being profiled. 827 * 828 * The target process being profiled could be different from the owner 829 * process which allocated the PMCs. Each target process descriptor 830 * is associated with NHWPMC 'struct pmc *' pointers. Each PMC at a 831 * given hardware row-index 'n' will use slot 'n' of the 'pp_pmcs[]' 832 * array. The size of this structure is thus PMC architecture 833 * dependent. 834 * 835 */ 836 837 struct pmc_targetstate { 838 struct pmc *pp_pmc; /* target PMC */ 839 pmc_value_t pp_pmcval; /* per-process value */ 840 }; 841 842 struct pmc_process { 843 LIST_ENTRY(pmc_process) pp_next; /* hash chain */ 844 LIST_HEAD(,pmc_thread) pp_tds; /* list of threads */ 845 struct mtx *pp_tdslock; /* lock on pp_tds thread list */ 846 int pp_refcnt; /* reference count */ 847 uint32_t pp_flags; /* flags PMC_PP_* */ 848 struct proc *pp_proc; /* target process */ 849 struct pmc_targetstate pp_pmcs[]; /* NHWPMCs */ 850 }; 851 852 #define PMC_PP_ENABLE_MSR_ACCESS 0x00000001 853 854 /* 855 * struct pmc_owner 856 * 857 * We associate a PMC with an 'owner' process. 858 * 859 * A process can be associated with 0..NCPUS*NHWPMC PMCs during its 860 * lifetime, where NCPUS is the numbers of CPUS in the system and 861 * NHWPMC is the number of hardware PMCs per CPU. These are 862 * maintained in the list headed by the 'po_pmcs' to save on space. 863 * 864 */ 865 866 struct pmc_owner { 867 LIST_ENTRY(pmc_owner) po_next; /* hash chain */ 868 CK_LIST_ENTRY(pmc_owner) po_ssnext; /* (g/p) list of SS PMC owners */ 869 LIST_HEAD(, pmc) po_pmcs; /* owned PMC list */ 870 TAILQ_HEAD(, pmclog_buffer) po_logbuffers; /* (o) logbuffer list */ 871 struct mtx po_mtx; /* spin lock for (o) */ 872 struct proc *po_owner; /* owner proc */ 873 uint32_t po_flags; /* (k) flags PMC_PO_* */ 874 struct proc *po_kthread; /* (k) helper kthread */ 875 struct file *po_file; /* file reference */ 876 int po_error; /* recorded error */ 877 short po_sscount; /* # SS PMCs owned */ 878 short po_logprocmaps; /* global mappings done */ 879 struct pmclog_buffer *po_curbuf[MAXCPU]; /* current log buffer */ 880 }; 881 882 #define PMC_PO_OWNS_LOGFILE 0x00000001 /* has a log file */ 883 #define PMC_PO_SHUTDOWN 0x00000010 /* in the process of shutdown */ 884 #define PMC_PO_INITIAL_MAPPINGS_DONE 0x00000020 885 886 /* 887 * struct pmc_hw -- describe the state of the PMC hardware 888 * 889 * When in use, a HW PMC is associated with one allocated 'struct pmc' 890 * pointed to by field 'phw_pmc'. When inactive, this field is NULL. 891 * 892 * On an SMP box, one or more HW PMC's in process virtual mode with 893 * the same 'phw_pmc' could be executing on different CPUs. In order 894 * to handle this case correctly, we need to ensure that only 895 * incremental counts get added to the saved value in the associated 896 * 'struct pmc'. The 'phw_save' field is used to keep the saved PMC 897 * value at the time the hardware is started during this context 898 * switch (i.e., the difference between the new (hardware) count and 899 * the saved count is atomically added to the count field in 'struct 900 * pmc' at context switch time). 901 * 902 */ 903 904 struct pmc_hw { 905 uint32_t phw_state; /* see PHW_* macros below */ 906 struct pmc *phw_pmc; /* current thread PMC */ 907 }; 908 909 #define PMC_PHW_RI_MASK 0x000000FF 910 #define PMC_PHW_CPU_SHIFT 8 911 #define PMC_PHW_CPU_MASK 0x0000FF00 912 #define PMC_PHW_FLAGS_SHIFT 16 913 #define PMC_PHW_FLAGS_MASK 0xFFFF0000 914 915 #define PMC_PHW_INDEX_TO_STATE(ri) ((ri) & PMC_PHW_RI_MASK) 916 #define PMC_PHW_STATE_TO_INDEX(state) ((state) & PMC_PHW_RI_MASK) 917 #define PMC_PHW_CPU_TO_STATE(cpu) (((cpu) << PMC_PHW_CPU_SHIFT) & \ 918 PMC_PHW_CPU_MASK) 919 #define PMC_PHW_STATE_TO_CPU(state) (((state) & PMC_PHW_CPU_MASK) >> \ 920 PMC_PHW_CPU_SHIFT) 921 #define PMC_PHW_FLAGS_TO_STATE(flags) (((flags) << PMC_PHW_FLAGS_SHIFT) & \ 922 PMC_PHW_FLAGS_MASK) 923 #define PMC_PHW_STATE_TO_FLAGS(state) (((state) & PMC_PHW_FLAGS_MASK) >> \ 924 PMC_PHW_FLAGS_SHIFT) 925 #define PMC_PHW_FLAG_IS_ENABLED (PMC_PHW_FLAGS_TO_STATE(0x01)) 926 #define PMC_PHW_FLAG_IS_SHAREABLE (PMC_PHW_FLAGS_TO_STATE(0x02)) 927 928 /* 929 * struct pmc_sample 930 * 931 * Space for N (tunable) PC samples and associated control data. 932 */ 933 934 struct pmc_sample { 935 uint16_t ps_nsamples; /* callchain depth */ 936 uint16_t ps_nsamples_actual; 937 uint16_t ps_cpu; /* cpu number */ 938 uint16_t ps_flags; /* other flags */ 939 lwpid_t ps_tid; /* thread id */ 940 pid_t ps_pid; /* process PID or -1 */ 941 int ps_ticks; /* ticks at sample time */ 942 /* pad */ 943 struct thread *ps_td; /* which thread */ 944 struct pmc *ps_pmc; /* interrupting PMC */ 945 uintptr_t *ps_pc; /* (const) callchain start */ 946 uint64_t ps_tsc; /* tsc value */ 947 }; 948 949 #define PMC_SAMPLE_FREE ((uint16_t) 0) 950 #define PMC_USER_CALLCHAIN_PENDING ((uint16_t) 0xFFFF) 951 952 struct pmc_samplebuffer { 953 volatile uint64_t ps_prodidx; /* producer index */ 954 volatile uint64_t ps_considx; /* consumer index */ 955 uintptr_t *ps_callchains; /* all saved call chains */ 956 struct pmc_sample ps_samples[]; /* array of sample entries */ 957 }; 958 959 #define PMC_CONS_SAMPLE(psb) \ 960 (&(psb)->ps_samples[(psb)->ps_considx & pmc_sample_mask]) 961 962 #define PMC_CONS_SAMPLE_OFF(psb, off) \ 963 (&(psb)->ps_samples[(off) & pmc_sample_mask]) 964 965 #define PMC_PROD_SAMPLE(psb) \ 966 (&(psb)->ps_samples[(psb)->ps_prodidx & pmc_sample_mask]) 967 968 /* 969 * struct pmc_cpustate 970 * 971 * A CPU is modelled as a collection of HW PMCs with space for additional 972 * flags. 973 */ 974 975 struct pmc_cpu { 976 uint32_t pc_state; /* physical cpu number + flags */ 977 struct pmc_samplebuffer *pc_sb[3]; /* space for samples */ 978 struct pmc_hw *pc_hwpmcs[]; /* 'npmc' pointers */ 979 }; 980 981 #define PMC_PCPU_CPU_MASK 0x000000FF 982 #define PMC_PCPU_FLAGS_MASK 0xFFFFFF00 983 #define PMC_PCPU_FLAGS_SHIFT 8 984 #define PMC_PCPU_STATE_TO_CPU(S) ((S) & PMC_PCPU_CPU_MASK) 985 #define PMC_PCPU_STATE_TO_FLAGS(S) (((S) & PMC_PCPU_FLAGS_MASK) >> PMC_PCPU_FLAGS_SHIFT) 986 #define PMC_PCPU_FLAGS_TO_STATE(F) (((F) << PMC_PCPU_FLAGS_SHIFT) & PMC_PCPU_FLAGS_MASK) 987 #define PMC_PCPU_CPU_TO_STATE(C) ((C) & PMC_PCPU_CPU_MASK) 988 #define PMC_PCPU_FLAG_HTT (PMC_PCPU_FLAGS_TO_STATE(0x1)) 989 990 /* 991 * struct pmc_binding 992 * 993 * CPU binding information. 994 */ 995 996 struct pmc_binding { 997 int pb_bound; /* is bound? */ 998 int pb_cpu; /* if so, to which CPU */ 999 }; 1000 1001 1002 struct pmc_mdep; 1003 1004 /* 1005 * struct pmc_classdep 1006 * 1007 * PMC class-dependent operations. 1008 */ 1009 struct pmc_classdep { 1010 uint32_t pcd_caps; /* class capabilities */ 1011 enum pmc_class pcd_class; /* class id */ 1012 int pcd_num; /* number of PMCs */ 1013 int pcd_ri; /* row index of the first PMC in class */ 1014 int pcd_width; /* width of the PMC */ 1015 1016 /* configuring/reading/writing the hardware PMCs */ 1017 int (*pcd_config_pmc)(int _cpu, int _ri, struct pmc *_pm); 1018 int (*pcd_get_config)(int _cpu, int _ri, struct pmc **_ppm); 1019 int (*pcd_read_pmc)(int _cpu, int _ri, pmc_value_t *_value); 1020 int (*pcd_write_pmc)(int _cpu, int _ri, pmc_value_t _value); 1021 1022 /* pmc allocation/release */ 1023 int (*pcd_allocate_pmc)(int _cpu, int _ri, struct pmc *_t, 1024 const struct pmc_op_pmcallocate *_a); 1025 int (*pcd_release_pmc)(int _cpu, int _ri, struct pmc *_pm); 1026 1027 /* starting and stopping PMCs */ 1028 int (*pcd_start_pmc)(int _cpu, int _ri); 1029 int (*pcd_stop_pmc)(int _cpu, int _ri); 1030 1031 /* description */ 1032 int (*pcd_describe)(int _cpu, int _ri, struct pmc_info *_pi, 1033 struct pmc **_ppmc); 1034 1035 /* class-dependent initialization & finalization */ 1036 int (*pcd_pcpu_init)(struct pmc_mdep *_md, int _cpu); 1037 int (*pcd_pcpu_fini)(struct pmc_mdep *_md, int _cpu); 1038 1039 /* machine-specific interface */ 1040 int (*pcd_get_msr)(int _ri, uint32_t *_msr); 1041 }; 1042 1043 /* 1044 * struct pmc_mdep 1045 * 1046 * Machine dependent bits needed per CPU type. 1047 */ 1048 1049 struct pmc_mdep { 1050 uint32_t pmd_cputype; /* from enum pmc_cputype */ 1051 uint32_t pmd_npmc; /* number of PMCs per CPU */ 1052 uint32_t pmd_nclass; /* number of PMC classes present */ 1053 1054 /* 1055 * Machine dependent methods. 1056 */ 1057 1058 /* per-cpu initialization and finalization */ 1059 int (*pmd_pcpu_init)(struct pmc_mdep *_md, int _cpu); 1060 int (*pmd_pcpu_fini)(struct pmc_mdep *_md, int _cpu); 1061 1062 /* thread context switch in/out */ 1063 int (*pmd_switch_in)(struct pmc_cpu *_p, struct pmc_process *_pp); 1064 int (*pmd_switch_out)(struct pmc_cpu *_p, struct pmc_process *_pp); 1065 1066 /* handle a PMC interrupt */ 1067 int (*pmd_intr)(struct trapframe *_tf); 1068 1069 /* 1070 * PMC class dependent information. 1071 */ 1072 struct pmc_classdep pmd_classdep[]; 1073 }; 1074 1075 /* 1076 * Per-CPU state. This is an array of 'mp_ncpu' pointers 1077 * to struct pmc_cpu descriptors. 1078 */ 1079 1080 extern struct pmc_cpu **pmc_pcpu; 1081 1082 /* driver statistics */ 1083 extern struct pmc_driverstats pmc_stats; 1084 1085 #if defined(HWPMC_DEBUG) 1086 #include <sys/ktr.h> 1087 1088 /* debug flags, major flag groups */ 1089 struct pmc_debugflags { 1090 int pdb_CPU; 1091 int pdb_CSW; 1092 int pdb_LOG; 1093 int pdb_MDP; 1094 int pdb_MOD; 1095 int pdb_OWN; 1096 int pdb_PMC; 1097 int pdb_PRC; 1098 int pdb_SAM; 1099 }; 1100 1101 extern struct pmc_debugflags pmc_debugflags; 1102 1103 #define KTR_PMC KTR_SUBSYS 1104 1105 #define PMC_DEBUG_STRSIZE 128 1106 #define PMC_DEBUG_DEFAULT_FLAGS { 0, 0, 0, 0, 0, 0, 0, 0, 0 } 1107 1108 #define PMCDBG0(M, N, L, F) do { \ 1109 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1110 CTR0(KTR_PMC, #M ":" #N ":" #L ": " F); \ 1111 } while (0) 1112 #define PMCDBG1(M, N, L, F, p1) do { \ 1113 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1114 CTR1(KTR_PMC, #M ":" #N ":" #L ": " F, p1); \ 1115 } while (0) 1116 #define PMCDBG2(M, N, L, F, p1, p2) do { \ 1117 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1118 CTR2(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2); \ 1119 } while (0) 1120 #define PMCDBG3(M, N, L, F, p1, p2, p3) do { \ 1121 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1122 CTR3(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3); \ 1123 } while (0) 1124 #define PMCDBG4(M, N, L, F, p1, p2, p3, p4) do { \ 1125 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1126 CTR4(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3, p4);\ 1127 } while (0) 1128 #define PMCDBG5(M, N, L, F, p1, p2, p3, p4, p5) do { \ 1129 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1130 CTR5(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3, p4, \ 1131 p5); \ 1132 } while (0) 1133 #define PMCDBG6(M, N, L, F, p1, p2, p3, p4, p5, p6) do { \ 1134 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1135 CTR6(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3, p4, \ 1136 p5, p6); \ 1137 } while (0) 1138 1139 /* Major numbers */ 1140 #define PMC_DEBUG_MAJ_CPU 0 /* cpu switches */ 1141 #define PMC_DEBUG_MAJ_CSW 1 /* context switches */ 1142 #define PMC_DEBUG_MAJ_LOG 2 /* logging */ 1143 #define PMC_DEBUG_MAJ_MDP 3 /* machine dependent */ 1144 #define PMC_DEBUG_MAJ_MOD 4 /* misc module infrastructure */ 1145 #define PMC_DEBUG_MAJ_OWN 5 /* owner */ 1146 #define PMC_DEBUG_MAJ_PMC 6 /* pmc management */ 1147 #define PMC_DEBUG_MAJ_PRC 7 /* processes */ 1148 #define PMC_DEBUG_MAJ_SAM 8 /* sampling */ 1149 1150 /* Minor numbers */ 1151 1152 /* Common (8 bits) */ 1153 #define PMC_DEBUG_MIN_ALL 0 /* allocation */ 1154 #define PMC_DEBUG_MIN_REL 1 /* release */ 1155 #define PMC_DEBUG_MIN_OPS 2 /* ops: start, stop, ... */ 1156 #define PMC_DEBUG_MIN_INI 3 /* init */ 1157 #define PMC_DEBUG_MIN_FND 4 /* find */ 1158 1159 /* MODULE */ 1160 #define PMC_DEBUG_MIN_PMH 14 /* pmc_hook */ 1161 #define PMC_DEBUG_MIN_PMS 15 /* pmc_syscall */ 1162 1163 /* OWN */ 1164 #define PMC_DEBUG_MIN_ORM 8 /* owner remove */ 1165 #define PMC_DEBUG_MIN_OMR 9 /* owner maybe remove */ 1166 1167 /* PROCESSES */ 1168 #define PMC_DEBUG_MIN_TLK 8 /* link target */ 1169 #define PMC_DEBUG_MIN_TUL 9 /* unlink target */ 1170 #define PMC_DEBUG_MIN_EXT 10 /* process exit */ 1171 #define PMC_DEBUG_MIN_EXC 11 /* process exec */ 1172 #define PMC_DEBUG_MIN_FRK 12 /* process fork */ 1173 #define PMC_DEBUG_MIN_ATT 13 /* attach/detach */ 1174 #define PMC_DEBUG_MIN_SIG 14 /* signalling */ 1175 1176 /* CONTEXT SWITCHES */ 1177 #define PMC_DEBUG_MIN_SWI 8 /* switch in */ 1178 #define PMC_DEBUG_MIN_SWO 9 /* switch out */ 1179 1180 /* PMC */ 1181 #define PMC_DEBUG_MIN_REG 8 /* pmc register */ 1182 #define PMC_DEBUG_MIN_ALR 9 /* allocate row */ 1183 1184 /* MACHINE DEPENDENT LAYER */ 1185 #define PMC_DEBUG_MIN_REA 8 /* read */ 1186 #define PMC_DEBUG_MIN_WRI 9 /* write */ 1187 #define PMC_DEBUG_MIN_CFG 10 /* config */ 1188 #define PMC_DEBUG_MIN_STA 11 /* start */ 1189 #define PMC_DEBUG_MIN_STO 12 /* stop */ 1190 #define PMC_DEBUG_MIN_INT 13 /* interrupts */ 1191 1192 /* CPU */ 1193 #define PMC_DEBUG_MIN_BND 8 /* bind */ 1194 #define PMC_DEBUG_MIN_SEL 9 /* select */ 1195 1196 /* LOG */ 1197 #define PMC_DEBUG_MIN_GTB 8 /* get buf */ 1198 #define PMC_DEBUG_MIN_SIO 9 /* schedule i/o */ 1199 #define PMC_DEBUG_MIN_FLS 10 /* flush */ 1200 #define PMC_DEBUG_MIN_SAM 11 /* sample */ 1201 #define PMC_DEBUG_MIN_CLO 12 /* close */ 1202 1203 #else 1204 #define PMCDBG0(M, N, L, F) /* nothing */ 1205 #define PMCDBG1(M, N, L, F, p1) 1206 #define PMCDBG2(M, N, L, F, p1, p2) 1207 #define PMCDBG3(M, N, L, F, p1, p2, p3) 1208 #define PMCDBG4(M, N, L, F, p1, p2, p3, p4) 1209 #define PMCDBG5(M, N, L, F, p1, p2, p3, p4, p5) 1210 #define PMCDBG6(M, N, L, F, p1, p2, p3, p4, p5, p6) 1211 #endif 1212 1213 /* declare a dedicated memory pool */ 1214 MALLOC_DECLARE(M_PMC); 1215 1216 /* 1217 * Functions 1218 */ 1219 1220 struct pmc_mdep *pmc_md_initialize(void); /* MD init function */ 1221 void pmc_md_finalize(struct pmc_mdep *_md); /* MD fini function */ 1222 int pmc_getrowdisp(int _ri); 1223 int pmc_process_interrupt(int _ring, struct pmc *_pm, struct trapframe *_tf); 1224 int pmc_save_kernel_callchain(uintptr_t *_cc, int _maxsamples, 1225 struct trapframe *_tf); 1226 int pmc_save_user_callchain(uintptr_t *_cc, int _maxsamples, 1227 struct trapframe *_tf); 1228 struct pmc_mdep *pmc_mdep_alloc(int nclasses); 1229 void pmc_mdep_free(struct pmc_mdep *md); 1230 uint64_t pmc_rdtsc(void); 1231 #endif /* _KERNEL */ 1232 #endif /* _SYS_PMC_H_ */ 1233